description: Create a bug report to help us improve
labels:
- bug
+ - bug-report
+ - to-triage
body:
- type: textarea
id: description
---
-blank_issues_enabled: false
+blank_issues_enabled: true
contact_links:
- name: Feature request
url: https://forum.openwrt.org/c/feature-requests
"target/omap":
- "target/linux/omap/**"
- "package/boot/uboot-omap/**"
-"target/oxnas":
- - "target/linux/oxnas/**"
- - "package/boot/uboot-oxnas/**"
"target/pistachio":
- "target/linux/pistachio/**"
"target/qoriq":
cd $(TMP_DIR)/dl && \
rm -rf $(SUBDIR) && \
[ \! -d $(SUBDIR) ] && \
- cvs -d $(URL) export $(VERSION) $(SUBDIR) && \
+ cvs -d $(URL) export $(SOURCE_VERSION) $(SUBDIR) && \
echo "Packing checkout..." && \
$(call dl_tar_pack,$(TMP_DIR)/dl/$(FILE),$(SUBDIR)) && \
mv $(TMP_DIR)/dl/$(FILE) $(DL_DIR)/ && \
rm -rf $(SUBDIR) && \
[ \! -d $(SUBDIR) ] && \
( svn help export | grep -q trust-server-cert && \
- svn export --non-interactive --trust-server-cert -r$(VERSION) $(URL) $(SUBDIR) || \
- svn export --non-interactive -r$(VERSION) $(URL) $(SUBDIR) ) && \
+ svn export --non-interactive --trust-server-cert -r$(SOURCE_VERSION) $(URL) $(SUBDIR) || \
+ svn export --non-interactive -r$(SOURCE_VERSION) $(URL) $(SUBDIR) ) && \
echo "Packing checkout..." && \
- export TAR_TIMESTAMP="`svn info -r$(VERSION) --show-item last-changed-date $(URL)`" && \
+ export TAR_TIMESTAMP="`svn info -r$(SOURCE_VERSION) --show-item last-changed-date $(URL)`" && \
$(call dl_tar_pack,$(TMP_DIR)/dl/$(FILE),$(SUBDIR)) && \
mv $(TMP_DIR)/dl/$(FILE) $(DL_DIR)/ && \
rm -rf $(SUBDIR); \
$(SCRIPT_DIR)/dl_github_archive.py \
--dl-dir="$(DL_DIR)" \
--url="$(URL)" \
- --version="$(VERSION)" \
+ --version="$(SOURCE_VERSION)" \
--subdir="$(SUBDIR)" \
--source="$(FILE)" \
--hash="$(MIRROR_HASH)" \
rm -rf $(SUBDIR) && \
[ \! -d $(SUBDIR) ] && \
git clone $(OPTS) $(URL) $(SUBDIR) && \
- (cd $(SUBDIR) && git checkout $(VERSION)) && \
+ (cd $(SUBDIR) && git checkout $(SOURCE_VERSION)) && \
export TAR_TIMESTAMP=`cd $(SUBDIR) && git log -1 --format='@%ct'` && \
echo "Generating formal git archive (apply .gitattributes rules)" && \
(cd $(SUBDIR) && git config core.abbrev 8 && \
cd $(TMP_DIR)/dl && \
rm -rf $(SUBDIR) && \
[ \! -d $(SUBDIR) ] && \
- bzr export --per-file-timestamps -r$(VERSION) $(SUBDIR) $(URL) && \
+ bzr export --per-file-timestamps -r$(SOURCE_VERSION) $(SUBDIR) $(URL) && \
echo "Packing checkout..." && \
export TAR_TIMESTAMP="" && \
$(call dl_tar_pack,$(TMP_DIR)/dl/$(FILE),$(SUBDIR)) && \
cd $(TMP_DIR)/dl && \
rm -rf $(SUBDIR) && \
[ \! -d $(SUBDIR) ] && \
- hg clone -r $(VERSION) $(URL) $(SUBDIR) && \
+ hg clone -r $(SOURCE_VERSION) $(URL) $(SUBDIR) && \
export TAR_TIMESTAMP=`cd $(SUBDIR) && hg log --template '@{date}' -l 1` && \
find $(SUBDIR) -name .hg | xargs rm -rf && \
echo "Packing checkout..." && \
cd $(TMP_DIR)/dl && \
rm -rf $(SUBDIR) && \
[ \! -d $(SUBDIR) ] && \
- darcs get -t $(VERSION) $(URL) $(SUBDIR) && \
+ darcs get -t $(SOURCE_VERSION) $(URL) $(SUBDIR) && \
export TAR_TIMESTAMP=`cd $(SUBDIR) && LC_ALL=C darcs log --last 1 | sed -ne 's!^Date: \+!!p'` && \
find $(SUBDIR) -name _darcs | xargs rm -rf && \
echo "Packing checkout..." && \
)
endef
-Validate/cvs=VERSION SUBDIR
-Validate/svn=VERSION SUBDIR
-Validate/git=VERSION SUBDIR
-Validate/bzr=VERSION SUBDIR
-Validate/hg=VERSION SUBDIR
-Validate/darcs=VERSION SUBDIR
+Validate/cvs=SOURCE_VERSION SUBDIR
+Validate/svn=SOURCE_VERSION SUBDIR
+Validate/git=SOURCE_VERSION SUBDIR
+Validate/bzr=SOURCE_VERSION SUBDIR
+Validate/hg=SOURCE_VERSION SUBDIR
+Validate/darcs=SOURCE_VERSION SUBDIR
define Download/Defaults
URL:=
MIRROR:=1
MIRROR_HASH=$$(MIRROR_MD5SUM)
MIRROR_MD5SUM:=x
- VERSION:=
+ SOURCE_VERSION:=
OPTS:=
SUBMODULES:=
endef
$(if $(PKG_SOURCE_MIRROR),MIRROR:=$(filter 1,$(PKG_MIRROR)))
$(if $(PKG_MIRROR_MD5SUM),MIRROR_MD5SUM:=$(PKG_MIRROR_MD5SUM))
$(if $(PKG_MIRROR_HASH),MIRROR_HASH:=$(PKG_MIRROR_HASH))
- VERSION:=$(PKG_SOURCE_VERSION)
+ SOURCE_VERSION:=$(PKG_SOURCE_VERSION)
$(if $(PKG_MD5SUM),MD5SUM:=$(PKG_MD5SUM))
$(if $(PKG_HASH),HASH:=$(PKG_HASH))
endef
HOST_STAMP_BUILT:=$(HOST_BUILD_DIR)/.built
HOST_BUILD_PREFIX?=$(if $(IS_PACKAGE_BUILD),$(STAGING_DIR_HOSTPKG),$(STAGING_DIR_HOST))
HOST_STAMP_INSTALLED:=$(HOST_BUILD_PREFIX)/stamp/.$(PKG_NAME)_installed
-HOST_STAMP_PROGRAMS:=$(foreach program,$(PKG_PROGRAMS),$(subst $(PKG_NAME),$(program),$(HOST_STAMP_INSTALLED)) )
+HOST_STAMP_PROGRAMS:=$(foreach program,$(PKG_PROGRAMS),$(dir $(HOST_STAMP_INSTALLED))$(subst $(PKG_NAME),$(program),$(notdir $(HOST_STAMP_INSTALLED))) )
override MAKEFLAGS=
-LINUX_VERSION-6.6 = .27
-LINUX_KERNEL_HASH-6.6.27 = 639e50060e3c8f23ed017cb10cfeacc6ba88ff5583812bb76859b4cc6a128291
+LINUX_VERSION-6.6 = .29
+LINUX_KERNEL_HASH-6.6.29 = 7f26f74c08082c86b1daf866e4d49c5d8276cc1906a89d0e367e457ec167cbd0
printf "%0${retlen}x" "$ret"
}
+data_2bin() {
+ local data=$1
+ local len=${#1}
+ local bin_data
+
+ for i in $(seq 0 2 $(($len - 1))); do
+ bin_data="${bin_data}\x${data:i:2}"
+ done
+
+ echo -ne $bin_data
+}
+
+data_2xor_val() {
+ local data=$1
+ local len=${#1}
+ local xor_data
+
+ for i in $(seq 0 4 $(($len - 1))); do
+ xor_data="${xor_data}${data:i:4} "
+ done
+
+ echo -n ${xor_data:0:-1}
+}
+
append() {
local var="$1"
local value="$2"
local caldata
mtd=$(find_mtd_chardev "$part")
- reversed=$(hexdump -v -s $offset -n $count -e '/1 "%02x "' $mtd)
+ reversed=$(hexdump -v -s $offset -n $count -e '1/1 "%02x "' $mtd)
for byte in $reversed; do
caldata="\x${byte}${caldata}"
return $?
}
-caldata_patch_chksum() {
- local mac=$1
- local mac_offset=$(($2))
+caldata_patch_data() {
+ local data=$1
+ local data_count=$((${#1} / 2))
+ local data_offset=$(($2))
local chksum_offset=$(($3))
local target=$4
- local xor_mac
- local xor_fw_mac
- local xor_fw_chksum
+ local fw_data
+ local fw_chksum
- xor_mac=${mac//:/}
- xor_mac="${xor_mac:0:4} ${xor_mac:4:4} ${xor_mac:8:4}"
+ [ -z "$data" -o -z "$data_offset" ] && return
- xor_fw_mac=$(hexdump -v -n 6 -s $mac_offset -e '/1 "%02x"' /lib/firmware/$FIRMWARE)
- xor_fw_mac="${xor_fw_mac:0:4} ${xor_fw_mac:4:4} ${xor_fw_mac:8:4}"
+ [ -n "$target" ] || target=/lib/firmware/$FIRMWARE
- xor_fw_chksum=$(hexdump -v -n 2 -s $chksum_offset -e '/1 "%02x"' /lib/firmware/$FIRMWARE)
- xor_fw_chksum=$(xor $xor_fw_chksum $xor_fw_mac $xor_mac)
+ fw_data=$(hexdump -v -n $data_count -s $data_offset -e '1/1 "%02x"' $target)
- printf "%b" "\x${xor_fw_chksum:0:2}\x${xor_fw_chksum:2:2}" | \
- dd of=$target conv=notrunc bs=1 seek=$chksum_offset count=2
-}
+ if [ "$data" != "$fw_data" ]; then
-caldata_patch_mac() {
- local mac=$1
- local mac_offset=$(($2))
- local chksum_offset=$3
- local target=$4
-
- [ -z "$mac" -o -z "$mac_offset" ] && return
+ if [ -n "$chksum_offset" ]; then
+ fw_chksum=$(hexdump -v -n 2 -s $chksum_offset -e '1/1 "%02x"' $target)
+ fw_chksum=$(xor $fw_chksum $(data_2xor_val $fw_data) $(data_2xor_val $data))
- [ -n "$target" ] || target=/lib/firmware/$FIRMWARE
+ data_2bin $fw_chksum | \
+ dd of=$target conv=notrunc bs=1 seek=$chksum_offset count=2 || \
+ caldata_die "failed to write chksum to eeprom file"
+ fi
- [ -n "$chksum_offset" ] && caldata_patch_chksum "$mac" "$mac_offset" "$chksum_offset" "$target"
-
- macaddr_2bin $mac | dd of=$target conv=notrunc oflag=seek_bytes bs=6 seek=$mac_offset count=1 || \
- caldata_die "failed to write MAC address to eeprom file"
+ data_2bin $data | \
+ dd of=$target conv=notrunc bs=1 seek=$data_offset count=$data_count || \
+ caldata_die "failed to write data to eeprom file"
+ fi
}
ath9k_patch_mac() {
local mac=$1
local target=$2
- caldata_patch_mac "$mac" 0x2 "" "$target"
+ caldata_patch_data "${mac//:/}" 0x2 "" "$target"
}
ath9k_patch_mac_crc() {
local chksum_offset=$((mac_offset - 10))
local target=$4
- caldata_patch_mac "$mac" "$mac_offset" "$chksum_offset" "$target"
+ caldata_patch_data "${mac//:/}" "$mac_offset" "$chksum_offset" "$target"
}
ath10k_patch_mac() {
local mac=$1
local target=$2
- caldata_patch_mac "$mac" 0x6 0x2 "$target"
+ caldata_patch_data "${mac//:/}" 0x6 0x2 "$target"
+}
+
+ath11k_patch_mac() {
+ local mac=$1
+ # mac_id from 0 to 5
+ local mac_id=$2
+ local target=$3
+
+ [ -z "$mac_id" ] && return
+
+ caldata_patch_data "${mac//:/}" $(printf "0x%x" $(($mac_id * 0x6 + 0xe))) 0xa "$target"
+}
+
+ath10k_remove_regdomain() {
+ local target=$1
+
+ caldata_patch_data "0000" 0xc 0x2 "$target"
+}
+
+ath11k_remove_regdomain() {
+ local target=$1
+ local regdomain
+ local regdomain_data
+
+ regdomain=$(hexdump -v -n 2 -s 0x34 -e '1/1 "%02x"' $target)
+ caldata_patch_data "0000" 0x34 0xa "$target"
+
+ for offset in 0x450 0x458 0x500 0x5a8; do
+ regdomain_data=$(hexdump -v -n 2 -s $offset -e '1/1 "%02x"' $target)
+
+ if [ "$regdomain" == "$regdomain_data" ]; then
+ caldata_patch_data "0000" $offset 0xa "$target"
+ fi
+ done
+}
+
+ath11k_set_macflag() {
+ local target=$1
+
+ caldata_patch_data "0100" 0x3e 0xa "$target"
}
echo "$(macaddr_unsetbit_mc "$(macaddr_setbit_la "${randsrc}")")"
}
-macaddr_2bin() {
- local mac=$1
-
- echo -ne \\x${mac//:/\\x}
-}
-
macaddr_canonicalize() {
local mac="$1"
local canon=""
include $(TOPDIR)/rules.mk
PKG_VERSION:=2.9
-PKG_RELEASE:=1
+PKG_RELEASE:=2
PKG_HASH:=76a66a1de0c01aeb83dfc7b72b51173fe62c6e51d6fca17cc562393117bed08b
PKG_MAINTAINER:=Vladimir Vid <vladimir.vid@sartura.hr>
FILE:=$(A3700_UTILS_SOURCE)
PROTO:=git
URL:=https://github.com/MarvellEmbeddedProcessors/A3700-utils-marvell.git
- VERSION:=a3e1c67bb378e1d8a938e1b826cb602af83628d2
+ SOURCE_VERSION:=a3e1c67bb378e1d8a938e1b826cb602af83628d2
MIRROR_HASH:=0e6b8ef6423dcb52a5e282669a8aeebc6eea2d45a7c3a2c9a2fc7a749b3275a7
SUBDIR:=$(A3700_UTILS_NAME)
endef
FILE:=$(CRYPTOPP_SOURCE)
PROTO:=git
URL:=https://github.com/weidai11/cryptopp.git
- VERSION:=4d0cad5401d1a2c998b314bc89288c9620d3021d
- MIRROR_HASH:=74ec9e48ee04b9f2d9a1d8c4f2392ed0ab52780d7af0f70405d7bbb23d1504fa
+ SOURCE_VERSION:=4d0cad5401d1a2c998b314bc89288c9620d3021d
+ MIRROR_HASH:=6c53c8b4dfa07df0c5915a90c20f70c64d150b652cf5ac52e2eae08c5a9cc7cd
SUBDIR:=$(CRYPTOPP_NAME)
endef
FILE:=$(MV_DDR_SOURCE)
PROTO:=git
URL:=https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git
- VERSION:=541616bc5d25a0167c9901546255c55973e2c0f0
+ SOURCE_VERSION:=541616bc5d25a0167c9901546255c55973e2c0f0
MIRROR_HASH:=9e86a986c7400ed1a72165a88150b6c494ebd87303b16314b43e5785e3f13068
SUBDIR:=$(MV_DDR_NAME)
endef
PROTO:=git
SUBMODULES:=skip
URL:=https://gitlab.nic.cz/turris/mox-boot-builder.git
- VERSION:=604f8f51d97b4e59fa6d1e579101daa194d6ed2d
+ SOURCE_VERSION:=604f8f51d97b4e59fa6d1e579101daa194d6ed2d
MIRROR_HASH:=b09337a7dde140f57e40133b6e7b7e1eb338e7cea9b15a3af6874824462f15f7
SUBDIR:=$(MOX_BB_NAME)
endef
include $(INCLUDE_DIR)/kernel.mk
PKG_NAME:=grub
-PKG_VERSION:=2.06
-PKG_RELEASE:=6
+PKG_VERSION:=2.12
+PKG_RELEASE:=1
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
PKG_SOURCE_URL:=@GNU/grub
-PKG_HASH:=b79ea44af91b93d17cd3fe80bdae6ed43770678a9a5ae192ccea803ebb657ee1
+PKG_HASH:=f3c97391f7c4eaa677a78e090c7e97e6dc47b16f655f04683ebd37bef7fe0faa
PKG_LICENSE:=GPL-3.0-or-later
PKG_CPE_ID:=cpe:/a:gnu:grub2
--- /dev/null
+From 4d4dae6a52b1749642261a15f5dcc1e3d4150b36 Mon Sep 17 00:00:00 2001
+From: Julien Olivain <ju.o@free.fr>
+Date: Fri, 22 Dec 2023 19:02:53 +0100
+Subject: [PATCH] Add missing grub-core/extra_deps.lst file in release tarball
+
+A file is missing in the grub-2.12 release tarballs (both .gz and .xz).
+See [1]. The issue was reported in [2] and fixed upstream in [3].
+
+This patch adds the missing file, on top of the release tarball. This
+patch won't apply on upstream git, since the file is present in the
+source repository. Since the issue is fixed upstream in [3], it is
+expected upcoming releases tarballs will include the file.
+
+The file content was fetched from the upstream git repo:
+https://git.savannah.gnu.org/gitweb/?p=grub.git;a=blob_plain;f=grub-core/extra_deps.lst;hb=refs/tags/grub-2.12
+
+[1] https://ftp.gnu.org/gnu/grub/grub-2.12.tar.xz
+[2] https://lists.gnu.org/archive/html/grub-devel/2023-12/msg00054.html
+[3] https://git.savannah.gnu.org/gitweb/?p=grub.git;a=commit;h=b835601c7639ed1890f2d3db91900a8506011a8e
+
+Signed-off-by: Julien Olivain <ju.o@free.fr>
+Upstream: Fixed by: https://git.savannah.gnu.org/gitweb/?p=grub.git;a=commit;h=b835601c7639ed1890f2d3db91900a8506011a8e
+---
+ grub-core/extra_deps.lst | 1 +
+ 1 file changed, 1 insertion(+)
+ create mode 100644 grub-core/extra_deps.lst
+
+--- /dev/null
++++ b/grub-core/extra_deps.lst
+@@ -0,0 +1 @@
++depends bli part_gpt
--- a/include/grub/util/install.h
+++ b/include/grub/util/install.h
-@@ -198,13 +198,13 @@ grub_install_get_image_target (const cha
+@@ -199,13 +199,13 @@ grub_install_get_image_target (const cha
void
grub_util_bios_setup (const char *dir,
const char *boot_file, const char *core_file,
--- a/util/grub-install.c
+++ b/util/grub-install.c
-@@ -1721,7 +1721,7 @@ main (int argc, char *argv[])
+@@ -1770,7 +1770,7 @@ main (int argc, char *argv[])
if (install_bootsector)
{
grub_util_bios_setup (platdir, "boot.img", "core.img",
fs_probe, allow_floppy, add_rs_codes,
!grub_install_is_short_mbrgap_supported ());
-@@ -1752,7 +1752,7 @@ main (int argc, char *argv[])
+@@ -1801,7 +1801,7 @@ main (int argc, char *argv[])
if (install_bootsector)
{
grub_util_sparc_setup (platdir, "boot.img", "core.img",
;;
bananapi,bpi-r3|\
bananapi,bpi-r3-mini|\
-bananapi,bpi-r4)
+bananapi,bpi-r4|\
+jdcloud,re-cp-03)
. /lib/upgrade/common.sh
bootdev="$(fitblk_get_bootdev)"
glinet,gl-mt3000)
ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x80000" "0x20000"
;;
-jdcloud,re-cp-03)
- local envdev=$(find_mmc_part "ubootenv" "mmcblk0")
- ubootenv_add_uci_config "$envdev" "0x0" "0x40000" "0x40000" "1"
- ubootenv_add_uci_config "$envdev" "0x40000" "0x40000" "0x40000" "1"
- ;;
mercusys,mr90x-v1|\
routerich,ax3000)
local envdev=/dev/mtd$(find_mtd_index "u-boot-env")
[ -n "$idx" ] && \
ubootenv_add_uci_config "/dev/mtd$idx" "0x0" "0x20000" "0x20000" "1"
;;
+spectrum,sax1v1k)
+ mmcpart="$(find_mmc_part 0:APPSBLENV)"
+ [ -n "$mmcpart" ] && \
+ ubootenv_add_uci_config "$mmcpart" "0x0" "0x40000" "0x40000" "1"
+ ;;
esac
config_load ubootenv
linksys,ea7500-v2|\
linksys,ea8100-v1|\
linksys,ea8100-v2|\
-mts,wg430223)
+mts,wg430223|\
+ubnt,edgerouter-x|\
+ubnt,edgerouter-x-sfp)
ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x1000" "0x20000"
;;
snr,snr-cpe-me1|\
+serverip=192.168.1.254
+loadaddr=0x46000000
+console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0
-+bootargs=root=/dev/mmcblk0p65
++bootargs=root=/dev/fit0 rootwait
+bootcmd=if pstore check ; then run boot_recovery ; else run boot_emmc ; fi
+bootconf=config-1
+bootdelay=0
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
-PKG_VERSION:=2023.07.02
+PKG_VERSION:=2024.04
PKG_RELEASE:=1
-PKG_HASH:=6b6a48581c14abb0f95bd87c1af4d740922406d7b801002a9f94727fdde021d5
+PKG_HASH:=18a853fe39fad7ad03a90cc2d4275aeaed6da69735defac3492b80508843dd4a
include $(INCLUDE_DIR)/u-boot.mk
include $(INCLUDE_DIR)/package.mk
+++ /dev/null
-From 8621f6d22a9589651c6f25742294dd19a26db430 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robert.marko@sartura.hr>
-Date: Thu, 3 Aug 2023 13:34:13 +0200
-Subject: [PATCH 1/3] arm: mvebu: Espressobin: move FDT fixup into a separate
- function
-
-Currently, Esspresobin FDT is being fixed up directly in ft_board_setup()
-which makes it hard to add support for any other board to be fixed up.
-
-So, lets just move the FDT fixup code to a separate function and call it
-if compatible matches, there should be no functional change.
-
-Signed-off-by: Robert Marko <robert.marko@sartura.hr>
----
- board/Marvell/mvebu_armada-37xx/board.c | 14 +++++++++-----
- 1 file changed, 9 insertions(+), 5 deletions(-)
-
---- a/board/Marvell/mvebu_armada-37xx/board.c
-+++ b/board/Marvell/mvebu_armada-37xx/board.c
-@@ -359,18 +359,14 @@ int last_stage_init(void)
- #endif
-
- #ifdef CONFIG_OF_BOARD_SETUP
--int ft_board_setup(void *blob, struct bd_info *bd)
-+static int espressobin_fdt_setup(void *blob)
- {
--#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
- int ret;
- int spi_off;
- int parts_off;
- int part_off;
-
- /* Fill SPI MTD partitions for Linux kernel on Espressobin */
-- if (!of_machine_is_compatible("globalscale,espressobin"))
-- return 0;
--
- spi_off = fdt_node_offset_by_compatible(blob, -1, "jedec,spi-nor");
- if (spi_off < 0)
- return 0;
-@@ -455,6 +451,14 @@ int ft_board_setup(void *blob, struct bd
- return 0;
- }
-
-+ return 0;
-+}
-+
-+int ft_board_setup(void *blob, struct bd_info *bd)
-+{
-+#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
-+ if (of_machine_is_compatible("globalscale,espressobin"))
-+ return espressobin_fdt_setup(blob);
- #endif
- return 0;
- }
--- /dev/null
+From ca4ecdce4cdcfab7df101b5df6ddad43d2f549e1 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <kabel@kernel.org>
+Date: Thu, 4 Apr 2024 09:50:50 +0200
+Subject: [PATCH] arm: mvebu: turris_omnia: Enable LTO by default on Turris
+ Omnia
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+U-Boot builds for Turris Omnia are approaching the limit of 0xf0000
+bytes, which is the size of the U-Boot partition on Omnia.
+
+Enable LTO to get more size optimized binaries.
+
+Signed-off-by: Marek Behún <kabel@kernel.org>
+Reviewed-by: Stefan Roese <sr@denx.de>
+---
+ configs/turris_omnia_defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/configs/turris_omnia_defconfig
++++ b/configs/turris_omnia_defconfig
+@@ -31,6 +31,7 @@ CONFIG_AHCI=y
+ CONFIG_OF_BOARD_FIXUP=y
+ CONFIG_SYS_MEMTEST_START=0x00800000
+ CONFIG_SYS_MEMTEST_END=0x00ffffff
++CONFIG_LTO=y
+ CONFIG_HAS_BOARD_SIZE_LIMIT=y
+ CONFIG_BOARD_SIZE_LIMIT=983040
+ CONFIG_FIT=y
+++ /dev/null
-From 3f8c18894a50fd45b81a807f217893f289500bc6 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robert.marko@sartura.hr>
-Date: Thu, 3 Aug 2023 14:24:31 +0200
-Subject: [PATCH 2/3] arm: mvebu: Espressobin: move network setup into a
- separate function
-
-Currently, Esspresobin switch is being setup directly in last_stage_init()
-which makes it hard to add support for any other board to be setup.
-
-So, lets just move the switch setup code to a separate function and call it
-if compatible matches, there should be no functional change.
-
-Signed-off-by: Robert Marko <robert.marko@sartura.hr>
----
- board/Marvell/mvebu_armada-37xx/board.c | 16 +++++++++++-----
- 1 file changed, 11 insertions(+), 5 deletions(-)
-
---- a/board/Marvell/mvebu_armada-37xx/board.c
-+++ b/board/Marvell/mvebu_armada-37xx/board.c
-@@ -300,15 +300,11 @@ static int mii_multi_chip_mode_write(str
- return 0;
- }
-
--/* Bring-up board-specific network stuff */
--int last_stage_init(void)
-+static int espressobin_last_stage_init(void)
- {
- struct udevice *bus;
- ofnode node;
-
-- if (!of_machine_is_compatible("globalscale,espressobin"))
-- return 0;
--
- node = ofnode_by_compatible(ofnode_null(), "marvell,orion-mdio");
- if (!ofnode_valid(node) ||
- uclass_get_device_by_ofnode(UCLASS_MDIO, node, &bus) ||
-@@ -356,6 +352,16 @@ int last_stage_init(void)
-
- return 0;
- }
-+
-+/* Bring-up board-specific network stuff */
-+int last_stage_init(void)
-+{
-+
-+ if (of_machine_is_compatible("globalscale,espressobin"))
-+ return espressobin_last_stage_init();
-+
-+ return 0;
-+}
- #endif
-
- #ifdef CONFIG_OF_BOARD_SETUP
+++ /dev/null
-From 83c00ee665b8dde813458b2b07cf97ce8409248d Mon Sep 17 00:00:00 2001
-From: Robert Marko <robert.marko@sartura.hr>
-Date: Fri, 4 Aug 2023 22:39:06 +0200
-Subject: [PATCH 3/3] arm: mvebu: eDPU: support new board revision
-
-There is a new eDPU revision that uses Marvell 88E6361 switch onboard.
-We can rely on detecting the switch to enable and fixup the Linux DTS
-so a single DTS can be used.
-
-There is currently no support for the 88E6361 switch and thus no working
-networking in U-Boot, so we disable both ports.
-
-Signed-off-by: Robert Marko <robert.marko@sartura.hr>
----
- arch/arm/dts/armada-3720-eDPU-u-boot.dtsi | 13 ++-
- arch/arm/dts/armada-3720-eDPU.dts | 47 ++++++++
- board/Marvell/mvebu_armada-37xx/board.c | 125 ++++++++++++++++++++++
- configs/eDPU_defconfig | 2 +
- 4 files changed, 182 insertions(+), 5 deletions(-)
-
---- a/arch/arm/dts/armada-3720-eDPU-u-boot.dtsi
-+++ b/arch/arm/dts/armada-3720-eDPU-u-boot.dtsi
-@@ -32,14 +32,17 @@
- bootph-all;
- };
-
--ð0 {
-- /* G.hn does not work without additional configuration */
-- status = "disabled";
--};
--
- ð1 {
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-+
-+/*
-+ * eDPU v2 has a MV88E6361 switch on the MDIO bus and U-boot is used
-+ * to patch the Linux DTS if its found so enable MDIO by default.
-+ */
-+&mdio {
-+ status = "okay";
-+};
---- a/arch/arm/dts/armada-3720-eDPU.dts
-+++ b/arch/arm/dts/armada-3720-eDPU.dts
-@@ -12,3 +12,50 @@
- ð0 {
- phy-mode = "2500base-x";
- };
-+
-+/*
-+ * External MV88E6361 switch is only available on v2 of the board.
-+ * U-Boot will enable the MDIO bus and switch nodes.
-+ */
-+&mdio {
-+ status = "disabled";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&smi_pins>;
-+
-+ /* Actual device is MV88E6361 */
-+ switch: switch@0 {
-+ compatible = "marvell,mv88e6190";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0>;
-+ status = "disabled";
-+
-+ ports {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ port@0 {
-+ reg = <0>;
-+ label = "cpu";
-+ phy-mode = "2500base-x";
-+ managed = "in-band-status";
-+ ethernet = <ð0>;
-+ };
-+
-+ port@9 {
-+ reg = <9>;
-+ label = "downlink";
-+ phy-mode = "2500base-x";
-+ managed = "in-band-status";
-+ };
-+
-+ port@a {
-+ reg = <10>;
-+ label = "uplink";
-+ phy-mode = "2500base-x";
-+ managed = "in-band-status";
-+ sfp = <&sfp_eth1>;
-+ };
-+ };
-+ };
-+};
---- a/board/Marvell/mvebu_armada-37xx/board.c
-+++ b/board/Marvell/mvebu_armada-37xx/board.c
-@@ -13,6 +13,7 @@
- #include <mmc.h>
- #include <miiphy.h>
- #include <phy.h>
-+#include <fdt_support.h>
- #include <asm/global_data.h>
- #include <asm/io.h>
- #include <asm/arch/cpu.h>
-@@ -49,6 +50,7 @@ DECLARE_GLOBAL_DATA_PTR;
- /* Single-chip mode */
- /* Switch Port Registers */
- #define MVEBU_SW_LINK_CTRL_REG (1)
-+#define MVEBU_SW_PORT_SWITCH_ID (3)
- #define MVEBU_SW_PORT_CTRL_REG (4)
- #define MVEBU_SW_PORT_BASE_VLAN (6)
-
-@@ -56,6 +58,8 @@ DECLARE_GLOBAL_DATA_PTR;
- #define MVEBU_G2_SMI_PHY_CMD_REG (24)
- #define MVEBU_G2_SMI_PHY_DATA_REG (25)
-
-+#define SWITCH_88E6361_PRODUCT_NUMBER 0x2610
-+
- /*
- * Memory Controller Registers
- *
-@@ -72,6 +76,27 @@ DECLARE_GLOBAL_DATA_PTR;
- #define A3700_MC_CTRL2_SDRAM_TYPE_DDR3 2
- #define A3700_MC_CTRL2_SDRAM_TYPE_DDR4 3
-
-+static bool is_edpu_plus(void)
-+{
-+ struct udevice *bus;
-+ ofnode node;
-+ int val;
-+
-+ node = ofnode_by_compatible(ofnode_null(), "marvell,orion-mdio");
-+ if (!ofnode_valid(node) ||
-+ uclass_get_device_by_ofnode(UCLASS_MDIO, node, &bus) ||
-+ device_probe(bus)) {
-+ printf("Cannot find MDIO bus\n");
-+ return -ENODEV;
-+ }
-+
-+ val = dm_mdio_read(bus, 0x0, MDIO_DEVAD_NONE, MVEBU_SW_PORT_SWITCH_ID);
-+ if (val == SWITCH_88E6361_PRODUCT_NUMBER)
-+ return true;
-+ else
-+ return false;
-+}
-+
- int board_early_init_f(void)
- {
- return 0;
-@@ -353,6 +378,41 @@ static int espressobin_last_stage_init(v
- return 0;
- }
-
-+static int edpu_plus_last_stage_init(void)
-+{
-+ struct udevice *dev;
-+ int ret;
-+
-+ if (is_edpu_plus()) {
-+ ret = uclass_get_device_by_name(UCLASS_ETH,
-+ "ethernet@40000",
-+ &dev);
-+ if (!ret) {
-+ device_remove(dev, DM_REMOVE_NORMAL);
-+ device_unbind(dev);
-+ }
-+
-+ /* Currently no networking support on the eDPU+ board */
-+ ret = uclass_get_device_by_name(UCLASS_ETH,
-+ "ethernet@30000",
-+ &dev);
-+ if (!ret) {
-+ device_remove(dev, DM_REMOVE_NORMAL);
-+ device_unbind(dev);
-+ }
-+ } else {
-+ ret = uclass_get_device_by_name(UCLASS_ETH,
-+ "ethernet@30000",
-+ &dev);
-+ if (!ret) {
-+ device_remove(dev, DM_REMOVE_NORMAL);
-+ device_unbind(dev);
-+ }
-+ }
-+
-+ return 0;
-+}
-+
- /* Bring-up board-specific network stuff */
- int last_stage_init(void)
- {
-@@ -360,6 +420,9 @@ int last_stage_init(void)
- if (of_machine_is_compatible("globalscale,espressobin"))
- return espressobin_last_stage_init();
-
-+ if (of_machine_is_compatible("methode,edpu"))
-+ return edpu_plus_last_stage_init();
-+
- return 0;
- }
- #endif
-@@ -460,12 +523,74 @@ static int espressobin_fdt_setup(void *b
- return 0;
- }
-
-+static int edpu_plus_fdt_setup(void *blob)
-+{
-+ const char *ports[] = { "downlink", "uplink" };
-+ uint8_t mac[ETH_ALEN];
-+ const char *path;
-+ int i, ret;
-+
-+ if (is_edpu_plus()) {
-+ ret = fdt_set_status_by_compatible(blob,
-+ "marvell,orion-mdio",
-+ FDT_STATUS_OKAY);
-+ if (ret)
-+ printf("Failed to enable MDIO!\n");
-+
-+ ret = fdt_set_status_by_alias(blob,
-+ "ethernet1",
-+ FDT_STATUS_DISABLED);
-+ if (ret)
-+ printf("Failed to disable ethernet1!\n");
-+
-+ path = fdt_get_alias(blob, "ethernet0");
-+ if (path)
-+ do_fixup_by_path_string(blob, path, "phy-mode", "2500base-x");
-+ else
-+ printf("Failed to update ethernet0 phy-mode to 2500base-x!\n");
-+
-+ ret = fdt_set_status_by_compatible(blob,
-+ "marvell,mv88e6190",
-+ FDT_STATUS_OKAY);
-+ if (ret)
-+ printf("Failed to enable MV88E6361!\n");
-+
-+ /*
-+ * MAC-s for Uplink and Downlink ports are stored under
-+ * non standard variable names, so lets manually fixup the
-+ * switch port nodes to have the desired MAC-s.
-+ */
-+ for (i = 0; i < 2; i++) {
-+ if (eth_env_get_enetaddr(ports[i], mac)) {
-+ do_fixup_by_prop(blob,
-+ "label",
-+ ports[i],
-+ strlen(ports[i]) + 1,
-+ "mac-address",
-+ mac, ARP_HLEN, 1);
-+
-+ do_fixup_by_prop(blob,
-+ "label",
-+ ports[i],
-+ strlen(ports[i]) + 1,
-+ "local-mac-address",
-+ mac, ARP_HLEN, 1);
-+ }
-+ }
-+ }
-+
-+ return 0;
-+}
-+
- int ft_board_setup(void *blob, struct bd_info *bd)
- {
- #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
- if (of_machine_is_compatible("globalscale,espressobin"))
- return espressobin_fdt_setup(blob);
- #endif
-+ if (of_machine_is_compatible("methode,edpu"))
-+ return edpu_plus_fdt_setup(blob);
-+
- return 0;
- }
- #endif
---- a/configs/eDPU_defconfig
-+++ b/configs/eDPU_defconfig
-@@ -17,12 +17,14 @@ CONFIG_DEBUG_UART=y
- # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
- CONFIG_FIT=y
- CONFIG_FIT_VERBOSE=y
-+CONFIG_OF_BOARD_SETUP=y
- CONFIG_DISTRO_DEFAULTS=y
- CONFIG_USE_PREBOOT=y
- # CONFIG_DISPLAY_CPUINFO is not set
- # CONFIG_DISPLAY_BOARDINFO is not set
- CONFIG_DISPLAY_BOARDINFO_LATE=y
- CONFIG_BOARD_EARLY_INIT_F=y
-+CONFIG_LAST_STAGE_INIT=y
- CONFIG_SYS_MAXARGS=32
- CONFIG_SYS_PBSIZE=1048
- # CONFIG_CMD_ELF is not set
+++ /dev/null
-From 1dbc6d3739869af38e6157cd8b9bc4314ca3c9fe Mon Sep 17 00:00:00 2001
-From: Josua Mayer <josua@solid-run.com>
-Date: Mon, 18 Jul 2022 20:04:54 +0300
-Subject: [PATCH 1/2] arm: mvebu: clearfog: read number of ddr channels from
- tlv data
-
-Extend the existing tlv vendor extension used for ram size by one byte to
-also store the number of ddr channels.
-The length of the tlv entry can indicate whether the new information is
-present. If not default to single channel.
-
-Signed-off-by: Josua Mayer <josua@solid-run.com>
----
- board/solidrun/clearfog/clearfog.c | 14 +++++++++++++-
- board/solidrun/common/tlv_data.c | 7 ++++++-
- board/solidrun/common/tlv_data.h | 1 +
- 3 files changed, 20 insertions(+), 2 deletions(-)
-
-diff --git a/board/solidrun/clearfog/clearfog.c b/board/solidrun/clearfog/clearfog.c
-index 6edb4221551..4f4532b537e 100644
---- a/board/solidrun/clearfog/clearfog.c
-+++ b/board/solidrun/clearfog/clearfog.c
-@@ -36,7 +36,7 @@ DECLARE_GLOBAL_DATA_PTR;
- #define BOARD_GPP_POL_LOW 0x0
- #define BOARD_GPP_POL_MID 0x0
-
--static struct tlv_data cf_tlv_data;
-+static struct tlv_data cf_tlv_data = { 0 };
-
- static void cf_read_tlv_data(void)
- {
-@@ -168,6 +168,18 @@ struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
- break;
- }
-
-+ switch (cf_tlv_data.ram_channels) {
-+ default:
-+ case 1:
-+ for (uint8_t i = 0; i < 5; i++)
-+ ifp->as_bus_params[i].cs_bitmask = 0x1;
-+ break;
-+ case 2:
-+ for (uint8_t i = 0; i < 5; i++)
-+ ifp->as_bus_params[i].cs_bitmask = 0x3;
-+ break;
-+ }
-+
- /* Return the board topology as defined in the board code */
- return &board_topology_map;
- }
-diff --git a/board/solidrun/common/tlv_data.c b/board/solidrun/common/tlv_data.c
-index 11d6e4a1380..cf5824886c3 100644
---- a/board/solidrun/common/tlv_data.c
-+++ b/board/solidrun/common/tlv_data.c
-@@ -45,9 +45,14 @@ static void parse_tlv_vendor_ext(struct tlvinfo_tlv *tlv_entry,
-
- if (val[4] != SR_TLV_CODE_RAM_SIZE)
- return;
-- if (tlv_entry->length != 6)
-+ if (tlv_entry->length < 6)
- return;
- td->ram_size = val[5];
-+
-+ /* extension with additional data field for number of ddr channels */
-+ if (tlv_entry->length >= 7) {
-+ td->ram_channels = val[6];
-+ }
- }
-
- static void parse_tlv_data(u8 *eeprom, struct tlvinfo_header *hdr,
-diff --git a/board/solidrun/common/tlv_data.h b/board/solidrun/common/tlv_data.h
-index a1432e4b8e1..be3f782ac4a 100644
---- a/board/solidrun/common/tlv_data.h
-+++ b/board/solidrun/common/tlv_data.h
-@@ -10,6 +10,7 @@ struct tlv_data {
- /* Store product name of both SOM and carrier */
- char tlv_product_name[2][32];
- unsigned int ram_size;
-+ uint8_t ram_channels;
- };
-
- void read_tlv_data(struct tlv_data *td);
---
-2.35.3
-
+++ /dev/null
-From b1b4941c2e3e16a21dc15604220725cf7f2de7c5 Mon Sep 17 00:00:00 2001
-From: Josua Mayer <josua@solid-run.com>
-Date: Wed, 20 Jul 2022 19:10:56 +0300
-Subject: [PATCH 2/2] arm: mvebu: clearfog: support 512MB memory size from tlv
- eeprom
-
-Handle 2GBit memory size value "2" from tlv eeprom on ddr
-initialisation, to support SoMs with 512MB ddr memory.
-
-Signed-off-by: Josua Mayer <josua@solid-run.com>
----
- board/solidrun/clearfog/clearfog.c | 3 +++
- 1 file changed, 3 insertions(+)
-
-diff --git a/board/solidrun/clearfog/clearfog.c b/board/solidrun/clearfog/clearfog.c
-index 4f4532b537e..6fa2fe5fe3e 100644
---- a/board/solidrun/clearfog/clearfog.c
-+++ b/board/solidrun/clearfog/clearfog.c
-@@ -159,6 +159,9 @@ struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
- cf_read_tlv_data();
-
- switch (cf_tlv_data.ram_size) {
-+ case 2:
-+ ifp->memory_size = MV_DDR_DIE_CAP_2GBIT;
-+ break;
- case 4:
- default:
- ifp->memory_size = MV_DDR_DIE_CAP_4GBIT;
---
-2.35.3
-
+++ /dev/null
-#
-# Copyright (C) 2012 OpenWrt.org
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-include $(TOPDIR)/rules.mk
-include $(INCLUDE_DIR)/kernel.mk
-
-PKG_VERSION:=2014.10
-PKG_RELEASE:=16
-
-PKG_HASH:=d3b132a7a9b3f3182b7aad71c2dfbd4fc15bea83e12c76134eb3ffefc07d1c71
-
-include $(INCLUDE_DIR)/u-boot.mk
-include $(INCLUDE_DIR)/package.mk
-
-define U-Boot/Default
- BUILD_TARGET:=oxnas
- BUILD_DEVICES:=Default
- HIDDEN:=y
-endef
-
-define U-Boot/ox820
- NAME:=Oxford/PLX NAS7820
-endef
-
-UBOOT_TARGETS:=ox820
-
-define Build/InstallDev
- $(INSTALL_DIR) $(STAGING_DIR_IMAGE)
- $(CP) $(PKG_BUILD_DIR)/u-boot.bin $(STAGING_DIR_IMAGE)/u-boot.bin
-endef
-
-$(eval $(call BuildPackage/U-Boot))
+++ /dev/null
-From df9fb90120423c4c55b66a5dc09af23f605a406b Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Mon, 1 Dec 2014 21:37:25 +0100
-Subject: [PATCH] disk/part.c: use unsigned format when printing capacity
-To: u-boot@lists.denx.de
-
-Large disks otherwise produce highly unplausible output such as
- Capacity: 1907729.0 MB = 1863.0 GB (-387938128 x 512)
-
-As supposedly all size-related decimals are unsigned, use unsigned
-format in printf statement, resulting in a correct capacity being
-displayed:
- Capacity: 1907729.0 MB = 1863.0 GB (3907029168 x 512)
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- disk/part.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/disk/part.c
-+++ b/disk/part.c
-@@ -229,13 +229,13 @@ void dev_print (block_dev_desc_t *dev_de
- printf (" Supports 48-bit addressing\n");
- #endif
- #if defined(CONFIG_SYS_64BIT_LBA)
-- printf (" Capacity: %ld.%ld MB = %ld.%ld GB (%Ld x %ld)\n",
-+ printf (" Capacity: %lu.%lu MB = %lu.%lu GB (%Lu x %lu)\n",
- mb_quot, mb_rem,
- gb_quot, gb_rem,
- lba,
- dev_desc->blksz);
- #else
-- printf (" Capacity: %ld.%ld MB = %ld.%ld GB (%ld x %ld)\n",
-+ printf (" Capacity: %lu.%lu MB = %lu.%lu GB (%lu x %lu)\n",
- mb_quot, mb_rem,
- gb_quot, gb_rem,
- (ulong)lba,
+++ /dev/null
---- a/tools/socfpgaimage.c
-+++ b/tools/socfpgaimage.c
-@@ -74,12 +74,12 @@ static uint16_t hdr_checksum(struct socf
- static void build_header(uint8_t *buf, uint8_t version, uint8_t flags,
- uint16_t length_bytes)
- {
-- header.validation = htole32(VALIDATION_WORD);
-+ header.validation = cpu_to_le32(VALIDATION_WORD);
- header.version = version;
- header.flags = flags;
-- header.length_u32 = htole16(length_bytes/4);
-+ header.length_u32 = cpu_to_le16(length_bytes/4);
- header.zero = 0;
-- header.checksum = htole16(hdr_checksum(&header));
-+ header.checksum = cpu_to_le16(hdr_checksum(&header));
-
- memcpy(buf, &header, sizeof(header));
- }
-@@ -92,12 +92,12 @@ static int verify_header(const uint8_t *
- {
- memcpy(&header, buf, sizeof(header));
-
-- if (le32toh(header.validation) != VALIDATION_WORD)
-+ if (le32_to_cpu(header.validation) != VALIDATION_WORD)
- return -1;
-- if (le16toh(header.checksum) != hdr_checksum(&header))
-+ if (le16_to_cpu(header.checksum) != hdr_checksum(&header))
- return -1;
-
-- return le16toh(header.length_u32) * 4;
-+ return le16_to_cpu(header.length_u32) * 4;
- }
-
- /* Sign the buffer and return the signed buffer size */
-@@ -116,7 +116,7 @@ static int sign_buffer(uint8_t *buf,
- /* Calculate and apply the CRC */
- calc_crc = ~pbl_crc32(0, (char *)buf, len);
-
-- *((uint32_t *)(buf + len)) = htole32(calc_crc);
-+ *((uint32_t *)(buf + len)) = cpu_to_le32(calc_crc);
-
- if (!pad_64k)
- return len + 4;
-@@ -150,7 +150,7 @@ static int verify_buffer(const uint8_t *
-
- calc_crc = ~pbl_crc32(0, (const char *)buf, len);
-
-- buf_crc = le32toh(*((uint32_t *)(buf + len)));
-+ buf_crc = le32_to_cpu(*((uint32_t *)(buf + len)));
-
- if (buf_crc != calc_crc) {
- fprintf(stderr, "CRC32 does not match (%08x != %08x)\n",
+++ /dev/null
---- a/common/spl/Makefile
-+++ b/common/spl/Makefile
-@@ -19,4 +19,5 @@ obj-$(CONFIG_SPL_MMC_SUPPORT) += spl_mmc
- obj-$(CONFIG_SPL_USB_SUPPORT) += spl_usb.o
- obj-$(CONFIG_SPL_FAT_SUPPORT) += spl_fat.o
- obj-$(CONFIG_SPL_SATA_SUPPORT) += spl_sata.o
-+obj-$(CONFIG_SPL_BLOCK_SUPPORT) += spl_block.o
- endif
---- a/common/spl/spl.c
-+++ b/common/spl/spl.c
-@@ -191,6 +191,14 @@ void board_init_r(gd_t *dummy1, ulong du
- spl_spi_load_image();
- break;
- #endif
-+#ifdef CONFIG_SPL_BLOCK_SUPPORT
-+ case BOOT_DEVICE_BLOCK:
-+ {
-+ extern void spl_block_load_image(void);
-+ spl_block_load_image();
-+ break;
-+ }
-+#endif
- #ifdef CONFIG_SPL_ETH_SUPPORT
- case BOOT_DEVICE_CPGMAC:
- #ifdef CONFIG_SPL_ETH_DEVICE
---- a/common/cmd_nvedit.c
-+++ b/common/cmd_nvedit.c
-@@ -49,6 +49,7 @@ DECLARE_GLOBAL_DATA_PTR;
- !defined(CONFIG_ENV_IS_IN_SPI_FLASH) && \
- !defined(CONFIG_ENV_IS_IN_REMOTE) && \
- !defined(CONFIG_ENV_IS_IN_UBI) && \
-+ !defined(CONFIG_ENV_IS_IN_EXT4) && \
- !defined(CONFIG_ENV_IS_NOWHERE)
- # error Define one of CONFIG_ENV_IS_IN_{EEPROM|FLASH|DATAFLASH|ONENAND|\
- SPI_FLASH|NVRAM|MMC|FAT|REMOTE|UBI} or CONFIG_ENV_IS_NOWHERE
---- a/common/Makefile
-+++ b/common/Makefile
-@@ -63,6 +63,7 @@ obj-$(CONFIG_ENV_IS_IN_ONENAND) += env_o
- obj-$(CONFIG_ENV_IS_IN_SPI_FLASH) += env_sf.o
- obj-$(CONFIG_ENV_IS_IN_REMOTE) += env_remote.o
- obj-$(CONFIG_ENV_IS_IN_UBI) += env_ubi.o
-+obj-$(CONFIG_ENV_IS_IN_EXT4) += env_ext4.o
- obj-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o
-
- # command
-@@ -213,6 +214,8 @@ obj-$(CONFIG_UPDATE_TFTP) += update.o
- obj-$(CONFIG_USB_KEYBOARD) += usb_kbd.o
- obj-$(CONFIG_CMD_DFU) += cmd_dfu.o
- obj-$(CONFIG_CMD_GPT) += cmd_gpt.o
-+else
-+obj-$(CONFIG_SPL_BLOCK_SUPPORT) += cmd_ide.o
- endif
-
- ifdef CONFIG_SPL_BUILD
+++ /dev/null
-From e719404ee1241af679a51879eaad291bc27e4817 Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Tue, 2 Dec 2014 14:46:05 +0100
-Subject: [PATCH] net/phy: add back icplus driver
-
-IC+ phy driver was removed due to the lack of users some time ago.
-Add it back, so we can use it.
----
- drivers/net/phy/Makefile | 1 +
- drivers/net/phy/icplus.c | 80 ++++++++++++++++++++++++++++++++++++++++++++++++
- drivers/net/phy/phy.c | 3 ++
- 3 files changed, 84 insertions(+)
- create mode 100644 drivers/net/phy/icplus.c
-
---- a/drivers/net/phy/Makefile
-+++ b/drivers/net/phy/Makefile
-@@ -15,6 +15,7 @@ obj-$(CONFIG_PHY_ATHEROS) += atheros.o
- obj-$(CONFIG_PHY_BROADCOM) += broadcom.o
- obj-$(CONFIG_PHY_DAVICOM) += davicom.o
- obj-$(CONFIG_PHY_ET1011C) += et1011c.o
-+obj-$(CONFIG_PHY_ICPLUS) += icplus.o
- obj-$(CONFIG_PHY_LXT) += lxt.o
- obj-$(CONFIG_PHY_MARVELL) += marvell.o
- obj-$(CONFIG_PHY_MICREL) += micrel.o
---- /dev/null
-+++ b/drivers/net/phy/icplus.c
-@@ -0,0 +1,93 @@
-+/*
-+ * ICPlus PHY drivers
-+ *
-+ * SPDX-License-Identifier: GPL-2.0+
-+ *
-+ * Copyright (c) 2007 Freescale Semiconductor, Inc.
-+ */
-+#include <phy.h>
-+
-+/* IP101A/G - IP1001 */
-+#define IP10XX_SPEC_CTRL_STATUS 16 /* Spec. Control Register */
-+#define IP1001_SPEC_CTRL_STATUS_2 20 /* IP1001 Spec. Control Reg 2 */
-+#define IP1001_PHASE_SEL_MASK 3 /* IP1001 RX/TXPHASE_SEL */
-+#define IP1001_APS_ON 11 /* IP1001 APS Mode bit */
-+#define IP101A_G_APS_ON 2 /* IP101A/G APS Mode bit */
-+#define IP101A_G_IRQ_CONF_STATUS 0x11 /* Conf Info IRQ & Status Reg */
-+#define IP101A_G_IRQ_PIN_USED (1<<15) /* INTR pin used */
-+#define IP101A_G_IRQ_DEFAULT IP101A_G_IRQ_PIN_USED
-+#define IP1001LF_DRIVE_MASK (15 << 5)
-+#define IP1001LF_RXCLKDRIVE_HI (2 << 5)
-+#define IP1001LF_RXDDRIVE_HI (2 << 7)
-+#define IP1001LF_RXCLKDRIVE_M (1 << 5)
-+#define IP1001LF_RXDDRIVE_M (1 << 7)
-+#define IP1001LF_RXCLKDRIVE_L (0 << 5)
-+#define IP1001LF_RXDDRIVE_L (0 << 7)
-+#define IP1001LF_RXCLKDRIVE_VL (3 << 5)
-+#define IP1001LF_RXDDRIVE_VL (3 << 7)
-+
-+static int ip1001_config(struct phy_device *phydev)
-+{
-+ int c;
-+
-+ /* Enable Auto Power Saving mode */
-+ c = phy_read(phydev, MDIO_DEVAD_NONE, IP1001_SPEC_CTRL_STATUS_2);
-+ if (c < 0)
-+ return c;
-+ c |= IP1001_APS_ON;
-+ c = phy_write(phydev, MDIO_DEVAD_NONE, IP1001_SPEC_CTRL_STATUS_2, c);
-+ if (c < 0)
-+ return c;
-+
-+ /* INTR pin used: speed/link/duplex will cause an interrupt */
-+ c = phy_write(phydev, MDIO_DEVAD_NONE, IP101A_G_IRQ_CONF_STATUS,
-+ IP101A_G_IRQ_DEFAULT);
-+ if (c < 0)
-+ return c;
-+
-+ if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
-+ /*
-+ * Additional delay (2ns) used to adjust RX clock phase
-+ * at RGMII interface
-+ */
-+ c = phy_read(phydev, MDIO_DEVAD_NONE, IP10XX_SPEC_CTRL_STATUS);
-+ if (c < 0)
-+ return c;
-+
-+ c |= IP1001_PHASE_SEL_MASK;
-+ /* adjust digtial drive strength */
-+ c &= ~IP1001LF_DRIVE_MASK;
-+ c |= IP1001LF_RXCLKDRIVE_M;
-+ c |= IP1001LF_RXDDRIVE_M;
-+ c = phy_write(phydev, MDIO_DEVAD_NONE, IP10XX_SPEC_CTRL_STATUS,
-+ c);
-+ if (c < 0)
-+ return c;
-+ }
-+
-+ return 0;
-+}
-+
-+static int ip1001_startup(struct phy_device *phydev)
-+{
-+ genphy_update_link(phydev);
-+ genphy_parse_link(phydev);
-+
-+ return 0;
-+}
-+static struct phy_driver IP1001_driver = {
-+ .name = "ICPlus IP1001",
-+ .uid = 0x02430d90,
-+ .mask = 0x0ffffff0,
-+ .features = PHY_GBIT_FEATURES,
-+ .config = &ip1001_config,
-+ .startup = &ip1001_startup,
-+ .shutdown = &genphy_shutdown,
-+};
-+
-+int phy_icplus_init(void)
-+{
-+ phy_register(&IP1001_driver);
-+
-+ return 0;
-+}
---- a/drivers/net/phy/phy.c
-+++ b/drivers/net/phy/phy.c
-@@ -454,6 +454,9 @@ int phy_init(void)
- #ifdef CONFIG_PHY_ET1011C
- phy_et1011c_init();
- #endif
-+#ifdef CONFIG_PHY_ICPLUS
-+ phy_icplus_init();
-+#endif
- #ifdef CONFIG_PHY_LXT
- phy_lxt_init();
- #endif
---- a/include/phy.h
-+++ b/include/phy.h
-@@ -225,6 +225,7 @@ int phy_atheros_init(void);
- int phy_broadcom_init(void);
- int phy_davicom_init(void);
- int phy_et1011c_init(void);
-+int phy_icplus_init(void);
- int phy_lxt_init(void);
- int phy_marvell_init(void);
- int phy_micrel_init(void);
+++ /dev/null
---- a/arch/arm/include/asm/mach-types.h
-+++ b/arch/arm/include/asm/mach-types.h
-@@ -212,6 +212,7 @@ extern unsigned int __machine_arch_type;
- #define MACH_TYPE_EDB9307A 1128
- #define MACH_TYPE_OMAP_3430SDP 1138
- #define MACH_TYPE_VSTMS 1140
-+#define MACH_TYPE_OXNAS 1152
- #define MACH_TYPE_MICRO9M 1169
- #define MACH_TYPE_BUG 1179
- #define MACH_TYPE_AT91SAM9263EK 1202
---- a/drivers/block/Makefile
-+++ b/drivers/block/Makefile
-@@ -21,3 +21,4 @@ obj-$(CONFIG_IDE_SIL680) += sil680.o
- obj-$(CONFIG_SANDBOX) += sandbox.o
- obj-$(CONFIG_SCSI_SYM53C8XX) += sym53c8xx.o
- obj-$(CONFIG_SYSTEMACE) += systemace.o
-+obj-$(CONFIG_IDE_PLX) += plxsata_ide.o
---- a/drivers/usb/host/Makefile
-+++ b/drivers/usb/host/Makefile
-@@ -33,6 +33,7 @@ obj-$(CONFIG_USB_EHCI_MX6) += ehci-mx6.o
- obj-$(CONFIG_USB_EHCI_OMAP) += ehci-omap.o
- obj-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o
- obj-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o
-+obj-$(CONFIG_USB_EHCI_OXNAS) += ehci-oxnas.o
- obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
- obj-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o
- obj-$(CONFIG_USB_EHCI_SUNXI) += ehci-sunxi.o
---- a/tools/.gitignore
-+++ b/tools/.gitignore
-@@ -9,6 +9,7 @@
- /mkenvimage
- /mkimage
- /mkexynosspl
-+/mkox820crc
- /mpc86x_clk
- /mxsboot
- /mksunxiboot
---- a/tools/Makefile
-+++ b/tools/Makefile
-@@ -143,6 +143,12 @@ hostprogs-$(CONFIG_KIRKWOOD) += kwboot
- hostprogs-y += proftool
- hostprogs-$(CONFIG_STATIC_RELA) += relocate-rela
-
-+
-+hostprogs-$(CONFIG_OX820) += mkox820crc$(SFX)
-+
-+mkox820crc$(SFX)-objs := mkox820crc.o lib/crc32.o
-+
-+
- # We build some files with extra pedantic flags to try to minimize things
- # that won't build on some weird host compiler -- though there are lots of
- # exceptions for files that aren't complaint.
---- a/drivers/serial/ns16550.c
-+++ b/drivers/serial/ns16550.c
-@@ -118,6 +118,14 @@ int ns16550_calc_divisor(NS16550_t port,
- }
- port->osc_12m_sel = 0; /* clear if previsouly set */
- #endif
-+#ifdef CONFIG_OX820
-+ {
-+ /* with additional 3 bit fractional */
-+ u32 div = (CONFIG_SYS_NS16550_CLK + baudrate) / (baudrate * 2);
-+ port->reg9 = (div & 7) << 5;
-+ return (div >> 3);
-+ }
-+#endif
-
- return DIV_ROUND_CLOSEST(clock, mode_x_div * baudrate);
- }
---- a/scripts/Makefile.spl
-+++ b/scripts/Makefile.spl
-@@ -202,6 +202,9 @@ OBJCOPYFLAGS_$(SPL_BIN).bin = $(SPL_OBJC
-
- $(obj)/$(SPL_BIN).bin: $(obj)/$(SPL_BIN) FORCE
- $(call if_changed,objcopy)
-+ifdef CONFIG_OX820
-+ $(OBJTREE)/tools/mkox820crc $@
-+endif
-
- LDFLAGS_$(SPL_BIN) += -T u-boot-spl.lds $(LDFLAGS_FINAL)
- ifneq ($(CONFIG_SPL_TEXT_BASE),)
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -488,6 +488,9 @@ config TARGET_BALLOON3
- config TARGET_H2200
- bool "Support h2200"
-
-+config TARGET_OX820
-+ bool "Support ox820"
-+
- config TARGET_PALMLD
- bool "Support palmld"
-
-@@ -650,6 +653,7 @@ source "board/logicpd/imx27lite/Kconfig"
- source "board/logicpd/imx31_litekit/Kconfig"
- source "board/mpl/vcma9/Kconfig"
- source "board/olimex/mx23_olinuxino/Kconfig"
-+source "board/ox820/Kconfig"
- source "board/palmld/Kconfig"
- source "board/palmtc/Kconfig"
- source "board/palmtreo680/Kconfig"
+++ /dev/null
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Sat, 7 Feb 2015 21:52:40 +0000 (+0100)
-Subject: Add linux/compiler-gcc5.h to fix builds with gcc5
-X-Git-Tag: v2015.04-rc2~31
-X-Git-Url: http://git.denx.de/?p=u-boot.git;a=commitdiff_plain;h=478b02f1a7043b673565075ea5016376f3293b23
-
-Add linux/compiler-gcc5.h to fix builds with gcc5
-
-Add linux/compiler-gcc5/h from the kernel sources at:
-
-commit 5631b8fba640a4ab2f8a954f63a603fa34eda96b
-Author: Steven Noonan <steven@uplinklabs.net>
-Date: Sat Oct 25 15:09:42 2014 -0700
-
- compiler/gcc4+: Remove inaccurate comment about 'asm goto' miscompiles
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
-
---- /dev/null
-+++ b/include/linux/compiler-gcc5.h
-@@ -0,0 +1,65 @@
-+#ifndef __LINUX_COMPILER_H
-+#error "Please don't include <linux/compiler-gcc5.h> directly, include <linux/compiler.h> instead."
-+#endif
-+
-+#define __used __attribute__((__used__))
-+#define __must_check __attribute__((warn_unused_result))
-+#define __compiler_offsetof(a, b) __builtin_offsetof(a, b)
-+
-+/* Mark functions as cold. gcc will assume any path leading to a call
-+ to them will be unlikely. This means a lot of manual unlikely()s
-+ are unnecessary now for any paths leading to the usual suspects
-+ like BUG(), printk(), panic() etc. [but let's keep them for now for
-+ older compilers]
-+
-+ Early snapshots of gcc 4.3 don't support this and we can't detect this
-+ in the preprocessor, but we can live with this because they're unreleased.
-+ Maketime probing would be overkill here.
-+
-+ gcc also has a __attribute__((__hot__)) to move hot functions into
-+ a special section, but I don't see any sense in this right now in
-+ the kernel context */
-+#define __cold __attribute__((__cold__))
-+
-+#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__)
-+
-+#ifndef __CHECKER__
-+# define __compiletime_warning(message) __attribute__((warning(message)))
-+# define __compiletime_error(message) __attribute__((error(message)))
-+#endif /* __CHECKER__ */
-+
-+/*
-+ * Mark a position in code as unreachable. This can be used to
-+ * suppress control flow warnings after asm blocks that transfer
-+ * control elsewhere.
-+ *
-+ * Early snapshots of gcc 4.5 don't support this and we can't detect
-+ * this in the preprocessor, but we can live with this because they're
-+ * unreleased. Really, we need to have autoconf for the kernel.
-+ */
-+#define unreachable() __builtin_unreachable()
-+
-+/* Mark a function definition as prohibited from being cloned. */
-+#define __noclone __attribute__((__noclone__))
-+
-+/*
-+ * Tell the optimizer that something else uses this function or variable.
-+ */
-+#define __visible __attribute__((externally_visible))
-+
-+/*
-+ * GCC 'asm goto' miscompiles certain code sequences:
-+ *
-+ * http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58670
-+ *
-+ * Work it around via a compiler barrier quirk suggested by Jakub Jelinek.
-+ *
-+ * (asm goto is automatically volatile - the naming reflects this.)
-+ */
-+#define asm_volatile_goto(x...) do { asm goto(x); asm (""); } while (0)
-+
-+#ifdef CONFIG_ARCH_USE_BUILTIN_BSWAP
-+#define __HAVE_BUILTIN_BSWAP32__
-+#define __HAVE_BUILTIN_BSWAP64__
-+#define __HAVE_BUILTIN_BSWAP16__
-+#endif /* CONFIG_ARCH_USE_BUILTIN_BSWAP */
+++ /dev/null
-From: Hans de Goede <hdegoede@redhat.com>
-Date: Sat, 7 Feb 2015 21:52:40 +0000 (+0100)
-Subject: Add linux/compiler-gcc6.h to fix builds with gcc6
-X-Git-Tag: v2015.04-rc2~31
-X-Git-Url: http://git.denx.de/?p=u-boot.git;a=commitdiff_plain;h=478b02f1a7043b673565075ea5016376f3293b23
-
-Add linux/compiler-gcc6.h to fix builds with gcc6
-
-Add linux/compiler-gcc6/h from the kernel sources at:
-
-commit 5631b8fba640a4ab2f8a954f63a603fa34eda96b
-Author: Steven Noonan <steven@uplinklabs.net>
-Date: Sat Oct 25 15:09:42 2014 -0700
-
- compiler/gcc4+: Remove inaccurate comment about 'asm goto' miscompiles
-
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
----
-
---- /dev/null
-+++ b/include/linux/compiler-gcc6.h
-@@ -0,0 +1,284 @@
-+#ifndef __LINUX_COMPILER_H
-+#error "Please don't include <linux/compiler-gcc.h> directly, include <linux/compiler.h> instead."
-+#endif
-+
-+/*
-+ * Common definitions for all gcc versions go here.
-+ */
-+#define GCC_VERSION (__GNUC__ * 10000 \
-+ + __GNUC_MINOR__ * 100 \
-+ + __GNUC_PATCHLEVEL__)
-+
-+/* Optimization barrier */
-+
-+/* The "volatile" is due to gcc bugs */
-+#define barrier() __asm__ __volatile__("": : :"memory")
-+/*
-+ * This version is i.e. to prevent dead stores elimination on @ptr
-+ * where gcc and llvm may behave differently when otherwise using
-+ * normal barrier(): while gcc behavior gets along with a normal
-+ * barrier(), llvm needs an explicit input variable to be assumed
-+ * clobbered. The issue is as follows: while the inline asm might
-+ * access any memory it wants, the compiler could have fit all of
-+ * @ptr into memory registers instead, and since @ptr never escaped
-+ * from that, it proofed that the inline asm wasn't touching any of
-+ * it. This version works well with both compilers, i.e. we're telling
-+ * the compiler that the inline asm absolutely may see the contents
-+ * of @ptr. See also: https://llvm.org/bugs/show_bug.cgi?id=15495
-+ */
-+#define barrier_data(ptr) __asm__ __volatile__("": :"r"(ptr) :"memory")
-+
-+/*
-+ * This macro obfuscates arithmetic on a variable address so that gcc
-+ * shouldn't recognize the original var, and make assumptions about it.
-+ *
-+ * This is needed because the C standard makes it undefined to do
-+ * pointer arithmetic on "objects" outside their boundaries and the
-+ * gcc optimizers assume this is the case. In particular they
-+ * assume such arithmetic does not wrap.
-+ *
-+ * A miscompilation has been observed because of this on PPC.
-+ * To work around it we hide the relationship of the pointer and the object
-+ * using this macro.
-+ *
-+ * Versions of the ppc64 compiler before 4.1 had a bug where use of
-+ * RELOC_HIDE could trash r30. The bug can be worked around by changing
-+ * the inline assembly constraint from =g to =r, in this particular
-+ * case either is valid.
-+ */
-+#define RELOC_HIDE(ptr, off) \
-+({ \
-+ unsigned long __ptr; \
-+ __asm__ ("" : "=r"(__ptr) : "0"(ptr)); \
-+ (typeof(ptr)) (__ptr + (off)); \
-+})
-+
-+/* Make the optimizer believe the variable can be manipulated arbitrarily. */
-+#define OPTIMIZER_HIDE_VAR(var) \
-+ __asm__ ("" : "=r" (var) : "0" (var))
-+
-+#ifdef __CHECKER__
-+#define __must_be_array(a) 0
-+#else
-+/* &a[0] degrades to a pointer: a different type from an array */
-+#define __must_be_array(a) BUILD_BUG_ON_ZERO(__same_type((a), &(a)[0]))
-+#endif
-+
-+/*
-+ * Force always-inline if the user requests it so via the .config,
-+ * or if gcc is too old:
-+ */
-+#if !defined(CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING) || \
-+ !defined(CONFIG_OPTIMIZE_INLINING) || (__GNUC__ < 4)
-+#define inline inline __attribute__((always_inline)) notrace
-+#define __inline__ __inline__ __attribute__((always_inline)) notrace
-+#define __inline __inline __attribute__((always_inline)) notrace
-+#else
-+/* A lot of inline functions can cause havoc with function tracing */
-+#define inline inline notrace
-+#define __inline__ __inline__ notrace
-+#define __inline __inline notrace
-+#endif
-+
-+#define __always_inline inline __attribute__((always_inline))
-+#define noinline __attribute__((noinline))
-+
-+#define __deprecated __attribute__((deprecated))
-+#define __packed __attribute__((packed))
-+#define __weak __attribute__((weak))
-+#define __alias(symbol) __attribute__((alias(#symbol)))
-+
-+/*
-+ * it doesn't make sense on ARM (currently the only user of __naked)
-+ * to trace naked functions because then mcount is called without
-+ * stack and frame pointer being set up and there is no chance to
-+ * restore the lr register to the value before mcount was called.
-+ *
-+ * The asm() bodies of naked functions often depend on standard calling
-+ * conventions, therefore they must be noinline and noclone.
-+ *
-+ * GCC 4.[56] currently fail to enforce this, so we must do so ourselves.
-+ * See GCC PR44290.
-+ */
-+#define __naked __attribute__((naked)) noinline __noclone notrace
-+
-+#define __noreturn __attribute__((noreturn))
-+
-+/*
-+ * From the GCC manual:
-+ *
-+ * Many functions have no effects except the return value and their
-+ * return value depends only on the parameters and/or global
-+ * variables. Such a function can be subject to common subexpression
-+ * elimination and loop optimization just as an arithmetic operator
-+ * would be.
-+ * [...]
-+ */
-+#define __pure __attribute__((pure))
-+#define __aligned(x) __attribute__((aligned(x)))
-+#define __printf(a, b) __attribute__((format(printf, a, b)))
-+#define __scanf(a, b) __attribute__((format(scanf, a, b)))
-+#define __attribute_const__ __attribute__((__const__))
-+#define __maybe_unused __attribute__((unused))
-+#define __always_unused __attribute__((unused))
-+
-+/* gcc version specific checks */
-+
-+#if GCC_VERSION < 30200
-+# error Sorry, your compiler is too old - please upgrade it.
-+#endif
-+
-+#if GCC_VERSION < 30300
-+# define __used __attribute__((__unused__))
-+#else
-+# define __used __attribute__((__used__))
-+#endif
-+
-+#ifdef CONFIG_GCOV_KERNEL
-+# if GCC_VERSION < 30400
-+# error "GCOV profiling support for gcc versions below 3.4 not included"
-+# endif /* __GNUC_MINOR__ */
-+#endif /* CONFIG_GCOV_KERNEL */
-+
-+#if GCC_VERSION >= 30400
-+#define __must_check __attribute__((warn_unused_result))
-+#define __malloc __attribute__((__malloc__))
-+#endif
-+
-+#if GCC_VERSION >= 40000
-+
-+/* GCC 4.1.[01] miscompiles __weak */
-+#ifdef __KERNEL__
-+# if GCC_VERSION >= 40100 && GCC_VERSION <= 40101
-+# error Your version of gcc miscompiles the __weak directive
-+# endif
-+#endif
-+
-+#define __used __attribute__((__used__))
-+#define __compiler_offsetof(a, b) \
-+ __builtin_offsetof(a, b)
-+
-+#if GCC_VERSION >= 40100 && GCC_VERSION < 40600
-+# define __compiletime_object_size(obj) __builtin_object_size(obj, 0)
-+#endif
-+
-+#if GCC_VERSION >= 40300
-+/* Mark functions as cold. gcc will assume any path leading to a call
-+ * to them will be unlikely. This means a lot of manual unlikely()s
-+ * are unnecessary now for any paths leading to the usual suspects
-+ * like BUG(), printk(), panic() etc. [but let's keep them for now for
-+ * older compilers]
-+ *
-+ * Early snapshots of gcc 4.3 don't support this and we can't detect this
-+ * in the preprocessor, but we can live with this because they're unreleased.
-+ * Maketime probing would be overkill here.
-+ *
-+ * gcc also has a __attribute__((__hot__)) to move hot functions into
-+ * a special section, but I don't see any sense in this right now in
-+ * the kernel context
-+ */
-+#define __cold __attribute__((__cold__))
-+
-+#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__)
-+
-+#ifndef __CHECKER__
-+# define __compiletime_warning(message) __attribute__((warning(message)))
-+# define __compiletime_error(message) __attribute__((error(message)))
-+#endif /* __CHECKER__ */
-+#endif /* GCC_VERSION >= 40300 */
-+
-+#if GCC_VERSION >= 40500
-+/*
-+ * Mark a position in code as unreachable. This can be used to
-+ * suppress control flow warnings after asm blocks that transfer
-+ * control elsewhere.
-+ *
-+ * Early snapshots of gcc 4.5 don't support this and we can't detect
-+ * this in the preprocessor, but we can live with this because they're
-+ * unreleased. Really, we need to have autoconf for the kernel.
-+ */
-+#define unreachable() __builtin_unreachable()
-+
-+/* Mark a function definition as prohibited from being cloned. */
-+#define __noclone __attribute__((__noclone__, __optimize__("no-tracer")))
-+
-+#endif /* GCC_VERSION >= 40500 */
-+
-+#if GCC_VERSION >= 40600
-+/*
-+ * When used with Link Time Optimization, gcc can optimize away C functions or
-+ * variables which are referenced only from assembly code. __visible tells the
-+ * optimizer that something else uses this function or variable, thus preventing
-+ * this.
-+ */
-+#define __visible __attribute__((externally_visible))
-+#endif
-+
-+
-+#if GCC_VERSION >= 40900 && !defined(__CHECKER__)
-+/*
-+ * __assume_aligned(n, k): Tell the optimizer that the returned
-+ * pointer can be assumed to be k modulo n. The second argument is
-+ * optional (default 0), so we use a variadic macro to make the
-+ * shorthand.
-+ *
-+ * Beware: Do not apply this to functions which may return
-+ * ERR_PTRs. Also, it is probably unwise to apply it to functions
-+ * returning extra information in the low bits (but in that case the
-+ * compiler should see some alignment anyway, when the return value is
-+ * massaged by 'flags = ptr & 3; ptr &= ~3;').
-+ */
-+#define __assume_aligned(a, ...) __attribute__((__assume_aligned__(a, ## __VA_ARGS__)))
-+#endif
-+
-+/*
-+ * GCC 'asm goto' miscompiles certain code sequences:
-+ *
-+ * http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58670
-+ *
-+ * Work it around via a compiler barrier quirk suggested by Jakub Jelinek.
-+ *
-+ * (asm goto is automatically volatile - the naming reflects this.)
-+ */
-+#define asm_volatile_goto(x...) do { asm goto(x); asm (""); } while (0)
-+
-+#ifdef CONFIG_ARCH_USE_BUILTIN_BSWAP
-+#if GCC_VERSION >= 40400
-+#define __HAVE_BUILTIN_BSWAP32__
-+#define __HAVE_BUILTIN_BSWAP64__
-+#endif
-+#if GCC_VERSION >= 40800
-+#define __HAVE_BUILTIN_BSWAP16__
-+#endif
-+#endif /* CONFIG_ARCH_USE_BUILTIN_BSWAP */
-+
-+#if GCC_VERSION >= 50000
-+#define KASAN_ABI_VERSION 4
-+#elif GCC_VERSION >= 40902
-+#define KASAN_ABI_VERSION 3
-+#endif
-+
-+#if GCC_VERSION >= 40902
-+/*
-+ * Tell the compiler that address safety instrumentation (KASAN)
-+ * should not be applied to that function.
-+ * Conflicts with inlining: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67368
-+ */
-+#define __no_sanitize_address __attribute__((no_sanitize_address))
-+#endif
-+
-+#endif /* gcc version >= 40000 specific checks */
-+
-+#if !defined(__noclone)
-+#define __noclone /* not needed */
-+#endif
-+
-+#if !defined(__no_sanitize_address)
-+#define __no_sanitize_address
-+#endif
-+
-+/*
-+ * A trick to suppress uninitialized variable warning without generating any
-+ * code
-+ */
-+#define uninitialized_var(x) x = x
+++ /dev/null
---- /dev/null
-+++ b/include/linux/compiler-gcc7.h
-@@ -0,0 +1,284 @@
-+#ifndef __LINUX_COMPILER_H
-+#error "Please don't include <linux/compiler-gcc.h> directly, include <linux/compiler.h> instead."
-+#endif
-+
-+/*
-+ * Common definitions for all gcc versions go here.
-+ */
-+#define GCC_VERSION (__GNUC__ * 10000 \
-+ + __GNUC_MINOR__ * 100 \
-+ + __GNUC_PATCHLEVEL__)
-+
-+/* Optimization barrier */
-+
-+/* The "volatile" is due to gcc bugs */
-+#define barrier() __asm__ __volatile__("": : :"memory")
-+/*
-+ * This version is i.e. to prevent dead stores elimination on @ptr
-+ * where gcc and llvm may behave differently when otherwise using
-+ * normal barrier(): while gcc behavior gets along with a normal
-+ * barrier(), llvm needs an explicit input variable to be assumed
-+ * clobbered. The issue is as follows: while the inline asm might
-+ * access any memory it wants, the compiler could have fit all of
-+ * @ptr into memory registers instead, and since @ptr never escaped
-+ * from that, it proofed that the inline asm wasn't touching any of
-+ * it. This version works well with both compilers, i.e. we're telling
-+ * the compiler that the inline asm absolutely may see the contents
-+ * of @ptr. See also: https://llvm.org/bugs/show_bug.cgi?id=15495
-+ */
-+#define barrier_data(ptr) __asm__ __volatile__("": :"r"(ptr) :"memory")
-+
-+/*
-+ * This macro obfuscates arithmetic on a variable address so that gcc
-+ * shouldn't recognize the original var, and make assumptions about it.
-+ *
-+ * This is needed because the C standard makes it undefined to do
-+ * pointer arithmetic on "objects" outside their boundaries and the
-+ * gcc optimizers assume this is the case. In particular they
-+ * assume such arithmetic does not wrap.
-+ *
-+ * A miscompilation has been observed because of this on PPC.
-+ * To work around it we hide the relationship of the pointer and the object
-+ * using this macro.
-+ *
-+ * Versions of the ppc64 compiler before 4.1 had a bug where use of
-+ * RELOC_HIDE could trash r30. The bug can be worked around by changing
-+ * the inline assembly constraint from =g to =r, in this particular
-+ * case either is valid.
-+ */
-+#define RELOC_HIDE(ptr, off) \
-+({ \
-+ unsigned long __ptr; \
-+ __asm__ ("" : "=r"(__ptr) : "0"(ptr)); \
-+ (typeof(ptr)) (__ptr + (off)); \
-+})
-+
-+/* Make the optimizer believe the variable can be manipulated arbitrarily. */
-+#define OPTIMIZER_HIDE_VAR(var) \
-+ __asm__ ("" : "=r" (var) : "0" (var))
-+
-+#ifdef __CHECKER__
-+#define __must_be_array(a) 0
-+#else
-+/* &a[0] degrades to a pointer: a different type from an array */
-+#define __must_be_array(a) BUILD_BUG_ON_ZERO(__same_type((a), &(a)[0]))
-+#endif
-+
-+/*
-+ * Force always-inline if the user requests it so via the .config,
-+ * or if gcc is too old:
-+ */
-+#if !defined(CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING) || \
-+ !defined(CONFIG_OPTIMIZE_INLINING) || (__GNUC__ < 4)
-+#define inline inline __attribute__((always_inline)) notrace
-+#define __inline__ __inline__ __attribute__((always_inline)) notrace
-+#define __inline __inline __attribute__((always_inline)) notrace
-+#else
-+/* A lot of inline functions can cause havoc with function tracing */
-+#define inline inline notrace
-+#define __inline__ __inline__ notrace
-+#define __inline __inline notrace
-+#endif
-+
-+#define __always_inline inline __attribute__((always_inline))
-+#define noinline __attribute__((noinline))
-+
-+#define __deprecated __attribute__((deprecated))
-+#define __packed __attribute__((packed))
-+#define __weak __attribute__((weak))
-+#define __alias(symbol) __attribute__((alias(#symbol)))
-+
-+/*
-+ * it doesn't make sense on ARM (currently the only user of __naked)
-+ * to trace naked functions because then mcount is called without
-+ * stack and frame pointer being set up and there is no chance to
-+ * restore the lr register to the value before mcount was called.
-+ *
-+ * The asm() bodies of naked functions often depend on standard calling
-+ * conventions, therefore they must be noinline and noclone.
-+ *
-+ * GCC 4.[56] currently fail to enforce this, so we must do so ourselves.
-+ * See GCC PR44290.
-+ */
-+#define __naked __attribute__((naked)) noinline __noclone notrace
-+
-+#define __noreturn __attribute__((noreturn))
-+
-+/*
-+ * From the GCC manual:
-+ *
-+ * Many functions have no effects except the return value and their
-+ * return value depends only on the parameters and/or global
-+ * variables. Such a function can be subject to common subexpression
-+ * elimination and loop optimization just as an arithmetic operator
-+ * would be.
-+ * [...]
-+ */
-+#define __pure __attribute__((pure))
-+#define __aligned(x) __attribute__((aligned(x)))
-+#define __printf(a, b) __attribute__((format(printf, a, b)))
-+#define __scanf(a, b) __attribute__((format(scanf, a, b)))
-+#define __attribute_const__ __attribute__((__const__))
-+#define __maybe_unused __attribute__((unused))
-+#define __always_unused __attribute__((unused))
-+
-+/* gcc version specific checks */
-+
-+#if GCC_VERSION < 30200
-+# error Sorry, your compiler is too old - please upgrade it.
-+#endif
-+
-+#if GCC_VERSION < 30300
-+# define __used __attribute__((__unused__))
-+#else
-+# define __used __attribute__((__used__))
-+#endif
-+
-+#ifdef CONFIG_GCOV_KERNEL
-+# if GCC_VERSION < 30400
-+# error "GCOV profiling support for gcc versions below 3.4 not included"
-+# endif /* __GNUC_MINOR__ */
-+#endif /* CONFIG_GCOV_KERNEL */
-+
-+#if GCC_VERSION >= 30400
-+#define __must_check __attribute__((warn_unused_result))
-+#define __malloc __attribute__((__malloc__))
-+#endif
-+
-+#if GCC_VERSION >= 40000
-+
-+/* GCC 4.1.[01] miscompiles __weak */
-+#ifdef __KERNEL__
-+# if GCC_VERSION >= 40100 && GCC_VERSION <= 40101
-+# error Your version of gcc miscompiles the __weak directive
-+# endif
-+#endif
-+
-+#define __used __attribute__((__used__))
-+#define __compiler_offsetof(a, b) \
-+ __builtin_offsetof(a, b)
-+
-+#if GCC_VERSION >= 40100 && GCC_VERSION < 40600
-+# define __compiletime_object_size(obj) __builtin_object_size(obj, 0)
-+#endif
-+
-+#if GCC_VERSION >= 40300
-+/* Mark functions as cold. gcc will assume any path leading to a call
-+ * to them will be unlikely. This means a lot of manual unlikely()s
-+ * are unnecessary now for any paths leading to the usual suspects
-+ * like BUG(), printk(), panic() etc. [but let's keep them for now for
-+ * older compilers]
-+ *
-+ * Early snapshots of gcc 4.3 don't support this and we can't detect this
-+ * in the preprocessor, but we can live with this because they're unreleased.
-+ * Maketime probing would be overkill here.
-+ *
-+ * gcc also has a __attribute__((__hot__)) to move hot functions into
-+ * a special section, but I don't see any sense in this right now in
-+ * the kernel context
-+ */
-+#define __cold __attribute__((__cold__))
-+
-+#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__)
-+
-+#ifndef __CHECKER__
-+# define __compiletime_warning(message) __attribute__((warning(message)))
-+# define __compiletime_error(message) __attribute__((error(message)))
-+#endif /* __CHECKER__ */
-+#endif /* GCC_VERSION >= 40300 */
-+
-+#if GCC_VERSION >= 40500
-+/*
-+ * Mark a position in code as unreachable. This can be used to
-+ * suppress control flow warnings after asm blocks that transfer
-+ * control elsewhere.
-+ *
-+ * Early snapshots of gcc 4.5 don't support this and we can't detect
-+ * this in the preprocessor, but we can live with this because they're
-+ * unreleased. Really, we need to have autoconf for the kernel.
-+ */
-+#define unreachable() __builtin_unreachable()
-+
-+/* Mark a function definition as prohibited from being cloned. */
-+#define __noclone __attribute__((__noclone__, __optimize__("no-tracer")))
-+
-+#endif /* GCC_VERSION >= 40500 */
-+
-+#if GCC_VERSION >= 40600
-+/*
-+ * When used with Link Time Optimization, gcc can optimize away C functions or
-+ * variables which are referenced only from assembly code. __visible tells the
-+ * optimizer that something else uses this function or variable, thus preventing
-+ * this.
-+ */
-+#define __visible __attribute__((externally_visible))
-+#endif
-+
-+
-+#if GCC_VERSION >= 40900 && !defined(__CHECKER__)
-+/*
-+ * __assume_aligned(n, k): Tell the optimizer that the returned
-+ * pointer can be assumed to be k modulo n. The second argument is
-+ * optional (default 0), so we use a variadic macro to make the
-+ * shorthand.
-+ *
-+ * Beware: Do not apply this to functions which may return
-+ * ERR_PTRs. Also, it is probably unwise to apply it to functions
-+ * returning extra information in the low bits (but in that case the
-+ * compiler should see some alignment anyway, when the return value is
-+ * massaged by 'flags = ptr & 3; ptr &= ~3;').
-+ */
-+#define __assume_aligned(a, ...) __attribute__((__assume_aligned__(a, ## __VA_ARGS__)))
-+#endif
-+
-+/*
-+ * GCC 'asm goto' miscompiles certain code sequences:
-+ *
-+ * http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58670
-+ *
-+ * Work it around via a compiler barrier quirk suggested by Jakub Jelinek.
-+ *
-+ * (asm goto is automatically volatile - the naming reflects this.)
-+ */
-+#define asm_volatile_goto(x...) do { asm goto(x); asm (""); } while (0)
-+
-+#ifdef CONFIG_ARCH_USE_BUILTIN_BSWAP
-+#if GCC_VERSION >= 40400
-+#define __HAVE_BUILTIN_BSWAP32__
-+#define __HAVE_BUILTIN_BSWAP64__
-+#endif
-+#if GCC_VERSION >= 40800
-+#define __HAVE_BUILTIN_BSWAP16__
-+#endif
-+#endif /* CONFIG_ARCH_USE_BUILTIN_BSWAP */
-+
-+#if GCC_VERSION >= 50000
-+#define KASAN_ABI_VERSION 4
-+#elif GCC_VERSION >= 40902
-+#define KASAN_ABI_VERSION 3
-+#endif
-+
-+#if GCC_VERSION >= 40902
-+/*
-+ * Tell the compiler that address safety instrumentation (KASAN)
-+ * should not be applied to that function.
-+ * Conflicts with inlining: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=67368
-+ */
-+#define __no_sanitize_address __attribute__((no_sanitize_address))
-+#endif
-+
-+#endif /* gcc version >= 40000 specific checks */
-+
-+#if !defined(__noclone)
-+#define __noclone /* not needed */
-+#endif
-+
-+#if !defined(__no_sanitize_address)
-+#define __no_sanitize_address
-+#endif
-+
-+/*
-+ * A trick to suppress uninitialized variable warning without generating any
-+ * code
-+ */
-+#define uninitialized_var(x) x = x
+++ /dev/null
---- a/common/cmd_bootm.c
-+++ b/common/cmd_bootm.c
-@@ -77,7 +77,7 @@ static int do_bootm_subcommand(cmd_tbl_t
- return CMD_RET_USAGE;
- }
-
-- if (state != BOOTM_STATE_START && images.state >= state) {
-+ if (!(state & BOOTM_STATE_START) && images.state >= state) {
- printf("Trying to execute a command out of order\n");
- return CMD_RET_USAGE;
- }
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += reset.o
-obj-y += timer.o
-obj-y += clock.o
-obj-y += pinmux.o
+++ /dev/null
-#include <common.h>
-#include <asm/arch/sysctl.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clock.h>
-
-typedef struct {
- unsigned short mhz;
- unsigned char refdiv;
- unsigned char outdiv;
- unsigned int fbdiv;
- unsigned short bwadj;
- unsigned short sfreq;
- unsigned int sslope;
-} PLL_CONFIG;
-
-const PLL_CONFIG C_PLL_CONFIG[] = {
- { 500, 1, 2, 3932160, 119, 208, 189 }, // 500 MHz
- { 525, 2, 1, 4128768, 125, 139, 297 }, // 525 MHz
- { 550, 2, 1, 4325376, 131, 139, 311 }, // 550 MHz
- { 575, 2, 1, 4521984, 137, 139, 326 }, // 575 MHz
- { 600, 2, 1, 4718592, 143, 138, 339 }, // 600 MHz
- { 625, 1, 1, 3276800, 99, 208, 157 }, // 625 MHz
- { 650, 1, 1, 3407872, 103, 208, 164 }, // 650 MHz
- { 675, 1, 1, 3538944, 107, 208, 170 }, // 675 MHz
- { 700, 0, 0, 917504, 27, 416, 22 }, // 700 MHz
- { 725, 1, 1, 3801088, 115, 208, 182 }, // 725 MHz
- { 750, 0, 0, 983040, 29, 416, 23 }, // 750 MHz
- { 775, 3, 0, 4063232, 123, 104, 390 }, // 775 MHz
- { 800, 3, 0, 4194304, 127, 104, 403 }, // 800 MHz
- { 825, 3, 0, 4325376, 131, 104, 415 }, // 825 MHz
- { 850, 2, 0, 3342336, 101, 139, 241 }, // 850 MHz
- { 875, 2, 0, 3440640, 104, 139, 248 }, // 875 MHz
- { 900, 2, 0, 3538944, 107, 139, 255 }, // 900 MHz
- { 925, 2, 0, 3637248, 110, 139, 262 }, // 925 MHz
- { 950, 2, 0, 3735552, 113, 139, 269 }, // 950 MHz
- { 975, 2, 0, 3833856, 116, 139, 276 }, // 975 MHz
- { 1000, 2, 0, 3932160, 119, 139, 283 }, // 1000 MHz
-};
-
-#define PLL_BYPASS (1<<1)
-#define SAT_ENABLE (1<<3)
-
-#define PLL_OUTDIV_SHIFT 4
-#define PLL_REFDIV_SHIFT 8
-#define PLL_BWADJ_SHIFT 16
-
-#define PLL_LOW_FREQ 500
-#define PLL_FREQ_STEP 25
-static void plla_configure(int outdiv, int refdiv, int fbdiv, int bwadj,
- int sfreq, int sslope)
-{
- setbits_le32(SYS_CTRL_PLLA_CTRL0, PLL_BYPASS);
- udelay(10);
- reset_block(SYS_CTRL_RST_PLLA, 1);
- udelay(10);
-
- writel((refdiv << PLL_REFDIV_SHIFT) | (outdiv << PLL_OUTDIV_SHIFT) |
- SAT_ENABLE | PLL_BYPASS,
- SYS_CTRL_PLLA_CTRL0);
-
- writel(fbdiv, SYS_CTRL_PLLA_CTRL1);
- writel((bwadj << PLL_BWADJ_SHIFT) | sfreq, SYS_CTRL_PLLA_CTRL2);
- writel(sslope, SYS_CTRL_PLLA_CTRL3);
-
- udelay(10); // 5us delay required (from TCI datasheet), use 10us
-
- reset_block(SYS_CTRL_RST_PLLA, 0);
-
- udelay(100); // Delay for PLL to lock
-
- printf(" plla_ctrl0 : %08x\n", readl(SYS_CTRL_PLLA_CTRL0));
- printf(" plla_ctrl1 : %08x\n", readl(SYS_CTRL_PLLA_CTRL1));
- printf(" plla_ctrl2 : %08x\n", readl(SYS_CTRL_PLLA_CTRL2));
- printf(" plla_ctrl3 : %08x\n", readl(SYS_CTRL_PLLA_CTRL3));
-
- clrbits_le32(SYS_CTRL_PLLA_CTRL0, PLL_BYPASS); // Take PLL out of bypass
- puts("\nPLLA Set\n");
-}
-
-int plla_set_config(int mhz)
-{
- int index = (mhz - PLL_LOW_FREQ) / PLL_FREQ_STEP;
- const PLL_CONFIG *cfg;
-
- if (index < 0 || index > ARRAY_SIZE(C_PLL_CONFIG)) {
- debug("Freq %d MHz out of range, default to lowest\n", mhz);
- index = 0;
- }
- cfg = &C_PLL_CONFIG[index];
-
- printf("Attempting to set PLLA to %d MHz ...\n", (unsigned) cfg->mhz);
- plla_configure(cfg->outdiv, cfg->refdiv, cfg->fbdiv, cfg->bwadj,
- cfg->sfreq, cfg->sslope);
-
- return cfg->mhz;
-}
-
+++ /dev/null
-#include <common.h>
-#include <asm/arch/pinmux.h>
-
-void pinmux_set(int bank, int pin, int func)
-{
- u32 reg;
- u32 base;
- /* TODO: check parameters */
-
- if (bank == PINMUX_BANK_MFA)
- base = SYS_CONTROL_BASE;
- else
- base = SEC_CONTROL_BASE;
-
- clrbits_le32(base + PINMUX_SECONDARY_SEL, BIT(pin));
- clrbits_le32(base + PINMUX_TERTIARY_SEL, BIT(pin));
- clrbits_le32(base + PINMUX_QUATERNARY_SEL, BIT(pin));
- clrbits_le32(base + PINMUX_DEBUG_SEL, BIT(pin));
- clrbits_le32(base + PINMUX_ALTERNATIVE_SEL, BIT(pin));
-
- switch (func) {
- case PINMUX_GPIO:
- default:
- return;
- break;
- case PINMUX_2:
- reg = base + PINMUX_SECONDARY_SEL;
- break;
- case PINMUX_3:
- reg = base + PINMUX_TERTIARY_SEL;
- break;
- case PINMUX_4:
- reg = base + PINMUX_QUATERNARY_SEL;
- break;
- case PINMUX_DEBUG:
- reg = base + PINMUX_DEBUG_SEL;
- break;
- case PINMUX_ALT:
- reg = base + PINMUX_ALTERNATIVE_SEL;
- break;
- }
- setbits_le32(reg, BIT(pin));
-}
+++ /dev/null
-#include <common.h>
-#include <asm/arch/sysctl.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch/clock.h>
-
-void reset_cpu(ulong addr)
-{
- u32 value;
-
- // Assert reset to cores as per power on defaults
- // Don't touch the DDR interface as things will come to an impromptu stop
- // NB Possibly should be asserting reset for PLLB, but there are timing
- // concerns here according to the docs
-
- value =
- BIT(SYS_CTRL_RST_COPRO ) |
- BIT(SYS_CTRL_RST_USBHS ) |
- BIT(SYS_CTRL_RST_USBHSPHYA ) |
- BIT(SYS_CTRL_RST_MACA ) |
- BIT(SYS_CTRL_RST_PCIEA ) |
- BIT(SYS_CTRL_RST_SGDMA ) |
- BIT(SYS_CTRL_RST_CIPHER ) |
- BIT(SYS_CTRL_RST_SATA ) |
- BIT(SYS_CTRL_RST_SATA_LINK ) |
- BIT(SYS_CTRL_RST_SATA_PHY ) |
- BIT(SYS_CTRL_RST_PCIEPHY ) |
- BIT(SYS_CTRL_RST_STATIC ) |
- BIT(SYS_CTRL_RST_UART1 ) |
- BIT(SYS_CTRL_RST_UART2 ) |
- BIT(SYS_CTRL_RST_MISC ) |
- BIT(SYS_CTRL_RST_I2S ) |
- BIT(SYS_CTRL_RST_SD ) |
- BIT(SYS_CTRL_RST_MACB ) |
- BIT(SYS_CTRL_RST_PCIEB ) |
- BIT(SYS_CTRL_RST_VIDEO ) |
- BIT(SYS_CTRL_RST_USBHSPHYB ) |
- BIT(SYS_CTRL_RST_USBDEV );
-
- writel(value, SYS_CTRL_RST_SET_CTRL);
-
- // Release reset to cores as per power on defaults
- writel(BIT(SYS_CTRL_RST_GPIO), SYS_CTRL_RST_CLR_CTRL);
-
- // Disable clocks to cores as per power-on defaults - must leave DDR
- // related clocks enabled otherwise we'll stop rather abruptly.
- value =
- BIT(SYS_CTRL_CLK_COPRO) |
- BIT(SYS_CTRL_CLK_DMA) |
- BIT(SYS_CTRL_CLK_CIPHER) |
- BIT(SYS_CTRL_CLK_SD) |
- BIT(SYS_CTRL_CLK_SATA) |
- BIT(SYS_CTRL_CLK_I2S) |
- BIT(SYS_CTRL_CLK_USBHS) |
- BIT(SYS_CTRL_CLK_MAC) |
- BIT(SYS_CTRL_CLK_PCIEA) |
- BIT(SYS_CTRL_CLK_STATIC) |
- BIT(SYS_CTRL_CLK_MACB) |
- BIT(SYS_CTRL_CLK_PCIEB) |
- BIT(SYS_CTRL_CLK_REF600) |
- BIT(SYS_CTRL_CLK_USBDEV);
-
- writel(value, SYS_CTRL_CLK_CLR_CTRL);
-
- // Enable clocks to cores as per power-on defaults
-
- // Set sys-control pin mux'ing as per power-on defaults
-
- writel(0, SYS_CONTROL_BASE + PINMUX_SECONDARY_SEL);
- writel(0, SYS_CONTROL_BASE + PINMUX_TERTIARY_SEL);
- writel(0, SYS_CONTROL_BASE + PINMUX_QUATERNARY_SEL);
- writel(0, SYS_CONTROL_BASE + PINMUX_DEBUG_SEL);
- writel(0, SYS_CONTROL_BASE + PINMUX_ALTERNATIVE_SEL);
- writel(0, SYS_CONTROL_BASE + PINMUX_PULLUP_SEL);
-
- writel(0, SEC_CONTROL_BASE + PINMUX_SECONDARY_SEL);
- writel(0, SEC_CONTROL_BASE + PINMUX_TERTIARY_SEL);
- writel(0, SEC_CONTROL_BASE + PINMUX_QUATERNARY_SEL);
- writel(0, SEC_CONTROL_BASE + PINMUX_DEBUG_SEL);
- writel(0, SEC_CONTROL_BASE + PINMUX_ALTERNATIVE_SEL);
- writel(0, SEC_CONTROL_BASE + PINMUX_PULLUP_SEL);
-
- // No need to save any state, as the ROM loader can determine whether reset
- // is due to power cycling or programatic action, just hit the (self-
- // clearing) CPU reset bit of the block reset register
- value =
- BIT(SYS_CTRL_RST_SCU) |
- BIT(SYS_CTRL_RST_ARM0) |
- BIT(SYS_CTRL_RST_ARM1);
-
- writel(value, SYS_CTRL_RST_SET_CTRL);
-}
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Texas Instruments
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-
-#define TIMER_CLOCK (CONFIG_SYS_CLK_FREQ / (1 << (CONFIG_TIMER_PRESCALE * 4)))
-#define TIMER_LOAD_VAL 0xFFFFFF
-
-/* macro to read the 32 bit timer */
-#define READ_TIMER (TIMER_LOAD_VAL - readl(CONFIG_SYS_TIMERBASE + TIMER_CURR)) \
- / (TIMER_CLOCK / CONFIG_SYS_HZ)
-
-#define READ_TIMER_HW (TIMER_LOAD_VAL - readl(CONFIG_SYS_TIMERBASE + TIMER_CURR))
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int timer_init (void)
-{
- int32_t val;
-
- /* Start the counter ticking up */
- writel(TIMER_LOAD_VAL, CONFIG_SYS_TIMERBASE + TIMER_LOAD); /* reload value on overflow*/
-
- val = (CONFIG_TIMER_PRESCALE << TIMER_PRESCALE_SHIFT) |
- (TIMER_MODE_PERIODIC << TIMER_MODE_SHIFT) |
- (TIMER_ENABLE << TIMER_ENABLE_SHIFT); /* mask to enable timer*/
- writel(val, CONFIG_SYS_TIMERBASE + TIMER_CTRL); /* start timer */
-
- /* reset time */
- gd->arch.lastinc = READ_TIMER; /* capture current incrementer value */
- gd->arch.tbl = 0; /* start "advancing" time stamp */
-
- return(0);
-}
-/*
- * timer without interrupts
- */
-ulong get_timer (ulong base)
-{
- return get_timer_masked () - base;
-}
-
-/* delay x useconds AND preserve advance timestamp value */
-void __udelay (unsigned long usec)
-{
- ulong tmo, tmp;
-
- if (usec > 100000) { /* if "big" number, spread normalization to seconds */
- tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
- tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */
- tmo /= 1000; /* finish normalize. */
-
- tmp = get_timer (0); /* get current timestamp */
- while (get_timer (tmp) < tmo)/* loop till event */
- /*NOP*/;
- } else { /* else small number, convert to hw ticks */
- tmo = usec * (TIMER_CLOCK / 1000) / 1000;
- /* timeout is no more than 0.1s, and the hw timer will roll over at most once */
- tmp = READ_TIMER_HW;
- while (((READ_TIMER_HW -tmp) & TIMER_LOAD_VAL) < tmo)/* loop till event */
- /*NOP*/;
- }
-}
-
-ulong get_timer_masked (void)
-{
- ulong now = READ_TIMER; /* current tick value */
-
- if (now >= gd->arch.lastinc) { /* normal mode (non roll) */
- /* move stamp fordward with absoulte diff ticks */
- gd->arch.tbl += (now - gd->arch.lastinc);
- } else {
- /* we have rollover of incrementer */
- gd->arch.tbl += ((TIMER_LOAD_VAL / (TIMER_CLOCK / CONFIG_SYS_HZ))
- - gd->arch.lastinc) + now;
- }
- gd->arch.lastinc = now;
- return gd->arch.tbl;
-}
-
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
- ulong tbclk;
- tbclk = CONFIG_SYS_HZ;
- return tbclk;
-}
+++ /dev/null
-#ifndef _NAS782X_CLOCK_H
-#define _NAS782X_CLOCK_H
-
-#include <asm/arch/sysctl.h>
-#include <asm/arch/cpu.h>
-
-/* bit numbers of clock control register */
-#define SYS_CTRL_CLK_COPRO 0
-#define SYS_CTRL_CLK_DMA 1
-#define SYS_CTRL_CLK_CIPHER 2
-#define SYS_CTRL_CLK_SD 3
-#define SYS_CTRL_CLK_SATA 4
-#define SYS_CTRL_CLK_I2S 5
-#define SYS_CTRL_CLK_USBHS 6
-#define SYS_CTRL_CLK_MACA 7
-#define SYS_CTRL_CLK_MAC SYS_CTRL_CLK_MACA
-#define SYS_CTRL_CLK_PCIEA 8
-#define SYS_CTRL_CLK_STATIC 9
-#define SYS_CTRL_CLK_MACB 10
-#define SYS_CTRL_CLK_PCIEB 11
-#define SYS_CTRL_CLK_REF600 12
-#define SYS_CTRL_CLK_USBDEV 13
-#define SYS_CTRL_CLK_DDR 14
-#define SYS_CTRL_CLK_DDRPHY 15
-#define SYS_CTRL_CLK_DDRCK 16
-
-/* bit numbers of reset control register */
-#define SYS_CTRL_RST_SCU 0
-#define SYS_CTRL_RST_COPRO 1
-#define SYS_CTRL_RST_ARM0 2
-#define SYS_CTRL_RST_ARM1 3
-#define SYS_CTRL_RST_USBHS 4
-#define SYS_CTRL_RST_USBHSPHYA 5
-#define SYS_CTRL_RST_MACA 6
-#define SYS_CTRL_RST_MAC SYS_CTRL_RST_MACA
-#define SYS_CTRL_RST_PCIEA 7
-#define SYS_CTRL_RST_SGDMA 8
-#define SYS_CTRL_RST_CIPHER 9
-#define SYS_CTRL_RST_DDR 10
-#define SYS_CTRL_RST_SATA 11
-#define SYS_CTRL_RST_SATA_LINK 12
-#define SYS_CTRL_RST_SATA_PHY 13
-#define SYS_CTRL_RST_PCIEPHY 14
-#define SYS_CTRL_RST_STATIC 15
-#define SYS_CTRL_RST_GPIO 16
-#define SYS_CTRL_RST_UART1 17
-#define SYS_CTRL_RST_UART2 18
-#define SYS_CTRL_RST_MISC 19
-#define SYS_CTRL_RST_I2S 20
-#define SYS_CTRL_RST_SD 21
-#define SYS_CTRL_RST_MACB 22
-#define SYS_CTRL_RST_PCIEB 23
-#define SYS_CTRL_RST_VIDEO 24
-#define SYS_CTRL_RST_DDR_PHY 25
-#define SYS_CTRL_RST_USBHSPHYB 26
-#define SYS_CTRL_RST_USBDEV 27
-#define SYS_CTRL_RST_ARMDBG 29
-#define SYS_CTRL_RST_PLLA 30
-#define SYS_CTRL_RST_PLLB 31
-
-static inline void reset_block(int block, int reset)
-{
- u32 reg;
- if (reset)
- reg = SYS_CTRL_RST_SET_CTRL;
- else
- reg = SYS_CTRL_RST_CLR_CTRL;
-
- writel(BIT(block), reg);
-}
-
-static inline void enable_clock(int block)
-{
- writel(BIT(block), SYS_CTRL_CLK_SET_CTRL);
-}
-
-static inline void disable_clock(int block)
-{
- writel(BIT(block), SYS_CTRL_CLK_CLR_CTRL);
-}
-
-int plla_set_config(int idx);
-
-#endif /* _NAS782X_CLOCK_H */
+++ /dev/null
-#ifndef _NAS782X_CPU_H
-#define _NAS782X_CPU_H
-
-#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
-#include <asm/types.h>
-#include <asm/io.h>
-#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
-
-#include <asm/arch/hardware.h>
-#include <asm/arch/timer.h>
-
-#ifndef __KERNEL_STRICT_NAMES
-#ifndef __ASSEMBLY__
-
-#define BIT(x) (1 << (x))
-
-/* fix "implicit declaration of function" warnning */
-void *memalign(size_t alignment, size_t bytes);
-void free(void* mem);
-void *malloc(size_t bytes);
-void *calloc(size_t n, size_t elem_size);
-
-#endif /* __ASSEMBLY__ */
-#endif /* __KERNEL_STRICT_NAMES */
-
-#endif /* _NAS782X_CPU_H */
+++ /dev/null
-#ifndef _NAS782X_HARDWARE_H
-#define _NAS782X_HARDWARE_H
-
-/* Core addresses */
-#define USB_HOST_BASE 0x40200000
-#define MACA_BASE 0x40400000
-#define MACB_BASE 0x40800000
-#define MAC_BASE MACA_BASE
-#define STATIC_CS0_BASE 0x41000000
-#define STATIC_CS1_BASE 0x41400000
-#define STATIC_CONTROL_BASE 0x41C00000
-#define SATA_DATA_BASE 0x42000000 /* non-functional, DMA just needs an address */
-#define GPIO_1_BASE 0x44000000
-#define GPIO_2_BASE 0x44100000
-#define UART_1_BASE 0x44200000
-#define UART_2_BASE 0x44300000
-#define SYS_CONTROL_BASE 0x44e00000
-#define SEC_CONTROL_BASE 0x44f00000
-#define RPSA_BASE 0x44400000
-#define RPSC_BASE 0x44500000
-#define DDR_BASE 0x44700000
-
-#define SATA_BASE 0x45900000
-#define SATA_0_REGS_BASE 0x45900000
-#define SATA_1_REGS_BASE 0x45910000
-#define SATA_DMA_REGS_BASE 0x459a0000
-#define SATA_SGDMA_REGS_BASE 0x459b0000
-#define SATA_HOST_REGS_BASE 0x459e0000
-
-#endif /* _NAS782X_HARDWARE_H */
+++ /dev/null
-#ifndef _NAS782X_PINMUX_H
-#define _NAS782X_PINMUX_H
-
-#include <asm/arch/cpu.h>
-
-#define PINMUX_GPIO 0
-#define PINMUX_2 1
-#define PINMUX_3 2
-#define PINMUX_4 3
-#define PINMUX_DEBUG 4
-#define PINMUX_ALT 5
-
-#define PINMUX_BANK_MFA 0
-#define PINMUX_BANK_MFB 1
-
-/* System control multi-function pin function selection */
-#define PINMUX_SECONDARY_SEL 0x14
-#define PINMUX_TERTIARY_SEL 0x8c
-#define PINMUX_QUATERNARY_SEL 0x94
-#define PINMUX_DEBUG_SEL 0x9c
-#define PINMUX_ALTERNATIVE_SEL 0xa4
-#define PINMUX_PULLUP_SEL 0xac
-
-#define PINMUX_UARTA_SIN PINMUX_ALT
-#define PINMUX_UARTA_SOUT PINMUX_ALT
-
-#define PINMUX_STATIC_DATA0 PINMUX_2
-#define PINMUX_STATIC_DATA1 PINMUX_2
-#define PINMUX_STATIC_DATA2 PINMUX_2
-#define PINMUX_STATIC_DATA3 PINMUX_2
-#define PINMUX_STATIC_DATA4 PINMUX_2
-#define PINMUX_STATIC_DATA5 PINMUX_2
-#define PINMUX_STATIC_DATA6 PINMUX_2
-#define PINMUX_STATIC_DATA7 PINMUX_2
-#define PINMUX_STATIC_NWE PINMUX_2
-#define PINMUX_STATIC_NOE PINMUX_2
-#define PINMUX_STATIC_NCS PINMUX_2
-#define PINMUX_STATIC_ADDR18 PINMUX_2
-#define PINMUX_STATIC_ADDR19 PINMUX_2
-
-#define PINMUX_MACA_MDC PINMUX_2
-#define PINMUX_MACA_MDIO PINMUX_2
-
-extern void pinmux_set(int bank, int pin, int func);
-
-#endif /* _NAS782X_PINMUX_H */
+++ /dev/null
-#ifndef _NAS782X_SPL_H
-#define _NAS782X_SPL_H
-
-#include <asm/arch/cpu.h>
-
-#endif /* _NAS782X_SPL_H */
+++ /dev/null
-#ifndef _NAS782X_SYSCTL_H
-#define _NAS782X_SYSCTL_H
-
-#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
-#include <asm/types.h>
-#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
-
-#include <asm/arch/hardware.h>
-
-/**
- * System block reset and clock control
- */
-#define SYS_CTRL_PCI_STAT (SYS_CONTROL_BASE + 0x20)
-#define SYS_CTRL_CLK_SET_CTRL (SYS_CONTROL_BASE + 0x2C)
-#define SYS_CTRL_CLK_CLR_CTRL (SYS_CONTROL_BASE + 0x30)
-#define SYS_CTRL_RST_SET_CTRL (SYS_CONTROL_BASE + 0x34)
-#define SYS_CTRL_RST_CLR_CTRL (SYS_CONTROL_BASE + 0x38)
-#define SYS_CTRL_PLLSYS_CTRL (SYS_CONTROL_BASE + 0x48)
-#define SYS_CTRL_PLLSYS_KEY_CTRL (SYS_CONTROL_BASE + 0x6C)
-#define SYS_CTRL_GMAC_CTRL (SYS_CONTROL_BASE + 0x78)
-
-/* Scratch registers */
-#define SYS_CTRL_SCRATCHWORD0 (SYS_CONTROL_BASE + 0xc4)
-#define SYS_CTRL_SCRATCHWORD1 (SYS_CONTROL_BASE + 0xc8)
-#define SYS_CTRL_SCRATCHWORD2 (SYS_CONTROL_BASE + 0xcc)
-#define SYS_CTRL_SCRATCHWORD3 (SYS_CONTROL_BASE + 0xd0)
-
-#define SYS_CTRL_PLLA_CTRL0 (SYS_CONTROL_BASE + 0x1F0)
-#define SYS_CTRL_PLLA_CTRL1 (SYS_CONTROL_BASE + 0x1F4)
-#define SYS_CTRL_PLLA_CTRL2 (SYS_CONTROL_BASE + 0x1F8)
-#define SYS_CTRL_PLLA_CTRL3 (SYS_CONTROL_BASE + 0x1FC)
-
-#define SYS_CTRL_GMAC_AUTOSPEED 3
-#define SYS_CTRL_GMAC_RGMII 2
-#define SYS_CTRL_GMAC_SIMPLE_MUX 1
-#define SYS_CTRL_GMAC_CKEN_GTX 0
-
-#define SYS_CTRL_CKCTRL_CTRL_ADDR (SYS_CONTROL_BASE + 0x64)
-
-#define SYS_CTRL_CKCTRL_PCI_DIV_BIT 0
-#define SYS_CTRL_CKCTRL_SLOW_BIT 8
-
-
-#define SYS_CTRL_USBHSMPH_CTRL (SYS_CONTROL_BASE + 0x40)
-#define SYS_CTRL_USBHSMPH_STAT (SYS_CONTROL_BASE + 0x44)
-#define SYS_CTRL_REF300_DIV (SYS_CONTROL_BASE + 0xF8)
-#define SYS_CTRL_USBHSPHY_CTRL (SYS_CONTROL_BASE + 0x84)
-#define SYS_CTRL_USB_CTRL (SYS_CONTROL_BASE + 0x90)
-
-/* System control multi-function pin function selection */
-#define SYS_CTRL_SECONDARY_SEL (SYS_CONTROL_BASE + 0x14)
-#define SYS_CTRL_TERTIARY_SEL (SYS_CONTROL_BASE + 0x8c)
-#define SYS_CTRL_QUATERNARY_SEL (SYS_CONTROL_BASE + 0x94)
-#define SYS_CTRL_DEBUG_SEL (SYS_CONTROL_BASE + 0x9c)
-#define SYS_CTRL_ALTERNATIVE_SEL (SYS_CONTROL_BASE + 0xa4)
-#define SYS_CTRL_PULLUP_SEL (SYS_CONTROL_BASE + 0xac)
-
-/* Secure control multi-function pin function selection */
-#define SEC_CTRL_SECONDARY_SEL (SEC_CONTROL_BASE + 0x14)
-#define SEC_CTRL_TERTIARY_SEL (SEC_CONTROL_BASE + 0x8c)
-#define SEC_CTRL_QUATERNARY_SEL (SEC_CONTROL_BASE + 0x94)
-#define SEC_CTRL_DEBUG_SEL (SEC_CONTROL_BASE + 0x9c)
-#define SEC_CTRL_ALTERNATIVE_SEL (SEC_CONTROL_BASE + 0xa4)
-#define SEC_CTRL_PULLUP_SEL (SEC_CONTROL_BASE + 0xac)
-
-#define SEC_CTRL_COPRO_CTRL (SEC_CONTROL_BASE + 0x68)
-#define SEC_CTRL_SECURE_CTRL (SEC_CONTROL_BASE + 0x98)
-#define SEC_CTRL_LEON_DEBUG (SEC_CONTROL_BASE + 0xF0)
-#define SEC_CTRL_PLLB_DIV_CTRL (SEC_CONTROL_BASE + 0xF8)
-#define SEC_CTRL_PLLB_CTRL0 (SEC_CONTROL_BASE + 0x1F0)
-#define SEC_CTRL_PLLB_CTRL1 (SEC_CONTROL_BASE + 0x1F4)
-#define SEC_CTRL_PLLB_CTRL8 (SEC_CONTROL_BASE + 0x1F4)
-
-#define REF300_DIV_INT_SHIFT 8
-#define REF300_DIV_FRAC_SHIFT 0
-#define REF300_DIV_INT(val) ((val) << REF300_DIV_INT_SHIFT)
-#define REF300_DIV_FRAC(val) ((val) << REF300_DIV_FRAC_SHIFT)
-
-#define USBHSPHY_SUSPENDM_MANUAL_ENABLE 16
-#define USBHSPHY_SUSPENDM_MANUAL_STATE 15
-#define USBHSPHY_ATE_ESET 14
-#define USBHSPHY_TEST_DIN 6
-#define USBHSPHY_TEST_ADD 2
-#define USBHSPHY_TEST_DOUT_SEL 1
-#define USBHSPHY_TEST_CLK 0
-
-#define USB_CTRL_USBAPHY_CKSEL_SHIFT 5
-#define USB_CLK_XTAL0_XTAL1 (0 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
-#define USB_CLK_XTAL0 (1 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
-#define USB_CLK_INTERNAL (2 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
-
-#define USBAMUX_DEVICE BIT(4)
-
-#define USBPHY_REFCLKDIV_SHIFT 2
-#define USB_PHY_REF_12MHZ (0 << USBPHY_REFCLKDIV_SHIFT)
-#define USB_PHY_REF_24MHZ (1 << USBPHY_REFCLKDIV_SHIFT)
-#define USB_PHY_REF_48MHZ (2 << USBPHY_REFCLKDIV_SHIFT)
-
-#define USB_CTRL_USB_CKO_SEL_BIT 0
-
-#define USB_INT_CLK_XTAL 0
-#define USB_INT_CLK_REF300 2
-#define USB_INT_CLK_PLLB 3
-
-#define SYS_CTRL_GMAC_AUTOSPEED 3
-#define SYS_CTRL_GMAC_RGMII 2
-#define SYS_CTRL_GMAC_SIMPLE_MUX 1
-#define SYS_CTRL_GMAC_CKEN_GTX 0
-
-
-#define PLLB_ENSAT 3
-#define PLLB_OUTDIV 4
-#define PLLB_REFDIV 8
-#define PLLB_DIV_INT_SHIFT 8
-#define PLLB_DIV_FRAC_SHIFT 0
-#define PLLB_DIV_INT(val) ((val) << PLLB_DIV_INT_SHIFT)
-#define PLLB_DIV_FRAC(val) ((val) << PLLB_DIV_FRAC_SHIFT)
-
-#ifndef __KERNEL_STRICT_NAMES
-#ifndef __ASSEMBLY__
-
-#endif /* __ASSEMBLY__ */
-#endif /* __KERNEL_STRICT_NAMES */
-
-#endif /* _NAS782X_SYSCTL_H */
+++ /dev/null
-#ifndef _NAS782X_TIMER_H
-#define _NAS782X_TIMER_H
-
-#define TIMER1_BASE (RPSA_BASE + 0x200)
-#define TIMER2_BASE (RPSA_BASE + 0x220)
-
-#define TIMER_LOAD 0
-#define TIMER_CURR 4
-#define TIMER_CTRL 8
-#define TIMER_INTR 0x0C
-
-#define TIMER_PRESCALE_SHIFT 2
-#define TIMER_PRESCALE_1 0
-#define TIMER_PRESCALE_16 1
-#define TIMER_PRESCALE_256 2
-#define TIMER_MODE_SHIFT 6
-#define TIMER_MODE_FREE_RUNNING 0
-#define TIMER_MODE_PERIODIC 1
-#define TIMER_ENABLE_SHIFT 7
-#define TIMER_DISABLE 0
-#define TIMER_ENABLE 1
-
-#endif /* _NAS782X_TIMER_H */
+++ /dev/null
-if TARGET_OX820
-
-config SYS_CPU
- default "arm1136"
-
-config SYS_SOC
- default "nas782x"
-
-config SYS_BOARD
- default "ox820"
-
-config SYS_CONFIG_NAME
- default "ox820"
-
-endif
+++ /dev/null
-SHEEVAPLUG BOARD
-M: Daniel Golle <daniel@makrotopia.org>
-S: Maintained
-F: board/ox820/
-F: include/configs/ox820.h
-F: configs/ox820_defconfig
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += ox820.o
-obj-y += lowlevel_init.o
-
-obj-$(CONFIG_SPL_BUILD) += spl_start.o
-obj-$(CONFIG_SPL_BUILD) += ddr.o
-
+++ /dev/null
-/*******************************************************************
- *
- * File: ddr_oxsemi.c
- *
- * Description: Declarations for DDR routines and data objects
- *
- * Author: Julien Margetts
- *
- * Copyright: Oxford Semiconductor Ltd, 2009
- */
-#include <common.h>
-#include <asm/arch/clock.h>
-
-#include "ddr.h"
-
-typedef unsigned int UINT;
-
-// DDR TIMING PARAMETERS
-typedef struct {
- unsigned int holdoff_cmd_A;
- unsigned int holdoff_cmd_ARW;
- unsigned int holdoff_cmd_N;
- unsigned int holdoff_cmd_LM;
- unsigned int holdoff_cmd_R;
- unsigned int holdoff_cmd_W;
- unsigned int holdoff_cmd_PC;
- unsigned int holdoff_cmd_RF;
- unsigned int holdoff_bank_R;
- unsigned int holdoff_bank_W;
- unsigned int holdoff_dir_RW;
- unsigned int holdoff_dir_WR;
- unsigned int holdoff_FAW;
- unsigned int latency_CAS;
- unsigned int latency_WL;
- unsigned int recovery_WR;
- unsigned int width_update;
- unsigned int odt_offset;
- unsigned int odt_drive_all;
- unsigned int use_fixed_re;
- unsigned int delay_wr_to_re;
- unsigned int wr_slave_ratio;
- unsigned int rd_slave_ratio0;
- unsigned int rd_slave_ratio1;
-} T_DDR_TIMING_PARAMETERS;
-
-// DDR CONFIG PARAMETERS
-
-typedef struct {
- unsigned int ddr_mode;
- unsigned int width;
- unsigned int blocs;
- unsigned int banks8;
- unsigned int rams;
- unsigned int asize;
- unsigned int speed;
- unsigned int cmd_mode_wr_cl_bl;
-} T_DDR_CONFIG_PARAMETERS;
-
-//cmd_mode_wr_cl_bl
-//when SDR : cmd_mode_wr_cl_bl = 0x80200002 + (latency_CAS_RAM * 16) + (recovery_WR - 1) * 512; -- Sets write rec XX, CL=XX; BL=8
-//else cmd_mode_wr_cl_bl = 0x80200003 + (latency_CAS_RAM * 16) + (recovery_WR - 1) * 512; -- Sets write rec XX, CL=XX; BL=8
-
-// cmd_ bank_ dir_ lat_ rec_ width_ odt_ odt_ fix delay ratio
-// A F C update offset all re re_to_we w r0 r1
-// R L P R R W A A W W
-//Timing Parameters A W N M R W C F R W W R W S L R
-static const T_DDR_TIMING_PARAMETERS C_TP_DDR2_25E_CL5_1GB = { 4, 5, 0, 2, 4, 4,
- 5, 51, 23, 24, 9, 11, 18, 5, 4, 6, 3, 2, 0, 1, 2, 75, 56, 56 }; //elida device.
-static const T_DDR_TIMING_PARAMETERS C_TP_DDR2_25E_CL5_2GB = { 4, 5, 0, 2, 4, 4,
- 5, 79, 22, 24, 9, 11, 20, 5, 4, 6, 3, 2, 0, 1, 2, 75, 56, 56 };
-static const T_DDR_TIMING_PARAMETERS C_TP_DDR2_25_CL6_1GB = { 4, 5, 0, 2, 4, 4,
- 4, 51, 22, 26, 10, 12, 18, 6, 5, 6, 3, 2, 0, 1, 2, 75, 56, 56 }; // 400MHz, Speedgrade 25 timings (1Gb parts)
-
-// D B B R A S
-// D W L K A S P
-//Config Parameters R D C 8 M Z D CMD_MODE
-//static const T_DDR_CONFIG_PARAMETERS C_CP_DDR2_25E_CL5 = { 2,16, 1, 0, 1, 32,25,0x80200A53}; // 64 MByte
-static const T_DDR_CONFIG_PARAMETERS C_CP_DDR2_25E_CL5 = { 2, 16, 1, 1, 1, 64,
- 25, 0x80200A53 }; // 128 MByte
-static const T_DDR_CONFIG_PARAMETERS C_CP_DDR2_25_CL6 = { 2, 16, 1, 1, 1, 128,
- 25, 0x80200A63 }; // 256 MByte
-
-static void ddr_phy_poll_until_locked(void)
-{
- volatile UINT reg_tmp = 0;
- volatile UINT locked = 0;
-
- //Extra read to put in delay before starting to poll...
- reg_tmp = *(volatile UINT *) C_DDR_REG_PHY2; // read
-
- //POLL C_DDR_PHY2_REG register until clock and flock
- //!!! Ideally have a timeout on this.
- while (locked == 0) {
- reg_tmp = *(volatile UINT *) C_DDR_REG_PHY2; // read
-
- //locked when bits 30 and 31 are set
- if (reg_tmp & 0xC0000000) {
- locked = 1;
- }
- }
-}
-
-static void ddr_poll_until_not_busy(void)
-{
- volatile UINT reg_tmp = 0;
- volatile UINT busy = 1;
-
- //Extra read to put in delay before starting to poll...
- reg_tmp = *(volatile UINT *) C_DDR_STAT_REG; // read
-
- //POLL DDR_STAT register until no longer busy
- //!!! Ideally have a timeout on this.
- while (busy == 1) {
- reg_tmp = *(volatile UINT *) C_DDR_STAT_REG; // read
-
- //when bit 31 is clear - core is no longer busy
- if ((reg_tmp & 0x80000000) == 0x00000000) {
- busy = 0;
- }
- }
-}
-
-static void ddr_issue_command(int commmand)
-{
- *(volatile UINT *) C_DDR_CMD_REG = commmand;
- ddr_poll_until_not_busy();
-}
-
-static void ddr_timing_initialisation(
- const T_DDR_TIMING_PARAMETERS *ddr_timing_parameters)
-{
- volatile UINT reg_tmp = 0;
- /* update the DDR controller registers for timing parameters */
- reg_tmp = (ddr_timing_parameters->holdoff_cmd_A << 0);
- reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_ARW << 4);
- reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_N << 8);
- reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_LM << 12);
- reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_R << 16);
- reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_W << 20);
- reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_cmd_PC << 24);
- *(volatile UINT *) C_DDR_REG_TIMING0 = reg_tmp;
-
- reg_tmp = (ddr_timing_parameters->holdoff_cmd_RF << 0);
- reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_bank_R << 8);
- reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_bank_W << 16);
- reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_dir_RW << 24);
- reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_dir_WR << 28);
- *(volatile UINT *) C_DDR_REG_TIMING1 = reg_tmp;
-
- reg_tmp = (ddr_timing_parameters->latency_CAS << 0);
- reg_tmp = reg_tmp + (ddr_timing_parameters->latency_WL << 4);
- reg_tmp = reg_tmp + (ddr_timing_parameters->holdoff_FAW << 8);
- reg_tmp = reg_tmp + (ddr_timing_parameters->width_update << 16);
- reg_tmp = reg_tmp + (ddr_timing_parameters->odt_offset << 21);
- reg_tmp = reg_tmp + (ddr_timing_parameters->odt_drive_all << 24);
-
- *(volatile UINT *) C_DDR_REG_TIMING2 = reg_tmp;
-
- /* Program the timing parameters in the PHY too */
- reg_tmp = (ddr_timing_parameters->use_fixed_re << 16)
- | (ddr_timing_parameters->delay_wr_to_re << 8)
- | (ddr_timing_parameters->latency_WL << 4)
- | (ddr_timing_parameters->latency_CAS << 0);
-
- *(volatile UINT *) C_DDR_REG_PHY_TIMING = reg_tmp;
-
- reg_tmp = ddr_timing_parameters->wr_slave_ratio;
-
- *(volatile UINT *) C_DDR_REG_PHY_WR_RATIO = reg_tmp;
-
- reg_tmp = ddr_timing_parameters->rd_slave_ratio0;
- reg_tmp += ddr_timing_parameters->rd_slave_ratio1 << 8;
-
- *(volatile UINT *) C_DDR_REG_PHY_RD_RATIO = reg_tmp;
-
-}
-
-static void ddr_normal_initialisation(
- const T_DDR_CONFIG_PARAMETERS *ddr_config_parameters, int mhz)
-{
- int i;
- volatile UINT tmp = 0;
- volatile UINT reg_tmp = 0;
- volatile UINT emr_cmd = 0;
- UINT refresh;
-
- //Total size of memory in Mbits...
- tmp = ddr_config_parameters->rams * ddr_config_parameters->asize
- * ddr_config_parameters->width;
- //Deduce value to program into DDR_CFG register...
- switch (tmp) {
- case 16:
- reg_tmp = 0x00020000 * 1;
- break;
- case 32:
- reg_tmp = 0x00020000 * 2;
- break;
- case 64:
- reg_tmp = 0x00020000 * 3;
- break;
- case 128:
- reg_tmp = 0x00020000 * 4;
- break;
- case 256:
- reg_tmp = 0x00020000 * 5;
- break;
- case 512:
- reg_tmp = 0x00020000 * 6;
- break;
- case 1024:
- reg_tmp = 0x00020000 * 7;
- break;
- case 2048:
- reg_tmp = 0x00020000 * 8;
- break;
- default:
- reg_tmp = 0; //forces sims not to work if badly configured
- }
-
- //Memory width
- tmp = ddr_config_parameters->rams * ddr_config_parameters->width;
- switch (tmp) {
- case 8:
- reg_tmp = reg_tmp + 0x00400000;
- break;
- case 16:
- reg_tmp = reg_tmp + 0x00200000;
- break;
- case 32:
- reg_tmp = reg_tmp + 0x00000000;
- break;
- default:
- reg_tmp = 0; //forces sims not to work if badly configured
- }
-
- //Setup DDR Mode
- switch (ddr_config_parameters->ddr_mode) {
- case 0:
- reg_tmp = reg_tmp + 0x00000000;
- break; //SDR
- case 1:
- reg_tmp = reg_tmp + 0x40000000;
- break; //DDR
- case 2:
- reg_tmp = reg_tmp + 0x80000000;
- break; //DDR2
- default:
- reg_tmp = 0; //forces sims not to work if badly configured
- }
-
- //Setup Banks
- if (ddr_config_parameters->banks8 == 1) {
- reg_tmp = reg_tmp + 0x00800000;
- }
-
- //Program DDR_CFG register...
- *(volatile UINT *) C_DDR_CFG_REG = reg_tmp;
-
- //Configure PHY0 reg - se_mode is bit 1,
- //needs to be 1 for DDR (single_ended drive)
- switch (ddr_config_parameters->ddr_mode) {
- case 0:
- reg_tmp = 2 + (0 << 4);
- break; //SDR
- case 1:
- reg_tmp = 2 + (4 << 4);
- break; //DDR
- case 2:
- reg_tmp = 0 + (4 << 4);
- break; //DDR2
- default:
- reg_tmp = 0;
- }
-
- //Program DDR_PHY0 register...
- *(volatile UINT *) C_DDR_REG_PHY0 = reg_tmp;
-
- //Read DDR_PHY* registers to exercise paths for vcd
- reg_tmp = *(volatile UINT *) C_DDR_REG_PHY3;
- reg_tmp = *(volatile UINT *) C_DDR_REG_PHY2;
- reg_tmp = *(volatile UINT *) C_DDR_REG_PHY1;
- reg_tmp = *(volatile UINT *) C_DDR_REG_PHY0;
-
- //Start up sequences - Different dependant on DDR mode
- switch (ddr_config_parameters->ddr_mode) {
- case 2: //DDR2
- //Start-up sequence: follows procedure described in Micron datasheet.
- //start up DDR PHY DLL
- reg_tmp = 0x00022828; // dll on, start point and inc = h28
- *(volatile UINT *) C_DDR_REG_PHY2 = reg_tmp;
-
- reg_tmp = 0x00032828; // start on, dll on, start point and inc = h28
- *(volatile UINT *) C_DDR_REG_PHY2 = reg_tmp;
-
- ddr_phy_poll_until_locked();
-
- udelay(200); //200us
-
- //Startup SDRAM...
- //!!! Software: CK should be running for 200us before wake-up
- ddr_issue_command( C_CMD_WAKE_UP);
- ddr_issue_command( C_CMD_NOP);
- ddr_issue_command( C_CMD_PRECHARGE_ALL);
- ddr_issue_command( C_CMD_DDR2_EMR2);
- ddr_issue_command( C_CMD_DDR2_EMR3);
-
- emr_cmd = C_CMD_DDR2_EMR1 + C_CMD_ODT_75 + C_CMD_REDUCED_DRIVE
- + C_CMD_ENABLE_DLL;
-
- ddr_issue_command(emr_cmd);
- //Sets CL=3; BL=8 but also reset DLL to trigger a DLL initialisation...
- udelay(1); //1us
- ddr_issue_command(
- ddr_config_parameters->cmd_mode_wr_cl_bl
- + C_CMD_RESET_DLL);
- udelay(1); //1us
-
- //!!! Software: Wait 200 CK cycles before...
- //for(i=1; i<=2; i++) {
- ddr_issue_command(C_CMD_PRECHARGE_ALL);
- // !!! Software: Wait here at least 8 CK cycles
- //}
- //need a wait here to ensure PHY DLL lock before the refresh is issued
- udelay(1); //1us
- for (i = 1; i <= 2; i++) {
- ddr_issue_command( C_CMD_AUTO_REFRESH);
- //!!! Software: Wait here at least 8 CK cycles to satify tRFC
- udelay(1); //1us
- }
- //As before but without 'RESET_DLL' bit set...
- ddr_issue_command(ddr_config_parameters->cmd_mode_wr_cl_bl);
- udelay(1); //1us
- // OCD commands
- ddr_issue_command(emr_cmd + C_CMD_MODE_DDR2_OCD_DFLT);
- ddr_issue_command(emr_cmd + C_CMD_MODE_DDR2_OCD_EXIT);
- break;
-
- default:
- break; //Do nothing
- }
-
- //Enable auto-refresh
-
- // 8192 Refreshes required every 64ms, so maximum refresh period is 7.8125 us
- // We have a 400 MHz DDR clock (2.5ns period) so max period is 3125 cycles
- // Our core now does 8 refreshes in a go, so we multiply this period by 8
-
- refresh = (64000 * mhz) / 8192; // Refresh period in clocks
-
- reg_tmp = *(volatile UINT *) C_DDR_CFG_REG; // read
-#ifdef BURST_REFRESH_ENABLE
- reg_tmp |= C_CFG_REFRESH_ENABLE | (refresh * 8);
- reg_tmp |= C_CFG_BURST_REFRESH_ENABLE;
-#else
- reg_tmp |= C_CFG_REFRESH_ENABLE | (refresh * 1);
- reg_tmp &= ~C_CFG_BURST_REFRESH_ENABLE;
-#endif
- *(volatile UINT *) C_DDR_CFG_REG = reg_tmp;
-
- //Verify register contents
- reg_tmp = *(volatile UINT *) C_DDR_REG_PHY2; // read
- //printf("Warning XXXXXXXXXXXXXXXXXXXXXX - get bad read data from C_DDR_PHY2_REG, though it looks OK on bus XXXXXXXXXXXXXXXXXX");
- //TBD Check_data (read_data, dll_reg, "Error: bad C_DDR_PHY2_REG read", tb_pass);
- reg_tmp = *(volatile UINT *) C_DDR_CFG_REG; // read
- //TBD Check_data (read_data, cfg_reg, "Error: bad DDR_CFG read", tb_pass);
-
- //disable optimised wrapping
- if (ddr_config_parameters->ddr_mode == 2) {
- reg_tmp = 0xFFFF0000;
- *(volatile UINT *) C_DDR_REG_IGNORE = reg_tmp;
- }
-
- //enable midbuffer followon
- reg_tmp = *(volatile UINT *) C_DDR_ARB_REG; // read
- reg_tmp = 0xFFFF0000 | reg_tmp;
- *(volatile UINT *) C_DDR_ARB_REG = reg_tmp;
-
- // Enable write behind coherency checking for all clients
-
- reg_tmp = 0xFFFF0000;
- *(volatile UINT *) C_DDR_AHB4_REG = reg_tmp;
-
- //Wait for 200 clock cycles for SDRAM DLL to lock...
- udelay(1); //1us
-}
-
-// Function used to Setup DDR core
-
-void ddr_setup(int mhz)
-{
- static const T_DDR_TIMING_PARAMETERS *ddr_timing_parameters =
- &C_TP_DDR2_25_CL6_1GB;
- static const T_DDR_CONFIG_PARAMETERS *ddr_config_parameters =
- &C_CP_DDR2_25_CL6;
-
- //Bring core out of Reset
- *(volatile UINT *) C_DDR_BLKEN_REG = C_BLKEN_DDR_ON;
-
- //DDR TIMING INITIALISTION
- ddr_timing_initialisation(ddr_timing_parameters);
-
- //DDR NORMAL INITIALISATION
- ddr_normal_initialisation(ddr_config_parameters, mhz);
-
- // route all writes through one client
- *(volatile UINT *) C_DDR_TRANSACTION_ROUTING = (0
- << DDR_ROUTE_CPU0_INSTR_SHIFT)
- | (1 << DDR_ROUTE_CPU0_RDDATA_SHIFT)
- | (3 << DDR_ROUTE_CPU0_WRDATA_SHIFT)
- | (2 << DDR_ROUTE_CPU1_INSTR_SHIFT)
- | (3 << DDR_ROUTE_CPU1_RDDATA_SHIFT)
- | (3 << DDR_ROUTE_CPU1_WRDATA_SHIFT);
-
- //Bring all clients out of reset
- *(volatile UINT *) C_DDR_BLKEN_REG = C_BLKEN_DDR_ON + 0x0000FFFF;
-
-}
-
-void set_ddr_timing(unsigned int w, unsigned int i)
-{
- unsigned int reg;
- unsigned int wnow = 16;
- unsigned int inow = 32;
-
- /* reset all timing controls to known value (31) */
- writel(DDR_PHY_TIMING_W_RST | DDR_PHY_TIMING_I_RST, DDR_PHY_TIMING);
- writel(DDR_PHY_TIMING_W_RST | DDR_PHY_TIMING_I_RST | DDR_PHY_TIMING_CK,
- DDR_PHY_TIMING);
- writel(DDR_PHY_TIMING_W_RST | DDR_PHY_TIMING_I_RST, DDR_PHY_TIMING);
-
- /* step up or down read delay to the requested value */
- while (wnow != w) {
- if (wnow < w) {
- reg = DDR_PHY_TIMING_INC;
- wnow++;
- } else {
- reg = 0;
- wnow--;
- }
- writel(DDR_PHY_TIMING_W_CE | reg, DDR_PHY_TIMING);
- writel(DDR_PHY_TIMING_CK | DDR_PHY_TIMING_W_CE | reg,
- DDR_PHY_TIMING);
- writel(DDR_PHY_TIMING_W_CE | reg, DDR_PHY_TIMING);
- }
-
- /* now write delay */
- while (inow != i) {
- if (inow < i) {
- reg = DDR_PHY_TIMING_INC;
- inow++;
- } else {
- reg = 0;
- inow--;
- }
- writel(DDR_PHY_TIMING_I_CE | reg, DDR_PHY_TIMING);
- writel(DDR_PHY_TIMING_CK | DDR_PHY_TIMING_I_CE | reg,
- DDR_PHY_TIMING);
- writel(DDR_PHY_TIMING_I_CE | reg, DDR_PHY_TIMING);
- }
-}
-
-//Function used to Setup SDRAM in DDR/SDR mode
-void init_ddr(int mhz)
-{
- /* start clocks */
- enable_clock(SYS_CTRL_CLK_DDRPHY);
- enable_clock(SYS_CTRL_CLK_DDR);
- enable_clock(SYS_CTRL_CLK_DDRCK);
-
- /* bring phy and core out of reset */
- reset_block(SYS_CTRL_RST_DDR_PHY, 0);
- reset_block(SYS_CTRL_RST_DDR, 0);
-
- /* DDR runs at half the speed of the CPU */
- ddr_setup(mhz >> 1);
- return;
-}
+++ /dev/null
-/*******************************************************************
-*
-* File: ddr_oxsemi.h
-*
-* Description: Declarations for DDR routines and data objects
-*
-* Author: Julien Margetts
-*
-* Copyright: Oxford Semiconductor Ltd, 2009
-*/
-
-void ddr_oxsemi_setup(int mhz);
-
-/* define to refresh in bursts of 8 */
-#define BURST_REFRESH_ENABLE
-
-#define DDR_BASE 0x44700000
-
-#define C_DDR_CFG_REG (DDR_BASE + 0x00)
-#define C_CFG_DDR 0x80000000
-#define C_CFG_SDR 0x00000000
-#define C_CFG_WIDTH8 0x00200000
-#define C_CFG_WIDTH16 0x00100000
-#define C_CFG_WIDTH32 0x00000000
-#define C_CFG_SIZE_FACTOR 0x00020000
-#define C_CFG_REFRESH_ENABLE 0x00010000
-#define C_CFG_BURST_REFRESH_ENABLE 0x01000000
-#define C_CFG_SIZE(x) (x << 17)
-#define CFG_SIZE_2MB 1
-#define CFG_SIZE_4MB 2
-#define CFG_SIZE_8MB 3
-#define CFG_SIZE_16MB 4
-#define CFG_SIZE_32MB 5
-#define CFG_SIZE_64MB 6
-#define CFG_SIZE_128MB 7
-
-#define C_DDR_BLKEN_REG (DDR_BASE + 0x04)
-#define C_BLKEN_DDR_ON 0x80000000
-
-#define C_DDR_STAT_REG (DDR_BASE + 0x08)
-
-#define C_DDR_CMD_REG (DDR_BASE + 0x0C)
-#define C_CMD_SEND_COMMAND (1UL << 31) | (1 << 21) // RAS/CAS/WE/CS all low(active), CKE High, indicates
-#define C_CMD_WAKE_UP 0x80FC0000 // Asserts CKE
-#define C_CMD_MODE_SDR 0x80200022 // Sets CL=2 BL=4
-#define C_CMD_MODE_DDR 0x80200063 // Sets CL=2.5 BL=8
-#define C_CMD_RESET_DLL 0x00000100 // A8=1 Use in conjunction with C_CMD_MODE_DDR
-#define C_CMD_PRECHARGE_ALL 0x80280400
-#define C_CMD_AUTO_REFRESH 0x80240000
-#define C_CMD_SELF_REFRESH 0x80040000 // As AUTO-REFRESH but with CKE low
-#define C_CMD_NOP 0x803C0000 // NOP just to insert guaranteed delay
-#define C_CMD_DDR2_EMR1 0x80210000 // Load extended mode register 1 with zeros (for init), CKE still set
-//#define C_CMD_DDR2_EMR1 0x80210400 // Load extended mode register 1 with zeros (for init), CKE still set
-#define C_CMD_ENABLE_DLL 0x00000000 // Values used in conjuction with C_CMD_DDR2_EMR1
-#define C_CMD_DISABLE_DLL 0x00000001
-#define C_CMD_REDUCED_DRIVE 0x00000002
-#define C_CMD_ODT_DISABLED 0x00000000
-#define C_CMD_ODT_50 0x00000044
-#define C_CMD_ODT_75 0x00000004
-#define C_CMD_ODT_150 0x00000040
-#define C_CMD_MODE_DDR2_OCD_DFLT 0x00000380
-#define C_CMD_MODE_DDR2_OCD_EXIT 0x00000000
-
-#define C_CMD_DDR2_EMR2 0x80220000 // Load extended mode register 2 with zeros (for init), CKE still set
-#define C_CMD_DDR2_EMR3 0x80230000 // Load extended mode register 3 with zeros (for init), CKE still set
-
-#define C_DDR_AHB_REG (DDR_BASE + 0x10)
-#define C_AHB_NO_RCACHES 0xFFFF0000
-#define C_AHB_FLUSH_ALL_RCACHES 0x0000FFFF
-#define C_AHB_FLUSH_AHB0_RCACHE 0x00000001
-#define C_AHB_FLUSH_AHB1_RCACHE 0x00000002
-
-#define C_DDR_DLL_REG (DDR_BASE + 0x14)
-#define C_DLL_DISABLED 0x00000000
-#define C_DLL_MANUAL 0x80000000
-#define C_DLL_AUTO_OFFSET 0xA0000000
-#define C_DLL_AUTO_IN_REFRESH 0xC0000000
-#define C_DLL_AUTOMATIC 0xE0000000
-
-#define C_DDR_MON_REG (DDR_BASE + 0x18)
-#define C_MON_ALL 0x00000010
-#define C_MON_CLIENT 0x00000000
-
-#define C_DDR_DIAG_REG (DDR_BASE + 0x1C)
-#define C_DDR_DIAG2_REG (DDR_BASE + 0x20)
-
-#define C_DDR_IOC_REG (DDR_BASE + 0x24)
-#define C_DDR_IOC_PWR_DWN (1 << 10)
-#define C_DDR_IOC_SEL_SSTL (1 << 9)
-#define C_DDR_IOC_CK_DRIVE(x) ((x) << 6)
-#define C_DDR_IOC_DQ_DRIVE(x) ((x) << 3)
-#define C_DDR_IOC_XX_DRIVE(x) ((x) << 0)
-
-#define C_DDR_ARB_REG (DDR_BASE + 0x28)
-#define C_DDR_ARB_MIDBUF (1 << 4)
-#define C_DDR_ARB_LRUBANK (1 << 3)
-#define C_DDR_ARB_REQAGE (1 << 2)
-#define C_DDR_ARB_DATDIR (1 << 1)
-#define C_DDR_ARB_DATDIR_NC (1 << 0)
-
-#define C_TOP_ADDRESS_BIT_TEST 22
-#define C_MEM_BASE C_SDRAM_BASE
-
-#define C_MEM_TEST_BASE 0
-#define C_MEM_TEST_LEN 1920
-#define C_MAX_RAND_ACCESS_LEN 16
-
-#define C_DDR_REG_IGNORE (DDR_BASE + 0x2C)
-#define C_DDR_AHB4_REG (DDR_BASE + 0x44)
-
-#define C_DDR_REG_TIMING0 (DDR_BASE + 0x34)
-#define C_DDR_REG_TIMING1 (DDR_BASE + 0x38)
-#define C_DDR_REG_TIMING2 (DDR_BASE + 0x3C)
-
-#define C_DDR_REG_PHY0 (DDR_BASE + 0x48)
-#define C_DDR_REG_PHY1 (DDR_BASE + 0x4C)
-#define C_DDR_REG_PHY2 (DDR_BASE + 0x50)
-#define C_DDR_REG_PHY3 (DDR_BASE + 0x54)
-
-#define C_DDR_REG_GENERIC (DDR_BASE + 0x60)
-
-#define C_OXSEMI_DDRC_SIGNATURE 0x054415AA
-
-#define DDR_PHY_BASE (DDR_BASE + 0x80000)
-#define DDR_PHY_TIMING (DDR_PHY_BASE + 0x48)
-#define DDR_PHY_TIMING_CK (1 << 12)
-#define DDR_PHY_TIMING_INC (1 << 13)
-#define DDR_PHY_TIMING_W_CE (1 << 14)
-#define DDR_PHY_TIMING_W_RST (1 << 15)
-#define DDR_PHY_TIMING_I_CE (1 << 16)
-#define DDR_PHY_TIMING_I_RST (1 << 17)
-
-#define C_DDR_REG_PHY_TIMING (DDR_PHY_BASE + 0x50)
-#define C_DDR_REG_PHY_WR_RATIO (DDR_PHY_BASE + 0x74)
-#define C_DDR_REG_PHY_RD_RATIO (DDR_PHY_BASE + 0x78)
-
-#define C_DDR_TRANSACTION_ROUTING (DDR_PHY_BASE + 0xC8)
-#define DDR_ROUTE_CPU0_INSTR_SHIFT 0
-#define DDR_ROUTE_CPU0_RDDATA_SHIFT 4
-#define DDR_ROUTE_CPU0_WRDATA_SHIFT 6
-#define DDR_ROUTE_CPU1_INSTR_SHIFT 8
-#define DDR_ROUTE_CPU1_RDDATA_SHIFT 12
-#define DDR_ROUTE_CPU1_WRDATA_SHIFT 14
-
-unsigned int ddrc_signature(void);
-void set_ddr_timing(unsigned int w, unsigned int i);
-int pause(unsigned int us);
-void set_ddr_sel(int val);
+++ /dev/null
-#include <config.h>
-#ifndef CONFIG_SPL_BUILD
-
-.globl lowlevel_init
-lowlevel_init:
- /*
- * Copy exception table to relocated address in internal SRAM
- */
- ldr r0, src /* Address of exception table in flash */
- ldr r1, dest /* Relocated address of exception table */
- ldmia r0!, {r3-r10} /* Copy exception table and jump values from */
- stmia r1!, {r3-r10} /* FLASH to relocated address */
- ldmia r0!, {r3-r10}
- stmia r1!, {r3-r10}
- mov pc, lr
-
-src: .word CONFIG_SYS_TEXT_BASE
-dest: .word CONFIG_SRAM_BASE
-
-#endif
\ No newline at end of file
+++ /dev/null
-#include <common.h>
-#include <spl.h>
-#include <phy.h>
-#include <netdev.h>
-#include <ide.h>
-#include <nand.h>
-#include <asm/arch/spl.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/sysctl.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_SPL_BUILD
-
-#ifdef DEBUG
-#define DILIGENCE (1048576/4)
-static int test_memory(u32 memory)
-{
- volatile u32 *read;
- volatile u32 *write;
- const u32 INIT_PATTERN = 0xAA55AA55;
- const u32 INC_PATTERN = 0x01030507;
- u32 pattern;
- int check;
- int i;
-
- check = 0;
- read = write = (volatile u32 *) memory;
- pattern = INIT_PATTERN;
- for (i = 0; i < DILIGENCE; i++) {
- *write++ = pattern;
- pattern += INC_PATTERN;
- }
- puts("testing\n");
- pattern = INIT_PATTERN;
- for (i = 0; i < DILIGENCE; i++) {
- check += (pattern == *read++) ? 1 : 0;
- pattern += INC_PATTERN;
- }
- return (check == DILIGENCE) ? 0 : -1;
-}
-#endif
-
-void uart_init(void)
-{
- /* Reset UART1 */
- reset_block(SYS_CTRL_RST_UART1, 1);
- udelay(100);
- reset_block(SYS_CTRL_RST_UART1, 0);
- udelay(100);
-
- /* Setup pin mux'ing for UART1 */
- pinmux_set(PINMUX_BANK_MFA, 30, PINMUX_UARTA_SIN);
- pinmux_set(PINMUX_BANK_MFA, 31, PINMUX_UARTA_SOUT);
-}
-
-extern void init_ddr(int mhz);
-
-void board_inithw(void)
-{
- int plla_freq;
-#ifdef DEBUG
- int i;
-#endif /* DEBUG */
-
- timer_init();
- uart_init();
- preloader_console_init();
-
- plla_freq = plla_set_config(CONFIG_PLLA_FREQ_MHZ);
- init_ddr(plla_freq);
-
-#ifdef DEBUG
- if(test_memory(CONFIG_SYS_SDRAM_BASE)) {
- puts("memory test failed\n");
- } else {
- puts("memory test done\n");
- }
-#endif /* DEBUG */
-#ifdef CONFIG_SPL_BSS_DRAM_START
- extern char __bss_dram_start[];
- extern char __bss_dram_end[];
- memset(&__bss_dram_start, 0, __bss_dram_end - __bss_dram_start);
-#endif
-}
-
-void board_init_f(ulong dummy)
-{
- /* Set the stack pointer. */
- asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK));
-
- /* Clear the BSS. */
- memset(__bss_start, 0, __bss_end - __bss_start);
-
- /* Set global data pointer. */
- gd = &gdata;
-
- board_inithw();
-
- board_init_r(NULL, 0);
-}
-
-u32 spl_boot_device(void)
-{
- return CONFIG_SPL_BOOT_DEVICE;
-}
-
-#ifdef CONFIG_SPL_BLOCK_SUPPORT
-void spl_block_device_init(void)
-{
- ide_init();
-}
-#endif
-
-#ifdef CONFIG_SPL_OS_BOOT
-int spl_start_uboot(void)
-{
- /* break into full u-boot on 'c' */
- return (serial_tstc() && serial_getc() == 'c');
-}
-#endif
-
-void spl_display_print(void)
-{
- /* print a hint, so that we will not use the wrong SPL by mistake */
- puts(" Boot device: " BOOT_DEVICE_TYPE "\n" );
-}
-
-void lowlevel_init(void)
-{
-}
-
-#ifdef USE_DL_PREFIX
-/* quick and dirty memory allocation */
-static ulong next_mem = CONFIG_SPL_MALLOC_START;
-
-void *memalign(size_t alignment, size_t bytes)
-{
- ulong mem = ALIGN(next_mem, alignment);
-
- next_mem = mem + bytes;
-
- if (next_mem > CONFIG_SYS_SDRAM_BASE + CONFIG_MIN_SDRAM_SIZE) {
- printf("spl: out of memory\n");
- hang();
- }
-
- return (void *)mem;
-}
-
-void free(void* mem)
-{
-}
-#endif
-
-#endif /* CONFIG_SPL_BUILD */
-
-int board_early_init_f(void)
-{
- return 0;
-}
-
-#define STATIC_CTL_BANK0 (STATIC_CONTROL_BASE + 4)
-#define STATIC_READ_CYCLE_SHIFT 0
-#define STATIC_DELAYED_OE (1 << 7)
-#define STATIC_WRITE_CYCLE_SHIFT 8
-#define STATIC_WRITE_PULSE_SHIFT 16
-#define STATIC_WRITE_BURST_EN (1 << 23)
-#define STATIC_TURN_AROUND_SHIFT 24
-#define STATIC_BUFFER_PRESENT (1 << 28)
-#define STATIC_READ_BURST_EN (1 << 29)
-#define STATIC_BUS_WIDTH8 (0 << 30)
-#define STATIC_BUS_WIDTH16 (1 << 30)
-#define STATIC_BUS_WIDTH32 (2 << 30)
-
-void nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
- struct nand_chip *this = mtd->priv;
- unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
-
- if (ctrl & NAND_CTRL_CHANGE) {
- nandaddr &= ~(BIT(NAND_ALE_ADDR_PIN) | BIT(NAND_CLE_ADDR_PIN));
- if (ctrl & NAND_CLE)
- nandaddr |= BIT(NAND_CLE_ADDR_PIN);
- else if (ctrl & NAND_ALE)
- nandaddr |= BIT(NAND_ALE_ADDR_PIN);
- this->IO_ADDR_W = (void __iomem *) nandaddr;
- }
-
- if (cmd != NAND_CMD_NONE)
- writeb(cmd, (void __iomem *) nandaddr);
-}
-
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOOT_FROM_NAND)
-
-int nand_dev_ready(struct mtd_info *mtd)
-{
- struct nand_chip *chip = mtd->priv;
-
- udelay(chip->chip_delay);
-
- return 1;
-}
-
-void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
-{
- int i;
- struct nand_chip *chip = mtd->priv;
-
- for (i = 0; i < len; i++)
- buf[i] = readb(chip->IO_ADDR_R);
-}
-
-void nand_dev_reset(struct nand_chip *chip)
-{
- writeb(NAND_CMD_RESET, chip->IO_ADDR_W + BIT(NAND_CLE_ADDR_PIN));
- udelay(chip->chip_delay);
- writeb(NAND_CMD_STATUS, chip->IO_ADDR_W + BIT(NAND_CLE_ADDR_PIN));
- while (!(readb(chip->IO_ADDR_R) & NAND_STATUS_READY)) {
- ;
- }
-}
-
-#else
-
-#define nand_dev_reset(chip) /* framework will reset the chip anyway */
-#define nand_read_buf NULL /* framework will provide a default one */
-#define nand_dev_ready NULL /* dev_ready is optional */
-
-#endif
-
-int board_nand_init(struct nand_chip *chip)
-{
- /* Block reset Static core */
- reset_block(SYS_CTRL_RST_STATIC, 1);
- reset_block(SYS_CTRL_RST_STATIC, 0);
-
- /* Enable clock to Static core */
- enable_clock(SYS_CTRL_CLK_STATIC);
-
- /* enable flash support on static bus.
- * Enable static bus onto GPIOs, only CS0 */
- pinmux_set(PINMUX_BANK_MFA, 12, PINMUX_STATIC_DATA0);
- pinmux_set(PINMUX_BANK_MFA, 13, PINMUX_STATIC_DATA1);
- pinmux_set(PINMUX_BANK_MFA, 14, PINMUX_STATIC_DATA2);
- pinmux_set(PINMUX_BANK_MFA, 15, PINMUX_STATIC_DATA3);
- pinmux_set(PINMUX_BANK_MFA, 16, PINMUX_STATIC_DATA4);
- pinmux_set(PINMUX_BANK_MFA, 17, PINMUX_STATIC_DATA5);
- pinmux_set(PINMUX_BANK_MFA, 18, PINMUX_STATIC_DATA6);
- pinmux_set(PINMUX_BANK_MFA, 19, PINMUX_STATIC_DATA7);
-
- pinmux_set(PINMUX_BANK_MFA, 20, PINMUX_STATIC_NWE);
- pinmux_set(PINMUX_BANK_MFA, 21, PINMUX_STATIC_NOE);
- pinmux_set(PINMUX_BANK_MFA, 22, PINMUX_STATIC_NCS);
- pinmux_set(PINMUX_BANK_MFA, 23, PINMUX_STATIC_ADDR18);
- pinmux_set(PINMUX_BANK_MFA, 24, PINMUX_STATIC_ADDR19);
-
- /* Setup the static bus CS0 to access FLASH */
-
- writel((0x3f << STATIC_READ_CYCLE_SHIFT)
- | (0x3f << STATIC_WRITE_CYCLE_SHIFT)
- | (0x1f << STATIC_WRITE_PULSE_SHIFT)
- | (0x03 << STATIC_TURN_AROUND_SHIFT) |
- STATIC_BUS_WIDTH16,
- STATIC_CTL_BANK0);
-
- chip->cmd_ctrl = nand_hwcontrol;
- chip->ecc.mode = NAND_ECC_SOFT;
- chip->chip_delay = 30;
- chip->dev_ready = nand_dev_ready;
- chip->read_buf = nand_read_buf;
-
- nand_dev_reset(chip);
-
- return 0;
-}
-
-int board_init(void)
-{
- gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
- gd->bd->bi_arch_number = MACH_TYPE_OXNAS;
-
- /* assume uart is already initialized by SPL */
-
-#if defined(CONFIG_START_IDE)
- puts("IDE: ");
- ide_init();
-#endif
-
- return 0;
-}
-
-/* copied from board/evb64260/sdram_init.c */
-/*
- * Check memory range for valid RAM. A simple memory test determines
- * the actually available RAM size between addresses `base' and
- * `base + maxsize'. Some (not all) hardware errors are detected:
- * - short between address lines
- * - short between data lines
- */
-static long int dram_size (long int *base, long int maxsize)
-{
- volatile long int *addr, *b = base;
- long int cnt, val, save1, save2;
-
-#define STARTVAL (CONFIG_MIN_SDRAM_SIZE / 2) /* start test at half size */
- for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long);
- cnt <<= 1) {
- addr = base + cnt; /* pointer arith! */
-
- save1 = *addr; /* save contents of addr */
- save2 = *b; /* save contents of base */
-
- *addr = cnt; /* write cnt to addr */
- *b = 0; /* put null at base */
-
- /* check at base address */
- if ((*b) != 0) {
- *addr = save1; /* restore *addr */
- *b = save2; /* restore *b */
- return (0);
- }
- val = *addr; /* read *addr */
-
- *addr = save1;
- *b = save2;
-
- if (val != cnt) {
- /* fix boundary condition.. STARTVAL means zero */
- if (cnt == STARTVAL / sizeof (long))
- cnt = 0;
- return (cnt * sizeof (long));
- }
- }
- return maxsize;
-}
-
-int dram_init(void)
-{
- gd->ram_size = dram_size((long int *)CONFIG_SYS_SDRAM_BASE,
- CONFIG_MAX_SDRAM_SIZE);
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
- u32 value;
-
- /* set the pin multiplexers to enable talking to Ethernent Phys */
- pinmux_set(PINMUX_BANK_MFA, 3, PINMUX_MACA_MDC);
- pinmux_set(PINMUX_BANK_MFA, 4, PINMUX_MACA_MDIO);
-
- // Ensure the MAC block is properly reset
- reset_block(SYS_CTRL_RST_MAC, 1);
- udelay(10);
- reset_block(SYS_CTRL_RST_MAC, 0);
-
- // Enable the clock to the MAC block
- enable_clock(SYS_CTRL_CLK_MAC);
-
- value = readl(SYS_CTRL_GMAC_CTRL);
- /* Use simple mux for 25/125 Mhz clock switching */
- value |= BIT(SYS_CTRL_GMAC_SIMPLE_MUX);
- /* Enable GMII_GTXCLK to follow GMII_REFCLK - required for gigabit PHY */
- value |= BIT(SYS_CTRL_GMAC_CKEN_GTX);
- /* set auto tx speed */
- value |= BIT(SYS_CTRL_GMAC_AUTOSPEED);
-
- writel(value, SYS_CTRL_GMAC_CTRL);
-
- return designware_initialize(MAC_BASE, PHY_INTERFACE_MODE_RGMII);
-}
-
+++ /dev/null
-.section .init
-.globl _spl_start
-_spl_start:
- b _start
- b _start+0x4
- b _start+0x8
- b _start+0xc
- b _start+0x10
- b _start+0x14
- b _start+0x18
- b _start+0x1c
- .space 0x30 - (. - _spl_start)
- .ascii "BOOT" /* 0x30 signature*/
- .word 0x50 /* 0x34 header size itself */
- .word 0 /* 0x38 */
- .word 0x5000f000 /* boot report location */
- .word _start /* 0x40 */
-
-main_crc_size: .word code_size /* 0x44 filled by linker */
-main_crc: .word 0 /* 0x48 fill later */
-header_crc: .word 0 /* 0x4C header crc*/
+++ /dev/null
-/*
- * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
- * on behalf of DENX Software Engineering GmbH
- *
- * January 2004 - Changed to support H4 device
- * Copyright (c) 2004-2008 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-MEMORY
-{
- sram (rwx) : ORIGIN = CONFIG_SPL_TEXT_BASE, LENGTH = CONFIG_SPL_MAX_SIZE
- dram : ORIGIN = CONFIG_SPL_BSS_DRAM_START, LENGTH = CONFIG_SPL_BSS_DRAM_SIZE
-}
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_spl_start)
-SECTIONS
-{
- .text.0 :
- {
- *(.init*)
- }
-
-
- /* Start of the rest of the SPL */
- code_start = . ;
-
- .text.1 :
- {
- *(.text*)
- }
-
- . = ALIGN(4);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(4);
- .data : {
- *(.data*)
- }
-
- . = ALIGN(4);
-
- __image_copy_end = .;
- code_size = . - code_start;
-
- .rel.dyn : {
- __rel_dyn_start = .;
- *(.rel*)
- __rel_dyn_end = .;
- }
-
- . = ALIGN(0x800);
-
- _end = .;
-
- .bss.sram __rel_dyn_start (OVERLAY) : {
- __bss_start = .;
- *(.bss.stdio_devices)
- *(.bss.serial_current)
- . = ALIGN(4);
- __bss_end = .;
- }
-
- .bss : {
- __bss_dram_start = .;
- *(.bss*)
- __bss_dram_end = .;
- } > dram
-
- /DISCARD/ : { *(.bss*) }
- /DISCARD/ : { *(.dynsym) }
- /DISCARD/ : { *(.dynstr*) }
- /DISCARD/ : { *(.dynsym*) }
- /DISCARD/ : { *(.dynamic*) }
- /DISCARD/ : { *(.hash*) }
- /DISCARD/ : { *(.plt*) }
- /DISCARD/ : { *(.interp*) }
- /DISCARD/ : { *(.gnu*) }
-}
+++ /dev/null
-/*
- * (c) Copyright 2011 by Tigris Elektronik GmbH
- *
- * Author:
- * Maximilian Schwerin <mvs@tigris.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-#include <command.h>
-#include <environment.h>
-#include <linux/stddef.h>
-#include <malloc.h>
-#include <search.h>
-#include <errno.h>
-#include <ext4fs.h>
-
-char *env_name_spec = "EXT4";
-
-env_t *env_ptr;
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int env_init(void)
-{
- /* use default */
- gd->env_addr = (ulong)&default_environment[0];
- gd->env_valid = 1;
-
- return 0;
-}
-
-#ifdef CONFIG_CMD_SAVEENV
-int saveenv(void)
-{
- env_t env_new;
- ssize_t len;
- char *res;
- block_dev_desc_t *dev_desc = NULL;
- int dev = EXT4_ENV_DEVICE;
- int part = EXT4_ENV_PART;
- int err;
-
- res = (char *)&env_new.data;
- len = hexport_r(&env_htab, '\0', 0, &res, ENV_SIZE, 0, NULL);
- if (len < 0) {
- error("Cannot export environment: errno = %d\n", errno);
- return 1;
- }
-
- dev_desc = get_dev(EXT4_ENV_INTERFACE, dev);
- if (dev_desc == NULL) {
- printf("Failed to find %s%d\n",
- EXT4_ENV_INTERFACE, dev);
- return 1;
- }
-
- err = ext4_register_device(dev_desc, part);
- if (err) {
- printf("Failed to register %s%d:%d\n",
- EXT4_ENV_INTERFACE, dev, part);
- return 1;
- }
-
- env_new.crc = crc32(0, env_new.data, ENV_SIZE);
- err = ext4fs_write(EXT4_ENV_FILE, (void *)&env_new, sizeof(env_t));
- ext4fs_close();
- if (err == -1) {
- printf("\n** Unable to write \"%s\" from %s%d:%d **\n",
- EXT4_ENV_FILE, EXT4_ENV_INTERFACE, dev, part);
- return 1;
- }
-
- puts("done\n");
- return 0;
-}
-#endif /* CONFIG_CMD_SAVEENV */
-
-void env_relocate_spec(void)
-{
- char buf[CONFIG_ENV_SIZE];
- block_dev_desc_t *dev_desc = NULL;
- int dev = EXT4_ENV_DEVICE;
- int part = EXT4_ENV_PART;
- int err;
-
- dev_desc = get_dev(EXT4_ENV_INTERFACE, dev);
- if (dev_desc == NULL) {
- printf("Failed to find %s%d\n",
- EXT4_ENV_INTERFACE, dev);
- set_default_env(NULL);
- return;
- }
-
- err = ext4_register_device(dev_desc, part);
- if (err) {
- printf("Failed to register %s%d:%d\n",
- EXT4_ENV_INTERFACE, dev, part);
- set_default_env(NULL);
- return;
- }
-
- err = ext4_read_file(EXT4_ENV_FILE, (uchar *)&buf, 0, CONFIG_ENV_SIZE);
- ext4fs_close();
-
- if (err == -1) {
- printf("\n** Unable to read \"%s\" from %s%d:%d **\n",
- EXT4_ENV_FILE, EXT4_ENV_INTERFACE, dev, part);
- set_default_env(NULL);
- return;
- }
-
- env_import(buf, 1);
-}
+++ /dev/null
-/*
- * (C) Copyright 2013
- *
- * Ma Haijun <mahaijuns@gmail.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-#include <spl.h>
-#include <asm/u-boot.h>
-#include <asm/utils.h>
-#include <version.h>
-#include <part.h>
-#include <fat.h>
-#include <ext4fs.h>
-
-/* should be implemented by board */
-extern void spl_block_device_init(void);
-
-block_dev_desc_t * spl_get_block_device(void)
-{
- block_dev_desc_t * device;
-
- spl_block_device_init();
-
- device = get_dev(CONFIG_SPL_BLOCKDEV_INTERFACE, CONFIG_SPL_BLOCKDEV_ID);
- if (!device) {
- printf("blk device %s%d not exists\n",
- CONFIG_SPL_BLOCKDEV_INTERFACE,
- CONFIG_SPL_BLOCKDEV_ID);
- hang();
- }
-
- return device;
-}
-
-#ifdef CONFIG_SPL_FAT_SUPPORT
-static int block_load_image_fat(const char *filename)
-{
- int err;
- struct image_header *header;
-
- header = (struct image_header *)(CONFIG_SYS_TEXT_BASE -
- sizeof(struct image_header));
-
- err = file_fat_read(filename, header, sizeof(struct image_header));
- if (err <= 0)
- goto end;
-
- spl_parse_image_header(header);
-
- err = file_fat_read(filename, (u8 *)spl_image.load_addr, 0);
-
-end:
- if (err <= 0)
- printf("spl: error reading image %s, err - %d\n",
- filename, err);
-
- return (err <= 0);
-}
-
-#ifdef CONFIG_SPL_OS_BOOT
-static int block_load_image_fat_os(void)
-{
- int err;
-
- err = file_fat_read(CONFIG_SPL_FAT_LOAD_ARGS_NAME,
- (void *)CONFIG_SYS_SPL_ARGS_ADDR, 0);
- if (err <= 0) {
- return -1;
- }
-
- return block_load_image_fat(CONFIG_SPL_FAT_LOAD_KERNEL_NAME);
-}
-#endif
-
-void spl_block_load_image(void)
-{
- int err;
- block_dev_desc_t * device;
-
- device = spl_get_block_device();
- err = fat_register_device(device, CONFIG_BLOCKDEV_FAT_BOOT_PARTITION);
- if (err) {
- printf("spl: fat register err - %d\n", err);
- hang();
- }
-#ifdef CONFIG_SPL_OS_BOOT
- if (spl_start_uboot() || block_load_image_fat_os())
-#endif
- {
- err = block_load_image_fat(CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME);
- if (err)
- hang();
- }
-}
-#elif defined(CONFIG_SPL_EXT4_SUPPORT) /* end CONFIG_SPL_FAT_SUPPORT */
-static int block_load_image_ext4(const char *filename)
-{
- int err;
- struct image_header *header;
-
- header = (struct image_header *)(CONFIG_SYS_TEXT_BASE -
- sizeof(struct image_header));
-
- err = ext4_read_file(filename, header, 0, sizeof(struct image_header));
- if (err <= 0)
- goto end;
-
- spl_parse_image_header(header);
-
- err = ext4_read_file(filename, (u8 *)spl_image.load_addr, 0, 0);
-
-end:
- return (err <= 0);
-}
-
-#ifdef CONFIG_SPL_OS_BOOT
-static int block_load_image_ext4_os(void)
-{
- int err;
-
- err = ext4_read_file(CONFIG_SPL_EXT4_LOAD_ARGS_NAME,
- (void *)CONFIG_SYS_SPL_ARGS_ADDR, 0, 0);
- if (err <= 0) {
- return -1;
- }
-
- return block_load_image_ext4(CONFIG_SPL_EXT4_LOAD_KERNEL_NAME);
-}
-#endif
-
-void spl_block_load_image(void)
-{
- int err;
- block_dev_desc_t * device;
-
- device = spl_get_block_device();
- err = ext4_register_device(device, CONFIG_BLOCKDEV_EXT4_BOOT_PARTITION);
- if (err) {
- hang();
- }
-#ifdef CONFIG_SPL_OS_BOOT
- if (spl_start_uboot() || block_load_image_ext4_os())
-#endif
- {
- err = block_load_image_ext4(CONFIG_SPL_EXT4_LOAD_PAYLOAD_NAME);
- if (err)
- hang();
- }
-}
-#else /* end CONFIG_SPL_EXT4_SUPPORT */
-static int block_load_image_raw(block_dev_desc_t * device, lbaint_t sector)
-{
- int n;
- u32 image_size_sectors;
- struct image_header *header;
-
- header = (struct image_header *)(CONFIG_SYS_TEXT_BASE -
- sizeof(struct image_header));
-
- /* read image header to find the image size & load address */
- n = device->block_read(device->dev, sector, 1, header);
-
- if (n != 1) {
- printf("spl: blk read err\n");
- return 1;
- }
-
- spl_parse_image_header(header);
-
- /* convert size to sectors - round up */
- image_size_sectors = (spl_image.size + 512 - 1) / 512;
- n = device->block_read(device->dev, sector, image_size_sectors,
- (void *)spl_image.load_addr);
-
- if (n != image_size_sectors) {
- printf("spl: blk read err\n");
- return 1;
- }
- return 0;
-}
-
-#ifdef CONFIG_SPL_OS_BOOT
-static int block_load_image_raw_os(block_dev_desc_t * device)
-{
- int n;
-
- n = device->block_read(device->dev, CONFIG_SYS_BLOCK_RAW_MODE_ARGS_SECTOR,
- CONFIG_SYS_BLOCK_RAW_MODE_ARGS_SECTORS,
- (u32 *)CONFIG_SYS_SPL_ARGS_ADDR);
- /* flush cache after read */
- flush_cache(addr, CONFIG_SYS_BLOCK_RAW_MODE_ARGS_SECTORS * 512);
-
- if (n != CONFIG_SYS_BLOCK_RAW_MODE_ARGS_SECTORS) {
- printf("args blk read error\n");
- return -1;
- }
-
- return block_load_image_raw(device, CONFIG_SYS_BLOCK_RAW_MODE_KERNEL_SECTOR);
-}
-#endif
-
-void spl_block_load_image(void)
-{
- int err;
- block_dev_desc_t * device;
-
- device = spl_get_block_device();
-#ifdef CONFIG_SPL_OS_BOOT
- if (spl_start_uboot() || block_load_image_raw_os(device))
-#endif
- {
- err = block_load_image_raw(device,
- CONFIG_SYS_BLOCK_RAW_MODE_U_BOOT_SECTOR);
- if (err)
- hang();
- }
-}
-#endif /* CONFIG_SPL_FAT_SUPPORT */
+++ /dev/null
-CONFIG_ARM=y
-CONFIG_OX820=y
-CONFIG_TARGET_OX820=y
+++ /dev/null
-/*
- * (C) Copyright 2005
- * Oxford Semiconductor Ltd
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,`
- * MA 02111-1307 USA
- */
-#include <common.h>
-#include <asm/arch/clock.h>
-
-/**
- * SATA related definitions
- */
-#define ATA_PORT_CTL 0
-#define ATA_PORT_FEATURE 1
-#define ATA_PORT_NSECT 2
-#define ATA_PORT_LBAL 3
-#define ATA_PORT_LBAM 4
-#define ATA_PORT_LBAH 5
-#define ATA_PORT_DEVICE 6
-#define ATA_PORT_COMMAND 7
-
-/* The offsets to the SATA registers */
-#define SATA_ORB1_OFF 0
-#define SATA_ORB2_OFF 1
-#define SATA_ORB3_OFF 2
-#define SATA_ORB4_OFF 3
-#define SATA_ORB5_OFF 4
-
-#define SATA_FIS_ACCESS 11
-#define SATA_INT_STATUS_OFF 12 /* Read only */
-#define SATA_INT_CLR_OFF 12 /* Write only */
-#define SATA_INT_ENABLE_OFF 13 /* Read only */
-#define SATA_INT_ENABLE_SET_OFF 13 /* Write only */
-#define SATA_INT_ENABLE_CLR_OFF 14 /* Write only */
-#define SATA_VERSION_OFF 15
-#define SATA_CONTROL_OFF 23
-#define SATA_COMMAND_OFF 24
-#define SATA_PORT_CONTROL_OFF 25
-#define SATA_DRIVE_CONTROL_OFF 26
-
-/* The offsets to the link registers that are access in an asynchronous manner */
-#define SATA_LINK_DATA 28
-#define SATA_LINK_RD_ADDR 29
-#define SATA_LINK_WR_ADDR 30
-#define SATA_LINK_CONTROL 31
-
-/* SATA interrupt status register fields */
-#define SATA_INT_STATUS_EOC_RAW_BIT ( 0 + 16)
-#define SATA_INT_STATUS_ERROR_BIT ( 2 + 16)
-#define SATA_INT_STATUS_EOADT_RAW_BIT ( 1 + 16)
-
-/* SATA core command register commands */
-#define SATA_CMD_WRITE_TO_ORB_REGS 2
-#define SATA_CMD_WRITE_TO_ORB_REGS_NO_COMMAND 4
-
-#define SATA_CMD_BUSY_BIT 7
-
-#define SATA_SCTL_CLR_ERR 0x00000316UL
-
-#define SATA_LBAL_BIT 0
-#define SATA_LBAM_BIT 8
-#define SATA_LBAH_BIT 16
-#define SATA_HOB_LBAH_BIT 24
-#define SATA_DEVICE_BIT 24
-#define SATA_NSECT_BIT 0
-#define SATA_HOB_NSECT_BIT 8
-#define SATA_LBA32_BIT 0
-#define SATA_LBA40_BIT 8
-#define SATA_FEATURE_BIT 16
-#define SATA_COMMAND_BIT 24
-#define SATA_CTL_BIT 24
-
-/* ATA status (7) register field definitions */
-#define ATA_STATUS_BSY_BIT 7
-#define ATA_STATUS_DRDY_BIT 6
-#define ATA_STATUS_DF_BIT 5
-#define ATA_STATUS_DRQ_BIT 3
-#define ATA_STATUS_ERR_BIT 0
-
-/* ATA device (6) register field definitions */
-#define ATA_DEVICE_FIXED_MASK 0xA0
-#define ATA_DEVICE_DRV_BIT 4
-#define ATA_DEVICE_DRV_NUM_BITS 1
-#define ATA_DEVICE_LBA_BIT 6
-
-/* ATA Command register initiated commands */
-#define ATA_CMD_INIT 0x91
-#define ATA_CMD_IDENT 0xEC
-
-#define SATA_STD_ASYNC_REGS_OFF 0x20
-#define SATA_SCR_STATUS 0
-#define SATA_SCR_ERROR 1
-#define SATA_SCR_CONTROL 2
-#define SATA_SCR_ACTIVE 3
-#define SATA_SCR_NOTIFICAION 4
-
-#define SATA_BURST_BUF_FORCE_EOT_BIT 0
-#define SATA_BURST_BUF_DATA_INJ_ENABLE_BIT 1
-#define SATA_BURST_BUF_DIR_BIT 2
-#define SATA_BURST_BUF_DATA_INJ_END_BIT 3
-#define SATA_BURST_BUF_FIFO_DIS_BIT 4
-#define SATA_BURST_BUF_DIS_DREQ_BIT 5
-#define SATA_BURST_BUF_DREQ_BIT 6
-
-#define SATA_OPCODE_MASK 0x3
-
-#define SATA_DMA_CHANNEL 0
-
-#define DMA_CTRL_STATUS (0x0)
-#define DMA_BASE_SRC_ADR (0x4)
-#define DMA_BASE_DST_ADR (0x8)
-#define DMA_BYTE_CNT (0xC)
-#define DMA_CURRENT_SRC_ADR (0x10)
-#define DMA_CURRENT_DST_ADR (0x14)
-#define DMA_CURRENT_BYTE_CNT (0x18)
-#define DMA_INTR_ID (0x1C)
-#define DMA_INTR_CLEAR_REG (DMA_CURRENT_SRC_ADR)
-
-#define DMA_CALC_REG_ADR(channel, register) ((volatile u32*)(DMA_BASE + ((channel) << 5) + (register)))
-
-#define DMA_CTRL_STATUS_FAIR_SHARE_ARB (1 << 0)
-#define DMA_CTRL_STATUS_IN_PROGRESS (1 << 1)
-#define DMA_CTRL_STATUS_SRC_DREQ_MASK (0x0000003C)
-#define DMA_CTRL_STATUS_SRC_DREQ_SHIFT (2)
-#define DMA_CTRL_STATUS_DEST_DREQ_MASK (0x000003C0)
-#define DMA_CTRL_STATUS_DEST_DREQ_SHIFT (6)
-#define DMA_CTRL_STATUS_INTR (1 << 10)
-#define DMA_CTRL_STATUS_NXT_FREE (1 << 11)
-#define DMA_CTRL_STATUS_RESET (1 << 12)
-#define DMA_CTRL_STATUS_DIR_MASK (0x00006000)
-#define DMA_CTRL_STATUS_DIR_SHIFT (13)
-#define DMA_CTRL_STATUS_SRC_ADR_MODE (1 << 15)
-#define DMA_CTRL_STATUS_DEST_ADR_MODE (1 << 16)
-#define DMA_CTRL_STATUS_TRANSFER_MODE_A (1 << 17)
-#define DMA_CTRL_STATUS_TRANSFER_MODE_B (1 << 18)
-#define DMA_CTRL_STATUS_SRC_WIDTH_MASK (0x00380000)
-#define DMA_CTRL_STATUS_SRC_WIDTH_SHIFT (19)
-#define DMA_CTRL_STATUS_DEST_WIDTH_MASK (0x01C00000)
-#define DMA_CTRL_STATUS_DEST_WIDTH_SHIFT (22)
-#define DMA_CTRL_STATUS_PAUSE (1 << 25)
-#define DMA_CTRL_STATUS_INTERRUPT_ENABLE (1 << 26)
-#define DMA_CTRL_STATUS_SOURCE_ADDRESS_FIXED (1 << 27)
-#define DMA_CTRL_STATUS_DESTINATION_ADDRESS_FIXED (1 << 28)
-#define DMA_CTRL_STATUS_STARVE_LOW_PRIORITY (1 << 29)
-#define DMA_CTRL_STATUS_INTR_CLEAR_ENABLE (1 << 30)
-
-#define DMA_BYTE_CNT_MASK ((1 << 21) - 1)
-#define DMA_BYTE_CNT_WR_EOT_MASK (1 << 30)
-#define DMA_BYTE_CNT_RD_EOT_MASK (1 << 31)
-#define DMA_BYTE_CNT_BURST_MASK (1 << 28)
-
-#define MAKE_FIELD(value, num_bits, bit_num) (((value) & ((1 << (num_bits)) - 1)) << (bit_num))
-
-typedef enum oxnas_dma_mode {
- OXNAS_DMA_MODE_FIXED, OXNAS_DMA_MODE_INC
-} oxnas_dma_mode_t;
-
-typedef enum oxnas_dma_direction {
- OXNAS_DMA_TO_DEVICE, OXNAS_DMA_FROM_DEVICE
-} oxnas_dma_direction_t;
-
-/* The available buses to which the DMA controller is attached */
-typedef enum oxnas_dma_transfer_bus {
- OXNAS_DMA_SIDE_A, OXNAS_DMA_SIDE_B
-} oxnas_dma_transfer_bus_t;
-
-/* Direction of data flow between the DMA controller's pair of interfaces */
-typedef enum oxnas_dma_transfer_direction {
- OXNAS_DMA_A_TO_A, OXNAS_DMA_B_TO_A, OXNAS_DMA_A_TO_B, OXNAS_DMA_B_TO_B
-} oxnas_dma_transfer_direction_t;
-
-/* The available data widths */
-typedef enum oxnas_dma_transfer_width {
- OXNAS_DMA_TRANSFER_WIDTH_8BITS,
- OXNAS_DMA_TRANSFER_WIDTH_16BITS,
- OXNAS_DMA_TRANSFER_WIDTH_32BITS
-} oxnas_dma_transfer_width_t;
-
-/* The mode of the DMA transfer */
-typedef enum oxnas_dma_transfer_mode {
- OXNAS_DMA_TRANSFER_MODE_SINGLE, OXNAS_DMA_TRANSFER_MODE_BURST
-} oxnas_dma_transfer_mode_t;
-
-/* The available transfer targets */
-typedef enum oxnas_dma_dreq {
- OXNAS_DMA_DREQ_SATA = 0, OXNAS_DMA_DREQ_MEMORY = 15
-} oxnas_dma_dreq_t;
-
-typedef struct oxnas_dma_device_settings {
- unsigned long address_;
- unsigned fifo_size_; // Chained transfers must take account of FIFO offset at end of previous transfer
- unsigned char dreq_;
- unsigned read_eot_ :1;
- unsigned read_final_eot_ :1;
- unsigned write_eot_ :1;
- unsigned write_final_eot_ :1;
- unsigned bus_ :1;
- unsigned width_ :2;
- unsigned transfer_mode_ :1;
- unsigned address_mode_ :1;
- unsigned address_really_fixed_ :1;
-} oxnas_dma_device_settings_t;
-
-static const int MAX_NO_ERROR_LOOPS = 100000; /* 1 second in units of 10uS */
-static const int MAX_DMA_XFER_LOOPS = 300000; /* 30 seconds in units of 100uS */
-static const int MAX_DMA_ABORT_LOOPS = 10000; /* 0.1 second in units of 10uS */
-static const int MAX_SRC_READ_LOOPS = 10000; /* 0.1 second in units of 10uS */
-static const int MAX_SRC_WRITE_LOOPS = 10000; /* 0.1 second in units of 10uS */
-static const int MAX_NOT_BUSY_LOOPS = 10000; /* 1 second in units of 100uS */
-
-/* The internal SATA drive on which we should attempt to find partitions */
-static volatile u32* sata_regs_base[2] = { (volatile u32*) SATA_0_REGS_BASE,
- (volatile u32*) SATA_1_REGS_BASE,
-
-};
-static u32 wr_sata_orb1[2] = { 0, 0 };
-static u32 wr_sata_orb2[2] = { 0, 0 };
-static u32 wr_sata_orb3[2] = { 0, 0 };
-static u32 wr_sata_orb4[2] = { 0, 0 };
-
-#ifdef CONFIG_LBA48
-/* need keeping a record of NSECT LBAL LBAM LBAH ide_outb values for lba48 support */
-#define OUT_HISTORY_BASE ATA_PORT_NSECT
-#define OUT_HISTORY_MAX ATA_PORT_LBAH
-static unsigned char out_history[2][OUT_HISTORY_MAX - OUT_HISTORY_BASE + 1] = {};
-#endif
-
-static oxnas_dma_device_settings_t oxnas_sata_dma_settings = { .address_ =
- SATA_DATA_BASE, .fifo_size_ = 16, .dreq_ = OXNAS_DMA_DREQ_SATA,
- .read_eot_ = 0, .read_final_eot_ = 1, .write_eot_ = 0,
- .write_final_eot_ = 1, .bus_ = OXNAS_DMA_SIDE_B, .width_ =
- OXNAS_DMA_TRANSFER_WIDTH_32BITS, .transfer_mode_ =
- OXNAS_DMA_TRANSFER_MODE_BURST, .address_mode_ =
- OXNAS_DMA_MODE_FIXED, .address_really_fixed_ = 0 };
-
-oxnas_dma_device_settings_t oxnas_ram_dma_settings = { .address_ = 0,
- .fifo_size_ = 0, .dreq_ = OXNAS_DMA_DREQ_MEMORY, .read_eot_ = 1,
- .read_final_eot_ = 1, .write_eot_ = 1, .write_final_eot_ = 1,
- .bus_ = OXNAS_DMA_SIDE_A, .width_ =
- OXNAS_DMA_TRANSFER_WIDTH_32BITS, .transfer_mode_ =
- OXNAS_DMA_TRANSFER_MODE_BURST, .address_mode_ =
- OXNAS_DMA_MODE_FIXED, .address_really_fixed_ = 1 };
-
-static void xfer_wr_shadow_to_orbs(int device)
-{
- *(sata_regs_base[device] + SATA_ORB1_OFF) = wr_sata_orb1[device];
- *(sata_regs_base[device] + SATA_ORB2_OFF) = wr_sata_orb2[device];
- *(sata_regs_base[device] + SATA_ORB3_OFF) = wr_sata_orb3[device];
- *(sata_regs_base[device] + SATA_ORB4_OFF) = wr_sata_orb4[device];
-}
-
-static inline void device_select(int device)
-{
- /* master/slave has no meaning to SATA core */
-}
-
-static int disk_present[CONFIG_SYS_IDE_MAXDEVICE];
-
-#include <ata.h>
-
-unsigned char ide_inb(int device, int port)
-{
- unsigned char val = 0;
-
- /* Only permit accesses to disks found to be present during ide_preinit() */
- if (!disk_present[device]) {
- return ATA_STAT_FAULT;
- }
-
- device_select(device);
-
- switch (port) {
- case ATA_PORT_CTL:
- val = (*(sata_regs_base[device] + SATA_ORB4_OFF)
- & (0xFFUL << SATA_CTL_BIT)) >> SATA_CTL_BIT;
- break;
- case ATA_PORT_FEATURE:
- val = (*(sata_regs_base[device] + SATA_ORB2_OFF)
- & (0xFFUL << SATA_FEATURE_BIT)) >> SATA_FEATURE_BIT;
- break;
- case ATA_PORT_NSECT:
- val = (*(sata_regs_base[device] + SATA_ORB2_OFF)
- & (0xFFUL << SATA_NSECT_BIT)) >> SATA_NSECT_BIT;
- break;
- case ATA_PORT_LBAL:
- val = (*(sata_regs_base[device] + SATA_ORB3_OFF)
- & (0xFFUL << SATA_LBAL_BIT)) >> SATA_LBAL_BIT;
- break;
- case ATA_PORT_LBAM:
- val = (*(sata_regs_base[device] + SATA_ORB3_OFF)
- & (0xFFUL << SATA_LBAM_BIT)) >> SATA_LBAM_BIT;
- break;
- case ATA_PORT_LBAH:
- val = (*(sata_regs_base[device] + SATA_ORB3_OFF)
- & (0xFFUL << SATA_LBAH_BIT)) >> SATA_LBAH_BIT;
- break;
- case ATA_PORT_DEVICE:
- val = (*(sata_regs_base[device] + SATA_ORB3_OFF)
- & (0xFFUL << SATA_HOB_LBAH_BIT)) >> SATA_HOB_LBAH_BIT;
- val |= (*(sata_regs_base[device] + SATA_ORB1_OFF)
- & (0xFFUL << SATA_DEVICE_BIT)) >> SATA_DEVICE_BIT;
- break;
- case ATA_PORT_COMMAND:
- val = (*(sata_regs_base[device] + SATA_ORB2_OFF)
- & (0xFFUL << SATA_COMMAND_BIT)) >> SATA_COMMAND_BIT;
- val |= ATA_STAT_DRQ;
- break;
- default:
- printf("ide_inb() Unknown port = %d\n", port);
- break;
- }
-
- // printf("inb: %d:%01x => %02x\n", device, port, val);
-
- return val;
-}
-
-/**
- * Possible that ATA status will not become no-error, so must have timeout
- * @returns An int which is zero on error
- */
-static inline int wait_no_error(int device)
-{
- int status = 0;
-
- /* Check for ATA core error */
- if (*(sata_regs_base[device] + SATA_INT_STATUS_OFF)
- & (1 << SATA_INT_STATUS_ERROR_BIT)) {
- printf("wait_no_error() SATA core flagged error\n");
- } else {
- int loops = MAX_NO_ERROR_LOOPS;
- do {
- /* Check for ATA device error */
- if (!(ide_inb(device, ATA_PORT_COMMAND)
- & (1 << ATA_STATUS_ERR_BIT))) {
- status = 1;
- break;
- }
- udelay(10);
- } while (--loops);
-
- if (!loops) {
- printf("wait_no_error() Timed out of wait for SATA no-error condition\n");
- }
- }
-
- return status;
-}
-
-/**
- * Expect SATA command to always finish, perhaps with error
- * @returns An int which is zero on error
- */
-static inline int wait_sata_command_not_busy(int device)
-{
- /* Wait for data to be available */
- int status = 0;
- int loops = MAX_NOT_BUSY_LOOPS;
- do {
- if (!(*(sata_regs_base[device] + SATA_COMMAND_OFF)
- & (1 << SATA_CMD_BUSY_BIT))) {
- status = 1;
- break;
- }
- udelay(100);
- } while (--loops);
-
- if (!loops) {
- printf("wait_sata_command_not_busy() Timed out of wait for SATA command to finish\n");
- }
-
- return status;
-}
-
-void ide_outb(int device, int port, unsigned char val)
-{
- typedef enum send_method {
- SEND_NONE, SEND_SIMPLE, SEND_CMD, SEND_CTL,
- } send_method_t;
-
- /* Only permit accesses to disks found to be present during ide_preinit() */
- if (!disk_present[device]) {
- return;
- }
-
- // printf("outb: %d:%01x <= %02x\n", device, port, val);
-
- device_select(device);
-
-#ifdef CONFIG_LBA48
- if (port >= OUT_HISTORY_BASE && port <= OUT_HISTORY_MAX) {
- out_history[0][port - OUT_HISTORY_BASE] =
- out_history[1][port - OUT_HISTORY_BASE];
- out_history[1][port - OUT_HISTORY_BASE] = val;
- }
-#endif
- send_method_t send_regs = SEND_NONE;
- switch (port) {
- case ATA_PORT_CTL:
- wr_sata_orb4[device] &= ~(0xFFUL << SATA_CTL_BIT);
- wr_sata_orb4[device] |= (val << SATA_CTL_BIT);
- send_regs = SEND_CTL;
- break;
- case ATA_PORT_FEATURE:
- wr_sata_orb2[device] &= ~(0xFFUL << SATA_FEATURE_BIT);
- wr_sata_orb2[device] |= (val << SATA_FEATURE_BIT);
- send_regs = SEND_SIMPLE;
- break;
- case ATA_PORT_NSECT:
- wr_sata_orb2[device] &= ~(0xFFUL << SATA_NSECT_BIT);
- wr_sata_orb2[device] |= (val << SATA_NSECT_BIT);
- send_regs = SEND_SIMPLE;
- break;
- case ATA_PORT_LBAL:
- wr_sata_orb3[device] &= ~(0xFFUL << SATA_LBAL_BIT);
- wr_sata_orb3[device] |= (val << SATA_LBAL_BIT);
- send_regs = SEND_SIMPLE;
- break;
- case ATA_PORT_LBAM:
- wr_sata_orb3[device] &= ~(0xFFUL << SATA_LBAM_BIT);
- wr_sata_orb3[device] |= (val << SATA_LBAM_BIT);
- send_regs = SEND_SIMPLE;
- break;
- case ATA_PORT_LBAH:
- wr_sata_orb3[device] &= ~(0xFFUL << SATA_LBAH_BIT);
- wr_sata_orb3[device] |= (val << SATA_LBAH_BIT);
- send_regs = SEND_SIMPLE;
- break;
- case ATA_PORT_DEVICE:
- wr_sata_orb1[device] &= ~(0xFFUL << SATA_DEVICE_BIT);
- wr_sata_orb1[device] |= (val << SATA_DEVICE_BIT);
- send_regs = SEND_SIMPLE;
- break;
- case ATA_PORT_COMMAND:
- wr_sata_orb2[device] &= ~(0xFFUL << SATA_COMMAND_BIT);
- wr_sata_orb2[device] |= (val << SATA_COMMAND_BIT);
- send_regs = SEND_CMD;
-#ifdef CONFIG_LBA48
- if (val == ATA_CMD_READ_EXT || val == ATA_CMD_WRITE_EXT)
- {
- /* fill high bytes of LBA48 && NSECT */
- wr_sata_orb2[device] &= ~(0xFFUL << SATA_HOB_NSECT_BIT);
- wr_sata_orb2[device] |=
- (out_history[0][ATA_PORT_NSECT - OUT_HISTORY_BASE] << SATA_HOB_NSECT_BIT);
-
- wr_sata_orb3[device] &= ~(0xFFUL << SATA_HOB_LBAH_BIT);
- wr_sata_orb3[device] |=
- (out_history[0][ATA_PORT_LBAL - OUT_HISTORY_BASE] << SATA_HOB_LBAH_BIT);
-
- wr_sata_orb4[device] &= ~(0xFFUL << SATA_LBA32_BIT);
- wr_sata_orb4[device] |=
- (out_history[0][ATA_PORT_LBAM - OUT_HISTORY_BASE] << SATA_LBA32_BIT);
-
- wr_sata_orb4[device] &= ~(0xFFUL << SATA_LBA40_BIT);
- wr_sata_orb4[device] |=
- (out_history[0][ATA_PORT_LBAH - OUT_HISTORY_BASE] << SATA_LBA40_BIT);
- }
-#endif
- break;
- default:
- printf("ide_outb() Unknown port = %d\n", port);
- }
-
- u32 command;
- switch (send_regs) {
- case SEND_CMD:
- wait_sata_command_not_busy(device);
- command = *(sata_regs_base[device] + SATA_COMMAND_OFF);
- command &= ~SATA_OPCODE_MASK;
- command |= SATA_CMD_WRITE_TO_ORB_REGS;
- xfer_wr_shadow_to_orbs(device);
- wait_sata_command_not_busy(device);
- *(sata_regs_base[device] + SATA_COMMAND_OFF) = command;
- if (!wait_no_error(device)) {
- printf("ide_outb() Wait for ATA no-error timed-out\n");
- }
- break;
- case SEND_CTL:
- wait_sata_command_not_busy(device);
- command = *(sata_regs_base[device] + SATA_COMMAND_OFF);
- command &= ~SATA_OPCODE_MASK;
- command |= SATA_CMD_WRITE_TO_ORB_REGS_NO_COMMAND;
- xfer_wr_shadow_to_orbs(device);
- wait_sata_command_not_busy(device);
- *(sata_regs_base[device] + SATA_COMMAND_OFF) = command;
- if (!wait_no_error(device)) {
- printf("ide_outb() Wait for ATA no-error timed-out\n");
- }
- break;
- default:
- break;
- }
-}
-
-static u32 encode_start(u32 ctrl_status)
-{
- return ctrl_status & ~DMA_CTRL_STATUS_PAUSE;
-}
-
-/* start a paused DMA transfer in channel 0 of the SATA DMA core */
-static void dma_start(void)
-{
- unsigned int reg;
- reg = readl(SATA_DMA_REGS_BASE + DMA_CTRL_STATUS);
- reg = encode_start(reg);
- writel(reg, SATA_DMA_REGS_BASE + DMA_CTRL_STATUS);
-}
-
-static unsigned long encode_control_status(
- oxnas_dma_device_settings_t* src_settings,
- oxnas_dma_device_settings_t* dst_settings)
-{
- unsigned long ctrl_status;
- oxnas_dma_transfer_direction_t direction;
-
- ctrl_status = DMA_CTRL_STATUS_PAUSE; // Paused
- ctrl_status |= DMA_CTRL_STATUS_FAIR_SHARE_ARB; // High priority
- ctrl_status |= (src_settings->dreq_ << DMA_CTRL_STATUS_SRC_DREQ_SHIFT); // Dreq
- ctrl_status |= (dst_settings->dreq_ << DMA_CTRL_STATUS_DEST_DREQ_SHIFT); // Dreq
- ctrl_status &= ~DMA_CTRL_STATUS_RESET; // !RESET
-
- // Use new interrupt clearing register
- ctrl_status |= DMA_CTRL_STATUS_INTR_CLEAR_ENABLE;
-
- // Setup the transfer direction and burst/single mode for the two DMA busses
- if (src_settings->bus_ == OXNAS_DMA_SIDE_A) {
- // Set the burst/single mode for bus A based on src device's settings
- if (src_settings->transfer_mode_
- == OXNAS_DMA_TRANSFER_MODE_BURST) {
- ctrl_status |= DMA_CTRL_STATUS_TRANSFER_MODE_A;
- } else {
- ctrl_status &= ~DMA_CTRL_STATUS_TRANSFER_MODE_A;
- }
-
- if (dst_settings->bus_ == OXNAS_DMA_SIDE_A) {
- direction = OXNAS_DMA_A_TO_A;
- } else {
- direction = OXNAS_DMA_A_TO_B;
-
- // Set the burst/single mode for bus B based on dst device's settings
- if (dst_settings->transfer_mode_
- == OXNAS_DMA_TRANSFER_MODE_BURST) {
- ctrl_status |= DMA_CTRL_STATUS_TRANSFER_MODE_B;
- } else {
- ctrl_status &= ~DMA_CTRL_STATUS_TRANSFER_MODE_B;
- }
- }
- } else {
- // Set the burst/single mode for bus B based on src device's settings
- if (src_settings->transfer_mode_
- == OXNAS_DMA_TRANSFER_MODE_BURST) {
- ctrl_status |= DMA_CTRL_STATUS_TRANSFER_MODE_B;
- } else {
- ctrl_status &= ~DMA_CTRL_STATUS_TRANSFER_MODE_B;
- }
-
- if (dst_settings->bus_ == OXNAS_DMA_SIDE_A) {
- direction = OXNAS_DMA_B_TO_A;
-
- // Set the burst/single mode for bus A based on dst device's settings
- if (dst_settings->transfer_mode_
- == OXNAS_DMA_TRANSFER_MODE_BURST) {
- ctrl_status |= DMA_CTRL_STATUS_TRANSFER_MODE_A;
- } else {
- ctrl_status &= ~DMA_CTRL_STATUS_TRANSFER_MODE_A;
- }
- } else {
- direction = OXNAS_DMA_B_TO_B;
- }
- }
- ctrl_status |= (direction << DMA_CTRL_STATUS_DIR_SHIFT);
-
- // Setup source address mode fixed or increment
- if (src_settings->address_mode_ == OXNAS_DMA_MODE_FIXED) {
- // Fixed address
- ctrl_status &= ~(DMA_CTRL_STATUS_SRC_ADR_MODE);
-
- // Set up whether fixed address is _really_ fixed
- if (src_settings->address_really_fixed_) {
- ctrl_status |= DMA_CTRL_STATUS_SOURCE_ADDRESS_FIXED;
- } else {
- ctrl_status &= ~DMA_CTRL_STATUS_SOURCE_ADDRESS_FIXED;
- }
- } else {
- // Incrementing address
- ctrl_status |= DMA_CTRL_STATUS_SRC_ADR_MODE;
- ctrl_status &= ~DMA_CTRL_STATUS_SOURCE_ADDRESS_FIXED;
- }
-
- // Setup destination address mode fixed or increment
- if (dst_settings->address_mode_ == OXNAS_DMA_MODE_FIXED) {
- // Fixed address
- ctrl_status &= ~(DMA_CTRL_STATUS_DEST_ADR_MODE);
-
- // Set up whether fixed address is _really_ fixed
- if (dst_settings->address_really_fixed_) {
- ctrl_status |=
- DMA_CTRL_STATUS_DESTINATION_ADDRESS_FIXED;
- } else {
- ctrl_status &=
- ~DMA_CTRL_STATUS_DESTINATION_ADDRESS_FIXED;
- }
- } else {
- // Incrementing address
- ctrl_status |= DMA_CTRL_STATUS_DEST_ADR_MODE;
- ctrl_status &= ~DMA_CTRL_STATUS_DESTINATION_ADDRESS_FIXED;
- }
-
- // Set up the width of the transfers on the DMA buses
- ctrl_status |=
- (src_settings->width_ << DMA_CTRL_STATUS_SRC_WIDTH_SHIFT);
- ctrl_status |=
- (dst_settings->width_ << DMA_CTRL_STATUS_DEST_WIDTH_SHIFT);
-
- // Setup the priority arbitration scheme
- ctrl_status &= ~DMA_CTRL_STATUS_STARVE_LOW_PRIORITY; // !Starve low priority
-
- return ctrl_status;
-}
-
-static u32 encode_final_eot(oxnas_dma_device_settings_t* src_settings,
- oxnas_dma_device_settings_t* dst_settings,
- unsigned long length)
-{
- // Write the length, with EOT configuration for a final transfer
- unsigned long encoded = length;
- if (dst_settings->write_final_eot_) {
- encoded |= DMA_BYTE_CNT_WR_EOT_MASK;
- } else {
- encoded &= ~DMA_BYTE_CNT_WR_EOT_MASK;
- }
- if (src_settings->read_final_eot_) {
- encoded |= DMA_BYTE_CNT_RD_EOT_MASK;
- } else {
- encoded &= ~DMA_BYTE_CNT_RD_EOT_MASK;
- }
- /* if((src_settings->transfer_mode_) ||
- (src_settings->transfer_mode_)) {
- encoded |= DMA_BYTE_CNT_BURST_MASK;
- } else {
- encoded &= ~DMA_BYTE_CNT_BURST_MASK;
- }*/
- return encoded;
-}
-
-static void dma_start_write(const ulong* buffer, int num_bytes)
-{
- // Assemble complete memory settings
- oxnas_dma_device_settings_t mem_settings = oxnas_ram_dma_settings;
- mem_settings.address_ = (unsigned long) buffer;
- mem_settings.address_mode_ = OXNAS_DMA_MODE_INC;
-
- writel(encode_control_status(&mem_settings, &oxnas_sata_dma_settings),
- SATA_DMA_REGS_BASE + DMA_CTRL_STATUS);
- writel(mem_settings.address_, SATA_DMA_REGS_BASE + DMA_BASE_SRC_ADR);
- writel(oxnas_sata_dma_settings.address_,
- SATA_DMA_REGS_BASE + DMA_BASE_DST_ADR);
- writel(encode_final_eot(&mem_settings, &oxnas_sata_dma_settings,
- num_bytes),
- SATA_DMA_REGS_BASE + DMA_BYTE_CNT);
-
- dma_start();
-}
-
-static void dma_start_read(ulong* buffer, int num_bytes)
-{
- // Assemble complete memory settings
- oxnas_dma_device_settings_t mem_settings = oxnas_ram_dma_settings;
- mem_settings.address_ = (unsigned long) buffer;
- mem_settings.address_mode_ = OXNAS_DMA_MODE_INC;
-
- writel(encode_control_status(&oxnas_sata_dma_settings, &mem_settings),
- SATA_DMA_REGS_BASE + DMA_CTRL_STATUS);
- writel(oxnas_sata_dma_settings.address_,
- SATA_DMA_REGS_BASE + DMA_BASE_SRC_ADR);
- writel(mem_settings.address_, SATA_DMA_REGS_BASE + DMA_BASE_DST_ADR);
- writel(encode_final_eot(&oxnas_sata_dma_settings, &mem_settings,
- num_bytes),
- SATA_DMA_REGS_BASE + DMA_BYTE_CNT);
-
- dma_start();
-}
-
-static inline int dma_busy(void)
-{
- return readl(SATA_DMA_REGS_BASE + DMA_CTRL_STATUS)
- & DMA_CTRL_STATUS_IN_PROGRESS;
-}
-
-static int wait_dma_not_busy(int device)
-{
- unsigned int cleanup_required = 0;
-
- /* Poll for DMA completion */
- int loops = MAX_DMA_XFER_LOOPS;
- do {
- if (!dma_busy()) {
- break;
- }
- udelay(100);
- } while (--loops);
-
- if (!loops) {
- printf("wait_dma_not_busy() Timed out of wait for DMA not busy\n");
- cleanup_required = 1;
- }
-
- if (cleanup_required) {
- /* Abort DMA to make sure it has finished. */
- unsigned int ctrl_status = readl(
- SATA_DMA_CHANNEL + DMA_CTRL_STATUS);
- ctrl_status |= DMA_CTRL_STATUS_RESET;
- writel(ctrl_status, SATA_DMA_CHANNEL + DMA_CTRL_STATUS);
-
- // Wait for the channel to become idle - should be quick as should
- // finish after the next AHB single or burst transfer
- loops = MAX_DMA_ABORT_LOOPS;
- do {
- if (!dma_busy()) {
- break;
- }
- udelay(10);
- } while (--loops);
-
- if (!loops) {
- printf("wait_dma_not_busy() Timed out of wait for DMA channel abort\n");
- } else {
- /* Successfully cleanup the DMA channel */
- cleanup_required = 0;
- }
-
- // Deassert reset for the channel
- ctrl_status = readl(SATA_DMA_CHANNEL + DMA_CTRL_STATUS);
- ctrl_status &= ~DMA_CTRL_STATUS_RESET;
- writel(ctrl_status, SATA_DMA_CHANNEL + DMA_CTRL_STATUS);
- }
-
- return !cleanup_required;
-}
-
-/**
- * Possible that ATA status will not become not-busy, so must have timeout
- */
-static unsigned int wait_not_busy(int device, unsigned long timeout_secs)
-{
- int busy = 1;
- unsigned long loops = (timeout_secs * 1000) / 50;
- do {
- // Test the ATA status register BUSY flag
- if (!((*(sata_regs_base[device] + SATA_ORB2_OFF)
- >> SATA_COMMAND_BIT) & (1UL << ATA_STATUS_BSY_BIT))) {
- /* Not busy, so stop polling */
- busy = 0;
- break;
- }
-
- // Wait for 50mS before sampling ATA status register again
- udelay(50000);
- } while (--loops);
-
- return busy;
-}
-
-void ide_output_data(int device, const ulong *sect_buf, int words)
-{
- /* Only permit accesses to disks found to be present during ide_preinit() */
- if (!disk_present[device]) {
- return;
- }
-
- /* Select the required internal SATA drive */
- device_select(device);
-
- /* Start the DMA channel sending data from the passed buffer to the SATA core */
- dma_start_write(sect_buf, words << 2);
-
- /* Don't know why we need this delay, but without it the wait for DMA not
- busy times soemtimes out, e.g. when saving environment to second disk */
- udelay(1000);
-
- /* Wait for DMA to finish */
- if (!wait_dma_not_busy(device)) {
- printf("Timed out of wait for DMA channel for SATA device %d to have in-progress clear\n",
- device);
- }
-
- /* Sata core should finish after DMA */
- if (wait_not_busy(device, 30)) {
- printf("Timed out of wait for SATA device %d to have BUSY clear\n",
- device);
- }
- if (!wait_no_error(device)) {
- printf("oxnas_sata_output_data() Wait for ATA no-error timed-out\n");
- }
-}
-
-
-#define SATA_DM_DBG1 (SATA_HOST_REGS_BASE + 0)
-#define SATA_DATACOUNT_PORT0 (SATA_HOST_REGS_BASE + 0x10)
-#define SATA_DATACOUNT_PORT1 (SATA_HOST_REGS_BASE + 0x14)
-#define SATA_DATA_MUX_RAM0 (SATA_HOST_REGS_BASE + 0x8000)
-#define SATA_DATA_MUX_RAM1 (SATA_HOST_REGS_BASE + 0xA000)
-/* Sata core debug1 register bits */
-#define SATA_CORE_PORT0_DATA_DIR_BIT 20
-#define SATA_CORE_PORT1_DATA_DIR_BIT 21
-#define SATA_CORE_PORT0_DATA_DIR (1 << SATA_CORE_PORT0_DATA_DIR_BIT)
-#define SATA_CORE_PORT1_DATA_DIR (1 << SATA_CORE_PORT1_DATA_DIR_BIT)
-
-/**
- * Ref bug-6320
- *
- * This code is a work around for a DMA hardware bug that will repeat the
- * penultimate 8-bytes on some reads. This code will check that the amount
- * of data transferred is a multiple of 512 bytes, if not the in it will
- * fetch the correct data from a buffer in the SATA core and copy it into
- * memory.
- *
- */
-static void sata_bug_6320_workaround(int port, ulong *candidate)
-{
- int is_read;
- int quads_transferred;
- int remainder;
- int sector_quads_remaining;
-
- /* Only want to apply fix to reads */
- is_read = !(*((unsigned long*) SATA_DM_DBG1)
- & (port ? SATA_CORE_PORT1_DATA_DIR : SATA_CORE_PORT0_DATA_DIR));
-
- /* Check for an incomplete transfer, i.e. not a multiple of 512 bytes
- transferred (datacount_port register counts quads transferred) */
- quads_transferred = *((unsigned long*) (
- port ? SATA_DATACOUNT_PORT1 : SATA_DATACOUNT_PORT0));
-
- remainder = quads_transferred & 0x7f;
- sector_quads_remaining = remainder ? (0x80 - remainder) : 0;
-
- if (is_read && (sector_quads_remaining == 2)) {
- debug("SATA read fixup, only transfered %d quads, "
- "sector_quads_remaining %d, port %d\n",
- quads_transferred, sector_quads_remaining, port);
-
- int total_len = ATA_SECT_SIZE;
- ulong *sata_data_ptr = (void*) (
- port ? SATA_DATA_MUX_RAM1 : SATA_DATA_MUX_RAM0)
- + ((total_len - 8) % 2048);
-
- *candidate = *sata_data_ptr;
- *(candidate + 1) = *(sata_data_ptr + 1);
- }
-}
-
-
-void ide_input_data(int device, ulong *sect_buf, int words)
-{
- /* Only permit accesses to disks found to be present during ide_preinit() */
- if (!disk_present[device]) {
- return;
- }
-
- /* Select the required internal SATA drive */
- device_select(device);
-
- /* Start the DMA channel receiving data from the SATA core into the passed buffer */
- dma_start_read(sect_buf, words << 2);
-
- /* Sata core should finish before DMA */
- if (wait_not_busy(device, 30)) {
- printf("Timed out of wait for SATA device %d to have BUSY clear\n",
- device);
- }
- if (!wait_no_error(device)) {
- printf("oxnas_sata_output_data() Wait for ATA no-error timed-out\n");
- }
-
- /* Wait for DMA to finish */
- if (!wait_dma_not_busy(device)) {
- printf("Timed out of wait for DMA channel for SATA device %d to have in-progress clear\n",
- device);
- }
-
- if (words == ATA_SECTORWORDS)
- sata_bug_6320_workaround(device, sect_buf + words - 2);
-}
-
-static u32 scr_read(int device, unsigned int sc_reg)
-{
- /* Setup adr of required register. std regs start eight into async region */
- *(sata_regs_base[device] + SATA_LINK_RD_ADDR) = sc_reg
- * 4+ SATA_STD_ASYNC_REGS_OFF;
-
- /* Wait for data to be available */
- int loops = MAX_SRC_READ_LOOPS;
- do {
- if (*(sata_regs_base[device] + SATA_LINK_CONTROL) & 1UL) {
- break;
- }
- udelay(10);
- } while (--loops);
-
- if (!loops) {
- printf("scr_read() Timed out of wait for read completion\n");
- }
-
- /* Read the data from the async register */
- return *(sata_regs_base[device] + SATA_LINK_DATA);
-}
-
-static void scr_write(int device, unsigned int sc_reg, u32 val)
-{
- /* Setup the data for the write */
- *(sata_regs_base[device] + SATA_LINK_DATA) = val;
-
- /* Setup adr of required register. std regs start eight into async region */
- *(sata_regs_base[device] + SATA_LINK_WR_ADDR) = sc_reg
- * 4+ SATA_STD_ASYNC_REGS_OFF;
-
- /* Wait for data to be written */
- int loops = MAX_SRC_WRITE_LOOPS;
- do {
- if (*(sata_regs_base[device] + SATA_LINK_CONTROL) & 1UL) {
- break;
- }
- udelay(10);
- } while (--loops);
-
- if (!loops) {
- printf("scr_write() Timed out of wait for write completion\n");
- }
-}
-extern void workaround5458(void);
-
-#define PHY_LOOP_COUNT 25 /* Wait for upto 5 seconds for PHY to be found */
-#define LOS_AND_TX_LVL 0x2988
-#define TX_ATTEN 0x55629
-
-static int phy_reset(int device)
-{
- int phy_status = 0;
- int loops = 0;
-
- scr_write(device, (0x60 - SATA_STD_ASYNC_REGS_OFF) / 4, LOS_AND_TX_LVL);
- scr_write(device, (0x70 - SATA_STD_ASYNC_REGS_OFF) / 4, TX_ATTEN);
-
- /* limit it to Gen-1 SATA (1.5G) */
- scr_write(device, SATA_SCR_CONTROL, 0x311); /* Issue phy wake & core reset */
- scr_read(device, SATA_SCR_STATUS); /* Dummy read; flush */
- udelay(1000);
- scr_write(device, SATA_SCR_CONTROL, 0x310); /* Issue phy wake & clear core reset */
-
- /* Wait for upto 5 seconds for PHY to become ready */
- do {
- udelay(200000);
- if ((scr_read(device, SATA_SCR_STATUS) & 0xf) == 3) {
- scr_write(device, SATA_SCR_ERROR, ~0);
- phy_status = 1;
- break;
- }
- //printf("No SATA PHY found status:0x%x\n", scr_read(device, SATA_SCR_STATUS));
- } while (++loops < PHY_LOOP_COUNT);
-
- if (phy_status) {
- udelay(500000); /* wait half a second */
- }
-
- return phy_status;
-}
-
-#define FIS_LOOP_COUNT 25 /* Wait for upto 5 seconds for FIS to be received */
-static int wait_FIS(int device)
-{
- int status = 0;
- int loops = 0;
-
- do {
- udelay(200000);
- if (ide_inb(device, ATA_PORT_NSECT) > 0) {
- status = 1;
- break;
- }
- } while (++loops < FIS_LOOP_COUNT);
-
- return status;
-}
-
-
-#define SATA_PHY_ASIC_STAT (0x44900000)
-#define SATA_PHY_ASIC_DATA (0x44900004)
-
-/**
- * initialise functions and macros for ASIC implementation
- */
-#define PH_GAIN 2
-#define FR_GAIN 3
-#define PH_GAIN_OFFSET 6
-#define FR_GAIN_OFFSET 8
-#define PH_GAIN_MASK (0x3 << PH_GAIN_OFFSET)
-#define FR_GAIN_MASK (0x3 << FR_GAIN_OFFSET)
-#define USE_INT_SETTING (1<<5)
-
-#define CR_READ_ENABLE (1<<16)
-#define CR_WRITE_ENABLE (1<<17)
-#define CR_CAP_DATA (1<<18)
-
-static void wait_cr_ack(void)
-{
- while ((readl(SATA_PHY_ASIC_STAT) >> 16) & 0x1f)
- /* wait for an ack bit to be set */;
-}
-
-static unsigned short read_cr(unsigned short address)
-{
- writel(address, SATA_PHY_ASIC_STAT);
- wait_cr_ack();
- writel(CR_READ_ENABLE, SATA_PHY_ASIC_DATA);
- wait_cr_ack();
- return readl(SATA_PHY_ASIC_STAT);
-}
-
-static void write_cr(unsigned short data, unsigned short address)
-{
- writel(address, SATA_PHY_ASIC_STAT);
- wait_cr_ack();
- writel((data | CR_CAP_DATA), SATA_PHY_ASIC_DATA);
- wait_cr_ack();
- writel(CR_WRITE_ENABLE, SATA_PHY_ASIC_DATA);
- wait_cr_ack();
- return;
-}
-
-void workaround5458(void)
-{
- unsigned i;
-
- for (i = 0; i < 2; i++) {
- unsigned short rx_control = read_cr(0x201d + (i << 8));
- rx_control &= ~(PH_GAIN_MASK | FR_GAIN_MASK);
- rx_control |= PH_GAIN << PH_GAIN_OFFSET;
- rx_control |= FR_GAIN << FR_GAIN_OFFSET;
- rx_control |= USE_INT_SETTING;
- write_cr(rx_control, 0x201d + (i << 8));
- }
-}
-
-int ide_preinit(void)
-{
- int num_disks_found = 0;
-
- /* Initialise records of which disks are present to all present */
- int i;
- for (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; i++) {
- disk_present[i] = 1;
- }
-
- /* Block reset SATA and DMA cores */
- reset_block(SYS_CTRL_RST_SATA, 1);
- reset_block(SYS_CTRL_RST_SATA_LINK, 1);
- reset_block(SYS_CTRL_RST_SATA_PHY, 1);
- reset_block(SYS_CTRL_RST_SGDMA, 1);
-
- /* Enable clocks to SATA and DMA cores */
- enable_clock(SYS_CTRL_CLK_SATA);
- enable_clock(SYS_CTRL_CLK_DMA);
-
- udelay(5000);
- reset_block(SYS_CTRL_RST_SATA_PHY, 0);
- udelay(50);
- reset_block(SYS_CTRL_RST_SATA, 0);
- reset_block(SYS_CTRL_RST_SATA_LINK, 0);
- udelay(50);
- reset_block(SYS_CTRL_RST_SGDMA, 0);
- udelay(100);
- /* Apply the Synopsis SATA PHY workarounds */
- workaround5458();
- udelay(10000);
-
- /* disable and clear core interrupts */
- *((unsigned long*) SATA_HOST_REGS_BASE + SATA_INT_ENABLE_CLR_OFF) =
- ~0UL;
- *((unsigned long*) SATA_HOST_REGS_BASE + SATA_INT_CLR_OFF) = ~0UL;
-
- int device;
- for (device = 0; device < CONFIG_SYS_IDE_MAXDEVICE; device++) {
- int found = 0;
- int retries = 1;
-
- /* Disable SATA interrupts */
- *(sata_regs_base[device] + SATA_INT_ENABLE_CLR_OFF) = ~0UL;
-
- /* Clear any pending SATA interrupts */
- *(sata_regs_base[device] + SATA_INT_CLR_OFF) = ~0UL;
-
- do {
- /* clear sector count register for FIS detection */
- ide_outb(device, ATA_PORT_NSECT, 0);
-
- /* Get the PHY working */
- if (!phy_reset(device)) {
- printf("SATA PHY not ready for device %d\n",
- device);
- break;
- }
-
- if (!wait_FIS(device)) {
- printf("No FIS received from device %d\n",
- device);
- } else {
- if ((scr_read(device, SATA_SCR_STATUS) & 0xf)
- == 0x3) {
- if (wait_not_busy(device, 30)) {
- printf("Timed out of wait for SATA device %d to have BUSY clear\n",
- device);
- } else {
- ++num_disks_found;
- found = 1;
- }
- } else {
- printf("No SATA device %d found, PHY status = 0x%08x\n",
- device,
- scr_read(
- device,
- SATA_SCR_STATUS));
- }
- break;
- }
- } while (retries--);
-
- /* Record whether disk is present, so won't attempt to access it later */
- disk_present[device] = found;
- }
-
- /* post disk detection clean-up */
- for (device = 0; device < CONFIG_SYS_IDE_MAXDEVICE; device++) {
- if (disk_present[device]) {
- /* set as ata-5 (28-bit) */
- *(sata_regs_base[device] + SATA_DRIVE_CONTROL_OFF) =
- 0UL;
-
- /* clear phy/link errors */
- scr_write(device, SATA_SCR_ERROR, ~0);
-
- /* clear host errors */
- *(sata_regs_base[device] + SATA_CONTROL_OFF) |=
- SATA_SCTL_CLR_ERR;
-
- /* clear interrupt register as this clears the error bit in the IDE
- status register */
- *(sata_regs_base[device] + SATA_INT_CLR_OFF) = ~0UL;
- }
- }
-
- return !num_disks_found;
-}
-
+++ /dev/null
-/*
- * drivers/usb/host/ehci-oxnas.c
- *
- * Tzachi Perelstein <tzachi@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <common.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/sysctl.h>
-#include <asm/arch/clock.h>
-
-#include "ehci.h"
-
-static struct ehci_hcor *ghcor;
-
-static int start_oxnas_usb_ehci(void)
-{
-#ifdef CONFIG_USB_PLLB_CLK
- reset_block(SYS_CTRL_RST_PLLB, 0);
- enable_clock(SYS_CTRL_CLK_REF600);
-
- writel((1 << PLLB_ENSAT) | (1 << PLLB_OUTDIV) | (2 << PLLB_REFDIV),
- SEC_CTRL_PLLB_CTRL0);
- /* 600MHz pllb divider for 12MHz */
- writel(PLLB_DIV_INT(50) | PLLB_DIV_FRAC(0), SEC_CTRL_PLLB_DIV_CTRL);
-#else
- /* ref 300 divider for 12MHz */
- writel(REF300_DIV_INT(25) | REF300_DIV_FRAC(0), SYS_CTRL_REF300_DIV);
-#endif
-
- /* Ensure the USB block is properly reset */
- reset_block(SYS_CTRL_RST_USBHS, 1);
- reset_block(SYS_CTRL_RST_USBHS, 0);
-
- reset_block(SYS_CTRL_RST_USBHSPHYA, 1);
- reset_block(SYS_CTRL_RST_USBHSPHYA, 0);
-
- reset_block(SYS_CTRL_RST_USBHSPHYB, 1);
- reset_block(SYS_CTRL_RST_USBHSPHYB, 0);
-
- /* Force the high speed clock to be generated all the time, via serial
- programming of the USB HS PHY */
- writel((2UL << USBHSPHY_TEST_ADD) |
- (0xe0UL << USBHSPHY_TEST_DIN), SYS_CTRL_USBHSPHY_CTRL);
-
- writel((1UL << USBHSPHY_TEST_CLK) |
- (2UL << USBHSPHY_TEST_ADD) |
- (0xe0UL << USBHSPHY_TEST_DIN), SYS_CTRL_USBHSPHY_CTRL);
-
- writel((0xfUL << USBHSPHY_TEST_ADD) |
- (0xaaUL << USBHSPHY_TEST_DIN), SYS_CTRL_USBHSPHY_CTRL);
-
- writel((1UL << USBHSPHY_TEST_CLK) |
- (0xfUL << USBHSPHY_TEST_ADD) |
- (0xaaUL << USBHSPHY_TEST_DIN), SYS_CTRL_USBHSPHY_CTRL);
-
-#ifdef CONFIG_USB_PLLB_CLK /* use pllb clock */
- writel(USB_CLK_INTERNAL | USB_INT_CLK_PLLB, SYS_CTRL_USB_CTRL);
-#else /* use ref300 derived clock */
- writel(USB_CLK_INTERNAL | USB_INT_CLK_REF300, SYS_CTRL_USB_CTRL);
-#endif
- /* Enable the clock to the USB block */
- enable_clock(SYS_CTRL_CLK_USBHS);
-
- return 0;
-}
-int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr,
- struct ehci_hcor **hcor)
-{
- start_oxnas_usb_ehci();
- *hccr = (struct ehci_hccr *)(USB_HOST_BASE + 0x100);
- *hcor = (struct ehci_hcor *)((uint32_t)*hccr +
- HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
- ghcor = *hcor;
- return 0;
-}
-
-int ehci_hcd_stop(int index)
-{
- reset_block(SYS_CTRL_RST_USBHS, 1);
- disable_clock(SYS_CTRL_CLK_USBHS);
- return 0;
-}
-
-extern void __ehci_set_usbmode(int index);
-void ehci_set_usbmode(int index)
-{
- #define or_txttfill_tuning _reserved_1_[0]
- u32 tmp;
-
- __ehci_set_usbmode(index);
-
- tmp = ehci_readl(&ghcor->or_txfilltuning);
- tmp &= ~0x00ff0000;
- tmp |= 0x003f0000; /* set burst pre load count to 0x40 (63 * 4 bytes) */
- tmp |= 0x16; /* set sheduler overhead to 22 * 1.267us (HS) or 22 * 6.33us (FS/LS)*/
- ehci_writel(&ghcor->or_txfilltuning, tmp);
-
- tmp = ehci_readl(&ghcor->or_txttfill_tuning);
- tmp |= 0x2; /* set sheduler overhead to 2 * 6.333us */
- ehci_writel(&ghcor->or_txttfill_tuning, tmp);
-}
+++ /dev/null
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* High Level Configuration Options */
-#define CONFIG_ARM1136
-#define CONFIG_OX820
-#define CONFIG_SYS_GENERIC_BOARD
-#define CONFIG_BOARD_EARLY_INIT_F
-
-#include <asm/arch/cpu.h> /* get chip and board defs */
-
-/* make cmd_ide.c quiet when compile */
-#define __io
-
-/*#define CONFIG_ARCH_CPU_INIT*/
-/*#define CONFIG_DISPLAY_CPUINFO*/
-/*#define CONFIG_DISPLAY_BOARDINFO*/
-/*#define CONFIG_BOARD_EARLY_INIT_F*/
-/*#define CONFIG_SKIP_LOWLEVEL_INIT*/
-
-/* mem */
-#define CONFIG_SYS_SDRAM_BASE 0x60000000
-#define CONFIG_NR_DRAM_BANKS 1
-#define CONFIG_MIN_SDRAM_SIZE (128 * 1024 * 1024) /* 128 MB */
-#define CONFIG_MAX_SDRAM_SIZE (512 * 1024 * 1024) /* 512 MB */
-#define CONFIG_SRAM_BASE 0x50000000
-#define CONFIG_SRAM_SIZE (64 * 1024)
-
-/* need do dma so better keep dcache off */
-#define CONFIG_SYS_DCACHE_OFF
-
-/* clock */
-#define CONFIG_PLLA_FREQ_MHZ 800
-#define CONFIG_RPSCLK 6250000
-#define CONFIG_SYS_HZ 1000
-#define CONFIG_SYS_CLK_FREQ CONFIG_RPSCLK
-#define CONFIG_SYS_TIMERBASE TIMER1_BASE
-#define CONFIG_TIMER_PRESCALE TIMER_PRESCALE_16
-
-/* serial */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_CLK CONFIG_RPSCLK
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_NS16550_COM1 UART_1_BASE
-#define CONFIG_CONS_INDEX 1
-
-/* ide */
-#define CONFIG_SYS_ATA_BASE_ADDR 0
-#define CONFIG_SYS_ATA_DATA_OFFSET 0
-#define CONFIG_SYS_ATA_REG_OFFSET 0
-#define CONFIG_SYS_ATA_ALT_OFFSET 0
-#define CONFIG_IDE_PLX
-#define CONFIG_SYS_IDE_MAXDEVICE 2
-#define CONFIG_SYS_IDE_MAXBUS 1
-#define CONFIG_IDE_PREINIT
-#define CONFIG_LBA48
-
-/* nand */
-#define CONFIG_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE STATIC_CS0_BASE
-#define NAND_CLE_ADDR_PIN 19
-#define NAND_ALE_ADDR_PIN 18
-#define MTDPARTS_DEFAULT "mtdparts=41000000.nand:" \
- "14m(boot)," \
- "-(ubi)"
-#define MTDIDS_DEFAULT "nand0=41000000.nand"
-#define UBIPART_DEFAULT "ubi"
-
-/* net */
-#define CONFIG_DESIGNWARE_ETH
-#define CONFIG_DW_ALTDESCRIPTOR
-#define CONFIG_MII
-#define CONFIG_CMD_MII
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_REALTEK
-#define CONFIG_PHY_ICPLUS
-
-/* spl */
-#ifdef CONFIG_SPL_BUILD
-#define USE_DL_PREFIX /* rename malloc free etc, so we can override them */
-#endif
-
-#if defined(CONFIG_BOOT_FROM_NAND) || defined(CONFIG_BOOT_FROM_SATA)
-#define CONFIG_SPL
-#define CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_TEXT_BASE 0x50000000
-#define CONFIG_SPL_STACK (CONFIG_SRAM_BASE + (48 * 1024))
-#define CONFIG_SPL_DISPLAY_PRINT
-#define CONFIG_SPL_BSS_DRAM_START 0x65000000
-#define CONFIG_SPL_BSS_DRAM_SIZE 0x01000000
-#define CONFIG_SPL_MALLOC_START 0x66000000
-#endif
-
-#if defined(CONFIG_BOOT_FROM_NAND)
-#define CONFIG_SPL_NAND_SUPPORT
-#define BOOT_DEVICE_TYPE "NAND"
-#define BOOT_DEVICE_NAND 0xfeedbacc
-#define CONFIG_SPL_BOOT_DEVICE BOOT_DEVICE_NAND
-#define CONFIG_SPL_NAND_SIMPLE
-#define CONFIG_SPL_NAND_ECC
-#define CONFIG_SPL_NAND_SOFTECC
-#define CONFIG_SYS_NAND_ECCSIZE 512
-#define CONFIG_SYS_NAND_ECCBYTES 6
-#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47, \
- 48, 49, 50, 51, 52, 53, 54, 55, \
- 56, 57, 58, 59, 60, 61, 62, 63}
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048
-#define CONFIG_SYS_NAND_OOBSIZE 64
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
-/* pages per erase block */
-#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / CONFIG_SYS_NAND_PAGE_SIZE)
-/* nand spl use 1 erase block, and use bit to byte encode for reliability */
-#define CONFIG_SPL_MAX_SIZE (128 * 1024 / 8)
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00040000
-/* spl kernel load is not enabled */
-#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000
-#define CONFIG_CMD_SPL_NAND_OFS 0
-#define CONFIG_CMD_SPL_WRITE_SIZE 1024
-#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100)
-/* CONFIG_BOOT_FROM_NAND end */
-
-#elif defined(CONFIG_BOOT_FROM_SATA)
-#define CONFIG_SPL_BLOCK_SUPPORT
-#define BOOT_DEVICE_TYPE "SATA"
-#define BOOT_DEVICE_BLOCK 860202
-#define CONFIG_SPL_BOOT_DEVICE BOOT_DEVICE_BLOCK
-#define CONFIG_SPL_MAX_SIZE (36 * 1024)
-#define CONFIG_SPL_LIBDISK_SUPPORT
-#define CONFIG_SPL_BLOCKDEV_INTERFACE "ide"
-#define CONFIG_SPL_BLOCKDEV_ID 0
-
-#ifdef CONFIG_BOOT_FROM_FAT /* u-boot in fat partition */
-
-#define CONFIG_SPL_FAT_SUPPORT
-
-#define CONFIG_BLOCKDEV_FAT_BOOT_PARTITION 1 /* first partition */
-#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" /* u-boot file name */
-/* enable U-Boot Falcon Mode */
-#define CONFIG_CMD_SPL
-#define CONFIG_SPL_OS_BOOT
-#define CONFIG_SPL_FAT_LOAD_ARGS_NAME "bootargs.bin" /* boot parameters */
-#define CONFIG_SPL_FAT_LOAD_KERNEL_NAME "falcon.img" /* kernel */
-#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100)
-
-#elif CONFIG_BOOT_FROM_EXT4
-
-#define CONFIG_SPL_EXT4_SUPPORT
-#define CONFIG_BLOCKDEV_EXT4_BOOT_PARTITION 1 /* first partition */
-#define CONFIG_SPL_EXT4_LOAD_PAYLOAD_NAME "/boot/u-boot.img" /* u-boot file name */
-/* enable U-Boot Falcon Mode */
-#define CONFIG_CMD_SPL
-#define CONFIG_SPL_OS_BOOT
-#define CONFIG_SPL_EXT4_LOAD_ARGS_NAME "/boot/bootargs.bin" /* boot parameters */
-#define CONFIG_SPL_EXT4_LOAD_KERNEL_NAME "/boot/falcon.img" /* kernel */
-#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100)
-
-#else /* u-boot in raw sectors */
-
-#define CONFIG_SYS_BLOCK_RAW_MODE_U_BOOT_SECTOR 1024
-/* spl kernel load is not enabled */
-#define CONFIG_SYS_BLOCK_RAW_MODE_KERNEL_SECTOR 4096
-#define CONFIG_SYS_BLOCK_RAW_MODE_ARGS_SECTOR 0
-#define CONFIG_SYS_BLOCK_RAW_MODE_ARGS_SECTORS (1024 / 512)
-#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100)
-
-#endif /* CONFIG_BOOT_FROM_FAT */
-/* CONFIG_BOOT_FROM_SATA end */
-
-#else
-/* generic, no spl support */
-#endif
-
-/* boot */
-#define CONFIG_IDENT_STRING " for OXNAS"
-#define CONFIG_MACH_TYPE MACH_TYPE_OXNAS
-#ifndef CONFIG_SPL_BUILD
-/* Enable devicetree support */
-#define CONFIG_OF_LIBFDT
-#endif
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_INITRD_TAG
-#define CONFIG_BOOTDELAY 1
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-#define CONFIG_DEFAULT_CONSOLE_PARM "console=ttyS0,115200n8 earlyprintk=serial"
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-/* memtest works on */
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE)
-#define CONFIG_SYS_AUTOLOAD "no"
-
-#define CONFIG_DEFAULT_CONSOLE CONFIG_DEFAULT_CONSOLE_PARM "\0"
-#define CONFIG_BOOTARGS CONFIG_DEFAULT_CONSOLE_PARM
-#define CONFIG_BOOTCOMMAND "run nandboot"
-#define CONFIG_BOOT_RETRY_TIME -1
-#define CONFIG_RESET_TO_RETRY 60
-
-#define CONFIG_NETCONSOLE
-#define CONFIG_IPADDR 192.168.50.100
-#define CONFIG_SERVERIP 192.168.50.59
-
-/* A sane default configuration...
- * When booting without a valid environment in ubi, first to loading and booting
- * the kernel image directly above U-Boot, maybe both were loaded there by
- * another bootloader.
- * Also use that same offset (0x90000) to load the rescue image later on (by
- * adding it onto the flash address where U-Boot is supposed to be stored by
- * the legacy loader, 0x440000, resulting in offset 0x4d0000 on the flash).
- * When coming up with a valid environment in ubi, first try to load the
- * kernel from a ubi volume kernel, if that fails, fallback to the rescue
- * image stored in boot partition. As a last resort try booting via
- * DHCP/TFTP.
- * In case there is no valid environment, first probe for a uimage in ram left
- * behind by the first bootloader on a tftp boot.
- * If that fails, switch to normal boot order and save environment.
- * The loader is supposed to be written to flash at offset 0x440000 and loaded to
- * RAM at 0x64000000
- */
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "load_kernel_ubi=ubi readvol 0x62000000 kernel;\0" \
- "load_kernel_rescue=nand read 0x62000000 0x4e0000 0x400000;\0" \
- "load_kernel_dhcp=dhcp 0x62000000 oxnas-rescue.bin;\0" \
- "boot_kernel=bootm 0x62000000;\0" \
- "boot_ubi=run load_kernel_ubi && run boot_kernel;\0" \
- "boot_rescue=run load_kernel_rescue && run boot_kernel;\0" \
- "boot_dhcp=run load_kernel_dhcp && run boot_kernel;\0" \
- "normalboot=run boot_ubi; run boot_rescue; run boot_dhcp;\0" \
- "firstboot=bootm 0x640a0000; setenv bootcmd run normalboot; " \
- "setenv firstboot; saveenv; run bootcmd; \0" \
- "bootcmd=run firstboot; \0" \
- "console=" CONFIG_DEFAULT_CONSOLE \
- "bootargs=" CONFIG_BOOTARGS "\0" \
- "mtdids=" MTDIDS_DEFAULT "\0" \
- "mtdparts=" MTDPARTS_DEFAULT "\0" \
-
-/* env */
-#if defined(CONFIG_BOOT_FROM_NAND)
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_OFFSET 0x000C0000
-#define CONFIG_ENV_SIZE 0x00020000
-#define CONFIG_ENV_OFFSET_REDUND 0x00100000
-#define CONFIG_ENV_SIZE_REDUND 0x00020000
-#define CONFIG_ENV_RANGE (CONFIG_ENV_SIZE * 2)
-/* CONFIG_BOOT_FROM_NAND end */
-
-#elif defined(CONFIG_BOOT_FROM_SATA)
-#ifdef CONFIG_BOOT_FROM_EXT4
-#define CONFIG_ENV_IS_IN_EXT4
-#define CONFIG_START_IDE
-#define EXT4_ENV_INTERFACE "ide"
-#define EXT4_ENV_DEVICE 0
-#define EXT4_ENV_PART 1
-#define EXT4_ENV_FILE "/boot/u-boot.env"
-#define CONFIG_ENV_SIZE (16 * 1024)
-#else
-#define CONFIG_ENV_IS_IN_FAT
-#define CONFIG_START_IDE
-#define FAT_ENV_INTERFACE "ide"
-#define FAT_ENV_DEVICE 0
-#define FAT_ENV_PART 1
-#define FAT_ENV_FILE "u-boot.env"
-#define CONFIG_ENV_SIZE (16 * 1024)
-#endif
-/* CONFIG_BOOT_FROM_SATA end */
-#elif defined(CONFIG_BOOT_FROM_SATA)
-
-#else
-/* generic */
-#define CONFIG_ENV_IS_IN_UBI 1
-#define CONFIG_ENV_UBI_PART UBIPART_DEFAULT
-#define CONFIG_ENV_UBI_VOLUME "ubootenv"
-#define CONFIG_ENV_UBI_VOLUME_REDUND "ubootenv2"
-#define CONFIG_ENV_SIZE (16 * 1024)
-#endif
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
-#define CONFIG_SYS_TEXT_BASE 0x64000000
-#define CONFIG_SYS_INIT_SP_ADDR 0x65000000
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
-
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-#define CONFIG_SYS_PROMPT "OX820 # "
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size*/
-#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_AUTO_COMPLETE
-
-/* usb */
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-#define CONFIG_USB_EHCI
-#define CONFIG_EHCI_IS_TDI
-/* #define CONFIG_USB_EHCI_TXFIFO_THRESH 0x3F */
-#define CONFIG_USB_PLLB_CLK
-#define CONFIG_USB_EHCI_OXNAS
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_USB_STORAGE
-#endif
-#define CONFIG_CMD_USB
-
-/* cmds */
-#define CONFIG_SYS_NO_FLASH
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_GREPENV
-#define CONFIG_CMD_ENV_FLAGS
-
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_PXE
-
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_CMD_UBI
-#define CONFIG_CMD_UBIFS
-
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_FAT
-#define CONFIG_FAT_WRITE
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_EXT4
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_CMD_EXT4_WRITE
-#endif
-
-#define CONFIG_CMD_ZIP
-#define CONFIG_CMD_UNZIP
-#define CONFIG_CMD_TIME
-#define CONFIG_CMD_SETEXPR
-#define CONFIG_CMD_MD5SUM
-#define CONFIG_CMD_HASH
-#define CONFIG_CMD_INI
-#define CONFIG_CMD_GETTIME
-#define CONFIG_CMD_BOOTMENU
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_BOOTZ
-
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
-
-/* for CONFIG_CMD_MTDPARTS */
-#define CONFIG_MTD_DEVICE
-/* for CONFIG_CMD_UBI */
-#define CONFIG_MTD_PARTITIONS
-/* for CONFIG_CMD_UBI */
-#define CONFIG_RBTREE
-
-/* optional, for CONFIG_CMD_BOOTM & required by CONFIG_CMD_UBIFS */
-#define CONFIG_LZO
-#define CONFIG_LZMA
-#define CONFIG_BZIP2
-
-/* for CONFIG_CMD_ZIP */
-#define CONFIG_GZIP_COMPRESSED
-/* for CONFIG_CMD_MD5SUM */
-#define CONFIG_MD5
-#define CONFIG_MD5SUM_VERIFY
-/* enable CONFIG_CMD_HASH's verification feature */
-#define CONFIG_HASH_VERIFY
-#define CONFIG_REGEX
-/* for CONFIG_CMD_BOOTMENU & CONFIG_CMD_PXE */
-#define CONFIG_MENU
-
-/* for new FIT uImage format generated in OpenWrt */
-#define CONFIG_FIT
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/* J J Larworthy 27 September 2006 */
-
-/* file to read the boot sector of a dis and the loaded image and report
- * if the boot rom would accept the data as intact and suitable for use
- */
-
-#include <sys/types.h>
-#include <sys/stat.h>
-#include <sys/errno.h>
-
-#include <fcntl.h>
-#include <unistd.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <assert.h>
-
-extern uint32_t crc32(uint32_t, const unsigned char *, unsigned int);
-
-#define NUMBER_VECTORS 12
-struct {
- unsigned int start_vector[NUMBER_VECTORS];
- char code[4];
- unsigned int header_length;
- unsigned int reserved[3];
- unsigned int length;
- unsigned int img_CRC;
- unsigned int CRC;
-} img_header;
-
-void print_usage(void)
-{
- printf("update_header file.bin\n");
-}
-
-void print_header(void)
-{
- int i;
-
- printf("vectors in header\n");
- for (i = 0; i < NUMBER_VECTORS; i++) {
- printf("%d:0x%08x\n", i, img_header.start_vector[i]);
- }
- printf("length:%8x\nimg_CRC:0x%08x\nHeader CRC:0x%08x\n",
- img_header.length, img_header.img_CRC, img_header.CRC);
-}
-
-int main(int argc, char **argv)
-{
- int in_file;
- int status;
- int unsigned crc;
- int file_length;
- int len;
-
- struct stat file_stat;
-
- void *executable;
-
- in_file = open(argv[1], O_RDWR);
-
- if (in_file < 0) {
- printf("failed to open file:%s\n", argv[optind]);
- return -ENOENT;
- }
-
- status = fstat(in_file, &file_stat);
-
- /* read header and obtain size of image */
- status = read(in_file, &img_header, sizeof(img_header));
-
- file_length = file_stat.st_size - sizeof(img_header);
-
- if (img_header.length != file_length) {
- printf("size in header:%d, size of file: %d\n",
- img_header.length, file_length);
- }
- img_header.length = file_length;
-
- /* read working image and CRC */
- executable = malloc(file_length);
-
- status = read(in_file, executable, file_length);
-
- if (status != file_length) {
- printf("Failed to load image\n");
- free(executable);
- return -ENOENT;
- }
-
- /* verify image CRC */
- crc = crc32(0, (const unsigned char *) executable, img_header.length);
-
- if (crc != img_header.img_CRC) {
- printf("New Image CRC:0x%08x, hdr:0x%08x\n", crc,
- img_header.img_CRC);
- img_header.img_CRC = crc;
- }
- memcpy(img_header.code, "BOOT", 4);
- img_header.header_length = sizeof(img_header);
-
- /* check header CRC */
- crc = crc32(0, (const unsigned char *) &img_header,
- sizeof(img_header) - sizeof(unsigned int));
- if (crc != img_header.CRC) {
- printf("New header CRC - crc:0x%08x hdr:0x%08x\n", crc,
- img_header.CRC);
- img_header.CRC = crc;
- }
-
- /* re-write the file */
- status = lseek(in_file, 0, SEEK_SET);
- if (status != 0) {
- printf("failed to rewind\n");
- free(executable);
- return 1;
- }
- len = write(in_file, &img_header, sizeof(img_header));
- assert(len == sizeof(img_header));
- len = write(in_file, executable, file_length);
- assert(len == file_length);
- close(in_file);
- free(executable);
-
- return 0;
-}
O=$(PKG_BUILD_DIR) \
prefix=/usr
+ifeq ($(LINUX_KARCH),powerpc)
+ MAKE_FLAGS += NO_AUXTRACE=1
+endif
+
define Build/Compile
+$(MAKE) $(PKG_JOBS) $(MAKE_FLAGS) \
--no-print-directory \
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL=$(PROJECT_GIT)/project/firmware/qca-wireless.git
-PKG_SOURCE_DATE:=2024-04-16
-PKG_SOURCE_VERSION:=1d51799e6768a304da7840b8346e7487efd77f49
-PKG_MIRROR_HASH:=9cf0917532283c1a1708643022a5ed1ec4af6bb9ebaff57fc2f0f2c229f2469e
+PKG_SOURCE_DATE:=2024-04-26
+PKG_SOURCE_VERSION:=644ba9ea2e6685e420561ef098cb6fbaaf136cbf
+PKG_MIRROR_HASH:=3b913fd6fb0fac404b16e67c66d36c10315dba5459a8d495d870afcb1e2c33cd
PKG_FLAGS:=nonshared
include $(INCLUDE_DIR)/package.mk
prpl_haze \
qnap_301w \
redmi_ax6 \
+ spectrum_sax1v1k \
wallys_dr40x9 \
xiaomi_ax3600 \
xiaomi_ax9000 \
$(eval $(call generate-ipq-wifi-package,qnap_301w,QNAP 301w))
$(eval $(call generate-ipq-wifi-package,prpl_haze,prpl Haze))
$(eval $(call generate-ipq-wifi-package,redmi_ax6,Redmi AX6))
+$(eval $(call generate-ipq-wifi-package,spectrum_sax1v1k,Spectrum SAX1V1K))
$(eval $(call generate-ipq-wifi-package,wallys_dr40x9,Wallys DR40X9))
$(eval $(call generate-ipq-wifi-package,xiaomi_ax3600,Xiaomi AX3600))
$(eval $(call generate-ipq-wifi-package,xiaomi_ax9000,Xiaomi AX9000))
$(eval $(call KernelPackage,phy-aquantia))
+define KernelPackage/dsa-tag-dsa
+ SUBMENU:=$(NETWORK_DEVICES_MENU)
+ TITLE:=Marvell DSA type DSA and EDSA taggers
+ KCONFIG:= CONFIG_NET_DSA_TAG_DSA_COMMON \
+ CONFIG_NET_DSA_TAG_DSA \
+ CONFIG_NET_DSA_TAG_EDSA \
+ CONFIG_NET_DSA=y
+ FILES:=$(LINUX_DIR)/net/dsa/tag_dsa.ko
+ AUTOLOAD:=$(call AutoLoad,40,tag_dsa,1)
+endef
+
+define KernelPackage/dsa-tag-dsa/description
+ Kernel modules for Marvell DSA and EDSA tagging
+endef
+
+$(eval $(call KernelPackage,dsa-tag-dsa))
+
+define KernelPackage/dsa-mv88e6xxx
+ SUBMENU:=$(NETWORK_DEVICES_MENU)
+ TITLE:=Marvell MV88E6XXX DSA Switch
+ DEPENDS:=+kmod-ptp +kmod-phy-marvell +kmod-dsa-tag-dsa
+ KCONFIG:=CONFIG_NET_DSA_MV88E6XXX \
+ CONFIG_NET_DSA_MV88E6XXX_PTP=y \
+ CONFIG_NET_DSA=y
+ FILES:=$(LINUX_DIR)/drivers/net/dsa/mv88e6xxx/mv88e6xxx.ko
+ AUTOLOAD:=$(call AutoLoad,41,mv88e6xxx,1)
+endef
+
+define KernelPackage/dsa-mv88e6xxx/description
+ Kernel modules for MV88E6XXX DSA switches
+endef
+
+$(eval $(call KernelPackage,dsa-mv88e6xxx))
+
define KernelPackage/swconfig
SUBMENU:=$(NETWORK_DEVICES_MENU)
PKG_SOURCE_URL:=https://github.com/kaloz/mwlwifi
PKG_SOURCE_PROTO:=git
-PKG_SOURCE_DATE:=2023-11-29
-PKG_SOURCE_VERSION:=ebf3167445f108346dcff9a31a708534c0bd7cc5
-PKG_MIRROR_HASH:=6dffc08208305366b9c25133b74693d5c2e544c1076b7b4ed846628c66be56c1
+PKG_SOURCE_DATE:=2024-04-19
+PKG_SOURCE_VERSION:=a737d348ef4fe00434b2bc44b2b6a68ea833d95b
+PKG_MIRROR_HASH:=d55f69c2fa48d02ba535b72b108fc77f5f13a52b29130a631489a053f1670d2c
PKG_MAINTAINER:=Imre Kaloz <kaloz@openwrt.org>
PKG_BUILD_PARALLEL:=1
include $(TOPDIR)/rules.mk
PKG_NAME:=gettext-full
-PKG_VERSION:=0.21.1
-PKG_RELEASE:=2
+PKG_VERSION:=0.22.5
+PKG_RELEASE:=1
PKG_SOURCE:=gettext-$(PKG_VERSION).tar.xz
PKG_SOURCE_URL:=@GNU/gettext
-PKG_HASH:=50dbc8f39797950aa2c98e939947c527e5ac9ebd2c1b99dd7b06ba33a6767ae6
+PKG_HASH:=fe10c37353213d78a5b83d48af231e005c4da84db5ce88037d88355938259640
PKG_BUILD_DIR:=$(BUILD_DIR)/gettext-$(PKG_VERSION)
HOST_BUILD_DIR:=$(BUILD_DIR_HOST)/gettext-$(PKG_VERSION)
--- a/autogen.sh
+++ b/autogen.sh
-@@ -78,6 +78,7 @@ if ! $skip_gnulib; then
+@@ -81,6 +81,7 @@ if ! $skip_gnulib; then
getopt-gnu
gettext-h
havelib
progname
--- a/gettext-runtime/src/Makefile.am
+++ b/gettext-runtime/src/Makefile.am
-@@ -40,7 +40,7 @@ envsubst_SOURCES = envsubst.c
+@@ -43,7 +43,7 @@ envsubst_SOURCES = envsubst.c
# Link dependencies.
# Need @LTLIBICONV@ because striconv.c uses iconv().
+++ /dev/null
-#
-# This is free software, licensed under the GNU General Public License v2.
-# See /LICENSE for more information.
-#
-
-include $(TOPDIR)/rules.mk
-
-PKG_NAME:=libaudit
-PKG_VERSION:=2.8.5
-PKG_RELEASE:=1
-
-PKG_SOURCE_NAME:=audit
-PKG_SOURCE:=$(PKG_SOURCE_NAME)-$(PKG_VERSION).tar.gz
-PKG_SOURCE_URL:=https://people.redhat.com/sgrubb/audit
-PKG_HASH:=0e5d4103646e00f8d1981e1cd2faea7a2ae28e854c31a803e907a383c5e2ecb7
-PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_SOURCE_NAME)-$(PKG_VERSION)
-HOST_BUILD_DIR:=$(BUILD_DIR_HOST)/$(PKG_SOURCE_NAME)-$(PKG_VERSION)
-PKG_MAINTAINER:=Thomas Petazzoni <thomas.petazzoni@bootlin.com>
-PKG_LICENSE:=GPL-2.0
-PKG_LICENSE_FILES:=COPYING
-PKG_CPE_ID:=cpe:/a:linux_audit_project:linux_audit
-
-PKG_FIXUP:=autoreconf
-
-PKG_BUILD_FLAGS:=no-mips16
-PKG_INSTALL:=1
-
-include $(INCLUDE_DIR)/package.mk
-include $(INCLUDE_DIR)/host-build.mk
-
-define Package/libaudit
- CATEGORY:=Libraries
- TITLE:=Linux Auditing Framework (shared library)
- URL:=http://people.redhat.com/sgrubb/audit/
-endef
-
-define Package/libaudit/description
- This package contains the audit shared library.
-endef
-
-CONFIGURE_VARS += \
- LDFLAGS_FOR_BUILD="$(HOST_LDFLAGS)" \
- CPPFLAGS_FOR_BUILD="$(HOST_CPPFLAGS)" \
- CFLAGS_FOR_BUILD="$(HOST_CFLAGS)" \
- CC_FOR_BUILD="$(HOSTCC)"
-
-CONFIGURE_ARGS += \
- --without-libcap-ng \
- --disable-systemd \
- --without-python \
- --without-python3 \
- --disable-zos-remote
-
-ifeq ($(ARCH),aarch64)
-CONFIGURE_ARGS += --with-aarch64
-else ifeq ($(ARCH),arm)
-CONFIGURE_ARGS += --with-arm
-endif
-
-HOST_CONFIGURE_ARGS += \
- --without-libcap-ng \
- --disable-systemd \
- --without-python \
- --without-python3 \
- --disable-zos-remote
-
-MAKE_PATH:=lib
-
-# Host/Compile/default doesn't include $(MAKE_PATH), override to use,
-# so we avoid building and installing unnecessary parts on the host.
-define Host/Compile
- +$(HOST_MAKE_VARS) $(MAKE) $(HOST_JOBS) -C $(HOST_BUILD_DIR)/$(MAKE_PATH) $(HOST_MAKE_FLAGS) all
-endef
-
-define Host/Install
- +$(HOST_MAKE_VARS) $(MAKE) $(HOST_JOBS) -C $(HOST_BUILD_DIR)/lib $(HOST_MAKE_FLAGS) install
- +$(HOST_MAKE_VARS) $(MAKE) $(HOST_JOBS) -C $(HOST_BUILD_DIR)/init.d $(HOST_MAKE_FLAGS) install
-endef
-
-# We can't use the default, as the default passes $(MAKE_ARGS), which
-# overrides CC, CFLAGS, etc. and defeats the *_FOR_BUILD definitions
-# passed in CONFIGURE_VARS
-define Build/Compile
- $(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR)/$(MAKE_PATH)
-endef
-
-define Build/Install
- $(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR)/lib $(MAKE_INSTALL_FLAGS) install
- $(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR)/init.d $(MAKE_INSTALL_FLAGS) install
-endef
-
-define Build/InstallDev
- $(INSTALL_DIR) $(1)/usr/include
- $(CP) $(PKG_INSTALL_DIR)/usr/include/* $(1)/usr/include/
- $(INSTALL_DIR) $(1)/usr/lib/pkgconfig
- $(INSTALL_DATA) $(PKG_INSTALL_DIR)/usr/lib/pkgconfig/*.pc $(1)/usr/lib/pkgconfig/
- $(INSTALL_DIR) $(1)/usr/lib
- $(CP) $(PKG_INSTALL_DIR)/usr/lib/* $(1)/usr/lib/
-endef
-
-define Package/libaudit/install
- $(INSTALL_DIR) $(1)/usr/lib
- $(CP) $(PKG_INSTALL_DIR)/usr/lib/*.so.* $(1)/usr/lib/
- $(INSTALL_DIR) $(1)/etc
- $(CP) $(PKG_INSTALL_DIR)/etc/libaudit.conf $(1)/etc/
-endef
-
-$(eval $(call HostBuild))
-$(eval $(call BuildPackage,libaudit))
+++ /dev/null
-From c39a071e7c021f6ff3554aca2758e97b47a9777c Mon Sep 17 00:00:00 2001
-From: Steve Grubb <sgrubb@redhat.com>
-Date: Tue, 26 Feb 2019 18:33:33 -0500
-Subject: [PATCH] Add substitue functions for strndupa & rawmemchr
-
-(cherry picked from commit d579a08bb1cde71f939c13ac6b2261052ae9f77e)
-Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
----
- auparse/auparse.c | 12 +++++++++++-
- auparse/interpret.c | 9 ++++++++-
- configure.ac | 14 +++++++++++++-
- src/ausearch-lol.c | 12 +++++++++++-
- 4 files changed, 43 insertions(+), 4 deletions(-)
-
-diff --git a/auparse/auparse.c b/auparse/auparse.c
-index 650db02..2e1c737 100644
---- a/auparse/auparse.c
-+++ b/auparse/auparse.c
-@@ -1,5 +1,5 @@
- /* auparse.c --
-- * Copyright 2006-08,2012-17 Red Hat Inc., Durham, North Carolina.
-+ * Copyright 2006-08,2012-19 Red Hat Inc., Durham, North Carolina.
- * All Rights Reserved.
- *
- * This library is free software; you can redistribute it and/or
-@@ -1118,6 +1118,16 @@ static int str2event(char *s, au_event_t *e)
- return 0;
- }
-
-+#ifndef HAVE_STRNDUPA
-+static inline char *strndupa(const char *old, size_t n)
-+{
-+ size_t len = strnlen(old, n);
-+ char *tmp = alloca(len + 1);
-+ tmp[len] = 0;
-+ return memcpy(tmp, old, len);
-+}
-+#endif
-+
- /* Returns 0 on success and 1 on error */
- static int extract_timestamp(const char *b, au_event_t *e)
- {
-diff --git a/auparse/interpret.c b/auparse/interpret.c
-index 51c4a5e..67b7b77 100644
---- a/auparse/interpret.c
-+++ b/auparse/interpret.c
-@@ -853,6 +853,13 @@ err_out:
- return print_escaped(id->val);
- }
-
-+// rawmemchr is faster. Let's use it if we have it.
-+#ifdef HAVE_RAWMEMCHR
-+#define STRCHR rawmemchr
-+#else
-+#define STRCHR strchr
-+#endif
-+
- static const char *print_proctitle(const char *val)
- {
- char *out = (char *)print_escaped(val);
-@@ -863,7 +870,7 @@ static const char *print_proctitle(const char *val)
- // Proctitle has arguments separated by NUL bytes
- // We need to write over the NUL bytes with a space
- // so that we can see the arguments
-- while ((ptr = rawmemchr(ptr, '\0'))) {
-+ while ((ptr = STRCHR(ptr, '\0'))) {
- if (ptr >= end)
- break;
- *ptr = ' ';
-diff --git a/configure.ac b/configure.ac
-index 6e345f1..6f3007e 100644
---- a/configure.ac
-+++ b/configure.ac
-@@ -1,7 +1,7 @@
- dnl
- define([AC_INIT_NOTICE],
- [### Generated automatically using autoconf version] AC_ACVERSION [
--### Copyright 2005-18 Steve Grubb <sgrubb@redhat.com>
-+### Copyright 2005-19 Steve Grubb <sgrubb@redhat.com>
- ###
- ### Permission is hereby granted, free of charge, to any person obtaining a
- ### copy of this software and associated documentation files (the "Software"),
-@@ -72,6 +72,18 @@ dnl; posix_fallocate is used in audisp-remote
- AC_CHECK_FUNCS([posix_fallocate])
- dnl; signalfd is needed for libev
- AC_CHECK_FUNC([signalfd], [], [ AC_MSG_ERROR([The signalfd system call is necessary for auditd]) ])
-+dnl; check if rawmemchr is available
-+AC_CHECK_FUNCS([rawmemchr])
-+dnl; check if strndupa is available
-+AC_LINK_IFELSE(
-+ [AC_LANG_SOURCE(
-+ [[
-+ #define _GNU_SOURCE
-+ #include <string.h>
-+ int main() { (void) strndupa("test", 10); return 0; }]])],
-+ [AC_DEFINE(HAVE_STRNDUPA, 1, [Let us know if we have it or not])],
-+ []
-+)
-
- ALLWARNS=""
- ALLDEBUG="-g"
-diff --git a/src/ausearch-lol.c b/src/ausearch-lol.c
-index 5d17a72..758c33e 100644
---- a/src/ausearch-lol.c
-+++ b/src/ausearch-lol.c
-@@ -1,6 +1,6 @@
- /*
- * ausearch-lol.c - linked list of linked lists library
--* Copyright (c) 2008,2010,2014,2016 Red Hat Inc., Durham, North Carolina.
-+* Copyright (c) 2008,2010,2014,2016,2019 Red Hat Inc., Durham, North Carolina.
- * All Rights Reserved.
- *
- * This software may be freely redistributed and/or modified under the
-@@ -152,6 +152,16 @@ static int compare_event_time(event *e1, event *e2)
- return 0;
- }
-
-+#ifndef HAVE_STRNDUPA
-+static inline char *strndupa(const char *old, size_t n)
-+{
-+ size_t len = strnlen(old, n);
-+ char *tmp = alloca(len + 1);
-+ tmp[len] = 0;
-+ return memcpy(tmp, old, len);
-+}
-+#endif
-+
- /*
- * This function will look at the line and pick out pieces of it.
- */
---
-2.21.0
-
+++ /dev/null
-From 017e6c6ab95df55f34e339d2139def83e5dada1f Mon Sep 17 00:00:00 2001
-From: Steve Grubb <sgrubb@redhat.com>
-Date: Fri, 10 Jan 2020 21:13:50 -0500
-Subject: [PATCH 01/30] Header definitions need to be external when building
- with -fno-common (which is default in GCC 10) - Tony Jones
-
----
- src/ausearch-common.h | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/src/ausearch-common.h b/src/ausearch-common.h
-index 6669203..3040547 100644
---- a/src/ausearch-common.h
-+++ b/src/ausearch-common.h
-@@ -50,7 +50,7 @@ extern pid_t event_pid;
- extern int event_exact_match;
- extern uid_t event_uid, event_euid, event_loginuid;
- extern const char *event_tuid, *event_teuid, *event_tauid;
--slist *event_node_list;
-+extern slist *event_node_list;
- extern const char *event_comm;
- extern const char *event_filename;
- extern const char *event_hostname;
---
-2.26.2
-
PKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>
PKG_LICENSE:=MIT
PKG_LICENSE_FILES:=COPYING
-PKG_CPE_ID:=cpe:/a:json-c_project:json-c
+PKG_CPE_ID:=cpe:/a:json-c:json-c
HOST_BUILD_PREFIX:=$(STAGING_DIR_HOST)
PKG_CPE_ID:=cpe:/a:selinuxproject:libsemanage
-HOST_BUILD_DEPENDS:=libaudit/host libselinux/host bzip2/host
+HOST_BUILD_DEPENDS:=audit/host libselinux/host bzip2/host
include $(INCLUDE_DIR)/package.mk
include $(TOPDIR)/rules.mk
PKG_NAME:=libunwind
-PKG_VERSION:=1.6.2
+PKG_VERSION:=1.8.1
PKG_RELEASE:=1
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
-PKG_SOURCE_URL:=@SAVANNAH/$(PKG_NAME)
-PKG_HASH:=4a6aec666991fb45d0889c44aede8ad6eb108071c3554fcdff671f9c94794976
+PKG_SOURCE_URL:=https://github.com/$(PKG_NAME)/$(PKG_NAME)/releases/download/v$(PKG_VERSION)/
+PKG_HASH:=ddf0e32dd5fafe5283198d37e4bf9decf7ba1770b6e7e006c33e6df79e6a6157
PKG_MAINTAINER:=Yousong Zhou <yszhou4tech@gmail.com>
PKG_LICENSE:=X11
--- a/include/libunwind-mips.h
+++ b/include/libunwind-mips.h
-@@ -114,6 +114,42 @@ typedef enum
+@@ -121,6 +121,42 @@ typedef enum
}
mips_regnum_t;
--- a/include/libunwind-ppc32.h
+++ b/include/libunwind-ppc32.h
-@@ -74,6 +74,88 @@ typedef int64_t unw_sword_t;
+@@ -81,6 +81,88 @@ typedef int64_t unw_sword_t;
typedef long double unw_tdep_fpreg_t;
UNW_PPC32_R0,
--- a/include/libunwind-ppc64.h
+++ b/include/libunwind-ppc64.h
-@@ -81,6 +81,88 @@ typedef struct {
+@@ -88,6 +88,88 @@ typedef struct {
uint64_t halves[2];
} unw_tdep_vreg_t;
UNW_PPC64_R0,
--- a/src/ppc32/Ginit.c
+++ b/src/ppc32/Ginit.c
-@@ -46,14 +46,19 @@ static void *
+@@ -46,10 +46,15 @@ static void *
uc_addr (ucontext_t *uc, int reg)
{
void *addr;
+#endif
if ((unsigned) (reg - UNW_PPC32_R0) < 32)
+ #if defined(__linux__)
- addr = &uc->uc_mcontext.uc_regs->gregs[reg - UNW_PPC32_R0];
+ addr = &mc->gregs[reg - UNW_PPC32_R0];
-
- else
+ #elif defined(__FreeBSD__)
+ addr = &uc->uc_mcontext.mc_gpr[reg - UNW_PPC32_R0];
+ #endif
+@@ -58,7 +63,7 @@ uc_addr (ucontext_t *uc, int reg)
if ( ((unsigned) (reg - UNW_PPC32_F0) < 32) &&
((unsigned) (reg - UNW_PPC32_F0) >= 0) )
+ #if defined(__linux__)
- addr = &uc->uc_mcontext.uc_regs->fpregs.fpregs[reg - UNW_PPC32_F0];
+ addr = &mc->fpregs.fpregs[reg - UNW_PPC32_F0];
-
- else
- {
-@@ -76,7 +81,7 @@ uc_addr (ucontext_t *uc, int reg)
- default:
+ #elif defined(__FreeBSD__)
+ addr = &uc->uc_mcontext.mc_fpreg[reg - UNW_PPC32_F0];
+ #endif
+@@ -85,7 +90,7 @@ uc_addr (ucontext_t *uc, int reg)
return NULL;
}
+ #if defined(__linux__)
- addr = &uc->uc_mcontext.uc_regs->gregs[gregs_idx];
+ addr = &mc->gregs[gregs_idx];
- }
- return addr;
- }
+ #elif defined(__FreeBSD__)
+ addr = &uc->uc_mcontext.mc_gpr[gregs_idx];
+ #endif
--- a/src/ppc32/ucontext_i.h
+++ b/src/ppc32/ucontext_i.h
-@@ -46,83 +46,89 @@ WITH THE SOFTWARE OR THE USE OR OTHER DE
- various structure members. */
- static ucontext_t dmy_ctxt UNUSED;
+@@ -44,8 +44,13 @@ WITH THE SOFTWARE OR THE USE OR OTHER DE
+ //#define MQ_IDX 36
+ #define LINK_IDX 36
--#define UC_MCONTEXT_GREGS_R0 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[0] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R1 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[1] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R2 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[2] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R3 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[3] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R4 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[4] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R5 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[5] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R6 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[6] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R7 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[7] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R8 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[8] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R9 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[9] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R10 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[10] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R11 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[11] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R12 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[12] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R13 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[13] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R14 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[14] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R15 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[15] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R16 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[16] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R17 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[17] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R18 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[18] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R19 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[19] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R20 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[20] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R21 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[21] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R22 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[22] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R23 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[23] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R24 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[24] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R25 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[25] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R26 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[26] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R27 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[27] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R28 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[28] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R29 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[29] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R30 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[30] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_R31 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[31] - (void *)&dmy_ctxt)
+#ifdef __GLIBC__
-+#define UC_MCONTEXT_OFFSET(field) ((void *)&dmy_ctxt.uc_mcontext.uc_regs->field - (void *)&dmy_ctxt)
+ #define _UC_MCONTEXT_GPR(x) ( ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[x] - (void *)&dmy_ctxt) )
+ #define _UC_MCONTEXT_FPR(x) ( ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[x] - (void *)&dmy_ctxt) )
+#else
-+#define UC_MCONTEXT_OFFSET(field) ((void *)&dmy_ctxt.uc_mcontext.field - (void *)&dmy_ctxt)
++#define _UC_MCONTEXT_GPR(x) ( ((void *)&dmy_ctxt.uc_mcontext.gregs[x] - (void *)&dmy_ctxt) )
++#define _UC_MCONTEXT_FPR(x) ( ((void *)&dmy_ctxt.uc_mcontext.fpregs.fpregs[x] - (void *)&dmy_ctxt) )
+#endif
-+
-+#define UC_MCONTEXT_GREGS_R0 UC_MCONTEXT_OFFSET(gregs[0])
-+#define UC_MCONTEXT_GREGS_R1 UC_MCONTEXT_OFFSET(gregs[1])
-+#define UC_MCONTEXT_GREGS_R2 UC_MCONTEXT_OFFSET(gregs[2])
-+#define UC_MCONTEXT_GREGS_R3 UC_MCONTEXT_OFFSET(gregs[3])
-+#define UC_MCONTEXT_GREGS_R4 UC_MCONTEXT_OFFSET(gregs[4])
-+#define UC_MCONTEXT_GREGS_R5 UC_MCONTEXT_OFFSET(gregs[5])
-+#define UC_MCONTEXT_GREGS_R6 UC_MCONTEXT_OFFSET(gregs[6])
-+#define UC_MCONTEXT_GREGS_R7 UC_MCONTEXT_OFFSET(gregs[7])
-+#define UC_MCONTEXT_GREGS_R8 UC_MCONTEXT_OFFSET(gregs[8])
-+#define UC_MCONTEXT_GREGS_R9 UC_MCONTEXT_OFFSET(gregs[9])
-+#define UC_MCONTEXT_GREGS_R10 UC_MCONTEXT_OFFSET(gregs[10])
-+#define UC_MCONTEXT_GREGS_R11 UC_MCONTEXT_OFFSET(gregs[11])
-+#define UC_MCONTEXT_GREGS_R12 UC_MCONTEXT_OFFSET(gregs[12])
-+#define UC_MCONTEXT_GREGS_R13 UC_MCONTEXT_OFFSET(gregs[13])
-+#define UC_MCONTEXT_GREGS_R14 UC_MCONTEXT_OFFSET(gregs[14])
-+#define UC_MCONTEXT_GREGS_R15 UC_MCONTEXT_OFFSET(gregs[15])
-+#define UC_MCONTEXT_GREGS_R16 UC_MCONTEXT_OFFSET(gregs[16])
-+#define UC_MCONTEXT_GREGS_R17 UC_MCONTEXT_OFFSET(gregs[17])
-+#define UC_MCONTEXT_GREGS_R18 UC_MCONTEXT_OFFSET(gregs[18])
-+#define UC_MCONTEXT_GREGS_R19 UC_MCONTEXT_OFFSET(gregs[19])
-+#define UC_MCONTEXT_GREGS_R20 UC_MCONTEXT_OFFSET(gregs[20])
-+#define UC_MCONTEXT_GREGS_R21 UC_MCONTEXT_OFFSET(gregs[21])
-+#define UC_MCONTEXT_GREGS_R22 UC_MCONTEXT_OFFSET(gregs[22])
-+#define UC_MCONTEXT_GREGS_R23 UC_MCONTEXT_OFFSET(gregs[23])
-+#define UC_MCONTEXT_GREGS_R24 UC_MCONTEXT_OFFSET(gregs[24])
-+#define UC_MCONTEXT_GREGS_R25 UC_MCONTEXT_OFFSET(gregs[25])
-+#define UC_MCONTEXT_GREGS_R26 UC_MCONTEXT_OFFSET(gregs[26])
-+#define UC_MCONTEXT_GREGS_R27 UC_MCONTEXT_OFFSET(gregs[27])
-+#define UC_MCONTEXT_GREGS_R28 UC_MCONTEXT_OFFSET(gregs[28])
-+#define UC_MCONTEXT_GREGS_R29 UC_MCONTEXT_OFFSET(gregs[29])
-+#define UC_MCONTEXT_GREGS_R30 UC_MCONTEXT_OFFSET(gregs[30])
-+#define UC_MCONTEXT_GREGS_R31 UC_MCONTEXT_OFFSET(gregs[31])
-
--#define UC_MCONTEXT_GREGS_MSR ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[MSR_IDX] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_ORIG_GPR3 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[ORIG_GPR3_IDX] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_CTR ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[CTR_IDX] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_LINK ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[LINK_IDX] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_XER ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[XER_IDX] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_CCR ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[CCR_IDX] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_SOFTE ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[SOFTE_IDX] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_TRAP ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[TRAP_IDX] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_DAR ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[DAR_IDX] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_DSISR ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[DSISR_IDX] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_GREGS_RESULT ((void *)&dmy_ctxt.uc_mcontext.uc_regs->gregs[RESULT_IDX] - (void *)&dmy_ctxt)
-+#define UC_MCONTEXT_GREGS_MSR UC_MCONTEXT_OFFSET(gregs[MSR_IDX])
-+#define UC_MCONTEXT_GREGS_ORIG_GPR3 UC_MCONTEXT_OFFSET(gregs[ORIG_GPR3_IDX])
-+#define UC_MCONTEXT_GREGS_CTR UC_MCONTEXT_OFFSET(gregs[CTR_IDX])
-+#define UC_MCONTEXT_GREGS_LINK UC_MCONTEXT_OFFSET(gregs[LINK_IDX])
-+#define UC_MCONTEXT_GREGS_XER UC_MCONTEXT_OFFSET(gregs[XER_IDX])
-+#define UC_MCONTEXT_GREGS_CCR UC_MCONTEXT_OFFSET(gregs[CCR_IDX])
-+#define UC_MCONTEXT_GREGS_SOFTE UC_MCONTEXT_OFFSET(gregs[SOFTE_IDX])
-+#define UC_MCONTEXT_GREGS_TRAP UC_MCONTEXT_OFFSET(gregs[TRAP_IDX])
-+#define UC_MCONTEXT_GREGS_DAR UC_MCONTEXT_OFFSET(gregs[DAR_IDX])
-+#define UC_MCONTEXT_GREGS_DSISR UC_MCONTEXT_OFFSET(gregs[DSISR_IDX])
-+#define UC_MCONTEXT_GREGS_RESULT UC_MCONTEXT_OFFSET(gregs[RESULT_IDX])
-
--#define UC_MCONTEXT_FREGS_R0 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[0] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R1 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[1] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R2 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[2] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R3 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[3] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R4 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[4] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R5 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[5] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R6 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[6] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R7 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[7] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R8 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[8] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R9 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[9] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R10 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[10] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R11 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[11] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R12 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[12] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R13 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[13] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R14 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[14] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R15 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[15] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R16 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[16] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R17 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[17] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R18 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[18] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R19 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[19] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R20 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[20] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R21 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[21] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R22 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[22] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R23 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[23] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R24 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[24] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R25 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[25] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R26 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[26] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R27 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[27] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R28 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[28] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R29 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[29] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R30 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[30] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_R31 ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[31] - (void *)&dmy_ctxt)
--#define UC_MCONTEXT_FREGS_FPSCR ((void *)&dmy_ctxt.uc_mcontext.uc_regs->fpregs.fpregs[32] - (void *)&dmy_ctxt)
-+#define UC_MCONTEXT_FREGS_R0 UC_MCONTEXT_OFFSET(fpregs.fpregs[0])
-+#define UC_MCONTEXT_FREGS_R1 UC_MCONTEXT_OFFSET(fpregs.fpregs[1])
-+#define UC_MCONTEXT_FREGS_R2 UC_MCONTEXT_OFFSET(fpregs.fpregs[2])
-+#define UC_MCONTEXT_FREGS_R3 UC_MCONTEXT_OFFSET(fpregs.fpregs[3])
-+#define UC_MCONTEXT_FREGS_R4 UC_MCONTEXT_OFFSET(fpregs.fpregs[4])
-+#define UC_MCONTEXT_FREGS_R5 UC_MCONTEXT_OFFSET(fpregs.fpregs[5])
-+#define UC_MCONTEXT_FREGS_R6 UC_MCONTEXT_OFFSET(fpregs.fpregs[6])
-+#define UC_MCONTEXT_FREGS_R7 UC_MCONTEXT_OFFSET(fpregs.fpregs[7])
-+#define UC_MCONTEXT_FREGS_R8 UC_MCONTEXT_OFFSET(fpregs.fpregs[8])
-+#define UC_MCONTEXT_FREGS_R9 UC_MCONTEXT_OFFSET(fpregs.fpregs[9])
-+#define UC_MCONTEXT_FREGS_R10 UC_MCONTEXT_OFFSET(fpregs.fpregs[10])
-+#define UC_MCONTEXT_FREGS_R11 UC_MCONTEXT_OFFSET(fpregs.fpregs[11])
-+#define UC_MCONTEXT_FREGS_R12 UC_MCONTEXT_OFFSET(fpregs.fpregs[12])
-+#define UC_MCONTEXT_FREGS_R13 UC_MCONTEXT_OFFSET(fpregs.fpregs[13])
-+#define UC_MCONTEXT_FREGS_R14 UC_MCONTEXT_OFFSET(fpregs.fpregs[14])
-+#define UC_MCONTEXT_FREGS_R15 UC_MCONTEXT_OFFSET(fpregs.fpregs[15])
-+#define UC_MCONTEXT_FREGS_R16 UC_MCONTEXT_OFFSET(fpregs.fpregs[16])
-+#define UC_MCONTEXT_FREGS_R17 UC_MCONTEXT_OFFSET(fpregs.fpregs[17])
-+#define UC_MCONTEXT_FREGS_R18 UC_MCONTEXT_OFFSET(fpregs.fpregs[18])
-+#define UC_MCONTEXT_FREGS_R19 UC_MCONTEXT_OFFSET(fpregs.fpregs[19])
-+#define UC_MCONTEXT_FREGS_R20 UC_MCONTEXT_OFFSET(fpregs.fpregs[20])
-+#define UC_MCONTEXT_FREGS_R21 UC_MCONTEXT_OFFSET(fpregs.fpregs[21])
-+#define UC_MCONTEXT_FREGS_R22 UC_MCONTEXT_OFFSET(fpregs.fpregs[22])
-+#define UC_MCONTEXT_FREGS_R23 UC_MCONTEXT_OFFSET(fpregs.fpregs[23])
-+#define UC_MCONTEXT_FREGS_R24 UC_MCONTEXT_OFFSET(fpregs.fpregs[24])
-+#define UC_MCONTEXT_FREGS_R25 UC_MCONTEXT_OFFSET(fpregs.fpregs[25])
-+#define UC_MCONTEXT_FREGS_R26 UC_MCONTEXT_OFFSET(fpregs.fpregs[26])
-+#define UC_MCONTEXT_FREGS_R27 UC_MCONTEXT_OFFSET(fpregs.fpregs[27])
-+#define UC_MCONTEXT_FREGS_R28 UC_MCONTEXT_OFFSET(fpregs.fpregs[28])
-+#define UC_MCONTEXT_FREGS_R29 UC_MCONTEXT_OFFSET(fpregs.fpregs[29])
-+#define UC_MCONTEXT_FREGS_R30 UC_MCONTEXT_OFFSET(fpregs.fpregs[30])
-+#define UC_MCONTEXT_FREGS_R31 UC_MCONTEXT_OFFSET(fpregs.fpregs[31])
-+#define UC_MCONTEXT_FREGS_FPSCR UC_MCONTEXT_OFFSET(fpregs.fpregs[32])
- #endif
+ /* These are dummy structures used only for obtaining the offsets of the
+ various structure members. */
bool "MBEDTLS_RIPEMD160_C"
default n
-config MBEDTLS_XTEA_C
- bool "MBEDTLS_XTEA_C"
- default n
-
config MBEDTLS_RSA_NO_CRT
bool "MBEDTLS_RSA_NO_CRT"
default y
comment "Build Options - unselect features to reduce binary size"
-config MBEDTLS_CERTS_C
- bool "MBEDTLS_CERTS_C"
- default n
-
config MBEDTLS_CIPHER_MODE_OFB
bool "MBEDTLS_CIPHER_MODE_OFB"
default n
bool "MBEDTLS_SELF_TEST"
default n
-config MBEDTLS_SSL_TRUNCATED_HMAC
- bool "MBEDTLS_SSL_TRUNCATED_HMAC"
- default n
-
config MBEDTLS_THREADING_C
bool "MBEDTLS_THREADING_C"
default y
bool "MBEDTLS_VERSION_FEATURES"
default n
+config MBEDTLS_PSA_CRYPTO_CLIENT
+ bool "MBEDTLS_PSA_CRYPTO_CLIENT"
+
+config MBEDTLS_DEPRECATED_WARNING
+ bool "MBEDTLS_DEPRECATED_WARNING"
+ default n
+
+config MBEDTLS_SSL_PROTO_TLS1_2
+ bool "MBEDTLS_SSL_PROTO_TLS1_2"
+ default y
+
+config MBEDTLS_SSL_PROTO_TLS1_3
+ bool "MBEDTLS_SSL_PROTO_TLS1_3"
+ select MBEDTLS_PSA_CRYPTO_CLIENT
+ select MBEDTLS_HKDF_C
+ default y
+
+config MBEDTLS_SSL_TLS1_3_COMPATIBILITY_MODE
+ bool "MBEDTLS_SSL_TLS1_3_COMPATIBILITY_MODE"
+ depends on MBEDTLS_SSL_PROTO_TLS1_3
+ default y
+
+config MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_ENABLED
+ bool "MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_ENABLED"
+ depends on MBEDTLS_SSL_PROTO_TLS1_3
+ default y
+
+config MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED
+ bool "MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED"
+ depends on MBEDTLS_SSL_PROTO_TLS1_3
+ default y
+
+config MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL_ENABLED
+ bool "MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL_ENABLED"
+ depends on MBEDTLS_SSL_PROTO_TLS1_3
+ default y
+
comment "Build Options"
config MBEDTLS_ENTROPY_FORCE_SHA256
config MBEDTLS_SSL_RENEGOTIATION
bool "MBEDTLS_SSL_RENEGOTIATION"
+ depends on MBEDTLS_SSL_PROTO_TLS1_2
default n
endif
include $(TOPDIR)/rules.mk
PKG_NAME:=mbedtls
-PKG_VERSION:=2.28.7
-PKG_RELEASE:=2
+PKG_VERSION:=3.6.0
+PKG_RELEASE:=1
PKG_BUILD_FLAGS:=no-mips16 gc-sections no-lto
-PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
-PKG_SOURCE_URL:=https://codeload.github.com/ARMmbed/mbedtls/tar.gz/v$(PKG_VERSION)?
-PKG_HASH:=1df6073f0cf6a4e1953890bf5e0de2a8c7e6be50d6d6c69fa9fefcb1d14e981a
+PKG_SOURCE_PROTO:=git
+PKG_SOURCE_URL=https://github.com/Mbed-TLS/mbedtls.git
+PKG_SOURCE_VERSION:=2ca6c285a0dd3f33982dd57299012dacab1ff206
+PKG_MIRROR_HASH:=a684012126590b4e0b6ab41e244cc2af0d2bcfc4b6c94bf42fc37d2d08f0553e
PKG_LICENSE:=GPL-2.0-or-later
PKG_LICENSE_FILES:=gpl-2.0.txt
CONFIG_MBEDTLS_NIST_KW_C \
CONFIG_MBEDTLS_RIPEMD160_C \
CONFIG_MBEDTLS_RSA_NO_CRT \
- CONFIG_MBEDTLS_XTEA_C
+ CONFIG_MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_ENABLED \
+ CONFIG_MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED \
+ CONFIG_MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL_ENABLED
MBEDTLS_BUILD_OPTS= \
$(MBEDTLS_BUILD_OPTS_CURVES) \
$(MBEDTLS_BUILD_OPTS_CIPHERS) \
- CONFIG_MBEDTLS_CERTS_C \
CONFIG_MBEDTLS_CIPHER_MODE_OFB \
CONFIG_MBEDTLS_CIPHER_MODE_XTS \
CONFIG_MBEDTLS_DEBUG_C \
CONFIG_MBEDTLS_PLATFORM_C \
CONFIG_MBEDTLS_SELF_TEST \
CONFIG_MBEDTLS_SSL_RENEGOTIATION \
- CONFIG_MBEDTLS_SSL_TRUNCATED_HMAC \
CONFIG_MBEDTLS_THREADING_C \
CONFIG_MBEDTLS_THREADING_PTHREAD \
CONFIG_MBEDTLS_VERSION_C \
- CONFIG_MBEDTLS_VERSION_FEATURES
+ CONFIG_MBEDTLS_VERSION_FEATURES \
+ CONFIG_MBEDTLS_PSA_CRYPTO_CLIENT \
+ CONFIG_MBEDTLS_DEPRECATED_WARNING \
+ CONFIG_MBEDTLS_SSL_PROTO_TLS1_2 \
+ CONFIG_MBEDTLS_SSL_PROTO_TLS1_3 \
+ CONFIG_MBEDTLS_SSL_TLS1_3_COMPATIBILITY_MODE
PKG_CONFIG_DEPENDS := $(MBEDTLS_BUILD_OPTS)
CATEGORY:=Libraries
SUBMENU:=SSL
TITLE+= (library)
- ABI_VERSION:=13
+ ABI_VERSION:=21
MENU:=1
endef
$(if $(strip $(foreach opt,$(MBEDTLS_BUILD_OPTS),$($(opt)))),
$(foreach opt,$(MBEDTLS_BUILD_OPTS),
$(PKG_BUILD_DIR)/scripts/config.py \
- -f $(PKG_BUILD_DIR)/include/mbedtls/config.h \
+ -f $(PKG_BUILD_DIR)/include/mbedtls/mbedtls_config.h \
$(if $($(opt)),set,unset) $(patsubst CONFIG_%,%,$(opt))),)
endef
$(INSTALL_DIR) $(1)/usr/lib
$(CP) $(PKG_INSTALL_DIR)/usr/lib/lib*.so* $(1)/usr/lib/
$(CP) $(PKG_INSTALL_DIR)/usr/lib/lib*.a $(1)/usr/lib/
+ $(INSTALL_DIR) $(1)/usr/lib/pkgconfig
+ $(CP) \
+ $(PKG_INSTALL_DIR)/usr/lib/pkgconfig/mbedcrypto.pc \
+ $(PKG_INSTALL_DIR)/usr/lib/pkgconfig/mbedtls.pc \
+ $(PKG_INSTALL_DIR)/usr/lib/pkgconfig/mbedx509.pc \
+ $(1)/usr/lib/pkgconfig/
endef
define Package/libmbedtls/install
+++ /dev/null
-From eb9d4fdf1846e688d51d86a9a50f0312aca2af25 Mon Sep 17 00:00:00 2001
-From: Glenn Strauss <gstrauss@gluelogic.com>
-Date: Sun, 23 Oct 2022 19:48:18 -0400
-Subject: [PATCH] x509 crt verify SAN iPAddress
-
-Signed-off-by: Glenn Strauss <gstrauss@gluelogic.com>
----
- include/mbedtls/x509_crt.h | 2 +-
- library/x509_crt.c | 126 ++++++++++++++++++++++++++++++-------
- 2 files changed, 103 insertions(+), 25 deletions(-)
-
---- a/include/mbedtls/x509_crt.h
-+++ b/include/mbedtls/x509_crt.h
-@@ -608,7 +608,7 @@ int mbedtls_x509_crt_verify_info(char *b
- * \param cn The expected Common Name. This will be checked to be
- * present in the certificate's subjectAltNames extension or,
- * if this extension is absent, as a CN component in its
-- * Subject name. Currently only DNS names are supported. This
-+ * Subject name. DNS names and IP addresses are supported. This
- * may be \c NULL if the CN need not be verified.
- * \param flags The address at which to store the result of the verification.
- * If the verification couldn't be completed, the flag value is
---- a/library/x509_crt.c
-+++ b/library/x509_crt.c
-@@ -57,6 +57,10 @@
-
- #if defined(MBEDTLS_HAVE_TIME)
- #if defined(_WIN32) && !defined(EFIX64) && !defined(EFI32)
-+#define WIN32_LEAN_AND_MEAN
-+#ifndef _WIN32_WINNT
-+#define _WIN32_WINNT 0x0600
-+#endif
- #include <windows.h>
- #else
- #include <time.h>
-@@ -3002,6 +3006,61 @@ find_parent:
- }
- }
-
-+#ifdef _WIN32
-+#ifdef _MSC_VER
-+#pragma comment(lib, "ws2_32.lib")
-+#include <winsock2.h>
-+#include <ws2tcpip.h>
-+#elif (defined(__MINGW32__) || defined(__MINGW64__)) && _WIN32_WINNT >= 0x0600
-+#include <winsock2.h>
-+#include <ws2tcpip.h>
-+#endif
-+#elif defined(__sun)
-+/* Solaris requires -lsocket -lnsl for inet_pton() */
-+#elif defined(__has_include)
-+#if __has_include(<sys/socket.h>)
-+#include <sys/socket.h>
-+#endif
-+#if __has_include(<arpa/inet.h>)
-+#include <arpa/inet.h>
-+#endif
-+#endif
-+
-+/* Use whether or not AF_INET6 is defined to indicate whether or not to use
-+ * the platform inet_pton() or a local implementation (below). The local
-+ * implementation may be used even in cases where the platform provides
-+ * inet_pton(), e.g. when there are different includes required and/or the
-+ * platform implementation requires dependencies on additional libraries.
-+ * Specifically, Windows requires custom includes and additional link
-+ * dependencies, and Solaris requires additional link dependencies.
-+ * Also, as a coarse heuristic, use the local implementation if the compiler
-+ * does not support __has_include(), or if the definition of AF_INET6 is not
-+ * provided by headers included (or not) via __has_include() above. */
-+#ifndef AF_INET6
-+
-+#define x509_cn_inet_pton(cn, dst) (0)
-+
-+#else
-+
-+static int x509_inet_pton_ipv6(const char *src, void *dst)
-+{
-+ return inet_pton(AF_INET6, src, dst) == 1 ? 0 : -1;
-+}
-+
-+static int x509_inet_pton_ipv4(const char *src, void *dst)
-+{
-+ return inet_pton(AF_INET, src, dst) == 1 ? 0 : -1;
-+}
-+
-+#endif /* AF_INET6 */
-+
-+static size_t x509_cn_inet_pton(const char *cn, void *dst)
-+{
-+ return strchr(cn, ':') == NULL
-+ ? x509_inet_pton_ipv4(cn, dst) == 0 ? 4 : 0
-+ : x509_inet_pton_ipv6(cn, dst) == 0 ? 16 : 0;
-+}
-+
- /*
- * Check for CN match
- */
-@@ -3022,24 +3081,51 @@ static int x509_crt_check_cn(const mbedt
- return -1;
- }
-
-+static int x509_crt_check_san_ip(const mbedtls_x509_sequence *san,
-+ const char *cn, size_t cn_len)
-+{
-+ uint32_t ip[4];
-+ cn_len = x509_cn_inet_pton(cn, ip);
-+ if (cn_len == 0) {
-+ return -1;
-+ }
-+
-+ for (const mbedtls_x509_sequence *cur = san; cur != NULL; cur = cur->next) {
-+ const unsigned char san_type = (unsigned char) cur->buf.tag &
-+ MBEDTLS_ASN1_TAG_VALUE_MASK;
-+ if (san_type == MBEDTLS_X509_SAN_IP_ADDRESS &&
-+ cur->buf.len == cn_len && memcmp(cur->buf.p, ip, cn_len) == 0) {
-+ return 0;
-+ }
-+ }
-+
-+ return -1;
-+}
-+
- /*
- * Check for SAN match, see RFC 5280 Section 4.2.1.6
- */
--static int x509_crt_check_san(const mbedtls_x509_buf *name,
-+static int x509_crt_check_san(const mbedtls_x509_sequence *san,
- const char *cn, size_t cn_len)
- {
-- const unsigned char san_type = (unsigned char) name->tag &
-- MBEDTLS_ASN1_TAG_VALUE_MASK;
--
-- /* dNSName */
-- if (san_type == MBEDTLS_X509_SAN_DNS_NAME) {
-- return x509_crt_check_cn(name, cn, cn_len);
-+ int san_ip = 0;
-+ for (const mbedtls_x509_sequence *cur = san; cur != NULL; cur = cur->next) {
-+ switch ((unsigned char) cur->buf.tag & MBEDTLS_ASN1_TAG_VALUE_MASK) {
-+ case MBEDTLS_X509_SAN_DNS_NAME: /* dNSName */
-+ if (x509_crt_check_cn(&cur->buf, cn, cn_len) == 0) {
-+ return 0;
-+ }
-+ break;
-+ case MBEDTLS_X509_SAN_IP_ADDRESS: /* iPAddress */
-+ san_ip = 1;
-+ break;
-+ /* (We may handle other types here later.) */
-+ default: /* Unrecognized type */
-+ break;
-+ }
- }
-
-- /* (We may handle other types here later.) */
--
-- /* Unrecognized type */
-- return -1;
-+ return san_ip ? x509_crt_check_san_ip(san, cn, cn_len) : -1;
- }
-
- /*
-@@ -3050,31 +3136,23 @@ static void x509_crt_verify_name(const m
- uint32_t *flags)
- {
- const mbedtls_x509_name *name;
-- const mbedtls_x509_sequence *cur;
- size_t cn_len = strlen(cn);
-
- if (crt->ext_types & MBEDTLS_X509_EXT_SUBJECT_ALT_NAME) {
-- for (cur = &crt->subject_alt_names; cur != NULL; cur = cur->next) {
-- if (x509_crt_check_san(&cur->buf, cn, cn_len) == 0) {
-- break;
-- }
-- }
--
-- if (cur == NULL) {
-- *flags |= MBEDTLS_X509_BADCERT_CN_MISMATCH;
-+ if (x509_crt_check_san(&crt->subject_alt_names, cn, cn_len) == 0) {
-+ return;
- }
- } else {
- for (name = &crt->subject; name != NULL; name = name->next) {
- if (MBEDTLS_OID_CMP(MBEDTLS_OID_AT_CN, &name->oid) == 0 &&
- x509_crt_check_cn(&name->val, cn, cn_len) == 0) {
-- break;
-+ return;
- }
- }
-
-- if (name == NULL) {
-- *flags |= MBEDTLS_X509_BADCERT_CN_MISMATCH;
-- }
- }
-+
-+ *flags |= MBEDTLS_X509_BADCERT_CN_MISMATCH;
- }
-
- /*
--- a/programs/CMakeLists.txt
+++ b/programs/CMakeLists.txt
-@@ -1,12 +1,8 @@
+@@ -1,13 +1,9 @@
add_subdirectory(aes)
+ add_subdirectory(cipher)
-if (NOT WIN32)
- add_subdirectory(fuzz)
-endif()
PKG_MAINTAINER:=Shane Peelar <lookatyouhacker@gmail.com>
PKG_LICENSE:=BSD-3-Clause
PKG_LICENSE_FILES:=LICENCE
-PKG_CPE_ID:=cpe:/a:pcre:pcre
+PKG_CPE_ID:=cpe:/a:pcre:pcre2
PKG_CONFIG_DEPENDS:=\
CONFIG_PACKAGE_libpcre2-16 \
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL=$(PROJECT_GIT)/project/uclient.git
-PKG_MIRROR_HASH:=21c95854c60757007edacc579ce874999d2d536f682b0e636a8d19bc75e70da5
-PKG_SOURCE_DATE:=2024-04-05
-PKG_SOURCE_VERSION:=6c16331e4bf542fbb538d62a6b5bf3d286ecbf2c
+PKG_MIRROR_HASH:=0a0ea0752d534db87f2a13342d1b1b33fb94e43b934bdd015f96f19c635aa08c
+PKG_SOURCE_DATE:=2024-04-19
+PKG_SOURCE_VERSION:=e8780fa7792aaa2d68af21c0df91cd9c05e1f73a
CMAKE_INSTALL:=1
PKG_BUILD_DEPENDS:=ustream-ssl
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL=$(PROJECT_GIT)/project/ustream-ssl.git
-PKG_SOURCE_DATE:=2024-04-07
-PKG_SOURCE_VERSION:=d61493a4420417cbf9931ffee8c862faf04f2967
-PKG_MIRROR_HASH:=a420d775ad4928836e33e0d9423486fe4904555dbbfff283cd96370a49cf9659
+PKG_SOURCE_DATE:=2024-04-19
+PKG_SOURCE_VERSION:=524a76e5af78fa577c46e0d24bdedd4254e07cd4
+PKG_MIRROR_HASH:=638a3143013c7b60faa0e92f466a4245c635b72a7a61baa84dc9fca000991999
CMAKE_INSTALL:=1
PKG_LICENSE:=ISC
include $(TOPDIR)/rules.mk
PKG_NAME:=wolfssl
-PKG_VERSION:=5.6.6-stable
+PKG_VERSION:=5.7.0-stable
PKG_RELEASE:=1
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
PKG_SOURCE_URL:=https://github.com/wolfSSL/wolfssl/archive/v$(PKG_VERSION)
-PKG_HASH:=3d2ca672d41c2c2fa667885a80d6fa03c3e91f0f4f72f87aef2bc947e8c87237
+PKG_HASH:=2de93e8af588ee856fe67a6d7fce23fc1b226b74d710b0e3946bc8061f6aa18f
PKG_FIXUP:=libtool libtool-abiver
PKG_INSTALL:=1
--- a/wolfssl/wolfcrypt/settings.h
+++ b/wolfssl/wolfcrypt/settings.h
-@@ -2774,7 +2774,7 @@ extern void uITRON4_free(void *p) ;
+@@ -2945,7 +2945,7 @@ extern void uITRON4_free(void *p) ;
/* warning for not using harden build options (default with ./configure) */
/* do not warn if big integer support is disabled */
}
reload_service() {
- packet_steering="$(uci get "network.@globals[0].packet_steering")"
+ packet_steering="$(uci -q get "network.@globals[0].packet_steering")"
+ steering_flows="$(uci -q get "network.@globals[0].steering_flows")"
+ [ "${steering_flows:-0}" -gt 0 ] && opts="-l $steering_flows"
if [ -e "/usr/libexec/platform/packet-steering.sh" ]; then
/usr/libexec/platform/packet-steering.sh "$packet_steering"
else
- /usr/libexec/network/packet-steering.uc "$packet_steering"
+ /usr/libexec/network/packet-steering.uc $opts "$packet_steering"
fi
}
let debug = 0, do_nothing = 0;
let disable;
let cpus;
+let all_cpus;
+let local_flows = 0;
-for (let arg in ARGV) {
+while (length(ARGV) > 0) {
+ let arg = shift(ARGV);
switch (arg) {
case "-d":
debug++;
case '0':
disable = true;
break;
+ case '2':
+ all_cpus = true;
+ break;
+ case '-l':
+ local_flows = +shift(ARGV);
+ break;
}
}
system(`taskset -p -c ${cpu} ${pid}`);
}
+function cpu_mask(cpu)
+{
+ let mask;
+ if (cpu < 0)
+ mask = (1 << length(cpus)) - 1;
+ else
+ mask = (1 << int(cpu));
+ return sprintf("%x", mask);
+}
+
function set_netdev_cpu(dev, cpu) {
let queues = glob(`/sys/class/net/${dev}/queues/rx-*/rps_cpus`);
- let val = sprintf("%x", (1 << int(cpu)));
+ let val = cpu_mask(cpu);
if (disable)
val = 0;
for (let queue in queues) {
if (!do_nothing)
writefile(queue, `${val}`);
}
+ queues = glob(`/sys/class/net/${dev}/queues/rx-*/rps_flow_cnt`);
+ for (let queue in queues) {
+ if (debug || do_nothing)
+ warn(`echo ${local_flows} > ${queue}\n`);
+ if (!do_nothing)
+ writefile(queue, `${local_flows}`);
+ }
}
function task_device_match(name, device)
}
if (length(dev.netdev) > 0) {
- let cpu = dev.rx_cpu = get_next_cpu(rx_weight, dev.napi_cpu);
+ let cpu;
+ if (all_cpus)
+ cpu = -1;
+ else
+ cpu = get_next_cpu(rx_weight, dev.napi_cpu);
+ dev.rx_cpu = cpu;
for (let netdev in dev.netdev)
set_netdev_cpu(netdev, cpu);
}
PKG_NAME:=bridger
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL=https://github.com/nbd168/bridger
-PKG_SOURCE_DATE:=2024-04-15
-PKG_SOURCE_VERSION:=a08e51e679dd7e1eaf70ea7fd6b6433e167d4c2d
-PKG_MIRROR_HASH:=e80ac0cc3c5b27afb233c03fed3fbcef34a1b3fdbe0d48532ad1d5c3aac4088d
+PKG_SOURCE_DATE:=2024-04-22
+PKG_SOURCE_VERSION:=40b1c5b6be4e73a6749cf2997c664520eb20055d
+PKG_MIRROR_HASH:=b3ba2ab5ffa1af55f8da2cae5a90df486474b97ed4c359ec40c986aa6e82c300
PKG_LICENSE:=GPL-2.0
PKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>
config defaults
# handle bridge local rx/tx
- option bridge_local 0
+ option bridge_local_tx 1
+ option bridge_local_rx 0
# example for blacklisting individual devices or bridges
# list blacklist eth0
done
json_close_array
- config_get_bool bridge_local "$cfg" bridge_local 0
- json_add_boolean bridge_local "$bridge_local"
+ config_get_bool bridge_local_tx "$cfg" bridge_local_tx 1
+ json_add_boolean bridge_local_tx "$bridge_local_tx"
+
+ config_get_bool bridge_local_rx "$cfg" bridge_local_rx 0
+ json_add_boolean bridge_local_rx "$bridge_local_rx"
}
reload_service() {
PKG_LICENSE:=MIT
PKG_LICENSE_FILES:=LICENSE libtomcrypt/LICENSE libtommath/LICENSE
-PKG_CPE_ID:=cpe:/a:matt_johnston:dropbear_ssh_server
+PKG_CPE_ID:=cpe:/a:dropbear_ssh_project:dropbear_ssh
PKG_BUILD_PARALLEL:=1
PKG_ASLR_PIE_REGULAR:=1
+{
+ #if !defined(MBEDTLS_USE_PSA_CRYPTO) /* XXX: (not extracted for PSA crypto) */
+ #if defined(MBEDTLS_SSL_PROTO_TLS1_3)
-+ if (tls_version == MBEDTLS_SSL_VERSION_TLS1_3)
++ if (mbedtls_ssl_get_version_number(ssl) == MBEDTLS_SSL_VERSION_TLS1_3)
+ return 0; /* (calculation not extracted) */
+ #endif /* MBEDTLS_SSL_PROTO_TLS1_3 */
+
PKG_NAME:=lldpd
PKG_VERSION:=1.0.17
-PKG_RELEASE:=3
+PKG_RELEASE:=5
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
PKG_SOURCE_URL:=https://github.com/lldpd/lldpd/releases/download/$(PKG_VERSION)/
config_get _ifaces 'config' "$2"
local _iface _ifnames=""
+ # Set noglob to prevent '*' capturing diverse file names in the for ... in
+ set -o noglob
for _iface in $_ifaces; do
- local _ifname=""
- if network_get_device _ifname "$_iface" || [ -e "/sys/class/net/$_iface" ]; then
- append _ifnames "${_ifname:-$_iface}" ","
+
+ local _l2device=""
+ if network_get_physdev _l2device "$_iface" || [ -e "/sys/class/net/$_iface" ]; then
+ append _ifnames "${_l2device:-$_iface}" ","
+ else
+ # Glob case (interface is e.g. '!eth1' or 'eth*' or '*')
+ append _ifnames "$_iface" ","
fi
done
+ # Turn noglob off i.e. enable glob again
+ set +o noglob
export -n "${1}=$_ifnames"
}
local lldp_mgmt_ip
config_get lldp_mgmt_ip 'config' 'lldp_mgmt_ip'
- # Configurable capabilities in lldpd >= v1.0.15
+ # Configurable capabilities in lldpd >= v1.0.15: defaults to 'unconfigured' i.e. kernel info
local lldp_syscapabilities
config_get lldp_syscapabilities 'config' 'lldp_syscapabilities'
- # Configurable capabilities in lldpd >= v1.0.15
+ # Configurable capabilities in lldpd >= v1.0.15: defaults to on in lldpd
local lldp_capability_advertisements
- config_get_bool lldp_capability_advertisements 'config' 'lldp_capability_advertisements' 0
+ config_get_bool lldp_capability_advertisements 'config' 'lldp_capability_advertisements' 1
- # Broadcast management address in lldpd >= 0.7.15
+ # Broadcast management address in lldpd >= 0.7.15: defaults to on in lldpd
local lldp_mgmt_addr_advertisements
- config_get_bool lldp_mgmt_addr_advertisements 'config' 'lldp_mgmt_addr_advertisements' 0
+ config_get_bool lldp_mgmt_addr_advertisements 'config' 'lldp_mgmt_addr_advertisements' 1
if [ "$CONFIG_LLDPD_WITH_LLDPMED" = "y" ]; then
local lldpmed_fast_start
[ -n "$lldp_platform" ] && echo "configure system platform" "\"$lldp_platform\"" >> "$LLDPD_CONF"
[ -n "$lldp_tx_interval" ] && echo "configure lldp tx-interval $lldp_tx_interval" >> "$LLDPD_CONF"
[ "$lldp_tx_hold" -gt 0 ] && echo "configure lldp tx-hold $lldp_tx_hold" >> "$LLDPD_CONF"
- [ "$lldp_capability_advertisements" -gt 0 ] && echo "configure lldp capabilities-advertisements" >> "$LLDPD_CONF"
- [ "$lldp_mgmt_addr_advertisements" -gt 0 ] && echo "configure lldp management-addresses-advertisements" >> "$LLDPD_CONF"
+ [ "$lldp_capability_advertisements" -gt 0 ] && echo "configure lldp capabilities-advertisements" >> "$LLDPD_CONF" ||\
+ echo "unconfigure lldp capabilities-advertisements" >> "$LLDPD_CONF"
+ [ "$lldp_mgmt_addr_advertisements" -gt 0 ] && echo "configure lldp management-addresses-advertisements" >> "$LLDPD_CONF" ||\
+ echo "unconfigure lldp management-addresses-advertisements" >> "$LLDPD_CONF"
# Since lldpd's sysconfdir is /tmp, we'll symlink /etc/lldpd.d to /tmp/$LLDPD_CONFS_DIR
[ -e "$LLDPD_CONFS_DIR" ] || ln -s /etc/lldpd.d "$LLDPD_CONFS_DIR"
unconfigure lldp custom-tlv
unconfigure lldp capabilities-advertisements
unconfigure lldp management-addresses-advertisements
+ # unconfigures user-configured system capabilities, and instead uses the kernel information:
+ unconfigure system capabilities enabled
unconfigure system interface pattern
unconfigure system description
unconfigure system hostname
[ -n "$EXTENDPREFIX" ] && json_add_string extendprefix 1
[ -n "$IP6TABLE" ] && json_add_string ip6table $IP6TABLE
[ -n "$PEERDNS" ] && json_add_boolean peerdns $PEERDNS
+ [ "$NOSOURCEFILTER" = "1" ] && json_add_boolean sourcefilter "0"
json_close_object
ubus call network add_dynamic "$(json_dump)"
fi
proto_config_add_boolean persist
proto_config_add_int maxfail
proto_config_add_int holdoff
+ proto_config_add_boolean sourcefilter
}
ppp_generic_setup() {
local config="$1"; shift
local localip
- json_get_vars ip6table demand keepalive keepalive_adaptive username password pppd_options pppname unnumbered persist maxfail holdoff peerdns
+ json_get_vars ip6table demand keepalive keepalive_adaptive username password pppd_options pppname unnumbered persist maxfail holdoff peerdns sourcefilter
[ ! -e /proc/sys/net/ipv6 ] && ipv6=0 || json_get_var ipv6 ipv6
[ "${keepalive_adaptive:-1}" -lt 1 ] && lcp_adaptive=""
[ -n "$connect" ] || json_get_var connect connect
[ -n "$disconnect" ] || json_get_var disconnect disconnect
+ [ "$sourcefilter" = "0" ] || sourcefilter=""
proto_run_command "$config" /usr/sbin/pppd \
nodetach ipparam "$config" \
${autoipv6:+set AUTOIPV6=1} \
${ip6table:+set IP6TABLE=$ip6table} \
${peerdns:+set PEERDNS=$peerdns} \
+ ${sourcefilter:+set NOSOURCEFILTER=1} \
nodefaultroute \
usepeerdns \
$demand $persist maxfail $maxfail \
PKG_SOURCE_URL=$(PROJECT_GIT)/project/ustp.git
PKG_SOURCE_PROTO:=git
-PKG_SOURCE_DATE:=2021-09-21
-PKG_SOURCE_VERSION:=462b3a491347e452c15220861949b1d6371fa59e
-PKG_MIRROR_HASH:=c3373b369b127c26d4a79425631cb5db83ef479ab21d164da879b35942539dfb
+PKG_SOURCE_DATE:=2023-05-29
+PKG_SOURCE_VERSION:=a85a5bc83bde5b485319ca12b6e32c4b7f0b120f
+PKG_MIRROR_HASH:=b907b91989320eb8916e719ced9bdce96b8c5db6abefcee35e25fb112ad5b27f
PKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>
PKG_LICENSE:=GPL-2.0
PKG_BUILD_FLAGS:=gc-sections no-lto
PKG_BUILD_PARALLEL:=1
PKG_LICENSE:=GPL-2.0
-PKG_CPE_ID:=cpe:/a:netfilter_core_team:iptables
+PKG_CPE_ID:=cpe:/a:netfilter:iptables
include $(INCLUDE_DIR)/package.mk
ifeq ($(DUMP),)
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL=$(PROJECT_GIT)/project/uqmi.git
-PKG_SOURCE_DATE:=2024-01-16
-PKG_SOURCE_VERSION:=c3488b831ce6285c8107704156b9b8ed7d59deb3
-PKG_MIRROR_HASH:=1aa576e46dfb6528ef12f5fd1b626585d565bbcf9119cde302cc34d732c75076
+PKG_SOURCE_DATE:=2024-04-24
+PKG_SOURCE_VERSION:=e7207bec95f02f2f7a98254d642186a082af838d
+PKG_MIRROR_HASH:=53e83720472f07cb9bb3e2b68ea6c379fc8c43ed8f93227bcb3d06c94a32a669
PKG_MAINTAINER:=Matti Laakso <malaakso@elisanet.fi>
PKG_LICENSE:=GPL-2.0
TARGET_CFLAGS += \
-I$(STAGING_DIR)/usr/include \
- -Wno-error=dangling-pointer \
-Wno-error=maybe-uninitialized
CMAKE_OPTIONS += \
define Package/uqmi/install
$(INSTALL_DIR) $(1)/sbin
- $(INSTALL_BIN) $(PKG_BUILD_DIR)/uqmi $(1)/sbin/
+ $(INSTALL_BIN) $(PKG_BUILD_DIR)/uqmi/uqmi $(1)/sbin/
$(CP) ./files/* $(1)/
endef
--- /dev/null
+include $(TOPDIR)/rules.mk
+
+PKG_NAME:=apk
+PKG_RELEASE:=1
+
+PKG_SOURCE_URL=https://gitlab.alpinelinux.org/alpine/apk-tools.git
+PKG_SOURCE_PROTO:=git
+PKG_SOURCE_DATE:=2024-04-16
+PKG_SOURCE_VERSION:=ba6c31a5469ef74fb85119508e55de9631ffef41
+PKG_MIRROR_HASH:=3455d5799481add9ece3db685576d58be6303f3a13140133979b965cbd3c9966
+
+PKG_VERSION=3.0.0_pre$(subst -,,$(PKG_SOURCE_DATE))
+
+PKG_MAINTAINER:=Paul Spooren <mail@aparcar.org>
+PKG_LICENSE:=GPL-2.0-only
+PKG_LICENSE_FILES:=LICENSE
+PKG_INSTALL:=1
+
+HOST_BUILD_PREFIX:=$(STAGING_DIR_HOST)
+HOST_BUILD_DEPENDS:=lua/host
+PKG_BUILD_DEPENDS:=$(HOST_BUILD_DEPENDS)
+
+include $(INCLUDE_DIR)/package.mk
+include $(INCLUDE_DIR)/host-build.mk
+include $(INCLUDE_DIR)/meson.mk
+
+define Package/apk/default
+ SECTION:=base
+ CATEGORY:=Base system
+ TITLE:=apk package manager
+ DEPENDS:=+zlib
+ URL:=$(PKG_SOURCE_URL)
+endef
+
+define Package/apk-mbedtls
+ $(Package/apk/default)
+ TITLE += (mbedtls)
+ DEPENDS +=+libmbedtls
+ VARIANT:=mbedtls
+ DEFAULT_VARIANT:=1
+ CONFLICTS:=apk-openssl
+endef
+
+define Package/apk-openssl
+ $(Package/apk/default)
+ TITLE += (openssl)
+ DEPENDS +=+libopenssl
+ VARIANT:=openssl
+endef
+
+MESON_HOST_VARS+=VERSION=$(PKG_VERSION)
+MESON_VARS+=VERSION=$(PKG_VERSION)
+
+MESON_HOST_ARGS += \
+ -Dlua_version=5.1 \
+ -Dcompressed-help=false \
+ -Ddocs=disabled \
+ -Dcrypto_backend=openssl \
+ -Dzstd=false
+
+MESON_ARGS += \
+ -Dlua_version=5.1 \
+ -Dcompressed-help=false \
+ -Ddocs=disabled \
+ -Durl_backend=wget \
+ -Dcrypto_backend=$(BUILD_VARIANT) \
+ -Dzstd=false
+
+HOST_LDFLAGS += \
+ -Wl,-rpath $(STAGING_DIR_HOST)/lib
+
+define Package/apk/default/install
+ $(INSTALL_DIR) $(1)/lib/apk/db
+
+ $(INSTALL_DIR) $(1)/usr/bin
+ $(INSTALL_BIN) $(PKG_INSTALL_DIR)/usr/bin/apk $(1)/usr/bin/apk
+
+ $(INSTALL_DIR) $(1)/usr/lib
+ $(CP) $(PKG_INSTALL_DIR)/usr/lib/libapk.so.* $(1)/usr/lib/
+endef
+
+Package/apk-mbedtls/install = $(Package/apk/default/install)
+Package/apk-openssl/install = $(Package/apk/default/install)
+
+$(eval $(call BuildPackage,apk-mbedtls))
+$(eval $(call BuildPackage,apk-openssl))
+$(eval $(call HostBuild))
--- /dev/null
+From 9918c683fcc2f148328332d58d030ec5750a1473 Mon Sep 17 00:00:00 2001
+From: Paul Spooren <mail@aparcar.org>
+Date: Sat, 19 Feb 2022 17:20:37 +0100
+Subject: [PATCH 1/4] openwrt: move layer db to temp folder
+
+Signed-off-by: Paul Spooren <mail@aparcar.org>
+---
+ src/database.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/src/database.c
++++ b/src/database.c
+@@ -1604,7 +1604,7 @@ const char *apk_db_layer_name(int layer)
+ {
+ switch (layer) {
+ case APK_DB_LAYER_ROOT: return "lib/apk/db";
+- case APK_DB_LAYER_UVOL: return "lib/apk/db-uvol";
++ case APK_DB_LAYER_UVOL: return "tmp/run/uvol/.meta/apk";
+ default:
+ assert("invalid layer");
+ return 0;
--- /dev/null
+From 74ea482102e1a7c1845b3eec19cbdb21264836d4 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Timo=20Ter=C3=A4s?= <timo.teras@iki.fi>
+Date: Fri, 5 Apr 2024 12:06:56 +0300
+Subject: [PATCH 1/4] add alternate url wget implementation
+
+---
+ .gitlab-ci.yml | 16 ++++-
+ meson.build | 6 +-
+ meson_options.txt | 1 +
+ src/io_url_wget.c | 150 ++++++++++++++++++++++++++++++++++++++++++++++
+ src/meson.build | 4 +-
+ 5 files changed, 173 insertions(+), 4 deletions(-)
+ create mode 100644 src/io_url_wget.c
+
+diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
+index 7fc86563..b7e00008 100644
+--- a/.gitlab-ci.yml
++++ b/.gitlab-ci.yml
+@@ -24,7 +24,19 @@ test:alpine:
+ script:
+ - apk update
+ - apk add make gcc git musl-dev openssl-dev linux-headers zlib-dev zstd-dev lua5.3-dev lua5.3-lzlib meson zlib-static zstd-static openssl-libs-static
+- - meson build
++ - meson setup build -Dstatic_apk=true
++ - ninja -C build
++ tags:
++ - docker-alpine
++ - x86_64
++
++test:alpine-alt-config:
++ image: alpine
++ stage: test
++ script:
++ - apk update
++ - apk add make gcc git musl-dev openssl-dev linux-headers zlib-dev lua5.3-dev lua5.3-lzlib meson
++ - meson setup build -Durl_backend=wget -Dzstd=false
+ - ninja -C build
+ tags:
+ - docker-alpine
+@@ -38,7 +50,7 @@ test:debian:
+ - apt-get install -y make gcc git libssl-dev zlib1g-dev libzstd-dev lua5.3-dev lua5.2 lua-zlib-dev sudo meson
+ - unlink /bin/sh
+ - ln -s /bin/bash /bin/sh
+- - meson build
++ - meson setup build
+ - ninja -C build
+ tags:
+ - docker-alpine
+diff --git a/meson.build b/meson.build
+index 1a44c11f..9a14cac0 100644
+--- a/meson.build
++++ b/meson.build
+@@ -33,6 +33,10 @@ subproject = meson.is_subproject()
+
+ subdir('doc')
+ subdir('portability')
+-subdir('libfetch')
++if get_option('url_backend') == 'libfetch'
++ subdir('libfetch')
++else
++ libfetch_dep = dependency('', required: false)
++endif
+ subdir('src')
+ subdir('tests')
+diff --git a/meson_options.txt b/meson_options.txt
+index 693f46ec..940fe9a4 100644
+--- a/meson_options.txt
++++ b/meson_options.txt
+@@ -5,5 +5,6 @@ option('help', description: 'Build help into apk binaries, needs lua', type: 'fe
+ option('lua', description: 'Build luaapk (lua bindings)', type: 'feature', value: 'auto')
+ option('lua_version', description: 'Lua version to build against', type: 'string', value: '5.3')
+ option('static_apk', description: 'Also build apk.static', type: 'boolean', value: false)
++option('url_backend', description: 'URL backend', type: 'combo', choices: ['libfetch', 'wget'], value: 'libfetch')
+ option('uvol_db_target', description: 'Default target for uvol database layer', type: 'string')
+ option('zstd', description: 'Build with zstd support', type: 'boolean', value: true)
+diff --git a/src/io_url_wget.c b/src/io_url_wget.c
+new file mode 100644
+index 00000000..9a929222
+--- /dev/null
++++ b/src/io_url_wget.c
+@@ -0,0 +1,150 @@
++/* io_url_wget.c - Alpine Package Keeper (APK)
++ *
++ * Copyright (C) 2005-2008 Natanael Copa <n@tanael.org>
++ * Copyright (C) 2008-2011 Timo Teräs <timo.teras@iki.fi>
++ * All rights reserved.
++ *
++ * SPDX-License-Identifier: GPL-2.0-only
++ */
++
++#include <spawn.h>
++#include <unistd.h>
++#include <sys/wait.h>
++#include "apk_io.h"
++
++static char wget_timeout[16];
++static char wget_no_check_certificate;
++
++static int wget_translate_status(int status)
++{
++ if (!WIFEXITED(status)) return -EFAULT;
++ switch (WEXITSTATUS(status)) {
++ case 0: return 0;
++ case 3: return -EIO;
++ case 4: return -ENETUNREACH;
++ case 5: return -EACCES;
++ case 6: return -EACCES;
++ case 7: return -EPROTO;
++ default: return -APKE_REMOTE_IO;
++ }
++}
++
++struct apk_wget_istream {
++ struct apk_istream is;
++ int fd;
++ pid_t pid;
++};
++
++static int wget_spawn(const char *url, pid_t *pid, int *fd)
++{
++ int i = 0, r, pipefds[2];
++ posix_spawn_file_actions_t act;
++ char *argv[16];
++
++ argv[i++] = "wget";
++ argv[i++] = "-q";
++ argv[i++] = "-T";
++ argv[i++] = wget_timeout;
++ if (wget_no_check_certificate) argv[i++] = "--no-check-certificate";
++ argv[i++] = (char *) url;
++ argv[i++] = "-O";
++ argv[i++] = "-";
++ argv[i++] = 0;
++
++ if (pipe2(pipefds, O_CLOEXEC) != 0) return -errno;
++
++ posix_spawn_file_actions_init(&act);
++ posix_spawn_file_actions_adddup2(&act, pipefds[1], STDOUT_FILENO);
++ r = posix_spawnp(pid, "wget", &act, 0, argv, environ);
++ posix_spawn_file_actions_destroy(&act);
++ if (r != 0) return -r;
++ close(pipefds[1]);
++ *fd = pipefds[0];
++ return 0;
++}
++
++static int wget_check_exit(struct apk_wget_istream *wis)
++{
++ int status;
++
++ if (wis->pid == 0) return apk_istream_error(&wis->is, 0);
++ if (waitpid(wis->pid, &status, 0) == wis->pid) {
++ wis->pid = 0;
++ return apk_istream_error(&wis->is, wget_translate_status(status));
++ }
++ return 0;
++}
++
++static void wget_get_meta(struct apk_istream *is, struct apk_file_meta *meta)
++{
++}
++
++static ssize_t wget_read(struct apk_istream *is, void *ptr, size_t size)
++{
++ struct apk_wget_istream *wis = container_of(is, struct apk_wget_istream, is);
++ ssize_t r;
++
++ r = read(wis->fd, ptr, size);
++ if (r < 0) return -errno;
++ if (r == 0) return wget_check_exit(wis);
++ return r;
++}
++
++static int wget_close(struct apk_istream *is)
++{
++ int r = is->err;
++ struct apk_wget_istream *wis = container_of(is, struct apk_wget_istream, is);
++
++ while (wis->pid != 0)
++ wget_check_exit(wis);
++
++ close(wis->fd);
++ free(wis);
++ return r < 0 ? r : 0;
++}
++
++static const struct apk_istream_ops wget_istream_ops = {
++ .get_meta = wget_get_meta,
++ .read = wget_read,
++ .close = wget_close,
++};
++
++struct apk_istream *apk_io_url_istream(const char *url, time_t since)
++{
++ struct apk_wget_istream *wis;
++ int r;
++
++ wis = malloc(sizeof(*wis) + apk_io_bufsize);
++ if (wis == NULL) return ERR_PTR(-ENOMEM);
++
++ *wis = (struct apk_wget_istream) {
++ .is.ops = &wget_istream_ops,
++ .is.buf = (uint8_t *)(wis + 1),
++ .is.buf_size = apk_io_bufsize,
++ };
++ r = wget_spawn(url, &wis->pid, &wis->fd);
++ if (r != 0) {
++ free(wis);
++ return ERR_PTR(r);
++ }
++
++ return &wis->is;
++}
++
++void apk_io_url_no_check_certificate(void)
++{
++ wget_no_check_certificate = 1;
++}
++
++void apk_io_url_set_timeout(int timeout)
++{
++ snprintf(wget_timeout, sizeof wget_timeout, "%d", timeout);
++}
++
++void apk_io_url_set_redirect_callback(void (*cb)(int, const char *))
++{
++}
++
++void apk_io_url_init(void)
++{
++}
+diff --git a/src/meson.build b/src/meson.build
+index c1aae550..38e9d3b0 100644
+--- a/src/meson.build
++++ b/src/meson.build
+@@ -1,3 +1,5 @@
++url_backend = get_option('url_backend')
++
+ libapk_so_version = '2.99.0'
+ libapk_src = [
+ 'adb.c',
+@@ -22,8 +24,8 @@ libapk_src = [
+ 'fs_uvol.c',
+ 'hash.c',
+ 'io.c',
+- 'io_url_libfetch.c',
+ 'io_gunzip.c',
++ 'io_url_@0@.c'.format(url_backend),
+ 'package.c',
+ 'pathbuilder.c',
+ 'print.c',
+--
+GitLab
+
+
+From b9fe78fbf19bb10e1d0b8eb1cb1de123bee2ed7e Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 16 Apr 2024 17:55:15 +0200
+Subject: [PATCH 2/4] add option to configure url backend in legacy make build
+ system
+
+Can be configured by setting URL_BACKEND. If not set libfetch is
+selected by default.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ src/Makefile | 20 ++++++++++++++------
+ 1 file changed, 14 insertions(+), 6 deletions(-)
+
+diff --git a/src/Makefile b/src/Makefile
+index f7873cb1..efdc68df 100644
+--- a/src/Makefile
++++ b/src/Makefile
+@@ -9,8 +9,8 @@ else
+ $(error Lua interpreter not found. Please specify LUA interpreter, or use LUA=no to build without help.)
+ endif
+
+-OPENSSL_CFLAGS := $(shell $(PKG_CONFIG) --cflags openssl)
+-OPENSSL_LIBS := $(shell $(PKG_CONFIG) --libs openssl)
++OPENSSL_CFLAGS := $(shell $(PKG_CONFIG) --cflags openssl)
++OPENSSL_LIBS := $(shell $(PKG_CONFIG) --libs openssl)
+
+ ZLIB_CFLAGS := $(shell $(PKG_CONFIG) --cflags zlib)
+ ZLIB_LIBS := $(shell $(PKG_CONFIG) --libs zlib)
+@@ -21,10 +21,18 @@ libapk_so := $(obj)/libapk.so.$(libapk_soname)
+ libapk.so.$(libapk_soname)-objs := \
+ adb.o adb_comp.o adb_walk_adb.o adb_walk_genadb.o adb_walk_gentext.o adb_walk_text.o apk_adb.o \
+ atom.o blob.o commit.o common.o context.o crypto.o crypto_openssl.o ctype.o database.o hash.o \
+- extract_v2.o extract_v3.o fs_fsys.o fs_uvol.o io.o io_gunzip.o io_url_libfetch.o \
+- tar.o package.o pathbuilder.o print.o solver.o trust.o version.o
++ extract_v2.o extract_v3.o fs_fsys.o fs_uvol.o io.o io_gunzip.o tar.o package.o pathbuilder.o \
++ print.o solver.o trust.o version.o
+
+-libapk.so.$(libapk_soname)-libs := libfetch/libfetch.a
++libapk.so.$(libapk_soname)-libs :=
++
++ifeq ($(URL_BACKEND),wget)
++libapk.so.$(libapk_soname)-objs += io_url_wget.o
++else
++CFLAGS_ALL += -Ilibfetch
++libapk.so.$(libapk_soname)-objs += io_url_libfetch.o
++libapk.so.$(libapk_soname)-libs += libfetch/libfetch.a
++endif
+
+ # ZSTD support can be disabled
+ ifneq ($(ZSTD),no)
+@@ -79,7 +87,7 @@ LIBS_apk := -lapk
+ LIBS_apk-test := -lapk
+ LIBS_apk.so := -L$(obj) -lapk
+
+-CFLAGS_ALL += -D_ATFILE_SOURCE -Ilibfetch -Iportability
++CFLAGS_ALL += -D_ATFILE_SOURCE -Iportability
+ CFLAGS_apk.o := -DAPK_VERSION=\"$(VERSION)\"
+ CFLAGS_apk-static.o := -DAPK_VERSION=\"$(VERSION)\" -DOPENSSL_NO_ENGINE
+ CFLAGS_apk-test.o := -DAPK_VERSION=\"$(VERSION)\" -DOPENSSL_NO_ENGINE -DTEST_MODE
+--
+GitLab
+
+
+From 0418b684898403c49905c1f0e4b7c5ca522b2d50 Mon Sep 17 00:00:00 2001
+From: Jonas Jelonek <jelonek.jonas@gmail.com>
+Date: Sun, 14 Apr 2024 00:20:14 +0200
+Subject: [PATCH 3/4] crypto: add support for mbedtls as backend
+
+backend is selected at compile-time with crypto_backend option
+
+Co-developed-by: Christian Marangi <ansuelsmth@gmail.com>
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
+---
+ libfetch/meson.build | 2 +-
+ meson.build | 14 +-
+ meson_options.txt | 1 +
+ portability/getrandom.c | 19 +++
+ portability/meson.build | 3 +-
+ portability/sys/random.h | 6 +
+ src/apk_crypto.h | 5 +
+ src/apk_crypto_mbedtls.h | 30 +++++
+ src/crypto_mbedtls.c | 285 +++++++++++++++++++++++++++++++++++++++
+ src/meson.build | 21 ++-
+ 10 files changed, 373 insertions(+), 13 deletions(-)
+ create mode 100644 portability/getrandom.c
+ create mode 100644 portability/sys/random.h
+ create mode 100644 src/apk_crypto_mbedtls.h
+ create mode 100644 src/crypto_mbedtls.c
+
+diff --git a/libfetch/meson.build b/libfetch/meson.build
+index 431ba197..e24f95eb 100644
+--- a/libfetch/meson.build
++++ b/libfetch/meson.build
+@@ -40,7 +40,7 @@ libfetch = static_library(
+ c_args: libfetch_cargs,
+ dependencies: [
+ libportability_dep.partial_dependency(compile_args: true, includes: true),
+- openssl_dep.partial_dependency(compile_args: true, includes: true)
++ crypto_dep.partial_dependency(compile_args: true, includes: true)
+ ],
+ )
+
+diff --git a/meson.build b/meson.build
+index 9a14cac0..3a83f4e1 100644
+--- a/meson.build
++++ b/meson.build
+@@ -13,15 +13,21 @@ apk_libdir = get_option('libdir')
+ lua_bin = find_program('lua' + get_option('lua_version'), required: get_option('help'))
+ lua_dep = dependency('lua' + get_option('lua_version'), required: get_option('lua'))
+ scdoc_dep = dependency('scdoc', version: '>=1.10', required: get_option('docs'))
+-openssl_dep = dependency('openssl')
+-openssl_static_dep = dependency('openssl', static: true)
+ zlib_dep = dependency('zlib')
+ zlib_static_dep = dependency('zlib', static: true)
+ libzstd_dep = dependency('libzstd', required: get_option('zstd'))
+ libzstd_static_dep = dependency('libzstd', required: get_option('zstd'), static: true)
+
+-shared_deps = [ openssl_dep, zlib_dep, libzstd_dep ]
+-static_deps = [ openssl_static_dep, zlib_static_dep, libzstd_static_dep ]
++if get_option('crypto_backend') == 'openssl'
++ crypto_dep = dependency('openssl')
++ crypto_static_dep = dependency('openssl', static: true)
++elif get_option('crypto_backend') == 'mbedtls'
++ crypto_dep = [ dependency('mbedtls'), dependency('mbedcrypto') ]
++ crypto_static_dep = [ dependency('mbedtls', static: true), dependency('mbedcrypto', static: true) ]
++endif
++
++shared_deps = [ crypto_dep, zlib_dep, libzstd_dep ]
++static_deps = [ crypto_static_dep, zlib_static_dep, libzstd_static_dep ]
+
+ add_project_arguments('-D_GNU_SOURCE', language: 'c')
+
+diff --git a/meson_options.txt b/meson_options.txt
+index 940fe9a4..df0b07dc 100644
+--- a/meson_options.txt
++++ b/meson_options.txt
+@@ -1,4 +1,5 @@
+ option('arch_prefix', description: 'Define a custom arch prefix for default arch', type: 'string')
++option('crypto_backend', description: 'Crypto backend', type: 'combo', choices: ['openssl', 'mbedtls'], value: 'openssl')
+ option('compressed-help', description: 'Compress help database, needs lua-zlib', type: 'boolean', value: true)
+ option('docs', description: 'Build manpages with scdoc', type: 'feature', value: 'auto')
+ option('help', description: 'Build help into apk binaries, needs lua', type: 'feature', value: 'auto')
+diff --git a/portability/getrandom.c b/portability/getrandom.c
+new file mode 100644
+index 00000000..b2f4a07c
+--- /dev/null
++++ b/portability/getrandom.c
+@@ -0,0 +1,19 @@
++#include <sys/random.h>
++#include <sys/types.h>
++#include <unistd.h>
++#include <fcntl.h>
++
++ssize_t getrandom(void *buf, size_t buflen, unsigned int flags)
++{
++ int fd;
++ ssize_t ret;
++
++ fd = open("/dev/urandom", O_RDONLY|O_CLOEXEC);
++ if (fd < 0)
++ return -1;
++
++ ret = read(fd, buf, buflen);
++ close(fd);
++ return ret;
++}
++
+diff --git a/portability/meson.build b/portability/meson.build
+index 89957c3c..3172044e 100644
+--- a/portability/meson.build
++++ b/portability/meson.build
+@@ -3,7 +3,8 @@ cc = meson.get_compiler('c')
+ libportability_src = []
+
+ check_symbols = [
+- ['memrchr', 'memrchr.c', 'NEED_MEMRCHR', 'string.h'],
++ ['getrandom', 'getrandom.c', 'NEED_GETRANDOM', 'sys/random.h'],
++ ['memrchr', 'memrchr.c', 'NEED_MEMRCHR', 'string.h'],
+ ['mknodat', 'mknodat.c', 'NEED_MKNODAT', 'sys/stat.h'],
+ ['pipe2', 'pipe2.c', 'NEED_PIPE2', 'unistd.h'],
+ ['qsort_r', 'qsort_r.c', 'NEED_QSORT_R', 'stdlib.h'],
+diff --git a/portability/sys/random.h b/portability/sys/random.h
+new file mode 100644
+index 00000000..02d5b1ca
+--- /dev/null
++++ b/portability/sys/random.h
+@@ -0,0 +1,6 @@
++#include_next <sys/random.h>
++#include <sys/types.h>
++
++#ifdef NEED_GETRANDOM
++ssize_t getrandom(void *buf, size_t buflen, unsigned int flags);
++#endif
+diff --git a/src/apk_crypto.h b/src/apk_crypto.h
+index 7de88dfc..5cae3bfe 100644
+--- a/src/apk_crypto.h
++++ b/src/apk_crypto.h
+@@ -12,7 +12,12 @@
+ #include <string.h>
+ #include "apk_defines.h"
+ #include "apk_blob.h"
++
++#if defined(CRYPTO_USE_OPENSSL)
+ #include "apk_crypto_openssl.h"
++#elif defined(CRYPTO_USE_MBEDTLS)
++#include "apk_crypto_mbedtls.h"
++#endif
+
+ // Digest
+
+diff --git a/src/apk_crypto_mbedtls.h b/src/apk_crypto_mbedtls.h
+new file mode 100644
+index 00000000..5481d149
+--- /dev/null
++++ b/src/apk_crypto_mbedtls.h
+@@ -0,0 +1,30 @@
++/* apk_crypto_mbedtls.h - Alpine Package Keeper (APK)
++ *
++ * Copyright (C) 2024
++ * All rights reserved.
++ *
++ * SPDX-License-Identifier: GPL-2.0-only
++ */
++
++#ifndef APK_CRYPTO_MBEDTLS_H
++#define APK_CRYPTO_MBEDTLS_H
++
++#include <mbedtls/md.h>
++#include <mbedtls/pk.h>
++#include <mbedtls/bignum.h>
++
++struct apk_pkey {
++ uint8_t id[16];
++ mbedtls_pk_context key;
++};
++
++struct apk_digest_ctx {
++ mbedtls_md_context_t mdctx;
++ struct apk_pkey *sigver_key;
++ uint8_t alg;
++};
++
++/* based on mbedtls' internal pkwrite.h calculations */
++#define APK_ENC_KEY_MAX_LENGTH (38 + 2 * MBEDTLS_MPI_MAX_SIZE)
++
++#endif
+diff --git a/src/crypto_mbedtls.c b/src/crypto_mbedtls.c
+new file mode 100644
+index 00000000..73d60e9d
+--- /dev/null
++++ b/src/crypto_mbedtls.c
+@@ -0,0 +1,285 @@
++#include <errno.h>
++#include <stdio.h>
++#include <stdlib.h>
++#include <fcntl.h>
++#include <sys/random.h>
++#include <sys/stat.h>
++#include <unistd.h>
++
++#include <mbedtls/platform.h>
++#include <mbedtls/md.h>
++#include <mbedtls/pk.h>
++#include <mbedtls/entropy.h>
++
++#ifdef MBEDTLS_PSA_CRYPTO_C
++#include <psa/crypto.h>
++#endif
++
++#include "apk_crypto.h"
++
++static inline const mbedtls_md_type_t apk_digest_alg_to_mbedtls_type(uint8_t alg) {
++ switch (alg) {
++ case APK_DIGEST_NONE: return MBEDTLS_MD_NONE;
++ case APK_DIGEST_MD5: return MBEDTLS_MD_MD5;
++ case APK_DIGEST_SHA1: return MBEDTLS_MD_SHA1;
++ case APK_DIGEST_SHA256_160:
++ case APK_DIGEST_SHA256: return MBEDTLS_MD_SHA256;
++ case APK_DIGEST_SHA512: return MBEDTLS_MD_SHA512;
++ default:
++ assert(alg);
++ return MBEDTLS_MD_NONE;
++ }
++}
++
++static inline const mbedtls_md_info_t *apk_digest_alg_to_mdinfo(uint8_t alg)
++{
++ return mbedtls_md_info_from_type(
++ apk_digest_alg_to_mbedtls_type(alg)
++ );
++}
++
++int apk_digest_calc(struct apk_digest *d, uint8_t alg, const void *ptr, size_t sz)
++{
++ if (mbedtls_md(apk_digest_alg_to_mdinfo(alg), ptr, sz, d->data))
++ return -APKE_CRYPTO_ERROR;
++
++ apk_digest_set(d, alg);
++ return 0;
++}
++
++int apk_digest_ctx_init(struct apk_digest_ctx *dctx, uint8_t alg)
++{
++ dctx->alg = alg;
++
++ mbedtls_md_init(&dctx->mdctx);
++ if (alg == APK_DIGEST_NONE) return 0;
++ if (mbedtls_md_setup(&dctx->mdctx, apk_digest_alg_to_mdinfo(alg), 0) ||
++ mbedtls_md_starts(&dctx->mdctx))
++ return -APKE_CRYPTO_ERROR;
++
++ return 0;
++}
++
++int apk_digest_ctx_reset(struct apk_digest_ctx *dctx)
++{
++ if (dctx->alg == APK_DIGEST_NONE) return 0;
++ if (mbedtls_md_starts(&dctx->mdctx)) return -APKE_CRYPTO_ERROR;
++ return 0;
++}
++
++int apk_digest_ctx_reset_alg(struct apk_digest_ctx *dctx, uint8_t alg)
++{
++ mbedtls_md_free(&dctx->mdctx);
++
++ dctx->alg = alg;
++ if (alg == APK_DIGEST_NONE) return 0;
++ if (mbedtls_md_setup(&dctx->mdctx, apk_digest_alg_to_mdinfo(alg), 0) ||
++ mbedtls_md_starts(&dctx->mdctx))
++ return -APKE_CRYPTO_ERROR;
++
++ return 0;
++}
++
++void apk_digest_ctx_free(struct apk_digest_ctx *dctx)
++{
++ mbedtls_md_free(&dctx->mdctx);
++}
++
++int apk_digest_ctx_update(struct apk_digest_ctx *dctx, const void *ptr, size_t sz)
++{
++ if (dctx->alg == APK_DIGEST_NONE) return 0;
++ return mbedtls_md_update(&dctx->mdctx, ptr, sz) == 0 ? 0 : -APKE_CRYPTO_ERROR;
++}
++
++int apk_digest_ctx_final(struct apk_digest_ctx *dctx, struct apk_digest *d)
++{
++ if (mbedtls_md_finish(&dctx->mdctx, d->data)) {
++ apk_digest_reset(d);
++ return -APKE_CRYPTO_ERROR;
++ }
++
++ d->alg = dctx->alg;
++ d->len = apk_digest_alg_len(d->alg);
++ return 0;
++}
++
++static int apk_load_file_at(int dirfd, const char *fn, unsigned char **buf, size_t *n)
++{
++ struct stat stats;
++ size_t size;
++ int fd;
++
++ if ((fd = openat(dirfd, fn, O_RDONLY|O_CLOEXEC)) < 0)
++ return -errno;
++
++ if (fstat(fd, &stats)) {
++ close(fd);
++ return -errno;
++ }
++
++ size = (size_t)stats.st_size;
++ *n = size;
++
++ if (size == 0 || (*buf = mbedtls_calloc(1, size + 1)) == NULL)
++ return MBEDTLS_ERR_PK_ALLOC_FAILED;
++
++ if (read(fd, *buf, size) != size) {
++ close(fd);
++
++ mbedtls_platform_zeroize(*buf, size);
++ mbedtls_free(*buf);
++
++ return MBEDTLS_ERR_PK_FILE_IO_ERROR;
++ }
++ close(fd);
++
++ (*buf)[size] = '\0';
++
++ if (strstr((const char *) *buf, "-----BEGIN ") != NULL) {
++ ++*n;
++ }
++
++ return 0;
++}
++
++static int apk_pkey_init(struct apk_pkey *pkey)
++{
++ unsigned char dig[APK_DIGEST_MAX_LENGTH];
++ unsigned char pub[APK_ENC_KEY_MAX_LENGTH] = {};
++ unsigned char *c;
++ int len, r = -APKE_CRYPTO_ERROR;
++
++ c = pub + APK_ENC_KEY_MAX_LENGTH;
++
++ // key is written backwards into pub starting at c!
++ if ((len = mbedtls_pk_write_pubkey(&c, pub, &pkey->key)) < 0) return -APKE_CRYPTO_ERROR;
++ if (!mbedtls_md(apk_digest_alg_to_mdinfo(APK_DIGEST_SHA512), c, len, dig)) {
++ memcpy(pkey->id, dig, sizeof pkey->id);
++ r = 0;
++ }
++
++ return r;
++}
++
++void apk_pkey_free(struct apk_pkey *pkey)
++{
++ mbedtls_pk_free(&pkey->key);
++}
++
++static int apk_random(void *ctx, unsigned char *out, size_t len)
++{
++ return (int)getrandom(out, len, 0);
++}
++
++#if MBEDTLS_VERSION_NUMBER >= 0x03000000
++static inline int apk_mbedtls_parse_privkey(struct apk_pkey *pkey, const unsigned char *buf, size_t blen)
++{
++ return mbedtls_pk_parse_key(&pkey->key, buf, blen, NULL, 0, apk_random, NULL);
++}
++static inline int apk_mbedtls_sign(struct apk_digest_ctx *dctx, struct apk_digest *dig,
++ unsigned char *sig, size_t *sig_len)
++{
++ return mbedtls_pk_sign(&dctx->sigver_key->key, apk_digest_alg_to_mbedtls_type(dctx->alg),
++ (const unsigned char *)&dig->data, dig->len, sig, sizeof *sig, sig_len,
++ apk_random, NULL);
++}
++#else
++static inline int apk_mbedtls_parse_privkey(struct apk_pkey *pkey, const unsigned char *buf, size_t blen)
++{
++ return mbedtls_pk_parse_key(&pkey->key, buf, blen, NULL, 0);
++}
++static inline int apk_mbedtls_sign(struct apk_digest_ctx *dctx, struct apk_digest *dig,
++ unsigned char *sig, size_t *sig_len)
++{
++ return mbedtls_pk_sign(&dctx->sigver_key->key, apk_digest_alg_to_mbedtls_type(dctx->alg),
++ (const unsigned char *)&dig->data, dig->len, sig, sig_len, apk_random, NULL);
++}
++#endif
++
++int apk_pkey_load(struct apk_pkey *pkey, int dirfd, const char *fn)
++{
++ unsigned char *buf = NULL;
++ size_t blen = 0;
++ int ret;
++
++ if (apk_load_file_at(dirfd, fn, &buf, &blen))
++ return -APKE_CRYPTO_ERROR;
++
++ mbedtls_pk_init(&pkey->key);
++ if ((ret = mbedtls_pk_parse_public_key(&pkey->key, buf, blen)) != 0)
++ ret = apk_mbedtls_parse_privkey(pkey, buf, blen);
++
++ mbedtls_platform_zeroize(buf, blen);
++ mbedtls_free(buf);
++ if (ret != 0)
++ return -APKE_CRYPTO_KEY_FORMAT;
++
++ return apk_pkey_init(pkey);
++}
++
++int apk_sign_start(struct apk_digest_ctx *dctx, uint8_t alg, struct apk_pkey *pkey)
++{
++ if (apk_digest_ctx_reset_alg(dctx, alg))
++ return -APKE_CRYPTO_ERROR;
++
++ dctx->sigver_key = pkey;
++
++ return 0;
++}
++
++int apk_sign(struct apk_digest_ctx *dctx, void *sig, size_t *len)
++{
++ struct apk_digest dig;
++ int r = 0;
++
++ if (apk_digest_ctx_final(dctx, &dig))
++ return -APKE_SIGNATURE_GEN_FAILURE;
++
++ if (apk_mbedtls_sign(dctx, &dig, sig, len))
++ r = -APKE_SIGNATURE_GEN_FAILURE;
++
++ dctx->sigver_key = NULL;
++ return r;
++}
++
++int apk_verify_start(struct apk_digest_ctx *dctx, uint8_t alg, struct apk_pkey *pkey)
++{
++ if (apk_digest_ctx_reset_alg(dctx, alg))
++ return -APKE_CRYPTO_ERROR;
++
++ dctx->sigver_key = pkey;
++
++ return 0;
++}
++
++int apk_verify(struct apk_digest_ctx *dctx, void *sig, size_t len)
++{
++ struct apk_digest dig;
++ int r = 0;
++
++ if (apk_digest_ctx_final(dctx, &dig))
++ return -APKE_SIGNATURE_GEN_FAILURE;
++
++ if (mbedtls_pk_verify(&dctx->sigver_key->key, apk_digest_alg_to_mbedtls_type(dctx->alg),
++ (const unsigned char *)&dig.data, dig.len, sig, len))
++ r = -APKE_SIGNATURE_INVALID;
++
++ dctx->sigver_key = NULL;
++ return r;
++}
++
++static void apk_crypto_cleanup(void)
++{
++#ifdef MBEDTLS_PSA_CRYPTO_C
++ mbedtls_psa_crypto_free();
++#endif
++}
++
++void apk_crypto_init(void)
++{
++ atexit(apk_crypto_cleanup);
++
++#ifdef MBEDTLS_PSA_CRYPTO_C
++ psa_crypto_init();
++#endif
++}
+diff --git a/src/meson.build b/src/meson.build
+index 38e9d3b0..e1204fc0 100644
+--- a/src/meson.build
++++ b/src/meson.build
+@@ -1,3 +1,4 @@
++crypto_backend = get_option('crypto_backend')
+ url_backend = get_option('url_backend')
+
+ libapk_so_version = '2.99.0'
+@@ -15,7 +16,7 @@ libapk_src = [
+ 'common.c',
+ 'context.c',
+ 'crypto.c',
+- 'crypto_openssl.c',
++ 'crypto_@0@.c'.format(crypto_backend),
+ 'ctype.c',
+ 'database.c',
+ 'extract_v2.c',
+@@ -40,7 +41,7 @@ libapk_headers = [
+ 'apk_atom.h',
+ 'apk_blob.h',
+ 'apk_crypto.h',
+- 'apk_crypto_openssl.h',
++ 'apk_crypto_@0@.h'.format(crypto_backend),
+ 'apk_ctype.h',
+ 'apk_database.h',
+ 'apk_defines.h',
+@@ -89,6 +90,17 @@ apk_src = [
+ 'applet.c',
+ ]
+
++apk_cargs = [
++ '-DAPK_VERSION="' + meson.project_version() + '"',
++ '-D_ATFILE_SOURCE',
++]
++
++if crypto_backend == 'openssl'
++ apk_cargs += [ '-DCRYPTO_USE_OPENSSL' ]
++elif crypto_backend == 'mbedtls'
++ apk_cargs += [ '-DCRYPTO_USE_MBEDTLS' ]
++endif
++
+ if lua_bin.found()
+ genhelp_script = files('genhelp.lua')
+ genhelp_args = [lua_bin, genhelp_script, '@INPUT@']
+@@ -115,11 +127,6 @@ endif
+
+ apk_src += [ generated_help ]
+
+-apk_cargs = [
+- '-DAPK_VERSION="' + meson.project_version() + '"',
+- '-D_ATFILE_SOURCE',
+-]
+-
+ apk_arch_prefix = get_option('arch_prefix')
+ if apk_arch_prefix != ''
+ apk_cargs += ['-DAPK_ARCH_PREFIX="@0@"'.format(apk_arch_prefix)]
+--
+GitLab
+
+
+From 34bb1021284dccbf97f02b0a0bb9e751b8887cad Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 16 Apr 2024 17:56:45 +0200
+Subject: [PATCH 4/4] add option to configure crypto backend in legacy make
+ build system
+
+Define CRYPTO to select mbedtls as alternative crypto backend. By
+default openssl is used.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ src/Makefile | 20 +++++++++++++++-----
+ 1 file changed, 15 insertions(+), 5 deletions(-)
+
+diff --git a/src/Makefile b/src/Makefile
+index efdc68df..97db0e72 100644
+--- a/src/Makefile
++++ b/src/Makefile
+@@ -20,9 +20,9 @@ libapk_soname := 2.99.0
+ libapk_so := $(obj)/libapk.so.$(libapk_soname)
+ libapk.so.$(libapk_soname)-objs := \
+ adb.o adb_comp.o adb_walk_adb.o adb_walk_genadb.o adb_walk_gentext.o adb_walk_text.o apk_adb.o \
+- atom.o blob.o commit.o common.o context.o crypto.o crypto_openssl.o ctype.o database.o hash.o \
+- extract_v2.o extract_v3.o fs_fsys.o fs_uvol.o io.o io_gunzip.o tar.o package.o pathbuilder.o \
+- print.o solver.o trust.o version.o
++ atom.o blob.o commit.o common.o context.o crypto.o ctype.o database.o hash.o extract_v2.o \
++ extract_v3.o fs_fsys.o fs_uvol.o io.o io_gunzip.o tar.o package.o pathbuilder.o print.o \
++ solver.o trust.o version.o
+
+ libapk.so.$(libapk_soname)-libs :=
+
+@@ -34,6 +34,16 @@ libapk.so.$(libapk_soname)-objs += io_url_libfetch.o
+ libapk.so.$(libapk_soname)-libs += libfetch/libfetch.a
+ endif
+
++ifeq ($(CRYPTO),mbedtls)
++CRYPTO_CFLAGS := $(shell $(PKG_CONFIG) --cflags mbedtls mbedcrypto) -DCRYPTO_USE_MBEDTLS
++CRYPTO_LIBS := $(shell $(PKG_CONFIG) --libs mbedtls mbedcrypto)
++libapk.so.$(libapk_soname)-objs += crypto_mbedtls.o
++else
++CRYPTO_CFLAGS := $(shell $(PKG_CONFIG) --cflags openssl) -DCRYPTO_USE_OPENSSL
++CRYPTO_LIBS := $(shell $(PKG_CONFIG) --libs openssl)
++libapk.so.$(libapk_soname)-objs += crypto_openssl.o
++endif
++
+ # ZSTD support can be disabled
+ ifneq ($(ZSTD),no)
+ ZSTD_CFLAGS := $(shell $(PKG_CONFIG) --cflags libzstd)
+@@ -100,9 +110,9 @@ LIBS_apk.static := -Wl,--as-needed -ldl -Wl,--no-as-needed
+ LDFLAGS_apk += -L$(obj)
+ LDFLAGS_apk-test += -L$(obj)
+
+-CFLAGS_ALL += $(OPENSSL_CFLAGS) $(ZLIB_CFLAGS) $(ZSTD_CFLAGS)
++CFLAGS_ALL += $(CRYPTO_CFLAGS) $(ZLIB_CFLAGS) $(ZSTD_CFLAGS)
+ LIBS := -Wl,--as-needed \
+- $(OPENSSL_LIBS) $(ZLIB_LIBS) $(ZSTD_LIBS) \
++ $(CRYPTO_LIBS) $(ZLIB_LIBS) $(ZSTD_LIBS) \
+ -Wl,--no-as-needed
+
+ # Help generation
+--
+GitLab
}
procd_add_mdns_service() {
- local service proto port
+ local service proto port txt_count=0
service=$1; shift
proto=$1; shift
port=$1; shift
json_add_object "${service}_$port"
json_add_string "service" "_$service._$proto.local"
json_add_int port "$port"
- [ -n "$1" ] && {
- json_add_array txt
- for txt in "$@"; do json_add_string "" "$txt"; done
- json_select ..
- }
+ for txt in "$@"; do
+ [ -z "$txt" ] && continue
+ txt_count=$((txt_count+1))
+ [ $txt_count -eq 1 ] && json_add_array txt
+ json_add_string "" "$txt"
+ done
+ [ $txt_count -gt 0 ] && json_select ..
+
json_select ..
}
include $(TOPDIR)/rules.mk
PKG_NAME:=ubox
-PKG_RELEASE:=2
+PKG_RELEASE:=1
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL=$(PROJECT_GIT)/project/ubox.git
-PKG_SOURCE_DATE:=2024-01-24
-PKG_SOURCE_VERSION:=2c5887cb46883a28d69071c4349c3dabbbe3972c
-PKG_MIRROR_HASH:=5b7b00c358cc53b842c25e6f6dd21bf429d4913204a8186a72b13447658927cf
+PKG_SOURCE_DATE:=2024-04-26
+PKG_SOURCE_VERSION:=85f1053019caf4cd333795760950235ee4529ba7
+PKG_MIRROR_HASH:=9e3fb6ab94854405fb91626a673b0547a061582c552ce719691be1bc8818da6c
CMAKE_INSTALL:=1
PKG_LICENSE:=GPL-2.0
--- /dev/null
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+include $(TOPDIR)/rules.mk
+
+PKG_NAME:=audit-userspace
+PKG_VERSION:=3.1.4
+PKG_RELEASE:=1
+PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
+PKG_SOURCE_URL:=https://github.com/linux-audit/audit-userspace/archive/refs/tags/v$(PKG_VERSION).tar.gz?
+PKG_HASH:=aec501760acd13ebbe00e78b9b59f795d16a430b1d673628e346cd18905c594b
+PKG_MAINTAINER:=Thomas Petazzoni <thomas.petazzoni@bootlin.com>
+PKG_LICENSE:=GPL-2.0-or-later
+PKG_LICENSE_FILES:=COPYING
+PKG_CPE_ID:=cpe:/a:linux_audit_project:linux_audit
+
+PKG_CONFIG_DEPENDS:=CONFIG_KERNEL_IO_URING
+PKG_FIXUP:=autoreconf
+
+PKG_BUILD_FLAGS:=no-mips16
+PKG_INSTALL:=1
+
+include $(INCLUDE_DIR)/package.mk
+include $(INCLUDE_DIR)/host-build.mk
+
+define Package/audit/Default
+ TITLE:=Audit
+ URL:=https://github.com/linux-audit/
+endef
+
+define Package/audit/Default/description
+ The audit package contains the user space utilities for
+ storing and searching the audit records generated by
+ the audit subsystem in the kernel.
+endef
+
+define Package/libaudit
+$(call Package/audit/Default)
+ SECTION:=libs
+ CATEGORY:=Libraries
+ TITLE+= (libaudit)
+endef
+
+define Package/libaudit/description
+$(call Package/audit/Default/description)
+ This package contains the audit shared library.
+endef
+
+define Package/libauparse
+$(call Package/audit/Default)
+ SECTION:=libs
+ CATEGORY:=Libraries
+ TITLE+= (libauparse)
+ DEPENDS:= +libaudit
+endef
+
+define Package/libauparse/description
+$(call Package/audit/Default/description)
+ This package contains the audit parsing shared library.
+endef
+
+define Package/audit-utils
+$(call Package/audit/Default)
+ SECTION:=admin
+ CATEGORY:=Administration
+ TITLE+= (utilities)
+ DEPENDS:= +libaudit +libauparse
+endef
+
+define Package/audit-utils/description
+$(call Package/audit/Default/description)
+ This package contains the audit utilities.
+endef
+
+define Package/auditd
+$(call Package/audit/Default)
+ SECTION:=admin
+ CATEGORY:=Administration
+ TITLE+= (daemon)
+ DEPENDS:= +libaudit +libauparse +audit-utils +libev
+endef
+
+define Package/auditd/description
+$(call Package/audit/Default/description)
+ This package contains the audit daemon.
+endef
+
+CONFIGURE_VARS += \
+ LDFLAGS_FOR_BUILD="$(HOST_LDFLAGS)" \
+ CPPFLAGS_FOR_BUILD="$(HOST_CPPFLAGS)" \
+ CFLAGS_FOR_BUILD="$(HOST_CFLAGS)" \
+ CC_FOR_BUILD="$(HOSTCC)"
+
+CONFIGURE_ARGS += \
+ --with-debug \
+ --disable-systemd \
+ --disable-zos-remote \
+ --disable-gssapi-krb5 \
+ --without-libcap-ng \
+ --without-python \
+ --without-python3 \
+ --without-golang
+
+ifeq ($(ARCH),aarch64)
+CONFIGURE_ARGS += --with-aarch64
+else ifeq ($(ARCH),arm)
+CONFIGURE_ARGS += --with-arm
+endif
+
+HOST_CONFIGURE_ARGS += \
+ --disable-systemd \
+ --disable-zos-remote \
+ --disable-gssapi-krb5 \
+ --without-libcap-ng \
+ --without-python \
+ --without-python3 \
+ --without-golang
+
+define Host/Install
+ +$(HOST_MAKE_VARS) $(MAKE) $(HOST_JOBS) -C $(HOST_BUILD_DIR)/lib $(HOST_MAKE_FLAGS) install
+ +$(HOST_MAKE_VARS) $(MAKE) $(HOST_JOBS) -C $(HOST_BUILD_DIR)/init.d $(HOST_MAKE_FLAGS) install
+endef
+
+# We can't use the default, as the default passes $(MAKE_ARGS), which
+# overrides CC, CFLAGS, etc. and defeats the *_FOR_BUILD definitions
+# passed in CONFIGURE_VARS
+define Build/Compile
+ $(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR)/$(MAKE_PATH)
+endef
+
+define Build/Install
+ $(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR)/lib $(MAKE_INSTALL_FLAGS) install
+ $(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR)/init.d $(MAKE_INSTALL_FLAGS) install
+ $(call Build/Install/Default,install)
+endef
+
+define Build/InstallDev
+ $(INSTALL_DIR) $(1)/usr/include
+ $(CP) $(PKG_INSTALL_DIR)/usr/include/* $(1)/usr/include/
+ $(INSTALL_DIR) $(1)/usr/lib/pkgconfig
+ $(INSTALL_DATA) $(PKG_INSTALL_DIR)/usr/lib/pkgconfig/*.pc $(1)/usr/lib/pkgconfig/
+ $(INSTALL_DIR) $(1)/usr/lib
+ $(CP) $(PKG_INSTALL_DIR)/usr/lib/* $(1)/usr/lib/
+endef
+
+define Package/libaudit/install
+ $(INSTALL_DIR) $(1)/usr/lib
+ $(CP) $(PKG_INSTALL_DIR)/usr/lib/libaudit.so* $(1)/usr/lib/
+ $(INSTALL_DIR) $(1)/etc
+ $(CP) $(PKG_INSTALL_DIR)/etc/libaudit.conf $(1)/etc/
+endef
+
+define Package/libauparse/install
+ $(INSTALL_DIR) $(1)/usr/lib
+ $(CP) $(PKG_INSTALL_DIR)/usr/lib/libauparse.so* $(1)/usr/lib/
+endef
+
+define Package/audit-utils/install
+ $(INSTALL_DIR) $(1)/usr/bin
+ $(CP) $(PKG_INSTALL_DIR)/usr/bin/* $(1)/usr/bin/
+ $(INSTALL_DIR) $(1)/usr/sbin
+ $(CP) \
+ $(PKG_INSTALL_DIR)/usr/sbin/{audisp-remote,audisp-syslog,auditctl,augenrules,aureport,ausearch,autrace} \
+ $(1)/usr/sbin/
+endef
+
+define Package/auditd/install
+ $(INSTALL_DIR) $(1)/etc/audit
+ $(CP) $(PKG_INSTALL_DIR)/etc/audit/* $(1)/etc/audit/
+ # af_unix plugin is not installed. Remove it's .conf.
+ if [[ -f $(1)/etc/audit/plugins.d/af_unix.conf ]] ; then rm $(1)/etc/audit/plugins.d/af_unix.conf ; fi
+ $(INSTALL_DIR) $(1)/etc/init.d
+ $(INSTALL_BIN) ./files/audit.init $(1)/etc/init.d/audit
+ $(INSTALL_DIR) $(1)/usr/sbin
+ $(CP) $(PKG_INSTALL_DIR)/usr/sbin/auditd $(1)/usr/sbin/
+endef
+
+$(eval $(call HostBuild))
+$(eval $(call BuildPackage,libaudit))
+$(eval $(call BuildPackage,libauparse))
+$(eval $(call BuildPackage,audit-utils))
+$(eval $(call BuildPackage,auditd))
--- /dev/null
+#!/bin/sh /etc/rc.common
+# Copyright (c) 2014 OpenWrt.org
+
+START=11
+
+USE_PROCD=1
+PROG=/usr/sbin/auditd
+
+start_service() {
+ mkdir -p /var/log/audit
+ procd_open_instance
+ procd_set_param command "$PROG" -n
+ procd_set_param respawn
+ procd_close_instance
+ test -f /etc/audit/rules.d/audit.rules && /usr/sbin/auditctl -R /etc/audit/rules.d/audit.rules
+}
#include <unistd.h>
#include "uencrypt.h"
+#if MBEDTLS_VERSION_NUMBER < 0x03010000 /* mbedtls 3.1.0 */
+static inline mbedtls_cipher_mode_t mbedtls_cipher_info_get_mode(
+ const mbedtls_cipher_info_t *info)
+{
+ if (info == NULL) {
+ return MBEDTLS_MODE_NONE;
+ } else {
+ return info->mode;
+ }
+}
+
+static inline size_t mbedtls_cipher_info_get_key_bitlen(
+ const mbedtls_cipher_info_t *info)
+{
+ if (info == NULL) {
+ return 0;
+ } else {
+ return info->key_bitlen;
+ }
+}
+
+static inline const char *mbedtls_cipher_info_get_name(
+ const mbedtls_cipher_info_t *info)
+{
+ if (info == NULL) {
+ return NULL;
+ } else {
+ return info->name;
+ }
+}
+
+static inline size_t mbedtls_cipher_info_get_iv_size(
+ const mbedtls_cipher_info_t *info)
+{
+ if (info == NULL) {
+ return 0;
+ }
+
+ return info->iv_size;
+}
+
+static inline size_t mbedtls_cipher_info_get_block_size(
+ const mbedtls_cipher_info_t *info)
+{
+ if (info == NULL) {
+ return 0;
+ }
+
+ return info->block_size;
+}
+#endif
+
unsigned char *hexstr2buf(const char *str, long *len)
{
unsigned char *buf;
cipher = mbedtls_cipher_info_from_type(*list);
if (!cipher)
continue;
- fprintf(stderr, "\t%s\n", cipher->name);
+ fprintf(stderr, "\t%s\n", mbedtls_cipher_info_get_name(cipher));
}
return NULL;
}
{
const mbedtls_cipher_info_t *c = cipher;
- return c->iv_size;
+ return mbedtls_cipher_info_get_iv_size(c);
}
int get_cipher_keysize(const cipher_t *cipher)
{
const mbedtls_cipher_info_t *c = cipher;
- return c->key_bitlen >> 3;
+ return mbedtls_cipher_info_get_key_bitlen(c) >> 3;
}
ctx_t *create_ctx(const cipher_t *cipher, const unsigned char *key,
}
}
- if (cipher_info->mode == MBEDTLS_MODE_CBC) {
+ if (mbedtls_cipher_info_get_mode(cipher_info) == MBEDTLS_MODE_CBC) {
ret = mbedtls_cipher_set_padding_mode(ctx, padding ?
MBEDTLS_PADDING_PKCS7 :
MBEDTLS_PADDING_NONE);
goto abort;
}
} else {
- if (cipher_info->block_size > 1 && padding) {
+ if (mbedtls_cipher_info_get_block_size(cipher_info) > 1 && padding) {
fprintf(stderr,
"Error: mbedTLS only allows padding with CBC ciphers.\n");
goto abort;
}
}
if (ivlen != get_cipher_ivsize(cipher)) {
- fprintf(stderr, "Error: IV must be %d bytes; given IV is %zd bytes.\n",
+ fprintf(stderr, "Error: IV must be %d bytes; given IV is %ld bytes.\n",
get_cipher_ivsize(cipher), ivlen);
exit(EXIT_FAILURE);
}
if (keylen != get_cipher_keysize(cipher)) {
- fprintf(stderr, "Error: key must be %d bytes; given key is %zd bytes.\n",
+ fprintf(stderr, "Error: key must be %d bytes; given key is %ld bytes.\n",
get_cipher_keysize(cipher), keylen);
exit(EXIT_FAILURE);
}
endif
else
ifeq ($(CONFIG_NATIVE_TOOLCHAIN),)
+ -include $(TOOLCHAIN_DIR)/info.mk
TARGET_CROSS:=$(call qstrip,$(CONFIG_TOOLCHAIN_PREFIX))
TOOLCHAIN_ROOT_DIR:=$(call qstrip,$(CONFIG_TOOLCHAIN_ROOT))
TOOLCHAIN_BIN_DIRS:=$(patsubst ./%,$(TOOLCHAIN_ROOT_DIR)/%,$(call qstrip,$(CONFIG_TOOLCHAIN_BIN_PATH)))
git commit \
--signoff \
--message "kernel/${platform_name}: Restore kernel files for v${source_version}" \
- --message "$(printf "This is an automatically generated commit which aids following Kernel patch history,\nas git will see the move and copy as a rename thus defeating the purpose.\n\nSee: https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html\nfor the original discussion.")"
+ --message "$(printf "This is an automatically generated commit which aids following Kernel patch\nhistory, as git will see the move and copy as a rename thus defeating the\npurpose.\n\nFor the original discussion see:\nhttps://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html")"
git switch "${initial_branch:?Unable to switch back to original branch. Quitting.}"
GIT_EDITOR=true git merge --no-ff '__openwrt_kernel_files_mover'
git branch --delete '__openwrt_kernel_files_mover'
rootsize="$( round_up "$( stat -c%s "$2" )" 1024 )"
;;
esac
- ubivol $vol_id rootfs "$2" "$autoresize" "$rootsize" dynamic
+ ubivol $vol_id rootfs "$2" "$autoresize" "$rootsize"
vol_id=$(( vol_id + 1 ))
- [ "$rootfs_type" = "ubifs" ] || ubivol $vol_id rootfs_data "" 1 dymamic
+ [ "$rootfs_type" = "ubifs" ] || ubivol $vol_id rootfs_data "" 1
fi
}
FEATURES:=ext4 squashfs targz usbgadget ubifs
SUBTARGETS:=sama7 sama5 sam9x
-KERNEL_PATCHVER:=5.15
+KERNEL_PATCHVER:=6.1
include $(INCLUDE_DIR)/target.mk
+++ /dev/null
-From 65bb4687b2a5c6f02f44345540c3389d6e7523e7 Mon Sep 17 00:00:00 2001
-From: Claudiu Beznea <claudiu.beznea@microchip.com>
-Date: Mon, 11 Oct 2021 14:27:05 +0300
-Subject: [PATCH 234/247] clk: at91: re-factor clocks suspend/resume
-
-SAMA5D2 and SAMA7G5 have a special power saving mode (backup mode) where
-most of the SoC's components are powered off (including PMC). Resuming
-from this mode is done with the help of bootloader. Peripherals are not
-aware of the power saving mode thus most of them are disabling clocks in
-proper suspend API and re-enable them in resume API without taking into
-account the previously setup rate. Moreover some of the peripherals are
-acting as wakeup sources and are not disabling the clocks in this
-scenario, when suspending. Since backup mode cuts the power for
-peripherals, in resume part these clocks needs to be re-configured.
-
-The initial PMC suspend/resume code was designed only for SAMA5D2's PMC
-(as it was the only one supporting backup mode). SAMA7G supports also
-backup mode and its PMC is different (few new functionalities, different
-registers offsets, different offsets in registers for each
-functionalities). To address both SAMA5D2 and SAMA7G5 PMC add
-.save_context()/.resume_context() support to each clocks driver and call
-this from PMC driver.
-
-Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
-Link: https://lore.kernel.org/r/20211011112719.3951784-2-claudiu.beznea@microchip.com
-Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/at91/clk-generated.c | 46 +++++--
- drivers/clk/at91/clk-main.c | 66 ++++++++++
- drivers/clk/at91/clk-master.c | 194 ++++++++++++++++++++++++++--
- drivers/clk/at91/clk-peripheral.c | 40 +++++-
- drivers/clk/at91/clk-pll.c | 39 ++++++
- drivers/clk/at91/clk-programmable.c | 29 ++++-
- drivers/clk/at91/clk-sam9x60-pll.c | 68 +++++++++-
- drivers/clk/at91/clk-system.c | 20 +++
- drivers/clk/at91/clk-usb.c | 27 ++++
- drivers/clk/at91/clk-utmi.c | 39 ++++++
- drivers/clk/at91/pmc.c | 147 +--------------------
- drivers/clk/at91/pmc.h | 24 ++--
- 12 files changed, 558 insertions(+), 181 deletions(-)
-
---- a/drivers/clk/at91/clk-generated.c
-+++ b/drivers/clk/at91/clk-generated.c
-@@ -27,6 +27,7 @@ struct clk_generated {
- u32 id;
- u32 gckdiv;
- const struct clk_pcr_layout *layout;
-+ struct at91_clk_pms pms;
- u8 parent_id;
- int chg_pid;
- };
-@@ -34,25 +35,35 @@ struct clk_generated {
- #define to_clk_generated(hw) \
- container_of(hw, struct clk_generated, hw)
-
--static int clk_generated_enable(struct clk_hw *hw)
-+static int clk_generated_set(struct clk_generated *gck, int status)
- {
-- struct clk_generated *gck = to_clk_generated(hw);
- unsigned long flags;
--
-- pr_debug("GCLK: %s, gckdiv = %d, parent id = %d\n",
-- __func__, gck->gckdiv, gck->parent_id);
-+ unsigned int enable = status ? AT91_PMC_PCR_GCKEN : 0;
-
- spin_lock_irqsave(gck->lock, flags);
- regmap_write(gck->regmap, gck->layout->offset,
- (gck->id & gck->layout->pid_mask));
- regmap_update_bits(gck->regmap, gck->layout->offset,
- AT91_PMC_PCR_GCKDIV_MASK | gck->layout->gckcss_mask |
-- gck->layout->cmd | AT91_PMC_PCR_GCKEN,
-+ gck->layout->cmd | enable,
- field_prep(gck->layout->gckcss_mask, gck->parent_id) |
- gck->layout->cmd |
- FIELD_PREP(AT91_PMC_PCR_GCKDIV_MASK, gck->gckdiv) |
-- AT91_PMC_PCR_GCKEN);
-+ enable);
- spin_unlock_irqrestore(gck->lock, flags);
-+
-+ return 0;
-+}
-+
-+static int clk_generated_enable(struct clk_hw *hw)
-+{
-+ struct clk_generated *gck = to_clk_generated(hw);
-+
-+ pr_debug("GCLK: %s, gckdiv = %d, parent id = %d\n",
-+ __func__, gck->gckdiv, gck->parent_id);
-+
-+ clk_generated_set(gck, 1);
-+
- return 0;
- }
-
-@@ -249,6 +260,23 @@ static int clk_generated_set_rate(struct
- return 0;
- }
-
-+static int clk_generated_save_context(struct clk_hw *hw)
-+{
-+ struct clk_generated *gck = to_clk_generated(hw);
-+
-+ gck->pms.status = clk_generated_is_enabled(&gck->hw);
-+
-+ return 0;
-+}
-+
-+static void clk_generated_restore_context(struct clk_hw *hw)
-+{
-+ struct clk_generated *gck = to_clk_generated(hw);
-+
-+ if (gck->pms.status)
-+ clk_generated_set(gck, gck->pms.status);
-+}
-+
- static const struct clk_ops generated_ops = {
- .enable = clk_generated_enable,
- .disable = clk_generated_disable,
-@@ -258,6 +286,8 @@ static const struct clk_ops generated_op
- .get_parent = clk_generated_get_parent,
- .set_parent = clk_generated_set_parent,
- .set_rate = clk_generated_set_rate,
-+ .save_context = clk_generated_save_context,
-+ .restore_context = clk_generated_restore_context,
- };
-
- /**
-@@ -324,8 +354,6 @@ at91_clk_register_generated(struct regma
- if (ret) {
- kfree(gck);
- hw = ERR_PTR(ret);
-- } else {
-- pmc_register_id(id);
- }
-
- return hw;
---- a/drivers/clk/at91/clk-main.c
-+++ b/drivers/clk/at91/clk-main.c
-@@ -28,6 +28,7 @@
- struct clk_main_osc {
- struct clk_hw hw;
- struct regmap *regmap;
-+ struct at91_clk_pms pms;
- };
-
- #define to_clk_main_osc(hw) container_of(hw, struct clk_main_osc, hw)
-@@ -37,6 +38,7 @@ struct clk_main_rc_osc {
- struct regmap *regmap;
- unsigned long frequency;
- unsigned long accuracy;
-+ struct at91_clk_pms pms;
- };
-
- #define to_clk_main_rc_osc(hw) container_of(hw, struct clk_main_rc_osc, hw)
-@@ -51,6 +53,7 @@ struct clk_rm9200_main {
- struct clk_sam9x5_main {
- struct clk_hw hw;
- struct regmap *regmap;
-+ struct at91_clk_pms pms;
- u8 parent;
- };
-
-@@ -120,10 +123,29 @@ static int clk_main_osc_is_prepared(stru
- return (status & AT91_PMC_MOSCS) && clk_main_parent_select(tmp);
- }
-
-+static int clk_main_osc_save_context(struct clk_hw *hw)
-+{
-+ struct clk_main_osc *osc = to_clk_main_osc(hw);
-+
-+ osc->pms.status = clk_main_osc_is_prepared(hw);
-+
-+ return 0;
-+}
-+
-+static void clk_main_osc_restore_context(struct clk_hw *hw)
-+{
-+ struct clk_main_osc *osc = to_clk_main_osc(hw);
-+
-+ if (osc->pms.status)
-+ clk_main_osc_prepare(hw);
-+}
-+
- static const struct clk_ops main_osc_ops = {
- .prepare = clk_main_osc_prepare,
- .unprepare = clk_main_osc_unprepare,
- .is_prepared = clk_main_osc_is_prepared,
-+ .save_context = clk_main_osc_save_context,
-+ .restore_context = clk_main_osc_restore_context,
- };
-
- struct clk_hw * __init
-@@ -240,12 +262,31 @@ static unsigned long clk_main_rc_osc_rec
- return osc->accuracy;
- }
-
-+static int clk_main_rc_osc_save_context(struct clk_hw *hw)
-+{
-+ struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
-+
-+ osc->pms.status = clk_main_rc_osc_is_prepared(hw);
-+
-+ return 0;
-+}
-+
-+static void clk_main_rc_osc_restore_context(struct clk_hw *hw)
-+{
-+ struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
-+
-+ if (osc->pms.status)
-+ clk_main_rc_osc_prepare(hw);
-+}
-+
- static const struct clk_ops main_rc_osc_ops = {
- .prepare = clk_main_rc_osc_prepare,
- .unprepare = clk_main_rc_osc_unprepare,
- .is_prepared = clk_main_rc_osc_is_prepared,
- .recalc_rate = clk_main_rc_osc_recalc_rate,
- .recalc_accuracy = clk_main_rc_osc_recalc_accuracy,
-+ .save_context = clk_main_rc_osc_save_context,
-+ .restore_context = clk_main_rc_osc_restore_context,
- };
-
- struct clk_hw * __init
-@@ -465,12 +506,37 @@ static u8 clk_sam9x5_main_get_parent(str
- return clk_main_parent_select(status);
- }
-
-+static int clk_sam9x5_main_save_context(struct clk_hw *hw)
-+{
-+ struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
-+
-+ clkmain->pms.status = clk_main_rc_osc_is_prepared(&clkmain->hw);
-+ clkmain->pms.parent = clk_sam9x5_main_get_parent(&clkmain->hw);
-+
-+ return 0;
-+}
-+
-+static void clk_sam9x5_main_restore_context(struct clk_hw *hw)
-+{
-+ struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
-+ int ret;
-+
-+ ret = clk_sam9x5_main_set_parent(hw, clkmain->pms.parent);
-+ if (ret)
-+ return;
-+
-+ if (clkmain->pms.status)
-+ clk_sam9x5_main_prepare(hw);
-+}
-+
- static const struct clk_ops sam9x5_main_ops = {
- .prepare = clk_sam9x5_main_prepare,
- .is_prepared = clk_sam9x5_main_is_prepared,
- .recalc_rate = clk_sam9x5_main_recalc_rate,
- .set_parent = clk_sam9x5_main_set_parent,
- .get_parent = clk_sam9x5_main_get_parent,
-+ .save_context = clk_sam9x5_main_save_context,
-+ .restore_context = clk_sam9x5_main_restore_context,
- };
-
- struct clk_hw * __init
---- a/drivers/clk/at91/clk-master.c
-+++ b/drivers/clk/at91/clk-master.c
-@@ -37,6 +37,7 @@ struct clk_master {
- spinlock_t *lock;
- const struct clk_master_layout *layout;
- const struct clk_master_characteristics *characteristics;
-+ struct at91_clk_pms pms;
- u32 *mux_table;
- u32 mckr;
- int chg_pid;
-@@ -112,10 +113,52 @@ static unsigned long clk_master_div_reca
- return rate;
- }
-
-+static int clk_master_div_save_context(struct clk_hw *hw)
-+{
-+ struct clk_master *master = to_clk_master(hw);
-+ struct clk_hw *parent_hw = clk_hw_get_parent(hw);
-+ unsigned long flags;
-+ unsigned int mckr, div;
-+
-+ spin_lock_irqsave(master->lock, flags);
-+ regmap_read(master->regmap, master->layout->offset, &mckr);
-+ spin_unlock_irqrestore(master->lock, flags);
-+
-+ mckr &= master->layout->mask;
-+ div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
-+ div = master->characteristics->divisors[div];
-+
-+ master->pms.parent_rate = clk_hw_get_rate(parent_hw);
-+ master->pms.rate = DIV_ROUND_CLOSEST(master->pms.parent_rate, div);
-+
-+ return 0;
-+}
-+
-+static void clk_master_div_restore_context(struct clk_hw *hw)
-+{
-+ struct clk_master *master = to_clk_master(hw);
-+ unsigned long flags;
-+ unsigned int mckr;
-+ u8 div;
-+
-+ spin_lock_irqsave(master->lock, flags);
-+ regmap_read(master->regmap, master->layout->offset, &mckr);
-+ spin_unlock_irqrestore(master->lock, flags);
-+
-+ mckr &= master->layout->mask;
-+ div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
-+ div = master->characteristics->divisors[div];
-+
-+ if (div != DIV_ROUND_CLOSEST(master->pms.parent_rate, master->pms.rate))
-+ pr_warn("MCKR DIV not configured properly by firmware!\n");
-+}
-+
- static const struct clk_ops master_div_ops = {
- .prepare = clk_master_prepare,
- .is_prepared = clk_master_is_prepared,
- .recalc_rate = clk_master_div_recalc_rate,
-+ .save_context = clk_master_div_save_context,
-+ .restore_context = clk_master_div_restore_context,
- };
-
- static int clk_master_div_set_rate(struct clk_hw *hw, unsigned long rate,
-@@ -125,7 +168,9 @@ static int clk_master_div_set_rate(struc
- const struct clk_master_characteristics *characteristics =
- master->characteristics;
- unsigned long flags;
-+ unsigned int mckr, tmp;
- int div, i;
-+ int ret;
-
- div = DIV_ROUND_CLOSEST(parent_rate, rate);
- if (div > ARRAY_SIZE(characteristics->divisors))
-@@ -145,11 +190,24 @@ static int clk_master_div_set_rate(struc
- return -EINVAL;
-
- spin_lock_irqsave(master->lock, flags);
-- regmap_update_bits(master->regmap, master->layout->offset,
-- (MASTER_DIV_MASK << MASTER_DIV_SHIFT),
-- (div << MASTER_DIV_SHIFT));
-+ ret = regmap_read(master->regmap, master->layout->offset, &mckr);
-+ if (ret)
-+ goto unlock;
-+
-+ tmp = mckr & master->layout->mask;
-+ tmp = (tmp >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
-+ if (tmp == div)
-+ goto unlock;
-+
-+ mckr &= ~(MASTER_DIV_MASK << MASTER_DIV_SHIFT);
-+ mckr |= (div << MASTER_DIV_SHIFT);
-+ ret = regmap_write(master->regmap, master->layout->offset, mckr);
-+ if (ret)
-+ goto unlock;
-+
- while (!clk_master_ready(master))
- cpu_relax();
-+unlock:
- spin_unlock_irqrestore(master->lock, flags);
-
- return 0;
-@@ -197,12 +255,25 @@ static int clk_master_div_determine_rate
- return 0;
- }
-
-+static void clk_master_div_restore_context_chg(struct clk_hw *hw)
-+{
-+ struct clk_master *master = to_clk_master(hw);
-+ int ret;
-+
-+ ret = clk_master_div_set_rate(hw, master->pms.rate,
-+ master->pms.parent_rate);
-+ if (ret)
-+ pr_warn("Failed to restore MCK DIV clock\n");
-+}
-+
- static const struct clk_ops master_div_ops_chg = {
- .prepare = clk_master_prepare,
- .is_prepared = clk_master_is_prepared,
- .recalc_rate = clk_master_div_recalc_rate,
- .determine_rate = clk_master_div_determine_rate,
- .set_rate = clk_master_div_set_rate,
-+ .save_context = clk_master_div_save_context,
-+ .restore_context = clk_master_div_restore_context_chg,
- };
-
- static void clk_sama7g5_master_best_diff(struct clk_rate_request *req,
-@@ -272,7 +343,8 @@ static int clk_master_pres_set_rate(stru
- {
- struct clk_master *master = to_clk_master(hw);
- unsigned long flags;
-- unsigned int pres;
-+ unsigned int pres, mckr, tmp;
-+ int ret;
-
- pres = DIV_ROUND_CLOSEST(parent_rate, rate);
- if (pres > MASTER_PRES_MAX)
-@@ -284,15 +356,27 @@ static int clk_master_pres_set_rate(stru
- pres = ffs(pres) - 1;
-
- spin_lock_irqsave(master->lock, flags);
-- regmap_update_bits(master->regmap, master->layout->offset,
-- (MASTER_PRES_MASK << master->layout->pres_shift),
-- (pres << master->layout->pres_shift));
-+ ret = regmap_read(master->regmap, master->layout->offset, &mckr);
-+ if (ret)
-+ goto unlock;
-+
-+ mckr &= master->layout->mask;
-+ tmp = (mckr >> master->layout->pres_shift) & MASTER_PRES_MASK;
-+ if (pres == tmp)
-+ goto unlock;
-+
-+ mckr &= ~(MASTER_PRES_MASK << master->layout->pres_shift);
-+ mckr |= (pres << master->layout->pres_shift);
-+ ret = regmap_write(master->regmap, master->layout->offset, mckr);
-+ if (ret)
-+ goto unlock;
-
- while (!clk_master_ready(master))
- cpu_relax();
-+unlock:
- spin_unlock_irqrestore(master->lock, flags);
-
-- return 0;
-+ return ret;
- }
-
- static unsigned long clk_master_pres_recalc_rate(struct clk_hw *hw,
-@@ -330,11 +414,68 @@ static u8 clk_master_pres_get_parent(str
- return mckr & AT91_PMC_CSS;
- }
-
-+static int clk_master_pres_save_context(struct clk_hw *hw)
-+{
-+ struct clk_master *master = to_clk_master(hw);
-+ struct clk_hw *parent_hw = clk_hw_get_parent(hw);
-+ unsigned long flags;
-+ unsigned int val, pres;
-+
-+ spin_lock_irqsave(master->lock, flags);
-+ regmap_read(master->regmap, master->layout->offset, &val);
-+ spin_unlock_irqrestore(master->lock, flags);
-+
-+ val &= master->layout->mask;
-+ pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK;
-+ if (pres == MASTER_PRES_MAX && master->characteristics->have_div3_pres)
-+ pres = 3;
-+ else
-+ pres = (1 << pres);
-+
-+ master->pms.parent = val & AT91_PMC_CSS;
-+ master->pms.parent_rate = clk_hw_get_rate(parent_hw);
-+ master->pms.rate = DIV_ROUND_CLOSEST_ULL(master->pms.parent_rate, pres);
-+
-+ return 0;
-+}
-+
-+static void clk_master_pres_restore_context(struct clk_hw *hw)
-+{
-+ struct clk_master *master = to_clk_master(hw);
-+ unsigned long flags;
-+ unsigned int val, pres;
-+
-+ spin_lock_irqsave(master->lock, flags);
-+ regmap_read(master->regmap, master->layout->offset, &val);
-+ spin_unlock_irqrestore(master->lock, flags);
-+
-+ val &= master->layout->mask;
-+ pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK;
-+ if (pres == MASTER_PRES_MAX && master->characteristics->have_div3_pres)
-+ pres = 3;
-+ else
-+ pres = (1 << pres);
-+
-+ if (master->pms.rate !=
-+ DIV_ROUND_CLOSEST_ULL(master->pms.parent_rate, pres) ||
-+ (master->pms.parent != (val & AT91_PMC_CSS)))
-+ pr_warn("MCKR PRES was not configured properly by firmware!\n");
-+}
-+
-+static void clk_master_pres_restore_context_chg(struct clk_hw *hw)
-+{
-+ struct clk_master *master = to_clk_master(hw);
-+
-+ clk_master_pres_set_rate(hw, master->pms.rate, master->pms.parent_rate);
-+}
-+
- static const struct clk_ops master_pres_ops = {
- .prepare = clk_master_prepare,
- .is_prepared = clk_master_is_prepared,
- .recalc_rate = clk_master_pres_recalc_rate,
- .get_parent = clk_master_pres_get_parent,
-+ .save_context = clk_master_pres_save_context,
-+ .restore_context = clk_master_pres_restore_context,
- };
-
- static const struct clk_ops master_pres_ops_chg = {
-@@ -344,6 +485,8 @@ static const struct clk_ops master_pres_
- .recalc_rate = clk_master_pres_recalc_rate,
- .get_parent = clk_master_pres_get_parent,
- .set_rate = clk_master_pres_set_rate,
-+ .save_context = clk_master_pres_save_context,
-+ .restore_context = clk_master_pres_restore_context_chg,
- };
-
- static struct clk_hw * __init
-@@ -539,20 +682,21 @@ static int clk_sama7g5_master_set_parent
- return 0;
- }
-
--static int clk_sama7g5_master_enable(struct clk_hw *hw)
-+static void clk_sama7g5_master_set(struct clk_master *master,
-+ unsigned int status)
- {
-- struct clk_master *master = to_clk_master(hw);
- unsigned long flags;
- unsigned int val, cparent;
-+ unsigned int enable = status ? PMC_MCR_EN : 0;
-
- spin_lock_irqsave(master->lock, flags);
-
- regmap_write(master->regmap, PMC_MCR, PMC_MCR_ID(master->id));
- regmap_read(master->regmap, PMC_MCR, &val);
- regmap_update_bits(master->regmap, PMC_MCR,
-- PMC_MCR_EN | PMC_MCR_CSS | PMC_MCR_DIV |
-+ enable | PMC_MCR_CSS | PMC_MCR_DIV |
- PMC_MCR_CMD | PMC_MCR_ID_MSK,
-- PMC_MCR_EN | (master->parent << PMC_MCR_CSS_SHIFT) |
-+ enable | (master->parent << PMC_MCR_CSS_SHIFT) |
- (master->div << MASTER_DIV_SHIFT) |
- PMC_MCR_CMD | PMC_MCR_ID(master->id));
-
-@@ -563,6 +707,13 @@ static int clk_sama7g5_master_enable(str
- cpu_relax();
-
- spin_unlock_irqrestore(master->lock, flags);
-+}
-+
-+static int clk_sama7g5_master_enable(struct clk_hw *hw)
-+{
-+ struct clk_master *master = to_clk_master(hw);
-+
-+ clk_sama7g5_master_set(master, 1);
-
- return 0;
- }
-@@ -620,6 +771,23 @@ static int clk_sama7g5_master_set_rate(s
- return 0;
- }
-
-+static int clk_sama7g5_master_save_context(struct clk_hw *hw)
-+{
-+ struct clk_master *master = to_clk_master(hw);
-+
-+ master->pms.status = clk_sama7g5_master_is_enabled(hw);
-+
-+ return 0;
-+}
-+
-+static void clk_sama7g5_master_restore_context(struct clk_hw *hw)
-+{
-+ struct clk_master *master = to_clk_master(hw);
-+
-+ if (master->pms.status)
-+ clk_sama7g5_master_set(master, master->pms.status);
-+}
-+
- static const struct clk_ops sama7g5_master_ops = {
- .enable = clk_sama7g5_master_enable,
- .disable = clk_sama7g5_master_disable,
-@@ -629,6 +797,8 @@ static const struct clk_ops sama7g5_mast
- .set_rate = clk_sama7g5_master_set_rate,
- .get_parent = clk_sama7g5_master_get_parent,
- .set_parent = clk_sama7g5_master_set_parent,
-+ .save_context = clk_sama7g5_master_save_context,
-+ .restore_context = clk_sama7g5_master_restore_context,
- };
-
- struct clk_hw * __init
---- a/drivers/clk/at91/clk-peripheral.c
-+++ b/drivers/clk/at91/clk-peripheral.c
-@@ -37,6 +37,7 @@ struct clk_sam9x5_peripheral {
- u32 id;
- u32 div;
- const struct clk_pcr_layout *layout;
-+ struct at91_clk_pms pms;
- bool auto_div;
- int chg_pid;
- };
-@@ -155,10 +156,11 @@ static void clk_sam9x5_peripheral_autodi
- periph->div = shift;
- }
-
--static int clk_sam9x5_peripheral_enable(struct clk_hw *hw)
-+static int clk_sam9x5_peripheral_set(struct clk_sam9x5_peripheral *periph,
-+ unsigned int status)
- {
-- struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
- unsigned long flags;
-+ unsigned int enable = status ? AT91_PMC_PCR_EN : 0;
-
- if (periph->id < PERIPHERAL_ID_MIN)
- return 0;
-@@ -168,15 +170,21 @@ static int clk_sam9x5_peripheral_enable(
- (periph->id & periph->layout->pid_mask));
- regmap_update_bits(periph->regmap, periph->layout->offset,
- periph->layout->div_mask | periph->layout->cmd |
-- AT91_PMC_PCR_EN,
-+ enable,
- field_prep(periph->layout->div_mask, periph->div) |
-- periph->layout->cmd |
-- AT91_PMC_PCR_EN);
-+ periph->layout->cmd | enable);
- spin_unlock_irqrestore(periph->lock, flags);
-
- return 0;
- }
-
-+static int clk_sam9x5_peripheral_enable(struct clk_hw *hw)
-+{
-+ struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
-+
-+ return clk_sam9x5_peripheral_set(periph, 1);
-+}
-+
- static void clk_sam9x5_peripheral_disable(struct clk_hw *hw)
- {
- struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
-@@ -393,6 +401,23 @@ static int clk_sam9x5_peripheral_set_rat
- return -EINVAL;
- }
-
-+static int clk_sam9x5_peripheral_save_context(struct clk_hw *hw)
-+{
-+ struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
-+
-+ periph->pms.status = clk_sam9x5_peripheral_is_enabled(hw);
-+
-+ return 0;
-+}
-+
-+static void clk_sam9x5_peripheral_restore_context(struct clk_hw *hw)
-+{
-+ struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
-+
-+ if (periph->pms.status)
-+ clk_sam9x5_peripheral_set(periph, periph->pms.status);
-+}
-+
- static const struct clk_ops sam9x5_peripheral_ops = {
- .enable = clk_sam9x5_peripheral_enable,
- .disable = clk_sam9x5_peripheral_disable,
-@@ -400,6 +425,8 @@ static const struct clk_ops sam9x5_perip
- .recalc_rate = clk_sam9x5_peripheral_recalc_rate,
- .round_rate = clk_sam9x5_peripheral_round_rate,
- .set_rate = clk_sam9x5_peripheral_set_rate,
-+ .save_context = clk_sam9x5_peripheral_save_context,
-+ .restore_context = clk_sam9x5_peripheral_restore_context,
- };
-
- static const struct clk_ops sam9x5_peripheral_chg_ops = {
-@@ -409,6 +436,8 @@ static const struct clk_ops sam9x5_perip
- .recalc_rate = clk_sam9x5_peripheral_recalc_rate,
- .determine_rate = clk_sam9x5_peripheral_determine_rate,
- .set_rate = clk_sam9x5_peripheral_set_rate,
-+ .save_context = clk_sam9x5_peripheral_save_context,
-+ .restore_context = clk_sam9x5_peripheral_restore_context,
- };
-
- struct clk_hw * __init
-@@ -460,7 +489,6 @@ at91_clk_register_sam9x5_peripheral(stru
- hw = ERR_PTR(ret);
- } else {
- clk_sam9x5_peripheral_autodiv(periph);
-- pmc_register_id(id);
- }
-
- return hw;
---- a/drivers/clk/at91/clk-pll.c
-+++ b/drivers/clk/at91/clk-pll.c
-@@ -40,6 +40,7 @@ struct clk_pll {
- u16 mul;
- const struct clk_pll_layout *layout;
- const struct clk_pll_characteristics *characteristics;
-+ struct at91_clk_pms pms;
- };
-
- static inline bool clk_pll_ready(struct regmap *regmap, int id)
-@@ -260,6 +261,42 @@ static int clk_pll_set_rate(struct clk_h
- return 0;
- }
-
-+static int clk_pll_save_context(struct clk_hw *hw)
-+{
-+ struct clk_pll *pll = to_clk_pll(hw);
-+ struct clk_hw *parent_hw = clk_hw_get_parent(hw);
-+
-+ pll->pms.parent_rate = clk_hw_get_rate(parent_hw);
-+ pll->pms.rate = clk_pll_recalc_rate(&pll->hw, pll->pms.parent_rate);
-+ pll->pms.status = clk_pll_ready(pll->regmap, PLL_REG(pll->id));
-+
-+ return 0;
-+}
-+
-+static void clk_pll_restore_context(struct clk_hw *hw)
-+{
-+ struct clk_pll *pll = to_clk_pll(hw);
-+ unsigned long calc_rate;
-+ unsigned int pllr, pllr_out, pllr_count;
-+ u8 out = 0;
-+
-+ if (pll->characteristics->out)
-+ out = pll->characteristics->out[pll->range];
-+
-+ regmap_read(pll->regmap, PLL_REG(pll->id), &pllr);
-+
-+ calc_rate = (pll->pms.parent_rate / PLL_DIV(pllr)) *
-+ (PLL_MUL(pllr, pll->layout) + 1);
-+ pllr_count = (pllr >> PLL_COUNT_SHIFT) & PLL_MAX_COUNT;
-+ pllr_out = (pllr >> PLL_OUT_SHIFT) & out;
-+
-+ if (pll->pms.rate != calc_rate ||
-+ pll->pms.status != clk_pll_ready(pll->regmap, PLL_REG(pll->id)) ||
-+ pllr_count != PLL_MAX_COUNT ||
-+ (out && pllr_out != out))
-+ pr_warn("PLLAR was not configured properly by firmware\n");
-+}
-+
- static const struct clk_ops pll_ops = {
- .prepare = clk_pll_prepare,
- .unprepare = clk_pll_unprepare,
-@@ -267,6 +304,8 @@ static const struct clk_ops pll_ops = {
- .recalc_rate = clk_pll_recalc_rate,
- .round_rate = clk_pll_round_rate,
- .set_rate = clk_pll_set_rate,
-+ .save_context = clk_pll_save_context,
-+ .restore_context = clk_pll_restore_context,
- };
-
- struct clk_hw * __init
---- a/drivers/clk/at91/clk-programmable.c
-+++ b/drivers/clk/at91/clk-programmable.c
-@@ -24,6 +24,7 @@ struct clk_programmable {
- u32 *mux_table;
- u8 id;
- const struct clk_programmable_layout *layout;
-+ struct at91_clk_pms pms;
- };
-
- #define to_clk_programmable(hw) container_of(hw, struct clk_programmable, hw)
-@@ -177,12 +178,38 @@ static int clk_programmable_set_rate(str
- return 0;
- }
-
-+static int clk_programmable_save_context(struct clk_hw *hw)
-+{
-+ struct clk_programmable *prog = to_clk_programmable(hw);
-+ struct clk_hw *parent_hw = clk_hw_get_parent(hw);
-+
-+ prog->pms.parent = clk_programmable_get_parent(hw);
-+ prog->pms.parent_rate = clk_hw_get_rate(parent_hw);
-+ prog->pms.rate = clk_programmable_recalc_rate(hw, prog->pms.parent_rate);
-+
-+ return 0;
-+}
-+
-+static void clk_programmable_restore_context(struct clk_hw *hw)
-+{
-+ struct clk_programmable *prog = to_clk_programmable(hw);
-+ int ret;
-+
-+ ret = clk_programmable_set_parent(hw, prog->pms.parent);
-+ if (ret)
-+ return;
-+
-+ clk_programmable_set_rate(hw, prog->pms.rate, prog->pms.parent_rate);
-+}
-+
- static const struct clk_ops programmable_ops = {
- .recalc_rate = clk_programmable_recalc_rate,
- .determine_rate = clk_programmable_determine_rate,
- .get_parent = clk_programmable_get_parent,
- .set_parent = clk_programmable_set_parent,
- .set_rate = clk_programmable_set_rate,
-+ .save_context = clk_programmable_save_context,
-+ .restore_context = clk_programmable_restore_context,
- };
-
- struct clk_hw * __init
-@@ -221,8 +248,6 @@ at91_clk_register_programmable(struct re
- if (ret) {
- kfree(prog);
- hw = ERR_PTR(ret);
-- } else {
-- pmc_register_pck(id);
- }
-
- return hw;
---- a/drivers/clk/at91/clk-sam9x60-pll.c
-+++ b/drivers/clk/at91/clk-sam9x60-pll.c
-@@ -38,12 +38,14 @@ struct sam9x60_pll_core {
-
- struct sam9x60_frac {
- struct sam9x60_pll_core core;
-+ struct at91_clk_pms pms;
- u32 frac;
- u16 mul;
- };
-
- struct sam9x60_div {
- struct sam9x60_pll_core core;
-+ struct at91_clk_pms pms;
- u8 div;
- };
-
-@@ -75,9 +77,8 @@ static unsigned long sam9x60_frac_pll_re
- DIV_ROUND_CLOSEST_ULL((u64)parent_rate * frac->frac, (1 << 22));
- }
-
--static int sam9x60_frac_pll_prepare(struct clk_hw *hw)
-+static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core)
- {
-- struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
- struct sam9x60_frac *frac = to_sam9x60_frac(core);
- struct regmap *regmap = core->regmap;
- unsigned int val, cfrac, cmul;
-@@ -141,6 +142,13 @@ unlock:
- return 0;
- }
-
-+static int sam9x60_frac_pll_prepare(struct clk_hw *hw)
-+{
-+ struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
-+
-+ return sam9x60_frac_pll_set(core);
-+}
-+
- static void sam9x60_frac_pll_unprepare(struct clk_hw *hw)
- {
- struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
-@@ -280,6 +288,25 @@ unlock:
- return ret;
- }
-
-+static int sam9x60_frac_pll_save_context(struct clk_hw *hw)
-+{
-+ struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
-+ struct sam9x60_frac *frac = to_sam9x60_frac(core);
-+
-+ frac->pms.status = sam9x60_pll_ready(core->regmap, core->id);
-+
-+ return 0;
-+}
-+
-+static void sam9x60_frac_pll_restore_context(struct clk_hw *hw)
-+{
-+ struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
-+ struct sam9x60_frac *frac = to_sam9x60_frac(core);
-+
-+ if (frac->pms.status)
-+ sam9x60_frac_pll_set(core);
-+}
-+
- static const struct clk_ops sam9x60_frac_pll_ops = {
- .prepare = sam9x60_frac_pll_prepare,
- .unprepare = sam9x60_frac_pll_unprepare,
-@@ -287,6 +314,8 @@ static const struct clk_ops sam9x60_frac
- .recalc_rate = sam9x60_frac_pll_recalc_rate,
- .round_rate = sam9x60_frac_pll_round_rate,
- .set_rate = sam9x60_frac_pll_set_rate,
-+ .save_context = sam9x60_frac_pll_save_context,
-+ .restore_context = sam9x60_frac_pll_restore_context,
- };
-
- static const struct clk_ops sam9x60_frac_pll_ops_chg = {
-@@ -296,11 +325,12 @@ static const struct clk_ops sam9x60_frac
- .recalc_rate = sam9x60_frac_pll_recalc_rate,
- .round_rate = sam9x60_frac_pll_round_rate,
- .set_rate = sam9x60_frac_pll_set_rate_chg,
-+ .save_context = sam9x60_frac_pll_save_context,
-+ .restore_context = sam9x60_frac_pll_restore_context,
- };
-
--static int sam9x60_div_pll_prepare(struct clk_hw *hw)
-+static int sam9x60_div_pll_set(struct sam9x60_pll_core *core)
- {
-- struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
- struct sam9x60_div *div = to_sam9x60_div(core);
- struct regmap *regmap = core->regmap;
- unsigned long flags;
-@@ -334,6 +364,13 @@ unlock:
- return 0;
- }
-
-+static int sam9x60_div_pll_prepare(struct clk_hw *hw)
-+{
-+ struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
-+
-+ return sam9x60_div_pll_set(core);
-+}
-+
- static void sam9x60_div_pll_unprepare(struct clk_hw *hw)
- {
- struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
-@@ -482,6 +519,25 @@ unlock:
- return 0;
- }
-
-+static int sam9x60_div_pll_save_context(struct clk_hw *hw)
-+{
-+ struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
-+ struct sam9x60_div *div = to_sam9x60_div(core);
-+
-+ div->pms.status = sam9x60_div_pll_is_prepared(hw);
-+
-+ return 0;
-+}
-+
-+static void sam9x60_div_pll_restore_context(struct clk_hw *hw)
-+{
-+ struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
-+ struct sam9x60_div *div = to_sam9x60_div(core);
-+
-+ if (div->pms.status)
-+ sam9x60_div_pll_set(core);
-+}
-+
- static const struct clk_ops sam9x60_div_pll_ops = {
- .prepare = sam9x60_div_pll_prepare,
- .unprepare = sam9x60_div_pll_unprepare,
-@@ -489,6 +545,8 @@ static const struct clk_ops sam9x60_div_
- .recalc_rate = sam9x60_div_pll_recalc_rate,
- .round_rate = sam9x60_div_pll_round_rate,
- .set_rate = sam9x60_div_pll_set_rate,
-+ .save_context = sam9x60_div_pll_save_context,
-+ .restore_context = sam9x60_div_pll_restore_context,
- };
-
- static const struct clk_ops sam9x60_div_pll_ops_chg = {
-@@ -498,6 +556,8 @@ static const struct clk_ops sam9x60_div_
- .recalc_rate = sam9x60_div_pll_recalc_rate,
- .round_rate = sam9x60_div_pll_round_rate,
- .set_rate = sam9x60_div_pll_set_rate_chg,
-+ .save_context = sam9x60_div_pll_save_context,
-+ .restore_context = sam9x60_div_pll_restore_context,
- };
-
- struct clk_hw * __init
---- a/drivers/clk/at91/clk-system.c
-+++ b/drivers/clk/at91/clk-system.c
-@@ -20,6 +20,7 @@
- struct clk_system {
- struct clk_hw hw;
- struct regmap *regmap;
-+ struct at91_clk_pms pms;
- u8 id;
- };
-
-@@ -77,10 +78,29 @@ static int clk_system_is_prepared(struct
- return !!(status & (1 << sys->id));
- }
-
-+static int clk_system_save_context(struct clk_hw *hw)
-+{
-+ struct clk_system *sys = to_clk_system(hw);
-+
-+ sys->pms.status = clk_system_is_prepared(hw);
-+
-+ return 0;
-+}
-+
-+static void clk_system_restore_context(struct clk_hw *hw)
-+{
-+ struct clk_system *sys = to_clk_system(hw);
-+
-+ if (sys->pms.status)
-+ clk_system_prepare(&sys->hw);
-+}
-+
- static const struct clk_ops system_ops = {
- .prepare = clk_system_prepare,
- .unprepare = clk_system_unprepare,
- .is_prepared = clk_system_is_prepared,
-+ .save_context = clk_system_save_context,
-+ .restore_context = clk_system_restore_context,
- };
-
- struct clk_hw * __init
---- a/drivers/clk/at91/clk-usb.c
-+++ b/drivers/clk/at91/clk-usb.c
-@@ -24,6 +24,7 @@
- struct at91sam9x5_clk_usb {
- struct clk_hw hw;
- struct regmap *regmap;
-+ struct at91_clk_pms pms;
- u32 usbs_mask;
- u8 num_parents;
- };
-@@ -148,12 +149,38 @@ static int at91sam9x5_clk_usb_set_rate(s
- return 0;
- }
-
-+static int at91sam9x5_usb_save_context(struct clk_hw *hw)
-+{
-+ struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);
-+ struct clk_hw *parent_hw = clk_hw_get_parent(hw);
-+
-+ usb->pms.parent = at91sam9x5_clk_usb_get_parent(hw);
-+ usb->pms.parent_rate = clk_hw_get_rate(parent_hw);
-+ usb->pms.rate = at91sam9x5_clk_usb_recalc_rate(hw, usb->pms.parent_rate);
-+
-+ return 0;
-+}
-+
-+static void at91sam9x5_usb_restore_context(struct clk_hw *hw)
-+{
-+ struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);
-+ int ret;
-+
-+ ret = at91sam9x5_clk_usb_set_parent(hw, usb->pms.parent);
-+ if (ret)
-+ return;
-+
-+ at91sam9x5_clk_usb_set_rate(hw, usb->pms.rate, usb->pms.parent_rate);
-+}
-+
- static const struct clk_ops at91sam9x5_usb_ops = {
- .recalc_rate = at91sam9x5_clk_usb_recalc_rate,
- .determine_rate = at91sam9x5_clk_usb_determine_rate,
- .get_parent = at91sam9x5_clk_usb_get_parent,
- .set_parent = at91sam9x5_clk_usb_set_parent,
- .set_rate = at91sam9x5_clk_usb_set_rate,
-+ .save_context = at91sam9x5_usb_save_context,
-+ .restore_context = at91sam9x5_usb_restore_context,
- };
-
- static int at91sam9n12_clk_usb_enable(struct clk_hw *hw)
---- a/drivers/clk/at91/clk-utmi.c
-+++ b/drivers/clk/at91/clk-utmi.c
-@@ -23,6 +23,7 @@ struct clk_utmi {
- struct clk_hw hw;
- struct regmap *regmap_pmc;
- struct regmap *regmap_sfr;
-+ struct at91_clk_pms pms;
- };
-
- #define to_clk_utmi(hw) container_of(hw, struct clk_utmi, hw)
-@@ -113,11 +114,30 @@ static unsigned long clk_utmi_recalc_rat
- return UTMI_RATE;
- }
-
-+static int clk_utmi_save_context(struct clk_hw *hw)
-+{
-+ struct clk_utmi *utmi = to_clk_utmi(hw);
-+
-+ utmi->pms.status = clk_utmi_is_prepared(hw);
-+
-+ return 0;
-+}
-+
-+static void clk_utmi_restore_context(struct clk_hw *hw)
-+{
-+ struct clk_utmi *utmi = to_clk_utmi(hw);
-+
-+ if (utmi->pms.status)
-+ clk_utmi_prepare(hw);
-+}
-+
- static const struct clk_ops utmi_ops = {
- .prepare = clk_utmi_prepare,
- .unprepare = clk_utmi_unprepare,
- .is_prepared = clk_utmi_is_prepared,
- .recalc_rate = clk_utmi_recalc_rate,
-+ .save_context = clk_utmi_save_context,
-+ .restore_context = clk_utmi_restore_context,
- };
-
- static struct clk_hw * __init
-@@ -232,10 +252,29 @@ static int clk_utmi_sama7g5_is_prepared(
- return 0;
- }
-
-+static int clk_utmi_sama7g5_save_context(struct clk_hw *hw)
-+{
-+ struct clk_utmi *utmi = to_clk_utmi(hw);
-+
-+ utmi->pms.status = clk_utmi_sama7g5_is_prepared(hw);
-+
-+ return 0;
-+}
-+
-+static void clk_utmi_sama7g5_restore_context(struct clk_hw *hw)
-+{
-+ struct clk_utmi *utmi = to_clk_utmi(hw);
-+
-+ if (utmi->pms.status)
-+ clk_utmi_sama7g5_prepare(hw);
-+}
-+
- static const struct clk_ops sama7g5_utmi_ops = {
- .prepare = clk_utmi_sama7g5_prepare,
- .is_prepared = clk_utmi_sama7g5_is_prepared,
- .recalc_rate = clk_utmi_recalc_rate,
-+ .save_context = clk_utmi_sama7g5_save_context,
-+ .restore_context = clk_utmi_sama7g5_restore_context,
- };
-
- struct clk_hw * __init
---- a/drivers/clk/at91/pmc.c
-+++ b/drivers/clk/at91/pmc.c
-@@ -3,6 +3,7 @@
- * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
- */
-
-+#include <linux/clk.h>
- #include <linux/clk-provider.h>
- #include <linux/clkdev.h>
- #include <linux/clk/at91_pmc.h>
-@@ -14,8 +15,6 @@
-
- #include <asm/proc-fns.h>
-
--#include <dt-bindings/clock/at91.h>
--
- #include "pmc.h"
-
- #define PMC_MAX_IDS 128
-@@ -111,147 +110,19 @@ struct pmc_data *pmc_data_allocate(unsig
- }
-
- #ifdef CONFIG_PM
--static struct regmap *pmcreg;
--
--static u8 registered_ids[PMC_MAX_IDS];
--static u8 registered_pcks[PMC_MAX_PCKS];
--
--static struct
--{
-- u32 scsr;
-- u32 pcsr0;
-- u32 uckr;
-- u32 mor;
-- u32 mcfr;
-- u32 pllar;
-- u32 mckr;
-- u32 usb;
-- u32 imr;
-- u32 pcsr1;
-- u32 pcr[PMC_MAX_IDS];
-- u32 audio_pll0;
-- u32 audio_pll1;
-- u32 pckr[PMC_MAX_PCKS];
--} pmc_cache;
--
--/*
-- * As Peripheral ID 0 is invalid on AT91 chips, the identifier is stored
-- * without alteration in the table, and 0 is for unused clocks.
-- */
--void pmc_register_id(u8 id)
-+static int at91_pmc_suspend(void)
- {
-- int i;
--
-- for (i = 0; i < PMC_MAX_IDS; i++) {
-- if (registered_ids[i] == 0) {
-- registered_ids[i] = id;
-- break;
-- }
-- if (registered_ids[i] == id)
-- break;
-- }
-+ return clk_save_context();
- }
-
--/*
-- * As Programmable Clock 0 is valid on AT91 chips, there is an offset
-- * of 1 between the stored value and the real clock ID.
-- */
--void pmc_register_pck(u8 pck)
-+static void at91_pmc_resume(void)
- {
-- int i;
--
-- for (i = 0; i < PMC_MAX_PCKS; i++) {
-- if (registered_pcks[i] == 0) {
-- registered_pcks[i] = pck + 1;
-- break;
-- }
-- if (registered_pcks[i] == (pck + 1))
-- break;
-- }
--}
--
--static int pmc_suspend(void)
--{
-- int i;
-- u8 num;
--
-- regmap_read(pmcreg, AT91_PMC_SCSR, &pmc_cache.scsr);
-- regmap_read(pmcreg, AT91_PMC_PCSR, &pmc_cache.pcsr0);
-- regmap_read(pmcreg, AT91_CKGR_UCKR, &pmc_cache.uckr);
-- regmap_read(pmcreg, AT91_CKGR_MOR, &pmc_cache.mor);
-- regmap_read(pmcreg, AT91_CKGR_MCFR, &pmc_cache.mcfr);
-- regmap_read(pmcreg, AT91_CKGR_PLLAR, &pmc_cache.pllar);
-- regmap_read(pmcreg, AT91_PMC_MCKR, &pmc_cache.mckr);
-- regmap_read(pmcreg, AT91_PMC_USB, &pmc_cache.usb);
-- regmap_read(pmcreg, AT91_PMC_IMR, &pmc_cache.imr);
-- regmap_read(pmcreg, AT91_PMC_PCSR1, &pmc_cache.pcsr1);
--
-- for (i = 0; registered_ids[i]; i++) {
-- regmap_write(pmcreg, AT91_PMC_PCR,
-- (registered_ids[i] & AT91_PMC_PCR_PID_MASK));
-- regmap_read(pmcreg, AT91_PMC_PCR,
-- &pmc_cache.pcr[registered_ids[i]]);
-- }
-- for (i = 0; registered_pcks[i]; i++) {
-- num = registered_pcks[i] - 1;
-- regmap_read(pmcreg, AT91_PMC_PCKR(num), &pmc_cache.pckr[num]);
-- }
--
-- return 0;
--}
--
--static bool pmc_ready(unsigned int mask)
--{
-- unsigned int status;
--
-- regmap_read(pmcreg, AT91_PMC_SR, &status);
--
-- return ((status & mask) == mask) ? 1 : 0;
--}
--
--static void pmc_resume(void)
--{
-- int i;
-- u8 num;
-- u32 tmp;
-- u32 mask = AT91_PMC_MCKRDY | AT91_PMC_LOCKA;
--
-- regmap_read(pmcreg, AT91_PMC_MCKR, &tmp);
-- if (pmc_cache.mckr != tmp)
-- pr_warn("MCKR was not configured properly by the firmware\n");
-- regmap_read(pmcreg, AT91_CKGR_PLLAR, &tmp);
-- if (pmc_cache.pllar != tmp)
-- pr_warn("PLLAR was not configured properly by the firmware\n");
--
-- regmap_write(pmcreg, AT91_PMC_SCER, pmc_cache.scsr);
-- regmap_write(pmcreg, AT91_PMC_PCER, pmc_cache.pcsr0);
-- regmap_write(pmcreg, AT91_CKGR_UCKR, pmc_cache.uckr);
-- regmap_write(pmcreg, AT91_CKGR_MOR, pmc_cache.mor);
-- regmap_write(pmcreg, AT91_CKGR_MCFR, pmc_cache.mcfr);
-- regmap_write(pmcreg, AT91_PMC_USB, pmc_cache.usb);
-- regmap_write(pmcreg, AT91_PMC_IMR, pmc_cache.imr);
-- regmap_write(pmcreg, AT91_PMC_PCER1, pmc_cache.pcsr1);
--
-- for (i = 0; registered_ids[i]; i++) {
-- regmap_write(pmcreg, AT91_PMC_PCR,
-- pmc_cache.pcr[registered_ids[i]] |
-- AT91_PMC_PCR_CMD);
-- }
-- for (i = 0; registered_pcks[i]; i++) {
-- num = registered_pcks[i] - 1;
-- regmap_write(pmcreg, AT91_PMC_PCKR(num), pmc_cache.pckr[num]);
-- }
--
-- if (pmc_cache.uckr & AT91_PMC_UPLLEN)
-- mask |= AT91_PMC_LOCKU;
--
-- while (!pmc_ready(mask))
-- cpu_relax();
-+ clk_restore_context();
- }
-
- static struct syscore_ops pmc_syscore_ops = {
-- .suspend = pmc_suspend,
-- .resume = pmc_resume,
-+ .suspend = at91_pmc_suspend,
-+ .resume = at91_pmc_resume,
- };
-
- static const struct of_device_id sama5d2_pmc_dt_ids[] = {
-@@ -271,11 +142,7 @@ static int __init pmc_register_ops(void)
- of_node_put(np);
- return -ENODEV;
- }
--
-- pmcreg = device_node_to_regmap(np);
- of_node_put(np);
-- if (IS_ERR(pmcreg))
-- return PTR_ERR(pmcreg);
-
- register_syscore_ops(&pmc_syscore_ops);
-
---- a/drivers/clk/at91/pmc.h
-+++ b/drivers/clk/at91/pmc.h
-@@ -13,6 +13,8 @@
- #include <linux/regmap.h>
- #include <linux/spinlock.h>
-
-+#include <dt-bindings/clock/at91.h>
-+
- extern spinlock_t pmc_pcr_lock;
-
- struct pmc_data {
-@@ -98,6 +100,20 @@ struct clk_pcr_layout {
- u32 pid_mask;
- };
-
-+/**
-+ * struct at91_clk_pms - Power management state for AT91 clock
-+ * @rate: clock rate
-+ * @parent_rate: clock parent rate
-+ * @status: clock status (enabled or disabled)
-+ * @parent: clock parent index
-+ */
-+struct at91_clk_pms {
-+ unsigned long rate;
-+ unsigned long parent_rate;
-+ unsigned int status;
-+ unsigned int parent;
-+};
-+
- #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))
- #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask))
-
-@@ -248,12 +264,4 @@ struct clk_hw * __init
- at91_clk_sama7g5_register_utmi(struct regmap *regmap, const char *name,
- const char *parent_name);
-
--#ifdef CONFIG_PM
--void pmc_register_id(u8 id);
--void pmc_register_pck(u8 pck);
--#else
--static inline void pmc_register_id(u8 id) {}
--static inline void pmc_register_pck(u8 pck) {}
--#endif
--
- #endif /* __PMC_H_ */
+++ /dev/null
-From 63a0c32028148e91ea91cfbf95841c4ecd69d21b Mon Sep 17 00:00:00 2001
-From: Claudiu Beznea <claudiu.beznea@microchip.com>
-Date: Mon, 11 Oct 2021 14:27:06 +0300
-Subject: [PATCH 235/247] clk: at91: pmc: execute suspend/resume only for
- backup mode
-
-Before going to backup mode architecture specific PM code sets the first
-word in securam (file arch/arm/mach-at91/pm.c, function at91_pm_begin()).
-Thus take this into account when suspending/resuming clocks. This will
-avoid executing unnecessary instructions when suspending to non backup
-modes.
-
-Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
-Link: https://lore.kernel.org/r/20211011112719.3951784-3-claudiu.beznea@microchip.com
-Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/at91/pmc.c | 39 +++++++++++++++++++++++++++++++++++++++
- 1 file changed, 39 insertions(+)
-
---- a/drivers/clk/at91/pmc.c
-+++ b/drivers/clk/at91/pmc.c
-@@ -8,6 +8,7 @@
- #include <linux/clkdev.h>
- #include <linux/clk/at91_pmc.h>
- #include <linux/of.h>
-+#include <linux/of_address.h>
- #include <linux/mfd/syscon.h>
- #include <linux/platform_device.h>
- #include <linux/regmap.h>
-@@ -110,13 +111,35 @@ struct pmc_data *pmc_data_allocate(unsig
- }
-
- #ifdef CONFIG_PM
-+
-+/* Address in SECURAM that say if we suspend to backup mode. */
-+static void __iomem *at91_pmc_backup_suspend;
-+
- static int at91_pmc_suspend(void)
- {
-+ unsigned int backup;
-+
-+ if (!at91_pmc_backup_suspend)
-+ return 0;
-+
-+ backup = readl_relaxed(at91_pmc_backup_suspend);
-+ if (!backup)
-+ return 0;
-+
- return clk_save_context();
- }
-
- static void at91_pmc_resume(void)
- {
-+ unsigned int backup;
-+
-+ if (!at91_pmc_backup_suspend)
-+ return;
-+
-+ backup = readl_relaxed(at91_pmc_backup_suspend);
-+ if (!backup)
-+ return;
-+
- clk_restore_context();
- }
-
-@@ -144,6 +167,22 @@ static int __init pmc_register_ops(void)
- }
- of_node_put(np);
-
-+ np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam");
-+ if (!np)
-+ return -ENODEV;
-+
-+ if (!of_device_is_available(np)) {
-+ of_node_put(np);
-+ return -ENODEV;
-+ }
-+ of_node_put(np);
-+
-+ at91_pmc_backup_suspend = of_iomap(np, 0);
-+ if (!at91_pmc_backup_suspend) {
-+ pr_warn("%s(): unable to map securam\n", __func__);
-+ return -ENOMEM;
-+ }
-+
- register_syscore_ops(&pmc_syscore_ops);
-
- return 0;
+++ /dev/null
-From c716562753d1e51a1c53647aa77a332f97187d15 Mon Sep 17 00:00:00 2001
-From: Claudiu Beznea <claudiu.beznea@microchip.com>
-Date: Mon, 11 Oct 2021 14:27:08 +0300
-Subject: [PATCH 237/247] clk: at91: clk-master: add register definition for
- sama7g5's master clock
-
-SAMA7G5 has 4 master clocks (MCK1..4) which are controlled though the
-register at offset 0x30 (relative to PMC). In the last/first phase of
-suspend/resume procedure (which is architecture specific) the parent
-of master clocks are changed (via assembly code) for more power saving
-(see file arch/arm/mach-at91/pm_suspend.S, macros at91_mckx_ps_enable
-and at91_mckx_ps_restore). Thus the macros corresponding to register
-at offset 0x30 need to be shared b/w clk-master.c and pm_suspend.S.
-commit ec03f18cc222 ("clk: at91: add register definition for sama7g5's
-master clock") introduced the proper macros but didn't adapted the
-clk-master.c as well. Thus, this commit adapt the clk-master.c to use
-the macros introduced in commit ec03f18cc222 ("clk: at91: add register
-definition for sama7g5's master clock").
-
-Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
-Link: https://lore.kernel.org/r/20211011112719.3951784-5-claudiu.beznea@microchip.com
-Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/at91/clk-master.c | 50 ++++++++++++++++-------------------
- 1 file changed, 23 insertions(+), 27 deletions(-)
-
---- a/drivers/clk/at91/clk-master.c
-+++ b/drivers/clk/at91/clk-master.c
-@@ -17,15 +17,7 @@
- #define MASTER_DIV_SHIFT 8
- #define MASTER_DIV_MASK 0x7
-
--#define PMC_MCR 0x30
--#define PMC_MCR_ID_MSK GENMASK(3, 0)
--#define PMC_MCR_CMD BIT(7)
--#define PMC_MCR_DIV GENMASK(10, 8)
--#define PMC_MCR_CSS GENMASK(20, 16)
- #define PMC_MCR_CSS_SHIFT (16)
--#define PMC_MCR_EN BIT(28)
--
--#define PMC_MCR_ID(x) ((x) & PMC_MCR_ID_MSK)
-
- #define MASTER_MAX_ID 4
-
-@@ -687,20 +679,22 @@ static void clk_sama7g5_master_set(struc
- {
- unsigned long flags;
- unsigned int val, cparent;
-- unsigned int enable = status ? PMC_MCR_EN : 0;
-+ unsigned int enable = status ? AT91_PMC_MCR_V2_EN : 0;
-
- spin_lock_irqsave(master->lock, flags);
-
-- regmap_write(master->regmap, PMC_MCR, PMC_MCR_ID(master->id));
-- regmap_read(master->regmap, PMC_MCR, &val);
-- regmap_update_bits(master->regmap, PMC_MCR,
-- enable | PMC_MCR_CSS | PMC_MCR_DIV |
-- PMC_MCR_CMD | PMC_MCR_ID_MSK,
-+ regmap_write(master->regmap, AT91_PMC_MCR_V2,
-+ AT91_PMC_MCR_V2_ID(master->id));
-+ regmap_read(master->regmap, AT91_PMC_MCR_V2, &val);
-+ regmap_update_bits(master->regmap, AT91_PMC_MCR_V2,
-+ enable | AT91_PMC_MCR_V2_CSS | AT91_PMC_MCR_V2_DIV |
-+ AT91_PMC_MCR_V2_CMD | AT91_PMC_MCR_V2_ID_MSK,
- enable | (master->parent << PMC_MCR_CSS_SHIFT) |
- (master->div << MASTER_DIV_SHIFT) |
-- PMC_MCR_CMD | PMC_MCR_ID(master->id));
-+ AT91_PMC_MCR_V2_CMD |
-+ AT91_PMC_MCR_V2_ID(master->id));
-
-- cparent = (val & PMC_MCR_CSS) >> PMC_MCR_CSS_SHIFT;
-+ cparent = (val & AT91_PMC_MCR_V2_CSS) >> PMC_MCR_CSS_SHIFT;
-
- /* Wait here only if parent is being changed. */
- while ((cparent != master->parent) && !clk_master_ready(master))
-@@ -725,10 +719,12 @@ static void clk_sama7g5_master_disable(s
-
- spin_lock_irqsave(master->lock, flags);
-
-- regmap_write(master->regmap, PMC_MCR, master->id);
-- regmap_update_bits(master->regmap, PMC_MCR,
-- PMC_MCR_EN | PMC_MCR_CMD | PMC_MCR_ID_MSK,
-- PMC_MCR_CMD | PMC_MCR_ID(master->id));
-+ regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id);
-+ regmap_update_bits(master->regmap, AT91_PMC_MCR_V2,
-+ AT91_PMC_MCR_V2_EN | AT91_PMC_MCR_V2_CMD |
-+ AT91_PMC_MCR_V2_ID_MSK,
-+ AT91_PMC_MCR_V2_CMD |
-+ AT91_PMC_MCR_V2_ID(master->id));
-
- spin_unlock_irqrestore(master->lock, flags);
- }
-@@ -741,12 +737,12 @@ static int clk_sama7g5_master_is_enabled
-
- spin_lock_irqsave(master->lock, flags);
-
-- regmap_write(master->regmap, PMC_MCR, master->id);
-- regmap_read(master->regmap, PMC_MCR, &val);
-+ regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id);
-+ regmap_read(master->regmap, AT91_PMC_MCR_V2, &val);
-
- spin_unlock_irqrestore(master->lock, flags);
-
-- return !!(val & PMC_MCR_EN);
-+ return !!(val & AT91_PMC_MCR_V2_EN);
- }
-
- static int clk_sama7g5_master_set_rate(struct clk_hw *hw, unsigned long rate,
-@@ -842,10 +838,10 @@ at91_clk_sama7g5_register_master(struct
- master->mux_table = mux_table;
-
- spin_lock_irqsave(master->lock, flags);
-- regmap_write(master->regmap, PMC_MCR, master->id);
-- regmap_read(master->regmap, PMC_MCR, &val);
-- master->parent = (val & PMC_MCR_CSS) >> PMC_MCR_CSS_SHIFT;
-- master->div = (val & PMC_MCR_DIV) >> MASTER_DIV_SHIFT;
-+ regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id);
-+ regmap_read(master->regmap, AT91_PMC_MCR_V2, &val);
-+ master->parent = (val & AT91_PMC_MCR_V2_CSS) >> PMC_MCR_CSS_SHIFT;
-+ master->div = (val & AT91_PMC_MCR_V2_DIV) >> MASTER_DIV_SHIFT;
- spin_unlock_irqrestore(master->lock, flags);
-
- hw = &master->hw;
+++ /dev/null
-From 17b53ad1574cb5f41789993289d3d94f7a50f0ce Mon Sep 17 00:00:00 2001
-From: Claudiu Beznea <claudiu.beznea@microchip.com>
-Date: Mon, 11 Oct 2021 14:27:09 +0300
-Subject: [PATCH 238/247] clk: at91: clk-master: improve readability by using
- local variables
-
-Improve readability in clk_sama7g5_master_set() by using local
-variables.
-
-Suggested-by: Nicolas Ferre <nicolas.ferre@microchip.com>
-Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
-Link: https://lore.kernel.org/r/20211011112719.3951784-6-claudiu.beznea@microchip.com
-Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/at91/clk-master.c | 6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
-
---- a/drivers/clk/at91/clk-master.c
-+++ b/drivers/clk/at91/clk-master.c
-@@ -680,6 +680,8 @@ static void clk_sama7g5_master_set(struc
- unsigned long flags;
- unsigned int val, cparent;
- unsigned int enable = status ? AT91_PMC_MCR_V2_EN : 0;
-+ unsigned int parent = master->parent << PMC_MCR_CSS_SHIFT;
-+ unsigned int div = master->div << MASTER_DIV_SHIFT;
-
- spin_lock_irqsave(master->lock, flags);
-
-@@ -689,9 +691,7 @@ static void clk_sama7g5_master_set(struc
- regmap_update_bits(master->regmap, AT91_PMC_MCR_V2,
- enable | AT91_PMC_MCR_V2_CSS | AT91_PMC_MCR_V2_DIV |
- AT91_PMC_MCR_V2_CMD | AT91_PMC_MCR_V2_ID_MSK,
-- enable | (master->parent << PMC_MCR_CSS_SHIFT) |
-- (master->div << MASTER_DIV_SHIFT) |
-- AT91_PMC_MCR_V2_CMD |
-+ enable | parent | div | AT91_PMC_MCR_V2_CMD |
- AT91_PMC_MCR_V2_ID(master->id));
-
- cparent = (val & AT91_PMC_MCR_V2_CSS) >> PMC_MCR_CSS_SHIFT;
+++ /dev/null
-From 8a38e0dda46c9d941a61d8b2e6c14704531b7871 Mon Sep 17 00:00:00 2001
-From: Claudiu Beznea <claudiu.beznea@microchip.com>
-Date: Mon, 11 Oct 2021 14:27:10 +0300
-Subject: [PATCH 239/247] clk: at91: pmc: add sama7g5 to the list of available
- pmcs
-
-Add SAMA7G5 to the list of available PMCs such that the suspend/resume
-code for clocks to be used on backup mode.
-
-Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
-Link: https://lore.kernel.org/r/20211011112719.3951784-7-claudiu.beznea@microchip.com
-Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/at91/pmc.c | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
---- a/drivers/clk/at91/pmc.c
-+++ b/drivers/clk/at91/pmc.c
-@@ -148,8 +148,9 @@ static struct syscore_ops pmc_syscore_op
- .resume = at91_pmc_resume,
- };
-
--static const struct of_device_id sama5d2_pmc_dt_ids[] = {
-+static const struct of_device_id pmc_dt_ids[] = {
- { .compatible = "atmel,sama5d2-pmc" },
-+ { .compatible = "microchip,sama7g5-pmc", },
- { /* sentinel */ }
- };
-
-@@ -157,7 +158,7 @@ static int __init pmc_register_ops(void)
- {
- struct device_node *np;
-
-- np = of_find_matching_node(NULL, sama5d2_pmc_dt_ids);
-+ np = of_find_matching_node(NULL, pmc_dt_ids);
- if (!np)
- return -ENODEV;
-
+++ /dev/null
-From 27c11c09346b7b9f67eeb39db1b943f4a9742ff3 Mon Sep 17 00:00:00 2001
-From: Claudiu Beznea <claudiu.beznea@microchip.com>
-Date: Mon, 11 Oct 2021 14:27:13 +0300
-Subject: [PATCH 241/247] clk: at91: clk-master: mask mckr against layout->mask
-
-Mask values read/written from/to MCKR against layout->mask as this
-mask may be different b/w PMC versions.
-
-Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
-Link: https://lore.kernel.org/r/20211011112719.3951784-10-claudiu.beznea@microchip.com
-Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/at91/clk-master.c | 7 +++++--
- 1 file changed, 5 insertions(+), 2 deletions(-)
-
---- a/drivers/clk/at91/clk-master.c
-+++ b/drivers/clk/at91/clk-master.c
-@@ -186,8 +186,8 @@ static int clk_master_div_set_rate(struc
- if (ret)
- goto unlock;
-
-- tmp = mckr & master->layout->mask;
-- tmp = (tmp >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
-+ mckr &= master->layout->mask;
-+ tmp = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
- if (tmp == div)
- goto unlock;
-
-@@ -384,6 +384,7 @@ static unsigned long clk_master_pres_rec
- regmap_read(master->regmap, master->layout->offset, &val);
- spin_unlock_irqrestore(master->lock, flags);
-
-+ val &= master->layout->mask;
- pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK;
- if (pres == MASTER_PRES_MAX && characteristics->have_div3_pres)
- pres = 3;
-@@ -403,6 +404,8 @@ static u8 clk_master_pres_get_parent(str
- regmap_read(master->regmap, master->layout->offset, &mckr);
- spin_unlock_irqrestore(master->lock, flags);
-
-+ mckr &= master->layout->mask;
-+
- return mckr & AT91_PMC_CSS;
- }
-
+++ /dev/null
-From e76d2af5009f52aa02d3db7ae32d150ad66398f9 Mon Sep 17 00:00:00 2001
-From: Claudiu Beznea <claudiu.beznea@microchip.com>
-Date: Mon, 11 Oct 2021 14:27:15 +0300
-Subject: [PATCH 243/247] clk: at91: clk-sam9x60-pll: add notifier for div part
- of PLL
-
-SAM9X60's PLL which is also part of SAMA7G5 is composed of 2 parts:
-one fractional part and one divider. On SAMA7G5 the CPU PLL could be
-changed at run-time to implement DVFS. The hardware clock tree on
-SAMA7G5 for CPU PLL is as follows:
-
- +---- div1 ----------------> cpuck
- |
-FRAC PLL ---> DIV PLL -+-> prescaler ---> div0 ---> mck0
-
-The div1 block is not implemented in Linux; on prescaler block it has
-been discovered a bug on some scenarios and will be removed from Linux
-in next commits. Thus, the final clock tree that will be used in Linux
-will be as follows:
-
- +-----------> cpuck
- |
-FRAC PLL ---> DIV PLL -+-> div0 ---> mck0
-
-It has been proposed in [1] to not introduce a new CPUFreq driver but
-to overload the proper clock drivers with proper operation such that
-cpufreq-dt to be used. To accomplish this DIV PLL and div0 implement
-clock notifiers which applies safe dividers before FRAC PLL is changed.
-The current commit treats only the DIV PLL by adding a notifier that
-sets a safe divider on PRE_RATE_CHANGE events. The safe divider is
-provided by initialization clock code (sama7g5.c). The div0 is treated
-in next commits (to keep the changes as clean as possible).
-
-[1] https://lore.kernel.org/lkml/20210105104426.4tmgc2l3vyicwedd@vireshk-i7/
-
-Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
-Link: https://lore.kernel.org/r/20211011112719.3951784-12-claudiu.beznea@microchip.com
-Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/at91/clk-sam9x60-pll.c | 102 ++++++++++++++++++++++-------
- drivers/clk/at91/pmc.h | 3 +-
- drivers/clk/at91/sam9x60.c | 6 +-
- drivers/clk/at91/sama7g5.c | 13 +++-
- 4 files changed, 95 insertions(+), 29 deletions(-)
-
---- a/drivers/clk/at91/clk-sam9x60-pll.c
-+++ b/drivers/clk/at91/clk-sam9x60-pll.c
-@@ -5,6 +5,7 @@
- */
-
- #include <linux/bitfield.h>
-+#include <linux/clk.h>
- #include <linux/clk-provider.h>
- #include <linux/clkdev.h>
- #include <linux/clk/at91_pmc.h>
-@@ -47,12 +48,15 @@ struct sam9x60_div {
- struct sam9x60_pll_core core;
- struct at91_clk_pms pms;
- u8 div;
-+ u8 safe_div;
- };
-
- #define to_sam9x60_pll_core(hw) container_of(hw, struct sam9x60_pll_core, hw)
- #define to_sam9x60_frac(core) container_of(core, struct sam9x60_frac, core)
- #define to_sam9x60_div(core) container_of(core, struct sam9x60_div, core)
-
-+static struct sam9x60_div *notifier_div;
-+
- static inline bool sam9x60_pll_ready(struct regmap *regmap, int id)
- {
- unsigned int status;
-@@ -329,6 +333,26 @@ static const struct clk_ops sam9x60_frac
- .restore_context = sam9x60_frac_pll_restore_context,
- };
-
-+/* This function should be called with spinlock acquired. */
-+static void sam9x60_div_pll_set_div(struct sam9x60_pll_core *core, u32 div,
-+ bool enable)
-+{
-+ struct regmap *regmap = core->regmap;
-+ u32 ena_msk = enable ? core->layout->endiv_mask : 0;
-+ u32 ena_val = enable ? (1 << core->layout->endiv_shift) : 0;
-+
-+ regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,
-+ core->layout->div_mask | ena_msk,
-+ (div << core->layout->div_shift) | ena_val);
-+
-+ regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
-+ AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
-+ AT91_PMC_PLL_UPDT_UPDATE | core->id);
-+
-+ while (!sam9x60_pll_ready(regmap, core->id))
-+ cpu_relax();
-+}
-+
- static int sam9x60_div_pll_set(struct sam9x60_pll_core *core)
- {
- struct sam9x60_div *div = to_sam9x60_div(core);
-@@ -346,17 +370,7 @@ static int sam9x60_div_pll_set(struct sa
- if (!!(val & core->layout->endiv_mask) && cdiv == div->div)
- goto unlock;
-
-- regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,
-- core->layout->div_mask | core->layout->endiv_mask,
-- (div->div << core->layout->div_shift) |
-- (1 << core->layout->endiv_shift));
--
-- regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
-- AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
-- AT91_PMC_PLL_UPDT_UPDATE | core->id);
--
-- while (!sam9x60_pll_ready(regmap, core->id))
-- cpu_relax();
-+ sam9x60_div_pll_set_div(core, div->div, 1);
-
- unlock:
- spin_unlock_irqrestore(core->lock, flags);
-@@ -502,16 +516,7 @@ static int sam9x60_div_pll_set_rate_chg(
- if (cdiv == div->div)
- goto unlock;
-
-- regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,
-- core->layout->div_mask,
-- (div->div << core->layout->div_shift));
--
-- regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
-- AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
-- AT91_PMC_PLL_UPDT_UPDATE | core->id);
--
-- while (!sam9x60_pll_ready(regmap, core->id))
-- cpu_relax();
-+ sam9x60_div_pll_set_div(core, div->div, 0);
-
- unlock:
- spin_unlock_irqrestore(core->lock, irqflags);
-@@ -538,6 +543,48 @@ static void sam9x60_div_pll_restore_cont
- sam9x60_div_pll_set(core);
- }
-
-+static int sam9x60_div_pll_notifier_fn(struct notifier_block *notifier,
-+ unsigned long code, void *data)
-+{
-+ struct sam9x60_div *div = notifier_div;
-+ struct sam9x60_pll_core core = div->core;
-+ struct regmap *regmap = core.regmap;
-+ unsigned long irqflags;
-+ u32 val, cdiv;
-+ int ret = NOTIFY_DONE;
-+
-+ if (code != PRE_RATE_CHANGE)
-+ return ret;
-+
-+ /*
-+ * We switch to safe divider to avoid overclocking of other domains
-+ * feed by us while the frac PLL (our parent) is changed.
-+ */
-+ div->div = div->safe_div;
-+
-+ spin_lock_irqsave(core.lock, irqflags);
-+ regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,
-+ core.id);
-+ regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);
-+ cdiv = (val & core.layout->div_mask) >> core.layout->div_shift;
-+
-+ /* Stop if nothing changed. */
-+ if (cdiv == div->safe_div)
-+ goto unlock;
-+
-+ sam9x60_div_pll_set_div(&core, div->div, 0);
-+ ret = NOTIFY_OK;
-+
-+unlock:
-+ spin_unlock_irqrestore(core.lock, irqflags);
-+
-+ return ret;
-+}
-+
-+static struct notifier_block sam9x60_div_pll_notifier = {
-+ .notifier_call = sam9x60_div_pll_notifier_fn,
-+};
-+
- static const struct clk_ops sam9x60_div_pll_ops = {
- .prepare = sam9x60_div_pll_prepare,
- .unprepare = sam9x60_div_pll_unprepare,
-@@ -647,7 +694,8 @@ struct clk_hw * __init
- sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
- const char *name, const char *parent_name, u8 id,
- const struct clk_pll_characteristics *characteristics,
-- const struct clk_pll_layout *layout, u32 flags)
-+ const struct clk_pll_layout *layout, u32 flags,
-+ u32 safe_div)
- {
- struct sam9x60_div *div;
- struct clk_hw *hw;
-@@ -656,9 +704,13 @@ sam9x60_clk_register_div_pll(struct regm
- unsigned int val;
- int ret;
-
-- if (id > PLL_MAX_ID || !lock)
-+ /* We only support one changeable PLL. */
-+ if (id > PLL_MAX_ID || !lock || (safe_div && notifier_div))
- return ERR_PTR(-EINVAL);
-
-+ if (safe_div >= PLL_DIV_MAX)
-+ safe_div = PLL_DIV_MAX - 1;
-+
- div = kzalloc(sizeof(*div), GFP_KERNEL);
- if (!div)
- return ERR_PTR(-ENOMEM);
-@@ -678,6 +730,7 @@ sam9x60_clk_register_div_pll(struct regm
- div->core.layout = layout;
- div->core.regmap = regmap;
- div->core.lock = lock;
-+ div->safe_div = safe_div;
-
- spin_lock_irqsave(div->core.lock, irqflags);
-
-@@ -693,6 +746,9 @@ sam9x60_clk_register_div_pll(struct regm
- if (ret) {
- kfree(div);
- hw = ERR_PTR(ret);
-+ } else if (div->safe_div) {
-+ notifier_div = div;
-+ clk_notifier_register(hw->clk, &sam9x60_div_pll_notifier);
- }
-
- return hw;
---- a/drivers/clk/at91/pmc.h
-+++ b/drivers/clk/at91/pmc.h
-@@ -214,7 +214,8 @@ struct clk_hw * __init
- sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
- const char *name, const char *parent_name, u8 id,
- const struct clk_pll_characteristics *characteristics,
-- const struct clk_pll_layout *layout, u32 flags);
-+ const struct clk_pll_layout *layout, u32 flags,
-+ u32 safe_div);
-
- struct clk_hw * __init
- sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
---- a/drivers/clk/at91/sam9x60.c
-+++ b/drivers/clk/at91/sam9x60.c
-@@ -242,7 +242,7 @@ static void __init sam9x60_pmc_setup(str
- * This feeds CPU. It should not
- * be disabled.
- */
-- CLK_IS_CRITICAL | CLK_SET_RATE_GATE);
-+ CLK_IS_CRITICAL | CLK_SET_RATE_GATE, 0);
- if (IS_ERR(hw))
- goto err_free;
-
-@@ -260,7 +260,7 @@ static void __init sam9x60_pmc_setup(str
- &pll_div_layout,
- CLK_SET_RATE_GATE |
- CLK_SET_PARENT_GATE |
-- CLK_SET_RATE_PARENT);
-+ CLK_SET_RATE_PARENT, 0);
- if (IS_ERR(hw))
- goto err_free;
-
-@@ -279,7 +279,7 @@ static void __init sam9x60_pmc_setup(str
- hw = at91_clk_register_master_div(regmap, "masterck_div",
- "masterck_pres", &sam9x60_master_layout,
- &mck_characteristics, &mck_lock,
-- CLK_SET_RATE_GATE);
-+ CLK_SET_RATE_GATE, 0);
- if (IS_ERR(hw))
- goto err_free;
-
---- a/drivers/clk/at91/sama7g5.c
-+++ b/drivers/clk/at91/sama7g5.c
-@@ -127,6 +127,8 @@ static const struct clk_pll_characterist
- * @t: clock type
- * @f: clock flags
- * @eid: export index in sama7g5->chws[] array
-+ * @safe_div: intermediate divider need to be set on PRE_RATE_CHANGE
-+ * notification
- */
- static const struct {
- const char *n;
-@@ -136,6 +138,7 @@ static const struct {
- unsigned long f;
- u8 t;
- u8 eid;
-+ u8 safe_div;
- } sama7g5_plls[][PLL_ID_MAX] = {
- [PLL_ID_CPU] = {
- { .n = "cpupll_fracck",
-@@ -156,7 +159,12 @@ static const struct {
- .t = PLL_TYPE_DIV,
- /* This feeds CPU. It should not be disabled. */
- .f = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
-- .eid = PMC_CPUPLL, },
-+ .eid = PMC_CPUPLL,
-+ /*
-+ * Safe div=15 should be safe even for switching b/w 1GHz and
-+ * 90MHz (frac pll might go up to 1.2GHz).
-+ */
-+ .safe_div = 15, },
- },
-
- [PLL_ID_SYS] = {
-@@ -966,7 +974,8 @@ static void __init sama7g5_pmc_setup(str
- sama7g5_plls[i][j].p, i,
- sama7g5_plls[i][j].c,
- sama7g5_plls[i][j].l,
-- sama7g5_plls[i][j].f);
-+ sama7g5_plls[i][j].f,
-+ sama7g5_plls[i][j].safe_div);
- break;
-
- default:
+++ /dev/null
-From 75d5d1d584ae73ba0c36d1d7255db6153ca4d3f3 Mon Sep 17 00:00:00 2001
-From: Claudiu Beznea <claudiu.beznea@microchip.com>
-Date: Mon, 11 Oct 2021 14:27:16 +0300
-Subject: [PATCH 244/247] clk: at91: clk-master: add notifier for divider
-
-SAMA7G5 supports DVFS by changing cpuck. On SAMA7G5 mck0 shares the same
-parent with cpuck as seen in the following clock tree:
-
- +----------> cpuck
- |
-FRAC PLL ---> DIV PLL -+-> DIV ---> mck0
-
-mck0 could go b/w 32KHz and 200MHz on SAMA7G5. To avoid mck0 overclocking
-while changing FRAC PLL or DIV PLL the commit implements a notifier for
-mck0 which applies a safe divider to register (maximum value of the divider
-which is 5) on PRE_RATE_CHANGE events (such that changes on PLL to not
-overclock mck0) and sets the maximum allowed rate on POST_RATE_CHANGE
-events.
-
-Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
-Link: https://lore.kernel.org/r/20211011112719.3951784-13-claudiu.beznea@microchip.com
-Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/at91/at91rm9200.c | 2 +-
- drivers/clk/at91/at91sam9260.c | 2 +-
- drivers/clk/at91/at91sam9g45.c | 2 +-
- drivers/clk/at91/at91sam9n12.c | 2 +-
- drivers/clk/at91/at91sam9rl.c | 2 +-
- drivers/clk/at91/at91sam9x5.c | 2 +-
- drivers/clk/at91/clk-master.c | 244 +++++++++++++++++++++++----------
- drivers/clk/at91/dt-compat.c | 2 +-
- drivers/clk/at91/pmc.h | 2 +-
- drivers/clk/at91/sama5d2.c | 2 +-
- drivers/clk/at91/sama5d3.c | 2 +-
- drivers/clk/at91/sama5d4.c | 2 +-
- drivers/clk/at91/sama7g5.c | 2 +-
- 13 files changed, 186 insertions(+), 82 deletions(-)
-
---- a/drivers/clk/at91/at91rm9200.c
-+++ b/drivers/clk/at91/at91rm9200.c
-@@ -152,7 +152,7 @@ static void __init at91rm9200_pmc_setup(
- "masterck_pres",
- &at91rm9200_master_layout,
- &rm9200_mck_characteristics,
-- &rm9200_mck_lock, CLK_SET_RATE_GATE);
-+ &rm9200_mck_lock, CLK_SET_RATE_GATE, 0);
- if (IS_ERR(hw))
- goto err_free;
-
---- a/drivers/clk/at91/at91sam9260.c
-+++ b/drivers/clk/at91/at91sam9260.c
-@@ -429,7 +429,7 @@ static void __init at91sam926x_pmc_setup
- &at91rm9200_master_layout,
- data->mck_characteristics,
- &at91sam9260_mck_lock,
-- CLK_SET_RATE_GATE);
-+ CLK_SET_RATE_GATE, 0);
- if (IS_ERR(hw))
- goto err_free;
-
---- a/drivers/clk/at91/at91sam9g45.c
-+++ b/drivers/clk/at91/at91sam9g45.c
-@@ -164,7 +164,7 @@ static void __init at91sam9g45_pmc_setup
- &at91rm9200_master_layout,
- &mck_characteristics,
- &at91sam9g45_mck_lock,
-- CLK_SET_RATE_GATE);
-+ CLK_SET_RATE_GATE, 0);
- if (IS_ERR(hw))
- goto err_free;
-
---- a/drivers/clk/at91/at91sam9n12.c
-+++ b/drivers/clk/at91/at91sam9n12.c
-@@ -191,7 +191,7 @@ static void __init at91sam9n12_pmc_setup
- &at91sam9x5_master_layout,
- &mck_characteristics,
- &at91sam9n12_mck_lock,
-- CLK_SET_RATE_GATE);
-+ CLK_SET_RATE_GATE, 0);
- if (IS_ERR(hw))
- goto err_free;
-
---- a/drivers/clk/at91/at91sam9rl.c
-+++ b/drivers/clk/at91/at91sam9rl.c
-@@ -132,7 +132,7 @@ static void __init at91sam9rl_pmc_setup(
- "masterck_pres",
- &at91rm9200_master_layout,
- &sam9rl_mck_characteristics,
-- &sam9rl_mck_lock, CLK_SET_RATE_GATE);
-+ &sam9rl_mck_lock, CLK_SET_RATE_GATE, 0);
- if (IS_ERR(hw))
- goto err_free;
-
---- a/drivers/clk/at91/at91sam9x5.c
-+++ b/drivers/clk/at91/at91sam9x5.c
-@@ -210,7 +210,7 @@ static void __init at91sam9x5_pmc_setup(
- "masterck_pres",
- &at91sam9x5_master_layout,
- &mck_characteristics, &mck_lock,
-- CLK_SET_RATE_GATE);
-+ CLK_SET_RATE_GATE, 0);
- if (IS_ERR(hw))
- goto err_free;
-
---- a/drivers/clk/at91/clk-master.c
-+++ b/drivers/clk/at91/clk-master.c
-@@ -5,6 +5,7 @@
-
- #include <linux/clk-provider.h>
- #include <linux/clkdev.h>
-+#include <linux/clk.h>
- #include <linux/clk/at91_pmc.h>
- #include <linux/of.h>
- #include <linux/mfd/syscon.h>
-@@ -36,8 +37,12 @@ struct clk_master {
- u8 id;
- u8 parent;
- u8 div;
-+ u32 safe_div;
- };
-
-+/* MCK div reference to be used by notifier. */
-+static struct clk_master *master_div;
-+
- static inline bool clk_master_ready(struct clk_master *master)
- {
- unsigned int bit = master->id ? AT91_PMC_MCKXRDY : AT91_PMC_MCKRDY;
-@@ -153,107 +158,81 @@ static const struct clk_ops master_div_o
- .restore_context = clk_master_div_restore_context,
- };
-
--static int clk_master_div_set_rate(struct clk_hw *hw, unsigned long rate,
-- unsigned long parent_rate)
-+/* This function must be called with lock acquired. */
-+static int clk_master_div_set(struct clk_master *master,
-+ unsigned long parent_rate, int div)
- {
-- struct clk_master *master = to_clk_master(hw);
- const struct clk_master_characteristics *characteristics =
- master->characteristics;
-- unsigned long flags;
-- unsigned int mckr, tmp;
-- int div, i;
-+ unsigned long rate = parent_rate;
-+ unsigned int max_div = 0, div_index = 0, max_div_index = 0;
-+ unsigned int i, mckr, tmp;
- int ret;
-
-- div = DIV_ROUND_CLOSEST(parent_rate, rate);
-- if (div > ARRAY_SIZE(characteristics->divisors))
-- return -EINVAL;
--
- for (i = 0; i < ARRAY_SIZE(characteristics->divisors); i++) {
- if (!characteristics->divisors[i])
- break;
-
-- if (div == characteristics->divisors[i]) {
-- div = i;
-- break;
-+ if (div == characteristics->divisors[i])
-+ div_index = i;
-+
-+ if (max_div < characteristics->divisors[i]) {
-+ max_div = characteristics->divisors[i];
-+ max_div_index = i;
- }
- }
-
-- if (i == ARRAY_SIZE(characteristics->divisors))
-- return -EINVAL;
-+ if (div > max_div)
-+ div_index = max_div_index;
-
-- spin_lock_irqsave(master->lock, flags);
- ret = regmap_read(master->regmap, master->layout->offset, &mckr);
- if (ret)
-- goto unlock;
-+ return ret;
-
- mckr &= master->layout->mask;
- tmp = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
-- if (tmp == div)
-- goto unlock;
-+ if (tmp == div_index)
-+ return 0;
-+
-+ rate /= characteristics->divisors[div_index];
-+ if (rate < characteristics->output.min)
-+ pr_warn("master clk div is underclocked");
-+ else if (rate > characteristics->output.max)
-+ pr_warn("master clk div is overclocked");
-
- mckr &= ~(MASTER_DIV_MASK << MASTER_DIV_SHIFT);
-- mckr |= (div << MASTER_DIV_SHIFT);
-+ mckr |= (div_index << MASTER_DIV_SHIFT);
- ret = regmap_write(master->regmap, master->layout->offset, mckr);
- if (ret)
-- goto unlock;
-+ return ret;
-
- while (!clk_master_ready(master))
- cpu_relax();
--unlock:
-- spin_unlock_irqrestore(master->lock, flags);
-+
-+ master->div = characteristics->divisors[div_index];
-
- return 0;
- }
-
--static int clk_master_div_determine_rate(struct clk_hw *hw,
-- struct clk_rate_request *req)
-+static unsigned long clk_master_div_recalc_rate_chg(struct clk_hw *hw,
-+ unsigned long parent_rate)
- {
- struct clk_master *master = to_clk_master(hw);
-- const struct clk_master_characteristics *characteristics =
-- master->characteristics;
-- struct clk_hw *parent;
-- unsigned long parent_rate, tmp_rate, best_rate = 0;
-- int i, best_diff = INT_MIN, tmp_diff;
--
-- parent = clk_hw_get_parent(hw);
-- if (!parent)
-- return -EINVAL;
--
-- parent_rate = clk_hw_get_rate(parent);
-- if (!parent_rate)
-- return -EINVAL;
-
-- for (i = 0; i < ARRAY_SIZE(characteristics->divisors); i++) {
-- if (!characteristics->divisors[i])
-- break;
--
-- tmp_rate = DIV_ROUND_CLOSEST_ULL(parent_rate,
-- characteristics->divisors[i]);
-- tmp_diff = abs(tmp_rate - req->rate);
--
-- if (!best_rate || best_diff > tmp_diff) {
-- best_diff = tmp_diff;
-- best_rate = tmp_rate;
-- }
--
-- if (!best_diff)
-- break;
-- }
--
-- req->best_parent_rate = best_rate;
-- req->best_parent_hw = parent;
-- req->rate = best_rate;
--
-- return 0;
-+ return DIV_ROUND_CLOSEST_ULL(parent_rate, master->div);
- }
-
- static void clk_master_div_restore_context_chg(struct clk_hw *hw)
- {
- struct clk_master *master = to_clk_master(hw);
-+ unsigned long flags;
- int ret;
-
-- ret = clk_master_div_set_rate(hw, master->pms.rate,
-- master->pms.parent_rate);
-+ spin_lock_irqsave(master->lock, flags);
-+ ret = clk_master_div_set(master, master->pms.parent_rate,
-+ DIV_ROUND_CLOSEST(master->pms.parent_rate,
-+ master->pms.rate));
-+ spin_unlock_irqrestore(master->lock, flags);
- if (ret)
- pr_warn("Failed to restore MCK DIV clock\n");
- }
-@@ -261,13 +240,116 @@ static void clk_master_div_restore_conte
- static const struct clk_ops master_div_ops_chg = {
- .prepare = clk_master_prepare,
- .is_prepared = clk_master_is_prepared,
-- .recalc_rate = clk_master_div_recalc_rate,
-- .determine_rate = clk_master_div_determine_rate,
-- .set_rate = clk_master_div_set_rate,
-+ .recalc_rate = clk_master_div_recalc_rate_chg,
- .save_context = clk_master_div_save_context,
- .restore_context = clk_master_div_restore_context_chg,
- };
-
-+static int clk_master_div_notifier_fn(struct notifier_block *notifier,
-+ unsigned long code, void *data)
-+{
-+ const struct clk_master_characteristics *characteristics =
-+ master_div->characteristics;
-+ struct clk_notifier_data *cnd = data;
-+ unsigned long flags, new_parent_rate, new_rate;
-+ unsigned int mckr, div, new_div = 0;
-+ int ret, i;
-+ long tmp_diff;
-+ long best_diff = -1;
-+
-+ spin_lock_irqsave(master_div->lock, flags);
-+ switch (code) {
-+ case PRE_RATE_CHANGE:
-+ /*
-+ * We want to avoid any overclocking of MCK DIV domain. To do
-+ * this we set a safe divider (the underclocking is not of
-+ * interest as we can go as low as 32KHz). The relation
-+ * b/w this clock and its parents are as follows:
-+ *
-+ * FRAC PLL -> DIV PLL -> MCK DIV
-+ *
-+ * With the proper safe divider we should be good even with FRAC
-+ * PLL at its maximum value.
-+ */
-+ ret = regmap_read(master_div->regmap, master_div->layout->offset,
-+ &mckr);
-+ if (ret) {
-+ ret = NOTIFY_STOP_MASK;
-+ goto unlock;
-+ }
-+
-+ mckr &= master_div->layout->mask;
-+ div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
-+
-+ /* Switch to safe divider. */
-+ clk_master_div_set(master_div,
-+ cnd->old_rate * characteristics->divisors[div],
-+ master_div->safe_div);
-+ break;
-+
-+ case POST_RATE_CHANGE:
-+ /*
-+ * At this point we want to restore MCK DIV domain to its maximum
-+ * allowed rate.
-+ */
-+ ret = regmap_read(master_div->regmap, master_div->layout->offset,
-+ &mckr);
-+ if (ret) {
-+ ret = NOTIFY_STOP_MASK;
-+ goto unlock;
-+ }
-+
-+ mckr &= master_div->layout->mask;
-+ div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
-+ new_parent_rate = cnd->new_rate * characteristics->divisors[div];
-+
-+ for (i = 0; i < ARRAY_SIZE(characteristics->divisors); i++) {
-+ if (!characteristics->divisors[i])
-+ break;
-+
-+ new_rate = DIV_ROUND_CLOSEST_ULL(new_parent_rate,
-+ characteristics->divisors[i]);
-+
-+ tmp_diff = characteristics->output.max - new_rate;
-+ if (tmp_diff < 0)
-+ continue;
-+
-+ if (best_diff < 0 || best_diff > tmp_diff) {
-+ new_div = characteristics->divisors[i];
-+ best_diff = tmp_diff;
-+ }
-+
-+ if (!tmp_diff)
-+ break;
-+ }
-+
-+ if (!new_div) {
-+ ret = NOTIFY_STOP_MASK;
-+ goto unlock;
-+ }
-+
-+ /* Update the div to preserve MCK DIV clock rate. */
-+ clk_master_div_set(master_div, new_parent_rate,
-+ new_div);
-+
-+ ret = NOTIFY_OK;
-+ break;
-+
-+ default:
-+ ret = NOTIFY_DONE;
-+ break;
-+ }
-+
-+unlock:
-+ spin_unlock_irqrestore(master_div->lock, flags);
-+
-+ return ret;
-+}
-+
-+static struct notifier_block clk_master_div_notifier = {
-+ .notifier_call = clk_master_div_notifier_fn,
-+};
-+
- static void clk_sama7g5_master_best_diff(struct clk_rate_request *req,
- struct clk_hw *parent,
- unsigned long parent_rate,
-@@ -496,6 +578,8 @@ at91_clk_register_master_internal(struct
- struct clk_master *master;
- struct clk_init_data init;
- struct clk_hw *hw;
-+ unsigned int mckr;
-+ unsigned long irqflags;
- int ret;
-
- if (!name || !num_parents || !parent_names || !lock)
-@@ -518,6 +602,16 @@ at91_clk_register_master_internal(struct
- master->chg_pid = chg_pid;
- master->lock = lock;
-
-+ if (ops == &master_div_ops_chg) {
-+ spin_lock_irqsave(master->lock, irqflags);
-+ regmap_read(master->regmap, master->layout->offset, &mckr);
-+ spin_unlock_irqrestore(master->lock, irqflags);
-+
-+ mckr &= layout->mask;
-+ mckr = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
-+ master->div = characteristics->divisors[mckr];
-+ }
-+
- hw = &master->hw;
- ret = clk_hw_register(NULL, &master->hw);
- if (ret) {
-@@ -554,19 +648,29 @@ at91_clk_register_master_div(struct regm
- const char *name, const char *parent_name,
- const struct clk_master_layout *layout,
- const struct clk_master_characteristics *characteristics,
-- spinlock_t *lock, u32 flags)
-+ spinlock_t *lock, u32 flags, u32 safe_div)
- {
- const struct clk_ops *ops;
-+ struct clk_hw *hw;
-
- if (flags & CLK_SET_RATE_GATE)
- ops = &master_div_ops;
- else
- ops = &master_div_ops_chg;
-
-- return at91_clk_register_master_internal(regmap, name, 1,
-- &parent_name, layout,
-- characteristics, ops,
-- lock, flags, -EINVAL);
-+ hw = at91_clk_register_master_internal(regmap, name, 1,
-+ &parent_name, layout,
-+ characteristics, ops,
-+ lock, flags, -EINVAL);
-+
-+ if (!IS_ERR(hw) && safe_div) {
-+ master_div = to_clk_master(hw);
-+ master_div->safe_div = safe_div;
-+ clk_notifier_register(hw->clk,
-+ &clk_master_div_notifier);
-+ }
-+
-+ return hw;
- }
-
- static unsigned long
---- a/drivers/clk/at91/dt-compat.c
-+++ b/drivers/clk/at91/dt-compat.c
-@@ -399,7 +399,7 @@ of_at91_clk_master_setup(struct device_n
-
- hw = at91_clk_register_master_div(regmap, name, "masterck_pres",
- layout, characteristics,
-- &mck_lock, CLK_SET_RATE_GATE);
-+ &mck_lock, CLK_SET_RATE_GATE, 0);
- if (IS_ERR(hw))
- goto out_free_characteristics;
-
---- a/drivers/clk/at91/pmc.h
-+++ b/drivers/clk/at91/pmc.h
-@@ -182,7 +182,7 @@ at91_clk_register_master_div(struct regm
- const char *parent_names,
- const struct clk_master_layout *layout,
- const struct clk_master_characteristics *characteristics,
-- spinlock_t *lock, u32 flags);
-+ spinlock_t *lock, u32 flags, u32 safe_div);
-
- struct clk_hw * __init
- at91_clk_sama7g5_register_master(struct regmap *regmap,
---- a/drivers/clk/at91/sama5d2.c
-+++ b/drivers/clk/at91/sama5d2.c
-@@ -249,7 +249,7 @@ static void __init sama5d2_pmc_setup(str
- "masterck_pres",
- &at91sam9x5_master_layout,
- &mck_characteristics, &mck_lock,
-- CLK_SET_RATE_GATE);
-+ CLK_SET_RATE_GATE, 0);
- if (IS_ERR(hw))
- goto err_free;
-
---- a/drivers/clk/at91/sama5d3.c
-+++ b/drivers/clk/at91/sama5d3.c
-@@ -184,7 +184,7 @@ static void __init sama5d3_pmc_setup(str
- "masterck_pres",
- &at91sam9x5_master_layout,
- &mck_characteristics, &mck_lock,
-- CLK_SET_RATE_GATE);
-+ CLK_SET_RATE_GATE, 0);
- if (IS_ERR(hw))
- goto err_free;
-
---- a/drivers/clk/at91/sama5d4.c
-+++ b/drivers/clk/at91/sama5d4.c
-@@ -199,7 +199,7 @@ static void __init sama5d4_pmc_setup(str
- "masterck_pres",
- &at91sam9x5_master_layout,
- &mck_characteristics, &mck_lock,
-- CLK_SET_RATE_GATE);
-+ CLK_SET_RATE_GATE, 0);
- if (IS_ERR(hw))
- goto err_free;
-
---- a/drivers/clk/at91/sama7g5.c
-+++ b/drivers/clk/at91/sama7g5.c
-@@ -993,7 +993,7 @@ static void __init sama7g5_pmc_setup(str
- parent_names[0] = "cpupll_divpmcck";
- hw = at91_clk_register_master_div(regmap, "mck0", "cpupll_divpmcck",
- &mck0_layout, &mck0_characteristics,
-- &pmc_mck0_lock, 0);
-+ &pmc_mck0_lock, CLK_GET_RATE_NOCACHE, 5);
- if (IS_ERR(hw))
- goto err_free;
-
+++ /dev/null
-From 9fd5a49f6da9de5da83f4a53eccefad647ab15ed Mon Sep 17 00:00:00 2001
-From: Claudiu Beznea <claudiu.beznea@microchip.com>
-Date: Mon, 11 Oct 2021 14:27:18 +0300
-Subject: [PATCH 246/247] clk: at91: sama7g5: set low limit for mck0 at 32KHz
-
-MCK0 could go as low as 32KHz. Set this limit.
-
-Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
-Link: https://lore.kernel.org/r/20211011112719.3951784-15-claudiu.beznea@microchip.com
-Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/at91/sama7g5.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/clk/at91/sama7g5.c
-+++ b/drivers/clk/at91/sama7g5.c
-@@ -849,7 +849,7 @@ static const struct {
-
- /* MCK0 characteristics. */
- static const struct clk_master_characteristics mck0_characteristics = {
-- .output = { .min = 50000000, .max = 200000000 },
-+ .output = { .min = 32768, .max = 200000000 },
- .divisors = { 1, 2, 4, 3, 5 },
- .have_div3_pres = 1,
- };
+++ /dev/null
-From fe07791494a78d5a4be1363385e6ba7940740644 Mon Sep 17 00:00:00 2001
-From: Claudiu Beznea <claudiu.beznea@microchip.com>
-Date: Mon, 11 Oct 2021 14:27:19 +0300
-Subject: [PATCH 247/247] clk: use clk_core_get_rate_recalc() in clk_rate_get()
-
-In case clock flags contains CLK_GET_RATE_NOCACHE the clk_rate_get()
-will return the cached rate. Thus, use clk_core_get_rate_recalc() which
-takes proper action when clock flags contains CLK_GET_RATE_NOCACHE.
-
-Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
-Link: https://lore.kernel.org/r/20211011112719.3951784-16-claudiu.beznea@microchip.com
-Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
-[sboyd@kernel.org: Grab prepare lock around operation]
-Signed-off-by: Stephen Boyd <sboyd@kernel.org>
----
- drivers/clk/clk.c | 5 ++++-
- 1 file changed, 4 insertions(+), 1 deletion(-)
-
---- a/drivers/clk/clk.c
-+++ b/drivers/clk/clk.c
-@@ -3145,7 +3145,10 @@ static int clk_rate_get(void *data, u64
- {
- struct clk_core *core = data;
-
-- *val = core->rate;
-+ clk_prepare_lock();
-+ *val = clk_core_get_rate_recalc(core);
-+ clk_prepare_unlock();
-+
- return 0;
- }
-
--- /dev/null
+From 5d8ae2928f71f0f9c2c3f8f13d00ecec35649ad3 Mon Sep 17 00:00:00 2001
+From: Arnd Bergmann <arnd@arndb.de>
+Date: Thu, 15 Dec 2022 17:42:54 +0100
+Subject: [PATCH] pinctrl: at91: convert to NOIRQ_SYSTEM_SLEEP_PM_OPS
+
+With the old SET_NOIRQ_SYSTEM_SLEEP_PM_OPS, some configs result in a
+build warning:
+
+drivers/pinctrl/pinctrl-at91.c:1668:12: error: 'at91_gpio_resume' defined but not used [-Werror=unused-function]
+ 1668 | static int at91_gpio_resume(struct device *dev)
+ | ^~~~~~~~~~~~~~~~
+drivers/pinctrl/pinctrl-at91.c:1650:12: error: 'at91_gpio_suspend' defined but not used [-Werror=unused-function]
+ 1650 | static int at91_gpio_suspend(struct device *dev)
+ | ^~~~~~~~~~~~~~~~~
+
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Reviewed-by: Ryan Wanner <Ryan.Wanner@microchip.com>
+Link: https://lore.kernel.org/r/20221215164301.934805-1-arnd@kernel.org
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/pinctrl/pinctrl-at91.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/pinctrl/pinctrl-at91.c
++++ b/drivers/pinctrl/pinctrl-at91.c
+@@ -1921,7 +1921,7 @@ err:
+ }
+
+ static const struct dev_pm_ops at91_gpio_pm_ops = {
+- SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(at91_gpio_suspend, at91_gpio_resume)
++ NOIRQ_SYSTEM_SLEEP_PM_OPS(at91_gpio_suspend, at91_gpio_resume)
+ };
+
+ static struct platform_driver at91_gpio_driver = {
+++ /dev/null
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_AT91=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-# CONFIG_ARCH_MULTI_V4 is not set
-CONFIG_ARCH_MULTI_V4T=y
-CONFIG_ARCH_MULTI_V4_V5=y
-CONFIG_ARCH_MULTI_V5=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM=y
-CONFIG_ARM_CPU_SUSPEND=y
-CONFIG_ARM_CRYPTO=y
-CONFIG_ARM_HAS_SG_CHAIN=y
-CONFIG_ARM_L1_CACHE_SHIFT=5
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_UNWIND=y
-# CONFIG_AT91RM9200_WATCHDOG is not set
-CONFIG_AT91SAM9X_WATCHDOG=y
-# CONFIG_AT91_ADC is not set
-CONFIG_AT91_SAMA5D2_ADC=y
-CONFIG_AT91_SOC_ID=y
-# CONFIG_AT91_SOC_SFR is not set
-CONFIG_ATMEL_AIC5_IRQ=y
-CONFIG_ATMEL_AIC_IRQ=y
-CONFIG_ATMEL_CLOCKSOURCE_PIT=y
-CONFIG_ATMEL_CLOCKSOURCE_TCB=y
-CONFIG_ATMEL_EBI=y
-CONFIG_ATMEL_PIT=y
-CONFIG_ATMEL_PM=y
-CONFIG_ATMEL_SDRAMC=y
-CONFIG_ATMEL_SSC=y
-CONFIG_ATMEL_ST=y
-CONFIG_ATMEL_TCB_CLKSRC=y
-CONFIG_AT_HDMAC=y
-CONFIG_AT_XDMAC=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_PM=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_AT91=y
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_CPU_32v4T=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV4T=y
-CONFIG_CPU_ABRT_EV5TJ=y
-CONFIG_CPU_ARM920T=y
-CONFIG_CPU_ARM926T=y
-# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
-CONFIG_CPU_CACHE_V4WT=y
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_COPY_V4WB=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
-CONFIG_CPU_NO_EFFICIENT_FFS=y
-CONFIG_CPU_PABRT_LEGACY=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_USE_DOMAINS=y
-CONFIG_CRC16=y
-CONFIG_CRC7=y
-CONFIG_CRC_CCITT=y
-CONFIG_CRC_ITU_T=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-CONFIG_DMADEVICES=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_OPS=y
-CONFIG_DMA_REMAP=y
-CONFIG_DTC=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EEPROM_AT24=y
-CONFIG_EXT4_FS=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FREEZER=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_CACHE=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GLOB=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_CDEV=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_ATMEL=y
-CONFIG_HZ=128
-CONFIG_HZ_FIXED=128
-CONFIG_HZ_PERIODIC=y
-CONFIG_I2C=y
-CONFIG_I2C_ALGOBIT=y
-CONFIG_I2C_AT91=y
-# CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL is not set
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_COMPAT=y
-CONFIG_I2C_GPIO=y
-CONFIG_IIO=y
-CONFIG_IIO_BUFFER=y
-CONFIG_IIO_KFIFO_BUF=y
-CONFIG_IIO_TRIGGER=y
-CONFIG_IIO_TRIGGERED_BUFFER=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD2=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_PWM=y
-CONFIG_LEDS_TRIGGER_CPU=y
-CONFIG_LEDS_TRIGGER_GPIO=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MACB=y
-CONFIG_MACB_USE_HWSTAMP=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MEMORY=y
-CONFIG_MFD_AT91_USART=y
-CONFIG_MFD_ATMEL_FLEXCOM=y
-CONFIG_MFD_ATMEL_HLCDC=y
-CONFIG_MFD_ATMEL_SMC=y
-CONFIG_MFD_CORE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MICREL_PHY=y
-CONFIG_MICROCHIP_PIT64B=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_ATMELMCI=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_OF_AT91=y
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_DATAFLASH=y
-# CONFIG_MTD_DATAFLASH_OTP is not set
-# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-# CONFIG_MTD_UBI_BLOCK is not set
-CONFIG_MTD_UBI_FASTMAP=y
-CONFIG_MTD_UBI_GLUEBI=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_KUSER_HELPERS=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NLS=y
-CONFIG_NVMEM=y
-# CONFIG_NVMEM_MICROCHIP_OTPC is not set
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_AT91=y
-# CONFIG_PINCTRL_AT91PIO4 is not set
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_PM_SLEEP=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_AT91_POWEROFF=y
-CONFIG_POWER_RESET_AT91_RESET=y
-CONFIG_POWER_RESET_AT91_SAMA5D2_SHDWC=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PPS=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
-CONFIG_PWM_ATMEL=y
-CONFIG_PWM_ATMEL_HLCDC_PWM=y
-CONFIG_PWM_ATMEL_TCB=y
-CONFIG_PWM_SYSFS=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_AT91RM9200=y
-CONFIG_RTC_DRV_AT91SAM9=y
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RTC_MC146818_LIB=y
-CONFIG_SAMA5D4_WATCHDOG=y
-# CONFIG_SERIAL_8250 is not set
-CONFIG_SERIAL_ATMEL=y
-CONFIG_SERIAL_ATMEL_CONSOLE=y
-CONFIG_SERIAL_ATMEL_PDC=y
-# CONFIG_SERIAL_ATMEL_TTYAT is not set
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SOC_AT91RM9200=y
-CONFIG_SOC_AT91SAM9=y
-CONFIG_SOC_BUS=y
-CONFIG_SOC_SAM9X60=y
-CONFIG_SOC_SAM_V4_V5=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-# CONFIG_SPI_AT91_USART is not set
-CONFIG_SPI_ATMEL=y
-CONFIG_SPI_ATMEL_QUADSPI=y
-CONFIG_SPI_BITBANG=y
-CONFIG_SPI_GPIO=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_SPIDEV=y
-CONFIG_SPLIT_PTLOCK_CPUS=999999
-CONFIG_SRAM=y
-CONFIG_SRAM_EXEC=y
-CONFIG_SRCU=y
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_SWPHY=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TINY_SRCU=y
-CONFIG_UBIFS_FS=y
-CONFIG_UBIFS_FS_ADVANCED_COMPR=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB=y
-CONFIG_USB_ACM=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-# CONFIG_USB_AT91 is not set
-# CONFIG_USB_ATMEL_USBA is not set
-CONFIG_USB_COMMON=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_HCD_AT91=y
-# CONFIG_USB_EHCI_HCD_PLATFORM is not set
-CONFIG_USB_GADGET=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_OHCI_HCD_AT91=y
-CONFIG_USB_OHCI_HCD_PLATFORM=y
-CONFIG_USB_SERIAL=y
-# CONFIG_USB_SERIAL_CONSOLE is not set
-CONFIG_USB_SERIAL_FTDI_SIO=y
-CONFIG_USB_SERIAL_PL2303=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-# CONFIG_VFP is not set
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XXHASH=y
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
--- /dev/null
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_AT91=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MULTIPLATFORM=y
+# CONFIG_ARCH_MULTI_V4 is not set
+CONFIG_ARCH_MULTI_V4T=y
+CONFIG_ARCH_MULTI_V4_V5=y
+CONFIG_ARCH_MULTI_V5=y
+CONFIG_ARCH_NR_GPIO=0
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARM=y
+CONFIG_ARM_CPU_SUSPEND=y
+CONFIG_ARM_HAS_GROUP_RELOCS=y
+CONFIG_ARM_L1_CACHE_SHIFT=5
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_UNWIND=y
+# CONFIG_AT91RM9200_WATCHDOG is not set
+CONFIG_AT91SAM9X_WATCHDOG=y
+# CONFIG_AT91_ADC is not set
+CONFIG_AT91_SAMA5D2_ADC=y
+CONFIG_AT91_SOC_ID=y
+# CONFIG_AT91_SOC_SFR is not set
+CONFIG_ATMEL_AIC5_IRQ=y
+CONFIG_ATMEL_AIC_IRQ=y
+CONFIG_ATMEL_CLOCKSOURCE_PIT=y
+CONFIG_ATMEL_CLOCKSOURCE_TCB=y
+CONFIG_ATMEL_EBI=y
+CONFIG_ATMEL_PIT=y
+CONFIG_ATMEL_PM=y
+CONFIG_ATMEL_SDRAMC=y
+CONFIG_ATMEL_SSC=y
+CONFIG_ATMEL_ST=y
+CONFIG_ATMEL_TCB_CLKSRC=y
+CONFIG_AT_HDMAC=y
+CONFIG_AT_XDMAC=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
+CONFIG_BLK_PM=y
+CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_AT91=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_CPU_32v4T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV4T=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_ARM920T=y
+CONFIG_CPU_ARM926T=y
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+CONFIG_CPU_CACHE_V4WT=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_NO_EFFICIENT_FFS=y
+CONFIG_CPU_PABRT_LEGACY=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_USE_DOMAINS=y
+CONFIG_CRC16=y
+CONFIG_CRC7=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+CONFIG_DMADEVICES=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_OPS=y
+CONFIG_DTC=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EEPROM_AT24=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_EXT4_FS=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FREEZER=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_CACHE=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC10_NO_ARRAY_BOUNDS=y
+CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GLOB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_ATMEL=y
+CONFIG_HZ=128
+CONFIG_HZ_FIXED=128
+CONFIG_HZ_PERIODIC=y
+CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_AT91=y
+# CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL is not set
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_GPIO=y
+CONFIG_IIO=y
+CONFIG_IIO_BUFFER=y
+CONFIG_IIO_KFIFO_BUF=y
+CONFIG_IIO_TRIGGER=y
+CONFIG_IIO_TRIGGERED_BUFFER=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INPUT=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQSTACKS=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+CONFIG_JBD2=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_PWM=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MACB=y
+CONFIG_MACB_USE_HWSTAMP=y
+# CONFIG_MCHP_EIC is not set
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MEMFD_CREATE=y
+CONFIG_MEMORY=y
+CONFIG_MFD_AT91_USART=y
+CONFIG_MFD_ATMEL_FLEXCOM=y
+CONFIG_MFD_ATMEL_HLCDC=y
+CONFIG_MFD_ATMEL_SMC=y
+CONFIG_MFD_CORE=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MICREL_PHY=y
+CONFIG_MICROCHIP_CLOCKSOURCE_PIT64B=y
+CONFIG_MICROCHIP_PIT64B=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_ATMELMCI=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_OF_AT91=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_DATAFLASH=y
+# CONFIG_MTD_DATAFLASH_OTP is not set
+# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+# CONFIG_MTD_UBI_BLOCK is not set
+CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_KUSER_HELPERS=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NLS=y
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+# CONFIG_NVMEM_MICROCHIP_OTPC is not set
+CONFIG_NVMEM_SYSFS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+CONFIG_PHYLINK=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
+# CONFIG_PINCTRL_AT91PIO4 is not set
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_PM_SLEEP=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_AT91_POWEROFF=y
+CONFIG_POWER_RESET_AT91_RESET=y
+CONFIG_POWER_RESET_AT91_SAMA5D2_SHDWC=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PPS=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_PWM=y
+CONFIG_PWM_ATMEL=y
+CONFIG_PWM_ATMEL_HLCDC_PWM=y
+CONFIG_PWM_ATMEL_TCB=y
+CONFIG_PWM_SYSFS=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RATIONAL=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_AT91RM9200=y
+CONFIG_RTC_DRV_AT91SAM9=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RTC_MC146818_LIB=y
+CONFIG_SAMA5D4_WATCHDOG=y
+# CONFIG_SERIAL_8250 is not set
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+CONFIG_SERIAL_ATMEL_PDC=y
+# CONFIG_SERIAL_ATMEL_TTYAT is not set
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SOC_AT91RM9200=y
+CONFIG_SOC_AT91SAM9=y
+CONFIG_SOC_BUS=y
+CONFIG_SOC_SAM9X60=y
+CONFIG_SOC_SAM_V4_V5=y
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+# CONFIG_SPI_AT91_USART is not set
+CONFIG_SPI_ATMEL=y
+CONFIG_SPI_ATMEL_QUADSPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_GPIO=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SPI_SPIDEV=y
+CONFIG_SPLIT_PTLOCK_CPUS=999999
+CONFIG_SRAM=y
+CONFIG_SRAM_EXEC=y
+CONFIG_SRCU=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_SWPHY=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TINY_SRCU=y
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNWINDER_ARM=y
+CONFIG_USB=y
+CONFIG_USB_ACM=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+# CONFIG_USB_AT91 is not set
+# CONFIG_USB_ATMEL_USBA is not set
+CONFIG_USB_COMMON=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_AT91=y
+# CONFIG_USB_EHCI_HCD_PLATFORM is not set
+CONFIG_USB_GADGET=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_AT91=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_SERIAL=y
+# CONFIG_USB_SERIAL_CONSOLE is not set
+CONFIG_USB_SERIAL_FTDI_SIO=y
+CONFIG_USB_SERIAL_PL2303=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+# CONFIG_VFP is not set
+# CONFIG_VIDEO_ATMEL_XISC is not set
+# CONFIG_VIDEO_MICROCHIP_CSI2DC is not set
+CONFIG_WATCHDOG_CORE=y
+CONFIG_XXHASH=y
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZSTD_COMMON=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y
+++ /dev/null
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_AT91=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM=y
-CONFIG_ARM_AT91_CPUIDLE=y
-CONFIG_ARM_CPU_SUSPEND=y
-CONFIG_ARM_CRYPTO=y
-CONFIG_ARM_HAS_SG_CHAIN=y
-CONFIG_ARM_HEAVY_MB=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-CONFIG_ARM_PATCH_IDIV=y
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_AT91SAM9X_WATCHDOG=y
-CONFIG_AT91_ADC=y
-CONFIG_AT91_SAMA5D2_ADC=y
-CONFIG_AT91_SOC_ID=y
-# CONFIG_AT91_SOC_SFR is not set
-CONFIG_ATMEL_AIC5_IRQ=y
-# CONFIG_ATMEL_CLOCKSOURCE_PIT is not set
-CONFIG_ATMEL_CLOCKSOURCE_TCB=y
-CONFIG_ATMEL_EBI=y
-CONFIG_ATMEL_PM=y
-CONFIG_ATMEL_SDRAMC=y
-CONFIG_ATMEL_SSC=y
-CONFIG_ATMEL_TCB_CLKSRC=y
-CONFIG_AT_HDMAC=y
-CONFIG_AT_XDMAC=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_PWM=y
-CONFIG_BATTERY_ACT8945A=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=4
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_PM=y
-CONFIG_CACHE_L2X0=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMA=y
-CONFIG_CMA_ALIGNMENT=8
-CONFIG_CMA_AREAS=7
-# CONFIG_CMA_DEBUG is not set
-# CONFIG_CMA_DEBUGFS is not set
-CONFIG_CMA_SIZE_MBYTES=16
-# CONFIG_CMA_SIZE_SEL_MAX is not set
-CONFIG_CMA_SIZE_SEL_MBYTES=y
-# CONFIG_CMA_SIZE_SEL_MIN is not set
-# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
-# CONFIG_CMA_SYSFS is not set
-CONFIG_CMDLINE="console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw"
-CONFIG_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_AT91=y
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_CONTIG_ALLOC=y
-CONFIG_COREDUMP=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_SPECTRE=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRASH_CORE=y
-CONFIG_CRASH_DUMP=y
-CONFIG_CRC16=y
-# CONFIG_CRC32_SARWATE is not set
-CONFIG_CRC32_SLICEBY8=y
-CONFIG_CROSS_MEMORY_ATTACH=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_DRBG=y
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_MENU=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_JITTERENTROPY=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=y
-CONFIG_CRYPTO_SEQIV=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-CONFIG_DEBUG_MEMORY_INIT=y
-CONFIG_DEBUG_USER=y
-CONFIG_DMADEVICES=y
-CONFIG_DMA_CMA=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_OPS=y
-CONFIG_DMA_REMAP=y
-CONFIG_DMA_SHARED_BUFFER=y
-CONFIG_DNOTIFY=y
-CONFIG_DRM=y
-CONFIG_DRM_ATMEL_HLCDC=y
-CONFIG_DRM_BRIDGE=y
-CONFIG_DRM_DP_AUX_BUS=y
-CONFIG_DRM_FBDEV_EMULATION=y
-CONFIG_DRM_FBDEV_OVERALLOC=100
-CONFIG_DRM_GEM_CMA_HELPER=y
-CONFIG_DRM_KMS_CMA_HELPER=y
-CONFIG_DRM_KMS_HELPER=y
-CONFIG_DRM_PANEL=y
-CONFIG_DRM_PANEL_BRIDGE=y
-CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
-CONFIG_DRM_PANEL_SIMPLE=y
-CONFIG_DTC=y
-CONFIG_DVB_CORE=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EEPROM_AT24=y
-CONFIG_ELF_CORE=y
-CONFIG_EXT4_FS=y
-CONFIG_FAT_FS=y
-CONFIG_FB=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-CONFIG_FB_CMDLINE=y
-CONFIG_FB_DEFERRED_IO=y
-CONFIG_FB_SYS_COPYAREA=y
-CONFIG_FB_SYS_FILLRECT=y
-CONFIG_FB_SYS_FOPS=y
-CONFIG_FB_SYS_IMAGEBLIT=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FORCE_MAX_ZONEORDER=15
-CONFIG_FREEZER=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_CACHE=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GENERIC_VDSO_32=y
-CONFIG_GLOB=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_CDEV=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-# CONFIG_HARDEN_BRANCH_HISTORY is not set
-# CONFIG_HARDEN_BRANCH_PREDICTOR is not set
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAVE_SMP=y
-CONFIG_HDMI=y
-CONFIG_HID=y
-CONFIG_HID_GENERIC=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_ATMEL=y
-CONFIG_HZ_FIXED=0
-CONFIG_I2C=y
-CONFIG_I2C_ALGOBIT=y
-CONFIG_I2C_AT91=y
-# CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL is not set
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_COMPAT=y
-CONFIG_I2C_GPIO=y
-CONFIG_I2C_HELPER_AUTO=y
-CONFIG_IIO=y
-CONFIG_IIO_BUFFER=y
-CONFIG_IIO_KFIFO_BUF=y
-CONFIG_IIO_TRIGGER=y
-CONFIG_IIO_TRIGGERED_BUFFER=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-CONFIG_INPUT_EVDEV=y
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_INPUT_LEDS=y
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD2=y
-# CONFIG_JFFS2_FS is not set
-CONFIG_KCMP=y
-CONFIG_KERNEL_GZIP=y
-# CONFIG_KERNEL_XZ is not set
-CONFIG_KEXEC=y
-CONFIG_KEXEC_CORE=y
-CONFIG_KEYBOARD_GPIO=y
-CONFIG_KEYBOARD_QT1070=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_PWM=y
-CONFIG_LEDS_TRIGGER_CPU=y
-CONFIG_LEDS_TRIGGER_GPIO=y
-CONFIG_LIBFDT=y
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOG_BUF_SHIFT=16
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MACB=y
-CONFIG_MACB_USE_HWSTAMP=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
-CONFIG_MEDIA_ATTACH=y
-CONFIG_MEDIA_CAMERA_SUPPORT=y
-CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
-CONFIG_MEDIA_PLATFORM_SUPPORT=y
-CONFIG_MEDIA_RADIO_SUPPORT=y
-CONFIG_MEDIA_SDR_SUPPORT=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_MEDIA_TEST_SUPPORT=y
-CONFIG_MEDIA_TUNER=y
-CONFIG_MEDIA_USB_SUPPORT=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MEMORY=y
-CONFIG_MEMORY_ISOLATION=y
-CONFIG_MFD_ACT8945A=y
-CONFIG_MFD_AT91_USART=y
-CONFIG_MFD_ATMEL_FLEXCOM=y
-CONFIG_MFD_ATMEL_HLCDC=y
-CONFIG_MFD_ATMEL_SMC=y
-CONFIG_MFD_CORE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MICREL_PHY=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_ATMELMCI=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_OF_AT91=y
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MODULES_USE_ELF_REL=y
-# CONFIG_MTD_CFI_AMDSTD is not set
-# CONFIG_MTD_CFI_INTELEXT is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-# CONFIG_MTD_UBI_BLOCK is not set
-CONFIG_MTD_UBI_FASTMAP=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-# CONFIG_NEON is not set
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NLS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_UTF8=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NVMEM=y
-# CONFIG_NVMEM_MICROCHIP_OTPC is not set
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_OUTER_CACHE=y
-CONFIG_OUTER_CACHE_SYNC=y
-CONFIG_PAGE_OFFSET=0xC0000000
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_AT91=y
-CONFIG_PINCTRL_AT91PIO4=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_PM_SLEEP=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_AT91_POWEROFF=y
-CONFIG_POWER_RESET_AT91_RESET=y
-CONFIG_POWER_RESET_AT91_SAMA5D2_SHDWC=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PPS=y
-# CONFIG_PREVENT_FIRMWARE_BUILD is not set
-CONFIG_PRINTK_TIME=y
-CONFIG_PROC_VMCORE=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
-CONFIG_PWM_ATMEL=y
-CONFIG_PWM_ATMEL_HLCDC_PWM=y
-CONFIG_PWM_ATMEL_TCB=y
-CONFIG_PWM_SYSFS=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGMAP_SPI=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_ACT8865=y
-CONFIG_REGULATOR_ACT8945A=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_AT91RM9200=y
-# CONFIG_RTC_DRV_AT91SAM9 is not set
-# CONFIG_RTC_DRV_CMOS is not set
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_SAMA5D4_WATCHDOG=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-# CONFIG_SCSI_LOWLEVEL is not set
-# CONFIG_SERIAL_8250 is not set
-CONFIG_SERIAL_ATMEL=y
-CONFIG_SERIAL_ATMEL_CONSOLE=y
-CONFIG_SERIAL_ATMEL_PDC=y
-# CONFIG_SERIAL_ATMEL_TTYAT is not set
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SG_POOL=y
-CONFIG_SND=y
-CONFIG_SND_ARM=y
-# CONFIG_SND_AT73C213 is not set
-# CONFIG_SND_AT91_SOC_SAM9G20_WM8731 is not set
-# CONFIG_SND_AT91_SOC_SAM9X5_WM8731 is not set
-CONFIG_SND_ATMEL_SOC=y
-CONFIG_SND_ATMEL_SOC_CLASSD=y
-CONFIG_SND_ATMEL_SOC_DMA=y
-CONFIG_SND_ATMEL_SOC_I2S=y
-CONFIG_SND_ATMEL_SOC_PDC=y
-# CONFIG_SND_ATMEL_SOC_PDMIC is not set
-CONFIG_SND_ATMEL_SOC_SSC=y
-CONFIG_SND_ATMEL_SOC_SSC_DMA=y
-# CONFIG_SND_ATMEL_SOC_SSC_PDC is not set
-# CONFIG_SND_ATMEL_SOC_TSE850_PCM5142 is not set
-CONFIG_SND_ATMEL_SOC_WM8904=y
-# CONFIG_SND_COMPRESS_OFFLOAD is not set
-CONFIG_SND_DMAENGINE_PCM=y
-CONFIG_SND_JACK=y
-CONFIG_SND_JACK_INPUT_DEV=y
-# CONFIG_SND_MCHP_SOC_I2S_MCC is not set
-# CONFIG_SND_MCHP_SOC_SPDIFRX is not set
-# CONFIG_SND_MCHP_SOC_SPDIFTX is not set
-CONFIG_SND_PCM=y
-CONFIG_SND_PCM_TIMER=y
-CONFIG_SND_SOC=y
-CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
-CONFIG_SND_SOC_I2C_AND_SPI=y
-CONFIG_SND_SOC_MIKROE_PROTO=y
-CONFIG_SND_SOC_WM8731=y
-CONFIG_SND_SOC_WM8904=y
-CONFIG_SND_SPI=y
-CONFIG_SND_SUPPORT_OLD_API=y
-CONFIG_SND_TIMER=y
-CONFIG_SOC_BUS=y
-CONFIG_SOC_SAMA5=y
-CONFIG_SOC_SAMA5D2=y
-CONFIG_SOC_SAMA5D3=y
-CONFIG_SOC_SAMA5D4=y
-# CONFIG_SOC_SAMA7G5 is not set
-CONFIG_SOC_SAM_V7=y
-CONFIG_SOUND=y
-CONFIG_SOUND_OSS_CORE=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-# CONFIG_SPI_AT91_USART is not set
-CONFIG_SPI_ATMEL=y
-CONFIG_SPI_ATMEL_QUADSPI=y
-CONFIG_SPI_BITBANG=y
-CONFIG_SPI_GPIO=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-# CONFIG_SQUASHFS is not set
-CONFIG_SRAM=y
-CONFIG_SRAM_EXEC=y
-CONFIG_SRCU=y
-# CONFIG_STANDALONE is not set
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_SWPHY=y
-# CONFIG_SWP_EMULATE is not set
-CONFIG_SYNC_FILE=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TINY_SRCU=y
-CONFIG_TOUCHSCREEN_ATMEL_MXT=y
-CONFIG_UACCESS_WITH_MEMCPY=y
-CONFIG_UBIFS_FS=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB=y
-CONFIG_USB_ACM=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-# CONFIG_USB_AT91 is not set
-# CONFIG_USB_ATMEL_USBA is not set
-CONFIG_USB_COMMON=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_HCD_AT91=y
-# CONFIG_USB_EHCI_HCD_PLATFORM is not set
-# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
-CONFIG_USB_GADGET=y
-CONFIG_USB_HID=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_OHCI_HCD_AT91=y
-CONFIG_USB_OHCI_HCD_PLATFORM=y
-# CONFIG_USB_PWC is not set
-CONFIG_USB_SERIAL=y
-# CONFIG_USB_SERIAL_CONSOLE is not set
-CONFIG_USB_SERIAL_FTDI_SIO=y
-CONFIG_USB_SERIAL_PL2303=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-CONFIG_V4L_PLATFORM_DRIVERS=y
-CONFIG_VFAT_FS=y
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_VIDEOMODE_HELPERS=y
-# CONFIG_VIDEO_CPIA2 is not set
-CONFIG_VIDEO_DEV=y
-CONFIG_VIDEO_V4L2=y
-CONFIG_VIDEO_V4L2_I2C=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_WATCHDOG_CORE=y
-# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
-CONFIG_XXHASH=y
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
--- /dev/null
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_AT91=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MULTIPLATFORM=y
+CONFIG_ARCH_MULTI_V6_V7=y
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_ARCH_NR_GPIO=0
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARM=y
+CONFIG_ARM_AT91_CPUIDLE=y
+CONFIG_ARM_CPU_SUSPEND=y
+CONFIG_ARM_HAS_GROUP_RELOCS=y
+CONFIG_ARM_HEAVY_MB=y
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+CONFIG_ARM_PATCH_IDIV=y
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_UNWIND=y
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_AT91SAM9X_WATCHDOG=y
+CONFIG_AT91_ADC=y
+CONFIG_AT91_SAMA5D2_ADC=y
+CONFIG_AT91_SOC_ID=y
+# CONFIG_AT91_SOC_SFR is not set
+CONFIG_ATMEL_AIC5_IRQ=y
+# CONFIG_ATMEL_CLOCKSOURCE_PIT is not set
+CONFIG_ATMEL_CLOCKSOURCE_TCB=y
+CONFIG_ATMEL_EBI=y
+CONFIG_ATMEL_PM=y
+CONFIG_ATMEL_SDRAMC=y
+# CONFIG_ATMEL_SECURE_PM is not set
+CONFIG_ATMEL_SSC=y
+CONFIG_ATMEL_TCB_CLKSRC=y
+CONFIG_AT_HDMAC=y
+CONFIG_AT_XDMAC=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_PWM=y
+CONFIG_BATTERY_ACT8945A=y
+CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=4
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_PM=y
+CONFIG_CACHE_L2X0=y
+CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMA=y
+CONFIG_CMA_ALIGNMENT=8
+CONFIG_CMA_AREAS=7
+# CONFIG_CMA_DEBUG is not set
+# CONFIG_CMA_DEBUGFS is not set
+CONFIG_CMA_SIZE_MBYTES=16
+# CONFIG_CMA_SIZE_SEL_MAX is not set
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+# CONFIG_CMA_SIZE_SEL_MIN is not set
+# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
+# CONFIG_CMA_SYSFS is not set
+CONFIG_CMDLINE="console=ttyS0,115200 initrd=0x21100000,25165824 root=/dev/ram0 rw"
+CONFIG_CMDLINE_FROM_BOOTLOADER=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_AT91=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_CONTIG_ALLOC=y
+CONFIG_COREDUMP=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_SPECTRE=y
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_V7=y
+CONFIG_CRASH_CORE=y
+CONFIG_CRASH_DUMP=y
+CONFIG_CRC16=y
+# CONFIG_CRC32_SARWATE is not set
+CONFIG_CRC32_SLICEBY8=y
+CONFIG_CROSS_MEMORY_ATTACH=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_DRBG_HMAC=y
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_SHA256=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RNG_DEFAULT=y
+CONFIG_CRYPTO_SEQIV=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_DEBUG_USER=y
+CONFIG_DMADEVICES=y
+CONFIG_DMA_CMA=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_OPS=y
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_DNOTIFY=y
+CONFIG_DRM=y
+CONFIG_DRM_ATMEL_HLCDC=y
+CONFIG_DRM_BRIDGE=y
+CONFIG_DRM_FBDEV_EMULATION=y
+CONFIG_DRM_FBDEV_OVERALLOC=100
+CONFIG_DRM_GEM_DMA_HELPER=y
+CONFIG_DRM_KMS_HELPER=y
+CONFIG_DRM_NOMODESET=y
+CONFIG_DRM_PANEL=y
+CONFIG_DRM_PANEL_BRIDGE=y
+CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
+CONFIG_DRM_PANEL_SIMPLE=y
+CONFIG_DTC=y
+CONFIG_DVB_CORE=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EEPROM_AT24=y
+CONFIG_ELF_CORE=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_EXT4_FS=y
+CONFIG_FAT_FS=y
+CONFIG_FB=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+CONFIG_FB_CMDLINE=y
+CONFIG_FB_DEFERRED_IO=y
+CONFIG_FB_SYS_COPYAREA=y
+CONFIG_FB_SYS_FILLRECT=y
+CONFIG_FB_SYS_FOPS=y
+CONFIG_FB_SYS_IMAGEBLIT=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FREEZER=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_CACHE=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC10_NO_ARRAY_BOUNDS=y
+CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_VDSO_32=y
+CONFIG_GLOB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+# CONFIG_HARDEN_BRANCH_HISTORY is not set
+# CONFIG_HARDEN_BRANCH_PREDICTOR is not set
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HAVE_SMP=y
+CONFIG_HDMI=y
+CONFIG_HID=y
+CONFIG_HID_GENERIC=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_ATMEL=y
+CONFIG_HZ_FIXED=0
+CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_AT91=y
+# CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL is not set
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_GPIO=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_IIO=y
+CONFIG_IIO_BUFFER=y
+CONFIG_IIO_KFIFO_BUF=y
+CONFIG_IIO_TRIGGER=y
+CONFIG_IIO_TRIGGERED_BUFFER=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INPUT=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_INPUT_LEDS=y
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQSTACKS=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+CONFIG_JBD2=y
+# CONFIG_JFFS2_FS is not set
+CONFIG_KCMP=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_XZ is not set
+CONFIG_KEXEC=y
+CONFIG_KEXEC_CORE=y
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_QT1070=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_PWM=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LIBFDT=y
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MACB=y
+CONFIG_MACB_USE_HWSTAMP=y
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_MCHP_EIC is not set
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
+CONFIG_MEDIA_ATTACH=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
+CONFIG_MEDIA_PLATFORM_SUPPORT=y
+CONFIG_MEDIA_RADIO_SUPPORT=y
+CONFIG_MEDIA_SDR_SUPPORT=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_TEST_SUPPORT=y
+CONFIG_MEDIA_TUNER=y
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_MEMFD_CREATE=y
+CONFIG_MEMORY=y
+CONFIG_MEMORY_ISOLATION=y
+CONFIG_MFD_ACT8945A=y
+CONFIG_MFD_AT91_USART=y
+CONFIG_MFD_ATMEL_FLEXCOM=y
+CONFIG_MFD_ATMEL_HLCDC=y
+CONFIG_MFD_ATMEL_SMC=y
+CONFIG_MFD_CORE=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MICREL_PHY=y
+# CONFIG_MICROCHIP_CLOCKSOURCE_PIT64B is not set
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_ATMELMCI=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_OF_AT91=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MODULES_USE_ELF_REL=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+# CONFIG_MTD_UBI_BLOCK is not set
+CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_KM=y
+# CONFIG_NEON is not set
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NLS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+# CONFIG_NVMEM_MICROCHIP_OTPC is not set
+CONFIG_NVMEM_SYSFS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_OUTER_CACHE=y
+CONFIG_OUTER_CACHE_SYNC=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+CONFIG_PHYLINK=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
+CONFIG_PINCTRL_AT91PIO4=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_PM_SLEEP=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_AT91_POWEROFF=y
+CONFIG_POWER_RESET_AT91_RESET=y
+CONFIG_POWER_RESET_AT91_SAMA5D2_SHDWC=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PPS=y
+CONFIG_PREEMPT_NONE_BUILD=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+CONFIG_PRINTK_TIME=y
+CONFIG_PROC_VMCORE=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_PWM=y
+CONFIG_PWM_ATMEL=y
+CONFIG_PWM_ATMEL_HLCDC_PWM=y
+CONFIG_PWM_ATMEL_TCB=y
+CONFIG_PWM_SYSFS=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RATIONAL=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGMAP_SPI=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_ACT8865=y
+CONFIG_REGULATOR_ACT8945A=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_AT91RM9200=y
+# CONFIG_RTC_DRV_AT91SAM9 is not set
+# CONFIG_RTC_DRV_CMOS is not set
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_SAMA5D4_WATCHDOG=y
+CONFIG_SCSI=y
+CONFIG_SCSI_COMMON=y
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SERIAL_8250 is not set
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+CONFIG_SERIAL_ATMEL_PDC=y
+# CONFIG_SERIAL_ATMEL_TTYAT is not set
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SG_POOL=y
+CONFIG_SND=y
+CONFIG_SND_ARM=y
+# CONFIG_SND_AT73C213 is not set
+# CONFIG_SND_AT91_SOC_SAM9G20_WM8731 is not set
+# CONFIG_SND_AT91_SOC_SAM9X5_WM8731 is not set
+CONFIG_SND_ATMEL_SOC=y
+CONFIG_SND_ATMEL_SOC_CLASSD=y
+CONFIG_SND_ATMEL_SOC_DMA=y
+CONFIG_SND_ATMEL_SOC_I2S=y
+CONFIG_SND_ATMEL_SOC_PDC=y
+# CONFIG_SND_ATMEL_SOC_PDMIC is not set
+CONFIG_SND_ATMEL_SOC_SSC=y
+CONFIG_SND_ATMEL_SOC_SSC_DMA=y
+# CONFIG_SND_ATMEL_SOC_SSC_PDC is not set
+# CONFIG_SND_ATMEL_SOC_TSE850_PCM5142 is not set
+CONFIG_SND_ATMEL_SOC_WM8904=y
+# CONFIG_SND_COMPRESS_OFFLOAD is not set
+CONFIG_SND_DMAENGINE_PCM=y
+CONFIG_SND_JACK=y
+CONFIG_SND_JACK_INPUT_DEV=y
+# CONFIG_SND_MCHP_SOC_I2S_MCC is not set
+# CONFIG_SND_MCHP_SOC_PDMC is not set
+# CONFIG_SND_MCHP_SOC_SPDIFRX is not set
+# CONFIG_SND_MCHP_SOC_SPDIFTX is not set
+CONFIG_SND_PCM=y
+CONFIG_SND_PCM_TIMER=y
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+CONFIG_SND_SOC_MIKROE_PROTO=y
+CONFIG_SND_SOC_WM8731=y
+CONFIG_SND_SOC_WM8904=y
+CONFIG_SND_SPI=y
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_TIMER=y
+CONFIG_SOC_BUS=y
+# CONFIG_SOC_LAN966 is not set
+CONFIG_SOC_SAMA5=y
+CONFIG_SOC_SAMA5D2=y
+CONFIG_SOC_SAMA5D3=y
+CONFIG_SOC_SAMA5D4=y
+# CONFIG_SOC_SAMA7G5 is not set
+CONFIG_SOC_SAM_V7=y
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+# CONFIG_SPI_AT91_USART is not set
+CONFIG_SPI_ATMEL=y
+CONFIG_SPI_ATMEL_QUADSPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_GPIO=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+# CONFIG_SQUASHFS is not set
+CONFIG_SRAM=y
+CONFIG_SRAM_EXEC=y
+CONFIG_SRCU=y
+# CONFIG_STANDALONE is not set
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_SWPHY=y
+# CONFIG_SWP_EMULATE is not set
+CONFIG_SYNC_FILE=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TINY_SRCU=y
+CONFIG_TOUCHSCREEN_ATMEL_MXT=y
+CONFIG_UACCESS_WITH_MEMCPY=y
+CONFIG_UBIFS_FS=y
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNWINDER_ARM=y
+CONFIG_USB=y
+CONFIG_USB_ACM=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+# CONFIG_USB_AT91 is not set
+# CONFIG_USB_ATMEL_USBA is not set
+CONFIG_USB_COMMON=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_AT91=y
+# CONFIG_USB_EHCI_HCD_PLATFORM is not set
+# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
+CONFIG_USB_GADGET=y
+CONFIG_USB_HID=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_AT91=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+# CONFIG_USB_PWC is not set
+CONFIG_USB_SERIAL=y
+# CONFIG_USB_SERIAL_CONSOLE is not set
+CONFIG_USB_SERIAL_FTDI_SIO=y
+CONFIG_USB_SERIAL_PL2303=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+CONFIG_VFAT_FS=y
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+# CONFIG_VIDEO_ATMEL_XISC is not set
+CONFIG_VIDEOMODE_HELPERS=y
+CONFIG_VIDEO_DEV=y
+# CONFIG_VIDEO_MICROCHIP_CSI2DC is not set
+CONFIG_VIDEO_V4L2_I2C=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_WATCHDOG_CORE=y
+# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
+CONFIG_XXHASH=y
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZSTD_COMMON=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y
+++ /dev/null
-CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_ALLOW_DEV_COREDUMP is not set
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_AT91=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM=y
-CONFIG_ARM_CRYPTO=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_HAS_SG_CHAIN=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-# CONFIG_ARM_PATCH_IDIV is not set
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ARM_VIRT_EXT=y
-# CONFIG_AT91SAM9X_WATCHDOG is not set
-# CONFIG_AT91_ADC is not set
-CONFIG_AT91_SAMA5D2_ADC=y
-CONFIG_AT91_SOC_ID=y
-# CONFIG_AT91_SOC_SFR is not set
-CONFIG_ATMEL_CLOCKSOURCE_TCB=y
-# CONFIG_ATMEL_EBI is not set
-CONFIG_ATMEL_SDRAMC=y
-CONFIG_ATMEL_TCB_CLKSRC=y
-# CONFIG_AT_HDMAC is not set
-CONFIG_AT_XDMAC=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=1
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_BLK_DEV_SD=y
-# CONFIG_CACHE_L2X0 is not set
-CONFIG_CAN=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMA=y
-CONFIG_CMA_ALIGNMENT=9
-CONFIG_CMA_AREAS=7
-# CONFIG_CMA_DEBUG is not set
-# CONFIG_CMA_DEBUGFS is not set
-CONFIG_CMA_SIZE_MBYTES=256
-# CONFIG_CMA_SIZE_SEL_MAX is not set
-CONFIG_CMA_SIZE_SEL_MBYTES=y
-# CONFIG_CMA_SIZE_SEL_MIN is not set
-# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
-# CONFIG_CMA_SYSFS is not set
-CONFIG_CMDLINE="console=ttyS0,115200 earlyprintk nocache ignore_loglevel"
-CONFIG_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_AT91=y
-# CONFIG_COMPACTION is not set
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONFIGFS_FS=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_CONTIG_ALLOC=y
-CONFIG_CPUFREQ_DT=y
-CONFIG_CPUFREQ_DT_PLATDEV=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=y
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_SPECTRE=y
-# CONFIG_CPU_SW_DOMAIN_PAN is not set
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRC16=y
-CONFIG_CRC_CCITT=y
-CONFIG_CRC_ITU_T=y
-CONFIG_CRYPTO_CMAC=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_DRBG=y
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_MENU=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_ECC=y
-CONFIG_CRYPTO_ECDH=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_JITTERENTROPY=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_AT91_SAMA7G5_FLEXCOM3=y
-CONFIG_DEBUG_AT91_UART=y
-CONFIG_DEBUG_LL=y
-CONFIG_DEBUG_LL_INCLUDE="debug/at91.S"
-CONFIG_DEBUG_UART_PHYS=0xe1824200
-CONFIG_DEBUG_UART_VIRT=0xe0824200
-# CONFIG_DEBUG_UNCOMPRESS is not set
-CONFIG_DEBUG_USER=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_DMADEVICES=y
-CONFIG_DMATEST=y
-CONFIG_DMA_CMA=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_ENGINE_RAID=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_OPS=y
-CONFIG_DMA_REMAP=y
-CONFIG_DTC=y
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EEPROM_AT24=y
-# CONFIG_EFI_PARTITION is not set
-CONFIG_EXT4_FS=y
-CONFIG_FANOTIFY=y
-CONFIG_FAT_FS=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FORCE_MAX_ZONEORDER=15
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GENERIC_VDSO_32=y
-CONFIG_GLOB=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GRACE_PERIOD=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-# CONFIG_HARDEN_BRANCH_HISTORY is not set
-# CONFIG_HARDEN_BRANCH_PREDICTOR is not set
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAVE_SMP=y
-CONFIG_HW_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_HZ_FIXED=0
-CONFIG_I2C=y
-CONFIG_I2C_AT91=y
-# CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL is not set
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_IIO=y
-CONFIG_IIO_BUFFER=y
-CONFIG_IIO_CONFIGFS=y
-# CONFIG_IIO_HRTIMER_TRIGGER is not set
-CONFIG_IIO_KFIFO_BUF=y
-CONFIG_IIO_SW_TRIGGER=y
-# CONFIG_IIO_TIGHTLOOP_TRIGGER is not set
-CONFIG_IIO_TRIGGER=y
-CONFIG_IIO_TRIGGERED_BUFFER=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-CONFIG_IP_PNP=y
-# CONFIG_IP_PNP_BOOTP is not set
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_IP_PNP_RARP is not set
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD2=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LIBFDT=y
-CONFIG_LOCKD=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOG_BUF_SHIFT=16
-CONFIG_LSM="N"
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MACB=y
-CONFIG_MACB_USE_HWSTAMP=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEDIA_CAMERA_SUPPORT=y
-CONFIG_MEDIA_CONTROLLER=y
-CONFIG_MEDIA_PLATFORM_SUPPORT=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_MEDIA_SUPPORT_FILTER=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MEMORY=y
-CONFIG_MEMORY_ISOLATION=y
-CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
-CONFIG_MFD_AT91_USART=y
-CONFIG_MFD_ATMEL_FLEXCOM=y
-CONFIG_MFD_CORE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MICREL_PHY=y
-CONFIG_MICROCHIP_PIT64B=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-# CONFIG_MMC_ATMELMCI is not set
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_OF_AT91=y
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MODULE_FORCE_LOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NEON=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NFS_FS=y
-CONFIG_NLS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_UTF8=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NVMEM=y
-# CONFIG_NVMEM_MICROCHIP_OTPC is not set
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PCCARD=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_AT91=y
-CONFIG_PINCTRL_AT91PIO4=y
-CONFIG_PM_OPP=y
-CONFIG_POWER_RESET=y
-# CONFIG_POWER_RESET_AT91_POWEROFF is not set
-CONFIG_POWER_RESET_AT91_RESET=y
-CONFIG_POWER_RESET_AT91_SAMA5D2_SHDWC=y
-CONFIG_PPS=y
-# CONFIG_PREVENT_FIRMWARE_BUILD is not set
-CONFIG_PRINTK_TIME=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
-CONFIG_PWM_ATMEL=y
-CONFIG_PWM_SYSFS=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGMAP_SPI=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_MCP16502=y
-CONFIG_ROOT_NFS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_AT91RM9200=y
-CONFIG_RTC_DRV_AT91SAM9=y
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RTC_MC146818_LIB=y
-# CONFIG_RUNTIME_TESTING_MENU is not set
-CONFIG_SAMA5D4_WATCHDOG=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-# CONFIG_SERIAL_8250 is not set
-CONFIG_SERIAL_ATMEL=y
-CONFIG_SERIAL_ATMEL_CONSOLE=y
-CONFIG_SERIAL_ATMEL_PDC=y
-# CONFIG_SERIAL_ATMEL_TTYAT is not set
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SG_POOL=y
-CONFIG_SND=y
-CONFIG_SND_ATMEL_SOC=y
-# CONFIG_SND_ATMEL_SOC_CLASSD is not set
-# CONFIG_SND_ATMEL_SOC_I2S is not set
-# CONFIG_SND_ATMEL_SOC_PDMIC is not set
-# CONFIG_SND_COMPRESS_OFFLOAD is not set
-CONFIG_SND_DMAENGINE_PCM=y
-CONFIG_SND_JACK=y
-CONFIG_SND_JACK_INPUT_DEV=y
-CONFIG_SND_MCHP_SOC_I2S_MCC=y
-CONFIG_SND_MCHP_SOC_SPDIFRX=y
-CONFIG_SND_MCHP_SOC_SPDIFTX=y
-CONFIG_SND_PCM=y
-CONFIG_SND_SIMPLE_CARD=y
-CONFIG_SND_SIMPLE_CARD_UTILS=y
-CONFIG_SND_SOC=y
-CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
-CONFIG_SND_SOC_I2C_AND_SPI=y
-# CONFIG_SND_SOC_MIKROE_PROTO is not set
-CONFIG_SND_SOC_PCM5102A=y
-CONFIG_SND_SOC_SPDIF=y
-CONFIG_SOC_BUS=y
-# CONFIG_SOC_SAMA5D2 is not set
-# CONFIG_SOC_SAMA5D3 is not set
-# CONFIG_SOC_SAMA5D4 is not set
-CONFIG_SOC_SAMA7=y
-CONFIG_SOC_SAMA7G5=y
-CONFIG_SOC_SAM_V7=y
-CONFIG_SOUND=y
-CONFIG_SOUND_OSS_CORE=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-# CONFIG_SPI_AT91_USART is not set
-CONFIG_SPI_ATMEL=y
-# CONFIG_SPI_ATMEL_QUADSPI is not set
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SRCU=y
-CONFIG_STACKTRACE=y
-# CONFIG_STANDALONE is not set
-CONFIG_SUNRPC=y
-# CONFIG_SWAP is not set
-CONFIG_SWPHY=y
-# CONFIG_SWP_EMULATE is not set
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TINY_SRCU=y
-CONFIG_UACCESS_WITH_MEMCPY=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNWINDER_ARM=y
-CONFIG_USE_OF=y
-CONFIG_V4L_PLATFORM_DRIVERS=y
-CONFIG_VFAT_FS=y
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-# CONFIG_VIDEO_ATMEL_XISC is not set
-CONFIG_VIDEO_DEV=y
-CONFIG_VIDEO_V4L2=y
-CONFIG_VIDEO_V4L2_I2C=y
-CONFIG_VIDEO_V4L2_SUBDEV_API=y
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-CONFIG_WATCHDOG_CORE=y
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
--- /dev/null
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_ALLOW_DEV_COREDUMP is not set
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_AT91=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MULTIPLATFORM=y
+CONFIG_ARCH_MULTI_V6_V7=y
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_ARCH_NR_GPIO=0
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARM=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_HAS_GROUP_RELOCS=y
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+# CONFIG_ARM_PATCH_IDIV is not set
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_UNWIND=y
+CONFIG_ARM_VIRT_EXT=y
+# CONFIG_AT91SAM9X_WATCHDOG is not set
+# CONFIG_AT91_ADC is not set
+CONFIG_AT91_SAMA5D2_ADC=y
+CONFIG_AT91_SOC_ID=y
+# CONFIG_AT91_SOC_SFR is not set
+CONFIG_ATMEL_CLOCKSOURCE_TCB=y
+# CONFIG_ATMEL_EBI is not set
+CONFIG_ATMEL_SDRAMC=y
+CONFIG_ATMEL_TCB_CLKSRC=y
+# CONFIG_AT_HDMAC is not set
+CONFIG_AT_XDMAC=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=1
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CACHE_L2X0 is not set
+CONFIG_CAN=y
+CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMA=y
+CONFIG_CMA_ALIGNMENT=9
+CONFIG_CMA_AREAS=7
+# CONFIG_CMA_DEBUG is not set
+# CONFIG_CMA_DEBUGFS is not set
+CONFIG_CMA_SIZE_MBYTES=256
+# CONFIG_CMA_SIZE_SEL_MAX is not set
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+# CONFIG_CMA_SIZE_SEL_MIN is not set
+# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
+# CONFIG_CMA_SYSFS is not set
+CONFIG_CMDLINE="console=ttyS0,115200 earlyprintk nocache ignore_loglevel"
+CONFIG_CMDLINE_FROM_BOOTLOADER=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_AT91=y
+# CONFIG_COMPACTION is not set
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_CONTIG_ALLOC=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPUFREQ_DT_PLATDEV=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_SPECTRE=y
+# CONFIG_CPU_SW_DOMAIN_PAN is not set
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_V7=y
+CONFIG_CRC16=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRYPTO_CMAC=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_DRBG_HMAC=y
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_ECC=y
+CONFIG_CRYPTO_ECDH=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_SHA256=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RNG_DEFAULT=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_AT91_SAMA7G5_FLEXCOM3=y
+CONFIG_DEBUG_AT91_UART=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_LL=y
+CONFIG_DEBUG_LL_INCLUDE="debug/at91.S"
+CONFIG_DEBUG_UART_PHYS=0xe1824200
+CONFIG_DEBUG_UART_VIRT=0xe0824200
+CONFIG_DEBUG_USER=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_DMADEVICES=y
+CONFIG_DMATEST=y
+CONFIG_DMA_CMA=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_ENGINE_RAID=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_OPS=y
+CONFIG_DTC=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EEPROM_AT24=y
+# CONFIG_EFI_PARTITION is not set
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_EXT4_FS=y
+CONFIG_FANOTIFY=y
+CONFIG_FAT_FS=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC10_NO_ARRAY_BOUNDS=y
+CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_VDSO_32=y
+CONFIG_GLOB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GRACE_PERIOD=y
+# CONFIG_HARDEN_BRANCH_HISTORY is not set
+# CONFIG_HARDEN_BRANCH_PREDICTOR is not set
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HAVE_SMP=y
+CONFIG_HW_CONSOLE=y
+CONFIG_HW_RANDOM=y
+CONFIG_HZ_FIXED=0
+CONFIG_I2C=y
+CONFIG_I2C_AT91=y
+# CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL is not set
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_IIO=y
+CONFIG_IIO_BUFFER=y
+CONFIG_IIO_CONFIGFS=y
+# CONFIG_IIO_HRTIMER_TRIGGER is not set
+CONFIG_IIO_KFIFO_BUF=y
+CONFIG_IIO_SW_TRIGGER=y
+# CONFIG_IIO_TIGHTLOOP_TRIGGER is not set
+CONFIG_IIO_TRIGGER=y
+CONFIG_IIO_TRIGGERED_BUFFER=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INPUT=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_BOOTP is not set
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_RARP is not set
+CONFIG_IRQCHIP=y
+CONFIG_IRQSTACKS=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+CONFIG_JBD2=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LIBFDT=y
+CONFIG_LOCKD=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_LSM="N"
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MACB=y
+CONFIG_MACB_USE_HWSTAMP=y
+# CONFIG_MCHP_EIC is not set
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_CONTROLLER=y
+CONFIG_MEDIA_PLATFORM_SUPPORT=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_SUPPORT_FILTER=y
+CONFIG_MEMFD_CREATE=y
+CONFIG_MEMORY=y
+CONFIG_MEMORY_ISOLATION=y
+CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
+CONFIG_MFD_AT91_USART=y
+CONFIG_MFD_ATMEL_FLEXCOM=y
+CONFIG_MFD_CORE=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MICREL_PHY=y
+CONFIG_MICROCHIP_CLOCKSOURCE_PIT64B=y
+CONFIG_MICROCHIP_PIT64B=y
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+# CONFIG_MMC_ATMELMCI is not set
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_OF_AT91=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NEON=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NFS_FS=y
+CONFIG_NLS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+# CONFIG_NVMEM_MICROCHIP_OTPC is not set
+CONFIG_NVMEM_SYSFS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
+CONFIG_PCCARD=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+CONFIG_PHYLINK=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AT91=y
+CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_PM_OPP=y
+CONFIG_POWER_RESET=y
+# CONFIG_POWER_RESET_AT91_POWEROFF is not set
+CONFIG_POWER_RESET_AT91_RESET=y
+CONFIG_POWER_RESET_AT91_SAMA5D2_SHDWC=y
+CONFIG_PPS=y
+CONFIG_PREEMPT_NONE_BUILD=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+CONFIG_PRINTK_TIME=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_PWM=y
+CONFIG_PWM_ATMEL=y
+CONFIG_PWM_SYSFS=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RATIONAL=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGMAP_SPI=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_MCP16502=y
+CONFIG_ROOT_NFS=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_AT91RM9200=y
+CONFIG_RTC_DRV_AT91SAM9=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RTC_MC146818_LIB=y
+# CONFIG_RUNTIME_TESTING_MENU is not set
+CONFIG_SAMA5D4_WATCHDOG=y
+CONFIG_SCSI=y
+CONFIG_SCSI_COMMON=y
+# CONFIG_SERIAL_8250 is not set
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+CONFIG_SERIAL_ATMEL_PDC=y
+# CONFIG_SERIAL_ATMEL_TTYAT is not set
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SG_POOL=y
+CONFIG_SND=y
+CONFIG_SND_ATMEL_SOC=y
+# CONFIG_SND_ATMEL_SOC_CLASSD is not set
+# CONFIG_SND_ATMEL_SOC_I2S is not set
+# CONFIG_SND_ATMEL_SOC_PDMIC is not set
+# CONFIG_SND_COMPRESS_OFFLOAD is not set
+CONFIG_SND_DMAENGINE_PCM=y
+CONFIG_SND_JACK=y
+CONFIG_SND_JACK_INPUT_DEV=y
+CONFIG_SND_MCHP_SOC_I2S_MCC=y
+# CONFIG_SND_MCHP_SOC_PDMC is not set
+CONFIG_SND_MCHP_SOC_SPDIFRX=y
+CONFIG_SND_MCHP_SOC_SPDIFTX=y
+CONFIG_SND_PCM=y
+CONFIG_SND_SIMPLE_CARD=y
+CONFIG_SND_SIMPLE_CARD_UTILS=y
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+# CONFIG_SND_SOC_MIKROE_PROTO is not set
+CONFIG_SND_SOC_PCM5102A=y
+CONFIG_SND_SOC_SPDIF=y
+CONFIG_SOC_BUS=y
+# CONFIG_SOC_LAN966 is not set
+# CONFIG_SOC_SAMA5D2 is not set
+# CONFIG_SOC_SAMA5D3 is not set
+# CONFIG_SOC_SAMA5D4 is not set
+CONFIG_SOC_SAMA7=y
+CONFIG_SOC_SAMA7G5=y
+CONFIG_SOC_SAM_V7=y
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+# CONFIG_SPI_AT91_USART is not set
+CONFIG_SPI_ATMEL=y
+# CONFIG_SPI_ATMEL_QUADSPI is not set
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SRCU=y
+CONFIG_STACKTRACE=y
+# CONFIG_STANDALONE is not set
+CONFIG_SUNRPC=y
+# CONFIG_SWAP is not set
+CONFIG_SWPHY=y
+# CONFIG_SWP_EMULATE is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TINY_SRCU=y
+CONFIG_UACCESS_WITH_MEMCPY=y
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNWINDER_ARM=y
+CONFIG_USE_OF=y
+CONFIG_VFAT_FS=y
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+# CONFIG_VIDEO_ATMEL_XISC is not set
+CONFIG_VIDEO_DEV=y
+# CONFIG_VIDEO_MICROCHIP_CSI2DC is not set
+CONFIG_VIDEO_V4L2_I2C=y
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_WATCHDOG_CORE=y
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
-@@ -2942,12 +2942,19 @@ static void spi_nor_set_mtd_info(struct
+@@ -2964,12 +2964,19 @@ static void spi_nor_set_mtd_info(struct
{
struct mtd_info *mtd = &nor->mtd;
struct device *dev = nor->dev;
--- a/net/ipv4/tcp_offload.c
+++ b/net/ipv4/tcp_offload.c
-@@ -220,7 +220,7 @@ struct sk_buff *tcp_gro_receive(struct l
+@@ -62,7 +62,7 @@ static struct sk_buff *__tcpv4_gso_segme
+ th2 = tcp_hdr(seg->next);
+ iph2 = ip_hdr(seg->next);
- th2 = tcp_hdr(p);
+- if (!(*(const u32 *)&th->source ^ *(const u32 *)&th2->source) &&
++ if (!(net_hdr_word(&th->source) ^ net_hdr_word(&th2->source)) &&
+ iph->daddr == iph2->daddr && iph->saddr == iph2->saddr)
+ return segs;
+
+@@ -254,7 +254,7 @@ struct sk_buff *tcp_gro_lookup(struct li
+ continue;
+ th2 = tcp_hdr(p);
- if (*(u32 *)&th->source ^ *(u32 *)&th2->source) {
+ if (net_hdr_word(&th->source) ^ net_hdr_word(&th2->source)) {
NAPI_GRO_CB(p)->same_flow = 0;
continue;
}
-@@ -238,8 +238,8 @@ found:
+@@ -320,8 +320,8 @@ struct sk_buff *tcp_gro_receive(struct l
~(TCP_FLAG_CWR | TCP_FLAG_FIN | TCP_FLAG_PSH));
flush |= (__force int)(th->ack_seq ^ th2->ack_seq);
for (i = sizeof(*th); i < thlen; i += 4)
SUBTARGETS:=generic
KERNEL_PATCHVER:=6.1
+KERNEL_TESTING_PATCHVER:=6.6
define Target/Description
Build firmware images for Broadcom BCM4908 SoC family routers.
+++ /dev/null
-CONFIG_64BIT=y
-CONFIG_ARCH_BCM4908=y
-CONFIG_ARCH_BCMBCA=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
-CONFIG_ARCH_MMAP_RND_BITS=18
-CONFIG_ARCH_MMAP_RND_BITS_MAX=24
-CONFIG_ARCH_MMAP_RND_BITS_MIN=18
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
-CONFIG_ARCH_PROC_KCORE_TEXT=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_STACKWALK=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WANTS_NO_INSTR=y
-CONFIG_ARM64=y
-CONFIG_ARM64_4K_PAGES=y
-CONFIG_ARM64_CRYPTO=y
-CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
-CONFIG_ARM64_PAGE_SHIFT=12
-CONFIG_ARM64_PA_BITS=48
-CONFIG_ARM64_PA_BITS_48=y
-CONFIG_ARM64_PTR_AUTH=y
-CONFIG_ARM64_PTR_AUTH_KERNEL=y
-CONFIG_ARM64_SVE=y
-CONFIG_ARM64_TAGGED_ADDR_ABI=y
-CONFIG_ARM64_VA_BITS=39
-CONFIG_ARM64_VA_BITS_39=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_GIC_V3=y
-CONFIG_ARM_GIC_V3_ITS=y
-CONFIG_ARM_PSCI_FW=y
-CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
-CONFIG_B53=y
-CONFIG_BCM4908_ENET=y
-CONFIG_BCM7038_WDT=y
-CONFIG_BCM7XXX_PHY=y
-CONFIG_BCM_NET_PHYLIB=y
-CONFIG_BCM_PMB=y
-# CONFIG_BLK_DEV_INITRD is not set
-CONFIG_BLK_PM=y
-CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="earlycon=bcm63xx_uart,0xff800640 console=ttyS0,115200"
-CONFIG_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_COMMON_CLK=y
-# CONFIG_COMPAT_32BIT_TIME is not set
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_RMAP=y
-CONFIG_CRC16=y
-CONFIG_CRYPTO_AES_ARM64=y
-CONFIG_CRYPTO_AES_ARM64_CE=y
-CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
-CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
-CONFIG_CRYPTO_CRYPTD=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_GHASH_ARM64_CE=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_SIMD=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DMA_DIRECT_REMAP=y
-CONFIG_DMA_REMAP=y
-CONFIG_DTC=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FRAME_POINTER=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_CSUM=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_FIND_FIRST_BIT=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_GENERIC_PLATFORM=y
-CONFIG_GRO_CELLS=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HZ_PERIODIC=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_BRCMSTB=y
-CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_LEDS_BCM63138=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MDIO_BCM_UNIMAC=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGRATION=y
-# CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY is not set
-CONFIG_MODULES_USE_ELF_RELA=y
-CONFIG_MTD_BRCM_U_BOOT=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_NAND_BRCMNAND=y
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
-CONFIG_MTD_OF_PARTS_BCM4908=y
-# CONFIG_MTD_OF_PARTS_LINKSYS_NS is not set
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_SPLIT_CFE_BOOTFS=y
-# CONFIG_MTD_SPLIT_SQUASHFS_ROOT is not set
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_NET_DEVLINK=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_BCM_SF2=y
-CONFIG_NET_DSA_TAG_BRCM=y
-CONFIG_NET_DSA_TAG_BRCM_COMMON=y
-CONFIG_NET_DSA_TAG_BRCM_LEGACY=y
-CONFIG_NET_DSA_TAG_BRCM_PREPEND=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NO_IOPORT_MAP=y
-CONFIG_NR_CPUS=4
-CONFIG_NVMEM=y
-CONFIG_NVMEM_SYSFS=y
-CONFIG_NVMEM_U_BOOT_ENV=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_PADATA=y
-CONFIG_PARTITION_PERCPU=y
-CONFIG_PGTABLE_LEVELS=3
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_PHY_BRCM_USB=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_BCM4908=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_PM_GENERIC_DOMAINS=y
-CONFIG_PM_GENERIC_DOMAINS_OF=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_SYSCON=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_RELOCATABLE=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
-CONFIG_RPS=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-# CONFIG_SERIAL_8250 is not set
-CONFIG_SERIAL_BCM63XX=y
-CONFIG_SERIAL_BCM63XX_CONSOLE=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SMP=y
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SPARSEMEM=y
-CONFIG_SPARSEMEM_EXTREME=y
-CONFIG_SPARSEMEM_VMEMMAP=y
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SRCU=y
-CONFIG_SWIOTLB=y
-CONFIG_SWPHY=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UBIFS_FS=y
-CONFIG_UNMAP_KERNEL_AT_EL0=y
-CONFIG_USB_SUPPORT=y
-CONFIG_VMAP_STACK=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZONE_DMA32=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
+++ /dev/null
-From d0ae9c944b9472c5691a482297df7a57d7fd1199 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Thu, 19 Aug 2021 14:11:08 +0200
-Subject: [PATCH] arm64: dts: broadcom: bcm4908: Fix NAND node name
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This matches nand-controller.yaml requirements.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-@@ -295,7 +295,7 @@
- status = "okay";
- };
-
-- nand@1800 {
-+ nand-controller@1800 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
+++ /dev/null
-From 7b0c9ca7f18e8d2e2cf3c342d91f037d436777bf Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Fri, 5 Nov 2021 11:14:12 +0100
-Subject: [PATCH] dt-bindings: arm: bcm: document Netgear RAXE500 binding
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-One more BCM4908 based device.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Acked-by: Rob Herring <robh@kernel.org>
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml
-+++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4908.yaml
-@@ -29,6 +29,7 @@ properties:
- items:
- - enum:
- - asus,gt-ac5300
-+ - netgear,raxe500
- - const: brcm,bcm4908
-
- - description: BCM49408 based boards
+++ /dev/null
-From 72b1c5da796ec5266f2012c36470e226cb4f09c9 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Thu, 30 Dec 2021 12:05:35 +0100
-Subject: [PATCH] arm64: dts: broadcom: bcm4908: add pinctrl binding
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Describe pinmux block with its maps.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- .../boot/dts/broadcom/bcmbca/bcm4908.dtsi | 135 ++++++++++++++++++
- 1 file changed, 135 insertions(+)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-@@ -286,6 +286,141 @@
- gpio-controller;
- };
-
-+ pinctrl@560 {
-+ compatible = "brcm,bcm4908-pinctrl";
-+ reg = <0x560 0x10>;
-+
-+ pins_led_0_a: led_0-a-pins {
-+ function = "led_0";
-+ groups = "led_0_grp_a";
-+ };
-+
-+ pins_led_1_a: led_1-a-pins {
-+ function = "led_1";
-+ groups = "led_1_grp_a";
-+ };
-+
-+ pins_led_2_a: led_2-a-pins {
-+ function = "led_2";
-+ groups = "led_2_grp_a";
-+ };
-+
-+ pins_led_3_a: led_3-a-pins {
-+ function = "led_3";
-+ groups = "led_3_grp_a";
-+ };
-+
-+ pins_led_4_a: led_4-a-pins {
-+ function = "led_4";
-+ groups = "led_4_grp_a";
-+ };
-+
-+ pins_led_5_a: led_5-a-pins {
-+ function = "led_5";
-+ groups = "led_5_grp_a";
-+ };
-+
-+ pins_led_6_a: led_6-a-pins {
-+ function = "led_6";
-+ groups = "led_6_grp_a";
-+ };
-+
-+ pins_led_7_a: led_7-a-pins {
-+ function = "led_7";
-+ groups = "led_7_grp_a";
-+ };
-+
-+ pins_led_8_a: led_8-a-pins {
-+ function = "led_8";
-+ groups = "led_8_grp_a";
-+ };
-+
-+ pins_led_9_a: led_9-a-pins {
-+ function = "led_9";
-+ groups = "led_9_grp_a";
-+ };
-+
-+ pins_led_21_a: led_21-a-pins {
-+ function = "led_21";
-+ groups = "led_21_grp_a";
-+ };
-+
-+ pins_led_22_a: led_22-a-pins {
-+ function = "led_22";
-+ groups = "led_22_grp_a";
-+ };
-+
-+ pins_led_26_a: led_26-a-pins {
-+ function = "led_26";
-+ groups = "led_26_grp_a";
-+ };
-+
-+ pins_led_27_a: led_27-a-pins {
-+ function = "led_27";
-+ groups = "led_27_grp_a";
-+ };
-+
-+ pins_led_28_a: led_28-a-pins {
-+ function = "led_28";
-+ groups = "led_28_grp_a";
-+ };
-+
-+ pins_led_29_a: led_29-a-pins {
-+ function = "led_29";
-+ groups = "led_29_grp_a";
-+ };
-+
-+ pins_led_30_a: led_30-a-pins {
-+ function = "led_30";
-+ groups = "led_30_grp_a";
-+ };
-+
-+ pins_hs_uart: hs_uart-pins {
-+ function = "hs_uart";
-+ groups = "hs_uart_grp";
-+ };
-+
-+ pins_i2c_a: i2c-a-pins {
-+ function = "i2c";
-+ groups = "i2c_grp_a";
-+ };
-+
-+ pins_i2c_b: i2c-b-pins {
-+ function = "i2c";
-+ groups = "i2c_grp_b";
-+ };
-+
-+ pins_i2s: i2s-pins {
-+ function = "i2s";
-+ groups = "i2s_grp";
-+ };
-+
-+ pins_nand_ctrl: nand_ctrl-pins {
-+ function = "nand_ctrl";
-+ groups = "nand_ctrl_grp";
-+ };
-+
-+ pins_nand_data: nand_data-pins {
-+ function = "nand_data";
-+ groups = "nand_data_grp";
-+ };
-+
-+ pins_emmc_ctrl: emmc_ctrl-pins {
-+ function = "emmc_ctrl";
-+ groups = "emmc_ctrl_grp";
-+ };
-+
-+ pins_usb0_pwr: usb0_pwr-pins {
-+ function = "usb0_pwr";
-+ groups = "usb0_pwr_grp";
-+ };
-+
-+ pins_usb1_pwr: usb1_pwr-pins {
-+ function = "usb1_pwr";
-+ groups = "usb1_pwr_grp";
-+ };
-+ };
-+
- uart0: serial@640 {
- compatible = "brcm,bcm6345-uart";
- reg = <0x640 0x18>;
+++ /dev/null
-From 47513f6dd93b5b7d91143219c2c1fb883664ed13 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Wed, 9 Feb 2022 21:14:17 +0100
-Subject: [PATCH] arm64: dts: broadcom: bcm4908: add watchdog block
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-BCM4908 has the same watchdog as BCM63xx devices. Use "brcm,bcm6345-wdt"
-binding which matches the first SoC with that block.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-@@ -275,6 +275,15 @@
- twd: timer-mfd@400 {
- compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon";
- reg = <0x400 0x4c>;
-+ ranges = <0x0 0x400 0x4c>;
-+
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ watchdog@28 {
-+ compatible = "brcm,bcm6345-wdt";
-+ reg = <0x28 0x8>;
-+ };
- };
-
- gpio0: gpio-controller@500 {
+++ /dev/null
-From ba5dfa2fd8d0aed4e4b6f650ba9e8ea7cdd6ead1 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Tue, 15 Feb 2022 07:36:39 +0100
-Subject: [PATCH] arm64: dts: broadcom: bcm4908: add I2C block
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-BCM4908 uses the same I2C hw as BCM63xx / BCM67xx / BCM68xx SoCs.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-@@ -455,6 +455,15 @@
- };
- };
-
-+ i2c@2100 {
-+ compatible = "brcm,brcmper-i2c";
-+ reg = <0x2100 0x58>;
-+ clock-frequency = <97500>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pins_i2c_a>;
-+ status = "disabled";
-+ };
-+
- misc@2600 {
- compatible = "brcm,misc", "simple-mfd";
- reg = <0x2600 0xe4>;
+++ /dev/null
-From 82a58061ada60058ec00113c179380f945914709 Mon Sep 17 00:00:00 2001
-From: William Zhang <william.zhang@broadcom.com>
-Date: Wed, 8 Jun 2022 11:00:59 -0700
-Subject: [PATCH] arm64: dts: Add DTS files for bcmbca SoC BCM63146
-
-Add DTS for ARMv8 based broadband SoC BCM63146. bcm63146.dtsi is the
-SoC description DTS header and bcm963146.dts is a simple DTS file for
-Broadcom BCM963146 Reference board that only enable the UART port.
-
-Signed-off-by: William Zhang <william.zhang@broadcom.com>
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- arch/arm64/boot/dts/broadcom/bcmbca/Makefile | 3 +-
- .../boot/dts/broadcom/bcmbca/bcm63146.dtsi | 110 ++++++++++++++++++
- .../boot/dts/broadcom/bcmbca/bcm963146.dts | 30 +++++
- 3 files changed, 142 insertions(+), 1 deletion(-)
- create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
- create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
-@@ -7,4 +7,5 @@ dtb-$(CONFIG_ARCH_BCMBCA) += \
- bcm4912-asus-gt-ax6000.dtb \
- bcm94912.dtb \
- bcm963158.dtb \
-- bcm96858.dtb
-+ bcm96858.dtb \
-+ bcm963146.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
-@@ -0,0 +1,110 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright 2022 Broadcom Ltd.
-+ */
-+
-+#include <dt-bindings/interrupt-controller/irq.h>
-+#include <dt-bindings/interrupt-controller/arm-gic.h>
-+
-+/ {
-+ compatible = "brcm,bcm63146", "brcm,bcmbca";
-+ #address-cells = <2>;
-+ #size-cells = <2>;
-+
-+ interrupt-parent = <&gic>;
-+
-+ cpus {
-+ #address-cells = <2>;
-+ #size-cells = <0>;
-+
-+ B53_0: cpu@0 {
-+ compatible = "brcm,brahma-b53";
-+ device_type = "cpu";
-+ reg = <0x0 0x0>;
-+ next-level-cache = <&L2_0>;
-+ enable-method = "psci";
-+ };
-+
-+ B53_1: cpu@1 {
-+ compatible = "brcm,brahma-b53";
-+ device_type = "cpu";
-+ reg = <0x0 0x1>;
-+ next-level-cache = <&L2_0>;
-+ enable-method = "psci";
-+ };
-+
-+ L2_0: l2-cache0 {
-+ compatible = "cache";
-+ };
-+ };
-+
-+ timer {
-+ compatible = "arm,armv8-timer";
-+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
-+ };
-+
-+ pmu: pmu {
-+ compatible = "arm,cortex-a53-pmu";
-+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-affinity = <&B53_0>, <&B53_1>;
-+ };
-+
-+ clocks: clocks {
-+ periph_clk: periph-clk {
-+ compatible = "fixed-clock";
-+ #clock-cells = <0>;
-+ clock-frequency = <200000000>;
-+ };
-+ uart_clk: uart-clk {
-+ compatible = "fixed-factor-clock";
-+ #clock-cells = <0>;
-+ clocks = <&periph_clk>;
-+ clock-div = <4>;
-+ clock-mult = <1>;
-+ };
-+ };
-+
-+ psci {
-+ compatible = "arm,psci-0.2";
-+ method = "smc";
-+ };
-+
-+ axi@81000000 {
-+ compatible = "simple-bus";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ ranges = <0x0 0x0 0x81000000 0x8000>;
-+
-+ gic: interrupt-controller@1000 {
-+ compatible = "arm,gic-400";
-+ #interrupt-cells = <3>;
-+ interrupt-controller;
-+ reg = <0x1000 0x1000>,
-+ <0x2000 0x2000>,
-+ <0x4000 0x2000>,
-+ <0x6000 0x2000>;
-+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
-+ IRQ_TYPE_LEVEL_HIGH)>;
-+ };
-+ };
-+
-+ bus@ff800000 {
-+ compatible = "simple-bus";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ ranges = <0x0 0x0 0xff800000 0x800000>;
-+
-+ uart0: serial@12000 {
-+ compatible = "arm,pl011", "arm,primecell";
-+ reg = <0x12000 0x1000>;
-+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&uart_clk>, <&uart_clk>;
-+ clock-names = "uartclk", "apb_pclk";
-+ status = "disabled";
-+ };
-+ };
-+};
---- /dev/null
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts
-@@ -0,0 +1,30 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright 2022 Broadcom Ltd.
-+ */
-+
-+/dts-v1/;
-+
-+#include "bcm63146.dtsi"
-+
-+/ {
-+ model = "Broadcom BCM963146 Reference Board";
-+ compatible = "brcm,bcm963146", "brcm,bcm63146", "brcm,bcmbca";
-+
-+ aliases {
-+ serial0 = &uart0;
-+ };
-+
-+ chosen {
-+ stdout-path = "serial0:115200n8";
-+ };
-+
-+ memory@0 {
-+ device_type = "memory";
-+ reg = <0x0 0x0 0x0 0x08000000>;
-+ };
-+};
-+
-+&uart0 {
-+ status = "okay";
-+};
+++ /dev/null
-From 64eca7ad058cff861b48cdead8dee40dfc284e9e Mon Sep 17 00:00:00 2001
-From: William Zhang <william.zhang@broadcom.com>
-Date: Wed, 8 Jun 2022 11:04:36 -0700
-Subject: [PATCH] arm64: dts: Add DTS files for bcmbca SoC BCM6856
-
-Add DTS for ARMv8 based broadband SoC BCM6856. bcm6856.dtsi is the
-SoC description DTS header and bcm96856.dts is a simple DTS file for
-Broadcom BCM96956 Reference board that only enable the UART port.
-
-Signed-off-by: William Zhang <william.zhang@broadcom.com>
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- arch/arm64/boot/dts/broadcom/bcmbca/Makefile | 3 +-
- .../boot/dts/broadcom/bcmbca/bcm6856.dtsi | 103 ++++++++++++++++++
- .../boot/dts/broadcom/bcmbca/bcm96856.dts | 30 +++++
- 3 files changed, 135 insertions(+), 1 deletion(-)
- create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
- create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
-@@ -8,4 +8,5 @@ dtb-$(CONFIG_ARCH_BCMBCA) += \
- bcm94912.dtb \
- bcm963158.dtb \
- bcm96858.dtb \
-- bcm963146.dtb
-+ bcm963146.dtb \
-+ bcm96856.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
-@@ -0,0 +1,103 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright 2022 Broadcom Ltd.
-+ */
-+
-+#include <dt-bindings/interrupt-controller/irq.h>
-+#include <dt-bindings/interrupt-controller/arm-gic.h>
-+
-+/ {
-+ compatible = "brcm,bcm6856", "brcm,bcmbca";
-+ #address-cells = <2>;
-+ #size-cells = <2>;
-+
-+ interrupt-parent = <&gic>;
-+
-+ cpus {
-+ #address-cells = <2>;
-+ #size-cells = <0>;
-+
-+ B53_0: cpu@0 {
-+ compatible = "brcm,brahma-b53";
-+ device_type = "cpu";
-+ reg = <0x0 0x0>;
-+ next-level-cache = <&L2_0>;
-+ enable-method = "psci";
-+ };
-+
-+ B53_1: cpu@1 {
-+ compatible = "brcm,brahma-b53";
-+ device_type = "cpu";
-+ reg = <0x0 0x1>;
-+ next-level-cache = <&L2_0>;
-+ enable-method = "psci";
-+ };
-+
-+ L2_0: l2-cache0 {
-+ compatible = "cache";
-+ };
-+ };
-+
-+ timer {
-+ compatible = "arm,armv8-timer";
-+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
-+ };
-+
-+ pmu: pmu {
-+ compatible = "arm,cortex-a53-pmu";
-+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-affinity = <&B53_0>, <&B53_1>;
-+ };
-+
-+ clocks: clocks {
-+ periph_clk:periph-clk {
-+ compatible = "fixed-clock";
-+ #clock-cells = <0>;
-+ clock-frequency = <200000000>;
-+ };
-+ };
-+
-+ psci {
-+ compatible = "arm,psci-0.2";
-+ method = "smc";
-+ };
-+
-+ axi@81000000 {
-+ compatible = "simple-bus";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ ranges = <0x0 0x0 0x81000000 0x8000>;
-+
-+ gic: interrupt-controller@1000 {
-+ compatible = "arm,gic-400";
-+ #interrupt-cells = <3>;
-+ interrupt-controller;
-+ reg = <0x1000 0x1000>, /* GICD */
-+ <0x2000 0x2000>, /* GICC */
-+ <0x4000 0x2000>, /* GICH */
-+ <0x6000 0x2000>; /* GICV */
-+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
-+ IRQ_TYPE_LEVEL_HIGH)>;
-+ };
-+ };
-+
-+ bus@ff800000 {
-+ compatible = "simple-bus";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ ranges = <0x0 0x0 0xff800000 0x800000>;
-+
-+ uart0: serial@640 {
-+ compatible = "brcm,bcm6345-uart";
-+ reg = <0x640 0x18>;
-+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&periph_clk>;
-+ clock-names = "refclk";
-+ status = "disabled";
-+ };
-+ };
-+};
---- /dev/null
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts
-@@ -0,0 +1,30 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright 2022 Broadcom Ltd.
-+ */
-+
-+/dts-v1/;
-+
-+#include "bcm6856.dtsi"
-+
-+/ {
-+ model = "Broadcom BCM96856 Reference Board";
-+ compatible = "brcm,bcm96856", "brcm,bcm6856", "brcm,bcmbca";
-+
-+ aliases {
-+ serial0 = &uart0;
-+ };
-+
-+ chosen {
-+ stdout-path = "serial0:115200n8";
-+ };
-+
-+ memory@0 {
-+ device_type = "memory";
-+ reg = <0x0 0x0 0x0 0x08000000>;
-+ };
-+};
-+
-+&uart0 {
-+ status = "okay";
-+};
+++ /dev/null
-From eab6bb0994b806525fc5e362e8b865f61c4a9e20 Mon Sep 17 00:00:00 2001
-From: William Zhang <william.zhang@broadcom.com>
-Date: Thu, 9 Jun 2022 17:15:33 -0700
-Subject: [PATCH] arm64: dts: Add DTS files for bcmbca SoC BCM6813
-
-Add DTS for ARMv8 based broadband SoC BCM6813. bcm6813.dtsi is the
-SoC description DTS header and bcm96813.dts is a simple DTS file for
-Broadcom BCM96813 Reference board that only enable the UART port.
-
-Signed-off-by: William Zhang <william.zhang@broadcom.com>
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- arch/arm64/boot/dts/broadcom/bcmbca/Makefile | 3 +-
- .../boot/dts/broadcom/bcmbca/bcm6813.dtsi | 128 ++++++++++++++++++
- .../boot/dts/broadcom/bcmbca/bcm96813.dts | 30 ++++
- 3 files changed, 160 insertions(+), 1 deletion(-)
- create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
- create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
-@@ -9,4 +9,5 @@ dtb-$(CONFIG_ARCH_BCMBCA) += \
- bcm963158.dtb \
- bcm96858.dtb \
- bcm963146.dtb \
-- bcm96856.dtb
-+ bcm96856.dtb \
-+ bcm96813.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
-@@ -0,0 +1,128 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright 2022 Broadcom Ltd.
-+ */
-+
-+#include <dt-bindings/interrupt-controller/irq.h>
-+#include <dt-bindings/interrupt-controller/arm-gic.h>
-+
-+/ {
-+ compatible = "brcm,bcm6813", "brcm,bcmbca";
-+ #address-cells = <2>;
-+ #size-cells = <2>;
-+
-+ interrupt-parent = <&gic>;
-+
-+ cpus {
-+ #address-cells = <2>;
-+ #size-cells = <0>;
-+
-+ B53_0: cpu@0 {
-+ compatible = "brcm,brahma-b53";
-+ device_type = "cpu";
-+ reg = <0x0 0x0>;
-+ next-level-cache = <&L2_0>;
-+ enable-method = "psci";
-+ };
-+
-+ B53_1: cpu@1 {
-+ compatible = "brcm,brahma-b53";
-+ device_type = "cpu";
-+ reg = <0x0 0x1>;
-+ next-level-cache = <&L2_0>;
-+ enable-method = "psci";
-+ };
-+
-+ B53_2: cpu@2 {
-+ compatible = "brcm,brahma-b53";
-+ device_type = "cpu";
-+ reg = <0x0 0x2>;
-+ next-level-cache = <&L2_0>;
-+ enable-method = "psci";
-+ };
-+
-+ B53_3: cpu@3 {
-+ compatible = "brcm,brahma-b53";
-+ device_type = "cpu";
-+ reg = <0x0 0x3>;
-+ next-level-cache = <&L2_0>;
-+ enable-method = "psci";
-+ };
-+
-+ L2_0: l2-cache0 {
-+ compatible = "cache";
-+ };
-+ };
-+
-+ timer {
-+ compatible = "arm,armv8-timer";
-+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
-+ };
-+
-+ pmu: pmu {
-+ compatible = "arm,cortex-a53-pmu";
-+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
-+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-affinity = <&B53_0>, <&B53_1>,
-+ <&B53_2>, <&B53_3>;
-+ };
-+
-+ clocks: clocks {
-+ periph_clk: periph-clk {
-+ compatible = "fixed-clock";
-+ #clock-cells = <0>;
-+ clock-frequency = <200000000>;
-+ };
-+ uart_clk: uart-clk {
-+ compatible = "fixed-factor-clock";
-+ #clock-cells = <0>;
-+ clocks = <&periph_clk>;
-+ clock-div = <4>;
-+ clock-mult = <1>;
-+ };
-+ };
-+
-+ psci {
-+ compatible = "arm,psci-0.2";
-+ method = "smc";
-+ };
-+
-+ axi@81000000 {
-+ compatible = "simple-bus";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ ranges = <0x0 0x0 0x81000000 0x8000>;
-+
-+ gic: interrupt-controller@1000 {
-+ compatible = "arm,gic-400";
-+ #interrupt-cells = <3>;
-+ interrupt-controller;
-+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
-+ reg = <0x1000 0x1000>,
-+ <0x2000 0x2000>,
-+ <0x4000 0x2000>,
-+ <0x6000 0x2000>;
-+ };
-+ };
-+
-+ bus@ff800000 {
-+ compatible = "simple-bus";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ ranges = <0x0 0x0 0xff800000 0x800000>;
-+
-+ uart0: serial@12000 {
-+ compatible = "arm,pl011", "arm,primecell";
-+ reg = <0x12000 0x1000>;
-+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&uart_clk>, <&uart_clk>;
-+ clock-names = "uartclk", "apb_pclk";
-+ status = "disabled";
-+ };
-+ };
-+};
---- /dev/null
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts
-@@ -0,0 +1,30 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright 2022 Broadcom Ltd.
-+ */
-+
-+/dts-v1/;
-+
-+#include "bcm6813.dtsi"
-+
-+/ {
-+ model = "Broadcom BCM96813 Reference Board";
-+ compatible = "brcm,bcm96813", "brcm,bcm6813", "brcm,bcmbca";
-+
-+ aliases {
-+ serial0 = &uart0;
-+ };
-+
-+ chosen {
-+ stdout-path = "serial0:115200n8";
-+ };
-+
-+ memory@0 {
-+ device_type = "memory";
-+ reg = <0x0 0x0 0x0 0x08000000>;
-+ };
-+};
-+
-+&uart0 {
-+ status = "okay";
-+};
+++ /dev/null
-From ea559c81b61603d4044df6f826f10a832c42c98c Mon Sep 17 00:00:00 2001
-From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Date: Wed, 15 Jun 2022 17:52:59 -0700
-Subject: [PATCH] arm64: dts: broadcom: align gpio-key node names with dtschema
-
-The node names should be generic and DT schema expects certain pattern
-(e.g. with key/button/switch).
-
-Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Link: https://lore.kernel.org/r/20220616005333.18491-6-krzysztof.kozlowski@linaro.org
----
- .../broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts | 8 ++++----
- .../boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts | 8 ++++----
- 2 files changed, 8 insertions(+), 8 deletions(-)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts
-@@ -83,25 +83,25 @@
- compatible = "gpio-keys-polled";
- poll-interval = <100>;
-
-- brightness {
-+ key-brightness {
- label = "LEDs";
- linux,code = <KEY_BRIGHTNESS_ZERO>;
- gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
- };
-
-- wps {
-+ key-wps {
- label = "WPS";
- linux,code = <KEY_WPS_BUTTON>;
- gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
- };
-
-- wifi {
-+ key-wifi {
- label = "WiFi";
- linux,code = <KEY_RFKILL>;
- gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
- };
-
-- restart {
-+ key-restart {
- label = "Reset";
- linux,code = <KEY_RESTART>;
- gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts
-@@ -18,25 +18,25 @@
- compatible = "gpio-keys-polled";
- poll-interval = <100>;
-
-- wifi {
-+ key-wifi {
- label = "WiFi";
- linux,code = <KEY_RFKILL>;
- gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
- };
-
-- wps {
-+ key-wps {
- label = "WPS";
- linux,code = <KEY_WPS_BUTTON>;
- gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
- };
-
-- restart {
-+ key-restart {
- label = "Reset";
- linux,code = <KEY_RESTART>;
- gpios = <&gpio0 30 GPIO_ACTIVE_LOW>;
- };
-
-- brightness {
-+ key-brightness {
- label = "LEDs";
- linux,code = <KEY_BRIGHTNESS_ZERO>;
- gpios = <&gpio0 31 GPIO_ACTIVE_LOW>;
+++ /dev/null
-From b4a544e415e9be33b37d9bfa9d9f9f4d13f553d6 Mon Sep 17 00:00:00 2001
-From: William Zhang <william.zhang@broadcom.com>
-Date: Fri, 8 Jul 2022 11:25:06 -0700
-Subject: [PATCH] arm64: dts: broadcom: bcm4908: Fix timer node for BCM4906 SoC
-
-The cpu mask value in interrupt property inherits from bcm4908.dtsi
-which sets to four cpus. Correct the value to two cpus for dual core
-BCM4906 SoC.
-
-Fixes: c8b404fb05dc ("arm64: dts: broadcom: bcm4908: add BCM4906 Netgear R8000P DTS files")
-Signed-off-by: William Zhang <william.zhang@broadcom.com>
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- arch/arm64/boot/dts/broadcom/bcmbca/bcm4906.dtsi | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906.dtsi
-@@ -17,6 +17,14 @@
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
- };
-
-+ timer {
-+ compatible = "arm,armv8-timer";
-+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
-+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
-+ };
-+
- pmu {
- compatible = "arm,cortex-a53-pmu";
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+++ /dev/null
-From fdcd652ce2b6b819f5c4dc3cead5215c84ee6933 Mon Sep 17 00:00:00 2001
-From: William Zhang <william.zhang@broadcom.com>
-Date: Wed, 1 Jun 2022 15:56:50 -0700
-Subject: [PATCH] arm64: bcmbca: add arch bcmbca machine entry
-
-Add ARCH_BCMBCA config for Broadcom Broadband SoC chipsets
-
-Signed-off-by: William Zhang <william.zhang@broadcom.com>
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- arch/arm64/Kconfig.platforms | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
---- a/arch/arm64/Kconfig.platforms
-+++ b/arch/arm64/Kconfig.platforms
-@@ -65,6 +65,15 @@ config ARCH_BCM_IPROC
- help
- This enables support for Broadcom iProc based SoCs
-
-+config ARCH_BCMBCA
-+ bool "Broadcom Broadband SoC"
-+ help
-+ Say Y if you intend to run the kernel on a Broadcom Broadband ARM-based
-+ BCA chipset.
-+
-+ This enables support for Broadcom BCA ARM-based broadband chipsets,
-+ including the DSL, PON and Wireless family of chips.
-+
- config ARCH_BERLIN
- bool "Marvell Berlin SoC Family"
- select DW_APB_ICTL
+++ /dev/null
-From 456b6dd1baadd2da10e28ffd1717b06d1fa17a97 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Mon, 18 Jul 2022 15:20:58 +0200
-Subject: [PATCH] arm64: dts: broadcom: bcm4908: add remaining LED pins
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Include all 32 pins.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Link: https://lore.kernel.org/r/20220718132100.13277-1-zajec5@gmail.com
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- .../boot/dts/broadcom/bcmbca/bcm4908.dtsi | 75 +++++++++++++++++++
- 1 file changed, 75 insertions(+)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-@@ -349,6 +349,61 @@
- groups = "led_9_grp_a";
- };
-
-+ pins_led_10_a: led_10-a-pins {
-+ function = "led_10";
-+ groups = "led_10_grp_a";
-+ };
-+
-+ pins_led_11_a: led_11-a-pins {
-+ function = "led_11";
-+ groups = "led_11_grp_a";
-+ };
-+
-+ pins_led_12_a: led_12-a-pins {
-+ function = "led_12";
-+ groups = "led_12_grp_a";
-+ };
-+
-+ pins_led_13_a: led_13-a-pins {
-+ function = "led_13";
-+ groups = "led_13_grp_a";
-+ };
-+
-+ pins_led_14_a: led_14-a-pins {
-+ function = "led_14";
-+ groups = "led_14_grp_a";
-+ };
-+
-+ pins_led_15_a: led_15-a-pins {
-+ function = "led_15";
-+ groups = "led_15_grp_a";
-+ };
-+
-+ pins_led_16_a: led_16-a-pins {
-+ function = "led_16";
-+ groups = "led_16_grp_a";
-+ };
-+
-+ pins_led_17_a: led_17-a-pins {
-+ function = "led_17";
-+ groups = "led_17_grp_a";
-+ };
-+
-+ pins_led_18_a: led_18-a-pins {
-+ function = "led_18";
-+ groups = "led_18_grp_a";
-+ };
-+
-+ pins_led_19_a: led_19-a-pins {
-+ function = "led_19";
-+ groups = "led_19_grp_a";
-+ };
-+
-+ pins_led_20_a: led_20-a-pins {
-+ function = "led_20";
-+ groups = "led_20_grp_a";
-+ };
-+
- pins_led_21_a: led_21-a-pins {
- function = "led_21";
- groups = "led_21_grp_a";
-@@ -359,6 +414,21 @@
- groups = "led_22_grp_a";
- };
-
-+ pins_led_23_a: led_23-a-pins {
-+ function = "led_23";
-+ groups = "led_23_grp_a";
-+ };
-+
-+ pins_led_24_a: led_24-a-pins {
-+ function = "led_24";
-+ groups = "led_24_grp_a";
-+ };
-+
-+ pins_led_25_a: led_25-a-pins {
-+ function = "led_25";
-+ groups = "led_25_grp_a";
-+ };
-+
- pins_led_26_a: led_26-a-pins {
- function = "led_26";
- groups = "led_26_grp_a";
-@@ -384,6 +454,11 @@
- groups = "led_30_grp_a";
- };
-
-+ pins_led_31_a: led_31-a-pins {
-+ function = "led_31";
-+ groups = "led_31_grp_a";
-+ };
-+
- pins_hs_uart: hs_uart-pins {
- function = "hs_uart";
- groups = "hs_uart_grp";
+++ /dev/null
-From 7de56b1dc1149c702d4cc1e89ccc251bfb2bc246 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Mon, 18 Jul 2022 15:20:59 +0200
-Subject: [PATCH] arm64: dts: broadcom: bcm4908: add LEDs controller block
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-BCM4908 includes LEDs controller that supports multiple brightness
-levels & hardware blinking.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Link: https://lore.kernel.org/r/20220718132100.13277-2-zajec5@gmail.com
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-@@ -514,6 +514,14 @@
- status = "okay";
- };
-
-+ leds: leds@800 {
-+ compatible = "brcm,bcm4908-leds", "brcm,bcm63138-leds";
-+ reg = <0x800 0xdc>;
-+
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
- nand-controller@1800 {
- #address-cells = <1>;
- #size-cells = <0>;
+++ /dev/null
-From 3bcae3396e986b4ab97a69e8de517e32f9691a4b Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Mon, 18 Jul 2022 15:21:00 +0200
-Subject: [PATCH] arm64: dts: broadcom: bcm4908: add Asus GT-AC5300 LEDs
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-There are 5 software-controllable LEDs on PCB.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Link: https://lore.kernel.org/r/20220718132100.13277-3-zajec5@gmail.com
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- .../bcmbca/bcm4908-asus-gt-ac5300.dts | 48 +++++++++++++++++++
- 1 file changed, 48 insertions(+)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts
-@@ -2,6 +2,7 @@
-
- #include <dt-bindings/gpio/gpio.h>
- #include <dt-bindings/input/input.h>
-+#include <dt-bindings/leds/common.h>
-
- #include "bcm4908.dtsi"
-
-@@ -118,6 +119,53 @@
- };
- };
-
-+&leds {
-+ led-power@11 {
-+ reg = <0x11>;
-+ function = LED_FUNCTION_POWER;
-+ color = <LED_COLOR_ID_WHITE>;
-+ default-state = "on";
-+ active-low;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pins_led_17_a>;
-+ };
-+
-+ led-wan-red@12 {
-+ reg = <0x12>;
-+ function = LED_FUNCTION_WAN;
-+ color = <LED_COLOR_ID_RED>;
-+ active-low;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pins_led_18_a>;
-+ };
-+
-+ led-wps@14 {
-+ reg = <0x14>;
-+ function = LED_FUNCTION_WPS;
-+ color = <LED_COLOR_ID_WHITE>;
-+ active-low;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pins_led_20_a>;
-+ };
-+
-+ led-wan-white@15 {
-+ reg = <0x15>;
-+ function = LED_FUNCTION_WAN;
-+ color = <LED_COLOR_ID_WHITE>;
-+ active-low;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pins_led_21_a>;
-+ };
-+
-+ led-lan@19 {
-+ reg = <0x19>;
-+ function = LED_FUNCTION_LAN;
-+ color = <LED_COLOR_ID_WHITE>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pins_led_25_a>;
-+ };
-+};
-+
- &nandcs {
- nand-ecc-strength = <4>;
- nand-ecc-step-size = <512>;
+++ /dev/null
-From 4fdcbde682291fba2c3f45a41decd656d92a314f Mon Sep 17 00:00:00 2001
-From: William Zhang <william.zhang@broadcom.com>
-Date: Wed, 3 Aug 2022 10:54:49 -0700
-Subject: [PATCH] arm64: dts: bcmbca: update BCM4908 board dts files
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Append "brcm,bcmbca" to compatible strings based on the new bcmbca
-binding rule for BCM4908 family based boards.
-
-Signed-off-by: William Zhang <william.zhang@broadcom.com>
-Acked-by: Rafał Miłecki <rafal@milecki.pl>
-Link: https://lore.kernel.org/r/20220803175455.47638-4-william.zhang@broadcom.com
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts | 2 +-
- .../dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts | 2 +-
- arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts | 2 +-
- .../arm64/boot/dts/broadcom/bcmbca/bcm4908-netgear-raxe500.dts | 2 +-
- 4 files changed, 4 insertions(+), 4 deletions(-)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts
-@@ -7,7 +7,7 @@
- #include "bcm4906.dtsi"
-
- / {
-- compatible = "netgear,r8000p", "brcm,bcm4906", "brcm,bcm4908";
-+ compatible = "netgear,r8000p", "brcm,bcm4906", "brcm,bcm4908", "brcm,bcmbca";
- model = "Netgear R8000P";
-
- memory@0 {
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts
-@@ -7,7 +7,7 @@
- #include "bcm4906.dtsi"
-
- / {
-- compatible = "tplink,archer-c2300-v1", "brcm,bcm4906", "brcm,bcm4908";
-+ compatible = "tplink,archer-c2300-v1", "brcm,bcm4906", "brcm,bcm4908", "brcm,bcmbca";
- model = "TP-Link Archer C2300 V1";
-
- memory@0 {
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts
-@@ -7,7 +7,7 @@
- #include "bcm4908.dtsi"
-
- / {
-- compatible = "asus,gt-ac5300", "brcm,bcm4908";
-+ compatible = "asus,gt-ac5300", "brcm,bcm4908", "brcm,bcmbca";
- model = "Asus GT-AC5300";
-
- memory@0 {
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-netgear-raxe500.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-netgear-raxe500.dts
-@@ -3,7 +3,7 @@
- #include "bcm4908.dtsi"
-
- / {
-- compatible = "netgear,raxe500", "brcm,bcm4908";
-+ compatible = "netgear,raxe500", "brcm,bcm4908", "brcm,bcmbca";
- model = "Netgear RAXE500";
-
- memory@0 {
+++ /dev/null
-From 72e0bdb6d7edb1785d58f2e8e7c80e1d2f93a319 Mon Sep 17 00:00:00 2001
-From: William Zhang <william.zhang@broadcom.com>
-Date: Wed, 3 Aug 2022 10:54:51 -0700
-Subject: [PATCH] arm64: dts: Add BCM4908 generic board dts
-
-Add generic bare bone bcm94908.dts file to support any 4908 based
-design. It supports cpu subsystem, memory and an uart console. This can
-be useful for board bring-up and cpu subsystem and memory related kernel
-test as well.
-
-Signed-off-by: William Zhang <william.zhang@broadcom.com>
-Link: https://lore.kernel.org/r/20220803175455.47638-6-william.zhang@broadcom.com
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- arch/arm64/boot/dts/broadcom/bcmbca/Makefile | 1 +
- .../boot/dts/broadcom/bcmbca/bcm94908.dts | 30 +++++++++++++++++++
- 2 files changed, 31 insertions(+)
- create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
-@@ -4,6 +4,7 @@ dtb-$(CONFIG_ARCH_BCMBCA) += \
- bcm4906-tplink-archer-c2300-v1.dtb \
- bcm4908-asus-gt-ac5300.dtb \
- bcm4908-netgear-raxe500.dtb \
-+ bcm94908.dtb \
- bcm4912-asus-gt-ax6000.dtb \
- bcm94912.dtb \
- bcm963158.dtb \
---- /dev/null
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts
-@@ -0,0 +1,30 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright 2022 Broadcom Ltd.
-+ */
-+
-+/dts-v1/;
-+
-+#include "bcm4908.dtsi"
-+
-+/ {
-+ model = "Broadcom BCM94908 Reference Board";
-+ compatible = "brcm,bcm94908", "brcm,bcm4908", "brcm,bcmbca";
-+
-+ aliases {
-+ serial0 = &uart0;
-+ };
-+
-+ chosen {
-+ stdout-path = "serial0:115200n8";
-+ };
-+
-+ memory@0 {
-+ device_type = "memory";
-+ reg = <0x0 0x0 0x0 0x08000000>;
-+ };
-+};
-+
-+&uart0 {
-+ status = "okay";
-+};
+++ /dev/null
-From 68064196cffea33f090bd2e8d81cd5e20107ecf1 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Thu, 3 Nov 2022 11:53:16 +0100
-Subject: [PATCH] arm64: dts: broadcom: bcmbca: bcm4908: add TWD block timer
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-BCM4908 TWD contains block with 4 timers. Add binding for it.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Link: https://lore.kernel.org/r/20221103105316.21294-1-zajec5@gmail.com
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi | 5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-@@ -280,6 +280,11 @@
- #address-cells = <1>;
- #size-cells = <1>;
-
-+ timer@0 {
-+ compatible = "brcm,bcm63138-timer";
-+ reg = <0x0 0x28>;
-+ };
-+
- watchdog@28 {
- compatible = "brcm,bcm6345-wdt";
- reg = <0x28 0x8>;
+++ /dev/null
-From 4f9fb09175e87a233787a2dee1e5dabb14deb022 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Thu, 3 Nov 2022 12:00:15 +0100
-Subject: [PATCH] arm64: dts: broadcom: bcmbca: bcm6858: add TWD block
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-BCM6858 contains TWD block with timers, watchdog, and reset subblocks.
-Describe it.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Link: https://lore.kernel.org/r/20221103110015.21761-1-zajec5@gmail.com
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- .../boot/dts/broadcom/bcmbca/bcm6858.dtsi | 19 +++++++++++++++++++
- 1 file changed, 19 insertions(+)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
-@@ -109,6 +109,25 @@
- #size-cells = <1>;
- ranges = <0x0 0x0 0xff800000 0x62000>;
-
-+ twd: timer-mfd@400 {
-+ compatible = "brcm,bcm4908-twd", "simple-mfd", "syscon";
-+ reg = <0x400 0x4c>;
-+ ranges = <0x0 0x400 0x4c>;
-+
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ timer@0 {
-+ compatible = "brcm,bcm63138-timer";
-+ reg = <0x0 0x28>;
-+ };
-+
-+ watchdog@28 {
-+ compatible = "brcm,bcm6345-wdt";
-+ reg = <0x28 0x8>;
-+ };
-+ };
-+
- uart0: serial@640 {
- compatible = "brcm,bcm6345-uart";
- reg = <0x640 0x18>;
+++ /dev/null
-From e567e58d6819adc002c57b81e16b88da24d3b4aa Mon Sep 17 00:00:00 2001
-From: Pierre Gondois <pierre.gondois@arm.com>
-Date: Tue, 22 Nov 2022 17:32:07 +0100
-Subject: [PATCH] arm64: dts: Update cache properties for broadcom
-
-The DeviceTree Specification v0.3 specifies that the cache node
-'compatible' and 'cache-level' properties are 'required'. Cf.
-s3.8 Multi-level and Shared Cache Nodes
-The 'cache-unified' property should be present if one of the
-properties for unified cache is present ('cache-size', ...).
-
-Update the Device Trees accordingly.
-
-Acked-by: William Zhang <william.zhang@broadcom.com>
-Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
-Link: https://lore.kernel.org/r/20221122163208.3810985-3-pierre.gondois@arm.com
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi | 1 +
- arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi | 1 +
- arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi | 1 +
- arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi | 1 +
- arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi | 1 +
- arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi | 1 +
- arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi | 1 +
- arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi | 1 +
- arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi | 4 ++++
- 9 files changed, 12 insertions(+)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-@@ -63,6 +63,7 @@
-
- l2: l2-cache0 {
- compatible = "cache";
-+ cache-level = <2>;
- };
- };
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
-@@ -51,6 +51,7 @@
-
- L2_0: l2-cache0 {
- compatible = "cache";
-+ cache-level = <2>;
- };
- };
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
-@@ -35,6 +35,7 @@
-
- L2_0: l2-cache0 {
- compatible = "cache";
-+ cache-level = <2>;
- };
- };
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
-@@ -51,6 +51,7 @@
-
- L2_0: l2-cache0 {
- compatible = "cache";
-+ cache-level = <2>;
- };
- };
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
-@@ -51,6 +51,7 @@
-
- L2_0: l2-cache0 {
- compatible = "cache";
-+ cache-level = <2>;
- };
- };
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
-@@ -35,6 +35,7 @@
-
- L2_0: l2-cache0 {
- compatible = "cache";
-+ cache-level = <2>;
- };
- };
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
-@@ -50,6 +50,7 @@
- };
- L2_0: l2-cache0 {
- compatible = "cache";
-+ cache-level = <2>;
- };
- };
-
---- a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
-@@ -79,6 +79,7 @@
-
- CLUSTER0_L2: l2-cache@0 {
- compatible = "cache";
-+ cache-level = <2>;
- };
- };
-
---- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
-@@ -108,18 +108,22 @@
-
- CLUSTER0_L2: l2-cache@0 {
- compatible = "cache";
-+ cache-level = <2>;
- };
-
- CLUSTER1_L2: l2-cache@100 {
- compatible = "cache";
-+ cache-level = <2>;
- };
-
- CLUSTER2_L2: l2-cache@200 {
- compatible = "cache";
-+ cache-level = <2>;
- };
-
- CLUSTER3_L2: l2-cache@300 {
- compatible = "cache";
-+ cache-level = <2>;
- };
- };
-
+++ /dev/null
-From f5d83b714e304d5f3229da434af2eeea033c4f5d Mon Sep 17 00:00:00 2001
-From: William Zhang <william.zhang@broadcom.com>
-Date: Mon, 6 Feb 2023 22:58:15 -0800
-Subject: [PATCH] arm64: dts: broadcom: bcmbca: Add spi controller node
-
-Add support for HSSPI controller in ARMv8 chip dts files.
-
-Signed-off-by: William Zhang <william.zhang@broadcom.com>
-Link: https://lore.kernel.org/r/20230207065826.285013-5-william.zhang@broadcom.com
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- .../boot/dts/broadcom/bcmbca/bcm4908.dtsi | 18 +++++++++++++++++
- .../boot/dts/broadcom/bcmbca/bcm4912.dtsi | 20 +++++++++++++++++++
- .../boot/dts/broadcom/bcmbca/bcm63146.dtsi | 19 ++++++++++++++++++
- .../boot/dts/broadcom/bcmbca/bcm63158.dtsi | 19 ++++++++++++++++++
- .../boot/dts/broadcom/bcmbca/bcm6813.dtsi | 20 +++++++++++++++++++
- .../boot/dts/broadcom/bcmbca/bcm6856.dtsi | 18 +++++++++++++++++
- .../boot/dts/broadcom/bcmbca/bcm6858.dtsi | 18 +++++++++++++++++
- .../boot/dts/broadcom/bcmbca/bcm94908.dts | 4 ++++
- .../boot/dts/broadcom/bcmbca/bcm94912.dts | 4 ++++
- .../boot/dts/broadcom/bcmbca/bcm963146.dts | 4 ++++
- .../boot/dts/broadcom/bcmbca/bcm963158.dts | 4 ++++
- .../boot/dts/broadcom/bcmbca/bcm96813.dts | 4 ++++
- .../boot/dts/broadcom/bcmbca/bcm96856.dts | 4 ++++
- .../boot/dts/broadcom/bcmbca/bcm96858.dts | 4 ++++
- 14 files changed, 160 insertions(+)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-@@ -107,6 +107,12 @@
- clock-frequency = <50000000>;
- clock-output-names = "periph";
- };
-+
-+ hsspi_pll: hsspi-pll {
-+ compatible = "fixed-clock";
-+ #clock-cells = <0>;
-+ clock-frequency = <400000000>;
-+ };
- };
-
- soc {
-@@ -528,6 +534,18 @@
- #size-cells = <0>;
- };
-
-+ hsspi: spi@1000{
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ compatible = "brcm,bcm4908-hsspi", "brcm,bcmbca-hsspi-v1.0";
-+ reg = <0x1000 0x600>;
-+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&hsspi_pll &hsspi_pll>;
-+ clock-names = "hsspi", "pll";
-+ num-cs = <8>;
-+ status = "disabled";
-+ };
-+
- nand-controller@1800 {
- #address-cells = <1>;
- #size-cells = <0>;
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
-@@ -79,6 +79,7 @@
- #clock-cells = <0>;
- clock-frequency = <200000000>;
- };
-+
- uart_clk: uart-clk {
- compatible = "fixed-factor-clock";
- #clock-cells = <0>;
-@@ -86,6 +87,12 @@
- clock-div = <4>;
- clock-mult = <1>;
- };
-+
-+ hsspi_pll: hsspi-pll {
-+ compatible = "fixed-clock";
-+ #clock-cells = <0>;
-+ clock-frequency = <200000000>;
-+ };
- };
-
- psci {
-@@ -117,6 +124,19 @@
- #size-cells = <1>;
- ranges = <0x0 0x0 0xff800000 0x800000>;
-
-+ hsspi: spi@1000 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ compatible = "brcm,bcm4912-hsspi", "brcm,bcmbca-hsspi-v1.1";
-+ reg = <0x1000 0x600>, <0x2610 0x4>;
-+ reg-names = "hsspi", "spim-ctrl";
-+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&hsspi_pll &hsspi_pll>;
-+ clock-names = "hsspi", "pll";
-+ num-cs = <8>;
-+ status = "disabled";
-+ };
-+
- uart0: serial@12000 {
- compatible = "arm,pl011", "arm,primecell";
- reg = <0x12000 0x1000>;
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
-@@ -60,6 +60,7 @@
- #clock-cells = <0>;
- clock-frequency = <200000000>;
- };
-+
- uart_clk: uart-clk {
- compatible = "fixed-factor-clock";
- #clock-cells = <0>;
-@@ -67,6 +68,12 @@
- clock-div = <4>;
- clock-mult = <1>;
- };
-+
-+ hsspi_pll: hsspi-pll {
-+ compatible = "fixed-clock";
-+ #clock-cells = <0>;
-+ clock-frequency = <200000000>;
-+ };
- };
-
- psci {
-@@ -99,6 +106,18 @@
- #size-cells = <1>;
- ranges = <0x0 0x0 0xff800000 0x800000>;
-
-+ hsspi: spi@1000 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ compatible = "brcm,bcm63146-hsspi", "brcm,bcmbca-hsspi-v1.0";
-+ reg = <0x1000 0x600>;
-+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&hsspi_pll &hsspi_pll>;
-+ clock-names = "hsspi", "pll";
-+ num-cs = <8>;
-+ status = "disabled";
-+ };
-+
- uart0: serial@12000 {
- compatible = "arm,pl011", "arm,primecell";
- reg = <0x12000 0x1000>;
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
-@@ -79,6 +79,7 @@
- #clock-cells = <0>;
- clock-frequency = <200000000>;
- };
-+
- uart_clk: uart-clk {
- compatible = "fixed-factor-clock";
- #clock-cells = <0>;
-@@ -86,6 +87,12 @@
- clock-div = <4>;
- clock-mult = <1>;
- };
-+
-+ hsspi_pll: hsspi-pll {
-+ compatible = "fixed-clock";
-+ #clock-cells = <0>;
-+ clock-frequency = <400000000>;
-+ };
- };
-
- psci {
-@@ -117,6 +124,18 @@
- #size-cells = <1>;
- ranges = <0x0 0x0 0xff800000 0x800000>;
-
-+ hsspi: spi@1000 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ compatible = "brcm,bcm63158-hsspi", "brcm,bcmbca-hsspi-v1.0";
-+ reg = <0x1000 0x600>;
-+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&hsspi_pll &hsspi_pll>;
-+ clock-names = "hsspi", "pll";
-+ num-cs = <8>;
-+ status = "disabled";
-+ };
-+
- uart0: serial@12000 {
- compatible = "arm,pl011", "arm,primecell";
- reg = <0x12000 0x1000>;
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
-@@ -79,6 +79,7 @@
- #clock-cells = <0>;
- clock-frequency = <200000000>;
- };
-+
- uart_clk: uart-clk {
- compatible = "fixed-factor-clock";
- #clock-cells = <0>;
-@@ -86,6 +87,12 @@
- clock-div = <4>;
- clock-mult = <1>;
- };
-+
-+ hsspi_pll: hsspi-pll {
-+ compatible = "fixed-clock";
-+ #clock-cells = <0>;
-+ clock-frequency = <200000000>;
-+ };
- };
-
- psci {
-@@ -117,6 +124,19 @@
- #size-cells = <1>;
- ranges = <0x0 0x0 0xff800000 0x800000>;
-
-+ hsspi: spi@1000 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ compatible = "brcm,bcm6813-hsspi", "brcm,bcmbca-hsspi-v1.1";
-+ reg = <0x1000 0x600>, <0x2610 0x4>;
-+ reg-names = "hsspi", "spim-ctrl";
-+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&hsspi_pll &hsspi_pll>;
-+ clock-names = "hsspi", "pll";
-+ num-cs = <8>;
-+ status = "disabled";
-+ };
-+
- uart0: serial@12000 {
- compatible = "arm,pl011", "arm,primecell";
- reg = <0x12000 0x1000>;
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
-@@ -60,6 +60,12 @@
- #clock-cells = <0>;
- clock-frequency = <200000000>;
- };
-+
-+ hsspi_pll: hsspi-pll {
-+ compatible = "fixed-clock";
-+ #clock-cells = <0>;
-+ clock-frequency = <400000000>;
-+ };
- };
-
- psci {
-@@ -100,5 +106,17 @@
- clock-names = "refclk";
- status = "disabled";
- };
-+
-+ hsspi: spi@1000 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ compatible = "brcm,bcm6856-hsspi", "brcm,bcmbca-hsspi-v1.0";
-+ reg = <0x1000 0x600>;
-+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&hsspi_pll &hsspi_pll>;
-+ clock-names = "hsspi", "pll";
-+ num-cs = <8>;
-+ status = "disabled";
-+ };
- };
- };
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
-@@ -78,6 +78,12 @@
- #clock-cells = <0>;
- clock-frequency = <200000000>;
- };
-+
-+ hsspi_pll: hsspi-pll {
-+ compatible = "fixed-clock";
-+ #clock-cells = <0>;
-+ clock-frequency = <400000000>;
-+ };
- };
-
- psci {
-@@ -137,5 +143,17 @@
- clock-names = "refclk";
- status = "disabled";
- };
-+
-+ hsspi: spi@1000 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ compatible = "brcm,bcm6858-hsspi", "brcm,bcmbca-hsspi-v1.0";
-+ reg = <0x1000 0x600>;
-+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&hsspi_pll &hsspi_pll>;
-+ clock-names = "hsspi", "pll";
-+ num-cs = <8>;
-+ status = "disabled";
-+ };
- };
- };
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94908.dts
-@@ -28,3 +28,7 @@
- &uart0 {
- status = "okay";
- };
-+
-+&hsspi {
-+ status = "okay";
-+};
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts
-@@ -28,3 +28,7 @@
- &uart0 {
- status = "okay";
- };
-+
-+&hsspi {
-+ status = "okay";
-+};
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963146.dts
-@@ -28,3 +28,7 @@
- &uart0 {
- status = "okay";
- };
-+
-+&hsspi {
-+ status = "okay";
-+};
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts
-@@ -28,3 +28,7 @@
- &uart0 {
- status = "okay";
- };
-+
-+&hsspi {
-+ status = "okay";
-+};
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96813.dts
-@@ -28,3 +28,7 @@
- &uart0 {
- status = "okay";
- };
-+
-+&hsspi {
-+ status = "okay";
-+};
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96856.dts
-@@ -28,3 +28,7 @@
- &uart0 {
- status = "okay";
- };
-+
-+&hsspi {
-+ status = "okay";
-+};
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm96858.dts
-@@ -28,3 +28,7 @@
- &uart0 {
- status = "okay";
- };
-+
-+&hsspi {
-+ status = "okay";
-+};
+++ /dev/null
-From 23be9f68f933adee8163b8efc9c6bff71410cc7c Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Tue, 28 Feb 2023 15:43:59 +0100
-Subject: [PATCH] arm64: dts: broadcom: bcmbca: bcm4908: fix LED nodenames
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This fixes:
-arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dtb: leds@800: 'led-lan@19', 'led-power@11', 'led-wan-red@12', 'led-wan-white@15', 'led-wps@14' do not match any of the regexes: '^led@[a-f0-9]+$', 'pinctrl-[0-9]+'
- From schema: Documentation/devicetree/bindings/leds/leds-bcm63138.yaml
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Link: https://lore.kernel.org/all/20230228144400.21689-2-zajec5@gmail.com/
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- .../dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts | 10 +++++-----
- 1 file changed, 5 insertions(+), 5 deletions(-)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908-asus-gt-ac5300.dts
-@@ -120,7 +120,7 @@
- };
-
- &leds {
-- led-power@11 {
-+ led@11 {
- reg = <0x11>;
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_WHITE>;
-@@ -130,7 +130,7 @@
- pinctrl-0 = <&pins_led_17_a>;
- };
-
-- led-wan-red@12 {
-+ led@12 {
- reg = <0x12>;
- function = LED_FUNCTION_WAN;
- color = <LED_COLOR_ID_RED>;
-@@ -139,7 +139,7 @@
- pinctrl-0 = <&pins_led_18_a>;
- };
-
-- led-wps@14 {
-+ led@14 {
- reg = <0x14>;
- function = LED_FUNCTION_WPS;
- color = <LED_COLOR_ID_WHITE>;
-@@ -148,7 +148,7 @@
- pinctrl-0 = <&pins_led_20_a>;
- };
-
-- led-wan-white@15 {
-+ led@15 {
- reg = <0x15>;
- function = LED_FUNCTION_WAN;
- color = <LED_COLOR_ID_WHITE>;
-@@ -157,7 +157,7 @@
- pinctrl-0 = <&pins_led_21_a>;
- };
-
-- led-lan@19 {
-+ led@19 {
- reg = <0x19>;
- function = LED_FUNCTION_LAN;
- color = <LED_COLOR_ID_WHITE>;
+++ /dev/null
-From 477cad715de1dfc256a20da3ed83b62f3cb2944d Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Tue, 28 Feb 2023 15:45:18 +0100
-Subject: [PATCH] arm64: dts: broadcom: bcmbca: bcm4908: add on-SoC USB ports
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-BCM4908 has 3 USB controllers each with 2 USB ports. Home routers often
-have LEDs indicating state of selected USB ports. Describe those SoC USB
-ports to allow using them as LED trigger sources.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Link: https://lore.kernel.org/all/20230228144520.21816-1-zajec5@gmail.com/
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- .../boot/dts/broadcom/bcmbca/bcm4908.dtsi | 39 +++++++++++++++++++
- 1 file changed, 39 insertions(+)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-@@ -148,6 +148,19 @@
- interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&usb_phy PHY_TYPE_USB2>;
- status = "disabled";
-+
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ ehci_port1: port@1 {
-+ reg = <1>;
-+ #trigger-source-cells = <0>;
-+ };
-+
-+ ehci_port2: port@2 {
-+ reg = <2>;
-+ #trigger-source-cells = <0>;
-+ };
- };
-
- ohci: usb@c400 {
-@@ -156,6 +169,19 @@
- interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&usb_phy PHY_TYPE_USB2>;
- status = "disabled";
-+
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ ohci_port1: port@1 {
-+ reg = <1>;
-+ #trigger-source-cells = <0>;
-+ };
-+
-+ ohci_port2: port@2 {
-+ reg = <2>;
-+ #trigger-source-cells = <0>;
-+ };
- };
-
- xhci: usb@d000 {
-@@ -164,6 +190,19 @@
- interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&usb_phy PHY_TYPE_USB3>;
- status = "disabled";
-+
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ xhci_port1: port@1 {
-+ reg = <1>;
-+ #trigger-source-cells = <0>;
-+ };
-+
-+ xhci_port2: port@2 {
-+ reg = <2>;
-+ #trigger-source-cells = <0>;
-+ };
- };
-
- bus@80000 {
+++ /dev/null
-From 889e53ccccc29ff4bf8d4c89cca34e8768845747 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Tue, 28 Feb 2023 15:45:19 +0100
-Subject: [PATCH] arm64: dts: broadcom: bcmbca: bcm4908: add Netgear R8000P USB
- LED triggers
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This device has 2 USB LEDs meant to be triggered by devices in relevant
-USB ports.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Link: https://lore.kernel.org/all/20230228144520.21816-2-zajec5@gmail.com/
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- .../arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-netgear-r8000p.dts
-@@ -58,12 +58,16 @@
- function = "usb2";
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
-+ trigger-sources = <&ohci_port1>, <&ehci_port1>;
-+ linux,default-trigger = "usbport";
- };
-
- led-usb3 {
- function = "usb3";
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
-+ trigger-sources = <&ohci_port2>, <&ehci_port2>, <&xhci_port2>;
-+ linux,default-trigger = "usbport";
- };
-
- led-wifi {
+++ /dev/null
-From e6d356b146b75f1f77621aab7950a1eb550859f9 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Tue, 28 Feb 2023 15:45:20 +0100
-Subject: [PATCH] arm64: dts: broadcom: bcmbca: bcm4908: add TP-Link C2300 USB
- LED triggers
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This device has 2 USB LEDs meant to be triggered by devices in relevant
-USB ports.
-
-While at it fix typo in USB LED name.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Link: https://lore.kernel.org/all/20230228144520.21816-3-zajec5@gmail.com/
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- .../dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts | 6 +++++-
- 1 file changed, 5 insertions(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4906-tplink-archer-c2300-v1.dts
-@@ -64,12 +64,16 @@
- function = "usb2";
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
-+ trigger-sources = <&ohci_port1>, <&ehci_port1>;
-+ linux,default-trigger = "usbport";
- };
-
- led-usb3 {
-- function = "usbd3";
-+ function = "usb3";
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
-+ trigger-sources = <&ohci_port2>, <&ehci_port2>, <&xhci_port2>;
-+ linux,default-trigger = "usbport";
- };
-
- led-brightness {
+++ /dev/null
-From 002181f5b150e60c77f21de7ad4dd10e4614cd91 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Mon, 11 Jul 2022 17:30:41 +0200
-Subject: [PATCH] mtd: parsers: add Broadcom's U-Boot parser
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Broadcom stores environment variables blocks inside U-Boot partition
-itself. This driver finds & registers them.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
-Link: https://lore.kernel.org/linux-mtd/20220711153041.6036-2-zajec5@gmail.com
----
- drivers/mtd/parsers/Kconfig | 10 ++++
- drivers/mtd/parsers/Makefile | 1 +
- drivers/mtd/parsers/brcm_u-boot.c | 84 +++++++++++++++++++++++++++++++
- 3 files changed, 95 insertions(+)
- create mode 100644 drivers/mtd/parsers/brcm_u-boot.c
-
---- a/drivers/mtd/parsers/Kconfig
-+++ b/drivers/mtd/parsers/Kconfig
-@@ -20,6 +20,16 @@ config MTD_BCM63XX_PARTS
- This provides partition parsing for BCM63xx devices with CFE
- bootloaders.
-
-+config MTD_BRCM_U_BOOT
-+ tristate "Broadcom's U-Boot partition parser"
-+ depends on ARCH_BCM4908 || COMPILE_TEST
-+ help
-+ Broadcom uses a custom way of storing U-Boot environment variables.
-+ They are placed inside U-Boot partition itself at unspecified offset.
-+ It's possible to locate them by looking for a custom header with a
-+ magic value. This driver does that and creates subpartitions for
-+ each found environment variables block.
-+
- config MTD_CMDLINE_PARTS
- tristate "Command line partition table parsing"
- depends on MTD
---- a/drivers/mtd/parsers/Makefile
-+++ b/drivers/mtd/parsers/Makefile
-@@ -2,6 +2,7 @@
- obj-$(CONFIG_MTD_AR7_PARTS) += ar7part.o
- obj-$(CONFIG_MTD_BCM47XX_PARTS) += bcm47xxpart.o
- obj-$(CONFIG_MTD_BCM63XX_PARTS) += bcm63xxpart.o
-+obj-$(CONFIG_MTD_BRCM_U_BOOT) += brcm_u-boot.o
- obj-$(CONFIG_MTD_CMDLINE_PARTS) += cmdlinepart.o
- obj-$(CONFIG_MTD_MYLOADER_PARTS) += myloader.o
- obj-$(CONFIG_MTD_OF_PARTS) += ofpart.o
---- /dev/null
-+++ b/drivers/mtd/parsers/brcm_u-boot.c
-@@ -0,0 +1,84 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+/*
-+ * Copyright © 2022 Rafał Miłecki <rafal@milecki.pl>
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/slab.h>
-+#include <linux/mtd/mtd.h>
-+#include <linux/mtd/partitions.h>
-+
-+#define BRCM_U_BOOT_MAX_OFFSET 0x200000
-+#define BRCM_U_BOOT_STEP 0x1000
-+
-+#define BRCM_U_BOOT_MAX_PARTS 2
-+
-+#define BRCM_U_BOOT_MAGIC 0x75456e76 /* uEnv */
-+
-+struct brcm_u_boot_header {
-+ __le32 magic;
-+ __le32 length;
-+} __packed;
-+
-+static const char *names[BRCM_U_BOOT_MAX_PARTS] = {
-+ "u-boot-env",
-+ "u-boot-env-backup",
-+};
-+
-+static int brcm_u_boot_parse(struct mtd_info *mtd,
-+ const struct mtd_partition **pparts,
-+ struct mtd_part_parser_data *data)
-+{
-+ struct brcm_u_boot_header header;
-+ struct mtd_partition *parts;
-+ size_t bytes_read;
-+ size_t offset;
-+ int err;
-+ int i = 0;
-+
-+ parts = kcalloc(BRCM_U_BOOT_MAX_PARTS, sizeof(*parts), GFP_KERNEL);
-+ if (!parts)
-+ return -ENOMEM;
-+
-+ for (offset = 0;
-+ offset < min_t(size_t, mtd->size, BRCM_U_BOOT_MAX_OFFSET);
-+ offset += BRCM_U_BOOT_STEP) {
-+ err = mtd_read(mtd, offset, sizeof(header), &bytes_read, (uint8_t *)&header);
-+ if (err && !mtd_is_bitflip(err)) {
-+ pr_err("Failed to read from %s at 0x%zx: %d\n", mtd->name, offset, err);
-+ continue;
-+ }
-+
-+ if (le32_to_cpu(header.magic) != BRCM_U_BOOT_MAGIC)
-+ continue;
-+
-+ parts[i].name = names[i];
-+ parts[i].offset = offset;
-+ parts[i].size = sizeof(header) + le32_to_cpu(header.length);
-+ i++;
-+ pr_info("offset:0x%zx magic:0x%08x BINGO\n", offset, header.magic);
-+
-+ if (i == BRCM_U_BOOT_MAX_PARTS)
-+ break;
-+ }
-+
-+ *pparts = parts;
-+
-+ return i;
-+};
-+
-+static const struct of_device_id brcm_u_boot_of_match_table[] = {
-+ { .compatible = "brcm,u-boot" },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, brcm_u_boot_of_match_table);
-+
-+static struct mtd_part_parser brcm_u_boot_mtd_parser = {
-+ .parse_fn = brcm_u_boot_parse,
-+ .name = "brcm_u-boot",
-+ .of_match_table = brcm_u_boot_of_match_table,
-+};
-+module_mtd_part_parser(brcm_u_boot_mtd_parser);
-+
-+MODULE_LICENSE("GPL");
+++ /dev/null
-From af30f8eaa8fe4ff1987280f716309711997bd979 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Wed, 29 Dec 2021 18:16:42 +0100
-Subject: [PATCH] net: dsa: bcm_sf2: refactor LED regs access
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-1. Define more regs. Some switches (e.g. BCM4908) have up to 6 regs.
-2. Add helper for handling non-lineral port <-> reg mappings.
-3. Add support for 12 B LED reg blocks on BCM4908 (different layout)
-
-Complete support for LEDs setup will be implemented once Linux receives
-a proper design & implementation for "hardware" LEDs.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Acked-by: Florian Fainelli <f.fainelli@gmail.com>
-Link: https://lore.kernel.org/r/20211229171642.22942-1-zajec5@gmail.com
-Signed-off-by: Jakub Kicinski <kuba@kernel.org>
----
- drivers/net/dsa/bcm_sf2.c | 54 ++++++++++++++++++++++++----
- drivers/net/dsa/bcm_sf2.h | 10 ++++++
- drivers/net/dsa/bcm_sf2_regs.h | 65 +++++++++++++++++++++++++++++++---
- 3 files changed, 119 insertions(+), 10 deletions(-)
-
---- a/drivers/net/dsa/bcm_sf2.c
-+++ b/drivers/net/dsa/bcm_sf2.c
-@@ -62,6 +62,38 @@ static u16 bcm_sf2_reg_rgmii_cntrl(struc
- return REG_SWITCH_STATUS;
- }
-
-+static u16 bcm_sf2_reg_led_base(struct bcm_sf2_priv *priv, int port)
-+{
-+ switch (port) {
-+ case 0:
-+ return REG_LED_0_CNTRL;
-+ case 1:
-+ return REG_LED_1_CNTRL;
-+ case 2:
-+ return REG_LED_2_CNTRL;
-+ }
-+
-+ switch (priv->type) {
-+ case BCM4908_DEVICE_ID:
-+ switch (port) {
-+ case 3:
-+ return REG_LED_3_CNTRL;
-+ case 7:
-+ return REG_LED_4_CNTRL;
-+ default:
-+ break;
-+ }
-+ break;
-+ default:
-+ break;
-+ }
-+
-+ WARN_ONCE(1, "Unsupported port %d\n", port);
-+
-+ /* RO fallback reg */
-+ return REG_SWITCH_STATUS;
-+}
-+
- /* Return the number of active ports, not counting the IMP (CPU) port */
- static unsigned int bcm_sf2_num_active_ports(struct dsa_switch *ds)
- {
-@@ -187,9 +219,14 @@ static void bcm_sf2_gphy_enable_set(stru
-
- /* Use PHY-driven LED signaling */
- if (!enable) {
-- reg = reg_readl(priv, REG_LED_CNTRL(0));
-- reg |= SPDLNK_SRC_SEL;
-- reg_writel(priv, reg, REG_LED_CNTRL(0));
-+ u16 led_ctrl = bcm_sf2_reg_led_base(priv, 0);
-+
-+ if (priv->type == BCM7278_DEVICE_ID ||
-+ priv->type == BCM7445_DEVICE_ID) {
-+ reg = reg_led_readl(priv, led_ctrl, 0);
-+ reg |= LED_CNTRL_SPDLNK_SRC_SEL;
-+ reg_led_writel(priv, reg, led_ctrl, 0);
-+ }
- }
- }
-
-@@ -1247,9 +1284,14 @@ static const u16 bcm_sf2_4908_reg_offset
- [REG_SPHY_CNTRL] = 0x24,
- [REG_CROSSBAR] = 0xc8,
- [REG_RGMII_11_CNTRL] = 0x014c,
-- [REG_LED_0_CNTRL] = 0x40,
-- [REG_LED_1_CNTRL] = 0x4c,
-- [REG_LED_2_CNTRL] = 0x58,
-+ [REG_LED_0_CNTRL] = 0x40,
-+ [REG_LED_1_CNTRL] = 0x4c,
-+ [REG_LED_2_CNTRL] = 0x58,
-+ [REG_LED_3_CNTRL] = 0x64,
-+ [REG_LED_4_CNTRL] = 0x88,
-+ [REG_LED_5_CNTRL] = 0xa0,
-+ [REG_LED_AGGREGATE_CTRL] = 0xb8,
-+
- };
-
- static const struct bcm_sf2_of_data bcm_sf2_4908_data = {
---- a/drivers/net/dsa/bcm_sf2.h
-+++ b/drivers/net/dsa/bcm_sf2.h
-@@ -210,6 +210,16 @@ SF2_IO_MACRO(acb);
- SWITCH_INTR_L2(0);
- SWITCH_INTR_L2(1);
-
-+static inline u32 reg_led_readl(struct bcm_sf2_priv *priv, u16 off, u16 reg)
-+{
-+ return readl_relaxed(priv->reg + priv->reg_offsets[off] + reg);
-+}
-+
-+static inline void reg_led_writel(struct bcm_sf2_priv *priv, u32 val, u16 off, u16 reg)
-+{
-+ writel_relaxed(val, priv->reg + priv->reg_offsets[off] + reg);
-+}
-+
- /* RXNFC */
- int bcm_sf2_get_rxnfc(struct dsa_switch *ds, int port,
- struct ethtool_rxnfc *nfc, u32 *rule_locs);
---- a/drivers/net/dsa/bcm_sf2_regs.h
-+++ b/drivers/net/dsa/bcm_sf2_regs.h
-@@ -25,6 +25,10 @@ enum bcm_sf2_reg_offs {
- REG_LED_0_CNTRL,
- REG_LED_1_CNTRL,
- REG_LED_2_CNTRL,
-+ REG_LED_3_CNTRL,
-+ REG_LED_4_CNTRL,
-+ REG_LED_5_CNTRL,
-+ REG_LED_AGGREGATE_CTRL,
- REG_SWITCH_REG_MAX,
- };
-
-@@ -56,6 +60,63 @@ enum bcm_sf2_reg_offs {
- #define CROSSBAR_BCM4908_EXT_GPHY4 1
- #define CROSSBAR_BCM4908_EXT_RGMII 2
-
-+/* Relative to REG_LED_*_CNTRL (BCM7278, BCM7445) */
-+#define LED_CNTRL_NO_LINK_ENCODE_SHIFT 0
-+#define LED_CNTRL_M10_ENCODE_SHIFT 2
-+#define LED_CNTRL_M100_ENCODE_SHIFT 4
-+#define LED_CNTRL_M1000_ENCODE_SHIFT 6
-+#define LED_CNTRL_SEL_NO_LINK_ENCODE_SHIFT 8
-+#define LED_CNTRL_SEL_10M_ENCODE_SHIFT 10
-+#define LED_CNTRL_SEL_100M_ENCODE_SHIFT 12
-+#define LED_CNTRL_SEL_1000M_ENCODE_SHIFT 14
-+#define LED_CNTRL_RX_DV_EN (1 << 16)
-+#define LED_CNTRL_TX_EN_EN (1 << 17)
-+#define LED_CNTRL_SPDLNK_LED0_ACT_SEL_SHIFT 18
-+#define LED_CNTRL_SPDLNK_LED1_ACT_SEL_SHIFT 20
-+#define LED_CNTRL_ACT_LED_ACT_SEL_SHIFT 22
-+#define LED_CNTRL_SPDLNK_SRC_SEL (1 << 24)
-+#define LED_CNTRL_SPDLNK_LED0_ACT_POL_SEL (1 << 25)
-+#define LED_CNTRL_SPDLNK_LED1_ACT_POL_SEL (1 << 26)
-+#define LED_CNTRL_ACT_LED_POL_SEL (1 << 27)
-+#define LED_CNTRL_MASK 0x3
-+
-+/* Register relative to REG_LED_*_CNTRL (BCM4908) */
-+#define REG_LED_CTRL 0x0
-+#define LED_CTRL_RX_ACT_EN 0x00000001
-+#define LED_CTRL_TX_ACT_EN 0x00000002
-+#define LED_CTRL_SPDLNK_LED0_ACT_SEL 0x00000004
-+#define LED_CTRL_SPDLNK_LED1_ACT_SEL 0x00000008
-+#define LED_CTRL_SPDLNK_LED2_ACT_SEL 0x00000010
-+#define LED_CTRL_ACT_LED_ACT_SEL 0x00000020
-+#define LED_CTRL_SPDLNK_LED0_ACT_POL_SEL 0x00000040
-+#define LED_CTRL_SPDLNK_LED1_ACT_POL_SEL 0x00000080
-+#define LED_CTRL_SPDLNK_LED2_ACT_POL_SEL 0x00000100
-+#define LED_CTRL_ACT_LED_POL_SEL 0x00000200
-+#define LED_CTRL_LED_SPD_OVRD 0x00001c00
-+#define LED_CTRL_LNK_STATUS_OVRD 0x00002000
-+#define LED_CTRL_SPD_OVRD_EN 0x00004000
-+#define LED_CTRL_LNK_OVRD_EN 0x00008000
-+
-+/* Register relative to REG_LED_*_CNTRL (BCM4908) */
-+#define REG_LED_LINK_SPEED_ENC_SEL 0x4
-+#define LED_LINK_SPEED_ENC_SEL_NO_LINK_SHIFT 0
-+#define LED_LINK_SPEED_ENC_SEL_10M_SHIFT 3
-+#define LED_LINK_SPEED_ENC_SEL_100M_SHIFT 6
-+#define LED_LINK_SPEED_ENC_SEL_1000M_SHIFT 9
-+#define LED_LINK_SPEED_ENC_SEL_2500M_SHIFT 12
-+#define LED_LINK_SPEED_ENC_SEL_10G_SHIFT 15
-+#define LED_LINK_SPEED_ENC_SEL_MASK 0x7
-+
-+/* Register relative to REG_LED_*_CNTRL (BCM4908) */
-+#define REG_LED_LINK_SPEED_ENC 0x8
-+#define LED_LINK_SPEED_ENC_NO_LINK_SHIFT 0
-+#define LED_LINK_SPEED_ENC_M10_SHIFT 3
-+#define LED_LINK_SPEED_ENC_M100_SHIFT 6
-+#define LED_LINK_SPEED_ENC_M1000_SHIFT 9
-+#define LED_LINK_SPEED_ENC_M2500_SHIFT 12
-+#define LED_LINK_SPEED_ENC_M10G_SHIFT 15
-+#define LED_LINK_SPEED_ENC_MASK 0x7
-+
- /* Relative to REG_RGMII_CNTRL */
- #define RGMII_MODE_EN (1 << 0)
- #define ID_MODE_DIS (1 << 1)
-@@ -73,10 +134,6 @@ enum bcm_sf2_reg_offs {
- #define LPI_COUNT_SHIFT 9
- #define LPI_COUNT_MASK 0x3F
-
--#define REG_LED_CNTRL(x) (REG_LED_0_CNTRL + (x))
--
--#define SPDLNK_SRC_SEL (1 << 24)
--
- /* Register set relative to 'INTRL2_0' and 'INTRL2_1' */
- #define INTRL2_CPU_STATUS 0x00
- #define INTRL2_CPU_SET 0x04
+++ /dev/null
-From e93a766da57fff3273bcb618edf5dfca1fb86b89 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Thu, 15 Sep 2022 15:30:13 +0200
-Subject: [PATCH] net: broadcom: bcm4908_enet: handle -EPROBE_DEFER when
- getting MAC
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Reading MAC from OF may return -EPROBE_DEFER if underlaying NVMEM device
-isn't ready yet. In such case pass that error code up and "wait" to be
-probed later.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Link: https://lore.kernel.org/r/20220915133013.2243-1-zajec5@gmail.com
-Signed-off-by: Jakub Kicinski <kuba@kernel.org>
----
- drivers/net/ethernet/broadcom/bcm4908_enet.c | 13 +++++++++----
- 1 file changed, 9 insertions(+), 4 deletions(-)
-
---- a/drivers/net/ethernet/broadcom/bcm4908_enet.c
-+++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c
-@@ -720,6 +720,8 @@ static int bcm4908_enet_probe(struct pla
-
- SET_NETDEV_DEV(netdev, &pdev->dev);
- err = of_get_ethdev_address(dev->of_node, netdev);
-+ if (err == -EPROBE_DEFER)
-+ goto err_dma_free;
- if (err)
- eth_hw_addr_random(netdev);
- netdev->netdev_ops = &bcm4908_enet_netdev_ops;
-@@ -730,14 +732,17 @@ static int bcm4908_enet_probe(struct pla
- netif_napi_add(netdev, &enet->rx_ring.napi, bcm4908_enet_poll_rx, NAPI_POLL_WEIGHT);
-
- err = register_netdev(netdev);
-- if (err) {
-- bcm4908_enet_dma_free(enet);
-- return err;
-- }
-+ if (err)
-+ goto err_dma_free;
-
- platform_set_drvdata(pdev, enet);
-
- return 0;
-+
-+err_dma_free:
-+ bcm4908_enet_dma_free(enet);
-+
-+ return err;
- }
-
- static int bcm4908_enet_remove(struct platform_device *pdev)
+++ /dev/null
-From 3a1cc23a75abcd9cea585eb84846507363d58397 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Tue, 25 Oct 2022 15:22:45 +0200
-Subject: [PATCH] net: broadcom: bcm4908_enet: use build_skb()
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-RX code can be more efficient with the build_skb(). Allocating actual
-SKB around eth packet buffer - right before passing it up - results in
-a better cache usage.
-
-Without RPS (echo 0 > rps_cpus) BCM4908 NAT masq performance "jumps"
-between two speeds: ~900 Mbps and 940 Mbps (it's a 4 CPUs SoC). This
-change bumps the lower speed from 905 Mb/s to 918 Mb/s (tested using
-single stream iperf 2.0.5 traffic).
-
-There are more optimizations to consider. One obvious to try is GRO
-however as BCM4908 doesn't do hw csum is may actually lower performance.
-Sometimes. Some early testing:
-
-┌─────────────────────────────────┬─────────────────────┬────────────────────┐
-│ │ netif_receive_skb() │ napi_gro_receive() │
-├─────────────────────────────────┼─────────────────────┼────────────────────┤
-│ netdev_alloc_skb() │ 905 Mb/s │ 892 Mb/s │
-│ napi_alloc_frag() + build_skb() │ 918 Mb/s │ 917 Mb/s │
-└─────────────────────────────────┴─────────────────────┴────────────────────┘
-
-Another ideas:
-1. napi_build_skb()
-2. skb_copy_from_linear_data() for small packets
-
-Those need proper testing first though. That can be done later.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Link: https://lore.kernel.org/r/20221025132245.22871-1-zajec5@gmail.com
-Signed-off-by: Paolo Abeni <pabeni@redhat.com>
----
- drivers/net/ethernet/broadcom/bcm4908_enet.c | 53 +++++++++++++-------
- 1 file changed, 36 insertions(+), 17 deletions(-)
-
---- a/drivers/net/ethernet/broadcom/bcm4908_enet.c
-+++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c
-@@ -36,13 +36,24 @@
- #define ENET_MAX_ETH_OVERHEAD (ETH_HLEN + BRCM_MAX_TAG_LEN + VLAN_HLEN + \
- ETH_FCS_LEN + 4) /* 32 */
-
-+#define ENET_RX_SKB_BUF_SIZE (NET_SKB_PAD + NET_IP_ALIGN + \
-+ ETH_HLEN + BRCM_MAX_TAG_LEN + VLAN_HLEN + \
-+ ENET_MTU_MAX + ETH_FCS_LEN + 4)
-+#define ENET_RX_SKB_BUF_ALLOC_SIZE (SKB_DATA_ALIGN(ENET_RX_SKB_BUF_SIZE) + \
-+ SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
-+#define ENET_RX_BUF_DMA_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
-+#define ENET_RX_BUF_DMA_SIZE (ENET_RX_SKB_BUF_SIZE - ENET_RX_BUF_DMA_OFFSET)
-+
- struct bcm4908_enet_dma_ring_bd {
- __le32 ctl;
- __le32 addr;
- } __packed;
-
- struct bcm4908_enet_dma_ring_slot {
-- struct sk_buff *skb;
-+ union {
-+ void *buf; /* RX */
-+ struct sk_buff *skb; /* TX */
-+ };
- unsigned int len;
- dma_addr_t dma_addr;
- };
-@@ -260,22 +271,21 @@ static int bcm4908_enet_dma_alloc_rx_buf
- u32 tmp;
- int err;
-
-- slot->len = ENET_MTU_MAX + ENET_MAX_ETH_OVERHEAD;
--
-- slot->skb = netdev_alloc_skb(enet->netdev, slot->len);
-- if (!slot->skb)
-+ slot->buf = napi_alloc_frag(ENET_RX_SKB_BUF_ALLOC_SIZE);
-+ if (!slot->buf)
- return -ENOMEM;
-
-- slot->dma_addr = dma_map_single(dev, slot->skb->data, slot->len, DMA_FROM_DEVICE);
-+ slot->dma_addr = dma_map_single(dev, slot->buf + ENET_RX_BUF_DMA_OFFSET,
-+ ENET_RX_BUF_DMA_SIZE, DMA_FROM_DEVICE);
- err = dma_mapping_error(dev, slot->dma_addr);
- if (err) {
- dev_err(dev, "Failed to map DMA buffer: %d\n", err);
-- kfree_skb(slot->skb);
-- slot->skb = NULL;
-+ skb_free_frag(slot->buf);
-+ slot->buf = NULL;
- return err;
- }
-
-- tmp = slot->len << DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT;
-+ tmp = ENET_RX_BUF_DMA_SIZE << DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT;
- tmp |= DMA_CTL_STATUS_OWN;
- if (idx == enet->rx_ring.length - 1)
- tmp |= DMA_CTL_STATUS_WRAP;
-@@ -315,11 +325,11 @@ static void bcm4908_enet_dma_uninit(stru
-
- for (i = rx_ring->length - 1; i >= 0; i--) {
- slot = &rx_ring->slots[i];
-- if (!slot->skb)
-+ if (!slot->buf)
- continue;
- dma_unmap_single(dev, slot->dma_addr, slot->len, DMA_FROM_DEVICE);
-- kfree_skb(slot->skb);
-- slot->skb = NULL;
-+ skb_free_frag(slot->buf);
-+ slot->buf = NULL;
- }
- }
-
-@@ -575,6 +585,7 @@ static int bcm4908_enet_poll_rx(struct n
- while (handled < weight) {
- struct bcm4908_enet_dma_ring_bd *buf_desc;
- struct bcm4908_enet_dma_ring_slot slot;
-+ struct sk_buff *skb;
- u32 ctl;
- int len;
- int err;
-@@ -598,16 +609,24 @@ static int bcm4908_enet_poll_rx(struct n
-
- if (len < ETH_ZLEN ||
- (ctl & (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) != (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) {
-- kfree_skb(slot.skb);
-+ skb_free_frag(slot.buf);
- enet->netdev->stats.rx_dropped++;
- break;
- }
-
-- dma_unmap_single(dev, slot.dma_addr, slot.len, DMA_FROM_DEVICE);
-+ dma_unmap_single(dev, slot.dma_addr, ENET_RX_BUF_DMA_SIZE, DMA_FROM_DEVICE);
-+
-+ skb = build_skb(slot.buf, ENET_RX_SKB_BUF_ALLOC_SIZE);
-+ if (unlikely(!skb)) {
-+ skb_free_frag(slot.buf);
-+ enet->netdev->stats.rx_dropped++;
-+ break;
-+ }
-+ skb_reserve(skb, ENET_RX_BUF_DMA_OFFSET);
-+ skb_put(skb, len - ETH_FCS_LEN);
-+ skb->protocol = eth_type_trans(skb, enet->netdev);
-
-- skb_put(slot.skb, len - ETH_FCS_LEN);
-- slot.skb->protocol = eth_type_trans(slot.skb, enet->netdev);
-- netif_receive_skb(slot.skb);
-+ netif_receive_skb(skb);
-
- enet->netdev->stats.rx_packets++;
- enet->netdev->stats.rx_bytes += len;
+++ /dev/null
-From 471ef777ec79baadc5cd9773d08f95f49cf5e2b1 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Mon, 31 Oct 2022 11:48:56 +0100
-Subject: [PATCH] net: broadcom: bcm4908_enet: report queued and transmitted
- bytes
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-This allows BQL to operate avoiding buffer bloat and reducing latency.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Link: https://lore.kernel.org/r/20221031104856.32388-1-zajec5@gmail.com
-Signed-off-by: Jakub Kicinski <kuba@kernel.org>
----
- drivers/net/ethernet/broadcom/bcm4908_enet.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/drivers/net/ethernet/broadcom/bcm4908_enet.c
-+++ b/drivers/net/ethernet/broadcom/bcm4908_enet.c
-@@ -505,6 +505,7 @@ static int bcm4908_enet_stop(struct net_
- netif_carrier_off(netdev);
- napi_disable(&rx_ring->napi);
- napi_disable(&tx_ring->napi);
-+ netdev_reset_queue(netdev);
-
- bcm4908_enet_dma_rx_ring_disable(enet, &enet->rx_ring);
- bcm4908_enet_dma_tx_ring_disable(enet, &enet->tx_ring);
-@@ -564,6 +565,8 @@ static int bcm4908_enet_start_xmit(struc
- if (ring->write_idx + 1 == ring->length - 1)
- tmp |= DMA_CTL_STATUS_WRAP;
-
-+ netdev_sent_queue(enet->netdev, skb->len);
-+
- buf_desc->addr = cpu_to_le32((uint32_t)slot->dma_addr);
- buf_desc->ctl = cpu_to_le32(tmp);
-
-@@ -671,6 +674,7 @@ static int bcm4908_enet_poll_tx(struct n
- tx_ring->read_idx = 0;
- }
-
-+ netdev_completed_queue(enet->netdev, handled, bytes);
- enet->netdev->stats.tx_packets += handled;
- enet->netdev->stats.tx_bytes += bytes;
-
+++ /dev/null
-From 7b5730f0ff24b0d7d1cb660a482384a807618a46 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Mon, 24 Jan 2022 11:22:42 +0100
-Subject: [PATCH] dt-bindings: pinctrl: Add binding for BCM4908 pinctrl
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-It's hardware block that is part of every SoC from BCM4908 family.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Reviewed-by: Rob Herring <robh@kernel.org>
-Link: https://lore.kernel.org/r/20220124102243.14912-1-zajec5@gmail.com
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- .../pinctrl/brcm,bcm4908-pinctrl.yaml | 72 +++++++++++++++++++
- MAINTAINERS | 7 ++
- 2 files changed, 79 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml
-@@ -0,0 +1,72 @@
-+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/pinctrl/brcm,bcm4908-pinctrl.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: Broadcom BCM4908 pin controller
-+
-+maintainers:
-+ - Rafał Miłecki <rafal@milecki.pl>
-+
-+description:
-+ Binding for pin controller present on BCM4908 family SoCs.
-+
-+properties:
-+ compatible:
-+ const: brcm,bcm4908-pinctrl
-+
-+ reg:
-+ maxItems: 1
-+
-+patternProperties:
-+ '-pins$':
-+ type: object
-+ $ref: pinmux-node.yaml#
-+
-+ properties:
-+ function:
-+ enum: [ led_0, led_1, led_2, led_3, led_4, led_5, led_6, led_7, led_8,
-+ led_9, led_10, led_11, led_12, led_13, led_14, led_15, led_16,
-+ led_17, led_18, led_19, led_20, led_21, led_22, led_23, led_24,
-+ led_25, led_26, led_27, led_28, led_29, led_30, led_31,
-+ hs_uart, i2c, i2s, nand_ctrl, nand_data, emmc_ctrl, usb0_pwr,
-+ usb1_pwr ]
-+
-+ groups:
-+ minItems: 1
-+ maxItems: 2
-+ items:
-+ enum: [ led_0_grp_a, led_1_grp_a, led_2_grp_a, led_3_grp_a,
-+ led_4_grp_a, led_5_grp_a, led_6_grp_a, led_7_grp_a,
-+ led_8_grp_a, led_9_grp_a, led_10_grp_a, led_10_grp_b,
-+ led_11_grp_a, led_11_grp_b, led_12_grp_a, led_12_grp_b,
-+ led_13_grp_a, led_13_grp_b, led_14_grp_a, led_15_grp_a,
-+ led_16_grp_a, led_17_grp_a, led_18_grp_a, led_19_grp_a,
-+ led_20_grp_a, led_21_grp_a, led_22_grp_a, led_23_grp_a,
-+ led_24_grp_a, led_25_grp_a, led_26_grp_a, led_27_grp_a,
-+ led_28_grp_a, led_29_grp_a, led_30_grp_a, led_31_grp_a,
-+ led_31_grp_b, hs_uart_grp, i2c_grp_a, i2c_grp_b, i2s_grp,
-+ nand_ctrl_grp, nand_data_grp, emmc_ctrl_grp, usb0_pwr_grp,
-+ usb1_pwr_grp ]
-+
-+allOf:
-+ - $ref: pinctrl.yaml#
-+
-+required:
-+ - compatible
-+ - reg
-+
-+unevaluatedProperties: false
-+
-+examples:
-+ - |
-+ pinctrl@ff800560 {
-+ compatible = "brcm,bcm4908-pinctrl";
-+ reg = <0xff800560 0x10>;
-+
-+ led_0-a-pins {
-+ function = "led_0";
-+ groups = "led_0_grp_a";
-+ };
-+ };
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -3573,6 +3573,13 @@ F: Documentation/devicetree/bindings/net
- F: drivers/net/ethernet/broadcom/bcm4908_enet.*
- F: drivers/net/ethernet/broadcom/unimac.h
-
-+BROADCOM BCM4908 PINMUX DRIVER
-+M: Rafał Miłecki <rafal@milecki.pl>
-+M: bcm-kernel-feedback-list@broadcom.com
-+L: linux-gpio@vger.kernel.org
-+S: Maintained
-+F: Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml
-+
- BROADCOM BCM5301X ARM ARCHITECTURE
- M: Hauke Mehrtens <hauke@hauke-m.de>
- M: Rafał Miłecki <zajec5@gmail.com>
+++ /dev/null
-From f7e322d99f1180270fb4a3e1ae992b3116cfcf34 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Mon, 24 Jan 2022 11:22:43 +0100
-Subject: [PATCH] pinctrl: bcm: add driver for BCM4908 pinmux
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-BCM4908 has its own pins layout so it needs a custom binding and a Linux
-driver.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
-Link: https://lore.kernel.org/r/20220124102243.14912-2-zajec5@gmail.com
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- MAINTAINERS | 1 +
- drivers/pinctrl/bcm/Kconfig | 14 +
- drivers/pinctrl/bcm/Makefile | 1 +
- drivers/pinctrl/bcm/pinctrl-bcm4908.c | 563 ++++++++++++++++++++++++++
- 4 files changed, 579 insertions(+)
- create mode 100644 drivers/pinctrl/bcm/pinctrl-bcm4908.c
-
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -3579,6 +3579,7 @@ M: bcm-kernel-feedback-list@broadcom.com
- L: linux-gpio@vger.kernel.org
- S: Maintained
- F: Documentation/devicetree/bindings/pinctrl/brcm,bcm4908-pinctrl.yaml
-+F: drivers/pinctrl/bcm/pinctrl-bcm4908.c
-
- BROADCOM BCM5301X ARM ARCHITECTURE
- M: Hauke Mehrtens <hauke@hauke-m.de>
---- a/drivers/pinctrl/bcm/Kconfig
-+++ b/drivers/pinctrl/bcm/Kconfig
-@@ -29,6 +29,20 @@ config PINCTRL_BCM2835
- help
- Say Y here to enable the Broadcom BCM2835 GPIO driver.
-
-+config PINCTRL_BCM4908
-+ tristate "Broadcom BCM4908 pinmux driver"
-+ depends on OF && (ARCH_BCM4908 || COMPILE_TEST)
-+ select PINMUX
-+ select PINCONF
-+ select GENERIC_PINCONF
-+ select GENERIC_PINCTRL_GROUPS
-+ select GENERIC_PINMUX_FUNCTIONS
-+ default ARCH_BCM4908
-+ help
-+ Driver for BCM4908 family SoCs with integrated pin controller.
-+
-+ If compiled as module it will be called pinctrl-bcm4908.
-+
- config PINCTRL_BCM63XX
- bool
- select PINMUX
---- a/drivers/pinctrl/bcm/Makefile
-+++ b/drivers/pinctrl/bcm/Makefile
-@@ -3,6 +3,7 @@
-
- obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o
- obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
-+obj-$(CONFIG_PINCTRL_BCM4908) += pinctrl-bcm4908.o
- obj-$(CONFIG_PINCTRL_BCM63XX) += pinctrl-bcm63xx.o
- obj-$(CONFIG_PINCTRL_BCM6318) += pinctrl-bcm6318.o
- obj-$(CONFIG_PINCTRL_BCM6328) += pinctrl-bcm6328.o
---- /dev/null
-+++ b/drivers/pinctrl/bcm/pinctrl-bcm4908.c
-@@ -0,0 +1,560 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/* Copyright (C) 2021 Rafał Miłecki <rafal@milecki.pl> */
-+
-+#include <linux/err.h>
-+#include <linux/io.h>
-+#include <linux/mod_devicetable.h>
-+#include <linux/module.h>
-+#include <linux/pinctrl/pinconf-generic.h>
-+#include <linux/pinctrl/pinctrl.h>
-+#include <linux/pinctrl/pinmux.h>
-+#include <linux/platform_device.h>
-+#include <linux/slab.h>
-+#include <linux/string_helpers.h>
-+
-+#include "../core.h"
-+#include "../pinmux.h"
-+
-+#define BCM4908_NUM_PINS 86
-+
-+#define BCM4908_TEST_PORT_BLOCK_EN_LSB 0x00
-+#define BCM4908_TEST_PORT_BLOCK_DATA_MSB 0x04
-+#define BCM4908_TEST_PORT_BLOCK_DATA_LSB 0x08
-+#define BCM4908_TEST_PORT_LSB_PINMUX_DATA_SHIFT 12
-+#define BCM4908_TEST_PORT_COMMAND 0x0c
-+#define BCM4908_TEST_PORT_CMD_LOAD_MUX_REG 0x00000021
-+
-+struct bcm4908_pinctrl {
-+ struct device *dev;
-+ void __iomem *base;
-+ struct mutex mutex;
-+ struct pinctrl_dev *pctldev;
-+ struct pinctrl_desc pctldesc;
-+};
-+
-+/*
-+ * Groups
-+ */
-+
-+struct bcm4908_pinctrl_pin_setup {
-+ unsigned int number;
-+ unsigned int function;
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_0_pins_a[] = {
-+ { 0, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_1_pins_a[] = {
-+ { 1, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_2_pins_a[] = {
-+ { 2, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_3_pins_a[] = {
-+ { 3, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_4_pins_a[] = {
-+ { 4, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_5_pins_a[] = {
-+ { 5, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_6_pins_a[] = {
-+ { 6, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_7_pins_a[] = {
-+ { 7, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_8_pins_a[] = {
-+ { 8, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_9_pins_a[] = {
-+ { 9, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_10_pins_a[] = {
-+ { 10, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_11_pins_a[] = {
-+ { 11, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_12_pins_a[] = {
-+ { 12, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_13_pins_a[] = {
-+ { 13, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_14_pins_a[] = {
-+ { 14, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_15_pins_a[] = {
-+ { 15, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_16_pins_a[] = {
-+ { 16, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_17_pins_a[] = {
-+ { 17, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_18_pins_a[] = {
-+ { 18, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_19_pins_a[] = {
-+ { 19, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_20_pins_a[] = {
-+ { 20, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_21_pins_a[] = {
-+ { 21, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_22_pins_a[] = {
-+ { 22, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_23_pins_a[] = {
-+ { 23, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_24_pins_a[] = {
-+ { 24, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_25_pins_a[] = {
-+ { 25, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_26_pins_a[] = {
-+ { 26, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_27_pins_a[] = {
-+ { 27, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_28_pins_a[] = {
-+ { 28, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_29_pins_a[] = {
-+ { 29, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_30_pins_a[] = {
-+ { 30, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_31_pins_a[] = {
-+ { 31, 3 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_10_pins_b[] = {
-+ { 8, 2 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_11_pins_b[] = {
-+ { 9, 2 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_12_pins_b[] = {
-+ { 0, 2 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_13_pins_b[] = {
-+ { 1, 2 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup led_31_pins_b[] = {
-+ { 30, 2 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup hs_uart_pins[] = {
-+ { 10, 0 }, /* CTS */
-+ { 11, 0 }, /* RTS */
-+ { 12, 0 }, /* RXD */
-+ { 13, 0 }, /* TXD */
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup i2c_pins_a[] = {
-+ { 18, 0 }, /* SDA */
-+ { 19, 0 }, /* SCL */
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup i2c_pins_b[] = {
-+ { 22, 0 }, /* SDA */
-+ { 23, 0 }, /* SCL */
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup i2s_pins[] = {
-+ { 27, 0 }, /* MCLK */
-+ { 28, 0 }, /* LRCK */
-+ { 29, 0 }, /* SDATA */
-+ { 30, 0 }, /* SCLK */
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup nand_ctrl_pins[] = {
-+ { 32, 0 },
-+ { 33, 0 },
-+ { 34, 0 },
-+ { 43, 0 },
-+ { 44, 0 },
-+ { 45, 0 },
-+ { 56, 1 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup nand_data_pins[] = {
-+ { 35, 0 },
-+ { 36, 0 },
-+ { 37, 0 },
-+ { 38, 0 },
-+ { 39, 0 },
-+ { 40, 0 },
-+ { 41, 0 },
-+ { 42, 0 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup emmc_ctrl_pins[] = {
-+ { 46, 0 },
-+ { 47, 0 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup usb0_pwr_pins[] = {
-+ { 63, 0 },
-+ { 64, 0 },
-+};
-+
-+static const struct bcm4908_pinctrl_pin_setup usb1_pwr_pins[] = {
-+ { 66, 0 },
-+ { 67, 0 },
-+};
-+
-+struct bcm4908_pinctrl_grp {
-+ const char *name;
-+ const struct bcm4908_pinctrl_pin_setup *pins;
-+ const unsigned int num_pins;
-+};
-+
-+static const struct bcm4908_pinctrl_grp bcm4908_pinctrl_grps[] = {
-+ { "led_0_grp_a", led_0_pins_a, ARRAY_SIZE(led_0_pins_a) },
-+ { "led_1_grp_a", led_1_pins_a, ARRAY_SIZE(led_1_pins_a) },
-+ { "led_2_grp_a", led_2_pins_a, ARRAY_SIZE(led_2_pins_a) },
-+ { "led_3_grp_a", led_3_pins_a, ARRAY_SIZE(led_3_pins_a) },
-+ { "led_4_grp_a", led_4_pins_a, ARRAY_SIZE(led_4_pins_a) },
-+ { "led_5_grp_a", led_5_pins_a, ARRAY_SIZE(led_5_pins_a) },
-+ { "led_6_grp_a", led_6_pins_a, ARRAY_SIZE(led_6_pins_a) },
-+ { "led_7_grp_a", led_7_pins_a, ARRAY_SIZE(led_7_pins_a) },
-+ { "led_8_grp_a", led_8_pins_a, ARRAY_SIZE(led_8_pins_a) },
-+ { "led_9_grp_a", led_9_pins_a, ARRAY_SIZE(led_9_pins_a) },
-+ { "led_10_grp_a", led_10_pins_a, ARRAY_SIZE(led_10_pins_a) },
-+ { "led_11_grp_a", led_11_pins_a, ARRAY_SIZE(led_11_pins_a) },
-+ { "led_12_grp_a", led_12_pins_a, ARRAY_SIZE(led_12_pins_a) },
-+ { "led_13_grp_a", led_13_pins_a, ARRAY_SIZE(led_13_pins_a) },
-+ { "led_14_grp_a", led_14_pins_a, ARRAY_SIZE(led_14_pins_a) },
-+ { "led_15_grp_a", led_15_pins_a, ARRAY_SIZE(led_15_pins_a) },
-+ { "led_16_grp_a", led_16_pins_a, ARRAY_SIZE(led_16_pins_a) },
-+ { "led_17_grp_a", led_17_pins_a, ARRAY_SIZE(led_17_pins_a) },
-+ { "led_18_grp_a", led_18_pins_a, ARRAY_SIZE(led_18_pins_a) },
-+ { "led_19_grp_a", led_19_pins_a, ARRAY_SIZE(led_19_pins_a) },
-+ { "led_20_grp_a", led_20_pins_a, ARRAY_SIZE(led_20_pins_a) },
-+ { "led_21_grp_a", led_21_pins_a, ARRAY_SIZE(led_21_pins_a) },
-+ { "led_22_grp_a", led_22_pins_a, ARRAY_SIZE(led_22_pins_a) },
-+ { "led_23_grp_a", led_23_pins_a, ARRAY_SIZE(led_23_pins_a) },
-+ { "led_24_grp_a", led_24_pins_a, ARRAY_SIZE(led_24_pins_a) },
-+ { "led_25_grp_a", led_25_pins_a, ARRAY_SIZE(led_25_pins_a) },
-+ { "led_26_grp_a", led_26_pins_a, ARRAY_SIZE(led_26_pins_a) },
-+ { "led_27_grp_a", led_27_pins_a, ARRAY_SIZE(led_27_pins_a) },
-+ { "led_28_grp_a", led_28_pins_a, ARRAY_SIZE(led_28_pins_a) },
-+ { "led_29_grp_a", led_29_pins_a, ARRAY_SIZE(led_29_pins_a) },
-+ { "led_30_grp_a", led_30_pins_a, ARRAY_SIZE(led_30_pins_a) },
-+ { "led_31_grp_a", led_31_pins_a, ARRAY_SIZE(led_31_pins_a) },
-+ { "led_10_grp_b", led_10_pins_b, ARRAY_SIZE(led_10_pins_b) },
-+ { "led_11_grp_b", led_11_pins_b, ARRAY_SIZE(led_11_pins_b) },
-+ { "led_12_grp_b", led_12_pins_b, ARRAY_SIZE(led_12_pins_b) },
-+ { "led_13_grp_b", led_13_pins_b, ARRAY_SIZE(led_13_pins_b) },
-+ { "led_31_grp_b", led_31_pins_b, ARRAY_SIZE(led_31_pins_b) },
-+ { "hs_uart_grp", hs_uart_pins, ARRAY_SIZE(hs_uart_pins) },
-+ { "i2c_grp_a", i2c_pins_a, ARRAY_SIZE(i2c_pins_a) },
-+ { "i2c_grp_b", i2c_pins_b, ARRAY_SIZE(i2c_pins_b) },
-+ { "i2s_grp", i2s_pins, ARRAY_SIZE(i2s_pins) },
-+ { "nand_ctrl_grp", nand_ctrl_pins, ARRAY_SIZE(nand_ctrl_pins) },
-+ { "nand_data_grp", nand_data_pins, ARRAY_SIZE(nand_data_pins) },
-+ { "emmc_ctrl_grp", emmc_ctrl_pins, ARRAY_SIZE(emmc_ctrl_pins) },
-+ { "usb0_pwr_grp", usb0_pwr_pins, ARRAY_SIZE(usb0_pwr_pins) },
-+ { "usb1_pwr_grp", usb1_pwr_pins, ARRAY_SIZE(usb1_pwr_pins) },
-+};
-+
-+/*
-+ * Functions
-+ */
-+
-+struct bcm4908_pinctrl_function {
-+ const char *name;
-+ const char **groups;
-+ const unsigned int num_groups;
-+};
-+
-+static const char *led_0_groups[] = { "led_0_grp_a" };
-+static const char *led_1_groups[] = { "led_1_grp_a" };
-+static const char *led_2_groups[] = { "led_2_grp_a" };
-+static const char *led_3_groups[] = { "led_3_grp_a" };
-+static const char *led_4_groups[] = { "led_4_grp_a" };
-+static const char *led_5_groups[] = { "led_5_grp_a" };
-+static const char *led_6_groups[] = { "led_6_grp_a" };
-+static const char *led_7_groups[] = { "led_7_grp_a" };
-+static const char *led_8_groups[] = { "led_8_grp_a" };
-+static const char *led_9_groups[] = { "led_9_grp_a" };
-+static const char *led_10_groups[] = { "led_10_grp_a", "led_10_grp_b" };
-+static const char *led_11_groups[] = { "led_11_grp_a", "led_11_grp_b" };
-+static const char *led_12_groups[] = { "led_12_grp_a", "led_12_grp_b" };
-+static const char *led_13_groups[] = { "led_13_grp_a", "led_13_grp_b" };
-+static const char *led_14_groups[] = { "led_14_grp_a" };
-+static const char *led_15_groups[] = { "led_15_grp_a" };
-+static const char *led_16_groups[] = { "led_16_grp_a" };
-+static const char *led_17_groups[] = { "led_17_grp_a" };
-+static const char *led_18_groups[] = { "led_18_grp_a" };
-+static const char *led_19_groups[] = { "led_19_grp_a" };
-+static const char *led_20_groups[] = { "led_20_grp_a" };
-+static const char *led_21_groups[] = { "led_21_grp_a" };
-+static const char *led_22_groups[] = { "led_22_grp_a" };
-+static const char *led_23_groups[] = { "led_23_grp_a" };
-+static const char *led_24_groups[] = { "led_24_grp_a" };
-+static const char *led_25_groups[] = { "led_25_grp_a" };
-+static const char *led_26_groups[] = { "led_26_grp_a" };
-+static const char *led_27_groups[] = { "led_27_grp_a" };
-+static const char *led_28_groups[] = { "led_28_grp_a" };
-+static const char *led_29_groups[] = { "led_29_grp_a" };
-+static const char *led_30_groups[] = { "led_30_grp_a" };
-+static const char *led_31_groups[] = { "led_31_grp_a", "led_31_grp_b" };
-+static const char *hs_uart_groups[] = { "hs_uart_grp" };
-+static const char *i2c_groups[] = { "i2c_grp_a", "i2c_grp_b" };
-+static const char *i2s_groups[] = { "i2s_grp" };
-+static const char *nand_ctrl_groups[] = { "nand_ctrl_grp" };
-+static const char *nand_data_groups[] = { "nand_data_grp" };
-+static const char *emmc_ctrl_groups[] = { "emmc_ctrl_grp" };
-+static const char *usb0_pwr_groups[] = { "usb0_pwr_grp" };
-+static const char *usb1_pwr_groups[] = { "usb1_pwr_grp" };
-+
-+static const struct bcm4908_pinctrl_function bcm4908_pinctrl_functions[] = {
-+ { "led_0", led_0_groups, ARRAY_SIZE(led_0_groups) },
-+ { "led_1", led_1_groups, ARRAY_SIZE(led_1_groups) },
-+ { "led_2", led_2_groups, ARRAY_SIZE(led_2_groups) },
-+ { "led_3", led_3_groups, ARRAY_SIZE(led_3_groups) },
-+ { "led_4", led_4_groups, ARRAY_SIZE(led_4_groups) },
-+ { "led_5", led_5_groups, ARRAY_SIZE(led_5_groups) },
-+ { "led_6", led_6_groups, ARRAY_SIZE(led_6_groups) },
-+ { "led_7", led_7_groups, ARRAY_SIZE(led_7_groups) },
-+ { "led_8", led_8_groups, ARRAY_SIZE(led_8_groups) },
-+ { "led_9", led_9_groups, ARRAY_SIZE(led_9_groups) },
-+ { "led_10", led_10_groups, ARRAY_SIZE(led_10_groups) },
-+ { "led_11", led_11_groups, ARRAY_SIZE(led_11_groups) },
-+ { "led_12", led_12_groups, ARRAY_SIZE(led_12_groups) },
-+ { "led_13", led_13_groups, ARRAY_SIZE(led_13_groups) },
-+ { "led_14", led_14_groups, ARRAY_SIZE(led_14_groups) },
-+ { "led_15", led_15_groups, ARRAY_SIZE(led_15_groups) },
-+ { "led_16", led_16_groups, ARRAY_SIZE(led_16_groups) },
-+ { "led_17", led_17_groups, ARRAY_SIZE(led_17_groups) },
-+ { "led_18", led_18_groups, ARRAY_SIZE(led_18_groups) },
-+ { "led_19", led_19_groups, ARRAY_SIZE(led_19_groups) },
-+ { "led_20", led_20_groups, ARRAY_SIZE(led_20_groups) },
-+ { "led_21", led_21_groups, ARRAY_SIZE(led_21_groups) },
-+ { "led_22", led_22_groups, ARRAY_SIZE(led_22_groups) },
-+ { "led_23", led_23_groups, ARRAY_SIZE(led_23_groups) },
-+ { "led_24", led_24_groups, ARRAY_SIZE(led_24_groups) },
-+ { "led_25", led_25_groups, ARRAY_SIZE(led_25_groups) },
-+ { "led_26", led_26_groups, ARRAY_SIZE(led_26_groups) },
-+ { "led_27", led_27_groups, ARRAY_SIZE(led_27_groups) },
-+ { "led_28", led_28_groups, ARRAY_SIZE(led_28_groups) },
-+ { "led_29", led_29_groups, ARRAY_SIZE(led_29_groups) },
-+ { "led_30", led_30_groups, ARRAY_SIZE(led_30_groups) },
-+ { "led_31", led_31_groups, ARRAY_SIZE(led_31_groups) },
-+ { "hs_uart", hs_uart_groups, ARRAY_SIZE(hs_uart_groups) },
-+ { "i2c", i2c_groups, ARRAY_SIZE(i2c_groups) },
-+ { "i2s", i2s_groups, ARRAY_SIZE(i2s_groups) },
-+ { "nand_ctrl", nand_ctrl_groups, ARRAY_SIZE(nand_ctrl_groups) },
-+ { "nand_data", nand_data_groups, ARRAY_SIZE(nand_data_groups) },
-+ { "emmc_ctrl", emmc_ctrl_groups, ARRAY_SIZE(emmc_ctrl_groups) },
-+ { "usb0_pwr", usb0_pwr_groups, ARRAY_SIZE(usb0_pwr_groups) },
-+ { "usb1_pwr", usb1_pwr_groups, ARRAY_SIZE(usb1_pwr_groups) },
-+};
-+
-+/*
-+ * Groups code
-+ */
-+
-+static const struct pinctrl_ops bcm4908_pinctrl_ops = {
-+ .get_groups_count = pinctrl_generic_get_group_count,
-+ .get_group_name = pinctrl_generic_get_group_name,
-+ .get_group_pins = pinctrl_generic_get_group_pins,
-+ .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
-+ .dt_free_map = pinconf_generic_dt_free_map,
-+};
-+
-+/*
-+ * Functions code
-+ */
-+
-+static int bcm4908_pinctrl_set_mux(struct pinctrl_dev *pctrl_dev,
-+ unsigned int func_selector,
-+ unsigned int group_selector)
-+{
-+ struct bcm4908_pinctrl *bcm4908_pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
-+ const struct bcm4908_pinctrl_grp *group;
-+ struct group_desc *group_desc;
-+ int i;
-+
-+ group_desc = pinctrl_generic_get_group(pctrl_dev, group_selector);
-+ if (!group_desc)
-+ return -EINVAL;
-+ group = group_desc->data;
-+
-+ mutex_lock(&bcm4908_pinctrl->mutex);
-+ for (i = 0; i < group->num_pins; i++) {
-+ u32 lsb = 0;
-+
-+ lsb |= group->pins[i].number;
-+ lsb |= group->pins[i].function << BCM4908_TEST_PORT_LSB_PINMUX_DATA_SHIFT;
-+
-+ writel(0x0, bcm4908_pinctrl->base + BCM4908_TEST_PORT_BLOCK_DATA_MSB);
-+ writel(lsb, bcm4908_pinctrl->base + BCM4908_TEST_PORT_BLOCK_DATA_LSB);
-+ writel(BCM4908_TEST_PORT_CMD_LOAD_MUX_REG,
-+ bcm4908_pinctrl->base + BCM4908_TEST_PORT_COMMAND);
-+ }
-+ mutex_unlock(&bcm4908_pinctrl->mutex);
-+
-+ return 0;
-+}
-+
-+static const struct pinmux_ops bcm4908_pinctrl_pmxops = {
-+ .get_functions_count = pinmux_generic_get_function_count,
-+ .get_function_name = pinmux_generic_get_function_name,
-+ .get_function_groups = pinmux_generic_get_function_groups,
-+ .set_mux = bcm4908_pinctrl_set_mux,
-+};
-+
-+/*
-+ * Controller code
-+ */
-+
-+static struct pinctrl_desc bcm4908_pinctrl_desc = {
-+ .name = "bcm4908-pinctrl",
-+ .pctlops = &bcm4908_pinctrl_ops,
-+ .pmxops = &bcm4908_pinctrl_pmxops,
-+};
-+
-+static const struct of_device_id bcm4908_pinctrl_of_match_table[] = {
-+ { .compatible = "brcm,bcm4908-pinctrl", },
-+ { }
-+};
-+
-+static int bcm4908_pinctrl_probe(struct platform_device *pdev)
-+{
-+ struct device *dev = &pdev->dev;
-+ struct bcm4908_pinctrl *bcm4908_pinctrl;
-+ struct pinctrl_desc *pctldesc;
-+ struct pinctrl_pin_desc *pins;
-+ int i;
-+
-+ bcm4908_pinctrl = devm_kzalloc(dev, sizeof(*bcm4908_pinctrl), GFP_KERNEL);
-+ if (!bcm4908_pinctrl)
-+ return -ENOMEM;
-+ pctldesc = &bcm4908_pinctrl->pctldesc;
-+ platform_set_drvdata(pdev, bcm4908_pinctrl);
-+
-+ /* Set basic properties */
-+
-+ bcm4908_pinctrl->dev = dev;
-+
-+ bcm4908_pinctrl->base = devm_platform_ioremap_resource(pdev, 0);
-+ if (IS_ERR(bcm4908_pinctrl->base))
-+ return PTR_ERR(bcm4908_pinctrl->base);
-+
-+ mutex_init(&bcm4908_pinctrl->mutex);
-+
-+ memcpy(pctldesc, &bcm4908_pinctrl_desc, sizeof(*pctldesc));
-+
-+ /* Set pinctrl properties */
-+
-+ pins = devm_kcalloc(dev, BCM4908_NUM_PINS, sizeof(*pins), GFP_KERNEL);
-+ if (!pins)
-+ return -ENOMEM;
-+ for (i = 0; i < BCM4908_NUM_PINS; i++) {
-+ pins[i].number = i;
-+ pins[i].name = devm_kasprintf(dev, GFP_KERNEL, "pin-%d", i);
-+ if (!pins[i].name)
-+ return -ENOMEM;
-+ }
-+ pctldesc->pins = pins;
-+ pctldesc->npins = BCM4908_NUM_PINS;
-+
-+ /* Register */
-+
-+ bcm4908_pinctrl->pctldev = devm_pinctrl_register(dev, pctldesc, bcm4908_pinctrl);
-+ if (IS_ERR(bcm4908_pinctrl->pctldev))
-+ return dev_err_probe(dev, PTR_ERR(bcm4908_pinctrl->pctldev),
-+ "Failed to register pinctrl\n");
-+
-+ /* Groups */
-+
-+ for (i = 0; i < ARRAY_SIZE(bcm4908_pinctrl_grps); i++) {
-+ const struct bcm4908_pinctrl_grp *group = &bcm4908_pinctrl_grps[i];
-+ int *pins;
-+ int j;
-+
-+ pins = devm_kcalloc(dev, group->num_pins, sizeof(*pins), GFP_KERNEL);
-+ if (!pins)
-+ return -ENOMEM;
-+ for (j = 0; j < group->num_pins; j++)
-+ pins[j] = group->pins[j].number;
-+
-+ pinctrl_generic_add_group(bcm4908_pinctrl->pctldev, group->name,
-+ pins, group->num_pins, (void *)group);
-+ }
-+
-+ /* Functions */
-+
-+ for (i = 0; i < ARRAY_SIZE(bcm4908_pinctrl_functions); i++) {
-+ const struct bcm4908_pinctrl_function *function = &bcm4908_pinctrl_functions[i];
-+
-+ pinmux_generic_add_function(bcm4908_pinctrl->pctldev,
-+ function->name,
-+ function->groups,
-+ function->num_groups, NULL);
-+ }
-+
-+ return 0;
-+}
-+
-+static struct platform_driver bcm4908_pinctrl_driver = {
-+ .probe = bcm4908_pinctrl_probe,
-+ .driver = {
-+ .name = "bcm4908-pinctrl",
-+ .of_match_table = bcm4908_pinctrl_of_match_table,
-+ },
-+};
-+
-+module_platform_driver(bcm4908_pinctrl_driver);
-+
-+MODULE_AUTHOR("Rafał Miłecki");
-+MODULE_LICENSE("GPL v2");
-+MODULE_DEVICE_TABLE(of, bcm4908_pinctrl_of_match_table);
+++ /dev/null
-From d0aee048d648ec2d9aa7af43b127ebf847d497d5 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Fri, 11 Feb 2022 11:58:06 +0100
-Subject: [PATCH] i2c: brcmstb: allow compiling on BCM4908
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-BCM4908 SoCs use the same I2C hardware block as STB and BCM63xx devices.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Acked-by: Florian Fainelli <f.fainelli@gmail.com>
-Signed-off-by: Wolfram Sang <wsa@kernel.org>
----
- drivers/i2c/busses/Kconfig | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/drivers/i2c/busses/Kconfig
-+++ b/drivers/i2c/busses/Kconfig
-@@ -477,8 +477,8 @@ config I2C_BCM_KONA
-
- config I2C_BRCMSTB
- tristate "BRCM Settop/DSL I2C controller"
-- depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC || \
-- ARCH_BCM_63XX || COMPILE_TEST
-+ depends on ARCH_BCM2835 || ARCH_BCM4908 || ARCH_BCM_63XX || \
-+ ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST
- default y
- help
- If you say yes to this option, support will be included for the
+++ /dev/null
-From cd91fb2776967b2b2dea27307a3f23ba3d9bbb32 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Wed, 9 Feb 2022 21:32:02 +0100
-Subject: [PATCH] watchdog: allow building BCM7038_WDT for BCM4908
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-BCM4908 is a SoCs family that shares a lot of hardware with BCM63xx
-including the watchdog block. Allow building this driver for it.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Acked-by: Florian Fainelli <f.fainelli@gmail.com>
-Reviewed-by: Guenter Roeck <linux@roeck-us.net>
-Link: https://lore.kernel.org/r/20220209203202.26395-1-zajec5@gmail.com
-Signed-off-by: Guenter Roeck <linux@roeck-us.net>
-Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
----
- drivers/watchdog/Kconfig | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/watchdog/Kconfig
-+++ b/drivers/watchdog/Kconfig
-@@ -1756,7 +1756,7 @@ config BCM7038_WDT
- tristate "BCM7038 Watchdog"
- select WATCHDOG_CORE
- depends on HAS_IOMEM
-- depends on ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST
-+ depends on ARCH_BCM4908 || ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST
- help
- Watchdog driver for the built-in hardware in Broadcom 7038 and
- later SoCs used in set-top boxes. BCM7038 was made public
+++ /dev/null
-From 2dd441f16d6ad6104d85c4e5dfeb6dde4df26869 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Wed, 16 Feb 2022 07:34:08 +0100
-Subject: [PATCH] watchdog: bcm7038_wdt: Support BCM6345 compatible string
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-A new "compatible" value has been added in the commit 17fffe91ba36
-("dt-bindings: watchdog: Add BCM6345 compatible to BCM7038 binding").
-It's meant to be used for BCM63xx SoCs family but hardware block can be
-programmed just like the 7038 one.
-
-Cc: Florian Fainelli <f.fainelli@gmail.com>
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Acked-by: Florian Fainelli <f.fainelli@gmail.com>
-Reviewed-by: Guenter Roeck <linux@roeck-us.net>
-Link: https://lore.kernel.org/r/20220216063408.23168-1-zajec5@gmail.com
-Signed-off-by: Guenter Roeck <linux@roeck-us.net>
-Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
----
- drivers/watchdog/bcm7038_wdt.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/watchdog/bcm7038_wdt.c
-+++ b/drivers/watchdog/bcm7038_wdt.c
-@@ -212,6 +212,7 @@ static SIMPLE_DEV_PM_OPS(bcm7038_wdt_pm_
- bcm7038_wdt_resume);
-
- static const struct of_device_id bcm7038_wdt_match[] = {
-+ { .compatible = "brcm,bcm6345-wdt" },
- { .compatible = "brcm,bcm7038-wdt" },
- {},
- };
+++ /dev/null
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Thu, 28 Mar 2024 10:24:34 +0100
-Subject: [PATCH] arm64: dts: broadcom: bcmbca: bcm4908: set
- brcm,wp-not-connected
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Every described BCM4908 board has WP pin not connected. This caused
-problems for drivers since day 0 but there was no property to describe
-that properly. Projects like OpenWrt were modifying Linux driver to deal
-with it.
-
-It's not clear if that is hardware limitation or just reference design
-being copied over and over but this applies to all known / supported
-BCM4908 boards. Handle it by marking WP as not connected by default.
-
-Fixes: 2961f69f151c ("arm64: dts: broadcom: add BCM4908 and Asus GT-AC5300 early DTS files")
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
----
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-@@ -593,6 +593,7 @@
- reg-names = "nand", "nand-int-base";
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "nand_ctlrdy";
-+ brcm,wp-not-connected;
- status = "okay";
-
- nandcs: nand@0 {
+++ /dev/null
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Mon, 15 Feb 2021 22:01:03 +0100
-Subject: [PATCH] arm64: dts: broadcom: bcmbca: bcm4908: limit amount of GPIOs
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Linux driver can't handle more than 64 GPIOs
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
----
-
---- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
-@@ -340,7 +340,7 @@
- gpio0: gpio-controller@500 {
- compatible = "brcm,bcm6345-gpio";
- reg-names = "dirout", "dat";
-- reg = <0x500 0x28>, <0x528 0x28>;
-+ reg = <0x500 0x8>, <0x528 0x8>;
-
- #gpio-cells = <2>;
- gpio-controller;
+++ /dev/null
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Thu, 12 Aug 2021 11:52:42 +0200
-Subject: [PATCH] arm64: don't issue HVC on boot
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Broadcom's CFE loader seems to miss setting SCR_EL3.HCE which results in
-generating an UNDEF and kernel panic on the first HVC.
-
-HVC gets issued by kernels 5.12+ while booting, by kexec and KVM. Until
-someone finds a workaround we have to avoid all above.
-
-Workarounds: 0c93df9622d4 ("arm64: Initialise as nVHE before switching to VHE")
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
----
- arch/arm64/kernel/hyp-stub.S | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm64/kernel/hyp-stub.S
-+++ b/arch/arm64/kernel/hyp-stub.S
-@@ -238,7 +238,7 @@ SYM_FUNC_START(switch_to_vhe)
-
- // Turn the world upside down
- mov x0, #HVC_VHE_RESTART
-- hvc #0
-+// hvc #0
- 1:
- ret
- SYM_FUNC_END(switch_to_vhe)
+++ /dev/null
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Mon, 15 Feb 2021 23:59:26 +0100
-Subject: [PATCH] net: dsa: bcm_sf2: enable GPHY for switch probing
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-GPHY needs to be enabled to succesfully probe & setup switch port
-connected to it. Otherwise hardcoding PHY OUI would be required.
-
-Before:
-brcm-sf2 80080000.switch lan4 (uninitialized): PHY [800c05c0.mdio--1:08] driver [Generic PHY] (irq=POLL)
-brcm-sf2 80080000.switch lan3 (uninitialized): PHY [800c05c0.mdio--1:09] driver [Generic PHY] (irq=POLL)
-brcm-sf2 80080000.switch lan2 (uninitialized): PHY [800c05c0.mdio--1:0a] driver [Generic PHY] (irq=POLL)
-brcm-sf2 80080000.switch lan1 (uninitialized): PHY [800c05c0.mdio--1:0b] driver [Generic PHY] (irq=POLL)
-brcm-sf2 80080000.switch wan (uninitialized): error -5 setting up PHY for tree 0, switch 0, port 7
-
-After:
-brcm-sf2 80080000.switch lan4 (uninitialized): PHY [800c05c0.mdio--1:08] driver [Generic PHY] (irq=POLL)
-brcm-sf2 80080000.switch lan3 (uninitialized): PHY [800c05c0.mdio--1:09] driver [Generic PHY] (irq=POLL)
-brcm-sf2 80080000.switch lan2 (uninitialized): PHY [800c05c0.mdio--1:0a] driver [Generic PHY] (irq=POLL)
-brcm-sf2 80080000.switch lan1 (uninitialized): PHY [800c05c0.mdio--1:0b] driver [Generic PHY] (irq=POLL)
-brcm-sf2 80080000.switch wan (uninitialized): PHY [800c05c0.mdio--1:0c] driver [Generic PHY] (irq=POLL)
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
----
- drivers/net/dsa/bcm_sf2.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/drivers/net/dsa/bcm_sf2.c
-+++ b/drivers/net/dsa/bcm_sf2.c
-@@ -1548,10 +1548,14 @@ static int bcm_sf2_sw_probe(struct platf
- rev = reg_readl(priv, REG_PHY_REVISION);
- priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
-
-+ bcm_sf2_gphy_enable_set(priv->dev->ds, true);
-+
- ret = b53_switch_register(dev);
- if (ret)
- goto out_mdio;
-
-+ bcm_sf2_gphy_enable_set(priv->dev->ds, false);
-+
- dev_info(&pdev->dev,
- "Starfighter 2 top: %x.%02x, core: %x.%02x, IRQs: %d, %d\n",
- priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
+++ /dev/null
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Tue, 16 Feb 2021 00:06:35 +0100
-Subject: [PATCH] net: dsa: bcm_sf2: keep GPHY enabled on the BCM4908
-
-Trying to access disabled PHY results in MDIO_READ_FAIL and:
-[ 11.962886] brcm-sf2 80080000.switch wan: configuring for phy/internal link mode
-[ 11.972500] 8021q: adding VLAN 0 to HW filter on device wan
-[ 11.980205] ------------[ cut here ]------------
-[ 11.984885] WARNING: CPU: 0 PID: 7 at phy_error+0x10/0x58
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
----
- drivers/net/dsa/bcm_sf2.c | 6 ++++++
- 1 file changed, 6 insertions(+)
-
---- a/drivers/net/dsa/bcm_sf2.c
-+++ b/drivers/net/dsa/bcm_sf2.c
-@@ -1562,6 +1562,12 @@ static int bcm_sf2_sw_probe(struct platf
- priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
- priv->irq0, priv->irq1);
-
-+ /* BCM4908 has 5 GPHYs which means bcm_sf2_port_setup() will not enable
-+ * GPHY when needed. Leave it enabled here.
-+ */
-+ if (priv->type == BCM4908_DEVICE_ID)
-+ bcm_sf2_gphy_enable_set(priv->dev->ds, true);
-+
- return 0;
-
- out_mdio:
#define NETIF_F_UPPER_DISABLES NETIF_F_LRO
/* changeable features with no special hardware requirements */
--#define NETIF_F_SOFT_FEATURES (NETIF_F_GSO | NETIF_F_GRO)
+-#define NETIF_F_SOFT_FEATURES (NETIF_F_GSO | NETIF_F_GRO | NETIF_F_GRO_FRAGLIST)
+#define NETIF_F_SOFT_FEATURES (NETIF_F_GSO)
/* Changeable features with no special hardware requirements that defaults to off. */
--#define NETIF_F_SOFT_FEATURES_OFF (NETIF_F_GRO_FRAGLIST | NETIF_F_GRO_UDP_FWD)
-+#define NETIF_F_SOFT_FEATURES_OFF (NETIF_F_GRO_FRAGLIST | NETIF_F_GRO_UDP_FWD | NETIF_F_GRO)
+-#define NETIF_F_SOFT_FEATURES_OFF (NETIF_F_GRO_UDP_FWD)
++#define NETIF_F_SOFT_FEATURES_OFF (NETIF_F_GRO_UDP_FWD | NETIF_F_GRO | NETIF_F_GRO_FRAGLIST)
#define NETIF_F_VLAN_FEATURES (NETIF_F_HW_VLAN_CTAG_FILTER | \
NETIF_F_HW_VLAN_CTAG_RX | \
if (xhci->quirks & XHCI_NEC_HOST)
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
-@@ -1907,6 +1907,7 @@ struct xhci_hcd {
+@@ -1912,6 +1912,7 @@ struct xhci_hcd {
#define XHCI_RESET_TO_DEFAULT BIT_ULL(44)
#define XHCI_ZHAOXIN_TRB_FETCH BIT_ULL(45)
#define XHCI_ZHAOXIN_HOST BIT_ULL(46)
subs r9, r9, #1 @ decrement the index
bge loop2
subs r4, r4, #1 @ decrement the way
+--- a/arch/arm/boot/compressed/vmlinux.lds.S
++++ b/arch/arm/boot/compressed/vmlinux.lds.S
+@@ -41,6 +41,7 @@ SECTIONS
+ *(.start)
+ *(.text)
+ *(.text.*)
++ *(.init.text)
+ ARM_STUBS_TEXT
+ }
+ .table : ALIGN(4) {
#define NETIF_F_UPPER_DISABLES NETIF_F_LRO
/* changeable features with no special hardware requirements */
--#define NETIF_F_SOFT_FEATURES (NETIF_F_GSO | NETIF_F_GRO)
+-#define NETIF_F_SOFT_FEATURES (NETIF_F_GSO | NETIF_F_GRO | NETIF_F_GRO_FRAGLIST)
+#define NETIF_F_SOFT_FEATURES (NETIF_F_GSO)
/* Changeable features with no special hardware requirements that defaults to off. */
--#define NETIF_F_SOFT_FEATURES_OFF (NETIF_F_GRO_FRAGLIST | NETIF_F_GRO_UDP_FWD)
-+#define NETIF_F_SOFT_FEATURES_OFF (NETIF_F_GRO_FRAGLIST | NETIF_F_GRO_UDP_FWD | NETIF_F_GRO)
+-#define NETIF_F_SOFT_FEATURES_OFF (NETIF_F_GRO_UDP_FWD)
++#define NETIF_F_SOFT_FEATURES_OFF (NETIF_F_GRO_UDP_FWD | NETIF_F_GRO | NETIF_F_GRO_FRAGLIST)
#define NETIF_F_VLAN_FEATURES (NETIF_F_HW_VLAN_CTAG_FILTER | \
NETIF_F_HW_VLAN_CTAG_RX | \
--- /dev/null
+From: Pablo Neira Ayuso <pablo@netfilter.org>
+Date: Thu, 11 Apr 2024 13:28:59 +0200
+Subject: [PATCH] netfilter: flowtable: validate pppoe header
+
+Ensure there is sufficient room to access the protocol field of the
+PPPoe header. Validate it once before the flowtable lookup, then use a
+helper function to access protocol field.
+
+Reported-by: syzbot+b6f07e1c07ef40199081@syzkaller.appspotmail.com
+Fixes: 72efd585f714 ("netfilter: flowtable: add pppoe support")
+Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
+---
+
+--- a/include/net/netfilter/nf_flow_table.h
++++ b/include/net/netfilter/nf_flow_table.h
+@@ -318,7 +318,7 @@ int nf_flow_rule_route_ipv6(struct net *
+ int nf_flow_table_offload_init(void);
+ void nf_flow_table_offload_exit(void);
+
+-static inline __be16 nf_flow_pppoe_proto(const struct sk_buff *skb)
++static inline __be16 __nf_flow_pppoe_proto(const struct sk_buff *skb)
+ {
+ __be16 proto;
+
+@@ -334,4 +334,14 @@ static inline __be16 nf_flow_pppoe_proto
+ return 0;
+ }
+
++static inline bool nf_flow_pppoe_proto(struct sk_buff *skb, __be16 *inner_proto)
++{
++ if (!pskb_may_pull(skb, PPPOE_SES_HLEN))
++ return false;
++
++ *inner_proto = __nf_flow_pppoe_proto(skb);
++
++ return true;
++}
++
+ #endif /* _NF_FLOW_TABLE_H */
+--- a/net/netfilter/nf_flow_table_inet.c
++++ b/net/netfilter/nf_flow_table_inet.c
+@@ -21,7 +21,8 @@ nf_flow_offload_inet_hook(void *priv, st
+ proto = veth->h_vlan_encapsulated_proto;
+ break;
+ case htons(ETH_P_PPP_SES):
+- proto = nf_flow_pppoe_proto(skb);
++ if (!nf_flow_pppoe_proto(skb, &proto))
++ return NF_ACCEPT;
+ break;
+ default:
+ proto = skb->protocol;
+--- a/net/netfilter/nf_flow_table_ip.c
++++ b/net/netfilter/nf_flow_table_ip.c
+@@ -246,10 +246,11 @@ static unsigned int nf_flow_xmit_xfrm(st
+ return NF_STOLEN;
+ }
+
+-static bool nf_flow_skb_encap_protocol(const struct sk_buff *skb, __be16 proto,
++static bool nf_flow_skb_encap_protocol(struct sk_buff *skb, __be16 proto,
+ u32 *offset)
+ {
+ struct vlan_ethhdr *veth;
++ __be16 inner_proto;
+
+ switch (skb->protocol) {
+ case htons(ETH_P_8021Q):
+@@ -260,7 +261,8 @@ static bool nf_flow_skb_encap_protocol(c
+ }
+ break;
+ case htons(ETH_P_PPP_SES):
+- if (nf_flow_pppoe_proto(skb) == proto) {
++ if (nf_flow_pppoe_proto(skb, &inner_proto) &&
++ inner_proto == proto) {
+ *offset += PPPOE_SES_HLEN;
+ return true;
+ }
+@@ -289,7 +291,7 @@ static void nf_flow_encap_pop(struct sk_
+ skb_reset_network_header(skb);
+ break;
+ case htons(ETH_P_PPP_SES):
+- skb->protocol = nf_flow_pppoe_proto(skb);
++ skb->protocol = __nf_flow_pppoe_proto(skb);
+ skb_pull(skb, PPPOE_SES_HLEN);
+ skb_reset_network_header(skb);
+ break;
--- /dev/null
+From: Pablo Neira Ayuso <pablo@netfilter.org>
+Date: Thu, 11 Apr 2024 13:29:00 +0200
+Subject: [PATCH] netfilter: flowtable: incorrect pppoe tuple
+
+pppoe traffic reaching ingress path does not match the flowtable entry
+because the pppoe header is expected to be at the network header offset.
+This bug causes a mismatch in the flow table lookup, so pppoe packets
+enter the classical forwarding path.
+
+Fixes: 72efd585f714 ("netfilter: flowtable: add pppoe support")
+Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
+---
+
+--- a/net/netfilter/nf_flow_table_ip.c
++++ b/net/netfilter/nf_flow_table_ip.c
+@@ -156,7 +156,7 @@ static void nf_flow_tuple_encap(struct s
+ tuple->encap[i].proto = skb->protocol;
+ break;
+ case htons(ETH_P_PPP_SES):
+- phdr = (struct pppoe_hdr *)skb_mac_header(skb);
++ phdr = (struct pppoe_hdr *)skb_network_header(skb);
+ tuple->encap[i].id = ntohs(phdr->sid);
+ tuple->encap[i].proto = skb->protocol;
+ break;
--- /dev/null
+From 2203718c2f59ffdd6c78d54e5add594aebb4461e Mon Sep 17 00:00:00 2001
+From: Georgi Valkov <gvalkov@gmail.com>
+Date: Wed, 7 Jun 2023 15:56:59 +0200
+Subject: [PATCH 1/4] usbnet: ipheth: fix risk of NULL pointer deallocation
+
+The cleanup precedure in ipheth_probe will attempt to free a
+NULL pointer in dev->ctrl_buf if the memory allocation for
+this buffer is not successful. While kfree ignores NULL pointers,
+and the existing code is safe, it is a better design to rearrange
+the goto labels and avoid this.
+
+Signed-off-by: Georgi Valkov <gvalkov@gmail.com>
+Signed-off-by: Foster Snowhill <forst@pen.gy>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/usb/ipheth.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/net/usb/ipheth.c
++++ b/drivers/net/usb/ipheth.c
+@@ -510,8 +510,8 @@ err_register_netdev:
+ ipheth_free_urbs(dev);
+ err_alloc_urbs:
+ err_get_macaddr:
+-err_alloc_ctrl_buf:
+ kfree(dev->ctrl_buf);
++err_alloc_ctrl_buf:
+ err_endpoints:
+ free_netdev(netdev);
+ return retval;
--- /dev/null
+From 3e65efcca87a9bb5f3b864e0a43d167bc0a8688c Mon Sep 17 00:00:00 2001
+From: Foster Snowhill <forst@pen.gy>
+Date: Wed, 7 Jun 2023 15:57:00 +0200
+Subject: [PATCH 2/4] usbnet: ipheth: transmit URBs without trailing padding
+
+The behaviour of the official iOS tethering driver on macOS is to not
+transmit any trailing padding at the end of URBs. This is applicable
+to both NCM and legacy modes, including older devices.
+
+Adapt the driver to not include trailing padding in TX URBs, matching
+the behaviour of the official macOS driver.
+
+Signed-off-by: Foster Snowhill <forst@pen.gy>
+Tested-by: Georgi Valkov <gvalkov@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/usb/ipheth.c | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+--- a/drivers/net/usb/ipheth.c
++++ b/drivers/net/usb/ipheth.c
+@@ -373,12 +373,10 @@ static netdev_tx_t ipheth_tx(struct sk_b
+ }
+
+ memcpy(dev->tx_buf, skb->data, skb->len);
+- if (skb->len < IPHETH_BUF_SIZE)
+- memset(dev->tx_buf + skb->len, 0, IPHETH_BUF_SIZE - skb->len);
+
+ usb_fill_bulk_urb(dev->tx_urb, udev,
+ usb_sndbulkpipe(udev, dev->bulk_out),
+- dev->tx_buf, IPHETH_BUF_SIZE,
++ dev->tx_buf, skb->len,
+ ipheth_sndbulk_callback,
+ dev);
+ dev->tx_urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP;
--- /dev/null
+From a2d274c62e44b1995c170595db3865c6fe701226 Mon Sep 17 00:00:00 2001
+From: Foster Snowhill <forst@pen.gy>
+Date: Wed, 7 Jun 2023 15:57:01 +0200
+Subject: [PATCH 3/4] usbnet: ipheth: add CDC NCM support
+
+Recent iOS releases support CDC NCM encapsulation on RX. This mode is
+the default on macOS and Windows. In this mode, an iOS device may include
+one or more Ethernet frames inside a single URB.
+
+Freshly booted iOS devices start in legacy mode, but are put into
+NCM mode by the official Apple driver. When reconnecting such a device
+from a macOS/Windows machine to a Linux host, the device stays in
+NCM mode, making it unusable with the legacy ipheth driver code.
+
+To correctly support such a device, the driver has to either support
+the NCM mode too, or put the device back into legacy mode.
+
+To match the behaviour of the macOS/Windows driver, and since there
+is no documented control command to revert to legacy mode, implement
+NCM support. The device is attempted to be put into NCM mode by default,
+and falls back to legacy mode if the attempt fails.
+
+Signed-off-by: Foster Snowhill <forst@pen.gy>
+Tested-by: Georgi Valkov <gvalkov@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/usb/ipheth.c | 180 +++++++++++++++++++++++++++++++++------
+ 1 file changed, 155 insertions(+), 25 deletions(-)
+
+--- a/drivers/net/usb/ipheth.c
++++ b/drivers/net/usb/ipheth.c
+@@ -52,6 +52,7 @@
+ #include <linux/ethtool.h>
+ #include <linux/usb.h>
+ #include <linux/workqueue.h>
++#include <linux/usb/cdc.h>
+
+ #define USB_VENDOR_APPLE 0x05ac
+
+@@ -59,8 +60,12 @@
+ #define IPHETH_USBINTF_SUBCLASS 253
+ #define IPHETH_USBINTF_PROTO 1
+
+-#define IPHETH_BUF_SIZE 1514
+ #define IPHETH_IP_ALIGN 2 /* padding at front of URB */
++#define IPHETH_NCM_HEADER_SIZE (12 + 96) /* NCMH + NCM0 */
++#define IPHETH_TX_BUF_SIZE ETH_FRAME_LEN
++#define IPHETH_RX_BUF_SIZE_LEGACY (IPHETH_IP_ALIGN + ETH_FRAME_LEN)
++#define IPHETH_RX_BUF_SIZE_NCM 65536
++
+ #define IPHETH_TX_TIMEOUT (5 * HZ)
+
+ #define IPHETH_INTFNUM 2
+@@ -71,6 +76,7 @@
+ #define IPHETH_CTRL_TIMEOUT (5 * HZ)
+
+ #define IPHETH_CMD_GET_MACADDR 0x00
++#define IPHETH_CMD_ENABLE_NCM 0x04
+ #define IPHETH_CMD_CARRIER_CHECK 0x45
+
+ #define IPHETH_CARRIER_CHECK_TIMEOUT round_jiffies_relative(1 * HZ)
+@@ -97,6 +103,8 @@ struct ipheth_device {
+ u8 bulk_out;
+ struct delayed_work carrier_work;
+ bool confirmed_pairing;
++ int (*rcvbulk_callback)(struct urb *urb);
++ size_t rx_buf_len;
+ };
+
+ static int ipheth_rx_submit(struct ipheth_device *dev, gfp_t mem_flags);
+@@ -116,12 +124,12 @@ static int ipheth_alloc_urbs(struct iphe
+ if (rx_urb == NULL)
+ goto free_tx_urb;
+
+- tx_buf = usb_alloc_coherent(iphone->udev, IPHETH_BUF_SIZE,
++ tx_buf = usb_alloc_coherent(iphone->udev, IPHETH_TX_BUF_SIZE,
+ GFP_KERNEL, &tx_urb->transfer_dma);
+ if (tx_buf == NULL)
+ goto free_rx_urb;
+
+- rx_buf = usb_alloc_coherent(iphone->udev, IPHETH_BUF_SIZE + IPHETH_IP_ALIGN,
++ rx_buf = usb_alloc_coherent(iphone->udev, iphone->rx_buf_len,
+ GFP_KERNEL, &rx_urb->transfer_dma);
+ if (rx_buf == NULL)
+ goto free_tx_buf;
+@@ -134,7 +142,7 @@ static int ipheth_alloc_urbs(struct iphe
+ return 0;
+
+ free_tx_buf:
+- usb_free_coherent(iphone->udev, IPHETH_BUF_SIZE, tx_buf,
++ usb_free_coherent(iphone->udev, IPHETH_TX_BUF_SIZE, tx_buf,
+ tx_urb->transfer_dma);
+ free_rx_urb:
+ usb_free_urb(rx_urb);
+@@ -146,9 +154,9 @@ error_nomem:
+
+ static void ipheth_free_urbs(struct ipheth_device *iphone)
+ {
+- usb_free_coherent(iphone->udev, IPHETH_BUF_SIZE + IPHETH_IP_ALIGN, iphone->rx_buf,
++ usb_free_coherent(iphone->udev, iphone->rx_buf_len, iphone->rx_buf,
+ iphone->rx_urb->transfer_dma);
+- usb_free_coherent(iphone->udev, IPHETH_BUF_SIZE, iphone->tx_buf,
++ usb_free_coherent(iphone->udev, IPHETH_TX_BUF_SIZE, iphone->tx_buf,
+ iphone->tx_urb->transfer_dma);
+ usb_free_urb(iphone->rx_urb);
+ usb_free_urb(iphone->tx_urb);
+@@ -160,15 +168,106 @@ static void ipheth_kill_urbs(struct iphe
+ usb_kill_urb(dev->rx_urb);
+ }
+
+-static void ipheth_rcvbulk_callback(struct urb *urb)
++static int ipheth_consume_skb(char *buf, int len, struct ipheth_device *dev)
+ {
+- struct ipheth_device *dev;
+ struct sk_buff *skb;
+- int status;
++
++ skb = dev_alloc_skb(len);
++ if (!skb) {
++ dev->net->stats.rx_dropped++;
++ return -ENOMEM;
++ }
++
++ skb_put_data(skb, buf, len);
++ skb->dev = dev->net;
++ skb->protocol = eth_type_trans(skb, dev->net);
++
++ dev->net->stats.rx_packets++;
++ dev->net->stats.rx_bytes += len;
++ netif_rx(skb);
++
++ return 0;
++}
++
++static int ipheth_rcvbulk_callback_legacy(struct urb *urb)
++{
++ struct ipheth_device *dev;
++ char *buf;
++ int len;
++
++ dev = urb->context;
++
++ if (urb->actual_length <= IPHETH_IP_ALIGN) {
++ dev->net->stats.rx_length_errors++;
++ return -EINVAL;
++ }
++ len = urb->actual_length - IPHETH_IP_ALIGN;
++ buf = urb->transfer_buffer + IPHETH_IP_ALIGN;
++
++ return ipheth_consume_skb(buf, len, dev);
++}
++
++static int ipheth_rcvbulk_callback_ncm(struct urb *urb)
++{
++ struct usb_cdc_ncm_nth16 *ncmh;
++ struct usb_cdc_ncm_ndp16 *ncm0;
++ struct usb_cdc_ncm_dpe16 *dpe;
++ struct ipheth_device *dev;
++ int retval = -EINVAL;
+ char *buf;
+ int len;
+
+ dev = urb->context;
++
++ if (urb->actual_length < IPHETH_NCM_HEADER_SIZE) {
++ dev->net->stats.rx_length_errors++;
++ return retval;
++ }
++
++ ncmh = urb->transfer_buffer;
++ if (ncmh->dwSignature != cpu_to_le32(USB_CDC_NCM_NTH16_SIGN) ||
++ le16_to_cpu(ncmh->wNdpIndex) >= urb->actual_length) {
++ dev->net->stats.rx_errors++;
++ return retval;
++ }
++
++ ncm0 = urb->transfer_buffer + le16_to_cpu(ncmh->wNdpIndex);
++ if (ncm0->dwSignature != cpu_to_le32(USB_CDC_NCM_NDP16_NOCRC_SIGN) ||
++ le16_to_cpu(ncmh->wHeaderLength) + le16_to_cpu(ncm0->wLength) >=
++ urb->actual_length) {
++ dev->net->stats.rx_errors++;
++ return retval;
++ }
++
++ dpe = ncm0->dpe16;
++ while (le16_to_cpu(dpe->wDatagramIndex) != 0 &&
++ le16_to_cpu(dpe->wDatagramLength) != 0) {
++ if (le16_to_cpu(dpe->wDatagramIndex) >= urb->actual_length ||
++ le16_to_cpu(dpe->wDatagramIndex) +
++ le16_to_cpu(dpe->wDatagramLength) > urb->actual_length) {
++ dev->net->stats.rx_length_errors++;
++ return retval;
++ }
++
++ buf = urb->transfer_buffer + le16_to_cpu(dpe->wDatagramIndex);
++ len = le16_to_cpu(dpe->wDatagramLength);
++
++ retval = ipheth_consume_skb(buf, len, dev);
++ if (retval != 0)
++ return retval;
++
++ dpe++;
++ }
++
++ return 0;
++}
++
++static void ipheth_rcvbulk_callback(struct urb *urb)
++{
++ struct ipheth_device *dev;
++ int retval, status;
++
++ dev = urb->context;
+ if (dev == NULL)
+ return;
+
+@@ -191,25 +290,27 @@ static void ipheth_rcvbulk_callback(stru
+ dev->net->stats.rx_length_errors++;
+ return;
+ }
+- len = urb->actual_length - IPHETH_IP_ALIGN;
+- buf = urb->transfer_buffer + IPHETH_IP_ALIGN;
+
+- skb = dev_alloc_skb(len);
+- if (!skb) {
+- dev_err(&dev->intf->dev, "%s: dev_alloc_skb: -ENOMEM\n",
+- __func__);
+- dev->net->stats.rx_dropped++;
++ /* RX URBs starting with 0x00 0x01 do not encapsulate Ethernet frames,
++ * but rather are control frames. Their purpose is not documented, and
++ * they don't affect driver functionality, okay to drop them.
++ * There is usually just one 4-byte control frame as the very first
++ * URB received from the bulk IN endpoint.
++ */
++ if (unlikely
++ (((char *)urb->transfer_buffer)[0] == 0 &&
++ ((char *)urb->transfer_buffer)[1] == 1))
++ goto rx_submit;
++
++ retval = dev->rcvbulk_callback(urb);
++ if (retval != 0) {
++ dev_err(&dev->intf->dev, "%s: callback retval: %d\n",
++ __func__, retval);
+ return;
+ }
+
+- skb_put_data(skb, buf, len);
+- skb->dev = dev->net;
+- skb->protocol = eth_type_trans(skb, dev->net);
+-
+- dev->net->stats.rx_packets++;
+- dev->net->stats.rx_bytes += len;
++rx_submit:
+ dev->confirmed_pairing = true;
+- netif_rx(skb);
+ ipheth_rx_submit(dev, GFP_ATOMIC);
+ }
+
+@@ -310,6 +411,27 @@ static int ipheth_get_macaddr(struct iph
+ return retval;
+ }
+
++static int ipheth_enable_ncm(struct ipheth_device *dev)
++{
++ struct usb_device *udev = dev->udev;
++ int retval;
++
++ retval = usb_control_msg(udev,
++ usb_sndctrlpipe(udev, IPHETH_CTRL_ENDP),
++ IPHETH_CMD_ENABLE_NCM, /* request */
++ 0x41, /* request type */
++ 0x00, /* value */
++ 0x02, /* index */
++ NULL,
++ 0,
++ IPHETH_CTRL_TIMEOUT);
++
++ dev_info(&dev->intf->dev, "%s: usb_control_msg: %d\n",
++ __func__, retval);
++
++ return retval;
++}
++
+ static int ipheth_rx_submit(struct ipheth_device *dev, gfp_t mem_flags)
+ {
+ struct usb_device *udev = dev->udev;
+@@ -317,7 +439,7 @@ static int ipheth_rx_submit(struct iphet
+
+ usb_fill_bulk_urb(dev->rx_urb, udev,
+ usb_rcvbulkpipe(udev, dev->bulk_in),
+- dev->rx_buf, IPHETH_BUF_SIZE + IPHETH_IP_ALIGN,
++ dev->rx_buf, dev->rx_buf_len,
+ ipheth_rcvbulk_callback,
+ dev);
+ dev->rx_urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP;
+@@ -365,7 +487,7 @@ static netdev_tx_t ipheth_tx(struct sk_b
+ int retval;
+
+ /* Paranoid */
+- if (skb->len > IPHETH_BUF_SIZE) {
++ if (skb->len > IPHETH_TX_BUF_SIZE) {
+ WARN(1, "%s: skb too large: %d bytes\n", __func__, skb->len);
+ dev->net->stats.tx_dropped++;
+ dev_kfree_skb_any(skb);
+@@ -448,6 +570,8 @@ static int ipheth_probe(struct usb_inter
+ dev->net = netdev;
+ dev->intf = intf;
+ dev->confirmed_pairing = false;
++ dev->rx_buf_len = IPHETH_RX_BUF_SIZE_LEGACY;
++ dev->rcvbulk_callback = ipheth_rcvbulk_callback_legacy;
+ /* Set up endpoints */
+ hintf = usb_altnum_to_altsetting(intf, IPHETH_ALT_INTFNUM);
+ if (hintf == NULL) {
+@@ -479,6 +603,12 @@ static int ipheth_probe(struct usb_inter
+ if (retval)
+ goto err_get_macaddr;
+
++ retval = ipheth_enable_ncm(dev);
++ if (!retval) {
++ dev->rx_buf_len = IPHETH_RX_BUF_SIZE_NCM;
++ dev->rcvbulk_callback = ipheth_rcvbulk_callback_ncm;
++ }
++
+ INIT_DELAYED_WORK(&dev->carrier_work, ipheth_carrier_check_work);
+
+ retval = ipheth_alloc_urbs(dev);
--- /dev/null
+From 0c6e9d32ef0ccfcf2d875cbcff23bf345a54d585 Mon Sep 17 00:00:00 2001
+From: Foster Snowhill <forst@pen.gy>
+Date: Wed, 7 Jun 2023 15:57:02 +0200
+Subject: [PATCH 4/4] usbnet: ipheth: update Kconfig description
+
+This module has for a long time not been limited to iPhone <= 3GS.
+Update description to match the actual state of the driver.
+
+Remove dead link from 2010, instead reference an existing userspace
+iOS device pairing implementation as part of libimobiledevice.
+
+Signed-off-by: Foster Snowhill <forst@pen.gy>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/usb/Kconfig | 10 ++++------
+ 1 file changed, 4 insertions(+), 6 deletions(-)
+
+--- a/drivers/net/usb/Kconfig
++++ b/drivers/net/usb/Kconfig
+@@ -582,12 +582,10 @@ config USB_IPHETH
+ default n
+ help
+ Module used to share Internet connection (tethering) from your
+- iPhone (Original, 3G and 3GS) to your system.
+- Note that you need userspace libraries and programs that are needed
+- to pair your device with your system and that understand the iPhone
+- protocol.
+-
+- For more information: http://giagio.com/wiki/moin.cgi/iPhoneEthernetDriver
++ iPhone to your system.
++ Note that you need a corresponding userspace library/program
++ to pair your device with your system, for example usbmuxd
++ <https://github.com/libimobiledevice/usbmuxd>.
+
+ config USB_SIERRA_NET
+ tristate "USB-to-WWAN Driver for Sierra Wireless modems"
--- /dev/null
+From 773bbe10449731c9525457873e0c2342e5cf883b Mon Sep 17 00:00:00 2001
+From: Michael Walle <michael@walle.cc>
+Date: Thu, 11 Aug 2022 00:06:53 +0200
+Subject: [PATCH] mtd: spi-nor: add generic flash driver
+
+Our SFDP parsing is everything we need to support all basic operations
+of a flash device. If the flash isn't found in our in-kernel flash
+database, gracefully fall back to a driver described solely by its SFDP
+tables.
+
+Signed-off-by: Michael Walle <michael@walle.cc>
+Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
+Tested-by: Tudor Ambarus <tudor.ambarus@microchip.com>
+Reviewed-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
+Link: https://lore.kernel.org/r/20220810220654.1297699-7-michael@walle.cc
+---
+ drivers/mtd/spi-nor/core.c | 26 ++++++++++++++++++++++++--
+ drivers/mtd/spi-nor/core.h | 1 +
+ drivers/mtd/spi-nor/sfdp.c | 27 +++++++++++++++++++++++++++
+ 3 files changed, 52 insertions(+), 2 deletions(-)
+
+--- a/drivers/mtd/spi-nor/core.c
++++ b/drivers/mtd/spi-nor/core.c
+@@ -1636,6 +1636,16 @@ static const struct spi_nor_manufacturer
+ &spi_nor_xmc,
+ };
+
++static const struct flash_info spi_nor_generic_flash = {
++ .name = "spi-nor-generic",
++ /*
++ * JESD216 rev A doesn't specify the page size, therefore we need a
++ * sane default.
++ */
++ .page_size = 256,
++ .parse_sfdp = true,
++};
++
+ static const struct flash_info *spi_nor_match_id(struct spi_nor *nor,
+ const u8 *id)
+ {
+@@ -1669,6 +1679,14 @@ static const struct flash_info *spi_nor_
+ }
+
+ info = spi_nor_match_id(nor, id);
++
++ /* Fallback to a generic flash described only by its SFDP data. */
++ if (!info) {
++ ret = spi_nor_check_sfdp_signature(nor);
++ if (!ret)
++ info = &spi_nor_generic_flash;
++ }
++
+ if (!info) {
+ dev_err(nor->dev, "unrecognized JEDEC id bytes: %*ph\n",
+ SPI_NOR_MAX_ID_LEN, id);
+@@ -2105,8 +2123,12 @@ static int spi_nor_select_pp(struct spi_
+ * spi_nor_select_uniform_erase() - select optimum uniform erase type
+ * @map: the erase map of the SPI NOR
+ * @wanted_size: the erase type size to search for. Contains the value of
+- * info->sector_size or of the "small sector" size in case
+- * CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is defined.
++ * info->sector_size, the "small sector" size in case
++ * CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is defined or 0 if
++ * there is no information about the sector size. The
++ * latter is the case if the flash parameters are parsed
++ * solely by SFDP, then the largest supported erase type
++ * is selected.
+ *
+ * Once the optimum uniform sector erase command is found, disable all the
+ * other.
+--- a/drivers/mtd/spi-nor/core.h
++++ b/drivers/mtd/spi-nor/core.h
+@@ -708,6 +708,8 @@ int spi_nor_controller_ops_read_reg(stru
+ int spi_nor_controller_ops_write_reg(struct spi_nor *nor, u8 opcode,
+ const u8 *buf, size_t len);
+
++int spi_nor_check_sfdp_signature(struct spi_nor *nor);
++
+ static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
+ {
+ return container_of(mtd, struct spi_nor, mtd);
+--- a/drivers/mtd/spi-nor/sfdp.c
++++ b/drivers/mtd/spi-nor/sfdp.c
+@@ -1250,6 +1250,33 @@ static void spi_nor_post_sfdp_fixups(str
+ }
+
+ /**
++ * spi_nor_check_sfdp_signature() - check for a valid SFDP signature
++ * @nor: pointer to a 'struct spi_nor'
++ *
++ * Used to detect if the flash supports the RDSFDP command as well as the
++ * presence of a valid SFDP table.
++ *
++ * Return: 0 on success, -errno otherwise.
++ */
++int spi_nor_check_sfdp_signature(struct spi_nor *nor)
++{
++ u32 signature;
++ int err;
++
++ /* Get the SFDP header. */
++ err = spi_nor_read_sfdp_dma_unsafe(nor, 0, sizeof(signature),
++ &signature);
++ if (err < 0)
++ return err;
++
++ /* Check the SFDP signature. */
++ if (le32_to_cpu(signature) != SFDP_SIGNATURE)
++ return -EINVAL;
++
++ return 0;
++}
++
++/**
+ * spi_nor_parse_sfdp() - parse the Serial Flash Discoverable Parameters.
+ * @nor: pointer to a 'struct spi_nor'
+ *
--- /dev/null
+From: Pablo Neira Ayuso <pablo@netfilter.org>
+Date: Thu, 11 Apr 2024 13:28:59 +0200
+Subject: [PATCH] netfilter: flowtable: validate pppoe header
+
+Ensure there is sufficient room to access the protocol field of the
+PPPoe header. Validate it once before the flowtable lookup, then use a
+helper function to access protocol field.
+
+Reported-by: syzbot+b6f07e1c07ef40199081@syzkaller.appspotmail.com
+Fixes: 72efd585f714 ("netfilter: flowtable: add pppoe support")
+Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
+---
+
+--- a/include/net/netfilter/nf_flow_table.h
++++ b/include/net/netfilter/nf_flow_table.h
+@@ -335,7 +335,7 @@ int nf_flow_rule_route_ipv6(struct net *
+ int nf_flow_table_offload_init(void);
+ void nf_flow_table_offload_exit(void);
+
+-static inline __be16 nf_flow_pppoe_proto(const struct sk_buff *skb)
++static inline __be16 __nf_flow_pppoe_proto(const struct sk_buff *skb)
+ {
+ __be16 proto;
+
+@@ -351,6 +351,16 @@ static inline __be16 nf_flow_pppoe_proto
+ return 0;
+ }
+
++static inline bool nf_flow_pppoe_proto(struct sk_buff *skb, __be16 *inner_proto)
++{
++ if (!pskb_may_pull(skb, PPPOE_SES_HLEN))
++ return false;
++
++ *inner_proto = __nf_flow_pppoe_proto(skb);
++
++ return true;
++}
++
+ #define NF_FLOW_TABLE_STAT_INC(net, count) __this_cpu_inc((net)->ft.stat->count)
+ #define NF_FLOW_TABLE_STAT_DEC(net, count) __this_cpu_dec((net)->ft.stat->count)
+ #define NF_FLOW_TABLE_STAT_INC_ATOMIC(net, count) \
+--- a/net/netfilter/nf_flow_table_inet.c
++++ b/net/netfilter/nf_flow_table_inet.c
+@@ -21,7 +21,8 @@ nf_flow_offload_inet_hook(void *priv, st
+ proto = veth->h_vlan_encapsulated_proto;
+ break;
+ case htons(ETH_P_PPP_SES):
+- proto = nf_flow_pppoe_proto(skb);
++ if (!nf_flow_pppoe_proto(skb, &proto))
++ return NF_ACCEPT;
+ break;
+ default:
+ proto = skb->protocol;
+--- a/net/netfilter/nf_flow_table_ip.c
++++ b/net/netfilter/nf_flow_table_ip.c
+@@ -267,10 +267,11 @@ static unsigned int nf_flow_xmit_xfrm(st
+ return NF_STOLEN;
+ }
+
+-static bool nf_flow_skb_encap_protocol(const struct sk_buff *skb, __be16 proto,
++static bool nf_flow_skb_encap_protocol(struct sk_buff *skb, __be16 proto,
+ u32 *offset)
+ {
+ struct vlan_ethhdr *veth;
++ __be16 inner_proto;
+
+ switch (skb->protocol) {
+ case htons(ETH_P_8021Q):
+@@ -281,7 +282,8 @@ static bool nf_flow_skb_encap_protocol(c
+ }
+ break;
+ case htons(ETH_P_PPP_SES):
+- if (nf_flow_pppoe_proto(skb) == proto) {
++ if (nf_flow_pppoe_proto(skb, &inner_proto) &&
++ inner_proto == proto) {
+ *offset += PPPOE_SES_HLEN;
+ return true;
+ }
+@@ -310,7 +312,7 @@ static void nf_flow_encap_pop(struct sk_
+ skb_reset_network_header(skb);
+ break;
+ case htons(ETH_P_PPP_SES):
+- skb->protocol = nf_flow_pppoe_proto(skb);
++ skb->protocol = __nf_flow_pppoe_proto(skb);
+ skb_pull(skb, PPPOE_SES_HLEN);
+ skb_reset_network_header(skb);
+ break;
--- /dev/null
+From: Pablo Neira Ayuso <pablo@netfilter.org>
+Date: Thu, 11 Apr 2024 13:29:00 +0200
+Subject: [PATCH] netfilter: flowtable: incorrect pppoe tuple
+
+pppoe traffic reaching ingress path does not match the flowtable entry
+because the pppoe header is expected to be at the network header offset.
+This bug causes a mismatch in the flow table lookup, so pppoe packets
+enter the classical forwarding path.
+
+Fixes: 72efd585f714 ("netfilter: flowtable: add pppoe support")
+Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
+---
+
+--- a/net/netfilter/nf_flow_table_ip.c
++++ b/net/netfilter/nf_flow_table_ip.c
+@@ -156,7 +156,7 @@ static void nf_flow_tuple_encap(struct s
+ tuple->encap[i].proto = skb->protocol;
+ break;
+ case htons(ETH_P_PPP_SES):
+- phdr = (struct pppoe_hdr *)skb_mac_header(skb);
++ phdr = (struct pppoe_hdr *)skb_network_header(skb);
+ tuple->encap[i].id = ntohs(phdr->sid);
+ tuple->encap[i].proto = skb->protocol;
+ break;
--- /dev/null
+From f13b2b33c7674fa0988dfaa9adb95d7d912b489f Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Wed, 10 Apr 2024 20:42:38 +0100
+Subject: [PATCH 1/2] net: dsa: introduce dsa_phylink_to_port()
+
+We convert from a phylink_config struct to a dsa_port struct in many
+places, let's provide a helper for this.
+
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
+Link: https://lore.kernel.org/r/E1rudqA-006K9B-85@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ include/net/dsa.h | 6 ++++++
+ net/dsa/port.c | 12 ++++++------
+ 2 files changed, 12 insertions(+), 6 deletions(-)
+
+--- a/include/net/dsa.h
++++ b/include/net/dsa.h
+@@ -337,6 +337,12 @@ struct dsa_port {
+ struct list_head vlans;
+ };
+
++static inline struct dsa_port *
++dsa_phylink_to_port(struct phylink_config *config)
++{
++ return container_of(config, struct dsa_port, pl_config);
++}
++
+ /* TODO: ideally DSA ports would have a single dp->link_dp member,
+ * and no dst->rtable nor this struct dsa_link would be needed,
+ * but this would require some more complex tree walking,
+--- a/net/dsa/port.c
++++ b/net/dsa/port.c
+@@ -1552,7 +1552,7 @@ static void dsa_port_phylink_validate(st
+ unsigned long *supported,
+ struct phylink_link_state *state)
+ {
+- struct dsa_port *dp = container_of(config, struct dsa_port, pl_config);
++ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct dsa_switch *ds = dp->ds;
+
+ if (!ds->ops->phylink_validate) {
+@@ -1567,7 +1567,7 @@ static void dsa_port_phylink_validate(st
+ static void dsa_port_phylink_mac_pcs_get_state(struct phylink_config *config,
+ struct phylink_link_state *state)
+ {
+- struct dsa_port *dp = container_of(config, struct dsa_port, pl_config);
++ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct dsa_switch *ds = dp->ds;
+ int err;
+
+@@ -1589,7 +1589,7 @@ static struct phylink_pcs *
+ dsa_port_phylink_mac_select_pcs(struct phylink_config *config,
+ phy_interface_t interface)
+ {
+- struct dsa_port *dp = container_of(config, struct dsa_port, pl_config);
++ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct phylink_pcs *pcs = ERR_PTR(-EOPNOTSUPP);
+ struct dsa_switch *ds = dp->ds;
+
+@@ -1603,7 +1603,7 @@ static void dsa_port_phylink_mac_config(
+ unsigned int mode,
+ const struct phylink_link_state *state)
+ {
+- struct dsa_port *dp = container_of(config, struct dsa_port, pl_config);
++ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct dsa_switch *ds = dp->ds;
+
+ if (!ds->ops->phylink_mac_config)
+@@ -1614,7 +1614,7 @@ static void dsa_port_phylink_mac_config(
+
+ static void dsa_port_phylink_mac_an_restart(struct phylink_config *config)
+ {
+- struct dsa_port *dp = container_of(config, struct dsa_port, pl_config);
++ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct dsa_switch *ds = dp->ds;
+
+ if (!ds->ops->phylink_mac_an_restart)
+@@ -1627,7 +1627,7 @@ static void dsa_port_phylink_mac_link_do
+ unsigned int mode,
+ phy_interface_t interface)
+ {
+- struct dsa_port *dp = container_of(config, struct dsa_port, pl_config);
++ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct phy_device *phydev = NULL;
+ struct dsa_switch *ds = dp->ds;
+
+@@ -1650,7 +1650,7 @@ static void dsa_port_phylink_mac_link_up
+ int speed, int duplex,
+ bool tx_pause, bool rx_pause)
+ {
+- struct dsa_port *dp = container_of(config, struct dsa_port, pl_config);
++ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct dsa_switch *ds = dp->ds;
+
+ if (!ds->ops->phylink_mac_link_up) {
--- /dev/null
+From c22d8240fcd73a1c3ec8dcb055bd583fb970c375 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Wed, 10 Apr 2024 20:42:43 +0100
+Subject: [PATCH 2/2] net: dsa: allow DSA switch drivers to provide their own
+ phylink mac ops
+
+Rather than having a shim for each and every phylink MAC operation,
+allow DSA switch drivers to provide their own ops structure. When a
+DSA driver provides the phylink MAC operations, the shimmed ops must
+not be provided, so fail an attempt to register a switch with both
+the phylink_mac_ops in struct dsa_switch and the phylink_mac_*
+operations populated in dsa_switch_ops populated.
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
+Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
+Link: https://lore.kernel.org/r/E1rudqF-006K9H-Cc@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ include/net/dsa.h | 5 +++++
+ net/dsa/dsa.c | 11 +++++++++++
+ net/dsa/port.c | 26 ++++++++++++++++++++------
+ 3 files changed, 36 insertions(+), 6 deletions(-)
+
+--- a/include/net/dsa.h
++++ b/include/net/dsa.h
+@@ -468,6 +468,11 @@ struct dsa_switch {
+ const struct dsa_switch_ops *ops;
+
+ /*
++ * Allow a DSA switch driver to override the phylink MAC ops
++ */
++ const struct phylink_mac_ops *phylink_mac_ops;
++
++ /*
+ * Slave mii_bus and devices for the individual ports.
+ */
+ u32 phys_mii_mask;
+--- a/net/dsa/port.c
++++ b/net/dsa/port.c
+@@ -1675,6 +1675,7 @@ static const struct phylink_mac_ops dsa_
+
+ int dsa_port_phylink_create(struct dsa_port *dp)
+ {
++ const struct phylink_mac_ops *mac_ops;
+ struct dsa_switch *ds = dp->ds;
+ phy_interface_t mode;
+ struct phylink *pl;
+@@ -1694,8 +1695,12 @@ int dsa_port_phylink_create(struct dsa_p
+ if (ds->ops->phylink_get_caps)
+ ds->ops->phylink_get_caps(ds, dp->index, &dp->pl_config);
+
+- pl = phylink_create(&dp->pl_config, of_fwnode_handle(dp->dn),
+- mode, &dsa_port_phylink_mac_ops);
++ mac_ops = &dsa_port_phylink_mac_ops;
++ if (ds->phylink_mac_ops)
++ mac_ops = ds->phylink_mac_ops;
++
++ pl = phylink_create(&dp->pl_config, of_fwnode_handle(dp->dn), mode,
++ mac_ops);
+ if (IS_ERR(pl)) {
+ pr_err("error creating PHYLINK: %ld\n", PTR_ERR(pl));
+ return PTR_ERR(pl);
+@@ -1961,12 +1966,23 @@ static void dsa_shared_port_validate_of(
+ dn, dsa_port_is_cpu(dp) ? "CPU" : "DSA", dp->index);
+ }
+
++static void dsa_shared_port_link_down(struct dsa_port *dp)
++{
++ struct dsa_switch *ds = dp->ds;
++
++ if (ds->phylink_mac_ops && ds->phylink_mac_ops->mac_link_down)
++ ds->phylink_mac_ops->mac_link_down(&dp->pl_config, MLO_AN_FIXED,
++ PHY_INTERFACE_MODE_NA);
++ else if (ds->ops->phylink_mac_link_down)
++ ds->ops->phylink_mac_link_down(ds, dp->index, MLO_AN_FIXED,
++ PHY_INTERFACE_MODE_NA);
++}
++
+ int dsa_shared_port_link_register_of(struct dsa_port *dp)
+ {
+ struct dsa_switch *ds = dp->ds;
+ bool missing_link_description;
+ bool missing_phy_mode;
+- int port = dp->index;
+
+ dsa_shared_port_validate_of(dp, &missing_phy_mode,
+ &missing_link_description);
+@@ -1982,9 +1998,7 @@ int dsa_shared_port_link_register_of(str
+ "Skipping phylink registration for %s port %d\n",
+ dsa_port_is_cpu(dp) ? "CPU" : "DSA", dp->index);
+ } else {
+- if (ds->ops->phylink_mac_link_down)
+- ds->ops->phylink_mac_link_down(ds, port,
+- MLO_AN_FIXED, PHY_INTERFACE_MODE_NA);
++ dsa_shared_port_link_down(dp);
+
+ return dsa_shared_port_phylink_register(dp);
+ }
+--- a/net/dsa/dsa2.c
++++ b/net/dsa/dsa2.c
+@@ -1736,6 +1736,15 @@ static int dsa_switch_probe(struct dsa_s
+ if (!ds->num_ports)
+ return -EINVAL;
+
++ if (ds->phylink_mac_ops) {
++ if (ds->ops->phylink_mac_select_pcs ||
++ ds->ops->phylink_mac_config ||
++ ds->ops->phylink_mac_link_down ||
++ ds->ops->phylink_mac_link_up ||
++ ds->ops->adjust_link)
++ return -EINVAL;
++ }
++
+ if (np) {
+ err = dsa_switch_parse_of(ds, np);
+ if (err)
--- /dev/null
+From ef972fc9f5743da589ce9546dd565d6c56e679b8 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 8 Apr 2024 10:08:53 +0300
+Subject: [PATCH 1/2] net: dsa: mt7530: fix enabling EEE on MT7531 switch on
+ all boards
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The commit 40b5d2f15c09 ("net: dsa: mt7530: Add support for EEE features")
+brought EEE support but did not enable EEE on MT7531 switch MACs. EEE is
+enabled on MT7531 switch MACs by pulling the LAN2LED0 pin low on the board
+(bootstrapping), unsetting the EEE_DIS bit on the trap register, or setting
+the internal EEE switch bit on the CORE_PLL_GROUP4 register. Thanks to
+SkyLake Huang (黃啟澤) from MediaTek for providing information on the
+internal EEE switch bit.
+
+There are existing boards that were not designed to pull the pin low.
+Because of that, the EEE status currently depends on the board design.
+
+The EEE_DIS bit on the trap pertains to the LAN2LED0 pin which is usually
+used to control an LED. Once the bit is unset, the pin will be low. That
+will make the active low LED turn on. The pin is controlled by the switch
+PHY. It seems that the PHY controls the pin in the way that it inverts the
+pin state. That means depending on the wiring of the LED connected to
+LAN2LED0 on the board, the LED may be on without an active link.
+
+To not cause this unwanted behaviour whilst enabling EEE on all boards, set
+the internal EEE switch bit on the CORE_PLL_GROUP4 register.
+
+My testing on MT7531 shows a certain amount of traffic loss when EEE is
+enabled. That said, I haven't come across a board that enables EEE. So
+enable EEE on the switch MACs but disable EEE advertisement on the switch
+PHYs. This way, we don't change the behaviour of the majority of the boards
+that have this switch. The mediatek-ge PHY driver already disables EEE
+advertisement on the switch PHYs but my testing shows that it is somehow
+enabled afterwards. Disabling EEE advertisement before the PHY driver
+initialises keeps it off.
+
+With this change, EEE can now be enabled using ethtool.
+
+Fixes: 40b5d2f15c09 ("net: dsa: mt7530: Add support for EEE features")
+Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 17 ++++++++++++-----
+ drivers/net/dsa/mt7530.h | 1 +
+ 2 files changed, 13 insertions(+), 5 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2496,18 +2496,25 @@ mt7531_setup(struct dsa_switch *ds)
+ mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
+ MT7531_GPIO0_INTERRUPT);
+
+- /* Enable PHY core PLL, since phy_device has not yet been created
+- * provided for phy_[read,write]_mmd_indirect is called, we provide
+- * our own mt7531_ind_mmd_phy_[read,write] to complete this
+- * function.
++ /* Enable Energy-Efficient Ethernet (EEE) and PHY core PLL, since
++ * phy_device has not yet been created provided for
++ * phy_[read,write]_mmd_indirect is called, we provide our own
++ * mt7531_ind_mmd_phy_[read,write] to complete this function.
+ */
+ val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR,
+ MDIO_MMD_VEND2, CORE_PLL_GROUP4);
+- val |= MT7531_PHY_PLL_BYPASS_MODE;
++ val |= MT7531_RG_SYSPLL_DMY2 | MT7531_PHY_PLL_BYPASS_MODE;
+ val &= ~MT7531_PHY_PLL_OFF;
+ mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2,
+ CORE_PLL_GROUP4, val);
+
++ /* Disable EEE advertisement on the switch PHYs. */
++ for (i = MT753X_CTRL_PHY_ADDR;
++ i < MT753X_CTRL_PHY_ADDR + MT7530_NUM_PHYS; i++) {
++ mt7531_ind_c45_phy_write(priv, i, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
++ 0);
++ }
++
+ mt7531_setup_common(ds);
+
+ /* Setup VLAN ID 0 for VLAN-unaware bridges */
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -616,6 +616,7 @@ enum mt7531_clk_skew {
+ #define RG_SYSPLL_DDSFBK_EN BIT(12)
+ #define RG_SYSPLL_BIAS_EN BIT(11)
+ #define RG_SYSPLL_BIAS_LPF_EN BIT(10)
++#define MT7531_RG_SYSPLL_DMY2 BIT(6)
+ #define MT7531_PHY_PLL_OFF BIT(5)
+ #define MT7531_PHY_PLL_BYPASS_MODE BIT(4)
+
--- /dev/null
+From b7427d66cb3d6dca5165de5f7d80d59f08c2795b Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Tue, 9 Apr 2024 18:01:14 +0300
+Subject: [PATCH 2/2] net: dsa: mt7530: trap link-local frames regardless of ST
+ Port State
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+In Clause 5 of IEEE Std 802-2014, two sublayers of the data link layer
+(DLL) of the Open Systems Interconnection basic reference model (OSI/RM)
+are described; the medium access control (MAC) and logical link control
+(LLC) sublayers. The MAC sublayer is the one facing the physical layer.
+
+In 8.2 of IEEE Std 802.1Q-2022, the Bridge architecture is described. A
+Bridge component comprises a MAC Relay Entity for interconnecting the Ports
+of the Bridge, at least two Ports, and higher layer entities with at least
+a Spanning Tree Protocol Entity included.
+
+Each Bridge Port also functions as an end station and shall provide the MAC
+Service to an LLC Entity. Each instance of the MAC Service is provided to a
+distinct LLC Entity that supports protocol identification, multiplexing,
+and demultiplexing, for protocol data unit (PDU) transmission and reception
+by one or more higher layer entities.
+
+It is described in 8.13.9 of IEEE Std 802.1Q-2022 that in a Bridge, the LLC
+Entity associated with each Bridge Port is modeled as being directly
+connected to the attached Local Area Network (LAN).
+
+On the switch with CPU port architecture, CPU port functions as Management
+Port, and the Management Port functionality is provided by software which
+functions as an end station. Software is connected to an IEEE 802 LAN that
+is wholly contained within the system that incorporates the Bridge.
+Software provides access to the LLC Entity associated with each Bridge Port
+by the value of the source port field on the special tag on the frame
+received by software.
+
+We call frames that carry control information to determine the active
+topology and current extent of each Virtual Local Area Network (VLAN),
+i.e., spanning tree or Shortest Path Bridging (SPB) and Multiple VLAN
+Registration Protocol Data Units (MVRPDUs), and frames from other link
+constrained protocols, such as Extensible Authentication Protocol over LAN
+(EAPOL) and Link Layer Discovery Protocol (LLDP), link-local frames. They
+are not forwarded by a Bridge. Permanently configured entries in the
+filtering database (FDB) ensure that such frames are discarded by the
+Forwarding Process. In 8.6.3 of IEEE Std 802.1Q-2022, this is described in
+detail:
+
+Each of the reserved MAC addresses specified in Table 8-1
+(01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]) shall be
+permanently configured in the FDB in C-VLAN components and ERs.
+
+Each of the reserved MAC addresses specified in Table 8-2
+(01-80-C2-00-00-[01,02,03,04,05,06,07,08,09,0A,0E]) shall be permanently
+configured in the FDB in S-VLAN components.
+
+Each of the reserved MAC addresses specified in Table 8-3
+(01-80-C2-00-00-[01,02,04,0E]) shall be permanently configured in the FDB
+in TPMR components.
+
+The FDB entries for reserved MAC addresses shall specify filtering for all
+Bridge Ports and all VIDs. Management shall not provide the capability to
+modify or remove entries for reserved MAC addresses.
+
+The addresses in Table 8-1, Table 8-2, and Table 8-3 determine the scope of
+propagation of PDUs within a Bridged Network, as follows:
+
+ The Nearest Bridge group address (01-80-C2-00-00-0E) is an address that
+ no conformant Two-Port MAC Relay (TPMR) component, Service VLAN (S-VLAN)
+ component, Customer VLAN (C-VLAN) component, or MAC Bridge can forward.
+ PDUs transmitted using this destination address, or any other addresses
+ that appear in Table 8-1, Table 8-2, and Table 8-3
+ (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]), can
+ therefore travel no further than those stations that can be reached via a
+ single individual LAN from the originating station.
+
+ The Nearest non-TPMR Bridge group address (01-80-C2-00-00-03), is an
+ address that no conformant S-VLAN component, C-VLAN component, or MAC
+ Bridge can forward; however, this address is relayed by a TPMR component.
+ PDUs using this destination address, or any of the other addresses that
+ appear in both Table 8-1 and Table 8-2 but not in Table 8-3
+ (01-80-C2-00-00-[00,03,05,06,07,08,09,0A,0B,0C,0D,0F]), will be relayed
+ by any TPMRs but will propagate no further than the nearest S-VLAN
+ component, C-VLAN component, or MAC Bridge.
+
+ The Nearest Customer Bridge group address (01-80-C2-00-00-00) is an
+ address that no conformant C-VLAN component, MAC Bridge can forward;
+ however, it is relayed by TPMR components and S-VLAN components. PDUs
+ using this destination address, or any of the other addresses that appear
+ in Table 8-1 but not in either Table 8-2 or Table 8-3
+ (01-80-C2-00-00-[00,0B,0C,0D,0F]), will be relayed by TPMR components and
+ S-VLAN components but will propagate no further than the nearest C-VLAN
+ component or MAC Bridge.
+
+Because the LLC Entity associated with each Bridge Port is provided via CPU
+port, we must not filter these frames but forward them to CPU port.
+
+In a Bridge, the transmission Port is majorly decided by ingress and egress
+rules, FDB, and spanning tree Port State functions of the Forwarding
+Process. For link-local frames, only CPU port should be designated as
+destination port in the FDB, and the other functions of the Forwarding
+Process must not interfere with the decision of the transmission Port. We
+call this process trapping frames to CPU port.
+
+Therefore, on the switch with CPU port architecture, link-local frames must
+be trapped to CPU port, and certain link-local frames received by a Port of
+a Bridge comprising a TPMR component or an S-VLAN component must be
+excluded from it.
+
+A Bridge of the switch with CPU port architecture cannot comprise a
+Two-Port MAC Relay (TPMR) component as a TPMR component supports only a
+subset of the functionality of a MAC Bridge. A Bridge comprising two Ports
+(Management Port doesn't count) of this architecture will either function
+as a standard MAC Bridge or a standard VLAN Bridge.
+
+Therefore, a Bridge of this architecture can only comprise S-VLAN
+components, C-VLAN components, or MAC Bridge components. Since there's no
+TPMR component, we don't need to relay PDUs using the destination addresses
+specified on the Nearest non-TPMR section, and the proportion of the
+Nearest Customer Bridge section where they must be relayed by TPMR
+components.
+
+One option to trap link-local frames to CPU port is to add static FDB
+entries with CPU port designated as destination port. However, because that
+Independent VLAN Learning (IVL) is being used on every VID, each entry only
+applies to a single VLAN Identifier (VID). For a Bridge comprising a MAC
+Bridge component or a C-VLAN component, there would have to be 16 times
+4096 entries. This switch intellectual property can only hold a maximum of
+2048 entries. Using this option, there also isn't a mechanism to prevent
+link-local frames from being discarded when the spanning tree Port State of
+the reception Port is discarding.
+
+The remaining option is to utilise the BPC, RGAC1, RGAC2, RGAC3, and RGAC4
+registers. Whilst this applies to every VID, it doesn't contain all of the
+reserved MAC addresses without affecting the remaining Standard Group MAC
+Addresses. The REV_UN frame tag utilised using the RGAC4 register covers
+the remaining 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] destination
+addresses. It also includes the 01-80-C2-00-00-22 to 01-80-C2-00-00-FF
+destination addresses which may be relayed by MAC Bridges or VLAN Bridges.
+The latter option provides better but not complete conformance.
+
+This switch intellectual property also does not provide a mechanism to trap
+link-local frames with specific destination addresses to CPU port by
+Bridge, to conform to the filtering rules for the distinct Bridge
+components.
+
+Therefore, regardless of the type of the Bridge component, link-local
+frames with these destination addresses will be trapped to CPU port:
+
+01-80-C2-00-00-[00,01,02,03,0E]
+
+In a Bridge comprising a MAC Bridge component or a C-VLAN component:
+
+ Link-local frames with these destination addresses won't be trapped to
+ CPU port which won't conform to IEEE Std 802.1Q-2022:
+
+ 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F]
+
+In a Bridge comprising an S-VLAN component:
+
+ Link-local frames with these destination addresses will be trapped to CPU
+ port which won't conform to IEEE Std 802.1Q-2022:
+
+ 01-80-C2-00-00-00
+
+ Link-local frames with these destination addresses won't be trapped to
+ CPU port which won't conform to IEEE Std 802.1Q-2022:
+
+ 01-80-C2-00-00-[04,05,06,07,08,09,0A]
+
+Currently on this switch intellectual property, if the spanning tree Port
+State of the reception Port is discarding, link-local frames will be
+discarded.
+
+To trap link-local frames regardless of the spanning tree Port State, make
+the switch regard them as Bridge Protocol Data Units (BPDUs). This switch
+intellectual property only lets the frames regarded as BPDUs bypass the
+spanning tree Port State function of the Forwarding Process.
+
+With this change, the only remaining interference is the ingress rules.
+When the reception Port has no PVID assigned on software, VLAN-untagged
+frames won't be allowed in. There doesn't seem to be a mechanism on the
+switch intellectual property to have link-local frames bypass this function
+of the Forwarding Process.
+
+Fixes: b8f126a8d543 ("net-next: dsa: add dsa support for Mediatek MT7530 switch")
+Reviewed-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 229 +++++++++++++++++++++++++++++++++------
+ drivers/net/dsa/mt7530.h | 5 +
+ 2 files changed, 200 insertions(+), 34 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -943,20 +943,173 @@ static void mt7530_setup_port5(struct ds
+ mutex_unlock(&priv->reg_mutex);
+ }
+
+-/* On page 205, section "8.6.3 Frame filtering" of the active standard, IEEE Std
+- * 802.1Q™-2022, it is stated that frames with 01:80:C2:00:00:00-0F as MAC DA
+- * must only be propagated to C-VLAN and MAC Bridge components. That means
+- * VLAN-aware and VLAN-unaware bridges. On the switch designs with CPU ports,
+- * these frames are supposed to be processed by the CPU (software). So we make
+- * the switch only forward them to the CPU port. And if received from a CPU
+- * port, forward to a single port. The software is responsible of making the
+- * switch conform to the latter by setting a single port as destination port on
+- * the special tag.
+- *
+- * This switch intellectual property cannot conform to this part of the standard
+- * fully. Whilst the REV_UN frame tag covers the remaining :04-0D and :0F MAC
+- * DAs, it also includes :22-FF which the scope of propagation is not supposed
+- * to be restricted for these MAC DAs.
++/* In Clause 5 of IEEE Std 802-2014, two sublayers of the data link layer (DLL)
++ * of the Open Systems Interconnection basic reference model (OSI/RM) are
++ * described; the medium access control (MAC) and logical link control (LLC)
++ * sublayers. The MAC sublayer is the one facing the physical layer.
++ *
++ * In 8.2 of IEEE Std 802.1Q-2022, the Bridge architecture is described. A
++ * Bridge component comprises a MAC Relay Entity for interconnecting the Ports
++ * of the Bridge, at least two Ports, and higher layer entities with at least a
++ * Spanning Tree Protocol Entity included.
++ *
++ * Each Bridge Port also functions as an end station and shall provide the MAC
++ * Service to an LLC Entity. Each instance of the MAC Service is provided to a
++ * distinct LLC Entity that supports protocol identification, multiplexing, and
++ * demultiplexing, for protocol data unit (PDU) transmission and reception by
++ * one or more higher layer entities.
++ *
++ * It is described in 8.13.9 of IEEE Std 802.1Q-2022 that in a Bridge, the LLC
++ * Entity associated with each Bridge Port is modeled as being directly
++ * connected to the attached Local Area Network (LAN).
++ *
++ * On the switch with CPU port architecture, CPU port functions as Management
++ * Port, and the Management Port functionality is provided by software which
++ * functions as an end station. Software is connected to an IEEE 802 LAN that is
++ * wholly contained within the system that incorporates the Bridge. Software
++ * provides access to the LLC Entity associated with each Bridge Port by the
++ * value of the source port field on the special tag on the frame received by
++ * software.
++ *
++ * We call frames that carry control information to determine the active
++ * topology and current extent of each Virtual Local Area Network (VLAN), i.e.,
++ * spanning tree or Shortest Path Bridging (SPB) and Multiple VLAN Registration
++ * Protocol Data Units (MVRPDUs), and frames from other link constrained
++ * protocols, such as Extensible Authentication Protocol over LAN (EAPOL) and
++ * Link Layer Discovery Protocol (LLDP), link-local frames. They are not
++ * forwarded by a Bridge. Permanently configured entries in the filtering
++ * database (FDB) ensure that such frames are discarded by the Forwarding
++ * Process. In 8.6.3 of IEEE Std 802.1Q-2022, this is described in detail:
++ *
++ * Each of the reserved MAC addresses specified in Table 8-1
++ * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]) shall be
++ * permanently configured in the FDB in C-VLAN components and ERs.
++ *
++ * Each of the reserved MAC addresses specified in Table 8-2
++ * (01-80-C2-00-00-[01,02,03,04,05,06,07,08,09,0A,0E]) shall be permanently
++ * configured in the FDB in S-VLAN components.
++ *
++ * Each of the reserved MAC addresses specified in Table 8-3
++ * (01-80-C2-00-00-[01,02,04,0E]) shall be permanently configured in the FDB in
++ * TPMR components.
++ *
++ * The FDB entries for reserved MAC addresses shall specify filtering for all
++ * Bridge Ports and all VIDs. Management shall not provide the capability to
++ * modify or remove entries for reserved MAC addresses.
++ *
++ * The addresses in Table 8-1, Table 8-2, and Table 8-3 determine the scope of
++ * propagation of PDUs within a Bridged Network, as follows:
++ *
++ * The Nearest Bridge group address (01-80-C2-00-00-0E) is an address that no
++ * conformant Two-Port MAC Relay (TPMR) component, Service VLAN (S-VLAN)
++ * component, Customer VLAN (C-VLAN) component, or MAC Bridge can forward.
++ * PDUs transmitted using this destination address, or any other addresses
++ * that appear in Table 8-1, Table 8-2, and Table 8-3
++ * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]), can
++ * therefore travel no further than those stations that can be reached via a
++ * single individual LAN from the originating station.
++ *
++ * The Nearest non-TPMR Bridge group address (01-80-C2-00-00-03), is an
++ * address that no conformant S-VLAN component, C-VLAN component, or MAC
++ * Bridge can forward; however, this address is relayed by a TPMR component.
++ * PDUs using this destination address, or any of the other addresses that
++ * appear in both Table 8-1 and Table 8-2 but not in Table 8-3
++ * (01-80-C2-00-00-[00,03,05,06,07,08,09,0A,0B,0C,0D,0F]), will be relayed by
++ * any TPMRs but will propagate no further than the nearest S-VLAN component,
++ * C-VLAN component, or MAC Bridge.
++ *
++ * The Nearest Customer Bridge group address (01-80-C2-00-00-00) is an address
++ * that no conformant C-VLAN component, MAC Bridge can forward; however, it is
++ * relayed by TPMR components and S-VLAN components. PDUs using this
++ * destination address, or any of the other addresses that appear in Table 8-1
++ * but not in either Table 8-2 or Table 8-3 (01-80-C2-00-00-[00,0B,0C,0D,0F]),
++ * will be relayed by TPMR components and S-VLAN components but will propagate
++ * no further than the nearest C-VLAN component or MAC Bridge.
++ *
++ * Because the LLC Entity associated with each Bridge Port is provided via CPU
++ * port, we must not filter these frames but forward them to CPU port.
++ *
++ * In a Bridge, the transmission Port is majorly decided by ingress and egress
++ * rules, FDB, and spanning tree Port State functions of the Forwarding Process.
++ * For link-local frames, only CPU port should be designated as destination port
++ * in the FDB, and the other functions of the Forwarding Process must not
++ * interfere with the decision of the transmission Port. We call this process
++ * trapping frames to CPU port.
++ *
++ * Therefore, on the switch with CPU port architecture, link-local frames must
++ * be trapped to CPU port, and certain link-local frames received by a Port of a
++ * Bridge comprising a TPMR component or an S-VLAN component must be excluded
++ * from it.
++ *
++ * A Bridge of the switch with CPU port architecture cannot comprise a Two-Port
++ * MAC Relay (TPMR) component as a TPMR component supports only a subset of the
++ * functionality of a MAC Bridge. A Bridge comprising two Ports (Management Port
++ * doesn't count) of this architecture will either function as a standard MAC
++ * Bridge or a standard VLAN Bridge.
++ *
++ * Therefore, a Bridge of this architecture can only comprise S-VLAN components,
++ * C-VLAN components, or MAC Bridge components. Since there's no TPMR component,
++ * we don't need to relay PDUs using the destination addresses specified on the
++ * Nearest non-TPMR section, and the proportion of the Nearest Customer Bridge
++ * section where they must be relayed by TPMR components.
++ *
++ * One option to trap link-local frames to CPU port is to add static FDB entries
++ * with CPU port designated as destination port. However, because that
++ * Independent VLAN Learning (IVL) is being used on every VID, each entry only
++ * applies to a single VLAN Identifier (VID). For a Bridge comprising a MAC
++ * Bridge component or a C-VLAN component, there would have to be 16 times 4096
++ * entries. This switch intellectual property can only hold a maximum of 2048
++ * entries. Using this option, there also isn't a mechanism to prevent
++ * link-local frames from being discarded when the spanning tree Port State of
++ * the reception Port is discarding.
++ *
++ * The remaining option is to utilise the BPC, RGAC1, RGAC2, RGAC3, and RGAC4
++ * registers. Whilst this applies to every VID, it doesn't contain all of the
++ * reserved MAC addresses without affecting the remaining Standard Group MAC
++ * Addresses. The REV_UN frame tag utilised using the RGAC4 register covers the
++ * remaining 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] destination
++ * addresses. It also includes the 01-80-C2-00-00-22 to 01-80-C2-00-00-FF
++ * destination addresses which may be relayed by MAC Bridges or VLAN Bridges.
++ * The latter option provides better but not complete conformance.
++ *
++ * This switch intellectual property also does not provide a mechanism to trap
++ * link-local frames with specific destination addresses to CPU port by Bridge,
++ * to conform to the filtering rules for the distinct Bridge components.
++ *
++ * Therefore, regardless of the type of the Bridge component, link-local frames
++ * with these destination addresses will be trapped to CPU port:
++ *
++ * 01-80-C2-00-00-[00,01,02,03,0E]
++ *
++ * In a Bridge comprising a MAC Bridge component or a C-VLAN component:
++ *
++ * Link-local frames with these destination addresses won't be trapped to CPU
++ * port which won't conform to IEEE Std 802.1Q-2022:
++ *
++ * 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F]
++ *
++ * In a Bridge comprising an S-VLAN component:
++ *
++ * Link-local frames with these destination addresses will be trapped to CPU
++ * port which won't conform to IEEE Std 802.1Q-2022:
++ *
++ * 01-80-C2-00-00-00
++ *
++ * Link-local frames with these destination addresses won't be trapped to CPU
++ * port which won't conform to IEEE Std 802.1Q-2022:
++ *
++ * 01-80-C2-00-00-[04,05,06,07,08,09,0A]
++ *
++ * To trap link-local frames to CPU port as conformant as this switch
++ * intellectual property can allow, link-local frames are made to be regarded as
++ * Bridge Protocol Data Units (BPDUs). This is because this switch intellectual
++ * property only lets the frames regarded as BPDUs bypass the spanning tree Port
++ * State function of the Forwarding Process.
++ *
++ * The only remaining interference is the ingress rules. When the reception Port
++ * has no PVID assigned on software, VLAN-untagged frames won't be allowed in.
++ * There doesn't seem to be a mechanism on the switch intellectual property to
++ * have link-local frames bypass this function of the Forwarding Process.
+ */
+ static void
+ mt753x_trap_frames(struct mt7530_priv *priv)
+@@ -964,35 +1117,43 @@ mt753x_trap_frames(struct mt7530_priv *p
+ /* Trap 802.1X PAE frames and BPDUs to the CPU port(s) and egress them
+ * VLAN-untagged.
+ */
+- mt7530_rmw(priv, MT753X_BPC, MT753X_PAE_EG_TAG_MASK |
+- MT753X_PAE_PORT_FW_MASK | MT753X_BPDU_EG_TAG_MASK |
+- MT753X_BPDU_PORT_FW_MASK,
+- MT753X_PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
+- MT753X_PAE_PORT_FW(MT753X_BPDU_CPU_ONLY) |
+- MT753X_BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
+- MT753X_BPDU_CPU_ONLY);
++ mt7530_rmw(priv, MT753X_BPC,
++ MT753X_PAE_BPDU_FR | MT753X_PAE_EG_TAG_MASK |
++ MT753X_PAE_PORT_FW_MASK | MT753X_BPDU_EG_TAG_MASK |
++ MT753X_BPDU_PORT_FW_MASK,
++ MT753X_PAE_BPDU_FR |
++ MT753X_PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
++ MT753X_PAE_PORT_FW(MT753X_BPDU_CPU_ONLY) |
++ MT753X_BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
++ MT753X_BPDU_CPU_ONLY);
+
+ /* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and egress
+ * them VLAN-untagged.
+ */
+- mt7530_rmw(priv, MT753X_RGAC1, MT753X_R02_EG_TAG_MASK |
+- MT753X_R02_PORT_FW_MASK | MT753X_R01_EG_TAG_MASK |
+- MT753X_R01_PORT_FW_MASK,
+- MT753X_R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
+- MT753X_R02_PORT_FW(MT753X_BPDU_CPU_ONLY) |
+- MT753X_R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
+- MT753X_BPDU_CPU_ONLY);
++ mt7530_rmw(priv, MT753X_RGAC1,
++ MT753X_R02_BPDU_FR | MT753X_R02_EG_TAG_MASK |
++ MT753X_R02_PORT_FW_MASK | MT753X_R01_BPDU_FR |
++ MT753X_R01_EG_TAG_MASK | MT753X_R01_PORT_FW_MASK,
++ MT753X_R02_BPDU_FR |
++ MT753X_R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
++ MT753X_R02_PORT_FW(MT753X_BPDU_CPU_ONLY) |
++ MT753X_R01_BPDU_FR |
++ MT753X_R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
++ MT753X_BPDU_CPU_ONLY);
+
+ /* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and egress
+ * them VLAN-untagged.
+ */
+- mt7530_rmw(priv, MT753X_RGAC2, MT753X_R0E_EG_TAG_MASK |
+- MT753X_R0E_PORT_FW_MASK | MT753X_R03_EG_TAG_MASK |
+- MT753X_R03_PORT_FW_MASK,
+- MT753X_R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
+- MT753X_R0E_PORT_FW(MT753X_BPDU_CPU_ONLY) |
+- MT753X_R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
+- MT753X_BPDU_CPU_ONLY);
++ mt7530_rmw(priv, MT753X_RGAC2,
++ MT753X_R0E_BPDU_FR | MT753X_R0E_EG_TAG_MASK |
++ MT753X_R0E_PORT_FW_MASK | MT753X_R03_BPDU_FR |
++ MT753X_R03_EG_TAG_MASK | MT753X_R03_PORT_FW_MASK,
++ MT753X_R0E_BPDU_FR |
++ MT753X_R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
++ MT753X_R0E_PORT_FW(MT753X_BPDU_CPU_ONLY) |
++ MT753X_R03_BPDU_FR |
++ MT753X_R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
++ MT753X_BPDU_CPU_ONLY);
+ }
+
+ static void
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -65,6 +65,7 @@ enum mt753x_id {
+
+ /* Registers for BPDU and PAE frame control*/
+ #define MT753X_BPC 0x24
++#define MT753X_PAE_BPDU_FR BIT(25)
+ #define MT753X_PAE_EG_TAG_MASK GENMASK(24, 22)
+ #define MT753X_PAE_EG_TAG(x) FIELD_PREP(MT753X_PAE_EG_TAG_MASK, x)
+ #define MT753X_PAE_PORT_FW_MASK GENMASK(18, 16)
+@@ -75,20 +76,24 @@ enum mt753x_id {
+
+ /* Register for :01 and :02 MAC DA frame control */
+ #define MT753X_RGAC1 0x28
++#define MT753X_R02_BPDU_FR BIT(25)
+ #define MT753X_R02_EG_TAG_MASK GENMASK(24, 22)
+ #define MT753X_R02_EG_TAG(x) FIELD_PREP(MT753X_R02_EG_TAG_MASK, x)
+ #define MT753X_R02_PORT_FW_MASK GENMASK(18, 16)
+ #define MT753X_R02_PORT_FW(x) FIELD_PREP(MT753X_R02_PORT_FW_MASK, x)
++#define MT753X_R01_BPDU_FR BIT(9)
+ #define MT753X_R01_EG_TAG_MASK GENMASK(8, 6)
+ #define MT753X_R01_EG_TAG(x) FIELD_PREP(MT753X_R01_EG_TAG_MASK, x)
+ #define MT753X_R01_PORT_FW_MASK GENMASK(2, 0)
+
+ /* Register for :03 and :0E MAC DA frame control */
+ #define MT753X_RGAC2 0x2c
++#define MT753X_R0E_BPDU_FR BIT(25)
+ #define MT753X_R0E_EG_TAG_MASK GENMASK(24, 22)
+ #define MT753X_R0E_EG_TAG(x) FIELD_PREP(MT753X_R0E_EG_TAG_MASK, x)
+ #define MT753X_R0E_PORT_FW_MASK GENMASK(18, 16)
+ #define MT753X_R0E_PORT_FW(x) FIELD_PREP(MT753X_R0E_PORT_FW_MASK, x)
++#define MT753X_R03_BPDU_FR BIT(9)
+ #define MT753X_R03_EG_TAG_MASK GENMASK(8, 6)
+ #define MT753X_R03_EG_TAG(x) FIELD_PREP(MT753X_R03_EG_TAG_MASK, x)
+ #define MT753X_R03_PORT_FW_MASK GENMASK(2, 0)
--- /dev/null
+From 5754b3bdcd872aa229881b8f07f84a8404c7d72a Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Fri, 12 Apr 2024 16:15:34 +0100
+Subject: [PATCH 1/5] net: dsa: mt7530: provide own phylink MAC operations
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Convert mt753x to provide its own phylink MAC operations, thus avoiding
+the shim layer in DSA's port.c
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Tested-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Link: https://lore.kernel.org/r/E1rvIco-006bQu-Fq@rmk-PC.armlinux.org.uk
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/dsa/mt7530.c | 46 +++++++++++++++++++++++++---------------
+ 1 file changed, 29 insertions(+), 17 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2841,28 +2841,34 @@ mt7531_mac_config(struct dsa_switch *ds,
+ }
+
+ static struct phylink_pcs *
+-mt753x_phylink_mac_select_pcs(struct dsa_switch *ds, int port,
++mt753x_phylink_mac_select_pcs(struct phylink_config *config,
+ phy_interface_t interface)
+ {
+- struct mt7530_priv *priv = ds->priv;
++ struct dsa_port *dp = dsa_phylink_to_port(config);
++ struct mt7530_priv *priv = dp->ds->priv;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_TRGMII:
+- return &priv->pcs[port].pcs;
++ return &priv->pcs[dp->index].pcs;
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
+- return priv->ports[port].sgmii_pcs;
++ return priv->ports[dp->index].sgmii_pcs;
+ default:
+ return NULL;
+ }
+ }
+
+ static void
+-mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
++mt753x_phylink_mac_config(struct phylink_config *config, unsigned int mode,
+ const struct phylink_link_state *state)
+ {
+- struct mt7530_priv *priv = ds->priv;
++ struct dsa_port *dp = dsa_phylink_to_port(config);
++ struct dsa_switch *ds = dp->ds;
++ struct mt7530_priv *priv;
++ int port = dp->index;
++
++ priv = ds->priv;
+
+ if ((port == 5 || port == 6) && priv->info->mac_port_config)
+ priv->info->mac_port_config(ds, port, mode, state->interface);
+@@ -2872,23 +2878,25 @@ mt753x_phylink_mac_config(struct dsa_swi
+ mt7530_set(priv, MT7530_PMCR_P(port), PMCR_EXT_PHY);
+ }
+
+-static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port,
++static void mt753x_phylink_mac_link_down(struct phylink_config *config,
+ unsigned int mode,
+ phy_interface_t interface)
+ {
+- struct mt7530_priv *priv = ds->priv;
++ struct dsa_port *dp = dsa_phylink_to_port(config);
++ struct mt7530_priv *priv = dp->ds->priv;
+
+- mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
++ mt7530_clear(priv, MT7530_PMCR_P(dp->index), PMCR_LINK_SETTINGS_MASK);
+ }
+
+-static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port,
++static void mt753x_phylink_mac_link_up(struct phylink_config *config,
++ struct phy_device *phydev,
+ unsigned int mode,
+ phy_interface_t interface,
+- struct phy_device *phydev,
+ int speed, int duplex,
+ bool tx_pause, bool rx_pause)
+ {
+- struct mt7530_priv *priv = ds->priv;
++ struct dsa_port *dp = dsa_phylink_to_port(config);
++ struct mt7530_priv *priv = dp->ds->priv;
+ u32 mcr;
+
+ mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK;
+@@ -2923,7 +2931,7 @@ static void mt753x_phylink_mac_link_up(s
+ }
+ }
+
+- mt7530_set(priv, MT7530_PMCR_P(port), mcr);
++ mt7530_set(priv, MT7530_PMCR_P(dp->index), mcr);
+ }
+
+ static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port,
+@@ -3148,16 +3156,19 @@ const struct dsa_switch_ops mt7530_switc
+ .port_mirror_add = mt753x_port_mirror_add,
+ .port_mirror_del = mt753x_port_mirror_del,
+ .phylink_get_caps = mt753x_phylink_get_caps,
+- .phylink_mac_select_pcs = mt753x_phylink_mac_select_pcs,
+- .phylink_mac_config = mt753x_phylink_mac_config,
+- .phylink_mac_link_down = mt753x_phylink_mac_link_down,
+- .phylink_mac_link_up = mt753x_phylink_mac_link_up,
+ .get_mac_eee = mt753x_get_mac_eee,
+ .set_mac_eee = mt753x_set_mac_eee,
+ .master_state_change = mt753x_conduit_state_change,
+ };
+ EXPORT_SYMBOL_GPL(mt7530_switch_ops);
+
++static const struct phylink_mac_ops mt753x_phylink_mac_ops = {
++ .mac_select_pcs = mt753x_phylink_mac_select_pcs,
++ .mac_config = mt753x_phylink_mac_config,
++ .mac_link_down = mt753x_phylink_mac_link_down,
++ .mac_link_up = mt753x_phylink_mac_link_up,
++};
++
+ const struct mt753x_info mt753x_table[] = {
+ [ID_MT7621] = {
+ .id = ID_MT7621,
+@@ -3227,6 +3238,7 @@ mt7530_probe_common(struct mt7530_priv *
+ priv->dev = dev;
+ priv->ds->priv = priv;
+ priv->ds->ops = &mt7530_switch_ops;
++ priv->ds->phylink_mac_ops = &mt753x_phylink_mac_ops;
+ mutex_init(&priv->reg_mutex);
+ dev_set_drvdata(dev, priv);
+
--- /dev/null
+From d4097ddef078a113643a6dcde01e99741f852adb Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Sat, 13 Apr 2024 16:01:39 +0300
+Subject: [PATCH 2/5] net: dsa: mt7530: fix mirroring frames received on local
+ port
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This switch intellectual property provides a bit on the ARL global control
+register which controls allowing mirroring frames which are received on the
+local port (monitor port). This bit is unset after reset.
+
+This ability must be enabled to fully support the port mirroring feature on
+this switch intellectual property.
+
+Therefore, this patch fixes the traffic not being reflected on a port,
+which would be configured like below:
+
+ tc qdisc add dev swp0 clsact
+
+ tc filter add dev swp0 ingress matchall skip_sw \
+ action mirred egress mirror dev swp0
+
+As a side note, this configuration provides the hairpinning feature for a
+single port.
+
+Fixes: 37feab6076aa ("net: dsa: mt7530: add support for port mirroring")
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/dsa/mt7530.c | 6 ++++++
+ drivers/net/dsa/mt7530.h | 4 ++++
+ 2 files changed, 10 insertions(+)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2471,6 +2471,9 @@ mt7530_setup(struct dsa_switch *ds)
+ PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
+ }
+
++ /* Allow mirroring frames received on the local port (monitor port). */
++ mt7530_set(priv, MT753X_AGC, LOCAL_EN);
++
+ /* Setup VLAN ID 0 for VLAN-unaware bridges */
+ ret = mt7530_setup_vlan0(priv);
+ if (ret)
+@@ -2582,6 +2585,9 @@ mt7531_setup_common(struct dsa_switch *d
+ PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
+ }
+
++ /* Allow mirroring frames received on the local port (monitor port). */
++ mt7530_set(priv, MT753X_AGC, LOCAL_EN);
++
+ /* Flush the FDB table */
+ ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
+ if (ret < 0)
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -32,6 +32,10 @@ enum mt753x_id {
+ #define SYSC_REG_RSTCTRL 0x34
+ #define RESET_MCM BIT(2)
+
++/* Register for ARL global control */
++#define MT753X_AGC 0xc
++#define LOCAL_EN BIT(7)
++
+ /* Registers to mac forward control for unknown frames */
+ #define MT7530_MFC 0x10
+ #define BC_FFP(x) (((x) & 0xff) << 24)
--- /dev/null
+From 019a17a5e76940ea86114838d1d638d4dc8d3750 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Sat, 13 Apr 2024 16:01:40 +0300
+Subject: [PATCH 3/5] net: dsa: mt7530: fix port mirroring for MT7988 SoC
+ switch
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The "MT7988A Wi-Fi 7 Generation Router Platform: Datasheet (Open Version)
+v0.1" document shows bits 16 to 18 as the MIRROR_PORT field of the CPU
+forward control register. Currently, the MT7530 DSA subdriver configures
+bits 0 to 2 of the CPU forward control register which breaks the port
+mirroring feature for the MT7988 SoC switch.
+
+Fix this by using the MT7531_MIRROR_PORT_GET() and MT7531_MIRROR_PORT_SET()
+macros which utilise the correct bits.
+
+Fixes: 110c18bfed41 ("net: dsa: mt7530: introduce driver for MT7988 built-in switch")
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Acked-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/dsa/mt7530.c | 10 ++++++----
+ 1 file changed, 6 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -1876,14 +1876,16 @@ mt7530_port_vlan_del(struct dsa_switch *
+
+ static int mt753x_mirror_port_get(unsigned int id, u32 val)
+ {
+- return (id == ID_MT7531) ? MT7531_MIRROR_PORT_GET(val) :
+- MIRROR_PORT(val);
++ return (id == ID_MT7531 || id == ID_MT7988) ?
++ MT7531_MIRROR_PORT_GET(val) :
++ MIRROR_PORT(val);
+ }
+
+ static int mt753x_mirror_port_set(unsigned int id, u32 val)
+ {
+- return (id == ID_MT7531) ? MT7531_MIRROR_PORT_SET(val) :
+- MIRROR_PORT(val);
++ return (id == ID_MT7531 || id == ID_MT7988) ?
++ MT7531_MIRROR_PORT_SET(val) :
++ MIRROR_PORT(val);
+ }
+
+ static int mt753x_port_mirror_add(struct dsa_switch *ds, int port,
--- /dev/null
+From 5053a6cf1d50d785078562470d2a63695a9f3bf2 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Thu, 18 Apr 2024 08:35:30 +0300
+Subject: [PATCH 4/5] net: dsa: mt7530-mdio: read PHY address of switch from
+ device tree
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Read the PHY address the switch listens on from the reg property of the
+switch node on the device tree. This change brings support for MT7530
+switches on boards with such bootstrapping configuration where the switch
+listens on a different PHY address than the hardcoded PHY address on the
+driver, 31.
+
+As described on the "MT7621 Programming Guide v0.4" document, the MT7530
+switch and its PHYs can be configured to listen on the range of 7-12,
+15-20, 23-28, and 31 and 0-4 PHY addresses.
+
+There are operations where the switch PHY registers are used. For the PHY
+address of the control PHY, transform the MT753X_CTRL_PHY_ADDR constant
+into a macro and use it. The PHY address for the control PHY is 0 when the
+switch listens on 31. In any other case, it is one greater than the PHY
+address the switch listens on.
+
+Reviewed-by: Daniel Golle <daniel@makrotopia.org>
+Tested-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/dsa/mt7530-mdio.c | 28 +++++++++++++-------------
+ drivers/net/dsa/mt7530.c | 37 +++++++++++++++++++++++------------
+ drivers/net/dsa/mt7530.h | 4 +++-
+ 3 files changed, 41 insertions(+), 28 deletions(-)
+
+--- a/drivers/net/dsa/mt7530-mdio.c
++++ b/drivers/net/dsa/mt7530-mdio.c
+@@ -18,7 +18,8 @@
+ static int
+ mt7530_regmap_write(void *context, unsigned int reg, unsigned int val)
+ {
+- struct mii_bus *bus = context;
++ struct mt7530_priv *priv = context;
++ struct mii_bus *bus = priv->bus;
+ u16 page, r, lo, hi;
+ int ret;
+
+@@ -27,36 +28,35 @@ mt7530_regmap_write(void *context, unsig
+ lo = val & 0xffff;
+ hi = val >> 16;
+
+- /* MT7530 uses 31 as the pseudo port */
+- ret = bus->write(bus, 0x1f, 0x1f, page);
++ ret = bus->write(bus, priv->mdiodev->addr, 0x1f, page);
+ if (ret < 0)
+ return ret;
+
+- ret = bus->write(bus, 0x1f, r, lo);
++ ret = bus->write(bus, priv->mdiodev->addr, r, lo);
+ if (ret < 0)
+ return ret;
+
+- ret = bus->write(bus, 0x1f, 0x10, hi);
++ ret = bus->write(bus, priv->mdiodev->addr, 0x10, hi);
+ return ret;
+ }
+
+ static int
+ mt7530_regmap_read(void *context, unsigned int reg, unsigned int *val)
+ {
+- struct mii_bus *bus = context;
++ struct mt7530_priv *priv = context;
++ struct mii_bus *bus = priv->bus;
+ u16 page, r, lo, hi;
+ int ret;
+
+ page = (reg >> 6) & 0x3ff;
+ r = (reg >> 2) & 0xf;
+
+- /* MT7530 uses 31 as the pseudo port */
+- ret = bus->write(bus, 0x1f, 0x1f, page);
++ ret = bus->write(bus, priv->mdiodev->addr, 0x1f, page);
+ if (ret < 0)
+ return ret;
+
+- lo = bus->read(bus, 0x1f, r);
+- hi = bus->read(bus, 0x1f, 0x10);
++ lo = bus->read(bus, priv->mdiodev->addr, r);
++ hi = bus->read(bus, priv->mdiodev->addr, 0x10);
+
+ *val = (hi << 16) | (lo & 0xffff);
+
+@@ -107,8 +107,7 @@ mt7531_create_sgmii(struct mt7530_priv *
+ mt7531_pcs_config[i]->unlock = mt7530_mdio_regmap_unlock;
+ mt7531_pcs_config[i]->lock_arg = &priv->bus->mdio_lock;
+
+- regmap = devm_regmap_init(priv->dev,
+- &mt7530_regmap_bus, priv->bus,
++ regmap = devm_regmap_init(priv->dev, &mt7530_regmap_bus, priv,
+ mt7531_pcs_config[i]);
+ if (IS_ERR(regmap)) {
+ ret = PTR_ERR(regmap);
+@@ -153,6 +152,7 @@ mt7530_probe(struct mdio_device *mdiodev
+
+ priv->bus = mdiodev->bus;
+ priv->dev = &mdiodev->dev;
++ priv->mdiodev = mdiodev;
+
+ ret = mt7530_probe_common(priv);
+ if (ret)
+@@ -203,8 +203,8 @@ mt7530_probe(struct mdio_device *mdiodev
+ regmap_config->reg_stride = 4;
+ regmap_config->max_register = MT7530_CREV;
+ regmap_config->disable_locking = true;
+- priv->regmap = devm_regmap_init(priv->dev, &mt7530_regmap_bus,
+- priv->bus, regmap_config);
++ priv->regmap = devm_regmap_init(priv->dev, &mt7530_regmap_bus, priv,
++ regmap_config);
+ if (IS_ERR(priv->regmap))
+ return PTR_ERR(priv->regmap);
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -86,22 +86,26 @@ core_read_mmd_indirect(struct mt7530_pri
+ int value, ret;
+
+ /* Write the desired MMD Devad */
+- ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
++ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
++ MII_MMD_CTRL, devad);
+ if (ret < 0)
+ goto err;
+
+ /* Write the desired MMD register address */
+- ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
++ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
++ MII_MMD_DATA, prtad);
+ if (ret < 0)
+ goto err;
+
+ /* Select the Function : DATA with no post increment */
+- ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
++ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
++ MII_MMD_CTRL, devad | MII_MMD_CTRL_NOINCR);
+ if (ret < 0)
+ goto err;
+
+ /* Read the content of the MMD's selected register */
+- value = bus->read(bus, 0, MII_MMD_DATA);
++ value = bus->read(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
++ MII_MMD_DATA);
+
+ return value;
+ err:
+@@ -118,22 +122,26 @@ core_write_mmd_indirect(struct mt7530_pr
+ int ret;
+
+ /* Write the desired MMD Devad */
+- ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
++ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
++ MII_MMD_CTRL, devad);
+ if (ret < 0)
+ goto err;
+
+ /* Write the desired MMD register address */
+- ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
++ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
++ MII_MMD_DATA, prtad);
+ if (ret < 0)
+ goto err;
+
+ /* Select the Function : DATA with no post increment */
+- ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
++ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
++ MII_MMD_CTRL, devad | MII_MMD_CTRL_NOINCR);
+ if (ret < 0)
+ goto err;
+
+ /* Write the data into MMD's selected register */
+- ret = bus->write(bus, 0, MII_MMD_DATA, data);
++ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
++ MII_MMD_DATA, data);
+ err:
+ if (ret < 0)
+ dev_err(&bus->dev,
+@@ -2670,16 +2678,19 @@ mt7531_setup(struct dsa_switch *ds)
+ * phy_[read,write]_mmd_indirect is called, we provide our own
+ * mt7531_ind_mmd_phy_[read,write] to complete this function.
+ */
+- val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR,
++ val = mt7531_ind_c45_phy_read(priv,
++ MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
+ MDIO_MMD_VEND2, CORE_PLL_GROUP4);
+ val |= MT7531_RG_SYSPLL_DMY2 | MT7531_PHY_PLL_BYPASS_MODE;
+ val &= ~MT7531_PHY_PLL_OFF;
+- mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2,
+- CORE_PLL_GROUP4, val);
++ mt7531_ind_c45_phy_write(priv,
++ MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
++ MDIO_MMD_VEND2, CORE_PLL_GROUP4, val);
+
+ /* Disable EEE advertisement on the switch PHYs. */
+- for (i = MT753X_CTRL_PHY_ADDR;
+- i < MT753X_CTRL_PHY_ADDR + MT7530_NUM_PHYS; i++) {
++ for (i = MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr);
++ i < MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr) + MT7530_NUM_PHYS;
++ i++) {
+ mt7531_ind_c45_phy_write(priv, i, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
+ 0);
+ }
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -629,7 +629,7 @@ enum mt7531_clk_skew {
+ #define MT7531_PHY_PLL_OFF BIT(5)
+ #define MT7531_PHY_PLL_BYPASS_MODE BIT(4)
+
+-#define MT753X_CTRL_PHY_ADDR 0
++#define MT753X_CTRL_PHY_ADDR(addr) ((addr + 1) & 0x1f)
+
+ #define CORE_PLL_GROUP5 0x404
+ #define RG_LCDDS_PCW_NCPO1(x) ((x) & 0xffff)
+@@ -771,6 +771,7 @@ struct mt753x_info {
+ * @irq_enable: IRQ enable bits, synced to SYS_INT_EN
+ * @create_sgmii: Pointer to function creating SGMII PCS instance(s)
+ * @active_cpu_ports: Holding the active CPU ports
++ * @mdiodev: The pointer to the MDIO device structure
+ */
+ struct mt7530_priv {
+ struct device *dev;
+@@ -797,6 +798,7 @@ struct mt7530_priv {
+ u32 irq_enable;
+ int (*create_sgmii)(struct mt7530_priv *priv);
+ u8 active_cpu_ports;
++ struct mdio_device *mdiodev;
+ };
+
+ struct mt7530_hw_vlan_entry {
--- /dev/null
+From 9764a08b3d260f4e7799d34bbfe64463db940d74 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Thu, 18 Apr 2024 08:35:31 +0300
+Subject: [PATCH 5/5] net: dsa: mt7530: simplify core operations
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The core_rmw() function calls core_read_mmd_indirect() to read the
+requested register, and then calls core_write_mmd_indirect() to write the
+requested value to the register. Because Clause 22 is used to access Clause
+45 registers, some operations on core_write_mmd_indirect() are
+unnecessarily run. Get rid of core_read_mmd_indirect() and
+core_write_mmd_indirect(), and run only the necessary operations on
+core_write() and core_rmw().
+
+Reviewed-by: Daniel Golle <daniel@makrotopia.org>
+Tested-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/dsa/mt7530.c | 108 ++++++++++++++++-----------------------
+ 1 file changed, 43 insertions(+), 65 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -74,116 +74,94 @@ static const struct mt7530_mib_desc mt75
+ MIB_DESC(1, 0xb8, "RxArlDrop"),
+ };
+
+-/* Since phy_device has not yet been created and
+- * phy_{read,write}_mmd_indirect is not available, we provide our own
+- * core_{read,write}_mmd_indirect with core_{clear,write,set} wrappers
+- * to complete this function.
+- */
+-static int
+-core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad)
++static void
++mt7530_mutex_lock(struct mt7530_priv *priv)
++{
++ if (priv->bus)
++ mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
++}
++
++static void
++mt7530_mutex_unlock(struct mt7530_priv *priv)
++{
++ if (priv->bus)
++ mutex_unlock(&priv->bus->mdio_lock);
++}
++
++static void
++core_write(struct mt7530_priv *priv, u32 reg, u32 val)
+ {
+ struct mii_bus *bus = priv->bus;
+- int value, ret;
++ int ret;
++
++ mt7530_mutex_lock(priv);
+
+ /* Write the desired MMD Devad */
+ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
+- MII_MMD_CTRL, devad);
++ MII_MMD_CTRL, MDIO_MMD_VEND2);
+ if (ret < 0)
+ goto err;
+
+ /* Write the desired MMD register address */
+ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
+- MII_MMD_DATA, prtad);
++ MII_MMD_DATA, reg);
+ if (ret < 0)
+ goto err;
+
+ /* Select the Function : DATA with no post increment */
+ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
+- MII_MMD_CTRL, devad | MII_MMD_CTRL_NOINCR);
++ MII_MMD_CTRL, MDIO_MMD_VEND2 | MII_MMD_CTRL_NOINCR);
+ if (ret < 0)
+ goto err;
+
+- /* Read the content of the MMD's selected register */
+- value = bus->read(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
+- MII_MMD_DATA);
+-
+- return value;
++ /* Write the data into MMD's selected register */
++ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
++ MII_MMD_DATA, val);
+ err:
+- dev_err(&bus->dev, "failed to read mmd register\n");
++ if (ret < 0)
++ dev_err(&bus->dev, "failed to write mmd register\n");
+
+- return ret;
++ mt7530_mutex_unlock(priv);
+ }
+
+-static int
+-core_write_mmd_indirect(struct mt7530_priv *priv, int prtad,
+- int devad, u32 data)
++static void
++core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set)
+ {
+ struct mii_bus *bus = priv->bus;
++ u32 val;
+ int ret;
+
++ mt7530_mutex_lock(priv);
++
+ /* Write the desired MMD Devad */
+ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
+- MII_MMD_CTRL, devad);
++ MII_MMD_CTRL, MDIO_MMD_VEND2);
+ if (ret < 0)
+ goto err;
+
+ /* Write the desired MMD register address */
+ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
+- MII_MMD_DATA, prtad);
++ MII_MMD_DATA, reg);
+ if (ret < 0)
+ goto err;
+
+ /* Select the Function : DATA with no post increment */
+ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
+- MII_MMD_CTRL, devad | MII_MMD_CTRL_NOINCR);
++ MII_MMD_CTRL, MDIO_MMD_VEND2 | MII_MMD_CTRL_NOINCR);
+ if (ret < 0)
+ goto err;
+
++ /* Read the content of the MMD's selected register */
++ val = bus->read(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
++ MII_MMD_DATA);
++ val &= ~mask;
++ val |= set;
+ /* Write the data into MMD's selected register */
+ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
+- MII_MMD_DATA, data);
++ MII_MMD_DATA, val);
+ err:
+ if (ret < 0)
+- dev_err(&bus->dev,
+- "failed to write mmd register\n");
+- return ret;
+-}
+-
+-static void
+-mt7530_mutex_lock(struct mt7530_priv *priv)
+-{
+- if (priv->bus)
+- mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
+-}
+-
+-static void
+-mt7530_mutex_unlock(struct mt7530_priv *priv)
+-{
+- if (priv->bus)
+- mutex_unlock(&priv->bus->mdio_lock);
+-}
+-
+-static void
+-core_write(struct mt7530_priv *priv, u32 reg, u32 val)
+-{
+- mt7530_mutex_lock(priv);
+-
+- core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
+-
+- mt7530_mutex_unlock(priv);
+-}
+-
+-static void
+-core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set)
+-{
+- u32 val;
+-
+- mt7530_mutex_lock(priv);
+-
+- val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2);
+- val &= ~mask;
+- val |= set;
+- core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
++ dev_err(&bus->dev, "failed to write mmd register\n");
+
+ mt7530_mutex_unlock(priv);
+ }
--- /dev/null
+From 856e8954a0a88d1a4d2b43e9002b9249131a156f Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:08 +0300
+Subject: [PATCH 01/15] net: dsa: mt7530: disable EEE abilities on failure on
+ MT7531 and MT7988
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The MT7531_FORCE_EEE1G and MT7531_FORCE_EEE100 bits let the
+PMCR_FORCE_EEE1G and PMCR_FORCE_EEE100 bits determine the 1G/100 EEE
+abilities of the MAC. If MT7531_FORCE_EEE1G and MT7531_FORCE_EEE100 are
+unset, the abilities are left to be determined by PHY auto polling.
+
+The commit 40b5d2f15c09 ("net: dsa: mt7530: Add support for EEE features")
+made it so that the PMCR_FORCE_EEE1G and PMCR_FORCE_EEE100 bits are set on
+mt753x_phylink_mac_link_up(). But it did not set the MT7531_FORCE_EEE1G and
+MT7531_FORCE_EEE100 bits. Because of this, the EEE abilities will be
+determined by PHY auto polling, regardless of the result of phy_init_eee().
+
+Define these bits and add them to the MT7531_FORCE_MODE mask which is set
+in mt7531_setup_common(). With this, there won't be any EEE abilities set
+when phy_init_eee() returns a negative value.
+
+Thanks to Russell for explaining when phy_init_eee() could return a
+negative value below.
+
+Looking at phy_init_eee(), it could return a negative value when:
+
+1. phydev->drv is NULL
+2. if genphy_c45_eee_is_active() returns negative
+3. if genphy_c45_eee_is_active() returns zero, it returns -EPROTONOSUPPORT
+4. if phy_set_bits_mmd() fails (e.g. communication error with the PHY)
+
+If we then look at genphy_c45_eee_is_active(), then:
+
+genphy_c45_read_eee_adv() and genphy_c45_read_eee_lpa() propagate their
+non-zero return values, otherwise this function returns zero or positive
+integer.
+
+If we then look at genphy_c45_read_eee_adv(), then a failure of
+phy_read_mmd() would cause a negative value to be returned.
+
+Looking at genphy_c45_read_eee_lpa(), the same is true.
+
+So, it can be summarised as:
+
+- phydev->drv is NULL
+- there is a communication error accessing the PHY
+- EEE is not active
+
+otherwise, it returns zero on success.
+
+If one wishes to determine whether an error occurred vs EEE not being
+supported through negotiation for the negotiated speed, if it returns
+-EPROTONOSUPPORT in the latter case. Other error codes mean either the
+driver has been unloaded or communication error.
+
+In conclusion, determining the EEE abilities by PHY auto polling shouldn't
+result in having any EEE abilities enabled, when one of the last two
+situations in the summary happens. And it seems that if phydev->drv is
+NULL, there would be bigger problems with the device than a broken link. So
+this is not a bugfix.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.h | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -328,11 +328,15 @@ enum mt7530_vlan_port_acc_frm {
+ #define MT7531_FORCE_DPX BIT(29)
+ #define MT7531_FORCE_RX_FC BIT(28)
+ #define MT7531_FORCE_TX_FC BIT(27)
++#define MT7531_FORCE_EEE100 BIT(26)
++#define MT7531_FORCE_EEE1G BIT(25)
+ #define MT7531_FORCE_MODE (MT7531_FORCE_LNK | \
+ MT7531_FORCE_SPD | \
+ MT7531_FORCE_DPX | \
+ MT7531_FORCE_RX_FC | \
+- MT7531_FORCE_TX_FC)
++ MT7531_FORCE_TX_FC | \
++ MT7531_FORCE_EEE100 | \
++ MT7531_FORCE_EEE1G)
+ #define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \
+ PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \
+ PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
--- /dev/null
+From 712ad00d2f43814c81a7abfcbc339690a05fb6a0 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:09 +0300
+Subject: [PATCH 02/15] net: dsa: mt7530: refactor MT7530_PMCR_P()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The MT7530_PMCR_P() registers are on MT7530, MT7531, and the switch on the
+MT7988 SoC. Rename the definition for them to MT753X_PMCR_P(). Bit 15 is
+for MT7530 only. Add MT7530 prefix to the definition for bit 15.
+
+Use GENMASK and FIELD_PREP for PMCR_IFG_XMIT().
+
+Rename PMCR_TX_EN and PMCR_RX_EN to PMCR_MAC_TX_EN and PMCR_MAC_TX_EN to
+follow the naming on the "MT7621 Giga Switch Programming Guide v0.3",
+"MT7531 Reference Manual for Development Board v1.0", and "MT7988A Wi-Fi 7
+Generation Router Platform: Datasheet (Open Version) v0.1" documents.
+
+These documents show that PMCR_RX_FC_EN is at bit 5. Correct this along
+with renaming it to PMCR_FORCE_RX_FC_EN, and the same for PMCR_TX_FC_EN.
+
+Remove PMCR_SPEED_MASK which doesn't have a use.
+
+Rename the force mode definitions for MT7531 to FORCE_MODE. Add MASK at the
+end for the mask that includes all force mode definitions.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 24 ++++++++---------
+ drivers/net/dsa/mt7530.h | 58 +++++++++++++++++++++-------------------
+ 2 files changed, 42 insertions(+), 40 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -889,7 +889,7 @@ static void mt7530_setup_port5(struct ds
+ val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
+
+ /* Setup the MAC by default for the cpu port */
+- mt7530_write(priv, MT7530_PMCR_P(5), 0x56300);
++ mt7530_write(priv, MT753X_PMCR_P(5), 0x56300);
+ break;
+ case P5_INTF_SEL_GMAC5:
+ /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */
+@@ -2435,8 +2435,8 @@ mt7530_setup(struct dsa_switch *ds)
+ /* Clear link settings and enable force mode to force link down
+ * on all ports until they're enabled later.
+ */
+- mt7530_rmw(priv, MT7530_PMCR_P(i), PMCR_LINK_SETTINGS_MASK |
+- PMCR_FORCE_MODE, PMCR_FORCE_MODE);
++ mt7530_rmw(priv, MT753X_PMCR_P(i), PMCR_LINK_SETTINGS_MASK |
++ MT7530_FORCE_MODE, MT7530_FORCE_MODE);
+
+ /* Disable forwarding by default on all ports */
+ mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
+@@ -2546,8 +2546,8 @@ mt7531_setup_common(struct dsa_switch *d
+ /* Clear link settings and enable force mode to force link down
+ * on all ports until they're enabled later.
+ */
+- mt7530_rmw(priv, MT7530_PMCR_P(i), PMCR_LINK_SETTINGS_MASK |
+- MT7531_FORCE_MODE, MT7531_FORCE_MODE);
++ mt7530_rmw(priv, MT753X_PMCR_P(i), PMCR_LINK_SETTINGS_MASK |
++ MT7531_FORCE_MODE_MASK, MT7531_FORCE_MODE_MASK);
+
+ /* Disable forwarding by default on all ports */
+ mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
+@@ -2630,7 +2630,7 @@ mt7531_setup(struct dsa_switch *ds)
+
+ /* Force link down on all ports before internal reset */
+ for (i = 0; i < MT7530_NUM_PORTS; i++)
+- mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK);
++ mt7530_write(priv, MT753X_PMCR_P(i), MT7531_FORCE_MODE_LNK);
+
+ /* Reset the switch through internal reset */
+ mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_SW_RST | SYS_CTRL_REG_RST);
+@@ -2872,7 +2872,7 @@ mt753x_phylink_mac_config(struct phylink
+
+ /* Are we connected to external phy */
+ if (port == 5 && dsa_is_user_port(ds, 5))
+- mt7530_set(priv, MT7530_PMCR_P(port), PMCR_EXT_PHY);
++ mt7530_set(priv, MT753X_PMCR_P(port), PMCR_EXT_PHY);
+ }
+
+ static void mt753x_phylink_mac_link_down(struct phylink_config *config,
+@@ -2882,7 +2882,7 @@ static void mt753x_phylink_mac_link_down
+ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct mt7530_priv *priv = dp->ds->priv;
+
+- mt7530_clear(priv, MT7530_PMCR_P(dp->index), PMCR_LINK_SETTINGS_MASK);
++ mt7530_clear(priv, MT753X_PMCR_P(dp->index), PMCR_LINK_SETTINGS_MASK);
+ }
+
+ static void mt753x_phylink_mac_link_up(struct phylink_config *config,
+@@ -2896,7 +2896,7 @@ static void mt753x_phylink_mac_link_up(s
+ struct mt7530_priv *priv = dp->ds->priv;
+ u32 mcr;
+
+- mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK;
++ mcr = PMCR_MAC_RX_EN | PMCR_MAC_TX_EN | PMCR_FORCE_LNK;
+
+ switch (speed) {
+ case SPEED_1000:
+@@ -2911,9 +2911,9 @@ static void mt753x_phylink_mac_link_up(s
+ if (duplex == DUPLEX_FULL) {
+ mcr |= PMCR_FORCE_FDX;
+ if (tx_pause)
+- mcr |= PMCR_TX_FC_EN;
++ mcr |= PMCR_FORCE_TX_FC_EN;
+ if (rx_pause)
+- mcr |= PMCR_RX_FC_EN;
++ mcr |= PMCR_FORCE_RX_FC_EN;
+ }
+
+ if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, false) >= 0) {
+@@ -2928,7 +2928,7 @@ static void mt753x_phylink_mac_link_up(s
+ }
+ }
+
+- mt7530_set(priv, MT7530_PMCR_P(dp->index), mcr);
++ mt7530_set(priv, MT753X_PMCR_P(dp->index), mcr);
+ }
+
+ static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port,
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -304,44 +304,46 @@ enum mt7530_vlan_port_acc_frm {
+ #define G0_PORT_VID_DEF G0_PORT_VID(0)
+
+ /* Register for port MAC control register */
+-#define MT7530_PMCR_P(x) (0x3000 + ((x) * 0x100))
+-#define PMCR_IFG_XMIT(x) (((x) & 0x3) << 18)
++#define MT753X_PMCR_P(x) (0x3000 + ((x) * 0x100))
++#define PMCR_IFG_XMIT_MASK GENMASK(19, 18)
++#define PMCR_IFG_XMIT(x) FIELD_PREP(PMCR_IFG_XMIT_MASK, x)
+ #define PMCR_EXT_PHY BIT(17)
+ #define PMCR_MAC_MODE BIT(16)
+-#define PMCR_FORCE_MODE BIT(15)
+-#define PMCR_TX_EN BIT(14)
+-#define PMCR_RX_EN BIT(13)
++#define MT7530_FORCE_MODE BIT(15)
++#define PMCR_MAC_TX_EN BIT(14)
++#define PMCR_MAC_RX_EN BIT(13)
+ #define PMCR_BACKOFF_EN BIT(9)
+ #define PMCR_BACKPR_EN BIT(8)
+ #define PMCR_FORCE_EEE1G BIT(7)
+ #define PMCR_FORCE_EEE100 BIT(6)
+-#define PMCR_TX_FC_EN BIT(5)
+-#define PMCR_RX_FC_EN BIT(4)
++#define PMCR_FORCE_RX_FC_EN BIT(5)
++#define PMCR_FORCE_TX_FC_EN BIT(4)
+ #define PMCR_FORCE_SPEED_1000 BIT(3)
+ #define PMCR_FORCE_SPEED_100 BIT(2)
+ #define PMCR_FORCE_FDX BIT(1)
+ #define PMCR_FORCE_LNK BIT(0)
+-#define PMCR_SPEED_MASK (PMCR_FORCE_SPEED_100 | \
+- PMCR_FORCE_SPEED_1000)
+-#define MT7531_FORCE_LNK BIT(31)
+-#define MT7531_FORCE_SPD BIT(30)
+-#define MT7531_FORCE_DPX BIT(29)
+-#define MT7531_FORCE_RX_FC BIT(28)
+-#define MT7531_FORCE_TX_FC BIT(27)
+-#define MT7531_FORCE_EEE100 BIT(26)
+-#define MT7531_FORCE_EEE1G BIT(25)
+-#define MT7531_FORCE_MODE (MT7531_FORCE_LNK | \
+- MT7531_FORCE_SPD | \
+- MT7531_FORCE_DPX | \
+- MT7531_FORCE_RX_FC | \
+- MT7531_FORCE_TX_FC | \
+- MT7531_FORCE_EEE100 | \
+- MT7531_FORCE_EEE1G)
+-#define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \
+- PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \
+- PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
+- PMCR_FORCE_FDX | PMCR_FORCE_LNK | \
+- PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100)
++#define MT7531_FORCE_MODE_LNK BIT(31)
++#define MT7531_FORCE_MODE_SPD BIT(30)
++#define MT7531_FORCE_MODE_DPX BIT(29)
++#define MT7531_FORCE_MODE_RX_FC BIT(28)
++#define MT7531_FORCE_MODE_TX_FC BIT(27)
++#define MT7531_FORCE_MODE_EEE100 BIT(26)
++#define MT7531_FORCE_MODE_EEE1G BIT(25)
++#define MT7531_FORCE_MODE_MASK (MT7531_FORCE_MODE_LNK | \
++ MT7531_FORCE_MODE_SPD | \
++ MT7531_FORCE_MODE_DPX | \
++ MT7531_FORCE_MODE_RX_FC | \
++ MT7531_FORCE_MODE_TX_FC | \
++ MT7531_FORCE_MODE_EEE100 | \
++ MT7531_FORCE_MODE_EEE1G)
++#define PMCR_LINK_SETTINGS_MASK (PMCR_MAC_TX_EN | PMCR_MAC_RX_EN | \
++ PMCR_FORCE_EEE1G | \
++ PMCR_FORCE_EEE100 | \
++ PMCR_FORCE_RX_FC_EN | \
++ PMCR_FORCE_TX_FC_EN | \
++ PMCR_FORCE_SPEED_1000 | \
++ PMCR_FORCE_SPEED_100 | \
++ PMCR_FORCE_FDX | PMCR_FORCE_LNK)
+
+ #define MT7530_PMEEECR_P(x) (0x3004 + (x) * 0x100)
+ #define WAKEUP_TIME_1000(x) (((x) & 0xFF) << 24)
--- /dev/null
+From 875ec5b67ab88e969b171e6e9ea803e3ed759614 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:10 +0300
+Subject: [PATCH 03/15] net: dsa: mt7530: rename p5_intf_sel and use only for
+ MT7530 switch
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The p5_intf_sel pointer is used to store the information of whether PHY
+muxing is used or not. PHY muxing is a feature specific to port 5 of the
+MT7530 switch. Do not use it for other switch models.
+
+Rename the pointer to p5_mode to store the mode the port is being used in.
+Rename the p5_interface_select enum to mt7530_p5_mode, the string
+representation to mt7530_p5_mode_str, and the enum elements.
+
+If PHY muxing is not detected, the default mode, GMAC5, will be used.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 62 +++++++++++++++++-----------------------
+ drivers/net/dsa/mt7530.h | 15 +++++-----
+ 2 files changed, 33 insertions(+), 44 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -850,19 +850,15 @@ mt7530_set_ageing_time(struct dsa_switch
+ return 0;
+ }
+
+-static const char *p5_intf_modes(unsigned int p5_interface)
++static const char *mt7530_p5_mode_str(unsigned int mode)
+ {
+- switch (p5_interface) {
+- case P5_DISABLED:
+- return "DISABLED";
+- case P5_INTF_SEL_PHY_P0:
+- return "PHY P0";
+- case P5_INTF_SEL_PHY_P4:
+- return "PHY P4";
+- case P5_INTF_SEL_GMAC5:
+- return "GMAC5";
++ switch (mode) {
++ case MUX_PHY_P0:
++ return "MUX PHY P0";
++ case MUX_PHY_P4:
++ return "MUX PHY P4";
+ default:
+- return "unknown";
++ return "GMAC5";
+ }
+ }
+
+@@ -879,23 +875,23 @@ static void mt7530_setup_port5(struct ds
+ val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS;
+ val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL;
+
+- switch (priv->p5_intf_sel) {
+- case P5_INTF_SEL_PHY_P0:
+- /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */
++ switch (priv->p5_mode) {
++ /* MUX_PHY_P0: P0 -> P5 -> SoC MAC */
++ case MUX_PHY_P0:
+ val |= MHWTRAP_PHY0_SEL;
+ fallthrough;
+- case P5_INTF_SEL_PHY_P4:
+- /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */
++
++ /* MUX_PHY_P4: P4 -> P5 -> SoC MAC */
++ case MUX_PHY_P4:
+ val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
+
+ /* Setup the MAC by default for the cpu port */
+ mt7530_write(priv, MT753X_PMCR_P(5), 0x56300);
+ break;
+- case P5_INTF_SEL_GMAC5:
+- /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */
+- val &= ~MHWTRAP_P5_DIS;
+- break;
++
++ /* GMAC5: P5 -> SoC MAC or external PHY */
+ default:
++ val &= ~MHWTRAP_P5_DIS;
+ break;
+ }
+
+@@ -923,8 +919,8 @@ static void mt7530_setup_port5(struct ds
+
+ mt7530_write(priv, MT7530_MHWTRAP, val);
+
+- dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n",
+- val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface));
++ dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, mode=%s, phy-mode=%s\n", val,
++ mt7530_p5_mode_str(priv->p5_mode), phy_modes(interface));
+
+ mutex_unlock(&priv->reg_mutex);
+ }
+@@ -2467,13 +2463,11 @@ mt7530_setup(struct dsa_switch *ds)
+ if (ret)
+ return ret;
+
+- /* Setup port 5 */
+- if (!dsa_is_unused_port(ds, 5)) {
+- priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
+- } else {
++ /* Check for PHY muxing on port 5 */
++ if (dsa_is_unused_port(ds, 5)) {
+ /* Scan the ethernet nodes. Look for GMAC1, lookup the used PHY.
+- * Set priv->p5_intf_sel to the appropriate value if PHY muxing
+- * is detected.
++ * Set priv->p5_mode to the appropriate value if PHY muxing is
++ * detected.
+ */
+ for_each_child_of_node(dn, mac_np) {
+ if (!of_device_is_compatible(mac_np,
+@@ -2497,17 +2491,16 @@ mt7530_setup(struct dsa_switch *ds)
+ }
+ id = of_mdio_parse_addr(ds->dev, phy_node);
+ if (id == 0)
+- priv->p5_intf_sel = P5_INTF_SEL_PHY_P0;
++ priv->p5_mode = MUX_PHY_P0;
+ if (id == 4)
+- priv->p5_intf_sel = P5_INTF_SEL_PHY_P4;
++ priv->p5_mode = MUX_PHY_P4;
+ }
+ of_node_put(mac_np);
+ of_node_put(phy_node);
+ break;
+ }
+
+- if (priv->p5_intf_sel == P5_INTF_SEL_PHY_P0 ||
+- priv->p5_intf_sel == P5_INTF_SEL_PHY_P4)
++ if (priv->p5_mode == MUX_PHY_P0 || priv->p5_mode == MUX_PHY_P4)
+ mt7530_setup_port5(ds, interface);
+ }
+
+@@ -2645,9 +2638,6 @@ mt7531_setup(struct dsa_switch *ds)
+ MT7531_EXT_P_MDIO_12);
+ }
+
+- if (!dsa_is_unused_port(ds, 5))
+- priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
+-
+ mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
+ MT7531_GPIO0_INTERRUPT);
+
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -708,12 +708,11 @@ struct mt7530_port {
+ struct phylink_pcs *sgmii_pcs;
+ };
+
+-/* Port 5 interface select definitions */
+-enum p5_interface_select {
+- P5_DISABLED,
+- P5_INTF_SEL_PHY_P0,
+- P5_INTF_SEL_PHY_P4,
+- P5_INTF_SEL_GMAC5,
++/* Port 5 mode definitions of the MT7530 switch */
++enum mt7530_p5_mode {
++ GMAC5,
++ MUX_PHY_P0,
++ MUX_PHY_P4,
+ };
+
+ struct mt7530_priv;
+@@ -769,7 +768,7 @@ struct mt753x_info {
+ * @ports: Holding the state among ports
+ * @reg_mutex: The lock for protecting among process accessing
+ * registers
+- * @p5_intf_sel: Holding the current port 5 interface select
++ * @p5_mode: Holding the current mode of port 5 of the MT7530 switch
+ * @p5_sgmii: Flag for distinguishing if port 5 of the MT7531 switch
+ * has got SGMII
+ * @irq: IRQ number of the switch
+@@ -791,7 +790,7 @@ struct mt7530_priv {
+ const struct mt753x_info *info;
+ unsigned int id;
+ bool mcm;
+- enum p5_interface_select p5_intf_sel;
++ enum mt7530_p5_mode p5_mode;
+ bool p5_sgmii;
+ u8 mirror_rx;
+ u8 mirror_tx;
--- /dev/null
+From 83fe3df057e641cd0e88425e579d7a5a370ca430 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:11 +0300
+Subject: [PATCH 04/15] net: dsa: mt7530: rename mt753x_bpdu_port_fw enum to
+ mt753x_to_cpu_fw
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The mt753x_bpdu_port_fw enum is globally used for manipulating the process
+of deciding the forwardable ports, specifically concerning the CPU port(s).
+Therefore, rename it and the values in it to mt753x_to_cpu_fw.
+
+Change FOLLOW_MFC to SYSTEM_DEFAULT to be on par with the switch documents.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 44 ++++++++++-------------
+ drivers/net/dsa/mt7530.h | 76 ++++++++++++++++++++--------------------
+ 2 files changed, 56 insertions(+), 64 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -1100,42 +1100,34 @@ mt753x_trap_frames(struct mt7530_priv *p
+ * VLAN-untagged.
+ */
+ mt7530_rmw(priv, MT753X_BPC,
+- MT753X_PAE_BPDU_FR | MT753X_PAE_EG_TAG_MASK |
+- MT753X_PAE_PORT_FW_MASK | MT753X_BPDU_EG_TAG_MASK |
+- MT753X_BPDU_PORT_FW_MASK,
+- MT753X_PAE_BPDU_FR |
+- MT753X_PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
+- MT753X_PAE_PORT_FW(MT753X_BPDU_CPU_ONLY) |
+- MT753X_BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
+- MT753X_BPDU_CPU_ONLY);
++ PAE_BPDU_FR | PAE_EG_TAG_MASK | PAE_PORT_FW_MASK |
++ BPDU_EG_TAG_MASK | BPDU_PORT_FW_MASK,
++ PAE_BPDU_FR | PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
++ PAE_PORT_FW(TO_CPU_FW_CPU_ONLY) |
++ BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
++ TO_CPU_FW_CPU_ONLY);
+
+ /* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and egress
+ * them VLAN-untagged.
+ */
+ mt7530_rmw(priv, MT753X_RGAC1,
+- MT753X_R02_BPDU_FR | MT753X_R02_EG_TAG_MASK |
+- MT753X_R02_PORT_FW_MASK | MT753X_R01_BPDU_FR |
+- MT753X_R01_EG_TAG_MASK | MT753X_R01_PORT_FW_MASK,
+- MT753X_R02_BPDU_FR |
+- MT753X_R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
+- MT753X_R02_PORT_FW(MT753X_BPDU_CPU_ONLY) |
+- MT753X_R01_BPDU_FR |
+- MT753X_R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
+- MT753X_BPDU_CPU_ONLY);
++ R02_BPDU_FR | R02_EG_TAG_MASK | R02_PORT_FW_MASK |
++ R01_BPDU_FR | R01_EG_TAG_MASK | R01_PORT_FW_MASK,
++ R02_BPDU_FR | R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
++ R02_PORT_FW(TO_CPU_FW_CPU_ONLY) | R01_BPDU_FR |
++ R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
++ TO_CPU_FW_CPU_ONLY);
+
+ /* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and egress
+ * them VLAN-untagged.
+ */
+ mt7530_rmw(priv, MT753X_RGAC2,
+- MT753X_R0E_BPDU_FR | MT753X_R0E_EG_TAG_MASK |
+- MT753X_R0E_PORT_FW_MASK | MT753X_R03_BPDU_FR |
+- MT753X_R03_EG_TAG_MASK | MT753X_R03_PORT_FW_MASK,
+- MT753X_R0E_BPDU_FR |
+- MT753X_R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
+- MT753X_R0E_PORT_FW(MT753X_BPDU_CPU_ONLY) |
+- MT753X_R03_BPDU_FR |
+- MT753X_R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
+- MT753X_BPDU_CPU_ONLY);
++ R0E_BPDU_FR | R0E_EG_TAG_MASK | R0E_PORT_FW_MASK |
++ R03_BPDU_FR | R03_EG_TAG_MASK | R03_PORT_FW_MASK,
++ R0E_BPDU_FR | R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
++ R0E_PORT_FW(TO_CPU_FW_CPU_ONLY) | R03_BPDU_FR |
++ R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
++ TO_CPU_FW_CPU_ONLY);
+ }
+
+ static void
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -67,47 +67,47 @@ enum mt753x_id {
+ #define MT753X_MIRROR_MASK(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
+ MT7531_MIRROR_MASK : MIRROR_MASK)
+
+-/* Registers for BPDU and PAE frame control*/
++/* Register for BPDU and PAE frame control */
+ #define MT753X_BPC 0x24
+-#define MT753X_PAE_BPDU_FR BIT(25)
+-#define MT753X_PAE_EG_TAG_MASK GENMASK(24, 22)
+-#define MT753X_PAE_EG_TAG(x) FIELD_PREP(MT753X_PAE_EG_TAG_MASK, x)
+-#define MT753X_PAE_PORT_FW_MASK GENMASK(18, 16)
+-#define MT753X_PAE_PORT_FW(x) FIELD_PREP(MT753X_PAE_PORT_FW_MASK, x)
+-#define MT753X_BPDU_EG_TAG_MASK GENMASK(8, 6)
+-#define MT753X_BPDU_EG_TAG(x) FIELD_PREP(MT753X_BPDU_EG_TAG_MASK, x)
+-#define MT753X_BPDU_PORT_FW_MASK GENMASK(2, 0)
++#define PAE_BPDU_FR BIT(25)
++#define PAE_EG_TAG_MASK GENMASK(24, 22)
++#define PAE_EG_TAG(x) FIELD_PREP(PAE_EG_TAG_MASK, x)
++#define PAE_PORT_FW_MASK GENMASK(18, 16)
++#define PAE_PORT_FW(x) FIELD_PREP(PAE_PORT_FW_MASK, x)
++#define BPDU_EG_TAG_MASK GENMASK(8, 6)
++#define BPDU_EG_TAG(x) FIELD_PREP(BPDU_EG_TAG_MASK, x)
++#define BPDU_PORT_FW_MASK GENMASK(2, 0)
+
+-/* Register for :01 and :02 MAC DA frame control */
++/* Register for 01-80-C2-00-00-[01,02] MAC DA frame control */
+ #define MT753X_RGAC1 0x28
+-#define MT753X_R02_BPDU_FR BIT(25)
+-#define MT753X_R02_EG_TAG_MASK GENMASK(24, 22)
+-#define MT753X_R02_EG_TAG(x) FIELD_PREP(MT753X_R02_EG_TAG_MASK, x)
+-#define MT753X_R02_PORT_FW_MASK GENMASK(18, 16)
+-#define MT753X_R02_PORT_FW(x) FIELD_PREP(MT753X_R02_PORT_FW_MASK, x)
+-#define MT753X_R01_BPDU_FR BIT(9)
+-#define MT753X_R01_EG_TAG_MASK GENMASK(8, 6)
+-#define MT753X_R01_EG_TAG(x) FIELD_PREP(MT753X_R01_EG_TAG_MASK, x)
+-#define MT753X_R01_PORT_FW_MASK GENMASK(2, 0)
++#define R02_BPDU_FR BIT(25)
++#define R02_EG_TAG_MASK GENMASK(24, 22)
++#define R02_EG_TAG(x) FIELD_PREP(R02_EG_TAG_MASK, x)
++#define R02_PORT_FW_MASK GENMASK(18, 16)
++#define R02_PORT_FW(x) FIELD_PREP(R02_PORT_FW_MASK, x)
++#define R01_BPDU_FR BIT(9)
++#define R01_EG_TAG_MASK GENMASK(8, 6)
++#define R01_EG_TAG(x) FIELD_PREP(R01_EG_TAG_MASK, x)
++#define R01_PORT_FW_MASK GENMASK(2, 0)
+
+-/* Register for :03 and :0E MAC DA frame control */
++/* Register for 01-80-C2-00-00-[03,0E] MAC DA frame control */
+ #define MT753X_RGAC2 0x2c
+-#define MT753X_R0E_BPDU_FR BIT(25)
+-#define MT753X_R0E_EG_TAG_MASK GENMASK(24, 22)
+-#define MT753X_R0E_EG_TAG(x) FIELD_PREP(MT753X_R0E_EG_TAG_MASK, x)
+-#define MT753X_R0E_PORT_FW_MASK GENMASK(18, 16)
+-#define MT753X_R0E_PORT_FW(x) FIELD_PREP(MT753X_R0E_PORT_FW_MASK, x)
+-#define MT753X_R03_BPDU_FR BIT(9)
+-#define MT753X_R03_EG_TAG_MASK GENMASK(8, 6)
+-#define MT753X_R03_EG_TAG(x) FIELD_PREP(MT753X_R03_EG_TAG_MASK, x)
+-#define MT753X_R03_PORT_FW_MASK GENMASK(2, 0)
++#define R0E_BPDU_FR BIT(25)
++#define R0E_EG_TAG_MASK GENMASK(24, 22)
++#define R0E_EG_TAG(x) FIELD_PREP(R0E_EG_TAG_MASK, x)
++#define R0E_PORT_FW_MASK GENMASK(18, 16)
++#define R0E_PORT_FW(x) FIELD_PREP(R0E_PORT_FW_MASK, x)
++#define R03_BPDU_FR BIT(9)
++#define R03_EG_TAG_MASK GENMASK(8, 6)
++#define R03_EG_TAG(x) FIELD_PREP(R03_EG_TAG_MASK, x)
++#define R03_PORT_FW_MASK GENMASK(2, 0)
+
+-enum mt753x_bpdu_port_fw {
+- MT753X_BPDU_FOLLOW_MFC,
+- MT753X_BPDU_CPU_EXCLUDE = 4,
+- MT753X_BPDU_CPU_INCLUDE = 5,
+- MT753X_BPDU_CPU_ONLY = 6,
+- MT753X_BPDU_DROP = 7,
++enum mt753x_to_cpu_fw {
++ TO_CPU_FW_SYSTEM_DEFAULT,
++ TO_CPU_FW_CPU_EXCLUDE = 4,
++ TO_CPU_FW_CPU_INCLUDE = 5,
++ TO_CPU_FW_CPU_ONLY = 6,
++ TO_CPU_FW_DROP = 7,
+ };
+
+ /* Registers for address table access */
--- /dev/null
+From 1dbc1bdc2869e6d2929235c70d64e393aa5a5fa2 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:12 +0300
+Subject: [PATCH 05/15] net: dsa: mt7530: refactor MT7530_MFC and MT7531_CFC,
+ add MT7531_QRY_FFP
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The MT7530_MFC register is on MT7530, MT7531, and the switch on the MT7988
+SoC. Rename it to MT753X_MFC. Bit 7 to 0 differs between MT7530 and
+MT7531/MT7988. Add MT7530 prefix to these definitions, and define the
+IGMP/MLD Query Frame Flooding Ports mask for MT7531.
+
+Rename the cases of MIRROR_MASK to MIRROR_PORT_MASK.
+
+Move mt753x_mirror_port_get() and mt753x_port_mirror_set() to mt7530.h as
+macros.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 38 ++++++++--------------
+ drivers/net/dsa/mt7530.h | 69 +++++++++++++++++++++++++---------------
+ 2 files changed, 57 insertions(+), 50 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -1140,7 +1140,7 @@ mt753x_cpu_port_enable(struct dsa_switch
+ PORT_SPEC_TAG);
+
+ /* Enable flooding on the CPU port */
+- mt7530_set(priv, MT7530_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) |
++ mt7530_set(priv, MT753X_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) |
+ UNU_FFP(BIT(port)));
+
+ /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on
+@@ -1304,15 +1304,15 @@ mt7530_port_bridge_flags(struct dsa_swit
+ flags.val & BR_LEARNING ? 0 : SA_DIS);
+
+ if (flags.mask & BR_FLOOD)
+- mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)),
++ mt7530_rmw(priv, MT753X_MFC, UNU_FFP(BIT(port)),
+ flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0);
+
+ if (flags.mask & BR_MCAST_FLOOD)
+- mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)),
++ mt7530_rmw(priv, MT753X_MFC, UNM_FFP(BIT(port)),
+ flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0);
+
+ if (flags.mask & BR_BCAST_FLOOD)
+- mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)),
++ mt7530_rmw(priv, MT753X_MFC, BC_FFP(BIT(port)),
+ flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0);
+
+ return 0;
+@@ -1848,20 +1848,6 @@ mt7530_port_vlan_del(struct dsa_switch *
+ return 0;
+ }
+
+-static int mt753x_mirror_port_get(unsigned int id, u32 val)
+-{
+- return (id == ID_MT7531 || id == ID_MT7988) ?
+- MT7531_MIRROR_PORT_GET(val) :
+- MIRROR_PORT(val);
+-}
+-
+-static int mt753x_mirror_port_set(unsigned int id, u32 val)
+-{
+- return (id == ID_MT7531 || id == ID_MT7988) ?
+- MT7531_MIRROR_PORT_SET(val) :
+- MIRROR_PORT(val);
+-}
+-
+ static int mt753x_port_mirror_add(struct dsa_switch *ds, int port,
+ struct dsa_mall_mirror_tc_entry *mirror,
+ bool ingress, struct netlink_ext_ack *extack)
+@@ -1877,14 +1863,14 @@ static int mt753x_port_mirror_add(struct
+ val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
+
+ /* MT7530 only supports one monitor port */
+- monitor_port = mt753x_mirror_port_get(priv->id, val);
++ monitor_port = MT753X_MIRROR_PORT_GET(priv->id, val);
+ if (val & MT753X_MIRROR_EN(priv->id) &&
+ monitor_port != mirror->to_local_port)
+ return -EEXIST;
+
+ val |= MT753X_MIRROR_EN(priv->id);
+- val &= ~MT753X_MIRROR_MASK(priv->id);
+- val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port);
++ val &= ~MT753X_MIRROR_PORT_MASK(priv->id);
++ val |= MT753X_MIRROR_PORT_SET(priv->id, mirror->to_local_port);
+ mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
+
+ val = mt7530_read(priv, MT7530_PCR_P(port));
+@@ -2524,7 +2510,7 @@ mt7531_setup_common(struct dsa_switch *d
+ mt7530_mib_reset(ds);
+
+ /* Disable flooding on all ports */
+- mt7530_clear(priv, MT7530_MFC, BC_FFP_MASK | UNM_FFP_MASK |
++ mt7530_clear(priv, MT753X_MFC, BC_FFP_MASK | UNM_FFP_MASK |
+ UNU_FFP_MASK);
+
+ for (i = 0; i < MT7530_NUM_PORTS; i++) {
+@@ -3086,10 +3072,12 @@ mt753x_conduit_state_change(struct dsa_s
+ else
+ priv->active_cpu_ports &= ~mask;
+
+- if (priv->active_cpu_ports)
+- val = CPU_EN | CPU_PORT(__ffs(priv->active_cpu_ports));
++ if (priv->active_cpu_ports) {
++ val = MT7530_CPU_EN |
++ MT7530_CPU_PORT(__ffs(priv->active_cpu_ports));
++ }
+
+- mt7530_rmw(priv, MT7530_MFC, CPU_EN | CPU_PORT_MASK, val);
++ mt7530_rmw(priv, MT753X_MFC, MT7530_CPU_EN | MT7530_CPU_PORT_MASK, val);
+ }
+
+ static int mt7988_setup(struct dsa_switch *ds)
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -36,36 +36,55 @@ enum mt753x_id {
+ #define MT753X_AGC 0xc
+ #define LOCAL_EN BIT(7)
+
+-/* Registers to mac forward control for unknown frames */
+-#define MT7530_MFC 0x10
+-#define BC_FFP(x) (((x) & 0xff) << 24)
+-#define BC_FFP_MASK BC_FFP(~0)
+-#define UNM_FFP(x) (((x) & 0xff) << 16)
+-#define UNM_FFP_MASK UNM_FFP(~0)
+-#define UNU_FFP(x) (((x) & 0xff) << 8)
+-#define UNU_FFP_MASK UNU_FFP(~0)
+-#define CPU_EN BIT(7)
+-#define CPU_PORT_MASK GENMASK(6, 4)
+-#define CPU_PORT(x) FIELD_PREP(CPU_PORT_MASK, x)
+-#define MIRROR_EN BIT(3)
+-#define MIRROR_PORT(x) ((x) & 0x7)
+-#define MIRROR_MASK 0x7
++/* Register for MAC forward control */
++#define MT753X_MFC 0x10
++#define BC_FFP_MASK GENMASK(31, 24)
++#define BC_FFP(x) FIELD_PREP(BC_FFP_MASK, x)
++#define UNM_FFP_MASK GENMASK(23, 16)
++#define UNM_FFP(x) FIELD_PREP(UNM_FFP_MASK, x)
++#define UNU_FFP_MASK GENMASK(15, 8)
++#define UNU_FFP(x) FIELD_PREP(UNU_FFP_MASK, x)
++#define MT7530_CPU_EN BIT(7)
++#define MT7530_CPU_PORT_MASK GENMASK(6, 4)
++#define MT7530_CPU_PORT(x) FIELD_PREP(MT7530_CPU_PORT_MASK, x)
++#define MT7530_MIRROR_EN BIT(3)
++#define MT7530_MIRROR_PORT_MASK GENMASK(2, 0)
++#define MT7530_MIRROR_PORT_GET(x) FIELD_GET(MT7530_MIRROR_PORT_MASK, x)
++#define MT7530_MIRROR_PORT_SET(x) FIELD_PREP(MT7530_MIRROR_PORT_MASK, x)
++#define MT7531_QRY_FFP_MASK GENMASK(7, 0)
++#define MT7531_QRY_FFP(x) FIELD_PREP(MT7531_QRY_FFP_MASK, x)
+
+-/* Registers for CPU forward control */
++/* Register for CPU forward control */
+ #define MT7531_CFC 0x4
+ #define MT7531_MIRROR_EN BIT(19)
+-#define MT7531_MIRROR_MASK (MIRROR_MASK << 16)
+-#define MT7531_MIRROR_PORT_GET(x) (((x) >> 16) & MIRROR_MASK)
+-#define MT7531_MIRROR_PORT_SET(x) (((x) & MIRROR_MASK) << 16)
++#define MT7531_MIRROR_PORT_MASK GENMASK(18, 16)
++#define MT7531_MIRROR_PORT_GET(x) FIELD_GET(MT7531_MIRROR_PORT_MASK, x)
++#define MT7531_MIRROR_PORT_SET(x) FIELD_PREP(MT7531_MIRROR_PORT_MASK, x)
+ #define MT7531_CPU_PMAP_MASK GENMASK(7, 0)
+ #define MT7531_CPU_PMAP(x) FIELD_PREP(MT7531_CPU_PMAP_MASK, x)
+
+-#define MT753X_MIRROR_REG(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
+- MT7531_CFC : MT7530_MFC)
+-#define MT753X_MIRROR_EN(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
+- MT7531_MIRROR_EN : MIRROR_EN)
+-#define MT753X_MIRROR_MASK(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
+- MT7531_MIRROR_MASK : MIRROR_MASK)
++#define MT753X_MIRROR_REG(id) ((id == ID_MT7531 || \
++ id == ID_MT7988) ? \
++ MT7531_CFC : MT753X_MFC)
++
++#define MT753X_MIRROR_EN(id) ((id == ID_MT7531 || \
++ id == ID_MT7988) ? \
++ MT7531_MIRROR_EN : MT7530_MIRROR_EN)
++
++#define MT753X_MIRROR_PORT_MASK(id) ((id == ID_MT7531 || \
++ id == ID_MT7988) ? \
++ MT7531_MIRROR_PORT_MASK : \
++ MT7530_MIRROR_PORT_MASK)
++
++#define MT753X_MIRROR_PORT_GET(id, val) ((id == ID_MT7531 || \
++ id == ID_MT7988) ? \
++ MT7531_MIRROR_PORT_GET(val) : \
++ MT7530_MIRROR_PORT_GET(val))
++
++#define MT753X_MIRROR_PORT_SET(id, val) ((id == ID_MT7531 || \
++ id == ID_MT7988) ? \
++ MT7531_MIRROR_PORT_SET(val) : \
++ MT7530_MIRROR_PORT_SET(val))
+
+ /* Register for BPDU and PAE frame control */
+ #define MT753X_BPC 0x24
--- /dev/null
+From 3ccf67597d35c06a7319e407b1c42f78a7966779 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:13 +0300
+Subject: [PATCH 06/15] net: dsa: mt7530: refactor MT7530_HWTRAP and
+ MT7530_MHWTRAP
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The MT7530_HWTRAP and MT7530_MHWTRAP registers are on MT7530 and MT7531.
+It's called hardware trap on MT7530, software trap on MT7531. That's
+because some bits of the trap on MT7530 cannot be modified by software
+whilst all bits of the trap on MT7531 can. Rename the definitions for them
+to MT753X_TRAP and MT753X_MTRAP. Add MT7530 and MT7531 prefixes to the
+definitions specific to the switch model.
+
+Remove the extra parentheses from MT7530_XTAL_40MHZ and MT7530_XTAL_20MHZ.
+
+Rename MHWTRAP_PHY0_SEL, MHWTRAP_MANUAL, and MHWTRAP_PHY_ACCESS to be on
+par with the "MT7621 Giga Switch Programming Guide v0.3" document.
+
+Make an enumaration for the XTAL frequency. Set the data type of the xtal
+variable on mt7531_pll_setup() to it.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 59 ++++++++++++++++++++--------------------
+ drivers/net/dsa/mt7530.h | 50 ++++++++++++++++------------------
+ 2 files changed, 54 insertions(+), 55 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -403,23 +403,23 @@ mt7530_setup_port6(struct dsa_switch *ds
+
+ mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, P6_INTF_MODE(1));
+
+- xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK;
++ xtal = mt7530_read(priv, MT753X_MTRAP) & MT7530_XTAL_MASK;
+
+- if (xtal == HWTRAP_XTAL_25MHZ)
++ if (xtal == MT7530_XTAL_25MHZ)
+ ssc_delta = 0x57;
+ else
+ ssc_delta = 0x87;
+
+ if (priv->id == ID_MT7621) {
+ /* PLL frequency: 125MHz: 1.0GBit */
+- if (xtal == HWTRAP_XTAL_40MHZ)
++ if (xtal == MT7530_XTAL_40MHZ)
+ ncpo1 = 0x0640;
+- if (xtal == HWTRAP_XTAL_25MHZ)
++ if (xtal == MT7530_XTAL_25MHZ)
+ ncpo1 = 0x0a00;
+ } else { /* PLL frequency: 250MHz: 2.0Gbit */
+- if (xtal == HWTRAP_XTAL_40MHZ)
++ if (xtal == MT7530_XTAL_40MHZ)
+ ncpo1 = 0x0c80;
+- if (xtal == HWTRAP_XTAL_25MHZ)
++ if (xtal == MT7530_XTAL_25MHZ)
+ ncpo1 = 0x1400;
+ }
+
+@@ -442,19 +442,20 @@ mt7530_setup_port6(struct dsa_switch *ds
+ static void
+ mt7531_pll_setup(struct mt7530_priv *priv)
+ {
++ enum mt7531_xtal_fsel xtal;
+ u32 top_sig;
+ u32 hwstrap;
+- u32 xtal;
+ u32 val;
+
+ val = mt7530_read(priv, MT7531_CREV);
+ top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR);
+- hwstrap = mt7530_read(priv, MT7531_HWTRAP);
++ hwstrap = mt7530_read(priv, MT753X_TRAP);
+ if ((val & CHIP_REV_M) > 0)
+- xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ :
+- HWTRAP_XTAL_FSEL_25MHZ;
++ xtal = (top_sig & PAD_MCM_SMI_EN) ? MT7531_XTAL_FSEL_40MHZ :
++ MT7531_XTAL_FSEL_25MHZ;
+ else
+- xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK;
++ xtal = (hwstrap & MT7531_XTAL25) ? MT7531_XTAL_FSEL_25MHZ :
++ MT7531_XTAL_FSEL_40MHZ;
+
+ /* Step 1 : Disable MT7531 COREPLL */
+ val = mt7530_read(priv, MT7531_PLLGP_EN);
+@@ -483,13 +484,13 @@ mt7531_pll_setup(struct mt7530_priv *pri
+ usleep_range(25, 35);
+
+ switch (xtal) {
+- case HWTRAP_XTAL_FSEL_25MHZ:
++ case MT7531_XTAL_FSEL_25MHZ:
+ val = mt7530_read(priv, MT7531_PLLGP_CR0);
+ val &= ~RG_COREPLL_SDM_PCW_M;
+ val |= 0x140000 << RG_COREPLL_SDM_PCW_S;
+ mt7530_write(priv, MT7531_PLLGP_CR0, val);
+ break;
+- case HWTRAP_XTAL_FSEL_40MHZ:
++ case MT7531_XTAL_FSEL_40MHZ:
+ val = mt7530_read(priv, MT7531_PLLGP_CR0);
+ val &= ~RG_COREPLL_SDM_PCW_M;
+ val |= 0x190000 << RG_COREPLL_SDM_PCW_S;
+@@ -870,20 +871,20 @@ static void mt7530_setup_port5(struct ds
+
+ mutex_lock(&priv->reg_mutex);
+
+- val = mt7530_read(priv, MT7530_MHWTRAP);
++ val = mt7530_read(priv, MT753X_MTRAP);
+
+- val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS;
+- val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL;
++ val |= MT7530_CHG_TRAP | MT7530_P5_MAC_SEL | MT7530_P5_DIS;
++ val &= ~MT7530_P5_RGMII_MODE & ~MT7530_P5_PHY0_SEL;
+
+ switch (priv->p5_mode) {
+ /* MUX_PHY_P0: P0 -> P5 -> SoC MAC */
+ case MUX_PHY_P0:
+- val |= MHWTRAP_PHY0_SEL;
++ val |= MT7530_P5_PHY0_SEL;
+ fallthrough;
+
+ /* MUX_PHY_P4: P4 -> P5 -> SoC MAC */
+ case MUX_PHY_P4:
+- val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
++ val &= ~MT7530_P5_MAC_SEL & ~MT7530_P5_DIS;
+
+ /* Setup the MAC by default for the cpu port */
+ mt7530_write(priv, MT753X_PMCR_P(5), 0x56300);
+@@ -891,13 +892,13 @@ static void mt7530_setup_port5(struct ds
+
+ /* GMAC5: P5 -> SoC MAC or external PHY */
+ default:
+- val &= ~MHWTRAP_P5_DIS;
++ val &= ~MT7530_P5_DIS;
+ break;
+ }
+
+ /* Setup RGMII settings */
+ if (phy_interface_mode_is_rgmii(interface)) {
+- val |= MHWTRAP_P5_RGMII_MODE;
++ val |= MT7530_P5_RGMII_MODE;
+
+ /* P5 RGMII RX Clock Control: delay setting for 1000M */
+ mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN);
+@@ -917,7 +918,7 @@ static void mt7530_setup_port5(struct ds
+ P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1));
+ }
+
+- mt7530_write(priv, MT7530_MHWTRAP, val);
++ mt7530_write(priv, MT753X_MTRAP, val);
+
+ dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, mode=%s, phy-mode=%s\n", val,
+ mt7530_p5_mode_str(priv->p5_mode), phy_modes(interface));
+@@ -2356,7 +2357,7 @@ mt7530_setup(struct dsa_switch *ds)
+ }
+
+ /* Waiting for MT7530 got to stable */
+- INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
++ INIT_MT7530_DUMMY_POLL(&p, priv, MT753X_TRAP);
+ ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
+ 20, 1000000);
+ if (ret < 0) {
+@@ -2371,7 +2372,7 @@ mt7530_setup(struct dsa_switch *ds)
+ return -ENODEV;
+ }
+
+- if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_20MHZ) {
++ if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_20MHZ) {
+ dev_err(priv->dev,
+ "MT7530 with a 20MHz XTAL is not supported!\n");
+ return -EINVAL;
+@@ -2392,12 +2393,12 @@ mt7530_setup(struct dsa_switch *ds)
+ RD_TAP_MASK, RD_TAP(16));
+
+ /* Enable port 6 */
+- val = mt7530_read(priv, MT7530_MHWTRAP);
+- val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS;
+- val |= MHWTRAP_MANUAL;
+- mt7530_write(priv, MT7530_MHWTRAP, val);
++ val = mt7530_read(priv, MT753X_MTRAP);
++ val &= ~MT7530_P6_DIS & ~MT7530_PHY_INDIRECT_ACCESS;
++ val |= MT7530_CHG_TRAP;
++ mt7530_write(priv, MT753X_MTRAP, val);
+
+- if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_40MHZ)
++ if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_40MHZ)
+ mt7530_pll_setup(priv);
+
+ mt753x_trap_frames(priv);
+@@ -2577,7 +2578,7 @@ mt7531_setup(struct dsa_switch *ds)
+ }
+
+ /* Waiting for MT7530 got to stable */
+- INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
++ INIT_MT7530_DUMMY_POLL(&p, priv, MT753X_TRAP);
+ ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
+ 20, 1000000);
+ if (ret < 0) {
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -495,32 +495,30 @@ enum mt7531_clk_skew {
+ MT7531_CLK_SKEW_REVERSE = 3,
+ };
+
+-/* Register for hw trap status */
+-#define MT7530_HWTRAP 0x7800
+-#define HWTRAP_XTAL_MASK (BIT(10) | BIT(9))
+-#define HWTRAP_XTAL_25MHZ (BIT(10) | BIT(9))
+-#define HWTRAP_XTAL_40MHZ (BIT(10))
+-#define HWTRAP_XTAL_20MHZ (BIT(9))
++/* Register for trap status */
++#define MT753X_TRAP 0x7800
++#define MT7530_XTAL_MASK (BIT(10) | BIT(9))
++#define MT7530_XTAL_25MHZ (BIT(10) | BIT(9))
++#define MT7530_XTAL_40MHZ BIT(10)
++#define MT7530_XTAL_20MHZ BIT(9)
++#define MT7531_XTAL25 BIT(7)
+
+-#define MT7531_HWTRAP 0x7800
+-#define HWTRAP_XTAL_FSEL_MASK BIT(7)
+-#define HWTRAP_XTAL_FSEL_25MHZ BIT(7)
+-#define HWTRAP_XTAL_FSEL_40MHZ 0
+-/* Unique fields of (M)HWSTRAP for MT7531 */
+-#define XTAL_FSEL_S 7
+-#define XTAL_FSEL_M BIT(7)
+-#define PHY_EN BIT(6)
+-#define CHG_STRAP BIT(8)
++/* Register for trap modification */
++#define MT753X_MTRAP 0x7804
++#define MT7530_P5_PHY0_SEL BIT(20)
++#define MT7530_CHG_TRAP BIT(16)
++#define MT7530_P5_MAC_SEL BIT(13)
++#define MT7530_P6_DIS BIT(8)
++#define MT7530_P5_RGMII_MODE BIT(7)
++#define MT7530_P5_DIS BIT(6)
++#define MT7530_PHY_INDIRECT_ACCESS BIT(5)
++#define MT7531_CHG_STRAP BIT(8)
++#define MT7531_PHY_EN BIT(6)
+
+-/* Register for hw trap modification */
+-#define MT7530_MHWTRAP 0x7804
+-#define MHWTRAP_PHY0_SEL BIT(20)
+-#define MHWTRAP_MANUAL BIT(16)
+-#define MHWTRAP_P5_MAC_SEL BIT(13)
+-#define MHWTRAP_P6_DIS BIT(8)
+-#define MHWTRAP_P5_RGMII_MODE BIT(7)
+-#define MHWTRAP_P5_DIS BIT(6)
+-#define MHWTRAP_PHY_ACCESS BIT(5)
++enum mt7531_xtal_fsel {
++ MT7531_XTAL_FSEL_25MHZ,
++ MT7531_XTAL_FSEL_40MHZ,
++};
+
+ /* Register for TOP signal control */
+ #define MT7530_TOP_SIG_CTRL 0x7808
--- /dev/null
+From 2982f395c9a513b168f1e685588f70013cba2f5f Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:14 +0300
+Subject: [PATCH 07/15] net: dsa: mt7530: move MT753X_MTRAP operations for
+ MT7530
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+On MT7530, the media-independent interfaces of port 5 and 6 are controlled
+by the MT7530_P5_DIS and MT7530_P6_DIS bits of the hardware trap. Deal with
+these bits only when the relevant port is being enabled or disabled. This
+ensures that these ports will be disabled when they are not in use.
+
+Do not set MT7530_CHG_TRAP on mt7530_setup_port5() as that's already being
+done on mt7530_setup().
+
+Instead of globally setting MT7530_P5_MAC_SEL, clear it, then set it only
+on the appropriate case.
+
+If PHY muxing is detected, clear MT7530_P5_DIS before calling
+mt7530_setup_port5().
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 38 +++++++++++++++++++++++++++-----------
+ 1 file changed, 27 insertions(+), 11 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -873,8 +873,7 @@ static void mt7530_setup_port5(struct ds
+
+ val = mt7530_read(priv, MT753X_MTRAP);
+
+- val |= MT7530_CHG_TRAP | MT7530_P5_MAC_SEL | MT7530_P5_DIS;
+- val &= ~MT7530_P5_RGMII_MODE & ~MT7530_P5_PHY0_SEL;
++ val &= ~MT7530_P5_PHY0_SEL & ~MT7530_P5_MAC_SEL & ~MT7530_P5_RGMII_MODE;
+
+ switch (priv->p5_mode) {
+ /* MUX_PHY_P0: P0 -> P5 -> SoC MAC */
+@@ -884,15 +883,13 @@ static void mt7530_setup_port5(struct ds
+
+ /* MUX_PHY_P4: P4 -> P5 -> SoC MAC */
+ case MUX_PHY_P4:
+- val &= ~MT7530_P5_MAC_SEL & ~MT7530_P5_DIS;
+-
+ /* Setup the MAC by default for the cpu port */
+ mt7530_write(priv, MT753X_PMCR_P(5), 0x56300);
+ break;
+
+ /* GMAC5: P5 -> SoC MAC or external PHY */
+ default:
+- val &= ~MT7530_P5_DIS;
++ val |= MT7530_P5_MAC_SEL;
+ break;
+ }
+
+@@ -1186,6 +1183,14 @@ mt7530_port_enable(struct dsa_switch *ds
+
+ mutex_unlock(&priv->reg_mutex);
+
++ if (priv->id != ID_MT7530 && priv->id != ID_MT7621)
++ return 0;
++
++ if (port == 5)
++ mt7530_clear(priv, MT753X_MTRAP, MT7530_P5_DIS);
++ else if (port == 6)
++ mt7530_clear(priv, MT753X_MTRAP, MT7530_P6_DIS);
++
+ return 0;
+ }
+
+@@ -1204,6 +1209,14 @@ mt7530_port_disable(struct dsa_switch *d
+ PCR_MATRIX_CLR);
+
+ mutex_unlock(&priv->reg_mutex);
++
++ if (priv->id != ID_MT7530 && priv->id != ID_MT7621)
++ return;
++
++ if (port == 5)
++ mt7530_set(priv, MT753X_MTRAP, MT7530_P5_DIS);
++ else if (port == 6)
++ mt7530_set(priv, MT753X_MTRAP, MT7530_P6_DIS);
+ }
+
+ static int
+@@ -2392,11 +2405,11 @@ mt7530_setup(struct dsa_switch *ds)
+ mt7530_rmw(priv, MT7530_TRGMII_RD(i),
+ RD_TAP_MASK, RD_TAP(16));
+
+- /* Enable port 6 */
+- val = mt7530_read(priv, MT753X_MTRAP);
+- val &= ~MT7530_P6_DIS & ~MT7530_PHY_INDIRECT_ACCESS;
+- val |= MT7530_CHG_TRAP;
+- mt7530_write(priv, MT753X_MTRAP, val);
++ /* Allow modifying the trap and directly access PHY registers via the
++ * MDIO bus the switch is on.
++ */
++ mt7530_rmw(priv, MT753X_MTRAP, MT7530_CHG_TRAP |
++ MT7530_PHY_INDIRECT_ACCESS, MT7530_CHG_TRAP);
+
+ if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_40MHZ)
+ mt7530_pll_setup(priv);
+@@ -2479,8 +2492,11 @@ mt7530_setup(struct dsa_switch *ds)
+ break;
+ }
+
+- if (priv->p5_mode == MUX_PHY_P0 || priv->p5_mode == MUX_PHY_P4)
++ if (priv->p5_mode == MUX_PHY_P0 ||
++ priv->p5_mode == MUX_PHY_P4) {
++ mt7530_clear(priv, MT753X_MTRAP, MT7530_P5_DIS);
+ mt7530_setup_port5(ds, interface);
++ }
+ }
+
+ #ifdef CONFIG_GPIOLIB
--- /dev/null
+From 1f5669efca65564c7533704917f79003c6b36c9c Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:15 +0300
+Subject: [PATCH 08/15] net: dsa: mt7530: return mt7530_setup_mdio &
+ mt7531_setup_common on error
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The mt7530_setup_mdio() and mt7531_setup_common() functions should be
+checked for errors. Return if the functions return a non-zero value.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2658,7 +2658,9 @@ mt7531_setup(struct dsa_switch *ds)
+ 0);
+ }
+
+- mt7531_setup_common(ds);
++ ret = mt7531_setup_common(ds);
++ if (ret)
++ return ret;
+
+ /* Setup VLAN ID 0 for VLAN-unaware bridges */
+ ret = mt7530_setup_vlan0(priv);
+@@ -3017,6 +3019,8 @@ mt753x_setup(struct dsa_switch *ds)
+ ret = mt7530_setup_mdio(priv);
+ if (ret && priv->irq)
+ mt7530_free_irq_common(priv);
++ if (ret)
++ return ret;
+
+ /* Initialise the PCS devices */
+ for (i = 0; i < priv->ds->num_ports; i++) {
--- /dev/null
+From 6cc2d4ccd77509df74b7b8ef46bbc6ba0a571318 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:16 +0300
+Subject: [PATCH 09/15] net: dsa: mt7530: define MAC speed capabilities per
+ switch model
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+With the support of the MT7988 SoC switch, the MAC speed capabilities
+defined on mt753x_phylink_get_caps() won't apply to all switch models
+anymore. Move them to more appropriate locations instead of overwriting
+config->mac_capabilities.
+
+Remove the comment on mt753x_phylink_get_caps() as it's become invalid with
+the support of MT7531 and MT7988 SoC switch.
+
+Add break to case 6 of mt7988_mac_port_get_caps() to be explicit.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 15 ++++++++++-----
+ 1 file changed, 10 insertions(+), 5 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2676,6 +2676,8 @@ mt7531_setup(struct dsa_switch *ds)
+ static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port,
+ struct phylink_config *config)
+ {
++ config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD;
++
+ switch (port) {
+ /* Ports which are connected to switch PHYs. There is no MII pinout. */
+ case 0 ... 4:
+@@ -2707,6 +2709,8 @@ static void mt7531_mac_port_get_caps(str
+ {
+ struct mt7530_priv *priv = ds->priv;
+
++ config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD;
++
+ switch (port) {
+ /* Ports which are connected to switch PHYs. There is no MII pinout. */
+ case 0 ... 4:
+@@ -2746,14 +2750,17 @@ static void mt7988_mac_port_get_caps(str
+ case 0 ... 3:
+ __set_bit(PHY_INTERFACE_MODE_INTERNAL,
+ config->supported_interfaces);
++
++ config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD;
+ break;
+
+ /* Port 6 is connected to SoC's XGMII MAC. There is no MII pinout. */
+ case 6:
+ __set_bit(PHY_INTERFACE_MODE_INTERNAL,
+ config->supported_interfaces);
+- config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
+- MAC_10000FD;
++
++ config->mac_capabilities |= MAC_10000FD;
++ break;
+ }
+ }
+
+@@ -2923,9 +2930,7 @@ static void mt753x_phylink_get_caps(stru
+ {
+ struct mt7530_priv *priv = ds->priv;
+
+- /* This switch only supports full-duplex at 1Gbps */
+- config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
+- MAC_10 | MAC_100 | MAC_1000FD;
++ config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE;
+
+ /* This driver does not make use of the speed, duplex, pause or the
+ * advertisement in its mac_config, so it is safe to mark this driver
--- /dev/null
+From dd0f15fc877c10567699190bce0f55e96f4ad6b5 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:17 +0300
+Subject: [PATCH 10/15] net: dsa: mt7530: get rid of function sanity check
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Get rid of checking whether functions are filled properly. priv->info which
+is an mt753x_info structure is filled and checked for before this check.
+It's unnecessary checking whether it's filled properly.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 7 -------
+ 1 file changed, 7 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -3220,13 +3220,6 @@ mt7530_probe_common(struct mt7530_priv *
+ if (!priv->info)
+ return -EINVAL;
+
+- /* Sanity check if these required device operations are filled
+- * properly.
+- */
+- if (!priv->info->sw_setup || !priv->info->phy_read ||
+- !priv->info->phy_write || !priv->info->mac_port_get_caps)
+- return -EINVAL;
+-
+ priv->id = priv->info->id;
+ priv->dev = dev;
+ priv->ds->priv = priv;
--- /dev/null
+From 2dff9759602b069f97ccc939e15a47ca051b2983 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:18 +0300
+Subject: [PATCH 11/15] net: dsa: mt7530: refactor MT7530_PMEEECR_P()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The MT7530_PMEEECR_P() register is on MT7530, MT7531, and the switch on the
+MT7988 SoC. Rename the definition for them to MT753X_PMEEECR_P(). Use the
+FIELD_PREP and FIELD_GET macros. Rename GET_LPI_THRESH() and
+SET_LPI_THRESH() to LPI_THRESH_GET() and LPI_THRESH_SET().
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 8 ++++----
+ drivers/net/dsa/mt7530.h | 13 +++++++------
+ 2 files changed, 11 insertions(+), 10 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -3048,10 +3048,10 @@ static int mt753x_get_mac_eee(struct dsa
+ struct ethtool_eee *e)
+ {
+ struct mt7530_priv *priv = ds->priv;
+- u32 eeecr = mt7530_read(priv, MT7530_PMEEECR_P(port));
++ u32 eeecr = mt7530_read(priv, MT753X_PMEEECR_P(port));
+
+ e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN);
+- e->tx_lpi_timer = GET_LPI_THRESH(eeecr);
++ e->tx_lpi_timer = LPI_THRESH_GET(eeecr);
+
+ return 0;
+ }
+@@ -3065,11 +3065,11 @@ static int mt753x_set_mac_eee(struct dsa
+ if (e->tx_lpi_timer > 0xFFF)
+ return -EINVAL;
+
+- set = SET_LPI_THRESH(e->tx_lpi_timer);
++ set = LPI_THRESH_SET(e->tx_lpi_timer);
+ if (!e->tx_lpi_enabled)
+ /* Force LPI Mode without a delay */
+ set |= LPI_MODE_EN;
+- mt7530_rmw(priv, MT7530_PMEEECR_P(port), mask, set);
++ mt7530_rmw(priv, MT753X_PMEEECR_P(port), mask, set);
+
+ return 0;
+ }
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -364,13 +364,14 @@ enum mt7530_vlan_port_acc_frm {
+ PMCR_FORCE_SPEED_100 | \
+ PMCR_FORCE_FDX | PMCR_FORCE_LNK)
+
+-#define MT7530_PMEEECR_P(x) (0x3004 + (x) * 0x100)
+-#define WAKEUP_TIME_1000(x) (((x) & 0xFF) << 24)
+-#define WAKEUP_TIME_100(x) (((x) & 0xFF) << 16)
++#define MT753X_PMEEECR_P(x) (0x3004 + (x) * 0x100)
++#define WAKEUP_TIME_1000_MASK GENMASK(31, 24)
++#define WAKEUP_TIME_1000(x) FIELD_PREP(WAKEUP_TIME_1000_MASK, x)
++#define WAKEUP_TIME_100_MASK GENMASK(23, 16)
++#define WAKEUP_TIME_100(x) FIELD_PREP(WAKEUP_TIME_100_MASK, x)
+ #define LPI_THRESH_MASK GENMASK(15, 4)
+-#define LPI_THRESH_SHT 4
+-#define SET_LPI_THRESH(x) (((x) << LPI_THRESH_SHT) & LPI_THRESH_MASK)
+-#define GET_LPI_THRESH(x) (((x) & LPI_THRESH_MASK) >> LPI_THRESH_SHT)
++#define LPI_THRESH_GET(x) FIELD_GET(LPI_THRESH_MASK, x)
++#define LPI_THRESH_SET(x) FIELD_PREP(LPI_THRESH_MASK, x)
+ #define LPI_MODE_EN BIT(0)
+
+ #define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100)
--- /dev/null
+From 21d67c2fabfe40baf33202d3287b67b6c16f8382 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:19 +0300
+Subject: [PATCH 12/15] net: dsa: mt7530: get rid of mac_port_validate member
+ of mt753x_info
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The mac_port_validate member of the mt753x_info structure is not being
+used, remove it. Improve the member description section in the process.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.h | 10 +++-------
+ 1 file changed, 3 insertions(+), 7 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -743,13 +743,12 @@ struct mt753x_pcs {
+
+ /* struct mt753x_info - This is the main data structure for holding the specific
+ * part for each supported device
++ * @id: Holding the identifier to a switch model
++ * @pcs_ops: Holding the pointer to the MAC PCS operations structure
+ * @sw_setup: Holding the handler to a device initialization
+ * @phy_read: Holding the way reading PHY port
+ * @phy_write: Holding the way writing PHY port
+- * @phy_mode_supported: Check if the PHY type is being supported on a certain
+- * port
+- * @mac_port_validate: Holding the way to set addition validate type for a
+- * certan MAC port
++ * @mac_port_get_caps: Holding the handler that provides MAC capabilities
+ * @mac_port_config: Holding the way setting up the PHY attribute to a
+ * certain MAC port
+ */
+@@ -763,9 +762,6 @@ struct mt753x_info {
+ int (*phy_write)(struct mt7530_priv *priv, int port, int regnum, u16 val);
+ void (*mac_port_get_caps)(struct dsa_switch *ds, int port,
+ struct phylink_config *config);
+- void (*mac_port_validate)(struct dsa_switch *ds, int port,
+- phy_interface_t interface,
+- unsigned long *supported);
+ void (*mac_port_config)(struct dsa_switch *ds, int port,
+ unsigned int mode,
+ phy_interface_t interface);
--- /dev/null
+From 6efc8ae3eb0363328f479191a0cf0dc12a16e090 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:20 +0300
+Subject: [PATCH 13/15] net: dsa: mt7530: use priv->ds->num_ports instead of
+ MT7530_NUM_PORTS
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Use priv->ds->num_ports on all for loops which configure the switch
+registers. In the future, the value of MT7530_NUM_PORTS will depend on
+priv->id. Therefore, this change prepares the subdriver for a simpler
+implementation.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -1404,7 +1404,7 @@ mt7530_port_set_vlan_unaware(struct dsa_
+ mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
+ G0_PORT_VID_DEF);
+
+- for (i = 0; i < MT7530_NUM_PORTS; i++) {
++ for (i = 0; i < priv->ds->num_ports; i++) {
+ if (dsa_is_user_port(ds, i) &&
+ dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) {
+ all_user_ports_removed = false;
+@@ -2419,7 +2419,7 @@ mt7530_setup(struct dsa_switch *ds)
+ /* Enable and reset MIB counters */
+ mt7530_mib_reset(ds);
+
+- for (i = 0; i < MT7530_NUM_PORTS; i++) {
++ for (i = 0; i < priv->ds->num_ports; i++) {
+ /* Clear link settings and enable force mode to force link down
+ * on all ports until they're enabled later.
+ */
+@@ -2530,7 +2530,7 @@ mt7531_setup_common(struct dsa_switch *d
+ mt7530_clear(priv, MT753X_MFC, BC_FFP_MASK | UNM_FFP_MASK |
+ UNU_FFP_MASK);
+
+- for (i = 0; i < MT7530_NUM_PORTS; i++) {
++ for (i = 0; i < priv->ds->num_ports; i++) {
+ /* Clear link settings and enable force mode to force link down
+ * on all ports until they're enabled later.
+ */
+@@ -2617,7 +2617,7 @@ mt7531_setup(struct dsa_switch *ds)
+ priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN);
+
+ /* Force link down on all ports before internal reset */
+- for (i = 0; i < MT7530_NUM_PORTS; i++)
++ for (i = 0; i < priv->ds->num_ports; i++)
+ mt7530_write(priv, MT753X_PMCR_P(i), MT7531_FORCE_MODE_LNK);
+
+ /* Reset the switch through internal reset */
--- /dev/null
+From 4794c12e3aefe05dd0063c2b6b0101854b143bac Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:21 +0300
+Subject: [PATCH 14/15] net: dsa: mt7530: do not pass port variable to
+ mt7531_rgmii_setup()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The mt7531_rgmii_setup() function does not use the port variable, do not
+pass the variable to it.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2776,7 +2776,7 @@ mt7530_mac_config(struct dsa_switch *ds,
+ mt7530_setup_port6(priv->ds, interface);
+ }
+
+-static void mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port,
++static void mt7531_rgmii_setup(struct mt7530_priv *priv,
+ phy_interface_t interface,
+ struct phy_device *phydev)
+ {
+@@ -2827,7 +2827,7 @@ mt7531_mac_config(struct dsa_switch *ds,
+ if (phy_interface_mode_is_rgmii(interface)) {
+ dp = dsa_to_port(ds, port);
+ phydev = dp->slave->phydev;
+- mt7531_rgmii_setup(priv, port, interface, phydev);
++ mt7531_rgmii_setup(priv, interface, phydev);
+ }
+ }
+
--- /dev/null
+From c45832fe783f468aaaace09ae95a30cbf0acf724 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:22 +0300
+Subject: [PATCH 15/15] net: dsa: mt7530: explain exposing MDIO bus of MT7531AE
+ better
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Unlike MT7531BE, the GPIO 6-12 pins are not used for RGMII on MT7531AE.
+Therefore, the GPIO 11-12 pins are set to function as MDC and MDIO to
+expose the MDIO bus of the switch. Replace the comment with a better
+explanation.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2626,7 +2626,10 @@ mt7531_setup(struct dsa_switch *ds)
+ if (!priv->p5_sgmii) {
+ mt7531_pll_setup(priv);
+ } else {
+- /* Let ds->slave_mii_bus be able to access external phy. */
++ /* Unlike MT7531BE, the GPIO 6-12 pins are not used for RGMII on
++ * MT7531AE. Set the GPIO 11-12 pins to function as MDC and MDIO
++ * to expose the MDIO bus of the switch.
++ */
+ mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK,
+ MT7531_EXT_P_MDC_11);
+ mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK,
--- /dev/null
+From 2203718c2f59ffdd6c78d54e5add594aebb4461e Mon Sep 17 00:00:00 2001
+From: Georgi Valkov <gvalkov@gmail.com>
+Date: Wed, 7 Jun 2023 15:56:59 +0200
+Subject: [PATCH 1/4] usbnet: ipheth: fix risk of NULL pointer deallocation
+
+The cleanup precedure in ipheth_probe will attempt to free a
+NULL pointer in dev->ctrl_buf if the memory allocation for
+this buffer is not successful. While kfree ignores NULL pointers,
+and the existing code is safe, it is a better design to rearrange
+the goto labels and avoid this.
+
+Signed-off-by: Georgi Valkov <gvalkov@gmail.com>
+Signed-off-by: Foster Snowhill <forst@pen.gy>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/usb/ipheth.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/net/usb/ipheth.c
++++ b/drivers/net/usb/ipheth.c
+@@ -510,8 +510,8 @@ err_register_netdev:
+ ipheth_free_urbs(dev);
+ err_alloc_urbs:
+ err_get_macaddr:
+-err_alloc_ctrl_buf:
+ kfree(dev->ctrl_buf);
++err_alloc_ctrl_buf:
+ err_endpoints:
+ free_netdev(netdev);
+ return retval;
--- /dev/null
+From 3e65efcca87a9bb5f3b864e0a43d167bc0a8688c Mon Sep 17 00:00:00 2001
+From: Foster Snowhill <forst@pen.gy>
+Date: Wed, 7 Jun 2023 15:57:00 +0200
+Subject: [PATCH 2/4] usbnet: ipheth: transmit URBs without trailing padding
+
+The behaviour of the official iOS tethering driver on macOS is to not
+transmit any trailing padding at the end of URBs. This is applicable
+to both NCM and legacy modes, including older devices.
+
+Adapt the driver to not include trailing padding in TX URBs, matching
+the behaviour of the official macOS driver.
+
+Signed-off-by: Foster Snowhill <forst@pen.gy>
+Tested-by: Georgi Valkov <gvalkov@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/usb/ipheth.c | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+--- a/drivers/net/usb/ipheth.c
++++ b/drivers/net/usb/ipheth.c
+@@ -373,12 +373,10 @@ static netdev_tx_t ipheth_tx(struct sk_b
+ }
+
+ memcpy(dev->tx_buf, skb->data, skb->len);
+- if (skb->len < IPHETH_BUF_SIZE)
+- memset(dev->tx_buf + skb->len, 0, IPHETH_BUF_SIZE - skb->len);
+
+ usb_fill_bulk_urb(dev->tx_urb, udev,
+ usb_sndbulkpipe(udev, dev->bulk_out),
+- dev->tx_buf, IPHETH_BUF_SIZE,
++ dev->tx_buf, skb->len,
+ ipheth_sndbulk_callback,
+ dev);
+ dev->tx_urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP;
--- /dev/null
+From a2d274c62e44b1995c170595db3865c6fe701226 Mon Sep 17 00:00:00 2001
+From: Foster Snowhill <forst@pen.gy>
+Date: Wed, 7 Jun 2023 15:57:01 +0200
+Subject: [PATCH 3/4] usbnet: ipheth: add CDC NCM support
+
+Recent iOS releases support CDC NCM encapsulation on RX. This mode is
+the default on macOS and Windows. In this mode, an iOS device may include
+one or more Ethernet frames inside a single URB.
+
+Freshly booted iOS devices start in legacy mode, but are put into
+NCM mode by the official Apple driver. When reconnecting such a device
+from a macOS/Windows machine to a Linux host, the device stays in
+NCM mode, making it unusable with the legacy ipheth driver code.
+
+To correctly support such a device, the driver has to either support
+the NCM mode too, or put the device back into legacy mode.
+
+To match the behaviour of the macOS/Windows driver, and since there
+is no documented control command to revert to legacy mode, implement
+NCM support. The device is attempted to be put into NCM mode by default,
+and falls back to legacy mode if the attempt fails.
+
+Signed-off-by: Foster Snowhill <forst@pen.gy>
+Tested-by: Georgi Valkov <gvalkov@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/usb/ipheth.c | 180 +++++++++++++++++++++++++++++++++------
+ 1 file changed, 155 insertions(+), 25 deletions(-)
+
+--- a/drivers/net/usb/ipheth.c
++++ b/drivers/net/usb/ipheth.c
+@@ -52,6 +52,7 @@
+ #include <linux/ethtool.h>
+ #include <linux/usb.h>
+ #include <linux/workqueue.h>
++#include <linux/usb/cdc.h>
+
+ #define USB_VENDOR_APPLE 0x05ac
+
+@@ -59,8 +60,12 @@
+ #define IPHETH_USBINTF_SUBCLASS 253
+ #define IPHETH_USBINTF_PROTO 1
+
+-#define IPHETH_BUF_SIZE 1514
+ #define IPHETH_IP_ALIGN 2 /* padding at front of URB */
++#define IPHETH_NCM_HEADER_SIZE (12 + 96) /* NCMH + NCM0 */
++#define IPHETH_TX_BUF_SIZE ETH_FRAME_LEN
++#define IPHETH_RX_BUF_SIZE_LEGACY (IPHETH_IP_ALIGN + ETH_FRAME_LEN)
++#define IPHETH_RX_BUF_SIZE_NCM 65536
++
+ #define IPHETH_TX_TIMEOUT (5 * HZ)
+
+ #define IPHETH_INTFNUM 2
+@@ -71,6 +76,7 @@
+ #define IPHETH_CTRL_TIMEOUT (5 * HZ)
+
+ #define IPHETH_CMD_GET_MACADDR 0x00
++#define IPHETH_CMD_ENABLE_NCM 0x04
+ #define IPHETH_CMD_CARRIER_CHECK 0x45
+
+ #define IPHETH_CARRIER_CHECK_TIMEOUT round_jiffies_relative(1 * HZ)
+@@ -97,6 +103,8 @@ struct ipheth_device {
+ u8 bulk_out;
+ struct delayed_work carrier_work;
+ bool confirmed_pairing;
++ int (*rcvbulk_callback)(struct urb *urb);
++ size_t rx_buf_len;
+ };
+
+ static int ipheth_rx_submit(struct ipheth_device *dev, gfp_t mem_flags);
+@@ -116,12 +124,12 @@ static int ipheth_alloc_urbs(struct iphe
+ if (rx_urb == NULL)
+ goto free_tx_urb;
+
+- tx_buf = usb_alloc_coherent(iphone->udev, IPHETH_BUF_SIZE,
++ tx_buf = usb_alloc_coherent(iphone->udev, IPHETH_TX_BUF_SIZE,
+ GFP_KERNEL, &tx_urb->transfer_dma);
+ if (tx_buf == NULL)
+ goto free_rx_urb;
+
+- rx_buf = usb_alloc_coherent(iphone->udev, IPHETH_BUF_SIZE + IPHETH_IP_ALIGN,
++ rx_buf = usb_alloc_coherent(iphone->udev, iphone->rx_buf_len,
+ GFP_KERNEL, &rx_urb->transfer_dma);
+ if (rx_buf == NULL)
+ goto free_tx_buf;
+@@ -134,7 +142,7 @@ static int ipheth_alloc_urbs(struct iphe
+ return 0;
+
+ free_tx_buf:
+- usb_free_coherent(iphone->udev, IPHETH_BUF_SIZE, tx_buf,
++ usb_free_coherent(iphone->udev, IPHETH_TX_BUF_SIZE, tx_buf,
+ tx_urb->transfer_dma);
+ free_rx_urb:
+ usb_free_urb(rx_urb);
+@@ -146,9 +154,9 @@ error_nomem:
+
+ static void ipheth_free_urbs(struct ipheth_device *iphone)
+ {
+- usb_free_coherent(iphone->udev, IPHETH_BUF_SIZE + IPHETH_IP_ALIGN, iphone->rx_buf,
++ usb_free_coherent(iphone->udev, iphone->rx_buf_len, iphone->rx_buf,
+ iphone->rx_urb->transfer_dma);
+- usb_free_coherent(iphone->udev, IPHETH_BUF_SIZE, iphone->tx_buf,
++ usb_free_coherent(iphone->udev, IPHETH_TX_BUF_SIZE, iphone->tx_buf,
+ iphone->tx_urb->transfer_dma);
+ usb_free_urb(iphone->rx_urb);
+ usb_free_urb(iphone->tx_urb);
+@@ -160,15 +168,106 @@ static void ipheth_kill_urbs(struct iphe
+ usb_kill_urb(dev->rx_urb);
+ }
+
+-static void ipheth_rcvbulk_callback(struct urb *urb)
++static int ipheth_consume_skb(char *buf, int len, struct ipheth_device *dev)
+ {
+- struct ipheth_device *dev;
+ struct sk_buff *skb;
+- int status;
++
++ skb = dev_alloc_skb(len);
++ if (!skb) {
++ dev->net->stats.rx_dropped++;
++ return -ENOMEM;
++ }
++
++ skb_put_data(skb, buf, len);
++ skb->dev = dev->net;
++ skb->protocol = eth_type_trans(skb, dev->net);
++
++ dev->net->stats.rx_packets++;
++ dev->net->stats.rx_bytes += len;
++ netif_rx(skb);
++
++ return 0;
++}
++
++static int ipheth_rcvbulk_callback_legacy(struct urb *urb)
++{
++ struct ipheth_device *dev;
++ char *buf;
++ int len;
++
++ dev = urb->context;
++
++ if (urb->actual_length <= IPHETH_IP_ALIGN) {
++ dev->net->stats.rx_length_errors++;
++ return -EINVAL;
++ }
++ len = urb->actual_length - IPHETH_IP_ALIGN;
++ buf = urb->transfer_buffer + IPHETH_IP_ALIGN;
++
++ return ipheth_consume_skb(buf, len, dev);
++}
++
++static int ipheth_rcvbulk_callback_ncm(struct urb *urb)
++{
++ struct usb_cdc_ncm_nth16 *ncmh;
++ struct usb_cdc_ncm_ndp16 *ncm0;
++ struct usb_cdc_ncm_dpe16 *dpe;
++ struct ipheth_device *dev;
++ int retval = -EINVAL;
+ char *buf;
+ int len;
+
+ dev = urb->context;
++
++ if (urb->actual_length < IPHETH_NCM_HEADER_SIZE) {
++ dev->net->stats.rx_length_errors++;
++ return retval;
++ }
++
++ ncmh = urb->transfer_buffer;
++ if (ncmh->dwSignature != cpu_to_le32(USB_CDC_NCM_NTH16_SIGN) ||
++ le16_to_cpu(ncmh->wNdpIndex) >= urb->actual_length) {
++ dev->net->stats.rx_errors++;
++ return retval;
++ }
++
++ ncm0 = urb->transfer_buffer + le16_to_cpu(ncmh->wNdpIndex);
++ if (ncm0->dwSignature != cpu_to_le32(USB_CDC_NCM_NDP16_NOCRC_SIGN) ||
++ le16_to_cpu(ncmh->wHeaderLength) + le16_to_cpu(ncm0->wLength) >=
++ urb->actual_length) {
++ dev->net->stats.rx_errors++;
++ return retval;
++ }
++
++ dpe = ncm0->dpe16;
++ while (le16_to_cpu(dpe->wDatagramIndex) != 0 &&
++ le16_to_cpu(dpe->wDatagramLength) != 0) {
++ if (le16_to_cpu(dpe->wDatagramIndex) >= urb->actual_length ||
++ le16_to_cpu(dpe->wDatagramIndex) +
++ le16_to_cpu(dpe->wDatagramLength) > urb->actual_length) {
++ dev->net->stats.rx_length_errors++;
++ return retval;
++ }
++
++ buf = urb->transfer_buffer + le16_to_cpu(dpe->wDatagramIndex);
++ len = le16_to_cpu(dpe->wDatagramLength);
++
++ retval = ipheth_consume_skb(buf, len, dev);
++ if (retval != 0)
++ return retval;
++
++ dpe++;
++ }
++
++ return 0;
++}
++
++static void ipheth_rcvbulk_callback(struct urb *urb)
++{
++ struct ipheth_device *dev;
++ int retval, status;
++
++ dev = urb->context;
+ if (dev == NULL)
+ return;
+
+@@ -191,25 +290,27 @@ static void ipheth_rcvbulk_callback(stru
+ dev->net->stats.rx_length_errors++;
+ return;
+ }
+- len = urb->actual_length - IPHETH_IP_ALIGN;
+- buf = urb->transfer_buffer + IPHETH_IP_ALIGN;
+
+- skb = dev_alloc_skb(len);
+- if (!skb) {
+- dev_err(&dev->intf->dev, "%s: dev_alloc_skb: -ENOMEM\n",
+- __func__);
+- dev->net->stats.rx_dropped++;
++ /* RX URBs starting with 0x00 0x01 do not encapsulate Ethernet frames,
++ * but rather are control frames. Their purpose is not documented, and
++ * they don't affect driver functionality, okay to drop them.
++ * There is usually just one 4-byte control frame as the very first
++ * URB received from the bulk IN endpoint.
++ */
++ if (unlikely
++ (((char *)urb->transfer_buffer)[0] == 0 &&
++ ((char *)urb->transfer_buffer)[1] == 1))
++ goto rx_submit;
++
++ retval = dev->rcvbulk_callback(urb);
++ if (retval != 0) {
++ dev_err(&dev->intf->dev, "%s: callback retval: %d\n",
++ __func__, retval);
+ return;
+ }
+
+- skb_put_data(skb, buf, len);
+- skb->dev = dev->net;
+- skb->protocol = eth_type_trans(skb, dev->net);
+-
+- dev->net->stats.rx_packets++;
+- dev->net->stats.rx_bytes += len;
++rx_submit:
+ dev->confirmed_pairing = true;
+- netif_rx(skb);
+ ipheth_rx_submit(dev, GFP_ATOMIC);
+ }
+
+@@ -310,6 +411,27 @@ static int ipheth_get_macaddr(struct iph
+ return retval;
+ }
+
++static int ipheth_enable_ncm(struct ipheth_device *dev)
++{
++ struct usb_device *udev = dev->udev;
++ int retval;
++
++ retval = usb_control_msg(udev,
++ usb_sndctrlpipe(udev, IPHETH_CTRL_ENDP),
++ IPHETH_CMD_ENABLE_NCM, /* request */
++ 0x41, /* request type */
++ 0x00, /* value */
++ 0x02, /* index */
++ NULL,
++ 0,
++ IPHETH_CTRL_TIMEOUT);
++
++ dev_info(&dev->intf->dev, "%s: usb_control_msg: %d\n",
++ __func__, retval);
++
++ return retval;
++}
++
+ static int ipheth_rx_submit(struct ipheth_device *dev, gfp_t mem_flags)
+ {
+ struct usb_device *udev = dev->udev;
+@@ -317,7 +439,7 @@ static int ipheth_rx_submit(struct iphet
+
+ usb_fill_bulk_urb(dev->rx_urb, udev,
+ usb_rcvbulkpipe(udev, dev->bulk_in),
+- dev->rx_buf, IPHETH_BUF_SIZE + IPHETH_IP_ALIGN,
++ dev->rx_buf, dev->rx_buf_len,
+ ipheth_rcvbulk_callback,
+ dev);
+ dev->rx_urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP;
+@@ -365,7 +487,7 @@ static netdev_tx_t ipheth_tx(struct sk_b
+ int retval;
+
+ /* Paranoid */
+- if (skb->len > IPHETH_BUF_SIZE) {
++ if (skb->len > IPHETH_TX_BUF_SIZE) {
+ WARN(1, "%s: skb too large: %d bytes\n", __func__, skb->len);
+ dev->net->stats.tx_dropped++;
+ dev_kfree_skb_any(skb);
+@@ -448,6 +570,8 @@ static int ipheth_probe(struct usb_inter
+ dev->net = netdev;
+ dev->intf = intf;
+ dev->confirmed_pairing = false;
++ dev->rx_buf_len = IPHETH_RX_BUF_SIZE_LEGACY;
++ dev->rcvbulk_callback = ipheth_rcvbulk_callback_legacy;
+ /* Set up endpoints */
+ hintf = usb_altnum_to_altsetting(intf, IPHETH_ALT_INTFNUM);
+ if (hintf == NULL) {
+@@ -479,6 +603,12 @@ static int ipheth_probe(struct usb_inter
+ if (retval)
+ goto err_get_macaddr;
+
++ retval = ipheth_enable_ncm(dev);
++ if (!retval) {
++ dev->rx_buf_len = IPHETH_RX_BUF_SIZE_NCM;
++ dev->rcvbulk_callback = ipheth_rcvbulk_callback_ncm;
++ }
++
+ INIT_DELAYED_WORK(&dev->carrier_work, ipheth_carrier_check_work);
+
+ retval = ipheth_alloc_urbs(dev);
--- /dev/null
+From 0c6e9d32ef0ccfcf2d875cbcff23bf345a54d585 Mon Sep 17 00:00:00 2001
+From: Foster Snowhill <forst@pen.gy>
+Date: Wed, 7 Jun 2023 15:57:02 +0200
+Subject: [PATCH 4/4] usbnet: ipheth: update Kconfig description
+
+This module has for a long time not been limited to iPhone <= 3GS.
+Update description to match the actual state of the driver.
+
+Remove dead link from 2010, instead reference an existing userspace
+iOS device pairing implementation as part of libimobiledevice.
+
+Signed-off-by: Foster Snowhill <forst@pen.gy>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/usb/Kconfig | 10 ++++------
+ 1 file changed, 4 insertions(+), 6 deletions(-)
+
+--- a/drivers/net/usb/Kconfig
++++ b/drivers/net/usb/Kconfig
+@@ -583,12 +583,10 @@ config USB_IPHETH
+ default n
+ help
+ Module used to share Internet connection (tethering) from your
+- iPhone (Original, 3G and 3GS) to your system.
+- Note that you need userspace libraries and programs that are needed
+- to pair your device with your system and that understand the iPhone
+- protocol.
+-
+- For more information: http://giagio.com/wiki/moin.cgi/iPhoneEthernetDriver
++ iPhone to your system.
++ Note that you need a corresponding userspace library/program
++ to pair your device with your system, for example usbmuxd
++ <https://github.com/libimobiledevice/usbmuxd>.
+
+ config USB_SIERRA_NET
+ tristate "USB-to-WWAN Driver for Sierra Wireless modems"
--- /dev/null
+From b3f1a164c7f742503dc7159011f7ad6b092b660e Mon Sep 17 00:00:00 2001
+From: Greg Ungerer <gerg@kernel.org>
+Date: Fri, 24 Nov 2023 14:15:28 +1000
+Subject: [PATCH] net: dsa: mv88e6xxx: fix marvell 6350 switch probing
+
+As of commit de5c9bf40c45 ("net: phylink: require supported_interfaces to
+be filled") Marvell 88e6350 switches fail to be probed:
+
+ ...
+ mv88e6085 d0072004.mdio-mii:11: switch 0x3710 detected: Marvell 88E6350, revision 2
+ mv88e6085 d0072004.mdio-mii:11: phylink: error: empty supported_interfaces
+ error creating PHYLINK: -22
+ mv88e6085: probe of d0072004.mdio-mii:11 failed with error -22
+ ...
+
+The problem stems from the use of mv88e6185_phylink_get_caps() to get
+the device capabilities. Create a new dedicated phylink_get_caps for the
+6351 family (which the 6350 is one of) to properly support their set of
+capabilities.
+
+According to chip.h the 6351 switch family includes the 6171, 6175, 6350
+and 6351 switches, so update each of these to use the correct
+phylink_get_caps.
+
+Fixes: de5c9bf40c45 ("net: phylink: require supported_interfaces to be filled")
+Signed-off-by: Greg Ungerer <gerg@kernel.org>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/dsa/mv88e6xxx/chip.c | 20 ++++++++++++++++----
+ 1 file changed, 16 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/dsa/mv88e6xxx/chip.c
++++ b/drivers/net/dsa/mv88e6xxx/chip.c
+@@ -652,6 +652,18 @@ static void mv88e6250_phylink_get_caps(s
+ config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
+ }
+
++static void mv88e6351_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
++ struct phylink_config *config)
++{
++ unsigned long *supported = config->supported_interfaces;
++
++ /* Translate the default cmode */
++ mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
++
++ config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
++ MAC_1000FD;
++}
++
+ static int mv88e6352_get_port4_serdes_cmode(struct mv88e6xxx_chip *chip)
+ {
+ u16 reg, val;
+@@ -4489,7 +4501,7 @@ static const struct mv88e6xxx_ops mv88e6
+ .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
+ .stu_getnext = mv88e6352_g1_stu_getnext,
+ .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
+- .phylink_get_caps = mv88e6185_phylink_get_caps,
++ .phylink_get_caps = mv88e6351_phylink_get_caps,
+ };
+
+ static const struct mv88e6xxx_ops mv88e6172_ops = {
+@@ -4590,7 +4602,7 @@ static const struct mv88e6xxx_ops mv88e6
+ .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
+ .stu_getnext = mv88e6352_g1_stu_getnext,
+ .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
+- .phylink_get_caps = mv88e6185_phylink_get_caps,
++ .phylink_get_caps = mv88e6351_phylink_get_caps,
+ };
+
+ static const struct mv88e6xxx_ops mv88e6176_ops = {
+@@ -5247,7 +5259,7 @@ static const struct mv88e6xxx_ops mv88e6
+ .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
+ .stu_getnext = mv88e6352_g1_stu_getnext,
+ .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
+- .phylink_get_caps = mv88e6185_phylink_get_caps,
++ .phylink_get_caps = mv88e6351_phylink_get_caps,
+ };
+
+ static const struct mv88e6xxx_ops mv88e6351_ops = {
+@@ -5293,7 +5305,7 @@ static const struct mv88e6xxx_ops mv88e6
+ .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
+ .avb_ops = &mv88e6352_avb_ops,
+ .ptp_ops = &mv88e6352_ptp_ops,
+- .phylink_get_caps = mv88e6185_phylink_get_caps,
++ .phylink_get_caps = mv88e6351_phylink_get_caps,
+ };
+
+ static const struct mv88e6xxx_ops mv88e6352_ops = {
__set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
} else {
if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) &&
-@@ -839,7 +837,7 @@ static void mv88e6xxx_get_caps(struct ds
+@@ -851,7 +849,7 @@ static void mv88e6xxx_get_caps(struct ds
chip->info->ops->phylink_get_caps(chip, port, config);
mv88e6xxx_reg_unlock(chip);
__set_bit(PHY_INTERFACE_MODE_INTERNAL,
config->supported_interfaces);
/* Internal ports with no phy-mode need GMII for PHYLIB */
-@@ -860,7 +858,7 @@ static void mv88e6xxx_mac_config(struct
+@@ -872,7 +870,7 @@ static void mv88e6xxx_mac_config(struct
mv88e6xxx_reg_lock(chip);
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
-@@ -5944,7 +5944,8 @@ static const struct mv88e6xxx_info mv88e
+@@ -5956,7 +5956,8 @@ static const struct mv88e6xxx_info mv88e
.name = "Marvell 88E6191X",
.num_databases = 4096,
.num_ports = 11, /* 10 + Z80 */
.max_vid = 8191,
.max_sid = 63,
.port_base_addr = 0x0,
-@@ -5967,7 +5968,8 @@ static const struct mv88e6xxx_info mv88e
+@@ -5979,7 +5980,8 @@ static const struct mv88e6xxx_info mv88e
.name = "Marvell 88E6193X",
.num_databases = 4096,
.num_ports = 11, /* 10 + Z80 */
.max_vid = 8191,
.max_sid = 63,
.port_base_addr = 0x0,
-@@ -6286,7 +6288,8 @@ static const struct mv88e6xxx_info mv88e
+@@ -6298,7 +6300,8 @@ static const struct mv88e6xxx_info mv88e
.name = "Marvell 88E6393X",
.num_databases = 4096,
.num_ports = 11, /* 10 + Z80 */
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
-@@ -3328,7 +3328,7 @@ static int mv88e6xxx_setup_port(struct m
+@@ -3340,7 +3340,7 @@ static int mv88e6xxx_setup_port(struct m
caps = pl_config.mac_capabilities;
if (chip->info->ops->port_max_speed_mode)
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
-@@ -797,6 +797,8 @@ static void mv88e6393x_phylink_get_caps(
+@@ -809,6 +809,8 @@ static void mv88e6393x_phylink_get_caps(
unsigned long *supported = config->supported_interfaces;
bool is_6191x =
chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X;
mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
-@@ -811,13 +813,17 @@ static void mv88e6393x_phylink_get_caps(
+@@ -823,13 +825,17 @@ static void mv88e6393x_phylink_get_caps(
/* 6191X supports >1G modes only on port 10 */
if (!is_6191x || port == 10) {
__set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
}
}
-@@ -6231,6 +6237,32 @@ static const struct mv88e6xxx_info mv88e
+@@ -6243,6 +6249,32 @@ static const struct mv88e6xxx_info mv88e
.ptp_support = true,
.ops = &mv88e6352_ops,
},
--- a/drivers/net/ethernet/mediatek/mtk_wed.c
+++ b/drivers/net/ethernet/mediatek/mtk_wed.c
-@@ -1713,19 +1713,20 @@ mtk_wed_irq_set_mask(struct mtk_wed_devi
+@@ -1709,19 +1709,20 @@ mtk_wed_irq_set_mask(struct mtk_wed_devi
int mtk_wed_flow_add(int index)
{
struct mtk_wed_hw *hw = hw_list[index];
goto out;
}
-@@ -1744,14 +1745,15 @@ void mtk_wed_flow_remove(int index)
+@@ -1740,14 +1741,15 @@ void mtk_wed_flow_remove(int index)
{
struct mtk_wed_hw *hw = hw_list[index];
wdma_clr(dev, MTK_WDMA_GLO_CFG,
MTK_WDMA_GLO_CFG_RX_INFO3_PRERES);
@@ -606,7 +606,7 @@ mtk_wed_stop(struct mtk_wed_device *dev)
+ wdma_w32(dev, MTK_WDMA_INT_MASK, 0);
wdma_w32(dev, MTK_WDMA_INT_GRP2, 0);
- wed_w32(dev, MTK_WED_WPDMA_INT_MASK, 0);
- if (dev->hw->version == 1)
+ if (mtk_wed_is_v1(dev->hw))
return;
wed_w32(dev, MTK_WED_EXT_INT_MASK1, 0);
-@@ -625,7 +625,7 @@ mtk_wed_deinit(struct mtk_wed_device *de
+@@ -624,7 +624,7 @@ mtk_wed_deinit(struct mtk_wed_device *de
MTK_WED_CTRL_WED_TX_BM_EN |
MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
return;
wed_clr(dev, MTK_WED_CTRL,
-@@ -731,7 +731,7 @@ mtk_wed_bus_init(struct mtk_wed_device *
+@@ -730,7 +730,7 @@ mtk_wed_bus_init(struct mtk_wed_device *
static void
mtk_wed_set_wpdma(struct mtk_wed_device *dev)
{
wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_phys);
} else {
mtk_wed_bus_init(dev);
-@@ -762,7 +762,7 @@ mtk_wed_hw_init_early(struct mtk_wed_dev
+@@ -761,7 +761,7 @@ mtk_wed_hw_init_early(struct mtk_wed_dev
MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY;
wed_m32(dev, MTK_WED_WDMA_GLO_CFG, mask, set);
u32 offset = dev->hw->index ? 0x04000400 : 0;
wdma_set(dev, MTK_WDMA_GLO_CFG,
-@@ -935,7 +935,7 @@ mtk_wed_hw_init(struct mtk_wed_device *d
+@@ -934,7 +934,7 @@ mtk_wed_hw_init(struct mtk_wed_device *d
wed_w32(dev, MTK_WED_TX_BM_BUF_LEN, MTK_WED_PKT_SIZE);
wed_w32(dev, MTK_WED_TX_BM_TKID,
FIELD_PREP(MTK_WED_TX_BM_TKID_START,
dev->wlan.token_start) |
-@@ -968,7 +968,7 @@ mtk_wed_hw_init(struct mtk_wed_device *d
+@@ -967,7 +967,7 @@ mtk_wed_hw_init(struct mtk_wed_device *d
mtk_wed_reset(dev, MTK_WED_RESET_TX_BM);
wed_set(dev, MTK_WED_CTRL,
MTK_WED_CTRL_WED_TX_BM_EN |
MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
-@@ -1218,7 +1218,7 @@ mtk_wed_reset_dma(struct mtk_wed_device
+@@ -1217,7 +1217,7 @@ mtk_wed_reset_dma(struct mtk_wed_device
}
dev->init_done = false;
return;
if (!busy) {
-@@ -1344,7 +1344,7 @@ mtk_wed_configure_irq(struct mtk_wed_dev
+@@ -1343,7 +1343,7 @@ mtk_wed_configure_irq(struct mtk_wed_dev
MTK_WED_CTRL_WED_TX_BM_EN |
MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER,
MTK_WED_PCIE_INT_TRIGGER_STATUS);
-@@ -1417,7 +1417,7 @@ mtk_wed_dma_enable(struct mtk_wed_device
+@@ -1416,7 +1416,7 @@ mtk_wed_dma_enable(struct mtk_wed_device
MTK_WDMA_GLO_CFG_RX_INFO1_PRERES |
MTK_WDMA_GLO_CFG_RX_INFO2_PRERES);
wdma_set(dev, MTK_WDMA_GLO_CFG,
MTK_WDMA_GLO_CFG_RX_INFO3_PRERES);
} else {
-@@ -1466,7 +1466,7 @@ mtk_wed_start(struct mtk_wed_device *dev
+@@ -1465,7 +1465,7 @@ mtk_wed_start(struct mtk_wed_device *dev
mtk_wed_set_ext_int(dev, true);
u32 val = dev->wlan.wpdma_phys | MTK_PCIE_MIRROR_MAP_EN |
FIELD_PREP(MTK_PCIE_MIRROR_MAP_WED_ID,
dev->hw->index);
-@@ -1551,7 +1551,7 @@ mtk_wed_attach(struct mtk_wed_device *de
+@@ -1550,7 +1550,7 @@ mtk_wed_attach(struct mtk_wed_device *de
}
mtk_wed_hw_init_early(dev);
regmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP,
BIT(hw->index), 0);
} else {
-@@ -1619,7 +1619,7 @@ static int
+@@ -1618,7 +1618,7 @@ static int
mtk_wed_txfree_ring_setup(struct mtk_wed_device *dev, void __iomem *regs)
{
struct mtk_wed_ring *ring = &dev->txfree_ring;
/*
* For txfree event handling, the same DMA ring is shared between WED
-@@ -1677,7 +1677,7 @@ mtk_wed_irq_get(struct mtk_wed_device *d
+@@ -1676,7 +1676,7 @@ mtk_wed_irq_get(struct mtk_wed_device *d
{
u32 val, ext_mask = MTK_WED_EXT_INT_STATUS_ERROR_MASK;
ext_mask |= MTK_WED_EXT_INT_STATUS_TX_DRV_R_RESP_ERR;
else
ext_mask |= MTK_WED_EXT_INT_STATUS_RX_FBUF_LO_TH |
-@@ -1844,7 +1844,7 @@ mtk_wed_setup_tc(struct mtk_wed_device *
+@@ -1840,7 +1840,7 @@ mtk_wed_setup_tc(struct mtk_wed_device *
{
struct mtk_wed_hw *hw = wed->hw;
return -EOPNOTSUPP;
switch (type) {
-@@ -1918,9 +1918,9 @@ void mtk_wed_add_hw(struct device_node *
+@@ -1914,9 +1914,9 @@ void mtk_wed_add_hw(struct device_node *
hw->wdma = wdma;
hw->index = index;
hw->irq = irq;
--- a/drivers/net/ethernet/mediatek/mtk_wed.c
+++ b/drivers/net/ethernet/mediatek/mtk_wed.c
@@ -606,7 +606,7 @@ mtk_wed_stop(struct mtk_wed_device *dev)
+ wdma_w32(dev, MTK_WDMA_INT_MASK, 0);
wdma_w32(dev, MTK_WDMA_INT_GRP2, 0);
- wed_w32(dev, MTK_WED_WPDMA_INT_MASK, 0);
- if (mtk_wed_is_v1(dev->hw))
+ if (!mtk_wed_get_rx_capa(dev))
return;
wed_w32(dev, MTK_WED_EXT_INT_MASK1, 0);
-@@ -733,16 +733,21 @@ mtk_wed_set_wpdma(struct mtk_wed_device
+@@ -732,16 +732,21 @@ mtk_wed_set_wpdma(struct mtk_wed_device
{
if (mtk_wed_is_v1(dev->hw)) {
wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_phys);
}
static void
-@@ -974,15 +979,17 @@ mtk_wed_hw_init(struct mtk_wed_device *d
+@@ -973,15 +978,17 @@ mtk_wed_hw_init(struct mtk_wed_device *d
MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
} else {
wed_clr(dev, MTK_WED_TX_TKID_CTRL, MTK_WED_TX_TKID_CTRL_PAUSE);
}
wed_clr(dev, MTK_WED_TX_BM_CTRL, MTK_WED_TX_BM_CTRL_PAUSE);
-@@ -1354,8 +1361,6 @@ mtk_wed_configure_irq(struct mtk_wed_dev
+@@ -1353,8 +1360,6 @@ mtk_wed_configure_irq(struct mtk_wed_dev
wed_clr(dev, MTK_WED_WDMA_INT_CTRL, wdma_mask);
} else {
/* initail tx interrupt trigger */
wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_TX,
MTK_WED_WPDMA_INT_CTRL_TX0_DONE_EN |
-@@ -1374,15 +1379,20 @@ mtk_wed_configure_irq(struct mtk_wed_dev
+@@ -1373,15 +1378,20 @@ mtk_wed_configure_irq(struct mtk_wed_dev
FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_TRIG,
dev->wlan.txfree_tbit));
wed_w32(dev, MTK_WED_WDMA_INT_CLR, wdma_mask);
wed_set(dev, MTK_WED_WDMA_INT_CTRL,
-@@ -1401,6 +1411,8 @@ mtk_wed_configure_irq(struct mtk_wed_dev
+@@ -1400,6 +1410,8 @@ mtk_wed_configure_irq(struct mtk_wed_dev
static void
mtk_wed_dma_enable(struct mtk_wed_device *dev)
{
wed_set(dev, MTK_WED_WPDMA_INT_CTRL, MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV);
wed_set(dev, MTK_WED_GLO_CFG,
-@@ -1420,33 +1432,33 @@ mtk_wed_dma_enable(struct mtk_wed_device
+@@ -1419,33 +1431,33 @@ mtk_wed_dma_enable(struct mtk_wed_device
if (mtk_wed_is_v1(dev->hw)) {
wdma_set(dev, MTK_WDMA_GLO_CFG,
MTK_WDMA_GLO_CFG_RX_INFO3_PRERES);
}
static void
-@@ -1473,7 +1485,7 @@ mtk_wed_start(struct mtk_wed_device *dev
+@@ -1472,7 +1484,7 @@ mtk_wed_start(struct mtk_wed_device *dev
val |= BIT(0) | (BIT(1) * !!dev->hw->index);
regmap_write(dev->hw->mirror, dev->hw->index * 4, val);
/* driver set mid ready and only once */
wed_w32(dev, MTK_WED_EXT_INT_MASK1,
MTK_WED_EXT_INT_STATUS_WPDMA_MID_RDY);
-@@ -1485,7 +1497,6 @@ mtk_wed_start(struct mtk_wed_device *dev
+@@ -1484,7 +1496,6 @@ mtk_wed_start(struct mtk_wed_device *dev
if (mtk_wed_rro_cfg(dev))
return;
}
mtk_wed_set_512_support(dev, dev->wlan.wcid_512);
-@@ -1551,13 +1562,14 @@ mtk_wed_attach(struct mtk_wed_device *de
+@@ -1550,13 +1561,14 @@ mtk_wed_attach(struct mtk_wed_device *de
}
mtk_wed_hw_init_early(dev);
static void
wed_m32(struct mtk_wed_device *dev, u32 reg, u32 mask, u32 val)
{
-@@ -747,7 +767,7 @@ mtk_wed_set_wpdma(struct mtk_wed_device
+@@ -746,7 +766,7 @@ mtk_wed_set_wpdma(struct mtk_wed_device
return;
wed_w32(dev, MTK_WED_WPDMA_RX_GLO_CFG, dev->wlan.wpdma_rx_glo);
}
static void
-@@ -941,22 +961,10 @@ mtk_wed_hw_init(struct mtk_wed_device *d
+@@ -940,22 +960,10 @@ mtk_wed_hw_init(struct mtk_wed_device *d
wed_w32(dev, MTK_WED_TX_BM_BUF_LEN, MTK_WED_PKT_SIZE);
if (mtk_wed_is_v1(dev->hw)) {
wed_w32(dev, MTK_WED_TX_BM_DYN_THR,
FIELD_PREP(MTK_WED_TX_BM_DYN_THR_LO_V2, 0) |
MTK_WED_TX_BM_DYN_THR_HI_V2);
-@@ -971,6 +979,11 @@ mtk_wed_hw_init(struct mtk_wed_device *d
+@@ -970,6 +978,11 @@ mtk_wed_hw_init(struct mtk_wed_device *d
MTK_WED_TX_TKID_DYN_THR_HI);
}
mtk_wed_reset(dev, MTK_WED_RESET_TX_BM);
if (mtk_wed_is_v1(dev->hw)) {
-@@ -1105,13 +1118,8 @@ mtk_wed_rx_reset(struct mtk_wed_device *
+@@ -1104,13 +1117,8 @@ mtk_wed_rx_reset(struct mtk_wed_device *
if (ret) {
mtk_wed_reset(dev, MTK_WED_RESET_WED_RX_DMA);
} else {
wed_w32(dev, MTK_WED_RESET_IDX, 0);
}
-@@ -1164,7 +1172,8 @@ mtk_wed_reset_dma(struct mtk_wed_device
+@@ -1163,7 +1171,8 @@ mtk_wed_reset_dma(struct mtk_wed_device
if (busy) {
mtk_wed_reset(dev, MTK_WED_RESET_WED_TX_DMA);
} else {
wed_w32(dev, MTK_WED_RESET_IDX, 0);
}
-@@ -1256,7 +1265,6 @@ static int
+@@ -1255,7 +1264,6 @@ static int
mtk_wed_wdma_rx_ring_setup(struct mtk_wed_device *dev, int idx, int size,
bool reset)
{
struct mtk_wed_ring *wdma;
if (idx >= ARRAY_SIZE(dev->rx_wdma))
-@@ -1264,7 +1272,7 @@ mtk_wed_wdma_rx_ring_setup(struct mtk_we
+@@ -1263,7 +1271,7 @@ mtk_wed_wdma_rx_ring_setup(struct mtk_we
wdma = &dev->rx_wdma[idx];
if (!reset && mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE,
return -ENOMEM;
wdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_BASE,
-@@ -1285,7 +1293,6 @@ static int
+@@ -1284,7 +1292,6 @@ static int
mtk_wed_wdma_tx_ring_setup(struct mtk_wed_device *dev, int idx, int size,
bool reset)
{
struct mtk_wed_ring *wdma;
if (idx >= ARRAY_SIZE(dev->tx_wdma))
-@@ -1293,7 +1300,7 @@ mtk_wed_wdma_tx_ring_setup(struct mtk_we
+@@ -1292,7 +1299,7 @@ mtk_wed_wdma_tx_ring_setup(struct mtk_we
wdma = &dev->tx_wdma[idx];
if (!reset && mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE,
return -ENOMEM;
wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_BASE,
-@@ -1932,7 +1939,12 @@ void mtk_wed_add_hw(struct device_node *
+@@ -1928,7 +1935,12 @@ void mtk_wed_add_hw(struct device_node *
hw->irq = irq;
hw->version = eth->soc->version;
hw->mirror = syscon_regmap_lookup_by_phandle(eth_np,
"mediatek,pcie-mirror");
hw->hifsys = syscon_regmap_lookup_by_phandle(eth_np,
-@@ -1946,6 +1958,8 @@ void mtk_wed_add_hw(struct device_node *
+@@ -1942,6 +1954,8 @@ void mtk_wed_add_hw(struct device_node *
regmap_write(hw->mirror, 0, 0);
regmap_write(hw->mirror, 4, 0);
}
}
mtk_wed_set_512_support(dev, false);
-@@ -652,6 +699,14 @@ mtk_wed_deinit(struct mtk_wed_device *de
+@@ -651,6 +698,14 @@ mtk_wed_deinit(struct mtk_wed_device *de
MTK_WED_CTRL_RX_ROUTE_QM_EN |
MTK_WED_CTRL_WED_RX_BM_EN |
MTK_WED_CTRL_RX_RRO_QM_EN);
}
static void
-@@ -701,21 +756,37 @@ mtk_wed_detach(struct mtk_wed_device *de
+@@ -700,21 +755,37 @@ mtk_wed_detach(struct mtk_wed_device *de
mutex_unlock(&hw_lock);
}
wed_w32(dev, MTK_WED_PCIE_INT_CTRL,
FIELD_PREP(MTK_WED_PCIE_INT_CTRL_POLL_EN, 2));
-@@ -723,19 +794,9 @@ mtk_wed_bus_init(struct mtk_wed_device *
+@@ -722,19 +793,9 @@ mtk_wed_bus_init(struct mtk_wed_device *
/* pcie interrupt control: pola/source selection */
wed_set(dev, MTK_WED_PCIE_INT_CTRL,
MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA |
break;
}
case MTK_WED_BUS_AXI:
-@@ -773,18 +834,19 @@ mtk_wed_set_wpdma(struct mtk_wed_device
+@@ -772,18 +833,19 @@ mtk_wed_set_wpdma(struct mtk_wed_device
static void
mtk_wed_hw_init_early(struct mtk_wed_device *dev)
{
wed_m32(dev, MTK_WED_WDMA_GLO_CFG, mask, set);
if (mtk_wed_is_v1(dev->hw)) {
-@@ -932,11 +994,18 @@ mtk_wed_route_qm_hw_init(struct mtk_wed_
+@@ -931,11 +993,18 @@ mtk_wed_route_qm_hw_init(struct mtk_wed_
}
/* configure RX_ROUTE_QM */
/* enable RX_ROUTE_QM */
wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_RX_ROUTE_QM_EN);
}
-@@ -949,22 +1018,30 @@ mtk_wed_hw_init(struct mtk_wed_device *d
+@@ -948,22 +1017,30 @@ mtk_wed_hw_init(struct mtk_wed_device *d
dev->init_done = true;
mtk_wed_set_ext_int(dev, false);
wed_w32(dev, MTK_WED_TX_BM_DYN_THR,
FIELD_PREP(MTK_WED_TX_BM_DYN_THR_LO_V2, 0) |
MTK_WED_TX_BM_DYN_THR_HI_V2);
-@@ -974,9 +1051,6 @@ mtk_wed_hw_init(struct mtk_wed_device *d
+@@ -973,9 +1050,6 @@ mtk_wed_hw_init(struct mtk_wed_device *d
dev->tx_buf_ring.size / 128) |
FIELD_PREP(MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM,
dev->tx_buf_ring.size / 128));
}
wed_w32(dev, dev->hw->soc->regmap.tx_bm_tkid,
-@@ -986,26 +1060,62 @@ mtk_wed_hw_init(struct mtk_wed_device *d
+@@ -985,26 +1059,62 @@ mtk_wed_hw_init(struct mtk_wed_device *d
mtk_wed_reset(dev, MTK_WED_RESET_TX_BM);
}
static void
-@@ -1303,6 +1413,24 @@ mtk_wed_wdma_tx_ring_setup(struct mtk_we
+@@ -1302,6 +1412,24 @@ mtk_wed_wdma_tx_ring_setup(struct mtk_we
dev->hw->soc->wdma_desc_size, true))
return -ENOMEM;
wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_BASE,
wdma->desc_phys);
wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_COUNT,
-@@ -1368,6 +1496,9 @@ mtk_wed_configure_irq(struct mtk_wed_dev
+@@ -1367,6 +1495,9 @@ mtk_wed_configure_irq(struct mtk_wed_dev
wed_clr(dev, MTK_WED_WDMA_INT_CTRL, wdma_mask);
} else {
/* initail tx interrupt trigger */
wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_TX,
MTK_WED_WPDMA_INT_CTRL_TX0_DONE_EN |
-@@ -1420,33 +1551,60 @@ mtk_wed_dma_enable(struct mtk_wed_device
+@@ -1419,33 +1550,60 @@ mtk_wed_dma_enable(struct mtk_wed_device
{
int i;
wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
MTK_WED_WPDMA_GLO_CFG_TX_TKID_KEEP |
MTK_WED_WPDMA_GLO_CFG_TX_DMAD_DW3_PREV);
-@@ -1458,11 +1616,22 @@ mtk_wed_dma_enable(struct mtk_wed_device
+@@ -1457,11 +1615,22 @@ mtk_wed_dma_enable(struct mtk_wed_device
MTK_WED_WDMA_GLO_CFG_TX_DRV_EN |
MTK_WED_WDMA_GLO_CFG_TX_DDONE_CHK);
for (i = 0; i < MTK_WED_RX_QUEUES; i++)
mtk_wed_check_wfdma_rx_fill(dev, i);
-@@ -1502,6 +1671,12 @@ mtk_wed_start(struct mtk_wed_device *dev
+@@ -1501,6 +1670,12 @@ mtk_wed_start(struct mtk_wed_device *dev
wed_r32(dev, MTK_WED_EXT_INT_MASK1);
wed_r32(dev, MTK_WED_EXT_INT_MASK2);
if (mtk_wed_rro_cfg(dev))
return;
}
-@@ -1553,6 +1728,7 @@ mtk_wed_attach(struct mtk_wed_device *de
+@@ -1552,6 +1727,7 @@ mtk_wed_attach(struct mtk_wed_device *de
dev->irq = hw->irq;
dev->wdma_idx = hw->index;
dev->version = hw->version;
if (hw->eth->dma_dev == hw->eth->dev &&
of_dma_is_coherent(hw->eth->dev->of_node))
-@@ -1620,6 +1796,23 @@ mtk_wed_tx_ring_setup(struct mtk_wed_dev
+@@ -1619,6 +1795,23 @@ mtk_wed_tx_ring_setup(struct mtk_wed_dev
ring->reg_base = MTK_WED_RING_TX(idx);
ring->wpdma = regs;
/* WED -> WPDMA */
wpdma_tx_w32(dev, idx, MTK_WED_RING_OFS_BASE, ring->desc_phys);
wpdma_tx_w32(dev, idx, MTK_WED_RING_OFS_COUNT, MTK_WED_TX_RING_SIZE);
-@@ -1694,15 +1887,13 @@ mtk_wed_rx_ring_setup(struct mtk_wed_dev
+@@ -1693,15 +1886,13 @@ mtk_wed_rx_ring_setup(struct mtk_wed_dev
static u32
mtk_wed_irq_get(struct mtk_wed_device *dev, u32 mask)
{
val = wed_r32(dev, MTK_WED_EXT_INT_STATUS);
wed_w32(dev, MTK_WED_EXT_INT_STATUS, val);
-@@ -1943,6 +2134,9 @@ void mtk_wed_add_hw(struct device_node *
+@@ -1939,6 +2130,9 @@ void mtk_wed_add_hw(struct device_node *
case 2:
hw->soc = &mt7986_data;
break;
}
static void
-@@ -1546,6 +1537,7 @@ mtk_wed_configure_irq(struct mtk_wed_dev
+@@ -1545,6 +1536,7 @@ mtk_wed_configure_irq(struct mtk_wed_dev
wed_w32(dev, MTK_WED_INT_MASK, irq_mask);
}
static void
mtk_wed_dma_enable(struct mtk_wed_device *dev)
{
-@@ -1633,8 +1625,26 @@ mtk_wed_dma_enable(struct mtk_wed_device
+@@ -1632,8 +1624,26 @@ mtk_wed_dma_enable(struct mtk_wed_device
wdma_set(dev, MTK_WDMA_WRBK_TX_CFG, MTK_WDMA_WRBK_TX_CFG_WRBK_EN);
}
mtk_wed_tx_buffer_alloc(struct mtk_wed_device *dev)
{
u32 desc_size = dev->hw->soc->tx_ring_desc_size;
-@@ -709,6 +840,7 @@ __mtk_wed_detach(struct mtk_wed_device *
+@@ -708,6 +839,7 @@ __mtk_wed_detach(struct mtk_wed_device *
mtk_wdma_rx_reset(dev);
mtk_wed_reset(dev, MTK_WED_RESET_WED);
mtk_wed_free_tx_buffer(dev);
mtk_wed_free_tx_rings(dev);
-@@ -1129,23 +1261,6 @@ mtk_wed_ring_reset(struct mtk_wed_ring *
+@@ -1128,23 +1260,6 @@ mtk_wed_ring_reset(struct mtk_wed_ring *
}
}
static int
mtk_wed_rx_reset(struct mtk_wed_device *dev)
{
-@@ -1692,6 +1807,7 @@ mtk_wed_start(struct mtk_wed_device *dev
+@@ -1691,6 +1806,7 @@ mtk_wed_start(struct mtk_wed_device *dev
}
mtk_wed_set_512_support(dev, dev->wlan.wcid_512);
mtk_wed_dma_enable(dev);
dev->running = true;
-@@ -1748,6 +1864,10 @@ mtk_wed_attach(struct mtk_wed_device *de
+@@ -1747,6 +1863,10 @@ mtk_wed_attach(struct mtk_wed_device *de
if (ret)
goto out;
}
static void
-@@ -935,6 +1056,8 @@ mtk_wed_bus_init(struct mtk_wed_device *
+@@ -934,6 +1055,8 @@ mtk_wed_bus_init(struct mtk_wed_device *
static void
mtk_wed_set_wpdma(struct mtk_wed_device *dev)
{
if (mtk_wed_is_v1(dev->hw)) {
wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_phys);
return;
-@@ -952,6 +1075,15 @@ mtk_wed_set_wpdma(struct mtk_wed_device
+@@ -951,6 +1074,15 @@ mtk_wed_set_wpdma(struct mtk_wed_device
wed_w32(dev, MTK_WED_WPDMA_RX_GLO_CFG, dev->wlan.wpdma_rx_glo);
wed_w32(dev, dev->hw->soc->regmap.wpdma_rx_ring0, dev->wlan.wpdma_rx);
}
static void
-@@ -1763,6 +1895,165 @@ mtk_wed_dma_enable(struct mtk_wed_device
+@@ -1762,6 +1894,165 @@ mtk_wed_dma_enable(struct mtk_wed_device
}
static void
mtk_wed_start(struct mtk_wed_device *dev, u32 irq_mask)
{
int i;
-@@ -2216,6 +2507,10 @@ void mtk_wed_add_hw(struct device_node *
+@@ -2212,6 +2503,10 @@ void mtk_wed_add_hw(struct device_node *
.detach = mtk_wed_detach,
.ppe_check = mtk_wed_ppe_check,
.setup_tc = mtk_wed_setup_tc,
wdma_w32(dev, MTK_WDMA_RESET_IDX, MTK_WDMA_RESET_IDX_TX);
wdma_w32(dev, MTK_WDMA_RESET_IDX, 0);
-@@ -1406,13 +1570,33 @@ mtk_wed_rx_reset(struct mtk_wed_device *
+@@ -1405,13 +1569,33 @@ mtk_wed_rx_reset(struct mtk_wed_device *
if (ret)
return ret;
wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX,
MTK_WED_WPDMA_RX_D_RST_CRX_IDX |
MTK_WED_WPDMA_RX_D_RST_DRV_IDX);
-@@ -1440,23 +1624,52 @@ mtk_wed_rx_reset(struct mtk_wed_device *
+@@ -1439,23 +1623,52 @@ mtk_wed_rx_reset(struct mtk_wed_device *
wed_w32(dev, MTK_WED_RROQM_RST_IDX, 0);
}
mtk_wed_reset(dev, MTK_WED_RESET_WDMA_TX_DRV);
/* reset wed rx dma */
-@@ -1477,6 +1690,14 @@ mtk_wed_rx_reset(struct mtk_wed_device *
+@@ -1476,6 +1689,14 @@ mtk_wed_rx_reset(struct mtk_wed_device *
MTK_WED_CTRL_WED_RX_BM_BUSY);
mtk_wed_reset(dev, MTK_WED_RESET_RX_BM);
/* wo change to enable state */
val = MTK_WED_WO_STATE_ENABLE;
ret = mtk_wed_mcu_send_msg(wo, MTK_WED_MODULE_ID_WO,
-@@ -1494,6 +1715,7 @@ mtk_wed_rx_reset(struct mtk_wed_device *
+@@ -1493,6 +1714,7 @@ mtk_wed_rx_reset(struct mtk_wed_device *
false);
}
mtk_wed_free_rx_buffer(dev);
return 0;
}
-@@ -1527,15 +1749,41 @@ mtk_wed_reset_dma(struct mtk_wed_device
+@@ -1526,15 +1748,41 @@ mtk_wed_reset_dma(struct mtk_wed_device
/* 2. reset WDMA rx DMA */
busy = !!mtk_wdma_rx_reset(dev);
wed_w32(dev, MTK_WED_WDMA_RESET_IDX,
MTK_WED_WDMA_RESET_IDX_RX | MTK_WED_WDMA_RESET_IDX_DRV);
wed_w32(dev, MTK_WED_WDMA_RESET_IDX, 0);
-@@ -1551,8 +1799,13 @@ mtk_wed_reset_dma(struct mtk_wed_device
+@@ -1550,8 +1798,13 @@ mtk_wed_reset_dma(struct mtk_wed_device
wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
for (i = 0; i < 100; i++) {
break;
}
-@@ -1574,6 +1827,8 @@ mtk_wed_reset_dma(struct mtk_wed_device
+@@ -1573,6 +1826,8 @@ mtk_wed_reset_dma(struct mtk_wed_device
mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_INT_AGENT);
mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_TX_DRV);
mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_RX_DRV);
} else {
wed_w32(dev, MTK_WED_WPDMA_RESET_IDX,
MTK_WED_WPDMA_RESET_IDX_TX |
-@@ -1590,7 +1845,14 @@ mtk_wed_reset_dma(struct mtk_wed_device
+@@ -1589,7 +1844,14 @@ mtk_wed_reset_dma(struct mtk_wed_device
wed_w32(dev, MTK_WED_RESET_IDX, 0);
}
}
static int
-@@ -1842,6 +2104,7 @@ mtk_wed_dma_enable(struct mtk_wed_device
+@@ -1841,6 +2103,7 @@ mtk_wed_dma_enable(struct mtk_wed_device
MTK_WED_WPDMA_GLO_CFG_RX_DRV_UNS_VER_FORCE_4);
wdma_set(dev, MTK_WDMA_PREF_RX_CFG, MTK_WDMA_PREF_RX_CFG_PREF_EN);
}
wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
-@@ -1905,6 +2168,12 @@ mtk_wed_start_hw_rro(struct mtk_wed_devi
+@@ -1904,6 +2167,12 @@ mtk_wed_start_hw_rro(struct mtk_wed_devi
if (!mtk_wed_get_rx_capa(dev) || !dev->wlan.hw_rro)
return;
--- /dev/null
+From f13b2b33c7674fa0988dfaa9adb95d7d912b489f Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Wed, 10 Apr 2024 20:42:38 +0100
+Subject: [PATCH 1/2] net: dsa: introduce dsa_phylink_to_port()
+
+We convert from a phylink_config struct to a dsa_port struct in many
+places, let's provide a helper for this.
+
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
+Link: https://lore.kernel.org/r/E1rudqA-006K9B-85@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ include/net/dsa.h | 6 ++++++
+ net/dsa/port.c | 12 ++++++------
+ 2 files changed, 12 insertions(+), 6 deletions(-)
+
+--- a/include/net/dsa.h
++++ b/include/net/dsa.h
+@@ -327,6 +327,12 @@ struct dsa_port {
+ };
+ };
+
++static inline struct dsa_port *
++dsa_phylink_to_port(struct phylink_config *config)
++{
++ return container_of(config, struct dsa_port, pl_config);
++}
++
+ /* TODO: ideally DSA ports would have a single dp->link_dp member,
+ * and no dst->rtable nor this struct dsa_link would be needed,
+ * but this would require some more complex tree walking,
+--- a/net/dsa/port.c
++++ b/net/dsa/port.c
+@@ -1572,7 +1572,7 @@ static struct phylink_pcs *
+ dsa_port_phylink_mac_select_pcs(struct phylink_config *config,
+ phy_interface_t interface)
+ {
+- struct dsa_port *dp = container_of(config, struct dsa_port, pl_config);
++ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct phylink_pcs *pcs = ERR_PTR(-EOPNOTSUPP);
+ struct dsa_switch *ds = dp->ds;
+
+@@ -1586,7 +1586,7 @@ static int dsa_port_phylink_mac_prepare(
+ unsigned int mode,
+ phy_interface_t interface)
+ {
+- struct dsa_port *dp = container_of(config, struct dsa_port, pl_config);
++ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct dsa_switch *ds = dp->ds;
+ int err = 0;
+
+@@ -1601,7 +1601,7 @@ static void dsa_port_phylink_mac_config(
+ unsigned int mode,
+ const struct phylink_link_state *state)
+ {
+- struct dsa_port *dp = container_of(config, struct dsa_port, pl_config);
++ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct dsa_switch *ds = dp->ds;
+
+ if (!ds->ops->phylink_mac_config)
+@@ -1614,7 +1614,7 @@ static int dsa_port_phylink_mac_finish(s
+ unsigned int mode,
+ phy_interface_t interface)
+ {
+- struct dsa_port *dp = container_of(config, struct dsa_port, pl_config);
++ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct dsa_switch *ds = dp->ds;
+ int err = 0;
+
+@@ -1629,7 +1629,7 @@ static void dsa_port_phylink_mac_link_do
+ unsigned int mode,
+ phy_interface_t interface)
+ {
+- struct dsa_port *dp = container_of(config, struct dsa_port, pl_config);
++ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct phy_device *phydev = NULL;
+ struct dsa_switch *ds = dp->ds;
+
+@@ -1652,7 +1652,7 @@ static void dsa_port_phylink_mac_link_up
+ int speed, int duplex,
+ bool tx_pause, bool rx_pause)
+ {
+- struct dsa_port *dp = container_of(config, struct dsa_port, pl_config);
++ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct dsa_switch *ds = dp->ds;
+
+ if (!ds->ops->phylink_mac_link_up) {
--- /dev/null
+From c22d8240fcd73a1c3ec8dcb055bd583fb970c375 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Wed, 10 Apr 2024 20:42:43 +0100
+Subject: [PATCH 2/2] net: dsa: allow DSA switch drivers to provide their own
+ phylink mac ops
+
+Rather than having a shim for each and every phylink MAC operation,
+allow DSA switch drivers to provide their own ops structure. When a
+DSA driver provides the phylink MAC operations, the shimmed ops must
+not be provided, so fail an attempt to register a switch with both
+the phylink_mac_ops in struct dsa_switch and the phylink_mac_*
+operations populated in dsa_switch_ops populated.
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
+Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
+Link: https://lore.kernel.org/r/E1rudqF-006K9H-Cc@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ include/net/dsa.h | 5 +++++
+ net/dsa/dsa.c | 11 +++++++++++
+ net/dsa/port.c | 26 ++++++++++++++++++++------
+ 3 files changed, 36 insertions(+), 6 deletions(-)
+
+--- a/include/net/dsa.h
++++ b/include/net/dsa.h
+@@ -458,6 +458,11 @@ struct dsa_switch {
+ const struct dsa_switch_ops *ops;
+
+ /*
++ * Allow a DSA switch driver to override the phylink MAC ops
++ */
++ const struct phylink_mac_ops *phylink_mac_ops;
++
++ /*
+ * Slave mii_bus and devices for the individual ports.
+ */
+ u32 phys_mii_mask;
+--- a/net/dsa/dsa.c
++++ b/net/dsa/dsa.c
+@@ -1510,6 +1510,17 @@ static int dsa_switch_probe(struct dsa_s
+ if (!ds->num_ports)
+ return -EINVAL;
+
++ if (ds->phylink_mac_ops) {
++ if (ds->ops->phylink_mac_select_pcs ||
++ ds->ops->phylink_mac_prepare ||
++ ds->ops->phylink_mac_config ||
++ ds->ops->phylink_mac_finish ||
++ ds->ops->phylink_mac_link_down ||
++ ds->ops->phylink_mac_link_up ||
++ ds->ops->adjust_link)
++ return -EINVAL;
++ }
++
+ if (np) {
+ err = dsa_switch_parse_of(ds, np);
+ if (err)
+--- a/net/dsa/port.c
++++ b/net/dsa/port.c
+@@ -1677,6 +1677,7 @@ static const struct phylink_mac_ops dsa_
+
+ int dsa_port_phylink_create(struct dsa_port *dp)
+ {
++ const struct phylink_mac_ops *mac_ops;
+ struct dsa_switch *ds = dp->ds;
+ phy_interface_t mode;
+ struct phylink *pl;
+@@ -1700,8 +1701,12 @@ int dsa_port_phylink_create(struct dsa_p
+ }
+ }
+
+- pl = phylink_create(&dp->pl_config, of_fwnode_handle(dp->dn),
+- mode, &dsa_port_phylink_mac_ops);
++ mac_ops = &dsa_port_phylink_mac_ops;
++ if (ds->phylink_mac_ops)
++ mac_ops = ds->phylink_mac_ops;
++
++ pl = phylink_create(&dp->pl_config, of_fwnode_handle(dp->dn), mode,
++ mac_ops);
+ if (IS_ERR(pl)) {
+ pr_err("error creating PHYLINK: %ld\n", PTR_ERR(pl));
+ return PTR_ERR(pl);
+@@ -1967,12 +1972,23 @@ static void dsa_shared_port_validate_of(
+ dn, dsa_port_is_cpu(dp) ? "CPU" : "DSA", dp->index);
+ }
+
++static void dsa_shared_port_link_down(struct dsa_port *dp)
++{
++ struct dsa_switch *ds = dp->ds;
++
++ if (ds->phylink_mac_ops && ds->phylink_mac_ops->mac_link_down)
++ ds->phylink_mac_ops->mac_link_down(&dp->pl_config, MLO_AN_FIXED,
++ PHY_INTERFACE_MODE_NA);
++ else if (ds->ops->phylink_mac_link_down)
++ ds->ops->phylink_mac_link_down(ds, dp->index, MLO_AN_FIXED,
++ PHY_INTERFACE_MODE_NA);
++}
++
+ int dsa_shared_port_link_register_of(struct dsa_port *dp)
+ {
+ struct dsa_switch *ds = dp->ds;
+ bool missing_link_description;
+ bool missing_phy_mode;
+- int port = dp->index;
+
+ dsa_shared_port_validate_of(dp, &missing_phy_mode,
+ &missing_link_description);
+@@ -1988,9 +2004,7 @@ int dsa_shared_port_link_register_of(str
+ "Skipping phylink registration for %s port %d\n",
+ dsa_port_is_cpu(dp) ? "CPU" : "DSA", dp->index);
+ } else {
+- if (ds->ops->phylink_mac_link_down)
+- ds->ops->phylink_mac_link_down(ds, port,
+- MLO_AN_FIXED, PHY_INTERFACE_MODE_NA);
++ dsa_shared_port_link_down(dp);
+
+ return dsa_shared_port_phylink_register(dp);
+ }
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-@@ -3003,13 +3003,25 @@ static void stmmac_tx_timer_arm(struct s
+@@ -2988,13 +2988,25 @@ static void stmmac_tx_timer_arm(struct s
{
struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
u32 tx_coal_timer = priv->tx_coal_timer[queue];
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-@@ -2551,9 +2551,13 @@ static void stmmac_bump_dma_threshold(st
+@@ -2536,9 +2536,13 @@ static void stmmac_bump_dma_threshold(st
* @priv: driver private structure
* @budget: napi budget limiting this functions packet handling
* @queue: TX queue index
{
struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
struct stmmac_txq_stats *txq_stats = &priv->xstats.txq_stats[queue];
-@@ -2713,7 +2717,7 @@ static int stmmac_tx_clean(struct stmmac
+@@ -2698,7 +2702,7 @@ static int stmmac_tx_clean(struct stmmac
/* We still have pending packets, let's call for a new scheduling */
if (tx_q->dirty_tx != tx_q->cur_tx)
u64_stats_update_begin(&txq_stats->napi_syncp);
u64_stats_add(&txq_stats->napi.tx_packets, tx_packets);
-@@ -5605,6 +5609,7 @@ static int stmmac_napi_poll_tx(struct na
+@@ -5590,6 +5594,7 @@ static int stmmac_napi_poll_tx(struct na
container_of(napi, struct stmmac_channel, tx_napi);
struct stmmac_priv *priv = ch->priv_data;
struct stmmac_txq_stats *txq_stats;
u32 chan = ch->index;
int work_done;
-@@ -5613,7 +5618,7 @@ static int stmmac_napi_poll_tx(struct na
+@@ -5598,7 +5603,7 @@ static int stmmac_napi_poll_tx(struct na
u64_stats_inc(&txq_stats->napi.poll);
u64_stats_update_end(&txq_stats->napi_syncp);
work_done = min(work_done, budget);
if (work_done < budget && napi_complete_done(napi, work_done)) {
-@@ -5624,6 +5629,10 @@ static int stmmac_napi_poll_tx(struct na
+@@ -5609,6 +5614,10 @@ static int stmmac_napi_poll_tx(struct na
spin_unlock_irqrestore(&ch->lock, flags);
}
return work_done;
}
-@@ -5632,6 +5641,7 @@ static int stmmac_napi_poll_rxtx(struct
+@@ -5617,6 +5626,7 @@ static int stmmac_napi_poll_rxtx(struct
struct stmmac_channel *ch =
container_of(napi, struct stmmac_channel, rxtx_napi);
struct stmmac_priv *priv = ch->priv_data;
int rx_done, tx_done, rxtx_done;
struct stmmac_rxq_stats *rxq_stats;
struct stmmac_txq_stats *txq_stats;
-@@ -5647,7 +5657,7 @@ static int stmmac_napi_poll_rxtx(struct
+@@ -5632,7 +5642,7 @@ static int stmmac_napi_poll_rxtx(struct
u64_stats_inc(&txq_stats->napi.poll);
u64_stats_update_end(&txq_stats->napi_syncp);
tx_done = min(tx_done, budget);
rx_done = stmmac_rx_zc(priv, budget, chan);
-@@ -5672,6 +5682,10 @@ static int stmmac_napi_poll_rxtx(struct
+@@ -5657,6 +5667,10 @@ static int stmmac_napi_poll_rxtx(struct
spin_unlock_irqrestore(&ch->lock, flags);
}
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2860,15 +2860,6 @@ static void mt753x_phylink_mac_link_down
+@@ -3037,15 +3037,6 @@ static void mt753x_phylink_mac_link_down
mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
}
static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port,
unsigned int mode,
phy_interface_t interface,
-@@ -2956,8 +2947,6 @@ mt7531_cpu_port_config(struct dsa_switch
+@@ -3133,8 +3124,6 @@ mt7531_cpu_port_config(struct dsa_switch
return ret;
mt7530_write(priv, MT7530_PMCR_P(port),
PMCR_CPU_PORT_SETTING(priv->id));
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2182,24 +2182,40 @@ mt7530_free_irq_common(struct mt7530_pri
+@@ -2345,24 +2345,40 @@ mt7530_free_irq_common(struct mt7530_pri
static void
mt7530_free_irq(struct mt7530_priv *priv)
{
bus->priv = priv;
bus->name = KBUILD_MODNAME "-mii";
snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++);
-@@ -2210,16 +2226,18 @@ mt7530_setup_mdio(struct mt7530_priv *pr
+@@ -2373,16 +2389,18 @@ mt7530_setup_mdio(struct mt7530_priv *pr
bus->parent = dev;
bus->phy_mask = ~ds->phys_mii_mask;
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -1071,10 +1071,6 @@ mt753x_cpu_port_enable(struct dsa_switch
+@@ -1232,10 +1232,6 @@ mt753x_cpu_port_enable(struct dsa_switch
mt7530_set(priv, MT7530_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) |
UNU_FFP(BIT(port)));
/* Add the CPU port to the CPU port bitmap for MT7531 and the switch on
* the MT7988 SoC. Trapped frames will be forwarded to the CPU port that
* is affine to the inbound user port.
-@@ -3128,6 +3124,36 @@ static int mt753x_set_mac_eee(struct dsa
+@@ -3305,6 +3301,36 @@ static int mt753x_set_mac_eee(struct dsa
return 0;
}
static int mt7988_pad_setup(struct dsa_switch *ds, phy_interface_t interface)
{
return 0;
-@@ -3183,6 +3209,7 @@ const struct dsa_switch_ops mt7530_switc
+@@ -3360,6 +3386,7 @@ const struct dsa_switch_ops mt7530_switc
.phylink_mac_link_up = mt753x_phylink_mac_link_up,
.get_mac_eee = mt753x_get_mac_eee,
.set_mac_eee = mt753x_set_mac_eee,
--- a/drivers/net/dsa/mt7530.h
+++ b/drivers/net/dsa/mt7530.h
-@@ -41,8 +41,8 @@ enum mt753x_id {
+@@ -45,8 +45,8 @@ enum mt753x_id {
#define UNU_FFP(x) (((x) & 0xff) << 8)
#define UNU_FFP_MASK UNU_FFP(~0)
#define CPU_EN BIT(7)
#define MIRROR_EN BIT(3)
#define MIRROR_PORT(x) ((x) & 0x7)
#define MIRROR_MASK 0x7
-@@ -780,6 +780,7 @@ struct mt753x_info {
+@@ -790,6 +790,7 @@ struct mt753x_info {
* @irq_domain: IRQ domain of the switch irq_chip
* @irq_enable: IRQ enable bits, synced to SYS_INT_EN
* @create_sgmii: Pointer to function creating SGMII PCS instance(s)
*/
struct mt7530_priv {
struct device *dev;
-@@ -806,6 +807,7 @@ struct mt7530_priv {
+@@ -816,6 +817,7 @@ struct mt7530_priv {
struct irq_domain *irq_domain;
u32 irq_enable;
int (*create_sgmii)(struct mt7530_priv *priv, bool dual_sgmii);
--- a/drivers/net/dsa/mt7530.h
+++ b/drivers/net/dsa/mt7530.h
-@@ -703,7 +703,7 @@ struct mt7530_port {
+@@ -713,7 +713,7 @@ struct mt7530_port {
/* Port 5 interface select definitions */
enum p5_interface_select {
P5_INTF_SEL_PHY_P0,
P5_INTF_SEL_PHY_P4,
P5_INTF_SEL_GMAC5,
-@@ -796,7 +796,7 @@ struct mt7530_priv {
+@@ -806,7 +806,7 @@ struct mt7530_priv {
bool mcm;
phy_interface_t p6_interface;
phy_interface_t p5_interface;
default:
return "unknown";
}
-@@ -2524,6 +2510,12 @@ mt7531_setup(struct dsa_switch *ds)
+@@ -2694,6 +2680,12 @@ mt7531_setup(struct dsa_switch *ds)
return -ENODEV;
}
/* all MACs must be forced link-down before sw reset */
for (i = 0; i < MT7530_NUM_PORTS; i++)
mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK);
-@@ -2533,21 +2525,18 @@ mt7531_setup(struct dsa_switch *ds)
+@@ -2703,21 +2695,18 @@ mt7531_setup(struct dsa_switch *ds)
SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
SYS_CTRL_REG_RST);
mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
MT7531_GPIO0_INTERRUPT);
-@@ -2607,11 +2596,6 @@ static void mt7530_mac_port_get_caps(str
+@@ -2784,11 +2773,6 @@ static void mt7530_mac_port_get_caps(str
}
}
static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port,
struct phylink_config *config)
{
-@@ -2624,7 +2608,7 @@ static void mt7531_mac_port_get_caps(str
+@@ -2801,7 +2785,7 @@ static void mt7531_mac_port_get_caps(str
break;
case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */
phy_interface_set_rgmii(config->supported_interfaces);
break;
}
-@@ -2691,7 +2675,7 @@ static int mt7531_rgmii_setup(struct mt7
+@@ -2868,7 +2852,7 @@ static int mt7531_rgmii_setup(struct mt7
{
u32 val;
dev_err(priv->dev, "RGMII mode is not available for port %d\n",
port);
return -EINVAL;
-@@ -2934,7 +2918,7 @@ mt7531_cpu_port_config(struct dsa_switch
+@@ -3111,7 +3095,7 @@ mt7531_cpu_port_config(struct dsa_switch
switch (port) {
case 5:
interface = PHY_INTERFACE_MODE_RGMII;
else
interface = PHY_INTERFACE_MODE_2500BASEX;
-@@ -3086,7 +3070,7 @@ mt753x_setup(struct dsa_switch *ds)
+@@ -3263,7 +3247,7 @@ mt753x_setup(struct dsa_switch *ds)
mt7530_free_irq_common(priv);
if (priv->create_sgmii) {
}
--- a/drivers/net/dsa/mt7530.h
+++ b/drivers/net/dsa/mt7530.h
-@@ -707,7 +707,6 @@ enum p5_interface_select {
+@@ -717,7 +717,6 @@ enum p5_interface_select {
P5_INTF_SEL_PHY_P0,
P5_INTF_SEL_PHY_P4,
P5_INTF_SEL_GMAC5,
};
struct mt7530_priv;
-@@ -776,6 +775,8 @@ struct mt753x_info {
+@@ -786,6 +785,8 @@ struct mt753x_info {
* registers
* @p6_interface Holding the current port 6 interface
* @p5_intf_sel: Holding the current port 5 interface select
* @irq: IRQ number of the switch
* @irq_domain: IRQ domain of the switch irq_chip
* @irq_enable: IRQ enable bits, synced to SYS_INT_EN
-@@ -797,6 +798,7 @@ struct mt7530_priv {
+@@ -807,6 +808,7 @@ struct mt7530_priv {
phy_interface_t p6_interface;
phy_interface_t p5_interface;
enum p5_interface_select p5_intf_sel;
u8 mirror_rx;
u8 mirror_tx;
struct mt7530_port ports[MT7530_NUM_PORTS];
-@@ -806,7 +808,7 @@ struct mt7530_priv {
+@@ -816,7 +818,7 @@ struct mt7530_priv {
int irq;
struct irq_domain *irq_domain;
u32 irq_enable;
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2574,12 +2574,14 @@ static void mt7530_mac_port_get_caps(str
+@@ -2751,12 +2751,14 @@ static void mt7530_mac_port_get_caps(str
struct phylink_config *config)
{
switch (port) {
phy_interface_set_rgmii(config->supported_interfaces);
__set_bit(PHY_INTERFACE_MODE_MII,
config->supported_interfaces);
-@@ -2587,7 +2589,8 @@ static void mt7530_mac_port_get_caps(str
+@@ -2764,7 +2766,8 @@ static void mt7530_mac_port_get_caps(str
config->supported_interfaces);
break;
__set_bit(PHY_INTERFACE_MODE_RGMII,
config->supported_interfaces);
__set_bit(PHY_INTERFACE_MODE_TRGMII,
-@@ -2602,19 +2605,24 @@ static void mt7531_mac_port_get_caps(str
+@@ -2779,19 +2782,24 @@ static void mt7531_mac_port_get_caps(str
struct mt7530_priv *priv = ds->priv;
switch (port) {
__set_bit(PHY_INTERFACE_MODE_SGMII,
config->supported_interfaces);
__set_bit(PHY_INTERFACE_MODE_1000BASEX,
-@@ -2633,11 +2641,13 @@ static void mt7988_mac_port_get_caps(str
+@@ -2810,11 +2818,13 @@ static void mt7988_mac_port_get_caps(str
phy_interface_zero(config->supported_interfaces);
switch (port) {
case 6:
__set_bit(PHY_INTERFACE_MODE_INTERNAL,
config->supported_interfaces);
-@@ -2801,12 +2811,12 @@ mt753x_phylink_mac_config(struct dsa_swi
+@@ -2978,12 +2988,12 @@ mt753x_phylink_mac_config(struct dsa_swi
u32 mcr_cur, mcr_new;
switch (port) {
if (priv->p5_interface == state->interface)
break;
-@@ -2816,7 +2826,7 @@ mt753x_phylink_mac_config(struct dsa_swi
+@@ -2993,7 +3003,7 @@ mt753x_phylink_mac_config(struct dsa_swi
if (priv->p5_intf_sel != P5_DISABLED)
priv->p5_interface = state->interface;
break;
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2362,16 +2362,15 @@ mt7530_setup(struct dsa_switch *ds)
+@@ -2529,16 +2529,15 @@ mt7530_setup(struct dsa_switch *ds)
return ret;
/* Setup port 5 */
for_each_child_of_node(dn, mac_np) {
if (!of_device_is_compatible(mac_np,
"mediatek,eth-mac"))
-@@ -2402,6 +2401,8 @@ mt7530_setup(struct dsa_switch *ds)
+@@ -2569,6 +2568,8 @@ mt7530_setup(struct dsa_switch *ds)
of_node_put(phy_node);
break;
}
}
#ifdef CONFIG_GPIOLIB
-@@ -2412,8 +2413,6 @@ mt7530_setup(struct dsa_switch *ds)
+@@ -2579,8 +2580,6 @@ mt7530_setup(struct dsa_switch *ds)
}
#endif /* CONFIG_GPIOLIB */
default:
dev_err(ds->dev, "Unsupported p5_intf_sel %d\n",
priv->p5_intf_sel);
-@@ -2367,8 +2364,6 @@ mt7530_setup(struct dsa_switch *ds)
+@@ -2534,8 +2531,6 @@ mt7530_setup(struct dsa_switch *ds)
* Set priv->p5_intf_sel to the appropriate value if PHY muxing
* is detected.
*/
for_each_child_of_node(dn, mac_np) {
if (!of_device_is_compatible(mac_np,
"mediatek,eth-mac"))
-@@ -2400,7 +2395,9 @@ mt7530_setup(struct dsa_switch *ds)
+@@ -2567,7 +2562,9 @@ mt7530_setup(struct dsa_switch *ds)
break;
}
switch (interface) {
case PHY_INTERFACE_MODE_RGMII:
trgint = 0;
-@@ -2295,6 +2288,12 @@ mt7530_setup(struct dsa_switch *ds)
+@@ -2458,6 +2451,12 @@ mt7530_setup(struct dsa_switch *ds)
return -ENODEV;
}
return 0;
}
-@@ -2649,11 +2653,10 @@ mt7530_mac_config(struct dsa_switch *ds,
+@@ -2826,11 +2830,10 @@ mt7530_mac_config(struct dsa_switch *ds,
{
struct mt7530_priv *priv = ds->priv;
static void
mt7531_pll_setup(struct mt7530_priv *priv)
{
-@@ -2640,14 +2628,6 @@ static void mt7988_mac_port_get_caps(str
+@@ -2817,14 +2805,6 @@ static void mt7988_mac_port_get_caps(str
}
static int
mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
phy_interface_t interface)
{
-@@ -2812,8 +2792,6 @@ mt753x_phylink_mac_config(struct dsa_swi
+@@ -2989,8 +2969,6 @@ mt753x_phylink_mac_config(struct dsa_swi
if (priv->p6_interface == state->interface)
break;
if (mt753x_mac_config(ds, port, mode, state) < 0)
goto unsupported;
-@@ -3130,11 +3108,6 @@ mt753x_conduit_state_change(struct dsa_s
+@@ -3307,11 +3285,6 @@ mt753x_conduit_state_change(struct dsa_s
mt7530_rmw(priv, MT7530_MFC, CPU_EN | CPU_PORT_MASK, val);
}
static int mt7988_setup(struct dsa_switch *ds)
{
struct mt7530_priv *priv = ds->priv;
-@@ -3198,7 +3171,6 @@ const struct mt753x_info mt753x_table[]
+@@ -3375,7 +3348,6 @@ const struct mt753x_info mt753x_table[]
.phy_write_c22 = mt7530_phy_write_c22,
.phy_read_c45 = mt7530_phy_read_c45,
.phy_write_c45 = mt7530_phy_write_c45,
.mac_port_get_caps = mt7530_mac_port_get_caps,
.mac_port_config = mt7530_mac_config,
},
-@@ -3210,7 +3182,6 @@ const struct mt753x_info mt753x_table[]
+@@ -3387,7 +3359,6 @@ const struct mt753x_info mt753x_table[]
.phy_write_c22 = mt7530_phy_write_c22,
.phy_read_c45 = mt7530_phy_read_c45,
.phy_write_c45 = mt7530_phy_write_c45,
.mac_port_get_caps = mt7530_mac_port_get_caps,
.mac_port_config = mt7530_mac_config,
},
-@@ -3222,7 +3193,6 @@ const struct mt753x_info mt753x_table[]
+@@ -3399,7 +3370,6 @@ const struct mt753x_info mt753x_table[]
.phy_write_c22 = mt7531_ind_c22_phy_write,
.phy_read_c45 = mt7531_ind_c45_phy_read,
.phy_write_c45 = mt7531_ind_c45_phy_write,
.cpu_port_config = mt7531_cpu_port_config,
.mac_port_get_caps = mt7531_mac_port_get_caps,
.mac_port_config = mt7531_mac_config,
-@@ -3235,7 +3205,6 @@ const struct mt753x_info mt753x_table[]
+@@ -3412,7 +3382,6 @@ const struct mt753x_info mt753x_table[]
.phy_write_c22 = mt7531_ind_c22_phy_write,
.phy_read_c45 = mt7531_ind_c45_phy_read,
.phy_write_c45 = mt7531_ind_c45_phy_write,
.cpu_port_config = mt7988_cpu_port_config,
.mac_port_get_caps = mt7988_mac_port_get_caps,
.mac_port_config = mt7988_mac_config,
-@@ -3265,9 +3234,8 @@ mt7530_probe_common(struct mt7530_priv *
+@@ -3442,9 +3411,8 @@ mt7530_probe_common(struct mt7530_priv *
/* Sanity check if these required device operations are filled
* properly.
*/
--- a/drivers/net/dsa/mt7530.h
+++ b/drivers/net/dsa/mt7530.h
-@@ -724,8 +724,6 @@ struct mt753x_pcs {
+@@ -734,8 +734,6 @@ struct mt753x_pcs {
* @phy_write_c22: Holding the way writing PHY port using C22
* @phy_read_c45: Holding the way reading PHY port using C45
* @phy_write_c45: Holding the way writing PHY port using C45
* @phy_mode_supported: Check if the PHY type is being supported on a certain
* port
* @mac_port_validate: Holding the way to set addition validate type for a
-@@ -746,7 +744,6 @@ struct mt753x_info {
+@@ -756,7 +754,6 @@ struct mt753x_info {
int regnum);
int (*phy_write_c45)(struct mt7530_priv *priv, int port, int devad,
int regnum, u16 val);
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2613,7 +2613,7 @@ static void mt7988_mac_port_get_caps(str
+@@ -2790,7 +2790,7 @@ static void mt7988_mac_port_get_caps(str
switch (port) {
/* Ports which are connected to switch PHYs. There is no MII pinout. */
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2609,8 +2609,6 @@ static void mt7531_mac_port_get_caps(str
+@@ -2786,8 +2786,6 @@ static void mt7531_mac_port_get_caps(str
static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port,
struct phylink_config *config)
{
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2692,17 +2692,6 @@ static bool mt753x_is_mac_port(u32 port)
+@@ -2869,17 +2869,6 @@ static bool mt753x_is_mac_port(u32 port)
}
static int
mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
phy_interface_t interface)
{
-@@ -2742,6 +2731,9 @@ mt753x_mac_config(struct dsa_switch *ds,
+@@ -2919,6 +2908,9 @@ mt753x_mac_config(struct dsa_switch *ds,
{
struct mt7530_priv *priv = ds->priv;
return priv->info->mac_port_config(ds, port, mode, state->interface);
}
-@@ -3205,7 +3197,6 @@ const struct mt753x_info mt753x_table[]
+@@ -3382,7 +3374,6 @@ const struct mt753x_info mt753x_table[]
.phy_write_c45 = mt7531_ind_c45_phy_write,
.cpu_port_config = mt7988_cpu_port_config,
.mac_port_get_caps = mt7988_mac_port_get_caps,
},
};
EXPORT_SYMBOL_GPL(mt753x_table);
-@@ -3233,8 +3224,7 @@ mt7530_probe_common(struct mt7530_priv *
+@@ -3410,8 +3401,7 @@ mt7530_probe_common(struct mt7530_priv *
* properly.
*/
if (!priv->info->sw_setup || !priv->info->phy_read_c22 ||
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2091,7 +2091,7 @@ mt7530_setup_irq(struct mt7530_priv *pri
+@@ -2254,7 +2254,7 @@ mt7530_setup_irq(struct mt7530_priv *pri
}
/* This register must be set for MT7530 to properly fire interrupts */
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2487,14 +2487,12 @@ mt7531_setup(struct dsa_switch *ds)
+@@ -2657,14 +2657,12 @@ mt7531_setup(struct dsa_switch *ds)
val = mt7530_read(priv, MT7531_TOP_SIG_SR);
priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN);
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2623,7 +2623,7 @@ static void mt7988_mac_port_get_caps(str
+@@ -2800,7 +2800,7 @@ static void mt7988_mac_port_get_caps(str
}
}
mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
phy_interface_t interface)
{
-@@ -2633,22 +2633,14 @@ mt7530_mac_config(struct dsa_switch *ds,
+@@ -2810,22 +2810,14 @@ mt7530_mac_config(struct dsa_switch *ds,
mt7530_setup_port5(priv->ds, interface);
else if (port == 6)
mt7530_setup_port6(priv->ds, interface);
val = mt7530_read(priv, MT7531_CLKGEN_CTRL);
val |= GP_CLK_EN;
val &= ~GP_MODE_MASK;
-@@ -2676,20 +2668,14 @@ static int mt7531_rgmii_setup(struct mt7
+@@ -2853,20 +2845,14 @@ static int mt7531_rgmii_setup(struct mt7
case PHY_INTERFACE_MODE_RGMII_ID:
break;
default:
mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
phy_interface_t interface)
{
-@@ -2697,42 +2683,21 @@ mt7531_mac_config(struct dsa_switch *ds,
+@@ -2874,42 +2860,21 @@ mt7531_mac_config(struct dsa_switch *ds,
struct phy_device *phydev;
struct dsa_port *dp;
}
static struct phylink_pcs *
-@@ -2761,17 +2726,11 @@ mt753x_phylink_mac_config(struct dsa_swi
+@@ -2938,17 +2903,11 @@ mt753x_phylink_mac_config(struct dsa_swi
u32 mcr_cur, mcr_new;
switch (port) {
if (priv->p5_intf_sel != P5_DISABLED)
priv->p5_interface = state->interface;
-@@ -2780,16 +2739,10 @@ mt753x_phylink_mac_config(struct dsa_swi
+@@ -2957,16 +2916,10 @@ mt753x_phylink_mac_config(struct dsa_swi
if (priv->p6_interface == state->interface)
break;
}
mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port));
-@@ -2872,7 +2825,6 @@ mt7531_cpu_port_config(struct dsa_switch
+@@ -3049,7 +3002,6 @@ mt7531_cpu_port_config(struct dsa_switch
struct mt7530_priv *priv = ds->priv;
phy_interface_t interface;
int speed;
switch (port) {
case 5:
-@@ -2897,9 +2849,8 @@ mt7531_cpu_port_config(struct dsa_switch
+@@ -3074,9 +3026,8 @@ mt7531_cpu_port_config(struct dsa_switch
else
speed = SPEED_1000;
mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL,
--- a/drivers/net/dsa/mt7530.h
+++ b/drivers/net/dsa/mt7530.h
-@@ -750,9 +750,9 @@ struct mt753x_info {
+@@ -760,9 +760,9 @@ struct mt753x_info {
void (*mac_port_validate)(struct dsa_switch *ds, int port,
phy_interface_t interface,
unsigned long *supported);
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -1002,18 +1002,10 @@ mt753x_trap_frames(struct mt7530_priv *p
- MT753X_BPDU_CPU_ONLY);
+@@ -1163,18 +1163,10 @@ mt753x_trap_frames(struct mt7530_priv *p
+ MT753X_BPDU_CPU_ONLY);
}
-static int
/* Enable Mediatek header mode on the cpu port */
mt7530_write(priv, MT7530_PVC_P(port),
-@@ -1039,8 +1031,6 @@ mt753x_cpu_port_enable(struct dsa_switch
+@@ -1200,8 +1192,6 @@ mt753x_cpu_port_enable(struct dsa_switch
/* Set to fallback mode for independent VLAN learning */
mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
MT7530_PORT_FALLBACK_MODE);
}
static int
-@@ -2297,8 +2287,6 @@ mt7530_setup(struct dsa_switch *ds)
+@@ -2458,8 +2448,6 @@ mt7530_setup(struct dsa_switch *ds)
val |= MHWTRAP_MANUAL;
mt7530_write(priv, MT7530_MHWTRAP, val);
- priv->p6_interface = PHY_INTERFACE_MODE_NA;
-
- mt753x_trap_frames(priv);
+ if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_40MHZ)
+ mt7530_pll_setup(priv);
- /* Enable and reset MIB counters */
-@@ -2313,9 +2301,7 @@ mt7530_setup(struct dsa_switch *ds)
+@@ -2477,9 +2465,7 @@ mt7530_setup(struct dsa_switch *ds)
mt7530_set(priv, MT7530_PSC_P(i), SA_DIS);
if (dsa_is_cpu_port(ds, i)) {
} else {
mt7530_port_disable(ds, i);
-@@ -2419,9 +2405,7 @@ mt7531_setup_common(struct dsa_switch *d
+@@ -2586,9 +2572,7 @@ mt7531_setup_common(struct dsa_switch *d
mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR);
if (dsa_is_cpu_port(ds, i)) {
} else {
mt7530_port_disable(ds, i);
-@@ -2510,10 +2494,6 @@ mt7531_setup(struct dsa_switch *ds)
+@@ -2680,10 +2664,6 @@ mt7531_setup(struct dsa_switch *ds)
mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
MT7531_GPIO0_INTERRUPT);
- priv->p5_interface = PHY_INTERFACE_MODE_NA;
- priv->p6_interface = PHY_INTERFACE_MODE_NA;
-
- /* Enable PHY core PLL, since phy_device has not yet been created
- * provided for phy_[read,write]_mmd_indirect is called, we provide
- * our own mt7531_ind_mmd_phy_[read,write] to complete this
-@@ -2725,26 +2705,9 @@ mt753x_phylink_mac_config(struct dsa_swi
+ /* Enable Energy-Efficient Ethernet (EEE) and PHY core PLL, since
+ * phy_device has not yet been created provided for
+ * phy_[read,write]_mmd_indirect is called, we provide our own
+@@ -2902,26 +2882,9 @@ mt753x_phylink_mac_config(struct dsa_swi
struct mt7530_priv *priv = ds->priv;
u32 mcr_cur, mcr_new;
mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port));
mcr_new = mcr_cur;
mcr_new &= ~PMCR_LINK_SETTINGS_MASK;
-@@ -2780,17 +2743,10 @@ static void mt753x_phylink_mac_link_up(s
+@@ -2957,17 +2920,10 @@ static void mt753x_phylink_mac_link_up(s
mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK;
mcr |= PMCR_FORCE_SPEED_1000;
break;
case SPEED_100:
-@@ -2808,6 +2764,7 @@ static void mt753x_phylink_mac_link_up(s
+@@ -2985,6 +2941,7 @@ static void mt753x_phylink_mac_link_up(s
if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, false) >= 0) {
switch (speed) {
case SPEED_1000:
mcr |= PMCR_FORCE_EEE1G;
break;
case SPEED_100:
-@@ -2819,61 +2776,6 @@ static void mt753x_phylink_mac_link_up(s
+@@ -2996,61 +2953,6 @@ static void mt753x_phylink_mac_link_up(s
mt7530_set(priv, MT7530_PMCR_P(port), mcr);
}
static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port,
struct phylink_config *config)
{
-@@ -3132,7 +3034,6 @@ const struct mt753x_info mt753x_table[]
+@@ -3309,7 +3211,6 @@ const struct mt753x_info mt753x_table[]
.phy_write_c22 = mt7531_ind_c22_phy_write,
.phy_read_c45 = mt7531_ind_c45_phy_read,
.phy_write_c45 = mt7531_ind_c45_phy_write,
.mac_port_get_caps = mt7531_mac_port_get_caps,
.mac_port_config = mt7531_mac_config,
},
-@@ -3144,7 +3045,6 @@ const struct mt753x_info mt753x_table[]
+@@ -3321,7 +3222,6 @@ const struct mt753x_info mt753x_table[]
.phy_write_c22 = mt7531_ind_c22_phy_write,
.phy_read_c45 = mt7531_ind_c45_phy_read,
.phy_write_c45 = mt7531_ind_c45_phy_write,
};
--- a/drivers/net/dsa/mt7530.h
+++ b/drivers/net/dsa/mt7530.h
-@@ -331,13 +331,6 @@ enum mt7530_vlan_port_acc_frm {
+@@ -340,13 +340,6 @@ enum mt7530_vlan_port_acc_frm {
PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
PMCR_FORCE_FDX | PMCR_FORCE_LNK | \
PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100)
#define MT7530_PMEEECR_P(x) (0x3004 + (x) * 0x100)
#define WAKEUP_TIME_1000(x) (((x) & 0xFF) << 24)
-@@ -744,7 +737,6 @@ struct mt753x_info {
+@@ -754,7 +747,6 @@ struct mt753x_info {
int regnum);
int (*phy_write_c45)(struct mt7530_priv *priv, int port, int devad,
int regnum, u16 val);
void (*mac_port_get_caps)(struct dsa_switch *ds, int port,
struct phylink_config *config);
void (*mac_port_validate)(struct dsa_switch *ds, int port,
-@@ -770,7 +762,6 @@ struct mt753x_info {
+@@ -780,7 +772,6 @@ struct mt753x_info {
* @ports: Holding the state among ports
* @reg_mutex: The lock for protecting among process accessing
* registers
* @p5_intf_sel: Holding the current port 5 interface select
* @p5_sgmii: Flag for distinguishing if port 5 of the MT7531 switch
* has got SGMII
-@@ -792,8 +783,6 @@ struct mt7530_priv {
+@@ -802,8 +793,6 @@ struct mt7530_priv {
const struct mt753x_info *info;
unsigned int id;
bool mcm;
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2670,16 +2670,6 @@ mt7531_mac_config(struct dsa_switch *ds,
+@@ -2847,16 +2847,6 @@ mt7531_mac_config(struct dsa_switch *ds,
}
}
static struct phylink_pcs *
mt753x_phylink_mac_select_pcs(struct dsa_switch *ds, int port,
phy_interface_t interface)
-@@ -2705,8 +2695,8 @@ mt753x_phylink_mac_config(struct dsa_swi
+@@ -2882,8 +2872,8 @@ mt753x_phylink_mac_config(struct dsa_swi
struct mt7530_priv *priv = ds->priv;
u32 mcr_cur, mcr_new;
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2848,17 +2848,9 @@ static int
+@@ -3025,17 +3025,9 @@ static int
mt753x_setup(struct dsa_switch *ds)
{
struct mt7530_priv *priv = ds->priv;
if (ret)
return ret;
-@@ -2870,6 +2862,14 @@ mt753x_setup(struct dsa_switch *ds)
+@@ -3047,6 +3039,14 @@ mt753x_setup(struct dsa_switch *ds)
if (ret && priv->irq)
mt7530_free_irq_common(priv);
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -1054,7 +1054,6 @@ mt7530_port_enable(struct dsa_switch *ds
+@@ -1215,7 +1215,6 @@ mt7530_port_enable(struct dsa_switch *ds
priv->ports[port].enable = true;
mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
priv->ports[port].pm);
mutex_unlock(&priv->reg_mutex);
-@@ -1074,7 +1073,6 @@ mt7530_port_disable(struct dsa_switch *d
+@@ -1235,7 +1234,6 @@ mt7530_port_disable(struct dsa_switch *d
priv->ports[port].enable = false;
mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
PCR_MATRIX_CLR);
mutex_unlock(&priv->reg_mutex);
}
-@@ -2293,6 +2291,12 @@ mt7530_setup(struct dsa_switch *ds)
+@@ -2457,6 +2455,12 @@ mt7530_setup(struct dsa_switch *ds)
mt7530_mib_reset(ds);
for (i = 0; i < MT7530_NUM_PORTS; i++) {
/* Disable forwarding by default on all ports */
mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
PCR_MATRIX_CLR);
-@@ -2395,6 +2399,12 @@ mt7531_setup_common(struct dsa_switch *d
+@@ -2562,6 +2566,12 @@ mt7531_setup_common(struct dsa_switch *d
UNU_FFP_MASK);
for (i = 0; i < MT7530_NUM_PORTS; i++) {
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2703,23 +2703,13 @@ mt753x_phylink_mac_config(struct dsa_swi
+@@ -2880,23 +2880,13 @@ mt753x_phylink_mac_config(struct dsa_swi
const struct phylink_link_state *state)
{
struct mt7530_priv *priv = ds->priv;
static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port,
--- a/drivers/net/dsa/mt7530.h
+++ b/drivers/net/dsa/mt7530.h
-@@ -324,8 +324,6 @@ enum mt7530_vlan_port_acc_frm {
+@@ -333,8 +333,6 @@ enum mt7530_vlan_port_acc_frm {
MT7531_FORCE_DPX | \
MT7531_FORCE_RX_FC | \
MT7531_FORCE_TX_FC)
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2228,6 +2228,12 @@ mt7530_setup(struct dsa_switch *ds)
+@@ -2391,6 +2391,12 @@ mt7530_setup(struct dsa_switch *ds)
}
}
+++ /dev/null
-From fa14c96eab3ec5b7cb44b06c0a54a851849a9810 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
-Date: Wed, 20 Mar 2024 23:45:30 +0300
-Subject: [PATCH 29/30] net: dsa: mt7530: fix improper frames on all 25MHz and
- 40MHz XTAL MT7530
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The MT7530 switch after reset initialises with a core clock frequency that
-works with a 25MHz XTAL connected to it. For 40MHz XTAL, the core clock
-frequency must be set to 500MHz.
-
-The mt7530_pll_setup() function is responsible of setting the core clock
-frequency. Currently, it runs on MT7530 with 25MHz and 40MHz XTAL. This
-causes MT7530 switch with 25MHz XTAL to egress and ingress frames
-improperly.
-
-Introduce a check to run it only on MT7530 with 40MHz XTAL.
-
-The core clock frequency is set by writing to a switch PHY's register.
-Access to the PHY's register is done via the MDIO bus the switch is also
-on. Therefore, it works only when the switch makes switch PHYs listen on
-the MDIO bus the switch is on. This is controlled either by the state of
-the ESW_P1_LED_1 pin after reset deassertion or modifying bit 5 of the
-modifiable trap register.
-
-When ESW_P1_LED_1 is pulled high, PHY indirect access is used. That means
-accessing PHY registers via the PHY indirect access control register of the
-switch.
-
-When ESW_P1_LED_1 is pulled low, PHY direct access is used. That means
-accessing PHY registers via the MDIO bus the switch is on.
-
-For MT7530 switch with 40MHz XTAL on a board with ESW_P1_LED_1 pulled high,
-the core clock frequency won't be set to 500MHz, causing the switch to
-egress and ingress frames improperly.
-
-Run mt7530_pll_setup() after PHY direct access is set on the modifiable
-trap register.
-
-With these two changes, all MT7530 switches with 25MHz and 40MHz, and
-P1_LED_1 pulled high or low, will egress and ingress frames properly.
-
-Link: https://github.com/BPI-SINOVOIP/BPI-R2-bsp/blob/4a5dd143f2172ec97a2872fa29c7c4cd520f45b5/linux-mt/drivers/net/ethernet/mediatek/gsw_mt7623.c#L1039
-Fixes: b8f126a8d543 ("net-next: dsa: add dsa support for Mediatek MT7530 switch")
-Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
-Link: https://lore.kernel.org/r/20240320-for-net-mt7530-fix-25mhz-xtal-with-direct-phy-access-v1-1-d92f605f1160@arinc9.com
-Signed-off-by: Paolo Abeni <pabeni@redhat.com>
----
- drivers/net/dsa/mt7530.c | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -2274,8 +2274,6 @@ mt7530_setup(struct dsa_switch *ds)
- SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
- SYS_CTRL_REG_RST);
-
-- mt7530_pll_setup(priv);
--
- /* Lower Tx driving for TRGMII path */
- for (i = 0; i < NUM_TRGMII_CTRL; i++)
- mt7530_write(priv, MT7530_TRGMII_TD_ODT(i),
-@@ -2291,6 +2289,9 @@ mt7530_setup(struct dsa_switch *ds)
- val |= MHWTRAP_MANUAL;
- mt7530_write(priv, MT7530_MHWTRAP, val);
-
-+ if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_40MHZ)
-+ mt7530_pll_setup(priv);
-+
- mt753x_trap_frames(priv);
-
- /* Enable and reset MIB counters */
--- a/drivers/net/dsa/mt7530.c
+++ b/drivers/net/dsa/mt7530.c
-@@ -2228,12 +2228,6 @@ mt7530_setup(struct dsa_switch *ds)
+@@ -2391,12 +2391,6 @@ mt7530_setup(struct dsa_switch *ds)
}
}
--- /dev/null
+From 5754b3bdcd872aa229881b8f07f84a8404c7d72a Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Fri, 12 Apr 2024 16:15:34 +0100
+Subject: [PATCH 1/5] net: dsa: mt7530: provide own phylink MAC operations
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Convert mt753x to provide its own phylink MAC operations, thus avoiding
+the shim layer in DSA's port.c
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Tested-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Link: https://lore.kernel.org/r/E1rvIco-006bQu-Fq@rmk-PC.armlinux.org.uk
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/dsa/mt7530.c | 46 +++++++++++++++++++++++++---------------
+ 1 file changed, 29 insertions(+), 17 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2858,28 +2858,34 @@ mt7531_mac_config(struct dsa_switch *ds,
+ }
+
+ static struct phylink_pcs *
+-mt753x_phylink_mac_select_pcs(struct dsa_switch *ds, int port,
++mt753x_phylink_mac_select_pcs(struct phylink_config *config,
+ phy_interface_t interface)
+ {
+- struct mt7530_priv *priv = ds->priv;
++ struct dsa_port *dp = dsa_phylink_to_port(config);
++ struct mt7530_priv *priv = dp->ds->priv;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_TRGMII:
+- return &priv->pcs[port].pcs;
++ return &priv->pcs[dp->index].pcs;
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
+- return priv->ports[port].sgmii_pcs;
++ return priv->ports[dp->index].sgmii_pcs;
+ default:
+ return NULL;
+ }
+ }
+
+ static void
+-mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
++mt753x_phylink_mac_config(struct phylink_config *config, unsigned int mode,
+ const struct phylink_link_state *state)
+ {
+- struct mt7530_priv *priv = ds->priv;
++ struct dsa_port *dp = dsa_phylink_to_port(config);
++ struct dsa_switch *ds = dp->ds;
++ struct mt7530_priv *priv;
++ int port = dp->index;
++
++ priv = ds->priv;
+
+ if ((port == 5 || port == 6) && priv->info->mac_port_config)
+ priv->info->mac_port_config(ds, port, mode, state->interface);
+@@ -2889,23 +2895,25 @@ mt753x_phylink_mac_config(struct dsa_swi
+ mt7530_set(priv, MT7530_PMCR_P(port), PMCR_EXT_PHY);
+ }
+
+-static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port,
++static void mt753x_phylink_mac_link_down(struct phylink_config *config,
+ unsigned int mode,
+ phy_interface_t interface)
+ {
+- struct mt7530_priv *priv = ds->priv;
++ struct dsa_port *dp = dsa_phylink_to_port(config);
++ struct mt7530_priv *priv = dp->ds->priv;
+
+- mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
++ mt7530_clear(priv, MT7530_PMCR_P(dp->index), PMCR_LINK_SETTINGS_MASK);
+ }
+
+-static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port,
++static void mt753x_phylink_mac_link_up(struct phylink_config *config,
++ struct phy_device *phydev,
+ unsigned int mode,
+ phy_interface_t interface,
+- struct phy_device *phydev,
+ int speed, int duplex,
+ bool tx_pause, bool rx_pause)
+ {
+- struct mt7530_priv *priv = ds->priv;
++ struct dsa_port *dp = dsa_phylink_to_port(config);
++ struct mt7530_priv *priv = dp->ds->priv;
+ u32 mcr;
+
+ mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK;
+@@ -2940,7 +2948,7 @@ static void mt753x_phylink_mac_link_up(s
+ }
+ }
+
+- mt7530_set(priv, MT7530_PMCR_P(port), mcr);
++ mt7530_set(priv, MT7530_PMCR_P(dp->index), mcr);
+ }
+
+ static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port,
+@@ -3160,16 +3168,19 @@ const struct dsa_switch_ops mt7530_switc
+ .port_mirror_add = mt753x_port_mirror_add,
+ .port_mirror_del = mt753x_port_mirror_del,
+ .phylink_get_caps = mt753x_phylink_get_caps,
+- .phylink_mac_select_pcs = mt753x_phylink_mac_select_pcs,
+- .phylink_mac_config = mt753x_phylink_mac_config,
+- .phylink_mac_link_down = mt753x_phylink_mac_link_down,
+- .phylink_mac_link_up = mt753x_phylink_mac_link_up,
+ .get_mac_eee = mt753x_get_mac_eee,
+ .set_mac_eee = mt753x_set_mac_eee,
+ .master_state_change = mt753x_conduit_state_change,
+ };
+ EXPORT_SYMBOL_GPL(mt7530_switch_ops);
+
++static const struct phylink_mac_ops mt753x_phylink_mac_ops = {
++ .mac_select_pcs = mt753x_phylink_mac_select_pcs,
++ .mac_config = mt753x_phylink_mac_config,
++ .mac_link_down = mt753x_phylink_mac_link_down,
++ .mac_link_up = mt753x_phylink_mac_link_up,
++};
++
+ const struct mt753x_info mt753x_table[] = {
+ [ID_MT7621] = {
+ .id = ID_MT7621,
+@@ -3247,6 +3258,7 @@ mt7530_probe_common(struct mt7530_priv *
+ priv->dev = dev;
+ priv->ds->priv = priv;
+ priv->ds->ops = &mt7530_switch_ops;
++ priv->ds->phylink_mac_ops = &mt753x_phylink_mac_ops;
+ mutex_init(&priv->reg_mutex);
+ dev_set_drvdata(dev, priv);
+
--- /dev/null
+From 5053a6cf1d50d785078562470d2a63695a9f3bf2 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Thu, 18 Apr 2024 08:35:30 +0300
+Subject: [PATCH 4/5] net: dsa: mt7530-mdio: read PHY address of switch from
+ device tree
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Read the PHY address the switch listens on from the reg property of the
+switch node on the device tree. This change brings support for MT7530
+switches on boards with such bootstrapping configuration where the switch
+listens on a different PHY address than the hardcoded PHY address on the
+driver, 31.
+
+As described on the "MT7621 Programming Guide v0.4" document, the MT7530
+switch and its PHYs can be configured to listen on the range of 7-12,
+15-20, 23-28, and 31 and 0-4 PHY addresses.
+
+There are operations where the switch PHY registers are used. For the PHY
+address of the control PHY, transform the MT753X_CTRL_PHY_ADDR constant
+into a macro and use it. The PHY address for the control PHY is 0 when the
+switch listens on 31. In any other case, it is one greater than the PHY
+address the switch listens on.
+
+Reviewed-by: Daniel Golle <daniel@makrotopia.org>
+Tested-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/dsa/mt7530-mdio.c | 28 +++++++++++++-------------
+ drivers/net/dsa/mt7530.c | 37 +++++++++++++++++++++++------------
+ drivers/net/dsa/mt7530.h | 4 +++-
+ 3 files changed, 41 insertions(+), 28 deletions(-)
+
+--- a/drivers/net/dsa/mt7530-mdio.c
++++ b/drivers/net/dsa/mt7530-mdio.c
+@@ -18,7 +18,8 @@
+ static int
+ mt7530_regmap_write(void *context, unsigned int reg, unsigned int val)
+ {
+- struct mii_bus *bus = context;
++ struct mt7530_priv *priv = context;
++ struct mii_bus *bus = priv->bus;
+ u16 page, r, lo, hi;
+ int ret;
+
+@@ -27,36 +28,35 @@ mt7530_regmap_write(void *context, unsig
+ lo = val & 0xffff;
+ hi = val >> 16;
+
+- /* MT7530 uses 31 as the pseudo port */
+- ret = bus->write(bus, 0x1f, 0x1f, page);
++ ret = bus->write(bus, priv->mdiodev->addr, 0x1f, page);
+ if (ret < 0)
+ return ret;
+
+- ret = bus->write(bus, 0x1f, r, lo);
++ ret = bus->write(bus, priv->mdiodev->addr, r, lo);
+ if (ret < 0)
+ return ret;
+
+- ret = bus->write(bus, 0x1f, 0x10, hi);
++ ret = bus->write(bus, priv->mdiodev->addr, 0x10, hi);
+ return ret;
+ }
+
+ static int
+ mt7530_regmap_read(void *context, unsigned int reg, unsigned int *val)
+ {
+- struct mii_bus *bus = context;
++ struct mt7530_priv *priv = context;
++ struct mii_bus *bus = priv->bus;
+ u16 page, r, lo, hi;
+ int ret;
+
+ page = (reg >> 6) & 0x3ff;
+ r = (reg >> 2) & 0xf;
+
+- /* MT7530 uses 31 as the pseudo port */
+- ret = bus->write(bus, 0x1f, 0x1f, page);
++ ret = bus->write(bus, priv->mdiodev->addr, 0x1f, page);
+ if (ret < 0)
+ return ret;
+
+- lo = bus->read(bus, 0x1f, r);
+- hi = bus->read(bus, 0x1f, 0x10);
++ lo = bus->read(bus, priv->mdiodev->addr, r);
++ hi = bus->read(bus, priv->mdiodev->addr, 0x10);
+
+ *val = (hi << 16) | (lo & 0xffff);
+
+@@ -107,8 +107,7 @@ mt7531_create_sgmii(struct mt7530_priv *
+ mt7531_pcs_config[i]->unlock = mt7530_mdio_regmap_unlock;
+ mt7531_pcs_config[i]->lock_arg = &priv->bus->mdio_lock;
+
+- regmap = devm_regmap_init(priv->dev,
+- &mt7530_regmap_bus, priv->bus,
++ regmap = devm_regmap_init(priv->dev, &mt7530_regmap_bus, priv,
+ mt7531_pcs_config[i]);
+ if (IS_ERR(regmap)) {
+ ret = PTR_ERR(regmap);
+@@ -153,6 +152,7 @@ mt7530_probe(struct mdio_device *mdiodev
+
+ priv->bus = mdiodev->bus;
+ priv->dev = &mdiodev->dev;
++ priv->mdiodev = mdiodev;
+
+ ret = mt7530_probe_common(priv);
+ if (ret)
+@@ -203,8 +203,8 @@ mt7530_probe(struct mdio_device *mdiodev
+ regmap_config->reg_stride = 4;
+ regmap_config->max_register = MT7530_CREV;
+ regmap_config->disable_locking = true;
+- priv->regmap = devm_regmap_init(priv->dev, &mt7530_regmap_bus,
+- priv->bus, regmap_config);
++ priv->regmap = devm_regmap_init(priv->dev, &mt7530_regmap_bus, priv,
++ regmap_config);
+ if (IS_ERR(priv->regmap))
+ return PTR_ERR(priv->regmap);
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -86,22 +86,26 @@ core_read_mmd_indirect(struct mt7530_pri
+ int value, ret;
+
+ /* Write the desired MMD Devad */
+- ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
++ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
++ MII_MMD_CTRL, devad);
+ if (ret < 0)
+ goto err;
+
+ /* Write the desired MMD register address */
+- ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
++ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
++ MII_MMD_DATA, prtad);
+ if (ret < 0)
+ goto err;
+
+ /* Select the Function : DATA with no post increment */
+- ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
++ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
++ MII_MMD_CTRL, devad | MII_MMD_CTRL_NOINCR);
+ if (ret < 0)
+ goto err;
+
+ /* Read the content of the MMD's selected register */
+- value = bus->read(bus, 0, MII_MMD_DATA);
++ value = bus->read(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
++ MII_MMD_DATA);
+
+ return value;
+ err:
+@@ -118,22 +122,26 @@ core_write_mmd_indirect(struct mt7530_pr
+ int ret;
+
+ /* Write the desired MMD Devad */
+- ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
++ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
++ MII_MMD_CTRL, devad);
+ if (ret < 0)
+ goto err;
+
+ /* Write the desired MMD register address */
+- ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
++ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
++ MII_MMD_DATA, prtad);
+ if (ret < 0)
+ goto err;
+
+ /* Select the Function : DATA with no post increment */
+- ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
++ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
++ MII_MMD_CTRL, devad | MII_MMD_CTRL_NOINCR);
+ if (ret < 0)
+ goto err;
+
+ /* Write the data into MMD's selected register */
+- ret = bus->write(bus, 0, MII_MMD_DATA, data);
++ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
++ MII_MMD_DATA, data);
+ err:
+ if (ret < 0)
+ dev_err(&bus->dev,
+@@ -2679,16 +2687,19 @@ mt7531_setup(struct dsa_switch *ds)
+ * phy_[read,write]_mmd_indirect is called, we provide our own
+ * mt7531_ind_mmd_phy_[read,write] to complete this function.
+ */
+- val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR,
++ val = mt7531_ind_c45_phy_read(priv,
++ MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
+ MDIO_MMD_VEND2, CORE_PLL_GROUP4);
+ val |= MT7531_RG_SYSPLL_DMY2 | MT7531_PHY_PLL_BYPASS_MODE;
+ val &= ~MT7531_PHY_PLL_OFF;
+- mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2,
+- CORE_PLL_GROUP4, val);
++ mt7531_ind_c45_phy_write(priv,
++ MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
++ MDIO_MMD_VEND2, CORE_PLL_GROUP4, val);
+
+ /* Disable EEE advertisement on the switch PHYs. */
+- for (i = MT753X_CTRL_PHY_ADDR;
+- i < MT753X_CTRL_PHY_ADDR + MT7530_NUM_PHYS; i++) {
++ for (i = MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr);
++ i < MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr) + MT7530_NUM_PHYS;
++ i++) {
+ mt7531_ind_c45_phy_write(priv, i, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
+ 0);
+ }
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -629,7 +629,7 @@ enum mt7531_clk_skew {
+ #define MT7531_PHY_PLL_OFF BIT(5)
+ #define MT7531_PHY_PLL_BYPASS_MODE BIT(4)
+
+-#define MT753X_CTRL_PHY_ADDR 0
++#define MT753X_CTRL_PHY_ADDR(addr) ((addr + 1) & 0x1f)
+
+ #define CORE_PLL_GROUP5 0x404
+ #define RG_LCDDS_PCW_NCPO1(x) ((x) & 0xffff)
+@@ -778,6 +778,7 @@ struct mt753x_info {
+ * @irq_enable: IRQ enable bits, synced to SYS_INT_EN
+ * @create_sgmii: Pointer to function creating SGMII PCS instance(s)
+ * @active_cpu_ports: Holding the active CPU ports
++ * @mdiodev: The pointer to the MDIO device structure
+ */
+ struct mt7530_priv {
+ struct device *dev;
+@@ -804,6 +805,7 @@ struct mt7530_priv {
+ u32 irq_enable;
+ int (*create_sgmii)(struct mt7530_priv *priv);
+ u8 active_cpu_ports;
++ struct mdio_device *mdiodev;
+ };
+
+ struct mt7530_hw_vlan_entry {
--- /dev/null
+From 9764a08b3d260f4e7799d34bbfe64463db940d74 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Thu, 18 Apr 2024 08:35:31 +0300
+Subject: [PATCH 5/5] net: dsa: mt7530: simplify core operations
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The core_rmw() function calls core_read_mmd_indirect() to read the
+requested register, and then calls core_write_mmd_indirect() to write the
+requested value to the register. Because Clause 22 is used to access Clause
+45 registers, some operations on core_write_mmd_indirect() are
+unnecessarily run. Get rid of core_read_mmd_indirect() and
+core_write_mmd_indirect(), and run only the necessary operations on
+core_write() and core_rmw().
+
+Reviewed-by: Daniel Golle <daniel@makrotopia.org>
+Tested-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/dsa/mt7530.c | 108 ++++++++++++++++-----------------------
+ 1 file changed, 43 insertions(+), 65 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -74,116 +74,94 @@ static const struct mt7530_mib_desc mt75
+ MIB_DESC(1, 0xb8, "RxArlDrop"),
+ };
+
+-/* Since phy_device has not yet been created and
+- * phy_{read,write}_mmd_indirect is not available, we provide our own
+- * core_{read,write}_mmd_indirect with core_{clear,write,set} wrappers
+- * to complete this function.
+- */
+-static int
+-core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad)
++static void
++mt7530_mutex_lock(struct mt7530_priv *priv)
++{
++ if (priv->bus)
++ mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
++}
++
++static void
++mt7530_mutex_unlock(struct mt7530_priv *priv)
++{
++ if (priv->bus)
++ mutex_unlock(&priv->bus->mdio_lock);
++}
++
++static void
++core_write(struct mt7530_priv *priv, u32 reg, u32 val)
+ {
+ struct mii_bus *bus = priv->bus;
+- int value, ret;
++ int ret;
++
++ mt7530_mutex_lock(priv);
+
+ /* Write the desired MMD Devad */
+ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
+- MII_MMD_CTRL, devad);
++ MII_MMD_CTRL, MDIO_MMD_VEND2);
+ if (ret < 0)
+ goto err;
+
+ /* Write the desired MMD register address */
+ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
+- MII_MMD_DATA, prtad);
++ MII_MMD_DATA, reg);
+ if (ret < 0)
+ goto err;
+
+ /* Select the Function : DATA with no post increment */
+ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
+- MII_MMD_CTRL, devad | MII_MMD_CTRL_NOINCR);
++ MII_MMD_CTRL, MDIO_MMD_VEND2 | MII_MMD_CTRL_NOINCR);
+ if (ret < 0)
+ goto err;
+
+- /* Read the content of the MMD's selected register */
+- value = bus->read(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
+- MII_MMD_DATA);
+-
+- return value;
++ /* Write the data into MMD's selected register */
++ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
++ MII_MMD_DATA, val);
+ err:
+- dev_err(&bus->dev, "failed to read mmd register\n");
++ if (ret < 0)
++ dev_err(&bus->dev, "failed to write mmd register\n");
+
+- return ret;
++ mt7530_mutex_unlock(priv);
+ }
+
+-static int
+-core_write_mmd_indirect(struct mt7530_priv *priv, int prtad,
+- int devad, u32 data)
++static void
++core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set)
+ {
+ struct mii_bus *bus = priv->bus;
++ u32 val;
+ int ret;
+
++ mt7530_mutex_lock(priv);
++
+ /* Write the desired MMD Devad */
+ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
+- MII_MMD_CTRL, devad);
++ MII_MMD_CTRL, MDIO_MMD_VEND2);
+ if (ret < 0)
+ goto err;
+
+ /* Write the desired MMD register address */
+ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
+- MII_MMD_DATA, prtad);
++ MII_MMD_DATA, reg);
+ if (ret < 0)
+ goto err;
+
+ /* Select the Function : DATA with no post increment */
+ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
+- MII_MMD_CTRL, devad | MII_MMD_CTRL_NOINCR);
++ MII_MMD_CTRL, MDIO_MMD_VEND2 | MII_MMD_CTRL_NOINCR);
+ if (ret < 0)
+ goto err;
+
++ /* Read the content of the MMD's selected register */
++ val = bus->read(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
++ MII_MMD_DATA);
++ val &= ~mask;
++ val |= set;
+ /* Write the data into MMD's selected register */
+ ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr),
+- MII_MMD_DATA, data);
++ MII_MMD_DATA, val);
+ err:
+ if (ret < 0)
+- dev_err(&bus->dev,
+- "failed to write mmd register\n");
+- return ret;
+-}
+-
+-static void
+-mt7530_mutex_lock(struct mt7530_priv *priv)
+-{
+- if (priv->bus)
+- mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
+-}
+-
+-static void
+-mt7530_mutex_unlock(struct mt7530_priv *priv)
+-{
+- if (priv->bus)
+- mutex_unlock(&priv->bus->mdio_lock);
+-}
+-
+-static void
+-core_write(struct mt7530_priv *priv, u32 reg, u32 val)
+-{
+- mt7530_mutex_lock(priv);
+-
+- core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
+-
+- mt7530_mutex_unlock(priv);
+-}
+-
+-static void
+-core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set)
+-{
+- u32 val;
+-
+- mt7530_mutex_lock(priv);
+-
+- val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2);
+- val &= ~mask;
+- val |= set;
+- core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
++ dev_err(&bus->dev, "failed to write mmd register\n");
+
+ mt7530_mutex_unlock(priv);
+ }
--- /dev/null
+From 856e8954a0a88d1a4d2b43e9002b9249131a156f Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:08 +0300
+Subject: [PATCH 01/15] net: dsa: mt7530: disable EEE abilities on failure on
+ MT7531 and MT7988
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The MT7531_FORCE_EEE1G and MT7531_FORCE_EEE100 bits let the
+PMCR_FORCE_EEE1G and PMCR_FORCE_EEE100 bits determine the 1G/100 EEE
+abilities of the MAC. If MT7531_FORCE_EEE1G and MT7531_FORCE_EEE100 are
+unset, the abilities are left to be determined by PHY auto polling.
+
+The commit 40b5d2f15c09 ("net: dsa: mt7530: Add support for EEE features")
+made it so that the PMCR_FORCE_EEE1G and PMCR_FORCE_EEE100 bits are set on
+mt753x_phylink_mac_link_up(). But it did not set the MT7531_FORCE_EEE1G and
+MT7531_FORCE_EEE100 bits. Because of this, the EEE abilities will be
+determined by PHY auto polling, regardless of the result of phy_init_eee().
+
+Define these bits and add them to the MT7531_FORCE_MODE mask which is set
+in mt7531_setup_common(). With this, there won't be any EEE abilities set
+when phy_init_eee() returns a negative value.
+
+Thanks to Russell for explaining when phy_init_eee() could return a
+negative value below.
+
+Looking at phy_init_eee(), it could return a negative value when:
+
+1. phydev->drv is NULL
+2. if genphy_c45_eee_is_active() returns negative
+3. if genphy_c45_eee_is_active() returns zero, it returns -EPROTONOSUPPORT
+4. if phy_set_bits_mmd() fails (e.g. communication error with the PHY)
+
+If we then look at genphy_c45_eee_is_active(), then:
+
+genphy_c45_read_eee_adv() and genphy_c45_read_eee_lpa() propagate their
+non-zero return values, otherwise this function returns zero or positive
+integer.
+
+If we then look at genphy_c45_read_eee_adv(), then a failure of
+phy_read_mmd() would cause a negative value to be returned.
+
+Looking at genphy_c45_read_eee_lpa(), the same is true.
+
+So, it can be summarised as:
+
+- phydev->drv is NULL
+- there is a communication error accessing the PHY
+- EEE is not active
+
+otherwise, it returns zero on success.
+
+If one wishes to determine whether an error occurred vs EEE not being
+supported through negotiation for the negotiated speed, if it returns
+-EPROTONOSUPPORT in the latter case. Other error codes mean either the
+driver has been unloaded or communication error.
+
+In conclusion, determining the EEE abilities by PHY auto polling shouldn't
+result in having any EEE abilities enabled, when one of the last two
+situations in the summary happens. And it seems that if phydev->drv is
+NULL, there would be bigger problems with the device than a broken link. So
+this is not a bugfix.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.h | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -328,11 +328,15 @@ enum mt7530_vlan_port_acc_frm {
+ #define MT7531_FORCE_DPX BIT(29)
+ #define MT7531_FORCE_RX_FC BIT(28)
+ #define MT7531_FORCE_TX_FC BIT(27)
++#define MT7531_FORCE_EEE100 BIT(26)
++#define MT7531_FORCE_EEE1G BIT(25)
+ #define MT7531_FORCE_MODE (MT7531_FORCE_LNK | \
+ MT7531_FORCE_SPD | \
+ MT7531_FORCE_DPX | \
+ MT7531_FORCE_RX_FC | \
+- MT7531_FORCE_TX_FC)
++ MT7531_FORCE_TX_FC | \
++ MT7531_FORCE_EEE100 | \
++ MT7531_FORCE_EEE1G)
+ #define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \
+ PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \
+ PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
--- /dev/null
+From 712ad00d2f43814c81a7abfcbc339690a05fb6a0 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:09 +0300
+Subject: [PATCH 02/15] net: dsa: mt7530: refactor MT7530_PMCR_P()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The MT7530_PMCR_P() registers are on MT7530, MT7531, and the switch on the
+MT7988 SoC. Rename the definition for them to MT753X_PMCR_P(). Bit 15 is
+for MT7530 only. Add MT7530 prefix to the definition for bit 15.
+
+Use GENMASK and FIELD_PREP for PMCR_IFG_XMIT().
+
+Rename PMCR_TX_EN and PMCR_RX_EN to PMCR_MAC_TX_EN and PMCR_MAC_TX_EN to
+follow the naming on the "MT7621 Giga Switch Programming Guide v0.3",
+"MT7531 Reference Manual for Development Board v1.0", and "MT7988A Wi-Fi 7
+Generation Router Platform: Datasheet (Open Version) v0.1" documents.
+
+These documents show that PMCR_RX_FC_EN is at bit 5. Correct this along
+with renaming it to PMCR_FORCE_RX_FC_EN, and the same for PMCR_TX_FC_EN.
+
+Remove PMCR_SPEED_MASK which doesn't have a use.
+
+Rename the force mode definitions for MT7531 to FORCE_MODE. Add MASK at the
+end for the mask that includes all force mode definitions.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 24 ++++++++---------
+ drivers/net/dsa/mt7530.h | 58 +++++++++++++++++++++-------------------
+ 2 files changed, 42 insertions(+), 40 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -896,7 +896,7 @@ static void mt7530_setup_port5(struct ds
+ val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
+
+ /* Setup the MAC by default for the cpu port */
+- mt7530_write(priv, MT7530_PMCR_P(5), 0x56300);
++ mt7530_write(priv, MT753X_PMCR_P(5), 0x56300);
+ break;
+ case P5_INTF_SEL_GMAC5:
+ /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */
+@@ -2444,8 +2444,8 @@ mt7530_setup(struct dsa_switch *ds)
+ /* Clear link settings and enable force mode to force link down
+ * on all ports until they're enabled later.
+ */
+- mt7530_rmw(priv, MT7530_PMCR_P(i), PMCR_LINK_SETTINGS_MASK |
+- PMCR_FORCE_MODE, PMCR_FORCE_MODE);
++ mt7530_rmw(priv, MT753X_PMCR_P(i), PMCR_LINK_SETTINGS_MASK |
++ MT7530_FORCE_MODE, MT7530_FORCE_MODE);
+
+ /* Disable forwarding by default on all ports */
+ mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
+@@ -2555,8 +2555,8 @@ mt7531_setup_common(struct dsa_switch *d
+ /* Clear link settings and enable force mode to force link down
+ * on all ports until they're enabled later.
+ */
+- mt7530_rmw(priv, MT7530_PMCR_P(i), PMCR_LINK_SETTINGS_MASK |
+- MT7531_FORCE_MODE, MT7531_FORCE_MODE);
++ mt7530_rmw(priv, MT753X_PMCR_P(i), PMCR_LINK_SETTINGS_MASK |
++ MT7531_FORCE_MODE_MASK, MT7531_FORCE_MODE_MASK);
+
+ /* Disable forwarding by default on all ports */
+ mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
+@@ -2639,7 +2639,7 @@ mt7531_setup(struct dsa_switch *ds)
+
+ /* Force link down on all ports before internal reset */
+ for (i = 0; i < MT7530_NUM_PORTS; i++)
+- mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK);
++ mt7530_write(priv, MT753X_PMCR_P(i), MT7531_FORCE_MODE_LNK);
+
+ /* Reset the switch through internal reset */
+ mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_SW_RST | SYS_CTRL_REG_RST);
+@@ -2881,7 +2881,7 @@ mt753x_phylink_mac_config(struct phylink
+
+ /* Are we connected to external phy */
+ if (port == 5 && dsa_is_user_port(ds, 5))
+- mt7530_set(priv, MT7530_PMCR_P(port), PMCR_EXT_PHY);
++ mt7530_set(priv, MT753X_PMCR_P(port), PMCR_EXT_PHY);
+ }
+
+ static void mt753x_phylink_mac_link_down(struct phylink_config *config,
+@@ -2891,7 +2891,7 @@ static void mt753x_phylink_mac_link_down
+ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct mt7530_priv *priv = dp->ds->priv;
+
+- mt7530_clear(priv, MT7530_PMCR_P(dp->index), PMCR_LINK_SETTINGS_MASK);
++ mt7530_clear(priv, MT753X_PMCR_P(dp->index), PMCR_LINK_SETTINGS_MASK);
+ }
+
+ static void mt753x_phylink_mac_link_up(struct phylink_config *config,
+@@ -2905,7 +2905,7 @@ static void mt753x_phylink_mac_link_up(s
+ struct mt7530_priv *priv = dp->ds->priv;
+ u32 mcr;
+
+- mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK;
++ mcr = PMCR_MAC_RX_EN | PMCR_MAC_TX_EN | PMCR_FORCE_LNK;
+
+ switch (speed) {
+ case SPEED_1000:
+@@ -2920,9 +2920,9 @@ static void mt753x_phylink_mac_link_up(s
+ if (duplex == DUPLEX_FULL) {
+ mcr |= PMCR_FORCE_FDX;
+ if (tx_pause)
+- mcr |= PMCR_TX_FC_EN;
++ mcr |= PMCR_FORCE_TX_FC_EN;
+ if (rx_pause)
+- mcr |= PMCR_RX_FC_EN;
++ mcr |= PMCR_FORCE_RX_FC_EN;
+ }
+
+ if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, false) >= 0) {
+@@ -2937,7 +2937,7 @@ static void mt753x_phylink_mac_link_up(s
+ }
+ }
+
+- mt7530_set(priv, MT7530_PMCR_P(dp->index), mcr);
++ mt7530_set(priv, MT753X_PMCR_P(dp->index), mcr);
+ }
+
+ static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port,
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -304,44 +304,46 @@ enum mt7530_vlan_port_acc_frm {
+ #define G0_PORT_VID_DEF G0_PORT_VID(0)
+
+ /* Register for port MAC control register */
+-#define MT7530_PMCR_P(x) (0x3000 + ((x) * 0x100))
+-#define PMCR_IFG_XMIT(x) (((x) & 0x3) << 18)
++#define MT753X_PMCR_P(x) (0x3000 + ((x) * 0x100))
++#define PMCR_IFG_XMIT_MASK GENMASK(19, 18)
++#define PMCR_IFG_XMIT(x) FIELD_PREP(PMCR_IFG_XMIT_MASK, x)
+ #define PMCR_EXT_PHY BIT(17)
+ #define PMCR_MAC_MODE BIT(16)
+-#define PMCR_FORCE_MODE BIT(15)
+-#define PMCR_TX_EN BIT(14)
+-#define PMCR_RX_EN BIT(13)
++#define MT7530_FORCE_MODE BIT(15)
++#define PMCR_MAC_TX_EN BIT(14)
++#define PMCR_MAC_RX_EN BIT(13)
+ #define PMCR_BACKOFF_EN BIT(9)
+ #define PMCR_BACKPR_EN BIT(8)
+ #define PMCR_FORCE_EEE1G BIT(7)
+ #define PMCR_FORCE_EEE100 BIT(6)
+-#define PMCR_TX_FC_EN BIT(5)
+-#define PMCR_RX_FC_EN BIT(4)
++#define PMCR_FORCE_RX_FC_EN BIT(5)
++#define PMCR_FORCE_TX_FC_EN BIT(4)
+ #define PMCR_FORCE_SPEED_1000 BIT(3)
+ #define PMCR_FORCE_SPEED_100 BIT(2)
+ #define PMCR_FORCE_FDX BIT(1)
+ #define PMCR_FORCE_LNK BIT(0)
+-#define PMCR_SPEED_MASK (PMCR_FORCE_SPEED_100 | \
+- PMCR_FORCE_SPEED_1000)
+-#define MT7531_FORCE_LNK BIT(31)
+-#define MT7531_FORCE_SPD BIT(30)
+-#define MT7531_FORCE_DPX BIT(29)
+-#define MT7531_FORCE_RX_FC BIT(28)
+-#define MT7531_FORCE_TX_FC BIT(27)
+-#define MT7531_FORCE_EEE100 BIT(26)
+-#define MT7531_FORCE_EEE1G BIT(25)
+-#define MT7531_FORCE_MODE (MT7531_FORCE_LNK | \
+- MT7531_FORCE_SPD | \
+- MT7531_FORCE_DPX | \
+- MT7531_FORCE_RX_FC | \
+- MT7531_FORCE_TX_FC | \
+- MT7531_FORCE_EEE100 | \
+- MT7531_FORCE_EEE1G)
+-#define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \
+- PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \
+- PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
+- PMCR_FORCE_FDX | PMCR_FORCE_LNK | \
+- PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100)
++#define MT7531_FORCE_MODE_LNK BIT(31)
++#define MT7531_FORCE_MODE_SPD BIT(30)
++#define MT7531_FORCE_MODE_DPX BIT(29)
++#define MT7531_FORCE_MODE_RX_FC BIT(28)
++#define MT7531_FORCE_MODE_TX_FC BIT(27)
++#define MT7531_FORCE_MODE_EEE100 BIT(26)
++#define MT7531_FORCE_MODE_EEE1G BIT(25)
++#define MT7531_FORCE_MODE_MASK (MT7531_FORCE_MODE_LNK | \
++ MT7531_FORCE_MODE_SPD | \
++ MT7531_FORCE_MODE_DPX | \
++ MT7531_FORCE_MODE_RX_FC | \
++ MT7531_FORCE_MODE_TX_FC | \
++ MT7531_FORCE_MODE_EEE100 | \
++ MT7531_FORCE_MODE_EEE1G)
++#define PMCR_LINK_SETTINGS_MASK (PMCR_MAC_TX_EN | PMCR_MAC_RX_EN | \
++ PMCR_FORCE_EEE1G | \
++ PMCR_FORCE_EEE100 | \
++ PMCR_FORCE_RX_FC_EN | \
++ PMCR_FORCE_TX_FC_EN | \
++ PMCR_FORCE_SPEED_1000 | \
++ PMCR_FORCE_SPEED_100 | \
++ PMCR_FORCE_FDX | PMCR_FORCE_LNK)
+
+ #define MT7530_PMEEECR_P(x) (0x3004 + (x) * 0x100)
+ #define WAKEUP_TIME_1000(x) (((x) & 0xFF) << 24)
--- /dev/null
+From 875ec5b67ab88e969b171e6e9ea803e3ed759614 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:10 +0300
+Subject: [PATCH 03/15] net: dsa: mt7530: rename p5_intf_sel and use only for
+ MT7530 switch
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The p5_intf_sel pointer is used to store the information of whether PHY
+muxing is used or not. PHY muxing is a feature specific to port 5 of the
+MT7530 switch. Do not use it for other switch models.
+
+Rename the pointer to p5_mode to store the mode the port is being used in.
+Rename the p5_interface_select enum to mt7530_p5_mode, the string
+representation to mt7530_p5_mode_str, and the enum elements.
+
+If PHY muxing is not detected, the default mode, GMAC5, will be used.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 62 +++++++++++++++++-----------------------
+ drivers/net/dsa/mt7530.h | 15 +++++-----
+ 2 files changed, 33 insertions(+), 44 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -857,19 +857,15 @@ mt7530_set_ageing_time(struct dsa_switch
+ return 0;
+ }
+
+-static const char *p5_intf_modes(unsigned int p5_interface)
++static const char *mt7530_p5_mode_str(unsigned int mode)
+ {
+- switch (p5_interface) {
+- case P5_DISABLED:
+- return "DISABLED";
+- case P5_INTF_SEL_PHY_P0:
+- return "PHY P0";
+- case P5_INTF_SEL_PHY_P4:
+- return "PHY P4";
+- case P5_INTF_SEL_GMAC5:
+- return "GMAC5";
++ switch (mode) {
++ case MUX_PHY_P0:
++ return "MUX PHY P0";
++ case MUX_PHY_P4:
++ return "MUX PHY P4";
+ default:
+- return "unknown";
++ return "GMAC5";
+ }
+ }
+
+@@ -886,23 +882,23 @@ static void mt7530_setup_port5(struct ds
+ val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS;
+ val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL;
+
+- switch (priv->p5_intf_sel) {
+- case P5_INTF_SEL_PHY_P0:
+- /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */
++ switch (priv->p5_mode) {
++ /* MUX_PHY_P0: P0 -> P5 -> SoC MAC */
++ case MUX_PHY_P0:
+ val |= MHWTRAP_PHY0_SEL;
+ fallthrough;
+- case P5_INTF_SEL_PHY_P4:
+- /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */
++
++ /* MUX_PHY_P4: P4 -> P5 -> SoC MAC */
++ case MUX_PHY_P4:
+ val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
+
+ /* Setup the MAC by default for the cpu port */
+ mt7530_write(priv, MT753X_PMCR_P(5), 0x56300);
+ break;
+- case P5_INTF_SEL_GMAC5:
+- /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */
+- val &= ~MHWTRAP_P5_DIS;
+- break;
++
++ /* GMAC5: P5 -> SoC MAC or external PHY */
+ default:
++ val &= ~MHWTRAP_P5_DIS;
+ break;
+ }
+
+@@ -930,8 +926,8 @@ static void mt7530_setup_port5(struct ds
+
+ mt7530_write(priv, MT7530_MHWTRAP, val);
+
+- dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n",
+- val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface));
++ dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, mode=%s, phy-mode=%s\n", val,
++ mt7530_p5_mode_str(priv->p5_mode), phy_modes(interface));
+
+ mutex_unlock(&priv->reg_mutex);
+ }
+@@ -2476,13 +2472,11 @@ mt7530_setup(struct dsa_switch *ds)
+ if (ret)
+ return ret;
+
+- /* Setup port 5 */
+- if (!dsa_is_unused_port(ds, 5)) {
+- priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
+- } else {
++ /* Check for PHY muxing on port 5 */
++ if (dsa_is_unused_port(ds, 5)) {
+ /* Scan the ethernet nodes. Look for GMAC1, lookup the used PHY.
+- * Set priv->p5_intf_sel to the appropriate value if PHY muxing
+- * is detected.
++ * Set priv->p5_mode to the appropriate value if PHY muxing is
++ * detected.
+ */
+ for_each_child_of_node(dn, mac_np) {
+ if (!of_device_is_compatible(mac_np,
+@@ -2506,17 +2500,16 @@ mt7530_setup(struct dsa_switch *ds)
+ }
+ id = of_mdio_parse_addr(ds->dev, phy_node);
+ if (id == 0)
+- priv->p5_intf_sel = P5_INTF_SEL_PHY_P0;
++ priv->p5_mode = MUX_PHY_P0;
+ if (id == 4)
+- priv->p5_intf_sel = P5_INTF_SEL_PHY_P4;
++ priv->p5_mode = MUX_PHY_P4;
+ }
+ of_node_put(mac_np);
+ of_node_put(phy_node);
+ break;
+ }
+
+- if (priv->p5_intf_sel == P5_INTF_SEL_PHY_P0 ||
+- priv->p5_intf_sel == P5_INTF_SEL_PHY_P4)
++ if (priv->p5_mode == MUX_PHY_P0 || priv->p5_mode == MUX_PHY_P4)
+ mt7530_setup_port5(ds, interface);
+ }
+
+@@ -2654,9 +2647,6 @@ mt7531_setup(struct dsa_switch *ds)
+ MT7531_EXT_P_MDIO_12);
+ }
+
+- if (!dsa_is_unused_port(ds, 5))
+- priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
+-
+ mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
+ MT7531_GPIO0_INTERRUPT);
+
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -708,12 +708,11 @@ struct mt7530_port {
+ struct phylink_pcs *sgmii_pcs;
+ };
+
+-/* Port 5 interface select definitions */
+-enum p5_interface_select {
+- P5_DISABLED,
+- P5_INTF_SEL_PHY_P0,
+- P5_INTF_SEL_PHY_P4,
+- P5_INTF_SEL_GMAC5,
++/* Port 5 mode definitions of the MT7530 switch */
++enum mt7530_p5_mode {
++ GMAC5,
++ MUX_PHY_P0,
++ MUX_PHY_P4,
+ };
+
+ struct mt7530_priv;
+@@ -776,7 +775,7 @@ struct mt753x_info {
+ * @ports: Holding the state among ports
+ * @reg_mutex: The lock for protecting among process accessing
+ * registers
+- * @p5_intf_sel: Holding the current port 5 interface select
++ * @p5_mode: Holding the current mode of port 5 of the MT7530 switch
+ * @p5_sgmii: Flag for distinguishing if port 5 of the MT7531 switch
+ * has got SGMII
+ * @irq: IRQ number of the switch
+@@ -798,7 +797,7 @@ struct mt7530_priv {
+ const struct mt753x_info *info;
+ unsigned int id;
+ bool mcm;
+- enum p5_interface_select p5_intf_sel;
++ enum mt7530_p5_mode p5_mode;
+ bool p5_sgmii;
+ u8 mirror_rx;
+ u8 mirror_tx;
--- /dev/null
+From 83fe3df057e641cd0e88425e579d7a5a370ca430 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:11 +0300
+Subject: [PATCH 04/15] net: dsa: mt7530: rename mt753x_bpdu_port_fw enum to
+ mt753x_to_cpu_fw
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The mt753x_bpdu_port_fw enum is globally used for manipulating the process
+of deciding the forwardable ports, specifically concerning the CPU port(s).
+Therefore, rename it and the values in it to mt753x_to_cpu_fw.
+
+Change FOLLOW_MFC to SYSTEM_DEFAULT to be on par with the switch documents.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 44 ++++++++++-------------
+ drivers/net/dsa/mt7530.h | 76 ++++++++++++++++++++--------------------
+ 2 files changed, 56 insertions(+), 64 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -1107,42 +1107,34 @@ mt753x_trap_frames(struct mt7530_priv *p
+ * VLAN-untagged.
+ */
+ mt7530_rmw(priv, MT753X_BPC,
+- MT753X_PAE_BPDU_FR | MT753X_PAE_EG_TAG_MASK |
+- MT753X_PAE_PORT_FW_MASK | MT753X_BPDU_EG_TAG_MASK |
+- MT753X_BPDU_PORT_FW_MASK,
+- MT753X_PAE_BPDU_FR |
+- MT753X_PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
+- MT753X_PAE_PORT_FW(MT753X_BPDU_CPU_ONLY) |
+- MT753X_BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
+- MT753X_BPDU_CPU_ONLY);
++ PAE_BPDU_FR | PAE_EG_TAG_MASK | PAE_PORT_FW_MASK |
++ BPDU_EG_TAG_MASK | BPDU_PORT_FW_MASK,
++ PAE_BPDU_FR | PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
++ PAE_PORT_FW(TO_CPU_FW_CPU_ONLY) |
++ BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
++ TO_CPU_FW_CPU_ONLY);
+
+ /* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and egress
+ * them VLAN-untagged.
+ */
+ mt7530_rmw(priv, MT753X_RGAC1,
+- MT753X_R02_BPDU_FR | MT753X_R02_EG_TAG_MASK |
+- MT753X_R02_PORT_FW_MASK | MT753X_R01_BPDU_FR |
+- MT753X_R01_EG_TAG_MASK | MT753X_R01_PORT_FW_MASK,
+- MT753X_R02_BPDU_FR |
+- MT753X_R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
+- MT753X_R02_PORT_FW(MT753X_BPDU_CPU_ONLY) |
+- MT753X_R01_BPDU_FR |
+- MT753X_R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
+- MT753X_BPDU_CPU_ONLY);
++ R02_BPDU_FR | R02_EG_TAG_MASK | R02_PORT_FW_MASK |
++ R01_BPDU_FR | R01_EG_TAG_MASK | R01_PORT_FW_MASK,
++ R02_BPDU_FR | R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
++ R02_PORT_FW(TO_CPU_FW_CPU_ONLY) | R01_BPDU_FR |
++ R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
++ TO_CPU_FW_CPU_ONLY);
+
+ /* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and egress
+ * them VLAN-untagged.
+ */
+ mt7530_rmw(priv, MT753X_RGAC2,
+- MT753X_R0E_BPDU_FR | MT753X_R0E_EG_TAG_MASK |
+- MT753X_R0E_PORT_FW_MASK | MT753X_R03_BPDU_FR |
+- MT753X_R03_EG_TAG_MASK | MT753X_R03_PORT_FW_MASK,
+- MT753X_R0E_BPDU_FR |
+- MT753X_R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
+- MT753X_R0E_PORT_FW(MT753X_BPDU_CPU_ONLY) |
+- MT753X_R03_BPDU_FR |
+- MT753X_R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
+- MT753X_BPDU_CPU_ONLY);
++ R0E_BPDU_FR | R0E_EG_TAG_MASK | R0E_PORT_FW_MASK |
++ R03_BPDU_FR | R03_EG_TAG_MASK | R03_PORT_FW_MASK,
++ R0E_BPDU_FR | R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
++ R0E_PORT_FW(TO_CPU_FW_CPU_ONLY) | R03_BPDU_FR |
++ R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
++ TO_CPU_FW_CPU_ONLY);
+ }
+
+ static void
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -67,47 +67,47 @@ enum mt753x_id {
+ #define MT753X_MIRROR_MASK(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
+ MT7531_MIRROR_MASK : MIRROR_MASK)
+
+-/* Registers for BPDU and PAE frame control*/
++/* Register for BPDU and PAE frame control */
+ #define MT753X_BPC 0x24
+-#define MT753X_PAE_BPDU_FR BIT(25)
+-#define MT753X_PAE_EG_TAG_MASK GENMASK(24, 22)
+-#define MT753X_PAE_EG_TAG(x) FIELD_PREP(MT753X_PAE_EG_TAG_MASK, x)
+-#define MT753X_PAE_PORT_FW_MASK GENMASK(18, 16)
+-#define MT753X_PAE_PORT_FW(x) FIELD_PREP(MT753X_PAE_PORT_FW_MASK, x)
+-#define MT753X_BPDU_EG_TAG_MASK GENMASK(8, 6)
+-#define MT753X_BPDU_EG_TAG(x) FIELD_PREP(MT753X_BPDU_EG_TAG_MASK, x)
+-#define MT753X_BPDU_PORT_FW_MASK GENMASK(2, 0)
++#define PAE_BPDU_FR BIT(25)
++#define PAE_EG_TAG_MASK GENMASK(24, 22)
++#define PAE_EG_TAG(x) FIELD_PREP(PAE_EG_TAG_MASK, x)
++#define PAE_PORT_FW_MASK GENMASK(18, 16)
++#define PAE_PORT_FW(x) FIELD_PREP(PAE_PORT_FW_MASK, x)
++#define BPDU_EG_TAG_MASK GENMASK(8, 6)
++#define BPDU_EG_TAG(x) FIELD_PREP(BPDU_EG_TAG_MASK, x)
++#define BPDU_PORT_FW_MASK GENMASK(2, 0)
+
+-/* Register for :01 and :02 MAC DA frame control */
++/* Register for 01-80-C2-00-00-[01,02] MAC DA frame control */
+ #define MT753X_RGAC1 0x28
+-#define MT753X_R02_BPDU_FR BIT(25)
+-#define MT753X_R02_EG_TAG_MASK GENMASK(24, 22)
+-#define MT753X_R02_EG_TAG(x) FIELD_PREP(MT753X_R02_EG_TAG_MASK, x)
+-#define MT753X_R02_PORT_FW_MASK GENMASK(18, 16)
+-#define MT753X_R02_PORT_FW(x) FIELD_PREP(MT753X_R02_PORT_FW_MASK, x)
+-#define MT753X_R01_BPDU_FR BIT(9)
+-#define MT753X_R01_EG_TAG_MASK GENMASK(8, 6)
+-#define MT753X_R01_EG_TAG(x) FIELD_PREP(MT753X_R01_EG_TAG_MASK, x)
+-#define MT753X_R01_PORT_FW_MASK GENMASK(2, 0)
++#define R02_BPDU_FR BIT(25)
++#define R02_EG_TAG_MASK GENMASK(24, 22)
++#define R02_EG_TAG(x) FIELD_PREP(R02_EG_TAG_MASK, x)
++#define R02_PORT_FW_MASK GENMASK(18, 16)
++#define R02_PORT_FW(x) FIELD_PREP(R02_PORT_FW_MASK, x)
++#define R01_BPDU_FR BIT(9)
++#define R01_EG_TAG_MASK GENMASK(8, 6)
++#define R01_EG_TAG(x) FIELD_PREP(R01_EG_TAG_MASK, x)
++#define R01_PORT_FW_MASK GENMASK(2, 0)
+
+-/* Register for :03 and :0E MAC DA frame control */
++/* Register for 01-80-C2-00-00-[03,0E] MAC DA frame control */
+ #define MT753X_RGAC2 0x2c
+-#define MT753X_R0E_BPDU_FR BIT(25)
+-#define MT753X_R0E_EG_TAG_MASK GENMASK(24, 22)
+-#define MT753X_R0E_EG_TAG(x) FIELD_PREP(MT753X_R0E_EG_TAG_MASK, x)
+-#define MT753X_R0E_PORT_FW_MASK GENMASK(18, 16)
+-#define MT753X_R0E_PORT_FW(x) FIELD_PREP(MT753X_R0E_PORT_FW_MASK, x)
+-#define MT753X_R03_BPDU_FR BIT(9)
+-#define MT753X_R03_EG_TAG_MASK GENMASK(8, 6)
+-#define MT753X_R03_EG_TAG(x) FIELD_PREP(MT753X_R03_EG_TAG_MASK, x)
+-#define MT753X_R03_PORT_FW_MASK GENMASK(2, 0)
++#define R0E_BPDU_FR BIT(25)
++#define R0E_EG_TAG_MASK GENMASK(24, 22)
++#define R0E_EG_TAG(x) FIELD_PREP(R0E_EG_TAG_MASK, x)
++#define R0E_PORT_FW_MASK GENMASK(18, 16)
++#define R0E_PORT_FW(x) FIELD_PREP(R0E_PORT_FW_MASK, x)
++#define R03_BPDU_FR BIT(9)
++#define R03_EG_TAG_MASK GENMASK(8, 6)
++#define R03_EG_TAG(x) FIELD_PREP(R03_EG_TAG_MASK, x)
++#define R03_PORT_FW_MASK GENMASK(2, 0)
+
+-enum mt753x_bpdu_port_fw {
+- MT753X_BPDU_FOLLOW_MFC,
+- MT753X_BPDU_CPU_EXCLUDE = 4,
+- MT753X_BPDU_CPU_INCLUDE = 5,
+- MT753X_BPDU_CPU_ONLY = 6,
+- MT753X_BPDU_DROP = 7,
++enum mt753x_to_cpu_fw {
++ TO_CPU_FW_SYSTEM_DEFAULT,
++ TO_CPU_FW_CPU_EXCLUDE = 4,
++ TO_CPU_FW_CPU_INCLUDE = 5,
++ TO_CPU_FW_CPU_ONLY = 6,
++ TO_CPU_FW_DROP = 7,
+ };
+
+ /* Registers for address table access */
--- /dev/null
+From 1dbc1bdc2869e6d2929235c70d64e393aa5a5fa2 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:12 +0300
+Subject: [PATCH 05/15] net: dsa: mt7530: refactor MT7530_MFC and MT7531_CFC,
+ add MT7531_QRY_FFP
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The MT7530_MFC register is on MT7530, MT7531, and the switch on the MT7988
+SoC. Rename it to MT753X_MFC. Bit 7 to 0 differs between MT7530 and
+MT7531/MT7988. Add MT7530 prefix to these definitions, and define the
+IGMP/MLD Query Frame Flooding Ports mask for MT7531.
+
+Rename the cases of MIRROR_MASK to MIRROR_PORT_MASK.
+
+Move mt753x_mirror_port_get() and mt753x_port_mirror_set() to mt7530.h as
+macros.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 38 ++++++++--------------
+ drivers/net/dsa/mt7530.h | 69 +++++++++++++++++++++++++---------------
+ 2 files changed, 57 insertions(+), 50 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -1147,7 +1147,7 @@ mt753x_cpu_port_enable(struct dsa_switch
+ PORT_SPEC_TAG);
+
+ /* Enable flooding on the CPU port */
+- mt7530_set(priv, MT7530_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) |
++ mt7530_set(priv, MT753X_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) |
+ UNU_FFP(BIT(port)));
+
+ /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on
+@@ -1311,15 +1311,15 @@ mt7530_port_bridge_flags(struct dsa_swit
+ flags.val & BR_LEARNING ? 0 : SA_DIS);
+
+ if (flags.mask & BR_FLOOD)
+- mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)),
++ mt7530_rmw(priv, MT753X_MFC, UNU_FFP(BIT(port)),
+ flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0);
+
+ if (flags.mask & BR_MCAST_FLOOD)
+- mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)),
++ mt7530_rmw(priv, MT753X_MFC, UNM_FFP(BIT(port)),
+ flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0);
+
+ if (flags.mask & BR_BCAST_FLOOD)
+- mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)),
++ mt7530_rmw(priv, MT753X_MFC, BC_FFP(BIT(port)),
+ flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0);
+
+ return 0;
+@@ -1855,20 +1855,6 @@ mt7530_port_vlan_del(struct dsa_switch *
+ return 0;
+ }
+
+-static int mt753x_mirror_port_get(unsigned int id, u32 val)
+-{
+- return (id == ID_MT7531 || id == ID_MT7988) ?
+- MT7531_MIRROR_PORT_GET(val) :
+- MIRROR_PORT(val);
+-}
+-
+-static int mt753x_mirror_port_set(unsigned int id, u32 val)
+-{
+- return (id == ID_MT7531 || id == ID_MT7988) ?
+- MT7531_MIRROR_PORT_SET(val) :
+- MIRROR_PORT(val);
+-}
+-
+ static int mt753x_port_mirror_add(struct dsa_switch *ds, int port,
+ struct dsa_mall_mirror_tc_entry *mirror,
+ bool ingress, struct netlink_ext_ack *extack)
+@@ -1884,14 +1870,14 @@ static int mt753x_port_mirror_add(struct
+ val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
+
+ /* MT7530 only supports one monitor port */
+- monitor_port = mt753x_mirror_port_get(priv->id, val);
++ monitor_port = MT753X_MIRROR_PORT_GET(priv->id, val);
+ if (val & MT753X_MIRROR_EN(priv->id) &&
+ monitor_port != mirror->to_local_port)
+ return -EEXIST;
+
+ val |= MT753X_MIRROR_EN(priv->id);
+- val &= ~MT753X_MIRROR_MASK(priv->id);
+- val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port);
++ val &= ~MT753X_MIRROR_PORT_MASK(priv->id);
++ val |= MT753X_MIRROR_PORT_SET(priv->id, mirror->to_local_port);
+ mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
+
+ val = mt7530_read(priv, MT7530_PCR_P(port));
+@@ -2533,7 +2519,7 @@ mt7531_setup_common(struct dsa_switch *d
+ mt7530_mib_reset(ds);
+
+ /* Disable flooding on all ports */
+- mt7530_clear(priv, MT7530_MFC, BC_FFP_MASK | UNM_FFP_MASK |
++ mt7530_clear(priv, MT753X_MFC, BC_FFP_MASK | UNM_FFP_MASK |
+ UNU_FFP_MASK);
+
+ for (i = 0; i < MT7530_NUM_PORTS; i++) {
+@@ -3089,10 +3075,12 @@ mt753x_conduit_state_change(struct dsa_s
+ else
+ priv->active_cpu_ports &= ~mask;
+
+- if (priv->active_cpu_ports)
+- val = CPU_EN | CPU_PORT(__ffs(priv->active_cpu_ports));
++ if (priv->active_cpu_ports) {
++ val = MT7530_CPU_EN |
++ MT7530_CPU_PORT(__ffs(priv->active_cpu_ports));
++ }
+
+- mt7530_rmw(priv, MT7530_MFC, CPU_EN | CPU_PORT_MASK, val);
++ mt7530_rmw(priv, MT753X_MFC, MT7530_CPU_EN | MT7530_CPU_PORT_MASK, val);
+ }
+
+ static int mt7988_setup(struct dsa_switch *ds)
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -36,36 +36,55 @@ enum mt753x_id {
+ #define MT753X_AGC 0xc
+ #define LOCAL_EN BIT(7)
+
+-/* Registers to mac forward control for unknown frames */
+-#define MT7530_MFC 0x10
+-#define BC_FFP(x) (((x) & 0xff) << 24)
+-#define BC_FFP_MASK BC_FFP(~0)
+-#define UNM_FFP(x) (((x) & 0xff) << 16)
+-#define UNM_FFP_MASK UNM_FFP(~0)
+-#define UNU_FFP(x) (((x) & 0xff) << 8)
+-#define UNU_FFP_MASK UNU_FFP(~0)
+-#define CPU_EN BIT(7)
+-#define CPU_PORT_MASK GENMASK(6, 4)
+-#define CPU_PORT(x) FIELD_PREP(CPU_PORT_MASK, x)
+-#define MIRROR_EN BIT(3)
+-#define MIRROR_PORT(x) ((x) & 0x7)
+-#define MIRROR_MASK 0x7
++/* Register for MAC forward control */
++#define MT753X_MFC 0x10
++#define BC_FFP_MASK GENMASK(31, 24)
++#define BC_FFP(x) FIELD_PREP(BC_FFP_MASK, x)
++#define UNM_FFP_MASK GENMASK(23, 16)
++#define UNM_FFP(x) FIELD_PREP(UNM_FFP_MASK, x)
++#define UNU_FFP_MASK GENMASK(15, 8)
++#define UNU_FFP(x) FIELD_PREP(UNU_FFP_MASK, x)
++#define MT7530_CPU_EN BIT(7)
++#define MT7530_CPU_PORT_MASK GENMASK(6, 4)
++#define MT7530_CPU_PORT(x) FIELD_PREP(MT7530_CPU_PORT_MASK, x)
++#define MT7530_MIRROR_EN BIT(3)
++#define MT7530_MIRROR_PORT_MASK GENMASK(2, 0)
++#define MT7530_MIRROR_PORT_GET(x) FIELD_GET(MT7530_MIRROR_PORT_MASK, x)
++#define MT7530_MIRROR_PORT_SET(x) FIELD_PREP(MT7530_MIRROR_PORT_MASK, x)
++#define MT7531_QRY_FFP_MASK GENMASK(7, 0)
++#define MT7531_QRY_FFP(x) FIELD_PREP(MT7531_QRY_FFP_MASK, x)
+
+-/* Registers for CPU forward control */
++/* Register for CPU forward control */
+ #define MT7531_CFC 0x4
+ #define MT7531_MIRROR_EN BIT(19)
+-#define MT7531_MIRROR_MASK (MIRROR_MASK << 16)
+-#define MT7531_MIRROR_PORT_GET(x) (((x) >> 16) & MIRROR_MASK)
+-#define MT7531_MIRROR_PORT_SET(x) (((x) & MIRROR_MASK) << 16)
++#define MT7531_MIRROR_PORT_MASK GENMASK(18, 16)
++#define MT7531_MIRROR_PORT_GET(x) FIELD_GET(MT7531_MIRROR_PORT_MASK, x)
++#define MT7531_MIRROR_PORT_SET(x) FIELD_PREP(MT7531_MIRROR_PORT_MASK, x)
+ #define MT7531_CPU_PMAP_MASK GENMASK(7, 0)
+ #define MT7531_CPU_PMAP(x) FIELD_PREP(MT7531_CPU_PMAP_MASK, x)
+
+-#define MT753X_MIRROR_REG(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
+- MT7531_CFC : MT7530_MFC)
+-#define MT753X_MIRROR_EN(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
+- MT7531_MIRROR_EN : MIRROR_EN)
+-#define MT753X_MIRROR_MASK(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
+- MT7531_MIRROR_MASK : MIRROR_MASK)
++#define MT753X_MIRROR_REG(id) ((id == ID_MT7531 || \
++ id == ID_MT7988) ? \
++ MT7531_CFC : MT753X_MFC)
++
++#define MT753X_MIRROR_EN(id) ((id == ID_MT7531 || \
++ id == ID_MT7988) ? \
++ MT7531_MIRROR_EN : MT7530_MIRROR_EN)
++
++#define MT753X_MIRROR_PORT_MASK(id) ((id == ID_MT7531 || \
++ id == ID_MT7988) ? \
++ MT7531_MIRROR_PORT_MASK : \
++ MT7530_MIRROR_PORT_MASK)
++
++#define MT753X_MIRROR_PORT_GET(id, val) ((id == ID_MT7531 || \
++ id == ID_MT7988) ? \
++ MT7531_MIRROR_PORT_GET(val) : \
++ MT7530_MIRROR_PORT_GET(val))
++
++#define MT753X_MIRROR_PORT_SET(id, val) ((id == ID_MT7531 || \
++ id == ID_MT7988) ? \
++ MT7531_MIRROR_PORT_SET(val) : \
++ MT7530_MIRROR_PORT_SET(val))
+
+ /* Register for BPDU and PAE frame control */
+ #define MT753X_BPC 0x24
--- /dev/null
+From 3ccf67597d35c06a7319e407b1c42f78a7966779 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:13 +0300
+Subject: [PATCH 06/15] net: dsa: mt7530: refactor MT7530_HWTRAP and
+ MT7530_MHWTRAP
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The MT7530_HWTRAP and MT7530_MHWTRAP registers are on MT7530 and MT7531.
+It's called hardware trap on MT7530, software trap on MT7531. That's
+because some bits of the trap on MT7530 cannot be modified by software
+whilst all bits of the trap on MT7531 can. Rename the definitions for them
+to MT753X_TRAP and MT753X_MTRAP. Add MT7530 and MT7531 prefixes to the
+definitions specific to the switch model.
+
+Remove the extra parentheses from MT7530_XTAL_40MHZ and MT7530_XTAL_20MHZ.
+
+Rename MHWTRAP_PHY0_SEL, MHWTRAP_MANUAL, and MHWTRAP_PHY_ACCESS to be on
+par with the "MT7621 Giga Switch Programming Guide v0.3" document.
+
+Make an enumaration for the XTAL frequency. Set the data type of the xtal
+variable on mt7531_pll_setup() to it.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 59 ++++++++++++++++++++--------------------
+ drivers/net/dsa/mt7530.h | 50 ++++++++++++++++------------------
+ 2 files changed, 54 insertions(+), 55 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -417,23 +417,23 @@ mt7530_setup_port6(struct dsa_switch *ds
+
+ mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, P6_INTF_MODE(1));
+
+- xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK;
++ xtal = mt7530_read(priv, MT753X_MTRAP) & MT7530_XTAL_MASK;
+
+- if (xtal == HWTRAP_XTAL_25MHZ)
++ if (xtal == MT7530_XTAL_25MHZ)
+ ssc_delta = 0x57;
+ else
+ ssc_delta = 0x87;
+
+ if (priv->id == ID_MT7621) {
+ /* PLL frequency: 125MHz: 1.0GBit */
+- if (xtal == HWTRAP_XTAL_40MHZ)
++ if (xtal == MT7530_XTAL_40MHZ)
+ ncpo1 = 0x0640;
+- if (xtal == HWTRAP_XTAL_25MHZ)
++ if (xtal == MT7530_XTAL_25MHZ)
+ ncpo1 = 0x0a00;
+ } else { /* PLL frequency: 250MHz: 2.0Gbit */
+- if (xtal == HWTRAP_XTAL_40MHZ)
++ if (xtal == MT7530_XTAL_40MHZ)
+ ncpo1 = 0x0c80;
+- if (xtal == HWTRAP_XTAL_25MHZ)
++ if (xtal == MT7530_XTAL_25MHZ)
+ ncpo1 = 0x1400;
+ }
+
+@@ -456,19 +456,20 @@ mt7530_setup_port6(struct dsa_switch *ds
+ static void
+ mt7531_pll_setup(struct mt7530_priv *priv)
+ {
++ enum mt7531_xtal_fsel xtal;
+ u32 top_sig;
+ u32 hwstrap;
+- u32 xtal;
+ u32 val;
+
+ val = mt7530_read(priv, MT7531_CREV);
+ top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR);
+- hwstrap = mt7530_read(priv, MT7531_HWTRAP);
++ hwstrap = mt7530_read(priv, MT753X_TRAP);
+ if ((val & CHIP_REV_M) > 0)
+- xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ :
+- HWTRAP_XTAL_FSEL_25MHZ;
++ xtal = (top_sig & PAD_MCM_SMI_EN) ? MT7531_XTAL_FSEL_40MHZ :
++ MT7531_XTAL_FSEL_25MHZ;
+ else
+- xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK;
++ xtal = (hwstrap & MT7531_XTAL25) ? MT7531_XTAL_FSEL_25MHZ :
++ MT7531_XTAL_FSEL_40MHZ;
+
+ /* Step 1 : Disable MT7531 COREPLL */
+ val = mt7530_read(priv, MT7531_PLLGP_EN);
+@@ -497,13 +498,13 @@ mt7531_pll_setup(struct mt7530_priv *pri
+ usleep_range(25, 35);
+
+ switch (xtal) {
+- case HWTRAP_XTAL_FSEL_25MHZ:
++ case MT7531_XTAL_FSEL_25MHZ:
+ val = mt7530_read(priv, MT7531_PLLGP_CR0);
+ val &= ~RG_COREPLL_SDM_PCW_M;
+ val |= 0x140000 << RG_COREPLL_SDM_PCW_S;
+ mt7530_write(priv, MT7531_PLLGP_CR0, val);
+ break;
+- case HWTRAP_XTAL_FSEL_40MHZ:
++ case MT7531_XTAL_FSEL_40MHZ:
+ val = mt7530_read(priv, MT7531_PLLGP_CR0);
+ val &= ~RG_COREPLL_SDM_PCW_M;
+ val |= 0x190000 << RG_COREPLL_SDM_PCW_S;
+@@ -877,20 +878,20 @@ static void mt7530_setup_port5(struct ds
+
+ mutex_lock(&priv->reg_mutex);
+
+- val = mt7530_read(priv, MT7530_MHWTRAP);
++ val = mt7530_read(priv, MT753X_MTRAP);
+
+- val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS;
+- val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL;
++ val |= MT7530_CHG_TRAP | MT7530_P5_MAC_SEL | MT7530_P5_DIS;
++ val &= ~MT7530_P5_RGMII_MODE & ~MT7530_P5_PHY0_SEL;
+
+ switch (priv->p5_mode) {
+ /* MUX_PHY_P0: P0 -> P5 -> SoC MAC */
+ case MUX_PHY_P0:
+- val |= MHWTRAP_PHY0_SEL;
++ val |= MT7530_P5_PHY0_SEL;
+ fallthrough;
+
+ /* MUX_PHY_P4: P4 -> P5 -> SoC MAC */
+ case MUX_PHY_P4:
+- val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
++ val &= ~MT7530_P5_MAC_SEL & ~MT7530_P5_DIS;
+
+ /* Setup the MAC by default for the cpu port */
+ mt7530_write(priv, MT753X_PMCR_P(5), 0x56300);
+@@ -898,13 +899,13 @@ static void mt7530_setup_port5(struct ds
+
+ /* GMAC5: P5 -> SoC MAC or external PHY */
+ default:
+- val &= ~MHWTRAP_P5_DIS;
++ val &= ~MT7530_P5_DIS;
+ break;
+ }
+
+ /* Setup RGMII settings */
+ if (phy_interface_mode_is_rgmii(interface)) {
+- val |= MHWTRAP_P5_RGMII_MODE;
++ val |= MT7530_P5_RGMII_MODE;
+
+ /* P5 RGMII RX Clock Control: delay setting for 1000M */
+ mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN);
+@@ -924,7 +925,7 @@ static void mt7530_setup_port5(struct ds
+ P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1));
+ }
+
+- mt7530_write(priv, MT7530_MHWTRAP, val);
++ mt7530_write(priv, MT753X_MTRAP, val);
+
+ dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, mode=%s, phy-mode=%s\n", val,
+ mt7530_p5_mode_str(priv->p5_mode), phy_modes(interface));
+@@ -2365,7 +2366,7 @@ mt7530_setup(struct dsa_switch *ds)
+ }
+
+ /* Waiting for MT7530 got to stable */
+- INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
++ INIT_MT7530_DUMMY_POLL(&p, priv, MT753X_TRAP);
+ ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
+ 20, 1000000);
+ if (ret < 0) {
+@@ -2380,7 +2381,7 @@ mt7530_setup(struct dsa_switch *ds)
+ return -ENODEV;
+ }
+
+- if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_20MHZ) {
++ if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_20MHZ) {
+ dev_err(priv->dev,
+ "MT7530 with a 20MHz XTAL is not supported!\n");
+ return -EINVAL;
+@@ -2401,12 +2402,12 @@ mt7530_setup(struct dsa_switch *ds)
+ RD_TAP_MASK, RD_TAP(16));
+
+ /* Enable port 6 */
+- val = mt7530_read(priv, MT7530_MHWTRAP);
+- val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS;
+- val |= MHWTRAP_MANUAL;
+- mt7530_write(priv, MT7530_MHWTRAP, val);
++ val = mt7530_read(priv, MT753X_MTRAP);
++ val &= ~MT7530_P6_DIS & ~MT7530_PHY_INDIRECT_ACCESS;
++ val |= MT7530_CHG_TRAP;
++ mt7530_write(priv, MT753X_MTRAP, val);
+
+- if ((val & HWTRAP_XTAL_MASK) == HWTRAP_XTAL_40MHZ)
++ if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_40MHZ)
+ mt7530_pll_setup(priv);
+
+ mt753x_trap_frames(priv);
+@@ -2586,7 +2587,7 @@ mt7531_setup(struct dsa_switch *ds)
+ }
+
+ /* Waiting for MT7530 got to stable */
+- INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
++ INIT_MT7530_DUMMY_POLL(&p, priv, MT753X_TRAP);
+ ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
+ 20, 1000000);
+ if (ret < 0) {
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -495,32 +495,30 @@ enum mt7531_clk_skew {
+ MT7531_CLK_SKEW_REVERSE = 3,
+ };
+
+-/* Register for hw trap status */
+-#define MT7530_HWTRAP 0x7800
+-#define HWTRAP_XTAL_MASK (BIT(10) | BIT(9))
+-#define HWTRAP_XTAL_25MHZ (BIT(10) | BIT(9))
+-#define HWTRAP_XTAL_40MHZ (BIT(10))
+-#define HWTRAP_XTAL_20MHZ (BIT(9))
++/* Register for trap status */
++#define MT753X_TRAP 0x7800
++#define MT7530_XTAL_MASK (BIT(10) | BIT(9))
++#define MT7530_XTAL_25MHZ (BIT(10) | BIT(9))
++#define MT7530_XTAL_40MHZ BIT(10)
++#define MT7530_XTAL_20MHZ BIT(9)
++#define MT7531_XTAL25 BIT(7)
+
+-#define MT7531_HWTRAP 0x7800
+-#define HWTRAP_XTAL_FSEL_MASK BIT(7)
+-#define HWTRAP_XTAL_FSEL_25MHZ BIT(7)
+-#define HWTRAP_XTAL_FSEL_40MHZ 0
+-/* Unique fields of (M)HWSTRAP for MT7531 */
+-#define XTAL_FSEL_S 7
+-#define XTAL_FSEL_M BIT(7)
+-#define PHY_EN BIT(6)
+-#define CHG_STRAP BIT(8)
++/* Register for trap modification */
++#define MT753X_MTRAP 0x7804
++#define MT7530_P5_PHY0_SEL BIT(20)
++#define MT7530_CHG_TRAP BIT(16)
++#define MT7530_P5_MAC_SEL BIT(13)
++#define MT7530_P6_DIS BIT(8)
++#define MT7530_P5_RGMII_MODE BIT(7)
++#define MT7530_P5_DIS BIT(6)
++#define MT7530_PHY_INDIRECT_ACCESS BIT(5)
++#define MT7531_CHG_STRAP BIT(8)
++#define MT7531_PHY_EN BIT(6)
+
+-/* Register for hw trap modification */
+-#define MT7530_MHWTRAP 0x7804
+-#define MHWTRAP_PHY0_SEL BIT(20)
+-#define MHWTRAP_MANUAL BIT(16)
+-#define MHWTRAP_P5_MAC_SEL BIT(13)
+-#define MHWTRAP_P6_DIS BIT(8)
+-#define MHWTRAP_P5_RGMII_MODE BIT(7)
+-#define MHWTRAP_P5_DIS BIT(6)
+-#define MHWTRAP_PHY_ACCESS BIT(5)
++enum mt7531_xtal_fsel {
++ MT7531_XTAL_FSEL_25MHZ,
++ MT7531_XTAL_FSEL_40MHZ,
++};
+
+ /* Register for TOP signal control */
+ #define MT7530_TOP_SIG_CTRL 0x7808
--- /dev/null
+From 2982f395c9a513b168f1e685588f70013cba2f5f Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:14 +0300
+Subject: [PATCH 07/15] net: dsa: mt7530: move MT753X_MTRAP operations for
+ MT7530
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+On MT7530, the media-independent interfaces of port 5 and 6 are controlled
+by the MT7530_P5_DIS and MT7530_P6_DIS bits of the hardware trap. Deal with
+these bits only when the relevant port is being enabled or disabled. This
+ensures that these ports will be disabled when they are not in use.
+
+Do not set MT7530_CHG_TRAP on mt7530_setup_port5() as that's already being
+done on mt7530_setup().
+
+Instead of globally setting MT7530_P5_MAC_SEL, clear it, then set it only
+on the appropriate case.
+
+If PHY muxing is detected, clear MT7530_P5_DIS before calling
+mt7530_setup_port5().
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 38 +++++++++++++++++++++++++++-----------
+ 1 file changed, 27 insertions(+), 11 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -880,8 +880,7 @@ static void mt7530_setup_port5(struct ds
+
+ val = mt7530_read(priv, MT753X_MTRAP);
+
+- val |= MT7530_CHG_TRAP | MT7530_P5_MAC_SEL | MT7530_P5_DIS;
+- val &= ~MT7530_P5_RGMII_MODE & ~MT7530_P5_PHY0_SEL;
++ val &= ~MT7530_P5_PHY0_SEL & ~MT7530_P5_MAC_SEL & ~MT7530_P5_RGMII_MODE;
+
+ switch (priv->p5_mode) {
+ /* MUX_PHY_P0: P0 -> P5 -> SoC MAC */
+@@ -891,15 +890,13 @@ static void mt7530_setup_port5(struct ds
+
+ /* MUX_PHY_P4: P4 -> P5 -> SoC MAC */
+ case MUX_PHY_P4:
+- val &= ~MT7530_P5_MAC_SEL & ~MT7530_P5_DIS;
+-
+ /* Setup the MAC by default for the cpu port */
+ mt7530_write(priv, MT753X_PMCR_P(5), 0x56300);
+ break;
+
+ /* GMAC5: P5 -> SoC MAC or external PHY */
+ default:
+- val &= ~MT7530_P5_DIS;
++ val |= MT7530_P5_MAC_SEL;
+ break;
+ }
+
+@@ -1193,6 +1190,14 @@ mt7530_port_enable(struct dsa_switch *ds
+
+ mutex_unlock(&priv->reg_mutex);
+
++ if (priv->id != ID_MT7530 && priv->id != ID_MT7621)
++ return 0;
++
++ if (port == 5)
++ mt7530_clear(priv, MT753X_MTRAP, MT7530_P5_DIS);
++ else if (port == 6)
++ mt7530_clear(priv, MT753X_MTRAP, MT7530_P6_DIS);
++
+ return 0;
+ }
+
+@@ -1211,6 +1216,14 @@ mt7530_port_disable(struct dsa_switch *d
+ PCR_MATRIX_CLR);
+
+ mutex_unlock(&priv->reg_mutex);
++
++ if (priv->id != ID_MT7530 && priv->id != ID_MT7621)
++ return;
++
++ if (port == 5)
++ mt7530_set(priv, MT753X_MTRAP, MT7530_P5_DIS);
++ else if (port == 6)
++ mt7530_set(priv, MT753X_MTRAP, MT7530_P6_DIS);
+ }
+
+ static int
+@@ -2401,11 +2414,11 @@ mt7530_setup(struct dsa_switch *ds)
+ mt7530_rmw(priv, MT7530_TRGMII_RD(i),
+ RD_TAP_MASK, RD_TAP(16));
+
+- /* Enable port 6 */
+- val = mt7530_read(priv, MT753X_MTRAP);
+- val &= ~MT7530_P6_DIS & ~MT7530_PHY_INDIRECT_ACCESS;
+- val |= MT7530_CHG_TRAP;
+- mt7530_write(priv, MT753X_MTRAP, val);
++ /* Allow modifying the trap and directly access PHY registers via the
++ * MDIO bus the switch is on.
++ */
++ mt7530_rmw(priv, MT753X_MTRAP, MT7530_CHG_TRAP |
++ MT7530_PHY_INDIRECT_ACCESS, MT7530_CHG_TRAP);
+
+ if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_40MHZ)
+ mt7530_pll_setup(priv);
+@@ -2488,8 +2501,11 @@ mt7530_setup(struct dsa_switch *ds)
+ break;
+ }
+
+- if (priv->p5_mode == MUX_PHY_P0 || priv->p5_mode == MUX_PHY_P4)
++ if (priv->p5_mode == MUX_PHY_P0 ||
++ priv->p5_mode == MUX_PHY_P4) {
++ mt7530_clear(priv, MT753X_MTRAP, MT7530_P5_DIS);
+ mt7530_setup_port5(ds, interface);
++ }
+ }
+
+ #ifdef CONFIG_GPIOLIB
--- /dev/null
+From 1f5669efca65564c7533704917f79003c6b36c9c Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:15 +0300
+Subject: [PATCH 08/15] net: dsa: mt7530: return mt7530_setup_mdio &
+ mt7531_setup_common on error
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The mt7530_setup_mdio() and mt7531_setup_common() functions should be
+checked for errors. Return if the functions return a non-zero value.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2667,7 +2667,9 @@ mt7531_setup(struct dsa_switch *ds)
+ 0);
+ }
+
+- mt7531_setup_common(ds);
++ ret = mt7531_setup_common(ds);
++ if (ret)
++ return ret;
+
+ /* Setup VLAN ID 0 for VLAN-unaware bridges */
+ ret = mt7530_setup_vlan0(priv);
+@@ -3020,6 +3022,8 @@ mt753x_setup(struct dsa_switch *ds)
+ ret = mt7530_setup_mdio(priv);
+ if (ret && priv->irq)
+ mt7530_free_irq_common(priv);
++ if (ret)
++ return ret;
+
+ /* Initialise the PCS devices */
+ for (i = 0; i < priv->ds->num_ports; i++) {
--- /dev/null
+From 6cc2d4ccd77509df74b7b8ef46bbc6ba0a571318 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:16 +0300
+Subject: [PATCH 09/15] net: dsa: mt7530: define MAC speed capabilities per
+ switch model
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+With the support of the MT7988 SoC switch, the MAC speed capabilities
+defined on mt753x_phylink_get_caps() won't apply to all switch models
+anymore. Move them to more appropriate locations instead of overwriting
+config->mac_capabilities.
+
+Remove the comment on mt753x_phylink_get_caps() as it's become invalid with
+the support of MT7531 and MT7988 SoC switch.
+
+Add break to case 6 of mt7988_mac_port_get_caps() to be explicit.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 15 ++++++++++-----
+ 1 file changed, 10 insertions(+), 5 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2685,6 +2685,8 @@ mt7531_setup(struct dsa_switch *ds)
+ static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port,
+ struct phylink_config *config)
+ {
++ config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD;
++
+ switch (port) {
+ /* Ports which are connected to switch PHYs. There is no MII pinout. */
+ case 0 ... 4:
+@@ -2716,6 +2718,8 @@ static void mt7531_mac_port_get_caps(str
+ {
+ struct mt7530_priv *priv = ds->priv;
+
++ config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD;
++
+ switch (port) {
+ /* Ports which are connected to switch PHYs. There is no MII pinout. */
+ case 0 ... 4:
+@@ -2755,14 +2759,17 @@ static void mt7988_mac_port_get_caps(str
+ case 0 ... 3:
+ __set_bit(PHY_INTERFACE_MODE_INTERNAL,
+ config->supported_interfaces);
++
++ config->mac_capabilities |= MAC_10 | MAC_100 | MAC_1000FD;
+ break;
+
+ /* Port 6 is connected to SoC's XGMII MAC. There is no MII pinout. */
+ case 6:
+ __set_bit(PHY_INTERFACE_MODE_INTERNAL,
+ config->supported_interfaces);
+- config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
+- MAC_10000FD;
++
++ config->mac_capabilities |= MAC_10000FD;
++ break;
+ }
+ }
+
+@@ -2932,9 +2939,7 @@ static void mt753x_phylink_get_caps(stru
+ {
+ struct mt7530_priv *priv = ds->priv;
+
+- /* This switch only supports full-duplex at 1Gbps */
+- config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
+- MAC_10 | MAC_100 | MAC_1000FD;
++ config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE;
+
+ priv->info->mac_port_get_caps(ds, port, config);
+ }
--- /dev/null
+From dd0f15fc877c10567699190bce0f55e96f4ad6b5 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:17 +0300
+Subject: [PATCH 10/15] net: dsa: mt7530: get rid of function sanity check
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Get rid of checking whether functions are filled properly. priv->info which
+is an mt753x_info structure is filled and checked for before this check.
+It's unnecessary checking whether it's filled properly.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 7 -------
+ 1 file changed, 7 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -3232,13 +3232,6 @@ mt7530_probe_common(struct mt7530_priv *
+ if (!priv->info)
+ return -EINVAL;
+
+- /* Sanity check if these required device operations are filled
+- * properly.
+- */
+- if (!priv->info->sw_setup || !priv->info->phy_read_c22 ||
+- !priv->info->phy_write_c22 || !priv->info->mac_port_get_caps)
+- return -EINVAL;
+-
+ priv->id = priv->info->id;
+ priv->dev = dev;
+ priv->ds->priv = priv;
--- /dev/null
+From 2dff9759602b069f97ccc939e15a47ca051b2983 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:18 +0300
+Subject: [PATCH 11/15] net: dsa: mt7530: refactor MT7530_PMEEECR_P()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The MT7530_PMEEECR_P() register is on MT7530, MT7531, and the switch on the
+MT7988 SoC. Rename the definition for them to MT753X_PMEEECR_P(). Use the
+FIELD_PREP and FIELD_GET macros. Rename GET_LPI_THRESH() and
+SET_LPI_THRESH() to LPI_THRESH_GET() and LPI_THRESH_SET().
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 8 ++++----
+ drivers/net/dsa/mt7530.h | 13 +++++++------
+ 2 files changed, 11 insertions(+), 10 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -3051,10 +3051,10 @@ static int mt753x_get_mac_eee(struct dsa
+ struct ethtool_eee *e)
+ {
+ struct mt7530_priv *priv = ds->priv;
+- u32 eeecr = mt7530_read(priv, MT7530_PMEEECR_P(port));
++ u32 eeecr = mt7530_read(priv, MT753X_PMEEECR_P(port));
+
+ e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN);
+- e->tx_lpi_timer = GET_LPI_THRESH(eeecr);
++ e->tx_lpi_timer = LPI_THRESH_GET(eeecr);
+
+ return 0;
+ }
+@@ -3068,11 +3068,11 @@ static int mt753x_set_mac_eee(struct dsa
+ if (e->tx_lpi_timer > 0xFFF)
+ return -EINVAL;
+
+- set = SET_LPI_THRESH(e->tx_lpi_timer);
++ set = LPI_THRESH_SET(e->tx_lpi_timer);
+ if (!e->tx_lpi_enabled)
+ /* Force LPI Mode without a delay */
+ set |= LPI_MODE_EN;
+- mt7530_rmw(priv, MT7530_PMEEECR_P(port), mask, set);
++ mt7530_rmw(priv, MT753X_PMEEECR_P(port), mask, set);
+
+ return 0;
+ }
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -364,13 +364,14 @@ enum mt7530_vlan_port_acc_frm {
+ PMCR_FORCE_SPEED_100 | \
+ PMCR_FORCE_FDX | PMCR_FORCE_LNK)
+
+-#define MT7530_PMEEECR_P(x) (0x3004 + (x) * 0x100)
+-#define WAKEUP_TIME_1000(x) (((x) & 0xFF) << 24)
+-#define WAKEUP_TIME_100(x) (((x) & 0xFF) << 16)
++#define MT753X_PMEEECR_P(x) (0x3004 + (x) * 0x100)
++#define WAKEUP_TIME_1000_MASK GENMASK(31, 24)
++#define WAKEUP_TIME_1000(x) FIELD_PREP(WAKEUP_TIME_1000_MASK, x)
++#define WAKEUP_TIME_100_MASK GENMASK(23, 16)
++#define WAKEUP_TIME_100(x) FIELD_PREP(WAKEUP_TIME_100_MASK, x)
+ #define LPI_THRESH_MASK GENMASK(15, 4)
+-#define LPI_THRESH_SHT 4
+-#define SET_LPI_THRESH(x) (((x) << LPI_THRESH_SHT) & LPI_THRESH_MASK)
+-#define GET_LPI_THRESH(x) (((x) & LPI_THRESH_MASK) >> LPI_THRESH_SHT)
++#define LPI_THRESH_GET(x) FIELD_GET(LPI_THRESH_MASK, x)
++#define LPI_THRESH_SET(x) FIELD_PREP(LPI_THRESH_MASK, x)
+ #define LPI_MODE_EN BIT(0)
+
+ #define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100)
--- /dev/null
+From 21d67c2fabfe40baf33202d3287b67b6c16f8382 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:19 +0300
+Subject: [PATCH 12/15] net: dsa: mt7530: get rid of mac_port_validate member
+ of mt753x_info
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The mac_port_validate member of the mt753x_info structure is not being
+used, remove it. Improve the member description section in the process.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.h | 10 +++-------
+ 1 file changed, 3 insertions(+), 7 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.h
++++ b/drivers/net/dsa/mt7530.h
+@@ -743,15 +743,14 @@ struct mt753x_pcs {
+
+ /* struct mt753x_info - This is the main data structure for holding the specific
+ * part for each supported device
++ * @id: Holding the identifier to a switch model
++ * @pcs_ops: Holding the pointer to the MAC PCS operations structure
+ * @sw_setup: Holding the handler to a device initialization
+ * @phy_read_c22: Holding the way reading PHY port using C22
+ * @phy_write_c22: Holding the way writing PHY port using C22
+ * @phy_read_c45: Holding the way reading PHY port using C45
+ * @phy_write_c45: Holding the way writing PHY port using C45
+- * @phy_mode_supported: Check if the PHY type is being supported on a certain
+- * port
+- * @mac_port_validate: Holding the way to set addition validate type for a
+- * certan MAC port
++ * @mac_port_get_caps: Holding the handler that provides MAC capabilities
+ * @mac_port_config: Holding the way setting up the PHY attribute to a
+ * certain MAC port
+ */
+@@ -770,9 +769,6 @@ struct mt753x_info {
+ int regnum, u16 val);
+ void (*mac_port_get_caps)(struct dsa_switch *ds, int port,
+ struct phylink_config *config);
+- void (*mac_port_validate)(struct dsa_switch *ds, int port,
+- phy_interface_t interface,
+- unsigned long *supported);
+ void (*mac_port_config)(struct dsa_switch *ds, int port,
+ unsigned int mode,
+ phy_interface_t interface);
--- /dev/null
+From 6efc8ae3eb0363328f479191a0cf0dc12a16e090 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:20 +0300
+Subject: [PATCH 13/15] net: dsa: mt7530: use priv->ds->num_ports instead of
+ MT7530_NUM_PORTS
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Use priv->ds->num_ports on all for loops which configure the switch
+registers. In the future, the value of MT7530_NUM_PORTS will depend on
+priv->id. Therefore, this change prepares the subdriver for a simpler
+implementation.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -1411,7 +1411,7 @@ mt7530_port_set_vlan_unaware(struct dsa_
+ mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
+ G0_PORT_VID_DEF);
+
+- for (i = 0; i < MT7530_NUM_PORTS; i++) {
++ for (i = 0; i < priv->ds->num_ports; i++) {
+ if (dsa_is_user_port(ds, i) &&
+ dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) {
+ all_user_ports_removed = false;
+@@ -2428,7 +2428,7 @@ mt7530_setup(struct dsa_switch *ds)
+ /* Enable and reset MIB counters */
+ mt7530_mib_reset(ds);
+
+- for (i = 0; i < MT7530_NUM_PORTS; i++) {
++ for (i = 0; i < priv->ds->num_ports; i++) {
+ /* Clear link settings and enable force mode to force link down
+ * on all ports until they're enabled later.
+ */
+@@ -2539,7 +2539,7 @@ mt7531_setup_common(struct dsa_switch *d
+ mt7530_clear(priv, MT753X_MFC, BC_FFP_MASK | UNM_FFP_MASK |
+ UNU_FFP_MASK);
+
+- for (i = 0; i < MT7530_NUM_PORTS; i++) {
++ for (i = 0; i < priv->ds->num_ports; i++) {
+ /* Clear link settings and enable force mode to force link down
+ * on all ports until they're enabled later.
+ */
+@@ -2626,7 +2626,7 @@ mt7531_setup(struct dsa_switch *ds)
+ priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN);
+
+ /* Force link down on all ports before internal reset */
+- for (i = 0; i < MT7530_NUM_PORTS; i++)
++ for (i = 0; i < priv->ds->num_ports; i++)
+ mt7530_write(priv, MT753X_PMCR_P(i), MT7531_FORCE_MODE_LNK);
+
+ /* Reset the switch through internal reset */
--- /dev/null
+From c078ebbf5f6f6d8390035a9f92eeab766b78884d Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:21 +0300
+Subject: [PATCH 14/15] net: dsa: mt7530: do not pass port variable to
+ mt7531_rgmii_setup()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The mt7531_rgmii_setup() function does not use the port variable, do not
+pass the variable to it.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2785,7 +2785,7 @@ mt7530_mac_config(struct dsa_switch *ds,
+ mt7530_setup_port6(priv->ds, interface);
+ }
+
+-static void mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port,
++static void mt7531_rgmii_setup(struct mt7530_priv *priv,
+ phy_interface_t interface,
+ struct phy_device *phydev)
+ {
+@@ -2836,7 +2836,7 @@ mt7531_mac_config(struct dsa_switch *ds,
+ if (phy_interface_mode_is_rgmii(interface)) {
+ dp = dsa_to_port(ds, port);
+ phydev = dp->slave->phydev;
+- mt7531_rgmii_setup(priv, port, interface, phydev);
++ mt7531_rgmii_setup(priv, interface, phydev);
+ }
+ }
+
--- /dev/null
+From e7a9cc3cc00b40e0bc2bae40bd2ece0e48fa51d5 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
+Date: Mon, 22 Apr 2024 10:15:22 +0300
+Subject: [PATCH 15/15] net: dsa: mt7530: explain exposing MDIO bus of MT7531AE
+ better
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Unlike MT7531BE, the GPIO 6-12 pins are not used for RGMII on MT7531AE.
+Therefore, the GPIO 11-12 pins are set to function as MDC and MDIO to
+expose the MDIO bus of the switch. Replace the comment with a better
+explanation.
+
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+ drivers/net/dsa/mt7530.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2635,7 +2635,10 @@ mt7531_setup(struct dsa_switch *ds)
+ if (!priv->p5_sgmii) {
+ mt7531_pll_setup(priv);
+ } else {
+- /* Let ds->slave_mii_bus be able to access external phy. */
++ /* Unlike MT7531BE, the GPIO 6-12 pins are not used for RGMII on
++ * MT7531AE. Set the GPIO 11-12 pins to function as MDC and MDIO
++ * to expose the MDIO bus of the switch.
++ */
+ mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK,
+ MT7531_EXT_P_MDC_11);
+ mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK,
# CONFIG_SPI_BCM2835 is not set
# CONFIG_SPI_BCM63XX_HSSPI is not set
# CONFIG_SPI_BCM_QSPI is not set
+# CONFIG_SPI_BCMBCA_HSSPI is not set
# CONFIG_SPI_BITBANG is not set
# CONFIG_SPI_BUTTERFLY is not set
# CONFIG_SPI_CADENCE is not set
obj-$(CONFIG_NETFILTER_XT_TARGET_LED) += xt_LED.o
--- /dev/null
+++ b/net/netfilter/xt_FLOWOFFLOAD.c
-@@ -0,0 +1,701 @@
+@@ -0,0 +1,702 @@
+/*
+ * Copyright (C) 2018-2021 Felix Fietkau <nbd@nbd.name>
+ *
+ proto = veth->h_vlan_encapsulated_proto;
+ break;
+ case htons(ETH_P_PPP_SES):
-+ proto = nf_flow_pppoe_proto(skb);
++ if (!nf_flow_pppoe_proto(skb, &proto))
++ return NF_ACCEPT;
+ break;
+ default:
+ proto = skb->protocol;
--- /dev/null
+From: Felix Fietkau <nbd@nbd.name>
+Date: Tue, 23 Apr 2024 12:35:21 +0200
+Subject: [PATCH] net: enable fraglist GRO by default
+
+This can significantly improve performance for packet forwarding/bridging
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/include/linux/netdev_features.h
++++ b/include/linux/netdev_features.h
+@@ -242,10 +242,10 @@ static inline int find_next_netdev_featu
+ #define NETIF_F_UPPER_DISABLES NETIF_F_LRO
+
+ /* changeable features with no special hardware requirements */
+-#define NETIF_F_SOFT_FEATURES (NETIF_F_GSO | NETIF_F_GRO)
++#define NETIF_F_SOFT_FEATURES (NETIF_F_GSO | NETIF_F_GRO | NETIF_F_GRO_FRAGLIST)
+
+ /* Changeable features with no special hardware requirements that defaults to off. */
+-#define NETIF_F_SOFT_FEATURES_OFF (NETIF_F_GRO_FRAGLIST | NETIF_F_GRO_UDP_FWD)
++#define NETIF_F_SOFT_FEATURES_OFF (NETIF_F_GRO_UDP_FWD)
+
+ #define NETIF_F_VLAN_FEATURES (NETIF_F_HW_VLAN_CTAG_FILTER | \
+ NETIF_F_HW_VLAN_CTAG_RX | \
obj-$(CONFIG_NETFILTER_XT_TARGET_LED) += xt_LED.o
--- /dev/null
+++ b/net/netfilter/xt_FLOWOFFLOAD.c
-@@ -0,0 +1,702 @@
+@@ -0,0 +1,703 @@
+/*
+ * Copyright (C) 2018-2021 Felix Fietkau <nbd@nbd.name>
+ *
+ proto = veth->h_vlan_encapsulated_proto;
+ break;
+ case htons(ETH_P_PPP_SES):
-+ proto = nf_flow_pppoe_proto(skb);
++ if (!nf_flow_pppoe_proto(skb, &proto))
++ return NF_ACCEPT;
+ break;
+ default:
+ proto = skb->protocol;
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
-@@ -3488,6 +3488,9 @@ static int mv88e6xxx_setup_port(struct m
+@@ -3500,6 +3500,9 @@ static int mv88e6xxx_setup_port(struct m
else
reg = 1 << port;
const struct header_ops *header_ops;
unsigned char operstate;
-@@ -2206,6 +2213,10 @@ struct net_device {
+@@ -2204,6 +2211,10 @@ struct net_device {
struct mctp_dev __rcu *mctp_ptr;
#endif
*/
--- a/include/linux/skbuff.h
+++ b/include/linux/skbuff.h
-@@ -3046,6 +3046,10 @@ static inline int pskb_trim(struct sk_bu
+@@ -3045,6 +3045,10 @@ static inline int pskb_trim(struct sk_bu
return (len < skb->len) ? __pskb_trim(skb, len) : 0;
}
/**
* pskb_trim_unique - remove end from a paged unique (not cloned) buffer
* @skb: buffer to alter
-@@ -3195,16 +3199,6 @@ static inline struct sk_buff *dev_alloc_
+@@ -3194,16 +3198,6 @@ static inline struct sk_buff *dev_alloc_
}
{
--- a/net/ethernet/eth.c
+++ b/net/ethernet/eth.c
-@@ -171,6 +171,12 @@ __be16 eth_type_trans(struct sk_buff *sk
+@@ -159,6 +159,12 @@ __be16 eth_type_trans(struct sk_buff *sk
const struct ethhdr *eth;
skb->dev = dev;
--- /dev/null
+From: Felix Fietkau <nbd@nbd.name>
+Date: Tue, 23 Apr 2024 12:35:21 +0200
+Subject: [PATCH] net: enable fraglist GRO by default
+
+This can significantly improve performance for packet forwarding/bridging
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/include/linux/netdev_features.h
++++ b/include/linux/netdev_features.h
+@@ -242,10 +242,10 @@ static inline int find_next_netdev_featu
+ #define NETIF_F_UPPER_DISABLES NETIF_F_LRO
+
+ /* changeable features with no special hardware requirements */
+-#define NETIF_F_SOFT_FEATURES (NETIF_F_GSO | NETIF_F_GRO)
++#define NETIF_F_SOFT_FEATURES (NETIF_F_GSO | NETIF_F_GRO | NETIF_F_GRO_FRAGLIST)
+
+ /* Changeable features with no special hardware requirements that defaults to off. */
+-#define NETIF_F_SOFT_FEATURES_OFF (NETIF_F_GRO_FRAGLIST | NETIF_F_GRO_UDP_FWD)
++#define NETIF_F_SOFT_FEATURES_OFF (NETIF_F_GRO_UDP_FWD)
+
+ #define NETIF_F_VLAN_FEATURES (NETIF_F_HW_VLAN_CTAG_FILTER | \
+ NETIF_F_HW_VLAN_CTAG_RX | \
obj-$(CONFIG_NETFILTER_XT_TARGET_LED) += xt_LED.o
--- /dev/null
+++ b/net/netfilter/xt_FLOWOFFLOAD.c
-@@ -0,0 +1,702 @@
+@@ -0,0 +1,703 @@
+/*
+ * Copyright (C) 2018-2021 Felix Fietkau <nbd@nbd.name>
+ *
+ proto = veth->h_vlan_encapsulated_proto;
+ break;
+ case htons(ETH_P_PPP_SES):
-+ proto = nf_flow_pppoe_proto(skb);
++ if (!nf_flow_pppoe_proto(skb, &proto))
++ return NF_ACCEPT;
+ break;
+ default:
+ proto = skb->protocol;
const struct header_ops *header_ops;
unsigned char operstate;
-@@ -2259,6 +2266,10 @@ struct net_device {
+@@ -2257,6 +2264,10 @@ struct net_device {
struct mctp_dev __rcu *mctp_ptr;
#endif
*/
--- a/include/linux/skbuff.h
+++ b/include/linux/skbuff.h
-@@ -3081,6 +3081,10 @@ static inline int pskb_trim(struct sk_bu
+@@ -3080,6 +3080,10 @@ static inline int pskb_trim(struct sk_bu
return (len < skb->len) ? __pskb_trim(skb, len) : 0;
}
/**
* pskb_trim_unique - remove end from a paged unique (not cloned) buffer
* @skb: buffer to alter
-@@ -3246,16 +3250,6 @@ static inline struct sk_buff *dev_alloc_
+@@ -3245,16 +3249,6 @@ static inline struct sk_buff *dev_alloc_
}
{
--- a/net/ethernet/eth.c
+++ b/net/ethernet/eth.c
-@@ -171,6 +171,12 @@ __be16 eth_type_trans(struct sk_buff *sk
+@@ -159,6 +159,12 @@ __be16 eth_type_trans(struct sk_buff *sk
const struct ethhdr *eth;
skb->dev = dev;
#define QUECTEL_VENDOR_ID 0x2c7c
/* These Quectel products use Quectel's vendor ID */
-@@ -1152,6 +1157,11 @@ static const struct usb_device_id option
+@@ -1156,6 +1161,11 @@ static const struct usb_device_id option
{ USB_DEVICE(QUALCOMM_VENDOR_ID, 0x0023)}, /* ONYX 3G device */
{ USB_DEVICE(QUALCOMM_VENDOR_ID, 0x9000), /* SIMCom SIM5218 */
.driver_info = NCTRL(0) | NCTRL(1) | NCTRL(2) | NCTRL(3) | RSVD(4) },
/* Quectel products using Qualcomm vendor ID */
{ USB_DEVICE(QUALCOMM_VENDOR_ID, QUECTEL_PRODUCT_UC15)},
{ USB_DEVICE(QUALCOMM_VENDOR_ID, QUECTEL_PRODUCT_UC20),
-@@ -1193,6 +1203,11 @@ static const struct usb_device_id option
+@@ -1197,6 +1207,11 @@ static const struct usb_device_id option
.driver_info = ZLP },
{ USB_DEVICE(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_BG96),
.driver_info = RSVD(4) },
--- /dev/null
+From 52d14545d2fc276b1bf9ccf48d4612fab6edfb6a Mon Sep 17 00:00:00 2001
+From: David Bauer <mail@david-bauer.net>
+Date: Thu, 6 May 2021 17:49:55 +0200
+Subject: [PATCH] mtd: spi-nor: Add support for BoHong bh25q128as
+
+Add MTD support for the BoHong bh25q128as SPI NOR chip.
+The chip has 16MB of total capacity, divided into a total of 256
+sectors, each 64KB sized. The chip also supports 4KB sectors.
+Additionally, it supports dual and quad read modes.
+
+Functionality was verified on an Tenbay WR1800K / MTK MT7621 board.
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+---
+ drivers/mtd/spi-nor/Makefile | 1 +
+ drivers/mtd/spi-nor/bohong.c | 21 +++++++++++++++++++++
+ drivers/mtd/spi-nor/core.c | 1 +
+ drivers/mtd/spi-nor/core.h | 1 +
+ 4 files changed, 24 insertions(+)
+ create mode 100644 drivers/mtd/spi-nor/bohong.c
+
+--- a/drivers/mtd/spi-nor/Makefile
++++ b/drivers/mtd/spi-nor/Makefile
+@@ -2,6 +2,7 @@
+
+ spi-nor-objs := core.o sfdp.o swp.o otp.o sysfs.o
+ spi-nor-objs += atmel.o
++spi-nor-objs += bohong.o
+ spi-nor-objs += catalyst.o
+ spi-nor-objs += eon.o
+ spi-nor-objs += esmt.o
+--- /dev/null
++++ b/drivers/mtd/spi-nor/bohong.c
+@@ -0,0 +1,21 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2005, Intec Automation Inc.
++ * Copyright (C) 2014, Freescale Semiconductor, Inc.
++ */
++
++#include <linux/mtd/spi-nor.h>
++
++#include "core.h"
++
++static const struct flash_info bohong_parts[] = {
++ /* BoHong Microelectronics */
++ { "bh25q128as", INFO(0x684018, 0, 64 * 1024, 256,
++ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
++};
++
++const struct spi_nor_manufacturer spi_nor_bohong = {
++ .name = "bohong",
++ .parts = bohong_parts,
++ .nparts = ARRAY_SIZE(bohong_parts),
++};
+--- a/drivers/mtd/spi-nor/core.c
++++ b/drivers/mtd/spi-nor/core.c
+@@ -1844,6 +1844,7 @@ int spi_nor_sr2_bit7_quad_enable(struct
+
+ static const struct spi_nor_manufacturer *manufacturers[] = {
+ &spi_nor_atmel,
++ &spi_nor_bohong,
+ &spi_nor_catalyst,
+ &spi_nor_eon,
+ &spi_nor_esmt,
+--- a/drivers/mtd/spi-nor/core.h
++++ b/drivers/mtd/spi-nor/core.h
+@@ -473,6 +473,7 @@ struct sfdp {
+
+ /* Manufacturer drivers. */
+ extern const struct spi_nor_manufacturer spi_nor_atmel;
++extern const struct spi_nor_manufacturer spi_nor_bohong;
+ extern const struct spi_nor_manufacturer spi_nor_catalyst;
+ extern const struct spi_nor_manufacturer spi_nor_eon;
+ extern const struct spi_nor_manufacturer spi_nor_esmt;
--- a/drivers/mtd/spi-nor/Makefile
+++ b/drivers/mtd/spi-nor/Makefile
-@@ -17,6 +17,7 @@ spi-nor-objs += sst.o
+@@ -18,6 +18,7 @@ spi-nor-objs += sst.o
spi-nor-objs += winbond.o
spi-nor-objs += xilinx.o
spi-nor-objs += xmc.o
+};
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
-@@ -1860,6 +1860,7 @@ static const struct spi_nor_manufacturer
+@@ -1861,6 +1861,7 @@ static const struct spi_nor_manufacturer
&spi_nor_winbond,
&spi_nor_xilinx,
&spi_nor_xmc,
static const struct flash_info *
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
-@@ -489,6 +489,7 @@ extern const struct spi_nor_manufacturer
+@@ -490,6 +490,7 @@ extern const struct spi_nor_manufacturer
extern const struct spi_nor_manufacturer spi_nor_winbond;
extern const struct spi_nor_manufacturer spi_nor_xilinx;
extern const struct spi_nor_manufacturer spi_nor_xmc;
return !!nor->params->erase_map.uniform_erase_type;
}
-@@ -2158,6 +2160,7 @@ static int spi_nor_select_erase(struct s
+@@ -2180,6 +2182,7 @@ static int spi_nor_select_erase(struct s
{
struct spi_nor_erase_map *map = &nor->params->erase_map;
const struct spi_nor_erase_type *erase = NULL;
struct mtd_info *mtd = &nor->mtd;
u32 wanted_size = nor->info->sector_size;
int i;
-@@ -2190,8 +2193,9 @@ static int spi_nor_select_erase(struct s
+@@ -2212,8 +2215,9 @@ static int spi_nor_select_erase(struct s
*/
for (i = SNOR_ERASE_TYPE_MAX - 1; i >= 0; i--) {
if (map->erase_type[i].size) {
}
}
-@@ -2199,6 +2203,9 @@ static int spi_nor_select_erase(struct s
+@@ -2221,6 +2225,9 @@ static int spi_nor_select_erase(struct s
return -EINVAL;
mtd->erasesize = erase->size;
+ &spi_nor_xtx,
};
- static const struct flash_info *spi_nor_match_id(struct spi_nor *nor,
+ static const struct flash_info spi_nor_generic_flash = {
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -633,6 +633,7 @@ extern const struct spi_nor_manufacturer
+++ /dev/null
-From: Felix Fietkau <nbd@nbd.name>
-Subject: net: replace GRO optimization patch with a new one that supports VLANs/bridges with different MAC addresses
-
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
- include/linux/netdevice.h | 2 ++
- include/linux/skbuff.h | 3 ++-
- net/core/dev.c | 48 +++++++++++++++++++++++++++++++++++++++++++++++
- net/ethernet/eth.c | 18 +++++++++++++++++-
- 4 files changed, 69 insertions(+), 2 deletions(-)
-
---- a/include/linux/netdevice.h
-+++ b/include/linux/netdevice.h
-@@ -2157,6 +2157,8 @@ struct net_device {
- struct netdev_hw_addr_list mc;
- struct netdev_hw_addr_list dev_addrs;
-
-+ unsigned char local_addr_mask[MAX_ADDR_LEN];
-+
- #ifdef CONFIG_SYSFS
- struct kset *queues_kset;
- #endif
---- a/include/linux/skbuff.h
-+++ b/include/linux/skbuff.h
-@@ -967,6 +967,7 @@ struct sk_buff {
- #ifdef CONFIG_IPV6_NDISC_NODETYPE
- __u8 ndisc_nodetype:2;
- #endif
-+ __u8 gro_skip:1;
-
- __u8 ipvs_property:1;
- __u8 inner_protocol_type:1;
---- a/net/core/gro.c
-+++ b/net/core/gro.c
-@@ -492,6 +492,9 @@ static enum gro_result dev_gro_receive(s
- int same_flow;
- int grow;
-
-+ if (skb->gro_skip)
-+ goto normal;
-+
- if (netif_elide_gro(skb->dev))
- goto normal;
-
---- a/net/core/dev.c
-+++ b/net/core/dev.c
-@@ -7628,6 +7628,48 @@ static void __netdev_adjacent_dev_unlink
- &upper_dev->adj_list.lower);
- }
-
-+static void __netdev_addr_mask(unsigned char *mask, const unsigned char *addr,
-+ struct net_device *dev)
-+{
-+ int i;
-+
-+ for (i = 0; i < dev->addr_len; i++)
-+ mask[i] |= addr[i] ^ dev->dev_addr[i];
-+}
-+
-+static void __netdev_upper_mask(unsigned char *mask, struct net_device *dev,
-+ struct net_device *lower)
-+{
-+ struct net_device *cur;
-+ struct list_head *iter;
-+
-+ netdev_for_each_upper_dev_rcu(dev, cur, iter) {
-+ __netdev_addr_mask(mask, cur->dev_addr, lower);
-+ __netdev_upper_mask(mask, cur, lower);
-+ }
-+}
-+
-+static void __netdev_update_addr_mask(struct net_device *dev)
-+{
-+ unsigned char mask[MAX_ADDR_LEN];
-+ struct net_device *cur;
-+ struct list_head *iter;
-+
-+ memset(mask, 0, sizeof(mask));
-+ __netdev_upper_mask(mask, dev, dev);
-+ memcpy(dev->local_addr_mask, mask, dev->addr_len);
-+
-+ netdev_for_each_lower_dev(dev, cur, iter)
-+ __netdev_update_addr_mask(cur);
-+}
-+
-+static void netdev_update_addr_mask(struct net_device *dev)
-+{
-+ rcu_read_lock();
-+ __netdev_update_addr_mask(dev);
-+ rcu_read_unlock();
-+}
-+
- static int __netdev_upper_dev_link(struct net_device *dev,
- struct net_device *upper_dev, bool master,
- void *upper_priv, void *upper_info,
-@@ -7679,6 +7721,7 @@ static int __netdev_upper_dev_link(struc
- if (ret)
- return ret;
-
-+ netdev_update_addr_mask(dev);
- ret = call_netdevice_notifiers_info(NETDEV_CHANGEUPPER,
- &changeupper_info.info);
- ret = notifier_to_errno(ret);
-@@ -7775,6 +7818,7 @@ static void __netdev_upper_dev_unlink(st
-
- __netdev_adjacent_dev_unlink_neighbour(dev, upper_dev);
-
-+ netdev_update_addr_mask(dev);
- call_netdevice_notifiers_info(NETDEV_CHANGEUPPER,
- &changeupper_info.info);
-
-@@ -8827,6 +8871,7 @@ int dev_set_mac_address(struct net_devic
- if (err)
- return err;
- dev->addr_assign_type = NET_ADDR_SET;
-+ netdev_update_addr_mask(dev);
- call_netdevice_notifiers(NETDEV_CHANGEADDR, dev);
- add_device_randomness(dev->dev_addr, dev->addr_len);
- return 0;
---- a/net/ethernet/eth.c
-+++ b/net/ethernet/eth.c
-@@ -143,6 +143,18 @@ u32 eth_get_headlen(const struct net_dev
- }
- EXPORT_SYMBOL(eth_get_headlen);
-
-+static inline bool
-+eth_check_local_mask(const void *addr1, const void *addr2, const void *mask)
-+{
-+ const u16 *a1 = addr1;
-+ const u16 *a2 = addr2;
-+ const u16 *m = mask;
-+
-+ return (((a1[0] ^ a2[0]) & ~m[0]) |
-+ ((a1[1] ^ a2[1]) & ~m[1]) |
-+ ((a1[2] ^ a2[2]) & ~m[2]));
-+}
-+
- /**
- * eth_type_trans - determine the packet's protocol ID.
- * @skb: received socket data
-@@ -174,6 +186,10 @@ __be16 eth_type_trans(struct sk_buff *sk
- } else {
- skb->pkt_type = PACKET_OTHERHOST;
- }
-+
-+ if (eth_check_local_mask(eth->h_dest, dev->dev_addr,
-+ dev->local_addr_mask))
-+ skb->gro_skip = 1;
- }
-
- /*
--- /dev/null
+From: Felix Fietkau <nbd@nbd.name>
+Date: Tue, 23 Apr 2024 11:23:03 +0200
+Subject: [PATCH] net: add TCP fraglist GRO support
+
+When forwarding TCP after GRO, software segmentation is very expensive,
+especially when the checksum needs to be recalculated.
+One case where that's currently unavoidable is when routing packets over
+PPPoE. Performance improves significantly when using fraglist GRO
+implemented in the same way as for UDP.
+
+Here's a measurement of running 2 TCP streams through a MediaTek MT7622
+device (2-core Cortex-A53), which runs NAT with flow offload enabled from
+one ethernet port to PPPoE on another ethernet port + cake qdisc set to
+1Gbps.
+
+rx-gro-list off: 630 Mbit/s, CPU 35% idle
+rx-gro-list on: 770 Mbit/s, CPU 40% idle
+
+Signe-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/include/net/gro.h
++++ b/include/net/gro.h
+@@ -424,6 +424,7 @@ static inline __wsum ip6_gro_compute_pse
+ }
+
+ int skb_gro_receive(struct sk_buff *p, struct sk_buff *skb);
++int skb_gro_receive_list(struct sk_buff *p, struct sk_buff *skb);
+
+ /* Pass the currently batched GRO_NORMAL SKBs up to the stack. */
+ static inline void gro_normal_list(struct napi_struct *napi)
+@@ -446,5 +447,48 @@ static inline void gro_normal_one(struct
+ gro_normal_list(napi);
+ }
+
++/* This function is the alternative of 'inet_iif' and 'inet_sdif'
++ * functions in case we can not rely on fields of IPCB.
++ *
++ * The caller must verify skb_valid_dst(skb) is false and skb->dev is initialized.
++ * The caller must hold the RCU read lock.
++ */
++static inline void inet_get_iif_sdif(const struct sk_buff *skb, int *iif, int *sdif)
++{
++ *iif = inet_iif(skb) ?: skb->dev->ifindex;
++ *sdif = 0;
++
++#if IS_ENABLED(CONFIG_NET_L3_MASTER_DEV)
++ if (netif_is_l3_slave(skb->dev)) {
++ struct net_device *master = netdev_master_upper_dev_get_rcu(skb->dev);
++
++ *sdif = *iif;
++ *iif = master ? master->ifindex : 0;
++ }
++#endif
++}
++
++/* This function is the alternative of 'inet6_iif' and 'inet6_sdif'
++ * functions in case we can not rely on fields of IP6CB.
++ *
++ * The caller must verify skb_valid_dst(skb) is false and skb->dev is initialized.
++ * The caller must hold the RCU read lock.
++ */
++static inline void inet6_get_iif_sdif(const struct sk_buff *skb, int *iif, int *sdif)
++{
++ /* using skb->dev->ifindex because skb_dst(skb) is not initialized */
++ *iif = skb->dev->ifindex;
++ *sdif = 0;
++
++#if IS_ENABLED(CONFIG_NET_L3_MASTER_DEV)
++ if (netif_is_l3_slave(skb->dev)) {
++ struct net_device *master = netdev_master_upper_dev_get_rcu(skb->dev);
++
++ *sdif = *iif;
++ *iif = master ? master->ifindex : 0;
++ }
++#endif
++}
++
+
+ #endif /* _NET_IPV6_GRO_H */
+--- a/include/net/tcp.h
++++ b/include/net/tcp.h
+@@ -2057,7 +2057,10 @@ void tcp_v4_destroy_sock(struct sock *sk
+
+ struct sk_buff *tcp_gso_segment(struct sk_buff *skb,
+ netdev_features_t features);
+-struct sk_buff *tcp_gro_receive(struct list_head *head, struct sk_buff *skb);
++struct tcphdr *tcp_gro_pull_header(struct sk_buff *skb);
++struct sk_buff *tcp_gro_lookup(struct list_head *head, struct tcphdr *th);
++struct sk_buff *tcp_gro_receive(struct list_head *head, struct sk_buff *skb,
++ struct tcphdr *th);
+ INDIRECT_CALLABLE_DECLARE(int tcp4_gro_complete(struct sk_buff *skb, int thoff));
+ INDIRECT_CALLABLE_DECLARE(struct sk_buff *tcp4_gro_receive(struct list_head *head, struct sk_buff *skb));
+ INDIRECT_CALLABLE_DECLARE(int tcp6_gro_complete(struct sk_buff *skb, int thoff));
+--- a/net/core/gro.c
++++ b/net/core/gro.c
+@@ -290,6 +290,33 @@ done:
+ return 0;
+ }
+
++int skb_gro_receive_list(struct sk_buff *p, struct sk_buff *skb)
++{
++ if (unlikely(p->len + skb->len >= 65536))
++ return -E2BIG;
++
++ if (NAPI_GRO_CB(p)->last == p)
++ skb_shinfo(p)->frag_list = skb;
++ else
++ NAPI_GRO_CB(p)->last->next = skb;
++
++ skb_pull(skb, skb_gro_offset(skb));
++
++ NAPI_GRO_CB(p)->last = skb;
++ NAPI_GRO_CB(p)->count++;
++ p->data_len += skb->len;
++
++ /* sk ownership - if any - completely transferred to the aggregated packet */
++ skb->destructor = NULL;
++ skb->sk = NULL;
++ p->truesize += skb->truesize;
++ p->len += skb->len;
++
++ NAPI_GRO_CB(skb)->same_flow = 1;
++
++ return 0;
++}
++
+
+ static void napi_gro_complete(struct napi_struct *napi, struct sk_buff *skb)
+ {
+--- a/net/ipv4/tcp_offload.c
++++ b/net/ipv4/tcp_offload.c
+@@ -27,6 +27,70 @@ static void tcp_gso_tstamp(struct sk_buf
+ }
+ }
+
++static void __tcpv4_gso_segment_csum(struct sk_buff *seg,
++ __be32 *oldip, __be32 newip,
++ __be16 *oldport, __be16 newport)
++{
++ struct tcphdr *th;
++ struct iphdr *iph;
++
++ if (*oldip == newip && *oldport == newport)
++ return;
++
++ th = tcp_hdr(seg);
++ iph = ip_hdr(seg);
++
++ inet_proto_csum_replace4(&th->check, seg, *oldip, newip, true);
++ inet_proto_csum_replace2(&th->check, seg, *oldport, newport, false);
++ *oldport = newport;
++
++ csum_replace4(&iph->check, *oldip, newip);
++ *oldip = newip;
++}
++
++static struct sk_buff *__tcpv4_gso_segment_list_csum(struct sk_buff *segs)
++{
++ const struct tcphdr *th;
++ const struct iphdr *iph;
++ struct sk_buff *seg;
++ struct tcphdr *th2;
++ struct iphdr *iph2;
++
++ seg = segs;
++ th = tcp_hdr(seg);
++ iph = ip_hdr(seg);
++ th2 = tcp_hdr(seg->next);
++ iph2 = ip_hdr(seg->next);
++
++ if (!(*(const u32 *)&th->source ^ *(const u32 *)&th2->source) &&
++ iph->daddr == iph2->daddr && iph->saddr == iph2->saddr)
++ return segs;
++
++ while ((seg = seg->next)) {
++ th2 = tcp_hdr(seg);
++ iph2 = ip_hdr(seg);
++
++ __tcpv4_gso_segment_csum(seg,
++ &iph2->saddr, iph->saddr,
++ &th2->source, th->source);
++ __tcpv4_gso_segment_csum(seg,
++ &iph2->daddr, iph->daddr,
++ &th2->dest, th->dest);
++ }
++
++ return segs;
++}
++
++static struct sk_buff *__tcp4_gso_segment_list(struct sk_buff *skb,
++ netdev_features_t features)
++{
++ skb = skb_segment_list(skb, features, skb_mac_header_len(skb));
++ if (IS_ERR(skb))
++ return skb;
++
++ return __tcpv4_gso_segment_list_csum(skb);
++}
++
+ static struct sk_buff *tcp4_gso_segment(struct sk_buff *skb,
+ netdev_features_t features)
+ {
+@@ -36,6 +100,9 @@ static struct sk_buff *tcp4_gso_segment(
+ if (!pskb_may_pull(skb, sizeof(struct tcphdr)))
+ return ERR_PTR(-EINVAL);
+
++ if (skb_shinfo(skb)->gso_type & SKB_GSO_FRAGLIST)
++ return __tcp4_gso_segment_list(skb, features);
++
+ if (unlikely(skb->ip_summed != CHECKSUM_PARTIAL)) {
+ const struct iphdr *iph = ip_hdr(skb);
+ struct tcphdr *th = tcp_hdr(skb);
+@@ -177,61 +244,76 @@ out:
+ return segs;
+ }
+
+-struct sk_buff *tcp_gro_receive(struct list_head *head, struct sk_buff *skb)
++struct sk_buff *tcp_gro_lookup(struct list_head *head, struct tcphdr *th)
+ {
+- struct sk_buff *pp = NULL;
++ struct tcphdr *th2;
+ struct sk_buff *p;
++
++ list_for_each_entry(p, head, list) {
++ if (!NAPI_GRO_CB(p)->same_flow)
++ continue;
++
++ th2 = tcp_hdr(p);
++ if (*(u32 *)&th->source ^ *(u32 *)&th2->source) {
++ NAPI_GRO_CB(p)->same_flow = 0;
++ continue;
++ }
++
++ return p;
++ }
++
++ return NULL;
++}
++
++struct tcphdr *tcp_gro_pull_header(struct sk_buff *skb)
++{
++ unsigned int thlen, hlen, off;
+ struct tcphdr *th;
+- struct tcphdr *th2;
+- unsigned int len;
+- unsigned int thlen;
+- __be32 flags;
+- unsigned int mss = 1;
+- unsigned int hlen;
+- unsigned int off;
+- int flush = 1;
+- int i;
+
+ off = skb_gro_offset(skb);
+ hlen = off + sizeof(*th);
+ th = skb_gro_header(skb, hlen, off);
+ if (unlikely(!th))
+- goto out;
++ return NULL;
+
+ thlen = th->doff * 4;
+ if (thlen < sizeof(*th))
+- goto out;
++ return NULL;
+
+ hlen = off + thlen;
+ if (skb_gro_header_hard(skb, hlen)) {
+ th = skb_gro_header_slow(skb, hlen, off);
+ if (unlikely(!th))
+- goto out;
++ return NULL;
+ }
+
+ skb_gro_pull(skb, thlen);
+
+- len = skb_gro_len(skb);
+- flags = tcp_flag_word(th);
+-
+- list_for_each_entry(p, head, list) {
+- if (!NAPI_GRO_CB(p)->same_flow)
+- continue;
++ return th;
++}
+
+- th2 = tcp_hdr(p);
++struct sk_buff *tcp_gro_receive(struct list_head *head, struct sk_buff *skb,
++ struct tcphdr *th)
++{
++ unsigned int thlen = th->doff * 4;
++ struct sk_buff *pp = NULL;
++ struct sk_buff *p;
++ struct tcphdr *th2;
++ unsigned int len;
++ __be32 flags;
++ unsigned int mss = 1;
++ int flush = 1;
++ int i;
+
+- if (*(u32 *)&th->source ^ *(u32 *)&th2->source) {
+- NAPI_GRO_CB(p)->same_flow = 0;
+- continue;
+- }
++ len = skb_gro_len(skb);
++ flags = tcp_flag_word(th);
+
+- goto found;
+- }
+- p = NULL;
+- goto out_check_final;
++ p = tcp_gro_lookup(head, th);
++ if (!p)
++ goto out_check_final;
+
+-found:
+ /* Include the IP ID check below from the inner most IP hdr */
++ th2 = tcp_hdr(p);
+ flush = NAPI_GRO_CB(p)->flush;
+ flush |= (__force int)(flags & TCP_FLAG_CWR);
+ flush |= (__force int)((flags ^ tcp_flag_word(th2)) &
+@@ -268,6 +350,18 @@ found:
+ flush |= p->decrypted ^ skb->decrypted;
+ #endif
+
++ if (unlikely(NAPI_GRO_CB(p)->is_flist)) {
++ flush |= (__force int)(flags ^ tcp_flag_word(th2));
++ flush |= skb->ip_summed != p->ip_summed;
++ flush |= skb->csum_level != p->csum_level;
++ flush |= NAPI_GRO_CB(p)->count >= 64;
++
++ if (flush || skb_gro_receive_list(p, skb))
++ mss = 1;
++
++ goto out_check_final;
++ }
++
+ if (flush || skb_gro_receive(p, skb)) {
+ mss = 1;
+ goto out_check_final;
+@@ -289,7 +383,6 @@ out_check_final:
+ if (p && (!NAPI_GRO_CB(skb)->same_flow || flush))
+ pp = p;
+
+-out:
+ NAPI_GRO_CB(skb)->flush |= (flush != 0);
+
+ return pp;
+@@ -315,18 +408,58 @@ int tcp_gro_complete(struct sk_buff *skb
+ }
+ EXPORT_SYMBOL(tcp_gro_complete);
+
++static void tcp4_check_fraglist_gro(struct list_head *head, struct sk_buff *skb,
++ struct tcphdr *th)
++{
++ const struct iphdr *iph;
++ struct sk_buff *p;
++ struct sock *sk;
++ struct net *net;
++ int iif, sdif;
++
++ if (!(skb->dev->features & NETIF_F_GRO_FRAGLIST))
++ return;
++
++ p = tcp_gro_lookup(head, th);
++ if (p) {
++ NAPI_GRO_CB(skb)->is_flist = NAPI_GRO_CB(p)->is_flist;
++ return;
++ }
++
++ inet_get_iif_sdif(skb, &iif, &sdif);
++ iph = skb_gro_network_header(skb);
++ net = dev_net(skb->dev);
++ sk = __inet_lookup_established(net, net->ipv4.tcp_death_row.hashinfo,
++ iph->saddr, th->source,
++ iph->daddr, ntohs(th->dest),
++ iif, sdif);
++ NAPI_GRO_CB(skb)->is_flist = !sk;
++ if (sk)
++ sock_put(sk);
++}
++
+ INDIRECT_CALLABLE_SCOPE
+ struct sk_buff *tcp4_gro_receive(struct list_head *head, struct sk_buff *skb)
+ {
++ struct tcphdr *th;
++
+ /* Don't bother verifying checksum if we're going to flush anyway. */
+ if (!NAPI_GRO_CB(skb)->flush &&
+ skb_gro_checksum_validate(skb, IPPROTO_TCP,
+- inet_gro_compute_pseudo)) {
+- NAPI_GRO_CB(skb)->flush = 1;
+- return NULL;
+- }
++ inet_gro_compute_pseudo))
++ goto flush;
++
++ th = tcp_gro_pull_header(skb);
++ if (!th)
++ goto flush;
+
+- return tcp_gro_receive(head, skb);
++ tcp4_check_fraglist_gro(head, skb, th);
++
++ return tcp_gro_receive(head, skb, th);
++
++flush:
++ NAPI_GRO_CB(skb)->flush = 1;
++ return NULL;
+ }
+
+ INDIRECT_CALLABLE_SCOPE int tcp4_gro_complete(struct sk_buff *skb, int thoff)
+@@ -334,6 +467,15 @@ INDIRECT_CALLABLE_SCOPE int tcp4_gro_com
+ const struct iphdr *iph = ip_hdr(skb);
+ struct tcphdr *th = tcp_hdr(skb);
+
++ if (unlikely(NAPI_GRO_CB(skb)->is_flist)) {
++ skb_shinfo(skb)->gso_type |= SKB_GSO_FRAGLIST | SKB_GSO_TCPV4;
++ skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count;
++
++ __skb_incr_checksum_unnecessary(skb);
++
++ return 0;
++ }
++
+ th->check = ~tcp_v4_check(skb->len - thoff, iph->saddr,
+ iph->daddr, 0);
+ skb_shinfo(skb)->gso_type |= SKB_GSO_TCPV4;
+--- a/net/ipv4/udp_offload.c
++++ b/net/ipv4/udp_offload.c
+@@ -425,33 +425,6 @@ out:
+ return segs;
+ }
+
+-static int skb_gro_receive_list(struct sk_buff *p, struct sk_buff *skb)
+-{
+- if (unlikely(p->len + skb->len >= 65536))
+- return -E2BIG;
+-
+- if (NAPI_GRO_CB(p)->last == p)
+- skb_shinfo(p)->frag_list = skb;
+- else
+- NAPI_GRO_CB(p)->last->next = skb;
+-
+- skb_pull(skb, skb_gro_offset(skb));
+-
+- NAPI_GRO_CB(p)->last = skb;
+- NAPI_GRO_CB(p)->count++;
+- p->data_len += skb->len;
+-
+- /* sk ownership - if any - completely transferred to the aggregated packet */
+- skb->destructor = NULL;
+- skb->sk = NULL;
+- p->truesize += skb->truesize;
+- p->len += skb->len;
+-
+- NAPI_GRO_CB(skb)->same_flow = 1;
+-
+- return 0;
+-}
+-
+
+ #define UDP_GRO_CNT_MAX 64
+ static struct sk_buff *udp_gro_receive_segment(struct list_head *head,
+--- a/net/ipv6/tcpv6_offload.c
++++ b/net/ipv6/tcpv6_offload.c
+@@ -7,24 +7,67 @@
+ */
+ #include <linux/indirect_call_wrapper.h>
+ #include <linux/skbuff.h>
++#include <net/inet6_hashtables.h>
+ #include <net/gro.h>
+ #include <net/protocol.h>
+ #include <net/tcp.h>
+ #include <net/ip6_checksum.h>
+ #include "ip6_offload.h"
+
++static void tcp6_check_fraglist_gro(struct list_head *head, struct sk_buff *skb,
++ struct tcphdr *th)
++{
++#if IS_ENABLED(CONFIG_IPV6)
++ const struct ipv6hdr *hdr;
++ struct sk_buff *p;
++ struct sock *sk;
++ struct net *net;
++ int iif, sdif;
++
++ if (!(skb->dev->features & NETIF_F_GRO_FRAGLIST))
++ return;
++
++ p = tcp_gro_lookup(head, th);
++ if (p) {
++ NAPI_GRO_CB(skb)->is_flist = NAPI_GRO_CB(p)->is_flist;
++ return;
++ }
++
++ inet6_get_iif_sdif(skb, &iif, &sdif);
++ hdr = skb_gro_network_header(skb);
++ net = dev_net(skb->dev);
++ sk = __inet6_lookup_established(net, net->ipv4.tcp_death_row.hashinfo,
++ &hdr->saddr, th->source,
++ &hdr->daddr, ntohs(th->dest),
++ iif, sdif);
++ NAPI_GRO_CB(skb)->is_flist = !sk;
++ if (sk)
++ sock_put(sk);
++#endif /* IS_ENABLED(CONFIG_IPV6) */
++}
++
+ INDIRECT_CALLABLE_SCOPE
+ struct sk_buff *tcp6_gro_receive(struct list_head *head, struct sk_buff *skb)
+ {
++ struct tcphdr *th;
++
+ /* Don't bother verifying checksum if we're going to flush anyway. */
+ if (!NAPI_GRO_CB(skb)->flush &&
+ skb_gro_checksum_validate(skb, IPPROTO_TCP,
+- ip6_gro_compute_pseudo)) {
+- NAPI_GRO_CB(skb)->flush = 1;
+- return NULL;
+- }
++ ip6_gro_compute_pseudo))
++ goto flush;
+
+- return tcp_gro_receive(head, skb);
++ th = tcp_gro_pull_header(skb);
++ if (!th)
++ goto flush;
++
++ tcp6_check_fraglist_gro(head, skb, th);
++
++ return tcp_gro_receive(head, skb, th);
++
++flush:
++ NAPI_GRO_CB(skb)->flush = 1;
++ return NULL;
+ }
+
+ INDIRECT_CALLABLE_SCOPE int tcp6_gro_complete(struct sk_buff *skb, int thoff)
+@@ -32,6 +75,15 @@ INDIRECT_CALLABLE_SCOPE int tcp6_gro_com
+ const struct ipv6hdr *iph = ipv6_hdr(skb);
+ struct tcphdr *th = tcp_hdr(skb);
+
++ if (unlikely(NAPI_GRO_CB(skb)->is_flist)) {
++ skb_shinfo(skb)->gso_type |= SKB_GSO_FRAGLIST | SKB_GSO_TCPV6;
++ skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count;
++
++ __skb_incr_checksum_unnecessary(skb);
++
++ return 0;
++ }
++
+ th->check = ~tcp_v6_check(skb->len - thoff, &iph->saddr,
+ &iph->daddr, 0);
+ skb_shinfo(skb)->gso_type |= SKB_GSO_TCPV6;
+@@ -39,6 +91,61 @@ INDIRECT_CALLABLE_SCOPE int tcp6_gro_com
+ return tcp_gro_complete(skb);
+ }
+
++static void __tcpv6_gso_segment_csum(struct sk_buff *seg,
++ __be16 *oldport, __be16 newport)
++{
++ struct tcphdr *th;
++
++ if (*oldport == newport)
++ return;
++
++ th = tcp_hdr(seg);
++ inet_proto_csum_replace2(&th->check, seg, *oldport, newport, false);
++ *oldport = newport;
++}
++
++static struct sk_buff *__tcpv6_gso_segment_list_csum(struct sk_buff *segs)
++{
++ const struct tcphdr *th;
++ const struct ipv6hdr *iph;
++ struct sk_buff *seg;
++ struct tcphdr *th2;
++ struct ipv6hdr *iph2;
++
++ seg = segs;
++ th = tcp_hdr(seg);
++ iph = ipv6_hdr(seg);
++ th2 = tcp_hdr(seg->next);
++ iph2 = ipv6_hdr(seg->next);
++
++ if (!(*(const u32 *)&th->source ^ *(const u32 *)&th2->source) &&
++ ipv6_addr_equal(&iph->saddr, &iph2->saddr) &&
++ ipv6_addr_equal(&iph->daddr, &iph2->daddr))
++ return segs;
++
++ while ((seg = seg->next)) {
++ th2 = tcp_hdr(seg);
++ iph2 = ipv6_hdr(seg);
++
++ iph2->saddr = iph->saddr;
++ iph2->daddr = iph->daddr;
++ __tcpv6_gso_segment_csum(seg, &th2->source, th->source);
++ __tcpv6_gso_segment_csum(seg, &th2->dest, th->dest);
++ }
++
++ return segs;
++}
++
++static struct sk_buff *__tcp6_gso_segment_list(struct sk_buff *skb,
++ netdev_features_t features)
++{
++ skb = skb_segment_list(skb, features, skb_mac_header_len(skb));
++ if (IS_ERR(skb))
++ return skb;
++
++ return __tcpv6_gso_segment_list_csum(skb);
++}
++
+ static struct sk_buff *tcp6_gso_segment(struct sk_buff *skb,
+ netdev_features_t features)
+ {
+@@ -50,6 +157,9 @@ static struct sk_buff *tcp6_gso_segment(
+ if (!pskb_may_pull(skb, sizeof(*th)))
+ return ERR_PTR(-EINVAL);
+
++ if (skb_shinfo(skb)->gso_type & SKB_GSO_FRAGLIST)
++ return __tcp6_gso_segment_list(skb, features);
++
+ if (unlikely(skb->ip_summed != CHECKSUM_PARTIAL)) {
+ const struct ipv6hdr *ipv6h = ipv6_hdr(skb);
+ struct tcphdr *th = tcp_hdr(skb);
--- /dev/null
+From: Felix Fietkau <nbd@nbd.name>
+Date: Sat, 27 Apr 2024 18:54:25 +0200
+Subject: [PATCH] net: bridge: fix multicast-to-unicast with fraglist GSO
+
+Calling skb_copy on a SKB_GSO_FRAGLIST skb is not valid, since it returns
+an invalid linearized skb. This code only needs to change the ethernet
+header, so pskb_copy is the right function to call here.
+
+Fixes: 6db6f0eae605 ("bridge: multicast to unicast")
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/net/bridge/br_forward.c
++++ b/net/bridge/br_forward.c
+@@ -261,7 +261,7 @@ static void maybe_deliver_addr(struct ne
+ if (skb->dev == p->dev && ether_addr_equal(src, addr))
+ return;
+
+- skb = skb_copy(skb, GFP_ATOMIC);
++ skb = pskb_copy(skb, GFP_ATOMIC);
+ if (!skb) {
+ DEV_STATS_INC(dev, tx_dropped);
+ return;
--- /dev/null
+From: Felix Fietkau <nbd@nbd.name>
+Date: Sat, 27 Apr 2024 19:29:45 +0200
+Subject: [PATCH] net: core: reject skb_copy(_expand) for fraglist GSO skbs
+
+SKB_GSO_FRAGLIST skbs must not be linearized, otherwise they become
+invalid. Return NULL if such an skb is passed to skb_copy or
+skb_copy_expand, in order to prevent a crash on a potential later
+call to skb_gso_segment.
+
+Fixes: 3a1296a38d0c ("net: Support GRO/GSO fraglist chaining.")
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/net/core/skbuff.c
++++ b/net/core/skbuff.c
+@@ -1720,11 +1720,17 @@ static inline int skb_alloc_rx_flag(cons
+
+ struct sk_buff *skb_copy(const struct sk_buff *skb, gfp_t gfp_mask)
+ {
+- int headerlen = skb_headroom(skb);
+- unsigned int size = skb_end_offset(skb) + skb->data_len;
+- struct sk_buff *n = __alloc_skb(size, gfp_mask,
+- skb_alloc_rx_flag(skb), NUMA_NO_NODE);
++ struct sk_buff *n;
++ unsigned int size;
++ int headerlen;
+
++ if (WARN_ON_ONCE(skb_shinfo(skb)->gso_type & SKB_GSO_FRAGLIST))
++ return NULL;
++
++ headerlen = skb_headroom(skb);
++ size = skb_end_offset(skb) + skb->data_len;
++ n = __alloc_skb(size, gfp_mask,
++ skb_alloc_rx_flag(skb), NUMA_NO_NODE);
+ if (!n)
+ return NULL;
+
+@@ -2037,12 +2043,17 @@ struct sk_buff *skb_copy_expand(const st
+ /*
+ * Allocate the copy buffer
+ */
+- struct sk_buff *n = __alloc_skb(newheadroom + skb->len + newtailroom,
+- gfp_mask, skb_alloc_rx_flag(skb),
+- NUMA_NO_NODE);
+- int oldheadroom = skb_headroom(skb);
+ int head_copy_len, head_copy_off;
++ struct sk_buff *n;
++ int oldheadroom;
++
++ if (WARN_ON_ONCE(skb_shinfo(skb)->gso_type & SKB_GSO_FRAGLIST))
++ return NULL;
+
++ oldheadroom = skb_headroom(skb);
++ n = __alloc_skb(newheadroom + skb->len + newtailroom,
++ gfp_mask, skb_alloc_rx_flag(skb),
++ NUMA_NO_NODE);
+ if (!n)
+ return NULL;
+
--- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h
-@@ -2192,7 +2192,7 @@ struct net_device {
+@@ -2190,7 +2190,7 @@ struct net_device {
#if IS_ENABLED(CONFIG_AX25)
void *ax25_ptr;
#endif
/**
* napi_disable - prevent NAPI from scheduling
-@@ -3152,6 +3153,7 @@ struct softnet_data {
+@@ -3150,6 +3151,7 @@ struct softnet_data {
unsigned int processed;
unsigned int time_squeeze;
unsigned int received_rps;
void netif_napi_add_weight(struct net_device *dev, struct napi_struct *napi,
int (*poll)(struct napi_struct *, int), int weight)
{
-@@ -11171,6 +11242,9 @@ static int dev_cpu_dead(unsigned int old
+@@ -11126,6 +11197,9 @@ static int dev_cpu_dead(unsigned int old
raise_softirq_irqoff(NET_TX_SOFTIRQ);
local_irq_enable();
#ifdef CONFIG_RPS
remsd = oldsd->rps_ipi_list;
oldsd->rps_ipi_list = NULL;
-@@ -11483,6 +11557,7 @@ static int __init net_dev_init(void)
+@@ -11438,6 +11512,7 @@ static int __init net_dev_init(void)
INIT_CSD(&sd->defer_csd, trigger_rx_softirq, sd);
spin_lock_init(&sd->defer_lock);
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
-@@ -7025,6 +7025,7 @@ static int mv88e6xxx_register_switch(str
+@@ -7037,6 +7037,7 @@ static int mv88e6xxx_register_switch(str
ds->ops = &mv88e6xxx_switch_ops;
ds->ageing_time_min = chip->info->age_time_coeff;
ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
--- /dev/null
+From patchwork Sat Apr 27 11:24:42 2024
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 8bit
+X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTCB2aWEgQjQgUmVsYXk=?=
+ <devnull+arinc.unal.arinc9.com@kernel.org>
+X-Patchwork-Id: 13645655
+From: =?utf-8?b?QXLEsW7DpyDDnE5BTCB2aWEgQjQgUmVsYXk=?=
+ <devnull+arinc.unal.arinc9.com@kernel.org>
+Date: Sat, 27 Apr 2024 14:24:42 +0300
+Subject: [PATCH net-next] net: dsa: mt7530: do not set MT7530_P5_DIS when
+ PHY muxing is being used
+Precedence: bulk
+X-Mailing-List: netdev@vger.kernel.org
+List-Id: <netdev.vger.kernel.org>
+List-Subscribe: <mailto:netdev+subscribe@vger.kernel.org>
+List-Unsubscribe: <mailto:netdev+unsubscribe@vger.kernel.org>
+MIME-Version: 1.0
+Message-Id:
+ <20240427-for-netnext-mt7530-do-not-disable-port5-when-phy-muxing-v1-1-793cdf9d7707@arinc9.com>
+To: Daniel Golle <daniel@makrotopia.org>, DENG Qingfang <dqfext@gmail.com>,
+ Sean Wang <sean.wang@mediatek.com>, Andrew Lunn <andrew@lunn.ch>,
+ Florian Fainelli <f.fainelli@gmail.com>,
+ Vladimir Oltean <olteanv@gmail.com>,
+ "David S. Miller" <davem@davemloft.net>, Eric Dumazet <edumazet@google.com>,
+ Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
+ Matthias Brugger <matthias.bgg@gmail.com>,
+ AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
+ linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org,
+ =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= <arinc.unal@arinc9.com>
+X-Mailer: b4 0.13.0
+X-Patchwork-Delegate: kuba@kernel.org
+
+From: Arınç ÜNAL <arinc.unal@arinc9.com>
+
+When the PHY muxing feature is in use, port 5 won't be defined in the
+device tree. Because of this, the type member of the dsa_port structure for
+this port will be assigned DSA_PORT_TYPE_UNUSED. The dsa_port_setup()
+function calls ds->ops->port_disable() when the port type is
+DSA_PORT_TYPE_UNUSED.
+
+The MT7530_P5_DIS bit is unset when PHY muxing is being used.
+mt7530_port_disable() which is assigned to ds->ops->port_disable() is
+called afterwards. Currently, mt7530_port_disable() sets MT7530_P5_DIS
+which breaks network connectivity when PHY muxing is being used.
+
+Therefore, do not set MT7530_P5_DIS when PHY muxing is being used.
+
+Fixes: 377174c5760c ("net: dsa: mt7530: move MT753X_MTRAP operations for MT7530")
+Reported-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+Hello.
+
+I've sent this to net-next as the patch it fixes is on the current
+development cycle.
+---
+ drivers/net/dsa/mt7530.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+
+---
+base-commit: 5c4c0edca68a5841a8d53ccd49596fe199c8334c
+change-id: 20240427-for-netnext-mt7530-do-not-disable-port5-when-phy-muxing-7ff5fd0995d7
+
+Best regards,
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -1213,7 +1213,7 @@ mt7530_port_disable(struct dsa_switch *d
+ if (priv->id != ID_MT7530 && priv->id != ID_MT7621)
+ return;
+
+- if (port == 5)
++ if (port == 5 && priv->p5_mode == GMAC5)
+ mt7530_set(priv, MT753X_MTRAP, MT7530_P5_DIS);
+ else if (port == 6)
+ mt7530_set(priv, MT753X_MTRAP, MT7530_P6_DIS);
+++ /dev/null
-From ef972fc9f5743da589ce9546dd565d6c56e679b8 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
-Date: Mon, 8 Apr 2024 10:08:53 +0300
-Subject: [PATCH 1/2] net: dsa: mt7530: fix enabling EEE on MT7531 switch on
- all boards
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The commit 40b5d2f15c09 ("net: dsa: mt7530: Add support for EEE features")
-brought EEE support but did not enable EEE on MT7531 switch MACs. EEE is
-enabled on MT7531 switch MACs by pulling the LAN2LED0 pin low on the board
-(bootstrapping), unsetting the EEE_DIS bit on the trap register, or setting
-the internal EEE switch bit on the CORE_PLL_GROUP4 register. Thanks to
-SkyLake Huang (黃啟澤) from MediaTek for providing information on the
-internal EEE switch bit.
-
-There are existing boards that were not designed to pull the pin low.
-Because of that, the EEE status currently depends on the board design.
-
-The EEE_DIS bit on the trap pertains to the LAN2LED0 pin which is usually
-used to control an LED. Once the bit is unset, the pin will be low. That
-will make the active low LED turn on. The pin is controlled by the switch
-PHY. It seems that the PHY controls the pin in the way that it inverts the
-pin state. That means depending on the wiring of the LED connected to
-LAN2LED0 on the board, the LED may be on without an active link.
-
-To not cause this unwanted behaviour whilst enabling EEE on all boards, set
-the internal EEE switch bit on the CORE_PLL_GROUP4 register.
-
-My testing on MT7531 shows a certain amount of traffic loss when EEE is
-enabled. That said, I haven't come across a board that enables EEE. So
-enable EEE on the switch MACs but disable EEE advertisement on the switch
-PHYs. This way, we don't change the behaviour of the majority of the boards
-that have this switch. The mediatek-ge PHY driver already disables EEE
-advertisement on the switch PHYs but my testing shows that it is somehow
-enabled afterwards. Disabling EEE advertisement before the PHY driver
-initialises keeps it off.
-
-With this change, EEE can now be enabled using ethtool.
-
-Fixes: 40b5d2f15c09 ("net: dsa: mt7530: Add support for EEE features")
-Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
-Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
----
- drivers/net/dsa/mt7530.c | 17 ++++++++++++-----
- drivers/net/dsa/mt7530.h | 1 +
- 2 files changed, 13 insertions(+), 5 deletions(-)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -2496,18 +2496,25 @@ mt7531_setup(struct dsa_switch *ds)
- mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
- MT7531_GPIO0_INTERRUPT);
-
-- /* Enable PHY core PLL, since phy_device has not yet been created
-- * provided for phy_[read,write]_mmd_indirect is called, we provide
-- * our own mt7531_ind_mmd_phy_[read,write] to complete this
-- * function.
-+ /* Enable Energy-Efficient Ethernet (EEE) and PHY core PLL, since
-+ * phy_device has not yet been created provided for
-+ * phy_[read,write]_mmd_indirect is called, we provide our own
-+ * mt7531_ind_mmd_phy_[read,write] to complete this function.
- */
- val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR,
- MDIO_MMD_VEND2, CORE_PLL_GROUP4);
-- val |= MT7531_PHY_PLL_BYPASS_MODE;
-+ val |= MT7531_RG_SYSPLL_DMY2 | MT7531_PHY_PLL_BYPASS_MODE;
- val &= ~MT7531_PHY_PLL_OFF;
- mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2,
- CORE_PLL_GROUP4, val);
-
-+ /* Disable EEE advertisement on the switch PHYs. */
-+ for (i = MT753X_CTRL_PHY_ADDR;
-+ i < MT753X_CTRL_PHY_ADDR + MT7530_NUM_PHYS; i++) {
-+ mt7531_ind_c45_phy_write(priv, i, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
-+ 0);
-+ }
-+
- mt7531_setup_common(ds);
-
- /* Setup VLAN ID 0 for VLAN-unaware bridges */
---- a/drivers/net/dsa/mt7530.h
-+++ b/drivers/net/dsa/mt7530.h
-@@ -616,6 +616,7 @@ enum mt7531_clk_skew {
- #define RG_SYSPLL_DDSFBK_EN BIT(12)
- #define RG_SYSPLL_BIAS_EN BIT(11)
- #define RG_SYSPLL_BIAS_LPF_EN BIT(10)
-+#define MT7531_RG_SYSPLL_DMY2 BIT(6)
- #define MT7531_PHY_PLL_OFF BIT(5)
- #define MT7531_PHY_PLL_BYPASS_MODE BIT(4)
-
+++ /dev/null
-From b7427d66cb3d6dca5165de5f7d80d59f08c2795b Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
-Date: Tue, 9 Apr 2024 18:01:14 +0300
-Subject: [PATCH 2/2] net: dsa: mt7530: trap link-local frames regardless of ST
- Port State
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-In Clause 5 of IEEE Std 802-2014, two sublayers of the data link layer
-(DLL) of the Open Systems Interconnection basic reference model (OSI/RM)
-are described; the medium access control (MAC) and logical link control
-(LLC) sublayers. The MAC sublayer is the one facing the physical layer.
-
-In 8.2 of IEEE Std 802.1Q-2022, the Bridge architecture is described. A
-Bridge component comprises a MAC Relay Entity for interconnecting the Ports
-of the Bridge, at least two Ports, and higher layer entities with at least
-a Spanning Tree Protocol Entity included.
-
-Each Bridge Port also functions as an end station and shall provide the MAC
-Service to an LLC Entity. Each instance of the MAC Service is provided to a
-distinct LLC Entity that supports protocol identification, multiplexing,
-and demultiplexing, for protocol data unit (PDU) transmission and reception
-by one or more higher layer entities.
-
-It is described in 8.13.9 of IEEE Std 802.1Q-2022 that in a Bridge, the LLC
-Entity associated with each Bridge Port is modeled as being directly
-connected to the attached Local Area Network (LAN).
-
-On the switch with CPU port architecture, CPU port functions as Management
-Port, and the Management Port functionality is provided by software which
-functions as an end station. Software is connected to an IEEE 802 LAN that
-is wholly contained within the system that incorporates the Bridge.
-Software provides access to the LLC Entity associated with each Bridge Port
-by the value of the source port field on the special tag on the frame
-received by software.
-
-We call frames that carry control information to determine the active
-topology and current extent of each Virtual Local Area Network (VLAN),
-i.e., spanning tree or Shortest Path Bridging (SPB) and Multiple VLAN
-Registration Protocol Data Units (MVRPDUs), and frames from other link
-constrained protocols, such as Extensible Authentication Protocol over LAN
-(EAPOL) and Link Layer Discovery Protocol (LLDP), link-local frames. They
-are not forwarded by a Bridge. Permanently configured entries in the
-filtering database (FDB) ensure that such frames are discarded by the
-Forwarding Process. In 8.6.3 of IEEE Std 802.1Q-2022, this is described in
-detail:
-
-Each of the reserved MAC addresses specified in Table 8-1
-(01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]) shall be
-permanently configured in the FDB in C-VLAN components and ERs.
-
-Each of the reserved MAC addresses specified in Table 8-2
-(01-80-C2-00-00-[01,02,03,04,05,06,07,08,09,0A,0E]) shall be permanently
-configured in the FDB in S-VLAN components.
-
-Each of the reserved MAC addresses specified in Table 8-3
-(01-80-C2-00-00-[01,02,04,0E]) shall be permanently configured in the FDB
-in TPMR components.
-
-The FDB entries for reserved MAC addresses shall specify filtering for all
-Bridge Ports and all VIDs. Management shall not provide the capability to
-modify or remove entries for reserved MAC addresses.
-
-The addresses in Table 8-1, Table 8-2, and Table 8-3 determine the scope of
-propagation of PDUs within a Bridged Network, as follows:
-
- The Nearest Bridge group address (01-80-C2-00-00-0E) is an address that
- no conformant Two-Port MAC Relay (TPMR) component, Service VLAN (S-VLAN)
- component, Customer VLAN (C-VLAN) component, or MAC Bridge can forward.
- PDUs transmitted using this destination address, or any other addresses
- that appear in Table 8-1, Table 8-2, and Table 8-3
- (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]), can
- therefore travel no further than those stations that can be reached via a
- single individual LAN from the originating station.
-
- The Nearest non-TPMR Bridge group address (01-80-C2-00-00-03), is an
- address that no conformant S-VLAN component, C-VLAN component, or MAC
- Bridge can forward; however, this address is relayed by a TPMR component.
- PDUs using this destination address, or any of the other addresses that
- appear in both Table 8-1 and Table 8-2 but not in Table 8-3
- (01-80-C2-00-00-[00,03,05,06,07,08,09,0A,0B,0C,0D,0F]), will be relayed
- by any TPMRs but will propagate no further than the nearest S-VLAN
- component, C-VLAN component, or MAC Bridge.
-
- The Nearest Customer Bridge group address (01-80-C2-00-00-00) is an
- address that no conformant C-VLAN component, MAC Bridge can forward;
- however, it is relayed by TPMR components and S-VLAN components. PDUs
- using this destination address, or any of the other addresses that appear
- in Table 8-1 but not in either Table 8-2 or Table 8-3
- (01-80-C2-00-00-[00,0B,0C,0D,0F]), will be relayed by TPMR components and
- S-VLAN components but will propagate no further than the nearest C-VLAN
- component or MAC Bridge.
-
-Because the LLC Entity associated with each Bridge Port is provided via CPU
-port, we must not filter these frames but forward them to CPU port.
-
-In a Bridge, the transmission Port is majorly decided by ingress and egress
-rules, FDB, and spanning tree Port State functions of the Forwarding
-Process. For link-local frames, only CPU port should be designated as
-destination port in the FDB, and the other functions of the Forwarding
-Process must not interfere with the decision of the transmission Port. We
-call this process trapping frames to CPU port.
-
-Therefore, on the switch with CPU port architecture, link-local frames must
-be trapped to CPU port, and certain link-local frames received by a Port of
-a Bridge comprising a TPMR component or an S-VLAN component must be
-excluded from it.
-
-A Bridge of the switch with CPU port architecture cannot comprise a
-Two-Port MAC Relay (TPMR) component as a TPMR component supports only a
-subset of the functionality of a MAC Bridge. A Bridge comprising two Ports
-(Management Port doesn't count) of this architecture will either function
-as a standard MAC Bridge or a standard VLAN Bridge.
-
-Therefore, a Bridge of this architecture can only comprise S-VLAN
-components, C-VLAN components, or MAC Bridge components. Since there's no
-TPMR component, we don't need to relay PDUs using the destination addresses
-specified on the Nearest non-TPMR section, and the proportion of the
-Nearest Customer Bridge section where they must be relayed by TPMR
-components.
-
-One option to trap link-local frames to CPU port is to add static FDB
-entries with CPU port designated as destination port. However, because that
-Independent VLAN Learning (IVL) is being used on every VID, each entry only
-applies to a single VLAN Identifier (VID). For a Bridge comprising a MAC
-Bridge component or a C-VLAN component, there would have to be 16 times
-4096 entries. This switch intellectual property can only hold a maximum of
-2048 entries. Using this option, there also isn't a mechanism to prevent
-link-local frames from being discarded when the spanning tree Port State of
-the reception Port is discarding.
-
-The remaining option is to utilise the BPC, RGAC1, RGAC2, RGAC3, and RGAC4
-registers. Whilst this applies to every VID, it doesn't contain all of the
-reserved MAC addresses without affecting the remaining Standard Group MAC
-Addresses. The REV_UN frame tag utilised using the RGAC4 register covers
-the remaining 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] destination
-addresses. It also includes the 01-80-C2-00-00-22 to 01-80-C2-00-00-FF
-destination addresses which may be relayed by MAC Bridges or VLAN Bridges.
-The latter option provides better but not complete conformance.
-
-This switch intellectual property also does not provide a mechanism to trap
-link-local frames with specific destination addresses to CPU port by
-Bridge, to conform to the filtering rules for the distinct Bridge
-components.
-
-Therefore, regardless of the type of the Bridge component, link-local
-frames with these destination addresses will be trapped to CPU port:
-
-01-80-C2-00-00-[00,01,02,03,0E]
-
-In a Bridge comprising a MAC Bridge component or a C-VLAN component:
-
- Link-local frames with these destination addresses won't be trapped to
- CPU port which won't conform to IEEE Std 802.1Q-2022:
-
- 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F]
-
-In a Bridge comprising an S-VLAN component:
-
- Link-local frames with these destination addresses will be trapped to CPU
- port which won't conform to IEEE Std 802.1Q-2022:
-
- 01-80-C2-00-00-00
-
- Link-local frames with these destination addresses won't be trapped to
- CPU port which won't conform to IEEE Std 802.1Q-2022:
-
- 01-80-C2-00-00-[04,05,06,07,08,09,0A]
-
-Currently on this switch intellectual property, if the spanning tree Port
-State of the reception Port is discarding, link-local frames will be
-discarded.
-
-To trap link-local frames regardless of the spanning tree Port State, make
-the switch regard them as Bridge Protocol Data Units (BPDUs). This switch
-intellectual property only lets the frames regarded as BPDUs bypass the
-spanning tree Port State function of the Forwarding Process.
-
-With this change, the only remaining interference is the ingress rules.
-When the reception Port has no PVID assigned on software, VLAN-untagged
-frames won't be allowed in. There doesn't seem to be a mechanism on the
-switch intellectual property to have link-local frames bypass this function
-of the Forwarding Process.
-
-Fixes: b8f126a8d543 ("net-next: dsa: add dsa support for Mediatek MT7530 switch")
-Reviewed-by: Daniel Golle <daniel@makrotopia.org>
-Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
----
- drivers/net/dsa/mt7530.c | 229 +++++++++++++++++++++++++++++++++------
- drivers/net/dsa/mt7530.h | 5 +
- 2 files changed, 200 insertions(+), 34 deletions(-)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -943,20 +943,173 @@ static void mt7530_setup_port5(struct ds
- mutex_unlock(&priv->reg_mutex);
- }
-
--/* On page 205, section "8.6.3 Frame filtering" of the active standard, IEEE Std
-- * 802.1Q™-2022, it is stated that frames with 01:80:C2:00:00:00-0F as MAC DA
-- * must only be propagated to C-VLAN and MAC Bridge components. That means
-- * VLAN-aware and VLAN-unaware bridges. On the switch designs with CPU ports,
-- * these frames are supposed to be processed by the CPU (software). So we make
-- * the switch only forward them to the CPU port. And if received from a CPU
-- * port, forward to a single port. The software is responsible of making the
-- * switch conform to the latter by setting a single port as destination port on
-- * the special tag.
-- *
-- * This switch intellectual property cannot conform to this part of the standard
-- * fully. Whilst the REV_UN frame tag covers the remaining :04-0D and :0F MAC
-- * DAs, it also includes :22-FF which the scope of propagation is not supposed
-- * to be restricted for these MAC DAs.
-+/* In Clause 5 of IEEE Std 802-2014, two sublayers of the data link layer (DLL)
-+ * of the Open Systems Interconnection basic reference model (OSI/RM) are
-+ * described; the medium access control (MAC) and logical link control (LLC)
-+ * sublayers. The MAC sublayer is the one facing the physical layer.
-+ *
-+ * In 8.2 of IEEE Std 802.1Q-2022, the Bridge architecture is described. A
-+ * Bridge component comprises a MAC Relay Entity for interconnecting the Ports
-+ * of the Bridge, at least two Ports, and higher layer entities with at least a
-+ * Spanning Tree Protocol Entity included.
-+ *
-+ * Each Bridge Port also functions as an end station and shall provide the MAC
-+ * Service to an LLC Entity. Each instance of the MAC Service is provided to a
-+ * distinct LLC Entity that supports protocol identification, multiplexing, and
-+ * demultiplexing, for protocol data unit (PDU) transmission and reception by
-+ * one or more higher layer entities.
-+ *
-+ * It is described in 8.13.9 of IEEE Std 802.1Q-2022 that in a Bridge, the LLC
-+ * Entity associated with each Bridge Port is modeled as being directly
-+ * connected to the attached Local Area Network (LAN).
-+ *
-+ * On the switch with CPU port architecture, CPU port functions as Management
-+ * Port, and the Management Port functionality is provided by software which
-+ * functions as an end station. Software is connected to an IEEE 802 LAN that is
-+ * wholly contained within the system that incorporates the Bridge. Software
-+ * provides access to the LLC Entity associated with each Bridge Port by the
-+ * value of the source port field on the special tag on the frame received by
-+ * software.
-+ *
-+ * We call frames that carry control information to determine the active
-+ * topology and current extent of each Virtual Local Area Network (VLAN), i.e.,
-+ * spanning tree or Shortest Path Bridging (SPB) and Multiple VLAN Registration
-+ * Protocol Data Units (MVRPDUs), and frames from other link constrained
-+ * protocols, such as Extensible Authentication Protocol over LAN (EAPOL) and
-+ * Link Layer Discovery Protocol (LLDP), link-local frames. They are not
-+ * forwarded by a Bridge. Permanently configured entries in the filtering
-+ * database (FDB) ensure that such frames are discarded by the Forwarding
-+ * Process. In 8.6.3 of IEEE Std 802.1Q-2022, this is described in detail:
-+ *
-+ * Each of the reserved MAC addresses specified in Table 8-1
-+ * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]) shall be
-+ * permanently configured in the FDB in C-VLAN components and ERs.
-+ *
-+ * Each of the reserved MAC addresses specified in Table 8-2
-+ * (01-80-C2-00-00-[01,02,03,04,05,06,07,08,09,0A,0E]) shall be permanently
-+ * configured in the FDB in S-VLAN components.
-+ *
-+ * Each of the reserved MAC addresses specified in Table 8-3
-+ * (01-80-C2-00-00-[01,02,04,0E]) shall be permanently configured in the FDB in
-+ * TPMR components.
-+ *
-+ * The FDB entries for reserved MAC addresses shall specify filtering for all
-+ * Bridge Ports and all VIDs. Management shall not provide the capability to
-+ * modify or remove entries for reserved MAC addresses.
-+ *
-+ * The addresses in Table 8-1, Table 8-2, and Table 8-3 determine the scope of
-+ * propagation of PDUs within a Bridged Network, as follows:
-+ *
-+ * The Nearest Bridge group address (01-80-C2-00-00-0E) is an address that no
-+ * conformant Two-Port MAC Relay (TPMR) component, Service VLAN (S-VLAN)
-+ * component, Customer VLAN (C-VLAN) component, or MAC Bridge can forward.
-+ * PDUs transmitted using this destination address, or any other addresses
-+ * that appear in Table 8-1, Table 8-2, and Table 8-3
-+ * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]), can
-+ * therefore travel no further than those stations that can be reached via a
-+ * single individual LAN from the originating station.
-+ *
-+ * The Nearest non-TPMR Bridge group address (01-80-C2-00-00-03), is an
-+ * address that no conformant S-VLAN component, C-VLAN component, or MAC
-+ * Bridge can forward; however, this address is relayed by a TPMR component.
-+ * PDUs using this destination address, or any of the other addresses that
-+ * appear in both Table 8-1 and Table 8-2 but not in Table 8-3
-+ * (01-80-C2-00-00-[00,03,05,06,07,08,09,0A,0B,0C,0D,0F]), will be relayed by
-+ * any TPMRs but will propagate no further than the nearest S-VLAN component,
-+ * C-VLAN component, or MAC Bridge.
-+ *
-+ * The Nearest Customer Bridge group address (01-80-C2-00-00-00) is an address
-+ * that no conformant C-VLAN component, MAC Bridge can forward; however, it is
-+ * relayed by TPMR components and S-VLAN components. PDUs using this
-+ * destination address, or any of the other addresses that appear in Table 8-1
-+ * but not in either Table 8-2 or Table 8-3 (01-80-C2-00-00-[00,0B,0C,0D,0F]),
-+ * will be relayed by TPMR components and S-VLAN components but will propagate
-+ * no further than the nearest C-VLAN component or MAC Bridge.
-+ *
-+ * Because the LLC Entity associated with each Bridge Port is provided via CPU
-+ * port, we must not filter these frames but forward them to CPU port.
-+ *
-+ * In a Bridge, the transmission Port is majorly decided by ingress and egress
-+ * rules, FDB, and spanning tree Port State functions of the Forwarding Process.
-+ * For link-local frames, only CPU port should be designated as destination port
-+ * in the FDB, and the other functions of the Forwarding Process must not
-+ * interfere with the decision of the transmission Port. We call this process
-+ * trapping frames to CPU port.
-+ *
-+ * Therefore, on the switch with CPU port architecture, link-local frames must
-+ * be trapped to CPU port, and certain link-local frames received by a Port of a
-+ * Bridge comprising a TPMR component or an S-VLAN component must be excluded
-+ * from it.
-+ *
-+ * A Bridge of the switch with CPU port architecture cannot comprise a Two-Port
-+ * MAC Relay (TPMR) component as a TPMR component supports only a subset of the
-+ * functionality of a MAC Bridge. A Bridge comprising two Ports (Management Port
-+ * doesn't count) of this architecture will either function as a standard MAC
-+ * Bridge or a standard VLAN Bridge.
-+ *
-+ * Therefore, a Bridge of this architecture can only comprise S-VLAN components,
-+ * C-VLAN components, or MAC Bridge components. Since there's no TPMR component,
-+ * we don't need to relay PDUs using the destination addresses specified on the
-+ * Nearest non-TPMR section, and the proportion of the Nearest Customer Bridge
-+ * section where they must be relayed by TPMR components.
-+ *
-+ * One option to trap link-local frames to CPU port is to add static FDB entries
-+ * with CPU port designated as destination port. However, because that
-+ * Independent VLAN Learning (IVL) is being used on every VID, each entry only
-+ * applies to a single VLAN Identifier (VID). For a Bridge comprising a MAC
-+ * Bridge component or a C-VLAN component, there would have to be 16 times 4096
-+ * entries. This switch intellectual property can only hold a maximum of 2048
-+ * entries. Using this option, there also isn't a mechanism to prevent
-+ * link-local frames from being discarded when the spanning tree Port State of
-+ * the reception Port is discarding.
-+ *
-+ * The remaining option is to utilise the BPC, RGAC1, RGAC2, RGAC3, and RGAC4
-+ * registers. Whilst this applies to every VID, it doesn't contain all of the
-+ * reserved MAC addresses without affecting the remaining Standard Group MAC
-+ * Addresses. The REV_UN frame tag utilised using the RGAC4 register covers the
-+ * remaining 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] destination
-+ * addresses. It also includes the 01-80-C2-00-00-22 to 01-80-C2-00-00-FF
-+ * destination addresses which may be relayed by MAC Bridges or VLAN Bridges.
-+ * The latter option provides better but not complete conformance.
-+ *
-+ * This switch intellectual property also does not provide a mechanism to trap
-+ * link-local frames with specific destination addresses to CPU port by Bridge,
-+ * to conform to the filtering rules for the distinct Bridge components.
-+ *
-+ * Therefore, regardless of the type of the Bridge component, link-local frames
-+ * with these destination addresses will be trapped to CPU port:
-+ *
-+ * 01-80-C2-00-00-[00,01,02,03,0E]
-+ *
-+ * In a Bridge comprising a MAC Bridge component or a C-VLAN component:
-+ *
-+ * Link-local frames with these destination addresses won't be trapped to CPU
-+ * port which won't conform to IEEE Std 802.1Q-2022:
-+ *
-+ * 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F]
-+ *
-+ * In a Bridge comprising an S-VLAN component:
-+ *
-+ * Link-local frames with these destination addresses will be trapped to CPU
-+ * port which won't conform to IEEE Std 802.1Q-2022:
-+ *
-+ * 01-80-C2-00-00-00
-+ *
-+ * Link-local frames with these destination addresses won't be trapped to CPU
-+ * port which won't conform to IEEE Std 802.1Q-2022:
-+ *
-+ * 01-80-C2-00-00-[04,05,06,07,08,09,0A]
-+ *
-+ * To trap link-local frames to CPU port as conformant as this switch
-+ * intellectual property can allow, link-local frames are made to be regarded as
-+ * Bridge Protocol Data Units (BPDUs). This is because this switch intellectual
-+ * property only lets the frames regarded as BPDUs bypass the spanning tree Port
-+ * State function of the Forwarding Process.
-+ *
-+ * The only remaining interference is the ingress rules. When the reception Port
-+ * has no PVID assigned on software, VLAN-untagged frames won't be allowed in.
-+ * There doesn't seem to be a mechanism on the switch intellectual property to
-+ * have link-local frames bypass this function of the Forwarding Process.
- */
- static void
- mt753x_trap_frames(struct mt7530_priv *priv)
-@@ -964,35 +1117,43 @@ mt753x_trap_frames(struct mt7530_priv *p
- /* Trap 802.1X PAE frames and BPDUs to the CPU port(s) and egress them
- * VLAN-untagged.
- */
-- mt7530_rmw(priv, MT753X_BPC, MT753X_PAE_EG_TAG_MASK |
-- MT753X_PAE_PORT_FW_MASK | MT753X_BPDU_EG_TAG_MASK |
-- MT753X_BPDU_PORT_FW_MASK,
-- MT753X_PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
-- MT753X_PAE_PORT_FW(MT753X_BPDU_CPU_ONLY) |
-- MT753X_BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
-- MT753X_BPDU_CPU_ONLY);
-+ mt7530_rmw(priv, MT753X_BPC,
-+ MT753X_PAE_BPDU_FR | MT753X_PAE_EG_TAG_MASK |
-+ MT753X_PAE_PORT_FW_MASK | MT753X_BPDU_EG_TAG_MASK |
-+ MT753X_BPDU_PORT_FW_MASK,
-+ MT753X_PAE_BPDU_FR |
-+ MT753X_PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
-+ MT753X_PAE_PORT_FW(MT753X_BPDU_CPU_ONLY) |
-+ MT753X_BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
-+ MT753X_BPDU_CPU_ONLY);
-
- /* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and egress
- * them VLAN-untagged.
- */
-- mt7530_rmw(priv, MT753X_RGAC1, MT753X_R02_EG_TAG_MASK |
-- MT753X_R02_PORT_FW_MASK | MT753X_R01_EG_TAG_MASK |
-- MT753X_R01_PORT_FW_MASK,
-- MT753X_R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
-- MT753X_R02_PORT_FW(MT753X_BPDU_CPU_ONLY) |
-- MT753X_R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
-- MT753X_BPDU_CPU_ONLY);
-+ mt7530_rmw(priv, MT753X_RGAC1,
-+ MT753X_R02_BPDU_FR | MT753X_R02_EG_TAG_MASK |
-+ MT753X_R02_PORT_FW_MASK | MT753X_R01_BPDU_FR |
-+ MT753X_R01_EG_TAG_MASK | MT753X_R01_PORT_FW_MASK,
-+ MT753X_R02_BPDU_FR |
-+ MT753X_R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
-+ MT753X_R02_PORT_FW(MT753X_BPDU_CPU_ONLY) |
-+ MT753X_R01_BPDU_FR |
-+ MT753X_R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
-+ MT753X_BPDU_CPU_ONLY);
-
- /* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and egress
- * them VLAN-untagged.
- */
-- mt7530_rmw(priv, MT753X_RGAC2, MT753X_R0E_EG_TAG_MASK |
-- MT753X_R0E_PORT_FW_MASK | MT753X_R03_EG_TAG_MASK |
-- MT753X_R03_PORT_FW_MASK,
-- MT753X_R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
-- MT753X_R0E_PORT_FW(MT753X_BPDU_CPU_ONLY) |
-- MT753X_R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
-- MT753X_BPDU_CPU_ONLY);
-+ mt7530_rmw(priv, MT753X_RGAC2,
-+ MT753X_R0E_BPDU_FR | MT753X_R0E_EG_TAG_MASK |
-+ MT753X_R0E_PORT_FW_MASK | MT753X_R03_BPDU_FR |
-+ MT753X_R03_EG_TAG_MASK | MT753X_R03_PORT_FW_MASK,
-+ MT753X_R0E_BPDU_FR |
-+ MT753X_R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
-+ MT753X_R0E_PORT_FW(MT753X_BPDU_CPU_ONLY) |
-+ MT753X_R03_BPDU_FR |
-+ MT753X_R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
-+ MT753X_BPDU_CPU_ONLY);
- }
-
- static void
---- a/drivers/net/dsa/mt7530.h
-+++ b/drivers/net/dsa/mt7530.h
-@@ -65,6 +65,7 @@ enum mt753x_id {
-
- /* Registers for BPDU and PAE frame control*/
- #define MT753X_BPC 0x24
-+#define MT753X_PAE_BPDU_FR BIT(25)
- #define MT753X_PAE_EG_TAG_MASK GENMASK(24, 22)
- #define MT753X_PAE_EG_TAG(x) FIELD_PREP(MT753X_PAE_EG_TAG_MASK, x)
- #define MT753X_PAE_PORT_FW_MASK GENMASK(18, 16)
-@@ -75,20 +76,24 @@ enum mt753x_id {
-
- /* Register for :01 and :02 MAC DA frame control */
- #define MT753X_RGAC1 0x28
-+#define MT753X_R02_BPDU_FR BIT(25)
- #define MT753X_R02_EG_TAG_MASK GENMASK(24, 22)
- #define MT753X_R02_EG_TAG(x) FIELD_PREP(MT753X_R02_EG_TAG_MASK, x)
- #define MT753X_R02_PORT_FW_MASK GENMASK(18, 16)
- #define MT753X_R02_PORT_FW(x) FIELD_PREP(MT753X_R02_PORT_FW_MASK, x)
-+#define MT753X_R01_BPDU_FR BIT(9)
- #define MT753X_R01_EG_TAG_MASK GENMASK(8, 6)
- #define MT753X_R01_EG_TAG(x) FIELD_PREP(MT753X_R01_EG_TAG_MASK, x)
- #define MT753X_R01_PORT_FW_MASK GENMASK(2, 0)
-
- /* Register for :03 and :0E MAC DA frame control */
- #define MT753X_RGAC2 0x2c
-+#define MT753X_R0E_BPDU_FR BIT(25)
- #define MT753X_R0E_EG_TAG_MASK GENMASK(24, 22)
- #define MT753X_R0E_EG_TAG(x) FIELD_PREP(MT753X_R0E_EG_TAG_MASK, x)
- #define MT753X_R0E_PORT_FW_MASK GENMASK(18, 16)
- #define MT753X_R0E_PORT_FW(x) FIELD_PREP(MT753X_R0E_PORT_FW_MASK, x)
-+#define MT753X_R03_BPDU_FR BIT(9)
- #define MT753X_R03_EG_TAG_MASK GENMASK(8, 6)
- #define MT753X_R03_EG_TAG(x) FIELD_PREP(MT753X_R03_EG_TAG_MASK, x)
- #define MT753X_R03_PORT_FW_MASK GENMASK(2, 0)
--- a/net/bridge/br_input.c
+++ b/net/bridge/br_input.c
-@@ -239,6 +239,9 @@ static void __br_handle_local_finish(str
+@@ -244,6 +244,9 @@ static void __br_handle_local_finish(str
/* note: already called with rcu_read_lock */
static int br_handle_local_finish(struct net *net, struct sock *sk, struct sk_buff *skb)
{
__br_handle_local_finish(skb);
/* return 1 to signal the okfn() was called so it's ok to use the skb */
-@@ -408,6 +411,17 @@ forward:
+@@ -415,6 +418,17 @@ forward:
goto defer_stp_filtering;
switch (p->state) {
for (i = sizeof(struct ipt_entry);
i < e->target_offset;
i += m->u.match_size) {
-@@ -1223,12 +1260,15 @@ compat_copy_entry_to_user(struct ipt_ent
+@@ -1225,12 +1262,15 @@ compat_copy_entry_to_user(struct ipt_ent
compat_uint_t origsize;
const struct xt_entry_match *ematch;
int ret = 0;
+++ /dev/null
-From: Felix Fietkau <nbd@nbd.name>
-Subject: net: replace GRO optimization patch with a new one that supports VLANs/bridges with different MAC addresses
-
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
- include/linux/netdevice.h | 2 ++
- include/linux/skbuff.h | 3 ++-
- net/core/dev.c | 48 +++++++++++++++++++++++++++++++++++++++++++++++
- net/ethernet/eth.c | 18 +++++++++++++++++-
- 4 files changed, 69 insertions(+), 2 deletions(-)
-
---- a/include/linux/netdevice.h
-+++ b/include/linux/netdevice.h
-@@ -2210,6 +2210,8 @@ struct net_device {
- struct netdev_hw_addr_list mc;
- struct netdev_hw_addr_list dev_addrs;
-
-+ unsigned char local_addr_mask[MAX_ADDR_LEN];
-+
- #ifdef CONFIG_SYSFS
- struct kset *queues_kset;
- #endif
---- a/include/linux/skbuff.h
-+++ b/include/linux/skbuff.h
-@@ -959,6 +959,7 @@ struct sk_buff {
- #ifdef CONFIG_IPV6_NDISC_NODETYPE
- __u8 ndisc_nodetype:2;
- #endif
-+ __u8 gro_skip:1;
-
- #if IS_ENABLED(CONFIG_IP_VS)
- __u8 ipvs_property:1;
---- a/net/core/gro.c
-+++ b/net/core/gro.c
-@@ -446,6 +446,9 @@ static enum gro_result dev_gro_receive(s
- enum gro_result ret;
- int same_flow;
-
-+ if (skb->gro_skip)
-+ goto normal;
-+
- if (netif_elide_gro(skb->dev))
- goto normal;
-
---- a/net/core/dev.c
-+++ b/net/core/dev.c
-@@ -7689,6 +7689,48 @@ static void __netdev_adjacent_dev_unlink
- &upper_dev->adj_list.lower);
- }
-
-+static void __netdev_addr_mask(unsigned char *mask, const unsigned char *addr,
-+ struct net_device *dev)
-+{
-+ int i;
-+
-+ for (i = 0; i < dev->addr_len; i++)
-+ mask[i] |= addr[i] ^ dev->dev_addr[i];
-+}
-+
-+static void __netdev_upper_mask(unsigned char *mask, struct net_device *dev,
-+ struct net_device *lower)
-+{
-+ struct net_device *cur;
-+ struct list_head *iter;
-+
-+ netdev_for_each_upper_dev_rcu(dev, cur, iter) {
-+ __netdev_addr_mask(mask, cur->dev_addr, lower);
-+ __netdev_upper_mask(mask, cur, lower);
-+ }
-+}
-+
-+static void __netdev_update_addr_mask(struct net_device *dev)
-+{
-+ unsigned char mask[MAX_ADDR_LEN];
-+ struct net_device *cur;
-+ struct list_head *iter;
-+
-+ memset(mask, 0, sizeof(mask));
-+ __netdev_upper_mask(mask, dev, dev);
-+ memcpy(dev->local_addr_mask, mask, dev->addr_len);
-+
-+ netdev_for_each_lower_dev(dev, cur, iter)
-+ __netdev_update_addr_mask(cur);
-+}
-+
-+static void netdev_update_addr_mask(struct net_device *dev)
-+{
-+ rcu_read_lock();
-+ __netdev_update_addr_mask(dev);
-+ rcu_read_unlock();
-+}
-+
- static int __netdev_upper_dev_link(struct net_device *dev,
- struct net_device *upper_dev, bool master,
- void *upper_priv, void *upper_info,
-@@ -7740,6 +7782,7 @@ static int __netdev_upper_dev_link(struc
- if (ret)
- return ret;
-
-+ netdev_update_addr_mask(dev);
- ret = call_netdevice_notifiers_info(NETDEV_CHANGEUPPER,
- &changeupper_info.info);
- ret = notifier_to_errno(ret);
-@@ -7836,6 +7879,7 @@ static void __netdev_upper_dev_unlink(st
-
- __netdev_adjacent_dev_unlink_neighbour(dev, upper_dev);
-
-+ netdev_update_addr_mask(dev);
- call_netdevice_notifiers_info(NETDEV_CHANGEUPPER,
- &changeupper_info.info);
-
-@@ -8892,6 +8936,7 @@ int dev_set_mac_address(struct net_devic
- return err;
- }
- dev->addr_assign_type = NET_ADDR_SET;
-+ netdev_update_addr_mask(dev);
- call_netdevice_notifiers(NETDEV_CHANGEADDR, dev);
- add_device_randomness(dev->dev_addr, dev->addr_len);
- return 0;
---- a/net/ethernet/eth.c
-+++ b/net/ethernet/eth.c
-@@ -143,6 +143,18 @@ u32 eth_get_headlen(const struct net_dev
- }
- EXPORT_SYMBOL(eth_get_headlen);
-
-+static inline bool
-+eth_check_local_mask(const void *addr1, const void *addr2, const void *mask)
-+{
-+ const u16 *a1 = addr1;
-+ const u16 *a2 = addr2;
-+ const u16 *m = mask;
-+
-+ return (((a1[0] ^ a2[0]) & ~m[0]) |
-+ ((a1[1] ^ a2[1]) & ~m[1]) |
-+ ((a1[2] ^ a2[2]) & ~m[2]));
-+}
-+
- /**
- * eth_type_trans - determine the packet's protocol ID.
- * @skb: received socket data
-@@ -174,6 +186,10 @@ __be16 eth_type_trans(struct sk_buff *sk
- } else {
- skb->pkt_type = PACKET_OTHERHOST;
- }
-+
-+ if (eth_check_local_mask(eth->h_dest, dev->dev_addr,
-+ dev->local_addr_mask))
-+ skb->gro_skip = 1;
- }
-
- /*
--- /dev/null
+From: Felix Fietkau <nbd@nbd.name>
+Date: Tue, 23 Apr 2024 11:23:03 +0200
+Subject: [PATCH] net: add TCP fraglist GRO support
+
+When forwarding TCP after GRO, software segmentation is very expensive,
+especially when the checksum needs to be recalculated.
+One case where that's currently unavoidable is when routing packets over
+PPPoE. Performance improves significantly when using fraglist GRO
+implemented in the same way as for UDP.
+
+Here's a measurement of running 2 TCP streams through a MediaTek MT7622
+device (2-core Cortex-A53), which runs NAT with flow offload enabled from
+one ethernet port to PPPoE on another ethernet port + cake qdisc set to
+1Gbps.
+
+rx-gro-list off: 630 Mbit/s, CPU 35% idle
+rx-gro-list on: 770 Mbit/s, CPU 40% idle
+
+Signe-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/include/net/gro.h
++++ b/include/net/gro.h
+@@ -430,6 +430,7 @@ static inline __wsum ip6_gro_compute_pse
+ }
+
+ int skb_gro_receive(struct sk_buff *p, struct sk_buff *skb);
++int skb_gro_receive_list(struct sk_buff *p, struct sk_buff *skb);
+
+ /* Pass the currently batched GRO_NORMAL SKBs up to the stack. */
+ static inline void gro_normal_list(struct napi_struct *napi)
+--- a/include/net/tcp.h
++++ b/include/net/tcp.h
+@@ -2082,7 +2082,10 @@ void tcp_v4_destroy_sock(struct sock *sk
+
+ struct sk_buff *tcp_gso_segment(struct sk_buff *skb,
+ netdev_features_t features);
+-struct sk_buff *tcp_gro_receive(struct list_head *head, struct sk_buff *skb);
++struct tcphdr *tcp_gro_pull_header(struct sk_buff *skb);
++struct sk_buff *tcp_gro_lookup(struct list_head *head, struct tcphdr *th);
++struct sk_buff *tcp_gro_receive(struct list_head *head, struct sk_buff *skb,
++ struct tcphdr *th);
+ INDIRECT_CALLABLE_DECLARE(int tcp4_gro_complete(struct sk_buff *skb, int thoff));
+ INDIRECT_CALLABLE_DECLARE(struct sk_buff *tcp4_gro_receive(struct list_head *head, struct sk_buff *skb));
+ INDIRECT_CALLABLE_DECLARE(int tcp6_gro_complete(struct sk_buff *skb, int thoff));
+--- a/net/core/gro.c
++++ b/net/core/gro.c
+@@ -233,6 +233,33 @@ done:
+ return 0;
+ }
+
++int skb_gro_receive_list(struct sk_buff *p, struct sk_buff *skb)
++{
++ if (unlikely(p->len + skb->len >= 65536))
++ return -E2BIG;
++
++ if (NAPI_GRO_CB(p)->last == p)
++ skb_shinfo(p)->frag_list = skb;
++ else
++ NAPI_GRO_CB(p)->last->next = skb;
++
++ skb_pull(skb, skb_gro_offset(skb));
++
++ NAPI_GRO_CB(p)->last = skb;
++ NAPI_GRO_CB(p)->count++;
++ p->data_len += skb->len;
++
++ /* sk ownership - if any - completely transferred to the aggregated packet */
++ skb->destructor = NULL;
++ skb->sk = NULL;
++ p->truesize += skb->truesize;
++ p->len += skb->len;
++
++ NAPI_GRO_CB(skb)->same_flow = 1;
++
++ return 0;
++}
++
+
+ static void napi_gro_complete(struct napi_struct *napi, struct sk_buff *skb)
+ {
+--- a/net/ipv4/tcp_offload.c
++++ b/net/ipv4/tcp_offload.c
+@@ -28,6 +28,70 @@ static void tcp_gso_tstamp(struct sk_buf
+ }
+ }
+
++static void __tcpv4_gso_segment_csum(struct sk_buff *seg,
++ __be32 *oldip, __be32 newip,
++ __be16 *oldport, __be16 newport)
++{
++ struct tcphdr *th;
++ struct iphdr *iph;
++
++ if (*oldip == newip && *oldport == newport)
++ return;
++
++ th = tcp_hdr(seg);
++ iph = ip_hdr(seg);
++
++ inet_proto_csum_replace4(&th->check, seg, *oldip, newip, true);
++ inet_proto_csum_replace2(&th->check, seg, *oldport, newport, false);
++ *oldport = newport;
++
++ csum_replace4(&iph->check, *oldip, newip);
++ *oldip = newip;
++}
++
++static struct sk_buff *__tcpv4_gso_segment_list_csum(struct sk_buff *segs)
++{
++ const struct tcphdr *th;
++ const struct iphdr *iph;
++ struct sk_buff *seg;
++ struct tcphdr *th2;
++ struct iphdr *iph2;
++
++ seg = segs;
++ th = tcp_hdr(seg);
++ iph = ip_hdr(seg);
++ th2 = tcp_hdr(seg->next);
++ iph2 = ip_hdr(seg->next);
++
++ if (!(*(const u32 *)&th->source ^ *(const u32 *)&th2->source) &&
++ iph->daddr == iph2->daddr && iph->saddr == iph2->saddr)
++ return segs;
++
++ while ((seg = seg->next)) {
++ th2 = tcp_hdr(seg);
++ iph2 = ip_hdr(seg);
++
++ __tcpv4_gso_segment_csum(seg,
++ &iph2->saddr, iph->saddr,
++ &th2->source, th->source);
++ __tcpv4_gso_segment_csum(seg,
++ &iph2->daddr, iph->daddr,
++ &th2->dest, th->dest);
++ }
++
++ return segs;
++}
++
++static struct sk_buff *__tcp4_gso_segment_list(struct sk_buff *skb,
++ netdev_features_t features)
++{
++ skb = skb_segment_list(skb, features, skb_mac_header_len(skb));
++ if (IS_ERR(skb))
++ return skb;
++
++ return __tcpv4_gso_segment_list_csum(skb);
++}
++
+ static struct sk_buff *tcp4_gso_segment(struct sk_buff *skb,
+ netdev_features_t features)
+ {
+@@ -37,6 +101,9 @@ static struct sk_buff *tcp4_gso_segment(
+ if (!pskb_may_pull(skb, sizeof(struct tcphdr)))
+ return ERR_PTR(-EINVAL);
+
++ if (skb_shinfo(skb)->gso_type & SKB_GSO_FRAGLIST)
++ return __tcp4_gso_segment_list(skb, features);
++
+ if (unlikely(skb->ip_summed != CHECKSUM_PARTIAL)) {
+ const struct iphdr *iph = ip_hdr(skb);
+ struct tcphdr *th = tcp_hdr(skb);
+@@ -178,61 +245,76 @@ out:
+ return segs;
+ }
+
+-struct sk_buff *tcp_gro_receive(struct list_head *head, struct sk_buff *skb)
++struct sk_buff *tcp_gro_lookup(struct list_head *head, struct tcphdr *th)
+ {
+- struct sk_buff *pp = NULL;
++ struct tcphdr *th2;
+ struct sk_buff *p;
++
++ list_for_each_entry(p, head, list) {
++ if (!NAPI_GRO_CB(p)->same_flow)
++ continue;
++
++ th2 = tcp_hdr(p);
++ if (*(u32 *)&th->source ^ *(u32 *)&th2->source) {
++ NAPI_GRO_CB(p)->same_flow = 0;
++ continue;
++ }
++
++ return p;
++ }
++
++ return NULL;
++}
++
++struct tcphdr *tcp_gro_pull_header(struct sk_buff *skb)
++{
++ unsigned int thlen, hlen, off;
+ struct tcphdr *th;
+- struct tcphdr *th2;
+- unsigned int len;
+- unsigned int thlen;
+- __be32 flags;
+- unsigned int mss = 1;
+- unsigned int hlen;
+- unsigned int off;
+- int flush = 1;
+- int i;
+
+ off = skb_gro_offset(skb);
+ hlen = off + sizeof(*th);
+ th = skb_gro_header(skb, hlen, off);
+ if (unlikely(!th))
+- goto out;
++ return NULL;
+
+ thlen = th->doff * 4;
+ if (thlen < sizeof(*th))
+- goto out;
++ return NULL;
+
+ hlen = off + thlen;
+ if (skb_gro_header_hard(skb, hlen)) {
+ th = skb_gro_header_slow(skb, hlen, off);
+ if (unlikely(!th))
+- goto out;
++ return NULL;
+ }
+
+ skb_gro_pull(skb, thlen);
+
+- len = skb_gro_len(skb);
+- flags = tcp_flag_word(th);
+-
+- list_for_each_entry(p, head, list) {
+- if (!NAPI_GRO_CB(p)->same_flow)
+- continue;
++ return th;
++}
+
+- th2 = tcp_hdr(p);
++struct sk_buff *tcp_gro_receive(struct list_head *head, struct sk_buff *skb,
++ struct tcphdr *th)
++{
++ unsigned int thlen = th->doff * 4;
++ struct sk_buff *pp = NULL;
++ struct sk_buff *p;
++ struct tcphdr *th2;
++ unsigned int len;
++ __be32 flags;
++ unsigned int mss = 1;
++ int flush = 1;
++ int i;
+
+- if (*(u32 *)&th->source ^ *(u32 *)&th2->source) {
+- NAPI_GRO_CB(p)->same_flow = 0;
+- continue;
+- }
++ len = skb_gro_len(skb);
++ flags = tcp_flag_word(th);
+
+- goto found;
+- }
+- p = NULL;
+- goto out_check_final;
++ p = tcp_gro_lookup(head, th);
++ if (!p)
++ goto out_check_final;
+
+-found:
+ /* Include the IP ID check below from the inner most IP hdr */
++ th2 = tcp_hdr(p);
+ flush = NAPI_GRO_CB(p)->flush;
+ flush |= (__force int)(flags & TCP_FLAG_CWR);
+ flush |= (__force int)((flags ^ tcp_flag_word(th2)) &
+@@ -269,6 +351,18 @@ found:
+ flush |= p->decrypted ^ skb->decrypted;
+ #endif
+
++ if (unlikely(NAPI_GRO_CB(p)->is_flist)) {
++ flush |= (__force int)(flags ^ tcp_flag_word(th2));
++ flush |= skb->ip_summed != p->ip_summed;
++ flush |= skb->csum_level != p->csum_level;
++ flush |= NAPI_GRO_CB(p)->count >= 64;
++
++ if (flush || skb_gro_receive_list(p, skb))
++ mss = 1;
++
++ goto out_check_final;
++ }
++
+ if (flush || skb_gro_receive(p, skb)) {
+ mss = 1;
+ goto out_check_final;
+@@ -290,7 +384,6 @@ out_check_final:
+ if (p && (!NAPI_GRO_CB(skb)->same_flow || flush))
+ pp = p;
+
+-out:
+ NAPI_GRO_CB(skb)->flush |= (flush != 0);
+
+ return pp;
+@@ -314,18 +407,58 @@ void tcp_gro_complete(struct sk_buff *sk
+ }
+ EXPORT_SYMBOL(tcp_gro_complete);
+
++static void tcp4_check_fraglist_gro(struct list_head *head, struct sk_buff *skb,
++ struct tcphdr *th)
++{
++ const struct iphdr *iph;
++ struct sk_buff *p;
++ struct sock *sk;
++ struct net *net;
++ int iif, sdif;
++
++ if (!(skb->dev->features & NETIF_F_GRO_FRAGLIST))
++ return;
++
++ p = tcp_gro_lookup(head, th);
++ if (p) {
++ NAPI_GRO_CB(skb)->is_flist = NAPI_GRO_CB(p)->is_flist;
++ return;
++ }
++
++ inet_get_iif_sdif(skb, &iif, &sdif);
++ iph = skb_gro_network_header(skb);
++ net = dev_net(skb->dev);
++ sk = __inet_lookup_established(net, net->ipv4.tcp_death_row.hashinfo,
++ iph->saddr, th->source,
++ iph->daddr, ntohs(th->dest),
++ iif, sdif);
++ NAPI_GRO_CB(skb)->is_flist = !sk;
++ if (sk)
++ sock_put(sk);
++}
++
+ INDIRECT_CALLABLE_SCOPE
+ struct sk_buff *tcp4_gro_receive(struct list_head *head, struct sk_buff *skb)
+ {
++ struct tcphdr *th;
++
+ /* Don't bother verifying checksum if we're going to flush anyway. */
+ if (!NAPI_GRO_CB(skb)->flush &&
+ skb_gro_checksum_validate(skb, IPPROTO_TCP,
+- inet_gro_compute_pseudo)) {
+- NAPI_GRO_CB(skb)->flush = 1;
+- return NULL;
+- }
++ inet_gro_compute_pseudo))
++ goto flush;
++
++ th = tcp_gro_pull_header(skb);
++ if (!th)
++ goto flush;
+
+- return tcp_gro_receive(head, skb);
++ tcp4_check_fraglist_gro(head, skb, th);
++
++ return tcp_gro_receive(head, skb, th);
++
++flush:
++ NAPI_GRO_CB(skb)->flush = 1;
++ return NULL;
+ }
+
+ INDIRECT_CALLABLE_SCOPE int tcp4_gro_complete(struct sk_buff *skb, int thoff)
+@@ -333,6 +466,15 @@ INDIRECT_CALLABLE_SCOPE int tcp4_gro_com
+ const struct iphdr *iph = ip_hdr(skb);
+ struct tcphdr *th = tcp_hdr(skb);
+
++ if (unlikely(NAPI_GRO_CB(skb)->is_flist)) {
++ skb_shinfo(skb)->gso_type |= SKB_GSO_FRAGLIST | SKB_GSO_TCPV4;
++ skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count;
++
++ __skb_incr_checksum_unnecessary(skb);
++
++ return 0;
++ }
++
+ th->check = ~tcp_v4_check(skb->len - thoff, iph->saddr,
+ iph->daddr, 0);
+ skb_shinfo(skb)->gso_type |= SKB_GSO_TCPV4;
+--- a/net/ipv4/udp_offload.c
++++ b/net/ipv4/udp_offload.c
+@@ -433,33 +433,6 @@ out:
+ return segs;
+ }
+
+-static int skb_gro_receive_list(struct sk_buff *p, struct sk_buff *skb)
+-{
+- if (unlikely(p->len + skb->len >= 65536))
+- return -E2BIG;
+-
+- if (NAPI_GRO_CB(p)->last == p)
+- skb_shinfo(p)->frag_list = skb;
+- else
+- NAPI_GRO_CB(p)->last->next = skb;
+-
+- skb_pull(skb, skb_gro_offset(skb));
+-
+- NAPI_GRO_CB(p)->last = skb;
+- NAPI_GRO_CB(p)->count++;
+- p->data_len += skb->len;
+-
+- /* sk ownership - if any - completely transferred to the aggregated packet */
+- skb->destructor = NULL;
+- skb->sk = NULL;
+- p->truesize += skb->truesize;
+- p->len += skb->len;
+-
+- NAPI_GRO_CB(skb)->same_flow = 1;
+-
+- return 0;
+-}
+-
+
+ #define UDP_GRO_CNT_MAX 64
+ static struct sk_buff *udp_gro_receive_segment(struct list_head *head,
+--- a/net/ipv6/tcpv6_offload.c
++++ b/net/ipv6/tcpv6_offload.c
+@@ -7,24 +7,67 @@
+ */
+ #include <linux/indirect_call_wrapper.h>
+ #include <linux/skbuff.h>
++#include <net/inet6_hashtables.h>
+ #include <net/gro.h>
+ #include <net/protocol.h>
+ #include <net/tcp.h>
+ #include <net/ip6_checksum.h>
+ #include "ip6_offload.h"
+
++static void tcp6_check_fraglist_gro(struct list_head *head, struct sk_buff *skb,
++ struct tcphdr *th)
++{
++#if IS_ENABLED(CONFIG_IPV6)
++ const struct ipv6hdr *hdr;
++ struct sk_buff *p;
++ struct sock *sk;
++ struct net *net;
++ int iif, sdif;
++
++ if (!(skb->dev->features & NETIF_F_GRO_FRAGLIST))
++ return;
++
++ p = tcp_gro_lookup(head, th);
++ if (p) {
++ NAPI_GRO_CB(skb)->is_flist = NAPI_GRO_CB(p)->is_flist;
++ return;
++ }
++
++ inet6_get_iif_sdif(skb, &iif, &sdif);
++ hdr = skb_gro_network_header(skb);
++ net = dev_net(skb->dev);
++ sk = __inet6_lookup_established(net, net->ipv4.tcp_death_row.hashinfo,
++ &hdr->saddr, th->source,
++ &hdr->daddr, ntohs(th->dest),
++ iif, sdif);
++ NAPI_GRO_CB(skb)->is_flist = !sk;
++ if (sk)
++ sock_put(sk);
++#endif /* IS_ENABLED(CONFIG_IPV6) */
++}
++
+ INDIRECT_CALLABLE_SCOPE
+ struct sk_buff *tcp6_gro_receive(struct list_head *head, struct sk_buff *skb)
+ {
++ struct tcphdr *th;
++
+ /* Don't bother verifying checksum if we're going to flush anyway. */
+ if (!NAPI_GRO_CB(skb)->flush &&
+ skb_gro_checksum_validate(skb, IPPROTO_TCP,
+- ip6_gro_compute_pseudo)) {
+- NAPI_GRO_CB(skb)->flush = 1;
+- return NULL;
+- }
++ ip6_gro_compute_pseudo))
++ goto flush;
+
+- return tcp_gro_receive(head, skb);
++ th = tcp_gro_pull_header(skb);
++ if (!th)
++ goto flush;
++
++ tcp6_check_fraglist_gro(head, skb, th);
++
++ return tcp_gro_receive(head, skb, th);
++
++flush:
++ NAPI_GRO_CB(skb)->flush = 1;
++ return NULL;
+ }
+
+ INDIRECT_CALLABLE_SCOPE int tcp6_gro_complete(struct sk_buff *skb, int thoff)
+@@ -32,6 +75,15 @@ INDIRECT_CALLABLE_SCOPE int tcp6_gro_com
+ const struct ipv6hdr *iph = ipv6_hdr(skb);
+ struct tcphdr *th = tcp_hdr(skb);
+
++ if (unlikely(NAPI_GRO_CB(skb)->is_flist)) {
++ skb_shinfo(skb)->gso_type |= SKB_GSO_FRAGLIST | SKB_GSO_TCPV6;
++ skb_shinfo(skb)->gso_segs = NAPI_GRO_CB(skb)->count;
++
++ __skb_incr_checksum_unnecessary(skb);
++
++ return 0;
++ }
++
+ th->check = ~tcp_v6_check(skb->len - thoff, &iph->saddr,
+ &iph->daddr, 0);
+ skb_shinfo(skb)->gso_type |= SKB_GSO_TCPV6;
+@@ -40,6 +92,61 @@ INDIRECT_CALLABLE_SCOPE int tcp6_gro_com
+ return 0;
+ }
+
++static void __tcpv6_gso_segment_csum(struct sk_buff *seg,
++ __be16 *oldport, __be16 newport)
++{
++ struct tcphdr *th;
++
++ if (*oldport == newport)
++ return;
++
++ th = tcp_hdr(seg);
++ inet_proto_csum_replace2(&th->check, seg, *oldport, newport, false);
++ *oldport = newport;
++}
++
++static struct sk_buff *__tcpv6_gso_segment_list_csum(struct sk_buff *segs)
++{
++ const struct tcphdr *th;
++ const struct ipv6hdr *iph;
++ struct sk_buff *seg;
++ struct tcphdr *th2;
++ struct ipv6hdr *iph2;
++
++ seg = segs;
++ th = tcp_hdr(seg);
++ iph = ipv6_hdr(seg);
++ th2 = tcp_hdr(seg->next);
++ iph2 = ipv6_hdr(seg->next);
++
++ if (!(*(const u32 *)&th->source ^ *(const u32 *)&th2->source) &&
++ ipv6_addr_equal(&iph->saddr, &iph2->saddr) &&
++ ipv6_addr_equal(&iph->daddr, &iph2->daddr))
++ return segs;
++
++ while ((seg = seg->next)) {
++ th2 = tcp_hdr(seg);
++ iph2 = ipv6_hdr(seg);
++
++ iph2->saddr = iph->saddr;
++ iph2->daddr = iph->daddr;
++ __tcpv6_gso_segment_csum(seg, &th2->source, th->source);
++ __tcpv6_gso_segment_csum(seg, &th2->dest, th->dest);
++ }
++
++ return segs;
++}
++
++static struct sk_buff *__tcp6_gso_segment_list(struct sk_buff *skb,
++ netdev_features_t features)
++{
++ skb = skb_segment_list(skb, features, skb_mac_header_len(skb));
++ if (IS_ERR(skb))
++ return skb;
++
++ return __tcpv6_gso_segment_list_csum(skb);
++}
++
+ static struct sk_buff *tcp6_gso_segment(struct sk_buff *skb,
+ netdev_features_t features)
+ {
+@@ -51,6 +158,9 @@ static struct sk_buff *tcp6_gso_segment(
+ if (!pskb_may_pull(skb, sizeof(*th)))
+ return ERR_PTR(-EINVAL);
+
++ if (skb_shinfo(skb)->gso_type & SKB_GSO_FRAGLIST)
++ return __tcp6_gso_segment_list(skb, features);
++
+ if (unlikely(skb->ip_summed != CHECKSUM_PARTIAL)) {
+ const struct ipv6hdr *ipv6h = ipv6_hdr(skb);
+ struct tcphdr *th = tcp_hdr(skb);
--- /dev/null
+From: Felix Fietkau <nbd@nbd.name>
+Date: Sat, 27 Apr 2024 18:54:25 +0200
+Subject: [PATCH] net: bridge: fix multicast-to-unicast with fraglist GSO
+
+Calling skb_copy on a SKB_GSO_FRAGLIST skb is not valid, since it returns
+an invalid linearized skb. This code only needs to change the ethernet
+header, so pskb_copy is the right function to call here.
+
+Fixes: 6db6f0eae605 ("bridge: multicast to unicast")
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/net/bridge/br_forward.c
++++ b/net/bridge/br_forward.c
+@@ -266,7 +266,7 @@ static void maybe_deliver_addr(struct ne
+ if (skb->dev == p->dev && ether_addr_equal(src, addr))
+ return;
+
+- skb = skb_copy(skb, GFP_ATOMIC);
++ skb = pskb_copy(skb, GFP_ATOMIC);
+ if (!skb) {
+ DEV_STATS_INC(dev, tx_dropped);
+ return;
--- /dev/null
+From: Felix Fietkau <nbd@nbd.name>
+Date: Sat, 27 Apr 2024 19:29:45 +0200
+Subject: [PATCH] net: core: reject skb_copy(_expand) for fraglist GSO skbs
+
+SKB_GSO_FRAGLIST skbs must not be linearized, otherwise they become
+invalid. Return NULL if such an skb is passed to skb_copy or
+skb_copy_expand, in order to prevent a crash on a potential later
+call to skb_gso_segment.
+
+Fixes: 3a1296a38d0c ("net: Support GRO/GSO fraglist chaining.")
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/net/core/skbuff.c
++++ b/net/core/skbuff.c
+@@ -1971,11 +1971,17 @@ static inline int skb_alloc_rx_flag(cons
+
+ struct sk_buff *skb_copy(const struct sk_buff *skb, gfp_t gfp_mask)
+ {
+- int headerlen = skb_headroom(skb);
+- unsigned int size = skb_end_offset(skb) + skb->data_len;
+- struct sk_buff *n = __alloc_skb(size, gfp_mask,
+- skb_alloc_rx_flag(skb), NUMA_NO_NODE);
++ struct sk_buff *n;
++ unsigned int size;
++ int headerlen;
+
++ if (WARN_ON_ONCE(skb_shinfo(skb)->gso_type & SKB_GSO_FRAGLIST))
++ return NULL;
++
++ headerlen = skb_headroom(skb);
++ size = skb_end_offset(skb) + skb->data_len;
++ n = __alloc_skb(size, gfp_mask,
++ skb_alloc_rx_flag(skb), NUMA_NO_NODE);
+ if (!n)
+ return NULL;
+
+@@ -2303,12 +2309,17 @@ struct sk_buff *skb_copy_expand(const st
+ /*
+ * Allocate the copy buffer
+ */
+- struct sk_buff *n = __alloc_skb(newheadroom + skb->len + newtailroom,
+- gfp_mask, skb_alloc_rx_flag(skb),
+- NUMA_NO_NODE);
+- int oldheadroom = skb_headroom(skb);
+ int head_copy_len, head_copy_off;
++ struct sk_buff *n;
++ int oldheadroom;
++
++ if (WARN_ON_ONCE(skb_shinfo(skb)->gso_type & SKB_GSO_FRAGLIST))
++ return NULL;
+
++ oldheadroom = skb_headroom(skb);
++ n = __alloc_skb(newheadroom + skb->len + newtailroom,
++ gfp_mask, skb_alloc_rx_flag(skb),
++ NUMA_NO_NODE);
+ if (!n)
+ return NULL;
+
--- a/net/netfilter/nf_tables_api.c
+++ b/net/netfilter/nf_tables_api.c
-@@ -8260,7 +8260,7 @@ static int nft_register_flowtable_net_ho
+@@ -8268,7 +8268,7 @@ static int nft_register_flowtable_net_ho
err = flowtable->data.type->setup(&flowtable->data,
hook->ops.dev,
FLOW_BLOCK_BIND);
if (!(p->flags & BR_BCAST_FLOOD) && skb->dev != br->dev)
--- a/net/bridge/br_input.c
+++ b/net/bridge/br_input.c
-@@ -362,6 +362,8 @@ static rx_handler_result_t br_handle_fra
+@@ -367,6 +367,8 @@ static rx_handler_result_t br_handle_fra
fwd_mask |= p->group_fwd_mask;
switch (dest[5]) {
case 0x00: /* Bridge Group Address */
--- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h
-@@ -2245,7 +2245,7 @@ struct net_device {
+@@ -2243,7 +2243,7 @@ struct net_device {
#if IS_ENABLED(CONFIG_AX25)
void *ax25_ptr;
#endif
/**
* napi_disable - prevent NAPI from scheduling
-@@ -3238,6 +3239,7 @@ struct softnet_data {
+@@ -3236,6 +3237,7 @@ struct softnet_data {
/* stats */
unsigned int processed;
unsigned int time_squeeze;
void netif_napi_add_weight(struct net_device *dev, struct napi_struct *napi,
int (*poll)(struct napi_struct *, int), int weight)
{
-@@ -11351,6 +11422,9 @@ static int dev_cpu_dead(unsigned int old
+@@ -11306,6 +11377,9 @@ static int dev_cpu_dead(unsigned int old
raise_softirq_irqoff(NET_TX_SOFTIRQ);
local_irq_enable();
#ifdef CONFIG_RPS
remsd = oldsd->rps_ipi_list;
oldsd->rps_ipi_list = NULL;
-@@ -11666,6 +11740,7 @@ static int __init net_dev_init(void)
+@@ -11621,6 +11695,7 @@ static int __init net_dev_init(void)
INIT_CSD(&sd->defer_csd, trigger_rx_softirq, sd);
spin_lock_init(&sd->defer_lock);
--- /dev/null
+From patchwork Sat Apr 27 11:24:42 2024
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 8bit
+X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTCB2aWEgQjQgUmVsYXk=?=
+ <devnull+arinc.unal.arinc9.com@kernel.org>
+X-Patchwork-Id: 13645655
+From: =?utf-8?b?QXLEsW7DpyDDnE5BTCB2aWEgQjQgUmVsYXk=?=
+ <devnull+arinc.unal.arinc9.com@kernel.org>
+Date: Sat, 27 Apr 2024 14:24:42 +0300
+Subject: [PATCH net-next] net: dsa: mt7530: do not set MT7530_P5_DIS when
+ PHY muxing is being used
+Precedence: bulk
+X-Mailing-List: netdev@vger.kernel.org
+List-Id: <netdev.vger.kernel.org>
+List-Subscribe: <mailto:netdev+subscribe@vger.kernel.org>
+List-Unsubscribe: <mailto:netdev+unsubscribe@vger.kernel.org>
+MIME-Version: 1.0
+Message-Id:
+ <20240427-for-netnext-mt7530-do-not-disable-port5-when-phy-muxing-v1-1-793cdf9d7707@arinc9.com>
+To: Daniel Golle <daniel@makrotopia.org>, DENG Qingfang <dqfext@gmail.com>,
+ Sean Wang <sean.wang@mediatek.com>, Andrew Lunn <andrew@lunn.ch>,
+ Florian Fainelli <f.fainelli@gmail.com>,
+ Vladimir Oltean <olteanv@gmail.com>,
+ "David S. Miller" <davem@davemloft.net>, Eric Dumazet <edumazet@google.com>,
+ Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
+ Matthias Brugger <matthias.bgg@gmail.com>,
+ AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
+ linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org,
+ =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= <arinc.unal@arinc9.com>
+X-Mailer: b4 0.13.0
+X-Patchwork-Delegate: kuba@kernel.org
+
+From: Arınç ÜNAL <arinc.unal@arinc9.com>
+
+When the PHY muxing feature is in use, port 5 won't be defined in the
+device tree. Because of this, the type member of the dsa_port structure for
+this port will be assigned DSA_PORT_TYPE_UNUSED. The dsa_port_setup()
+function calls ds->ops->port_disable() when the port type is
+DSA_PORT_TYPE_UNUSED.
+
+The MT7530_P5_DIS bit is unset when PHY muxing is being used.
+mt7530_port_disable() which is assigned to ds->ops->port_disable() is
+called afterwards. Currently, mt7530_port_disable() sets MT7530_P5_DIS
+which breaks network connectivity when PHY muxing is being used.
+
+Therefore, do not set MT7530_P5_DIS when PHY muxing is being used.
+
+Fixes: 377174c5760c ("net: dsa: mt7530: move MT753X_MTRAP operations for MT7530")
+Reported-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+---
+Hello.
+
+I've sent this to net-next as the patch it fixes is on the current
+development cycle.
+---
+ drivers/net/dsa/mt7530.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+
+---
+base-commit: 5c4c0edca68a5841a8d53ccd49596fe199c8334c
+change-id: 20240427-for-netnext-mt7530-do-not-disable-port5-when-phy-muxing-7ff5fd0995d7
+
+Best regards,
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -1220,7 +1220,7 @@ mt7530_port_disable(struct dsa_switch *d
+ if (priv->id != ID_MT7530 && priv->id != ID_MT7621)
+ return;
+
+- if (port == 5)
++ if (port == 5 && priv->p5_mode == GMAC5)
+ mt7530_set(priv, MT753X_MTRAP, MT7530_P5_DIS);
+ else if (port == 6)
+ mt7530_set(priv, MT753X_MTRAP, MT7530_P6_DIS);
+++ /dev/null
-From ef972fc9f5743da589ce9546dd565d6c56e679b8 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
-Date: Mon, 8 Apr 2024 10:08:53 +0300
-Subject: [PATCH 1/2] net: dsa: mt7530: fix enabling EEE on MT7531 switch on
- all boards
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The commit 40b5d2f15c09 ("net: dsa: mt7530: Add support for EEE features")
-brought EEE support but did not enable EEE on MT7531 switch MACs. EEE is
-enabled on MT7531 switch MACs by pulling the LAN2LED0 pin low on the board
-(bootstrapping), unsetting the EEE_DIS bit on the trap register, or setting
-the internal EEE switch bit on the CORE_PLL_GROUP4 register. Thanks to
-SkyLake Huang (黃啟澤) from MediaTek for providing information on the
-internal EEE switch bit.
-
-There are existing boards that were not designed to pull the pin low.
-Because of that, the EEE status currently depends on the board design.
-
-The EEE_DIS bit on the trap pertains to the LAN2LED0 pin which is usually
-used to control an LED. Once the bit is unset, the pin will be low. That
-will make the active low LED turn on. The pin is controlled by the switch
-PHY. It seems that the PHY controls the pin in the way that it inverts the
-pin state. That means depending on the wiring of the LED connected to
-LAN2LED0 on the board, the LED may be on without an active link.
-
-To not cause this unwanted behaviour whilst enabling EEE on all boards, set
-the internal EEE switch bit on the CORE_PLL_GROUP4 register.
-
-My testing on MT7531 shows a certain amount of traffic loss when EEE is
-enabled. That said, I haven't come across a board that enables EEE. So
-enable EEE on the switch MACs but disable EEE advertisement on the switch
-PHYs. This way, we don't change the behaviour of the majority of the boards
-that have this switch. The mediatek-ge PHY driver already disables EEE
-advertisement on the switch PHYs but my testing shows that it is somehow
-enabled afterwards. Disabling EEE advertisement before the PHY driver
-initialises keeps it off.
-
-With this change, EEE can now be enabled using ethtool.
-
-Fixes: 40b5d2f15c09 ("net: dsa: mt7530: Add support for EEE features")
-Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
-Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
----
- drivers/net/dsa/mt7530.c | 17 ++++++++++++-----
- drivers/net/dsa/mt7530.h | 1 +
- 2 files changed, 13 insertions(+), 5 deletions(-)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -2505,18 +2505,25 @@ mt7531_setup(struct dsa_switch *ds)
- mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
- MT7531_GPIO0_INTERRUPT);
-
-- /* Enable PHY core PLL, since phy_device has not yet been created
-- * provided for phy_[read,write]_mmd_indirect is called, we provide
-- * our own mt7531_ind_mmd_phy_[read,write] to complete this
-- * function.
-+ /* Enable Energy-Efficient Ethernet (EEE) and PHY core PLL, since
-+ * phy_device has not yet been created provided for
-+ * phy_[read,write]_mmd_indirect is called, we provide our own
-+ * mt7531_ind_mmd_phy_[read,write] to complete this function.
- */
- val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR,
- MDIO_MMD_VEND2, CORE_PLL_GROUP4);
-- val |= MT7531_PHY_PLL_BYPASS_MODE;
-+ val |= MT7531_RG_SYSPLL_DMY2 | MT7531_PHY_PLL_BYPASS_MODE;
- val &= ~MT7531_PHY_PLL_OFF;
- mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2,
- CORE_PLL_GROUP4, val);
-
-+ /* Disable EEE advertisement on the switch PHYs. */
-+ for (i = MT753X_CTRL_PHY_ADDR;
-+ i < MT753X_CTRL_PHY_ADDR + MT7530_NUM_PHYS; i++) {
-+ mt7531_ind_c45_phy_write(priv, i, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
-+ 0);
-+ }
-+
- mt7531_setup_common(ds);
-
- /* Setup VLAN ID 0 for VLAN-unaware bridges */
---- a/drivers/net/dsa/mt7530.h
-+++ b/drivers/net/dsa/mt7530.h
-@@ -616,6 +616,7 @@ enum mt7531_clk_skew {
- #define RG_SYSPLL_DDSFBK_EN BIT(12)
- #define RG_SYSPLL_BIAS_EN BIT(11)
- #define RG_SYSPLL_BIAS_LPF_EN BIT(10)
-+#define MT7531_RG_SYSPLL_DMY2 BIT(6)
- #define MT7531_PHY_PLL_OFF BIT(5)
- #define MT7531_PHY_PLL_BYPASS_MODE BIT(4)
-
+++ /dev/null
-From b7427d66cb3d6dca5165de5f7d80d59f08c2795b Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
-Date: Tue, 9 Apr 2024 18:01:14 +0300
-Subject: [PATCH 2/2] net: dsa: mt7530: trap link-local frames regardless of ST
- Port State
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-In Clause 5 of IEEE Std 802-2014, two sublayers of the data link layer
-(DLL) of the Open Systems Interconnection basic reference model (OSI/RM)
-are described; the medium access control (MAC) and logical link control
-(LLC) sublayers. The MAC sublayer is the one facing the physical layer.
-
-In 8.2 of IEEE Std 802.1Q-2022, the Bridge architecture is described. A
-Bridge component comprises a MAC Relay Entity for interconnecting the Ports
-of the Bridge, at least two Ports, and higher layer entities with at least
-a Spanning Tree Protocol Entity included.
-
-Each Bridge Port also functions as an end station and shall provide the MAC
-Service to an LLC Entity. Each instance of the MAC Service is provided to a
-distinct LLC Entity that supports protocol identification, multiplexing,
-and demultiplexing, for protocol data unit (PDU) transmission and reception
-by one or more higher layer entities.
-
-It is described in 8.13.9 of IEEE Std 802.1Q-2022 that in a Bridge, the LLC
-Entity associated with each Bridge Port is modeled as being directly
-connected to the attached Local Area Network (LAN).
-
-On the switch with CPU port architecture, CPU port functions as Management
-Port, and the Management Port functionality is provided by software which
-functions as an end station. Software is connected to an IEEE 802 LAN that
-is wholly contained within the system that incorporates the Bridge.
-Software provides access to the LLC Entity associated with each Bridge Port
-by the value of the source port field on the special tag on the frame
-received by software.
-
-We call frames that carry control information to determine the active
-topology and current extent of each Virtual Local Area Network (VLAN),
-i.e., spanning tree or Shortest Path Bridging (SPB) and Multiple VLAN
-Registration Protocol Data Units (MVRPDUs), and frames from other link
-constrained protocols, such as Extensible Authentication Protocol over LAN
-(EAPOL) and Link Layer Discovery Protocol (LLDP), link-local frames. They
-are not forwarded by a Bridge. Permanently configured entries in the
-filtering database (FDB) ensure that such frames are discarded by the
-Forwarding Process. In 8.6.3 of IEEE Std 802.1Q-2022, this is described in
-detail:
-
-Each of the reserved MAC addresses specified in Table 8-1
-(01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]) shall be
-permanently configured in the FDB in C-VLAN components and ERs.
-
-Each of the reserved MAC addresses specified in Table 8-2
-(01-80-C2-00-00-[01,02,03,04,05,06,07,08,09,0A,0E]) shall be permanently
-configured in the FDB in S-VLAN components.
-
-Each of the reserved MAC addresses specified in Table 8-3
-(01-80-C2-00-00-[01,02,04,0E]) shall be permanently configured in the FDB
-in TPMR components.
-
-The FDB entries for reserved MAC addresses shall specify filtering for all
-Bridge Ports and all VIDs. Management shall not provide the capability to
-modify or remove entries for reserved MAC addresses.
-
-The addresses in Table 8-1, Table 8-2, and Table 8-3 determine the scope of
-propagation of PDUs within a Bridged Network, as follows:
-
- The Nearest Bridge group address (01-80-C2-00-00-0E) is an address that
- no conformant Two-Port MAC Relay (TPMR) component, Service VLAN (S-VLAN)
- component, Customer VLAN (C-VLAN) component, or MAC Bridge can forward.
- PDUs transmitted using this destination address, or any other addresses
- that appear in Table 8-1, Table 8-2, and Table 8-3
- (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]), can
- therefore travel no further than those stations that can be reached via a
- single individual LAN from the originating station.
-
- The Nearest non-TPMR Bridge group address (01-80-C2-00-00-03), is an
- address that no conformant S-VLAN component, C-VLAN component, or MAC
- Bridge can forward; however, this address is relayed by a TPMR component.
- PDUs using this destination address, or any of the other addresses that
- appear in both Table 8-1 and Table 8-2 but not in Table 8-3
- (01-80-C2-00-00-[00,03,05,06,07,08,09,0A,0B,0C,0D,0F]), will be relayed
- by any TPMRs but will propagate no further than the nearest S-VLAN
- component, C-VLAN component, or MAC Bridge.
-
- The Nearest Customer Bridge group address (01-80-C2-00-00-00) is an
- address that no conformant C-VLAN component, MAC Bridge can forward;
- however, it is relayed by TPMR components and S-VLAN components. PDUs
- using this destination address, or any of the other addresses that appear
- in Table 8-1 but not in either Table 8-2 or Table 8-3
- (01-80-C2-00-00-[00,0B,0C,0D,0F]), will be relayed by TPMR components and
- S-VLAN components but will propagate no further than the nearest C-VLAN
- component or MAC Bridge.
-
-Because the LLC Entity associated with each Bridge Port is provided via CPU
-port, we must not filter these frames but forward them to CPU port.
-
-In a Bridge, the transmission Port is majorly decided by ingress and egress
-rules, FDB, and spanning tree Port State functions of the Forwarding
-Process. For link-local frames, only CPU port should be designated as
-destination port in the FDB, and the other functions of the Forwarding
-Process must not interfere with the decision of the transmission Port. We
-call this process trapping frames to CPU port.
-
-Therefore, on the switch with CPU port architecture, link-local frames must
-be trapped to CPU port, and certain link-local frames received by a Port of
-a Bridge comprising a TPMR component or an S-VLAN component must be
-excluded from it.
-
-A Bridge of the switch with CPU port architecture cannot comprise a
-Two-Port MAC Relay (TPMR) component as a TPMR component supports only a
-subset of the functionality of a MAC Bridge. A Bridge comprising two Ports
-(Management Port doesn't count) of this architecture will either function
-as a standard MAC Bridge or a standard VLAN Bridge.
-
-Therefore, a Bridge of this architecture can only comprise S-VLAN
-components, C-VLAN components, or MAC Bridge components. Since there's no
-TPMR component, we don't need to relay PDUs using the destination addresses
-specified on the Nearest non-TPMR section, and the proportion of the
-Nearest Customer Bridge section where they must be relayed by TPMR
-components.
-
-One option to trap link-local frames to CPU port is to add static FDB
-entries with CPU port designated as destination port. However, because that
-Independent VLAN Learning (IVL) is being used on every VID, each entry only
-applies to a single VLAN Identifier (VID). For a Bridge comprising a MAC
-Bridge component or a C-VLAN component, there would have to be 16 times
-4096 entries. This switch intellectual property can only hold a maximum of
-2048 entries. Using this option, there also isn't a mechanism to prevent
-link-local frames from being discarded when the spanning tree Port State of
-the reception Port is discarding.
-
-The remaining option is to utilise the BPC, RGAC1, RGAC2, RGAC3, and RGAC4
-registers. Whilst this applies to every VID, it doesn't contain all of the
-reserved MAC addresses without affecting the remaining Standard Group MAC
-Addresses. The REV_UN frame tag utilised using the RGAC4 register covers
-the remaining 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] destination
-addresses. It also includes the 01-80-C2-00-00-22 to 01-80-C2-00-00-FF
-destination addresses which may be relayed by MAC Bridges or VLAN Bridges.
-The latter option provides better but not complete conformance.
-
-This switch intellectual property also does not provide a mechanism to trap
-link-local frames with specific destination addresses to CPU port by
-Bridge, to conform to the filtering rules for the distinct Bridge
-components.
-
-Therefore, regardless of the type of the Bridge component, link-local
-frames with these destination addresses will be trapped to CPU port:
-
-01-80-C2-00-00-[00,01,02,03,0E]
-
-In a Bridge comprising a MAC Bridge component or a C-VLAN component:
-
- Link-local frames with these destination addresses won't be trapped to
- CPU port which won't conform to IEEE Std 802.1Q-2022:
-
- 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F]
-
-In a Bridge comprising an S-VLAN component:
-
- Link-local frames with these destination addresses will be trapped to CPU
- port which won't conform to IEEE Std 802.1Q-2022:
-
- 01-80-C2-00-00-00
-
- Link-local frames with these destination addresses won't be trapped to
- CPU port which won't conform to IEEE Std 802.1Q-2022:
-
- 01-80-C2-00-00-[04,05,06,07,08,09,0A]
-
-Currently on this switch intellectual property, if the spanning tree Port
-State of the reception Port is discarding, link-local frames will be
-discarded.
-
-To trap link-local frames regardless of the spanning tree Port State, make
-the switch regard them as Bridge Protocol Data Units (BPDUs). This switch
-intellectual property only lets the frames regarded as BPDUs bypass the
-spanning tree Port State function of the Forwarding Process.
-
-With this change, the only remaining interference is the ingress rules.
-When the reception Port has no PVID assigned on software, VLAN-untagged
-frames won't be allowed in. There doesn't seem to be a mechanism on the
-switch intellectual property to have link-local frames bypass this function
-of the Forwarding Process.
-
-Fixes: b8f126a8d543 ("net-next: dsa: add dsa support for Mediatek MT7530 switch")
-Reviewed-by: Daniel Golle <daniel@makrotopia.org>
-Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
----
- drivers/net/dsa/mt7530.c | 229 +++++++++++++++++++++++++++++++++------
- drivers/net/dsa/mt7530.h | 5 +
- 2 files changed, 200 insertions(+), 34 deletions(-)
-
---- a/drivers/net/dsa/mt7530.c
-+++ b/drivers/net/dsa/mt7530.c
-@@ -950,20 +950,173 @@ static void mt7530_setup_port5(struct ds
- mutex_unlock(&priv->reg_mutex);
- }
-
--/* On page 205, section "8.6.3 Frame filtering" of the active standard, IEEE Std
-- * 802.1Q™-2022, it is stated that frames with 01:80:C2:00:00:00-0F as MAC DA
-- * must only be propagated to C-VLAN and MAC Bridge components. That means
-- * VLAN-aware and VLAN-unaware bridges. On the switch designs with CPU ports,
-- * these frames are supposed to be processed by the CPU (software). So we make
-- * the switch only forward them to the CPU port. And if received from a CPU
-- * port, forward to a single port. The software is responsible of making the
-- * switch conform to the latter by setting a single port as destination port on
-- * the special tag.
-- *
-- * This switch intellectual property cannot conform to this part of the standard
-- * fully. Whilst the REV_UN frame tag covers the remaining :04-0D and :0F MAC
-- * DAs, it also includes :22-FF which the scope of propagation is not supposed
-- * to be restricted for these MAC DAs.
-+/* In Clause 5 of IEEE Std 802-2014, two sublayers of the data link layer (DLL)
-+ * of the Open Systems Interconnection basic reference model (OSI/RM) are
-+ * described; the medium access control (MAC) and logical link control (LLC)
-+ * sublayers. The MAC sublayer is the one facing the physical layer.
-+ *
-+ * In 8.2 of IEEE Std 802.1Q-2022, the Bridge architecture is described. A
-+ * Bridge component comprises a MAC Relay Entity for interconnecting the Ports
-+ * of the Bridge, at least two Ports, and higher layer entities with at least a
-+ * Spanning Tree Protocol Entity included.
-+ *
-+ * Each Bridge Port also functions as an end station and shall provide the MAC
-+ * Service to an LLC Entity. Each instance of the MAC Service is provided to a
-+ * distinct LLC Entity that supports protocol identification, multiplexing, and
-+ * demultiplexing, for protocol data unit (PDU) transmission and reception by
-+ * one or more higher layer entities.
-+ *
-+ * It is described in 8.13.9 of IEEE Std 802.1Q-2022 that in a Bridge, the LLC
-+ * Entity associated with each Bridge Port is modeled as being directly
-+ * connected to the attached Local Area Network (LAN).
-+ *
-+ * On the switch with CPU port architecture, CPU port functions as Management
-+ * Port, and the Management Port functionality is provided by software which
-+ * functions as an end station. Software is connected to an IEEE 802 LAN that is
-+ * wholly contained within the system that incorporates the Bridge. Software
-+ * provides access to the LLC Entity associated with each Bridge Port by the
-+ * value of the source port field on the special tag on the frame received by
-+ * software.
-+ *
-+ * We call frames that carry control information to determine the active
-+ * topology and current extent of each Virtual Local Area Network (VLAN), i.e.,
-+ * spanning tree or Shortest Path Bridging (SPB) and Multiple VLAN Registration
-+ * Protocol Data Units (MVRPDUs), and frames from other link constrained
-+ * protocols, such as Extensible Authentication Protocol over LAN (EAPOL) and
-+ * Link Layer Discovery Protocol (LLDP), link-local frames. They are not
-+ * forwarded by a Bridge. Permanently configured entries in the filtering
-+ * database (FDB) ensure that such frames are discarded by the Forwarding
-+ * Process. In 8.6.3 of IEEE Std 802.1Q-2022, this is described in detail:
-+ *
-+ * Each of the reserved MAC addresses specified in Table 8-1
-+ * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]) shall be
-+ * permanently configured in the FDB in C-VLAN components and ERs.
-+ *
-+ * Each of the reserved MAC addresses specified in Table 8-2
-+ * (01-80-C2-00-00-[01,02,03,04,05,06,07,08,09,0A,0E]) shall be permanently
-+ * configured in the FDB in S-VLAN components.
-+ *
-+ * Each of the reserved MAC addresses specified in Table 8-3
-+ * (01-80-C2-00-00-[01,02,04,0E]) shall be permanently configured in the FDB in
-+ * TPMR components.
-+ *
-+ * The FDB entries for reserved MAC addresses shall specify filtering for all
-+ * Bridge Ports and all VIDs. Management shall not provide the capability to
-+ * modify or remove entries for reserved MAC addresses.
-+ *
-+ * The addresses in Table 8-1, Table 8-2, and Table 8-3 determine the scope of
-+ * propagation of PDUs within a Bridged Network, as follows:
-+ *
-+ * The Nearest Bridge group address (01-80-C2-00-00-0E) is an address that no
-+ * conformant Two-Port MAC Relay (TPMR) component, Service VLAN (S-VLAN)
-+ * component, Customer VLAN (C-VLAN) component, or MAC Bridge can forward.
-+ * PDUs transmitted using this destination address, or any other addresses
-+ * that appear in Table 8-1, Table 8-2, and Table 8-3
-+ * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]), can
-+ * therefore travel no further than those stations that can be reached via a
-+ * single individual LAN from the originating station.
-+ *
-+ * The Nearest non-TPMR Bridge group address (01-80-C2-00-00-03), is an
-+ * address that no conformant S-VLAN component, C-VLAN component, or MAC
-+ * Bridge can forward; however, this address is relayed by a TPMR component.
-+ * PDUs using this destination address, or any of the other addresses that
-+ * appear in both Table 8-1 and Table 8-2 but not in Table 8-3
-+ * (01-80-C2-00-00-[00,03,05,06,07,08,09,0A,0B,0C,0D,0F]), will be relayed by
-+ * any TPMRs but will propagate no further than the nearest S-VLAN component,
-+ * C-VLAN component, or MAC Bridge.
-+ *
-+ * The Nearest Customer Bridge group address (01-80-C2-00-00-00) is an address
-+ * that no conformant C-VLAN component, MAC Bridge can forward; however, it is
-+ * relayed by TPMR components and S-VLAN components. PDUs using this
-+ * destination address, or any of the other addresses that appear in Table 8-1
-+ * but not in either Table 8-2 or Table 8-3 (01-80-C2-00-00-[00,0B,0C,0D,0F]),
-+ * will be relayed by TPMR components and S-VLAN components but will propagate
-+ * no further than the nearest C-VLAN component or MAC Bridge.
-+ *
-+ * Because the LLC Entity associated with each Bridge Port is provided via CPU
-+ * port, we must not filter these frames but forward them to CPU port.
-+ *
-+ * In a Bridge, the transmission Port is majorly decided by ingress and egress
-+ * rules, FDB, and spanning tree Port State functions of the Forwarding Process.
-+ * For link-local frames, only CPU port should be designated as destination port
-+ * in the FDB, and the other functions of the Forwarding Process must not
-+ * interfere with the decision of the transmission Port. We call this process
-+ * trapping frames to CPU port.
-+ *
-+ * Therefore, on the switch with CPU port architecture, link-local frames must
-+ * be trapped to CPU port, and certain link-local frames received by a Port of a
-+ * Bridge comprising a TPMR component or an S-VLAN component must be excluded
-+ * from it.
-+ *
-+ * A Bridge of the switch with CPU port architecture cannot comprise a Two-Port
-+ * MAC Relay (TPMR) component as a TPMR component supports only a subset of the
-+ * functionality of a MAC Bridge. A Bridge comprising two Ports (Management Port
-+ * doesn't count) of this architecture will either function as a standard MAC
-+ * Bridge or a standard VLAN Bridge.
-+ *
-+ * Therefore, a Bridge of this architecture can only comprise S-VLAN components,
-+ * C-VLAN components, or MAC Bridge components. Since there's no TPMR component,
-+ * we don't need to relay PDUs using the destination addresses specified on the
-+ * Nearest non-TPMR section, and the proportion of the Nearest Customer Bridge
-+ * section where they must be relayed by TPMR components.
-+ *
-+ * One option to trap link-local frames to CPU port is to add static FDB entries
-+ * with CPU port designated as destination port. However, because that
-+ * Independent VLAN Learning (IVL) is being used on every VID, each entry only
-+ * applies to a single VLAN Identifier (VID). For a Bridge comprising a MAC
-+ * Bridge component or a C-VLAN component, there would have to be 16 times 4096
-+ * entries. This switch intellectual property can only hold a maximum of 2048
-+ * entries. Using this option, there also isn't a mechanism to prevent
-+ * link-local frames from being discarded when the spanning tree Port State of
-+ * the reception Port is discarding.
-+ *
-+ * The remaining option is to utilise the BPC, RGAC1, RGAC2, RGAC3, and RGAC4
-+ * registers. Whilst this applies to every VID, it doesn't contain all of the
-+ * reserved MAC addresses without affecting the remaining Standard Group MAC
-+ * Addresses. The REV_UN frame tag utilised using the RGAC4 register covers the
-+ * remaining 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] destination
-+ * addresses. It also includes the 01-80-C2-00-00-22 to 01-80-C2-00-00-FF
-+ * destination addresses which may be relayed by MAC Bridges or VLAN Bridges.
-+ * The latter option provides better but not complete conformance.
-+ *
-+ * This switch intellectual property also does not provide a mechanism to trap
-+ * link-local frames with specific destination addresses to CPU port by Bridge,
-+ * to conform to the filtering rules for the distinct Bridge components.
-+ *
-+ * Therefore, regardless of the type of the Bridge component, link-local frames
-+ * with these destination addresses will be trapped to CPU port:
-+ *
-+ * 01-80-C2-00-00-[00,01,02,03,0E]
-+ *
-+ * In a Bridge comprising a MAC Bridge component or a C-VLAN component:
-+ *
-+ * Link-local frames with these destination addresses won't be trapped to CPU
-+ * port which won't conform to IEEE Std 802.1Q-2022:
-+ *
-+ * 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F]
-+ *
-+ * In a Bridge comprising an S-VLAN component:
-+ *
-+ * Link-local frames with these destination addresses will be trapped to CPU
-+ * port which won't conform to IEEE Std 802.1Q-2022:
-+ *
-+ * 01-80-C2-00-00-00
-+ *
-+ * Link-local frames with these destination addresses won't be trapped to CPU
-+ * port which won't conform to IEEE Std 802.1Q-2022:
-+ *
-+ * 01-80-C2-00-00-[04,05,06,07,08,09,0A]
-+ *
-+ * To trap link-local frames to CPU port as conformant as this switch
-+ * intellectual property can allow, link-local frames are made to be regarded as
-+ * Bridge Protocol Data Units (BPDUs). This is because this switch intellectual
-+ * property only lets the frames regarded as BPDUs bypass the spanning tree Port
-+ * State function of the Forwarding Process.
-+ *
-+ * The only remaining interference is the ingress rules. When the reception Port
-+ * has no PVID assigned on software, VLAN-untagged frames won't be allowed in.
-+ * There doesn't seem to be a mechanism on the switch intellectual property to
-+ * have link-local frames bypass this function of the Forwarding Process.
- */
- static void
- mt753x_trap_frames(struct mt7530_priv *priv)
-@@ -971,35 +1124,43 @@ mt753x_trap_frames(struct mt7530_priv *p
- /* Trap 802.1X PAE frames and BPDUs to the CPU port(s) and egress them
- * VLAN-untagged.
- */
-- mt7530_rmw(priv, MT753X_BPC, MT753X_PAE_EG_TAG_MASK |
-- MT753X_PAE_PORT_FW_MASK | MT753X_BPDU_EG_TAG_MASK |
-- MT753X_BPDU_PORT_FW_MASK,
-- MT753X_PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
-- MT753X_PAE_PORT_FW(MT753X_BPDU_CPU_ONLY) |
-- MT753X_BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
-- MT753X_BPDU_CPU_ONLY);
-+ mt7530_rmw(priv, MT753X_BPC,
-+ MT753X_PAE_BPDU_FR | MT753X_PAE_EG_TAG_MASK |
-+ MT753X_PAE_PORT_FW_MASK | MT753X_BPDU_EG_TAG_MASK |
-+ MT753X_BPDU_PORT_FW_MASK,
-+ MT753X_PAE_BPDU_FR |
-+ MT753X_PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
-+ MT753X_PAE_PORT_FW(MT753X_BPDU_CPU_ONLY) |
-+ MT753X_BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
-+ MT753X_BPDU_CPU_ONLY);
-
- /* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and egress
- * them VLAN-untagged.
- */
-- mt7530_rmw(priv, MT753X_RGAC1, MT753X_R02_EG_TAG_MASK |
-- MT753X_R02_PORT_FW_MASK | MT753X_R01_EG_TAG_MASK |
-- MT753X_R01_PORT_FW_MASK,
-- MT753X_R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
-- MT753X_R02_PORT_FW(MT753X_BPDU_CPU_ONLY) |
-- MT753X_R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
-- MT753X_BPDU_CPU_ONLY);
-+ mt7530_rmw(priv, MT753X_RGAC1,
-+ MT753X_R02_BPDU_FR | MT753X_R02_EG_TAG_MASK |
-+ MT753X_R02_PORT_FW_MASK | MT753X_R01_BPDU_FR |
-+ MT753X_R01_EG_TAG_MASK | MT753X_R01_PORT_FW_MASK,
-+ MT753X_R02_BPDU_FR |
-+ MT753X_R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
-+ MT753X_R02_PORT_FW(MT753X_BPDU_CPU_ONLY) |
-+ MT753X_R01_BPDU_FR |
-+ MT753X_R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
-+ MT753X_BPDU_CPU_ONLY);
-
- /* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and egress
- * them VLAN-untagged.
- */
-- mt7530_rmw(priv, MT753X_RGAC2, MT753X_R0E_EG_TAG_MASK |
-- MT753X_R0E_PORT_FW_MASK | MT753X_R03_EG_TAG_MASK |
-- MT753X_R03_PORT_FW_MASK,
-- MT753X_R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
-- MT753X_R0E_PORT_FW(MT753X_BPDU_CPU_ONLY) |
-- MT753X_R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
-- MT753X_BPDU_CPU_ONLY);
-+ mt7530_rmw(priv, MT753X_RGAC2,
-+ MT753X_R0E_BPDU_FR | MT753X_R0E_EG_TAG_MASK |
-+ MT753X_R0E_PORT_FW_MASK | MT753X_R03_BPDU_FR |
-+ MT753X_R03_EG_TAG_MASK | MT753X_R03_PORT_FW_MASK,
-+ MT753X_R0E_BPDU_FR |
-+ MT753X_R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
-+ MT753X_R0E_PORT_FW(MT753X_BPDU_CPU_ONLY) |
-+ MT753X_R03_BPDU_FR |
-+ MT753X_R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
-+ MT753X_BPDU_CPU_ONLY);
- }
-
- static void
---- a/drivers/net/dsa/mt7530.h
-+++ b/drivers/net/dsa/mt7530.h
-@@ -65,6 +65,7 @@ enum mt753x_id {
-
- /* Registers for BPDU and PAE frame control*/
- #define MT753X_BPC 0x24
-+#define MT753X_PAE_BPDU_FR BIT(25)
- #define MT753X_PAE_EG_TAG_MASK GENMASK(24, 22)
- #define MT753X_PAE_EG_TAG(x) FIELD_PREP(MT753X_PAE_EG_TAG_MASK, x)
- #define MT753X_PAE_PORT_FW_MASK GENMASK(18, 16)
-@@ -75,20 +76,24 @@ enum mt753x_id {
-
- /* Register for :01 and :02 MAC DA frame control */
- #define MT753X_RGAC1 0x28
-+#define MT753X_R02_BPDU_FR BIT(25)
- #define MT753X_R02_EG_TAG_MASK GENMASK(24, 22)
- #define MT753X_R02_EG_TAG(x) FIELD_PREP(MT753X_R02_EG_TAG_MASK, x)
- #define MT753X_R02_PORT_FW_MASK GENMASK(18, 16)
- #define MT753X_R02_PORT_FW(x) FIELD_PREP(MT753X_R02_PORT_FW_MASK, x)
-+#define MT753X_R01_BPDU_FR BIT(9)
- #define MT753X_R01_EG_TAG_MASK GENMASK(8, 6)
- #define MT753X_R01_EG_TAG(x) FIELD_PREP(MT753X_R01_EG_TAG_MASK, x)
- #define MT753X_R01_PORT_FW_MASK GENMASK(2, 0)
-
- /* Register for :03 and :0E MAC DA frame control */
- #define MT753X_RGAC2 0x2c
-+#define MT753X_R0E_BPDU_FR BIT(25)
- #define MT753X_R0E_EG_TAG_MASK GENMASK(24, 22)
- #define MT753X_R0E_EG_TAG(x) FIELD_PREP(MT753X_R0E_EG_TAG_MASK, x)
- #define MT753X_R0E_PORT_FW_MASK GENMASK(18, 16)
- #define MT753X_R0E_PORT_FW(x) FIELD_PREP(MT753X_R0E_PORT_FW_MASK, x)
-+#define MT753X_R03_BPDU_FR BIT(9)
- #define MT753X_R03_EG_TAG_MASK GENMASK(8, 6)
- #define MT753X_R03_EG_TAG(x) FIELD_PREP(MT753X_R03_EG_TAG_MASK, x)
- #define MT753X_R03_PORT_FW_MASK GENMASK(2, 0)
#endif /* __LINUX_USB_PCI_QUIRKS_H */
--- a/include/linux/usb/hcd.h
+++ b/include/linux/usb/hcd.h
-@@ -484,7 +484,14 @@ extern int usb_hcd_pci_probe(struct pci_
+@@ -485,7 +485,14 @@ extern int usb_hcd_pci_probe(struct pci_
extern void usb_hcd_pci_remove(struct pci_dev *dev);
extern void usb_hcd_pci_shutdown(struct pci_dev *dev);
/*
* We need to store the untouched command line for future reference.
* We also need to store the touched command line since the parameter
-@@ -896,6 +919,7 @@ void start_kernel(void)
+@@ -898,6 +921,7 @@ void start_kernel(void)
pr_notice("%s", linux_banner);
early_security_init();
setup_arch(&command_line);
CPU_SUBTYPE:=neon-vfpv4
SUBTARGETS:=generic chromium mikrotik
-KERNEL_PATCHVER:=6.1
-KERNEL_TESTING_PATCHVER:=6.6
+KERNEL_PATCHVER:=6.6
KERNELNAME:=zImage Image dtbs
+++ /dev/null
-CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_APQ_GCC_8084 is not set
-# CONFIG_APQ_MMCC_8084 is not set
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_IPQ40XX=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-# CONFIG_ARCH_MDM9615 is not set
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-# CONFIG_ARCH_MSM8909 is not set
-# CONFIG_ARCH_MSM8916 is not set
-# CONFIG_ARCH_MSM8960 is not set
-# CONFIG_ARCH_MSM8974 is not set
-# CONFIG_ARCH_MSM8X60 is not set
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_QCOM=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-# CONFIG_ARM_ATAG_DTB_COMPAT is not set
-CONFIG_ARM_CPUIDLE=y
-# CONFIG_ARM_CPU_TOPOLOGY is not set
-CONFIG_ARM_GIC=y
-CONFIG_ARM_HAS_GROUP_RELOCS=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-CONFIG_ARM_PATCH_IDIV=y
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-# CONFIG_ARM_QCOM_CPUFREQ_HW is not set
-# CONFIG_ARM_QCOM_CPUFREQ_NVMEM is not set
-# CONFIG_ARM_QCOM_SPM_CPUIDLE is not set
-# CONFIG_ARM_SMMU is not set
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_AT803X_PHY=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BCH=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BOUNCE=y
-# CONFIG_CACHE_L2X0 is not set
-CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_CC_NO_ARRAY_BOUNDS=y
-CONFIG_CLKSRC_QCOM=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE_PARTITION=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_QCOM=y
-CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONTEXT_TRACKING=y
-CONFIG_CONTEXT_TRACKING_IDLE=y
-CONFIG_CPUFREQ_DT=y
-CONFIG_CPUFREQ_DT_PLATDEV=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_FREQ=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_SPECTRE=y
-CONFIG_CPU_THERMAL=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRC16=y
-# CONFIG_CRC32_SARWATE is not set
-CONFIG_CRC32_SLICEBY8=y
-CONFIG_CRC8=y
-CONFIG_CRYPTO_AES_ARM=y
-CONFIG_CRYPTO_AES_ARM_BS=y
-CONFIG_CRYPTO_ARCH_HAVE_LIB_BLAKE2S=y
-CONFIG_CRYPTO_BLAKE2S_ARM=y
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_CRYPTD=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_DES=y
-CONFIG_CRYPTO_DEV_QCE=y
-# CONFIG_CRYPTO_DEV_QCE_ENABLE_AEAD is not set
-# CONFIG_CRYPTO_DEV_QCE_ENABLE_ALL is not set
-# CONFIG_CRYPTO_DEV_QCE_ENABLE_SHA is not set
-CONFIG_CRYPTO_DEV_QCE_ENABLE_SKCIPHER=y
-CONFIG_CRYPTO_DEV_QCE_SKCIPHER=y
-CONFIG_CRYPTO_DEV_QCE_SW_MAX_LEN=512
-CONFIG_CRYPTO_DEV_QCOM_RNG=y
-CONFIG_CRYPTO_DRBG=y
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_MENU=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_JITTERENTROPY=y
-CONFIG_CRYPTO_LIB_DES=y
-CONFIG_CRYPTO_LIB_SHA1=y
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_LIB_UTILS=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=y
-CONFIG_CRYPTO_SEQIV=y
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA256_ARM=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_SIMD=y
-CONFIG_CRYPTO_XTS=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-CONFIG_DEBUG_MISC=y
-CONFIG_DMADEVICES=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_OPS=y
-CONFIG_DMA_SHARED_BUFFER=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DTC=y
-CONFIG_DT_IDLE_STATES=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EEPROM_AT24=y
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-CONFIG_EXTCON=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GENERIC_VDSO_32=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_74X164=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_WATCHDOG=y
-CONFIG_GPIO_WATCHDOG_ARCH_INITCALL=y
-CONFIG_GRO_CELLS=y
-CONFIG_HARDEN_BRANCH_PREDICTOR=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAVE_SMP=y
-CONFIG_HIGHMEM=y
-# CONFIG_HIGHPTE is not set
-CONFIG_HWSPINLOCK=y
-CONFIG_HWSPINLOCK_QCOM=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_OPTEE=y
-CONFIG_HZ_FIXED=0
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_HELPER_AUTO=y
-# CONFIG_I2C_QCOM_CCI is not set
-CONFIG_I2C_QUP=y
-CONFIG_INITRAMFS_SOURCE=""
-# CONFIG_IOMMU_DEBUGFS is not set
-# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
-# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
-CONFIG_IOMMU_SUPPORT=y
-# CONFIG_IPQ_APSS_PLL is not set
-CONFIG_IPQ_GCC_4019=y
-# CONFIG_IPQ_GCC_6018 is not set
-# CONFIG_IPQ_GCC_806X is not set
-# CONFIG_IPQ_GCC_8074 is not set
-# CONFIG_IPQ_LCC_806X is not set
-CONFIG_IRQCHIP=y
-CONFIG_IRQSTACKS=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_KMAP_LOCAL=y
-CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
-# CONFIG_KPSS_XCC is not set
-# CONFIG_KRAITCC is not set
-CONFIG_LED_TRIGGER_PHY=y
-CONFIG_LEDS_LP5523=y
-CONFIG_LEDS_LP5562=y
-CONFIG_LEDS_LP55XX_COMMON=y
-CONFIG_LEDS_TLC591XX=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MDIO_BITBANG=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MDIO_GPIO=y
-CONFIG_MDIO_IPQ4019=y
-# CONFIG_MDM_GCC_9615 is not set
-# CONFIG_MDM_LCC_9615 is not set
-CONFIG_MEMFD_CREATE=y
-# CONFIG_MFD_HI6421_SPMI is not set
-# CONFIG_MFD_QCOM_RPM is not set
-# CONFIG_MFD_SPMI_PMIC is not set
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_CQHCI=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_IO_ACCESSORS=y
-CONFIG_MMC_SDHCI_MSM=y
-# CONFIG_MMC_SDHCI_PCI is not set
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MODULES_USE_ELF_REL=y
-# CONFIG_MSM_GCC_8660 is not set
-# CONFIG_MSM_GCC_8909 is not set
-# CONFIG_MSM_GCC_8916 is not set
-# CONFIG_MSM_GCC_8939 is not set
-# CONFIG_MSM_GCC_8960 is not set
-# CONFIG_MSM_GCC_8974 is not set
-# CONFIG_MSM_GCC_8976 is not set
-# CONFIG_MSM_GCC_8994 is not set
-# CONFIG_MSM_GCC_8996 is not set
-# CONFIG_MSM_GCC_8998 is not set
-# CONFIG_MSM_GPUCC_8998 is not set
-# CONFIG_MSM_LCC_8960 is not set
-# CONFIG_MSM_MMCC_8960 is not set
-# CONFIG_MSM_MMCC_8974 is not set
-# CONFIG_MSM_MMCC_8996 is not set
-# CONFIG_MSM_MMCC_8998 is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_ECC_SW_BCH=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
-CONFIG_MTD_NAND_QCOM=y
-# CONFIG_MTD_QCOMSMEM_PARTS is not set
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_SPI_NAND=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_FIT_FW=y
-CONFIG_MTD_SPLIT_WRGG_FW=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEON=y
-CONFIG_NET_DEVLINK=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_QCA8K_IPQ4019=y
-CONFIG_NET_DSA_TAG_OOB=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NLS=y
-CONFIG_NO_HZ=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=4
-CONFIG_NVMEM=y
-CONFIG_NVMEM_QCOM_QFPROM=y
-# CONFIG_NVMEM_QCOM_SEC_QFPROM is not set
-# CONFIG_NVMEM_SPMI_SDAM is not set
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_OPTEE=y
-CONFIG_PADATA=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_DW=y
-CONFIG_PCIE_DW_HOST=y
-CONFIG_PCIE_QCOM=y
-CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-# CONFIG_PHY_QCOM_APQ8064_SATA is not set
-# CONFIG_PHY_QCOM_EDP is not set
-CONFIG_PHY_QCOM_IPQ4019_USB=y
-# CONFIG_PHY_QCOM_IPQ806X_SATA is not set
-# CONFIG_PHY_QCOM_IPQ806X_USB is not set
-# CONFIG_PHY_QCOM_PCIE2 is not set
-# CONFIG_PHY_QCOM_QMP is not set
-# CONFIG_PHY_QCOM_QUSB2 is not set
-# CONFIG_PHY_QCOM_USB_HS_28NM is not set
-# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set
-# CONFIG_PHY_QCOM_USB_SS is not set
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_APQ8064 is not set
-# CONFIG_PINCTRL_APQ8084 is not set
-CONFIG_PINCTRL_IPQ4019=y
-# CONFIG_PINCTRL_IPQ8064 is not set
-# CONFIG_PINCTRL_MDM9615 is not set
-CONFIG_PINCTRL_MSM=y
-# CONFIG_PINCTRL_MSM8226 is not set
-# CONFIG_PINCTRL_MSM8660 is not set
-# CONFIG_PINCTRL_MSM8909 is not set
-# CONFIG_PINCTRL_MSM8916 is not set
-# CONFIG_PINCTRL_MSM8960 is not set
-# CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set
-# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set
-# CONFIG_PINCTRL_SDX65 is not set
-CONFIG_PM_OPP=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_GPIO_RESTART=y
-CONFIG_POWER_RESET_MSM=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PPS=y
-CONFIG_PREEMPT_NONE_BUILD=y
-CONFIG_PRINTK_TIME=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_QCA807X_PHY=y
-# CONFIG_QCM_DISPCC_2290 is not set
-# CONFIG_QCM_GCC_2290 is not set
-CONFIG_QCOM_A53PLL=y
-# CONFIG_QCOM_ADM is not set
-CONFIG_QCOM_BAM_DMA=y
-# CONFIG_QCOM_COMMAND_DB is not set
-# CONFIG_QCOM_CPR is not set
-# CONFIG_QCOM_EBI2 is not set
-# CONFIG_QCOM_GENI_SE is not set
-# CONFIG_QCOM_GSBI is not set
-# CONFIG_QCOM_HFPLL is not set
-# CONFIG_QCOM_ICC_BWMON is not set
-# CONFIG_QCOM_IOMMU is not set
-CONFIG_QCOM_IPQ4019_ESS_EDMA=y
-# CONFIG_QCOM_LLCC is not set
-# CONFIG_QCOM_OCMEM is not set
-# CONFIG_QCOM_PDC is not set
-# CONFIG_QCOM_RMTFS_MEM is not set
-# CONFIG_QCOM_RPMH is not set
-CONFIG_QCOM_SCM=y
-# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set
-CONFIG_QCOM_SMEM=y
-# CONFIG_QCOM_SMSM is not set
-# CONFIG_QCOM_SOCINFO is not set
-# CONFIG_QCOM_SPM is not set
-# CONFIG_QCOM_STATS is not set
-CONFIG_QCOM_TCSR=y
-# CONFIG_QCOM_TSENS is not set
-CONFIG_QCOM_WDT=y
-# CONFIG_QCS_GCC_404 is not set
-# CONFIG_QCS_Q6SSTOP_404 is not set
-# CONFIG_QCS_TURING_404 is not set
-CONFIG_RANDSTRUCT_NONE=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-# CONFIG_REGULATOR_QCOM_LABIBB is not set
-# CONFIG_REGULATOR_QCOM_SPMI is not set
-# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
-CONFIG_REGULATOR_VCTRL=y
-CONFIG_REGULATOR_VQMMC_IPQ4019=y
-CONFIG_RESET_CONTROLLER=y
-# CONFIG_RESET_QCOM_AOSS is not set
-# CONFIG_RESET_QCOM_PDC is not set
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-# CONFIG_RTC_DRV_OPTEE is not set
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RTC_MC146818_LIB=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-# CONFIG_SC_CAMCC_7280 is not set
-# CONFIG_SC_DISPCC_7180 is not set
-# CONFIG_SC_GCC_7180 is not set
-# CONFIG_SC_GCC_8280XP is not set
-# CONFIG_SC_GPUCC_7180 is not set
-# CONFIG_SC_LPASSCC_7280 is not set
-# CONFIG_SC_LPASS_CORECC_7180 is not set
-# CONFIG_SC_LPASS_CORECC_7280 is not set
-# CONFIG_SC_MSS_7180 is not set
-# CONFIG_SC_VIDEOCC_7180 is not set
-# CONFIG_SDM_CAMCC_845 is not set
-# CONFIG_SDM_DISPCC_845 is not set
-# CONFIG_SDM_GCC_660 is not set
-# CONFIG_SDM_GCC_845 is not set
-# CONFIG_SDM_GPUCC_845 is not set
-# CONFIG_SDM_LPASSCC_845 is not set
-# CONFIG_SDM_VIDEOCC_845 is not set
-# CONFIG_SDX_GCC_65 is not set
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_MSM=y
-CONFIG_SERIAL_MSM_CONSOLE=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SKB_EXTENSIONS=y
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-# CONFIG_SM_CAMCC_8450 is not set
-# CONFIG_SM_GCC_8150 is not set
-# CONFIG_SM_GCC_8250 is not set
-# CONFIG_SM_GCC_8450 is not set
-# CONFIG_SM_GPUCC_6350 is not set
-# CONFIG_SM_GPUCC_8150 is not set
-# CONFIG_SM_GPUCC_8250 is not set
-# CONFIG_SM_GPUCC_8350 is not set
-# CONFIG_SM_VIDEOCC_8150 is not set
-# CONFIG_SM_VIDEOCC_8250 is not set
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SOFTIRQ_ON_OWN_STACK=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_BITBANG=y
-CONFIG_SPI_GPIO=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_QUP=y
-CONFIG_SPMI=y
-# CONFIG_SPMI_HISI3670 is not set
-CONFIG_SPMI_MSM_PMIC_ARB=y
-# CONFIG_SPMI_PMIC_CLKDIV is not set
-CONFIG_SRCU=y
-CONFIG_SWPHY=y
-CONFIG_SWP_EMULATE=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_TEE=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_OF=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UBIFS_FS=y
-CONFIG_UEVENT_HELPER_PATH=""
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZSTD_COMMON=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
+++ /dev/null
-// SPDX-License-Identifier: ISC
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
- * Copyright (c) 2017, Sven Eckelmann <sven.eckelmann@openmesh.com>
- */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "OpenMesh A42";
- compatible = "openmesh,a42";
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- tcsr@194b000 {
- /* select hostmode */
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2: usb2@60f8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- aliases {
- led-boot = &led_status_green;
- led-failsafe = &led_status_green;
- led-running = &led_status_green;
- led-upgrade = &led_status_green;
- label-mac-device = &swport5;
- };
-
- leds {
- compatible = "gpio-leds";
-
- status_red {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_RED>;
- gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
- };
-
- led_status_green: status_green {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
- };
-
- status_blue {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
- };
- };
-
- watchdog {
- compatible = "linux,wdt-gpio";
- gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
- hw_algo = "toggle";
- /* hw_margin_ms is actually 300s but driver limits it to 60s */
- hw_margin_ms = <60000>;
- always-running;
- };
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pin {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
- pin_cs {
- function = "gpio";
- pins = "gpio54";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- /* partitions are passed via bootloader */
- partitions {
- partition-art {
- label = "0:ART";
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_gmac0: macaddr@0 {
- reg = <0x0 0x6>;
- };
-
- macaddr_gmac1: macaddr@6 {
- reg = <0x6 0x6>;
- };
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&mdio {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
- label = "ethernet2";
-
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_gmac1>;
-};
-
-&swport5 {
- status = "okay";
- label = "ethernet1";
-
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_gmac0>;
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "OM-A42";
-
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "OM-A42";
-
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "ALFA Network AP120C-AC";
- compatible = "alfa-network,ap120c-ac";
-
- aliases {
- led-boot = &status;
- led-failsafe = &status;
- led-running = &status;
- led-upgrade = &status;
- ethernet1 = &swport5;
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- status: status {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
- default-state = "keep";
- };
-
- wan {
- function = LED_FUNCTION_WAN;
- color = <LED_COLOR_ID_AMBER>;
- gpios = <ðphy4 1 GPIO_ACTIVE_HIGH>;
- };
-
- wlan2g {
- label = "green:wlan2g";
- gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy0tpt";
- };
-
- wlan5g {
- label = "red:wlan5g";
- gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy1tpt";
- };
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
-
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- };
-
- counter@4a1000 {
- compatible = "qcom,qca-gcnt";
- reg = <0x4a1000 0x4>;
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2@60f8800 {
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
-
- dwc3@8a00000 {
- phys = <&usb3_hs_phy>;
- phy-names = "usb2-phy";
- };
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_i2c3 {
- status = "okay";
-
- pinctrl-0 = <&i2c0_pins>;
- pinctrl-names = "default";
-
- tpm@29 {
- compatible = "atmel,at97sc3204t";
- reg = <0x29>;
- };
-};
-
-&blsp1_spi1 {
- status = "okay";
-
- pinctrl-0 = <&spi0_pins>;
- pinctrl-names = "default";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,
- <&tlmm 4 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SBL1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
-
- partition@40000 {
- label = "MIBIB";
- reg = <0x00040000 0x00020000>;
- read-only;
- };
-
- partition@60000 {
- label = "QSEE";
- reg = <0x00060000 0x00060000>;
- read-only;
- };
-
- partition@c0000 {
- label = "CDT";
- reg = <0x000c0000 0x00010000>;
- read-only;
- };
-
- partition@d0000 {
- label = "DDRPARAMS";
- reg = <0x000d0000 0x00010000>;
- read-only;
- };
-
- partition@e0000 {
- label = "APPSBLENV";
- reg = <0x000e0000 0x00010000>;
- };
-
- partition@f0000 {
- label = "APPSBL";
- reg = <0x000f0000 0x00080000>;
- read-only;
- };
-
- partition@170000 {
- label = "ART";
- reg = <0x00170000 0x00010000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- partition@180000 {
- label = "priv_data1";
- reg = <0x00180000 0x00010000>;
- read-only;
- };
-
- partition@190000 {
- label = "priv_data2";
- reg = <0x00190000 0x00010000>;
- read-only;
- };
- };
- };
-
- nand@1 {
- compatible = "spi-nand";
- reg = <1>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "rootfs1";
- reg = <0x00000000 0x04000000>;
- };
-
- partition@4000000 {
- label = "rootfs2";
- reg = <0x04000000 0x04000000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- status = "okay";
-
- pinctrl-0 = <&serial0_pins>;
- pinctrl-names = "default";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-ðphy4 {
- gpio-controller;
- #gpio-cells = <2>;
-};
-
-&tlmm {
- i2c0_pins: i2c0_pinmux {
- mux_i2c {
- function = "blsp_i2c0";
- pins = "gpio58", "gpio59";
- drive-strength = <16>;
- bias-disable;
- };
- };
-
- mdio_pins: mdio_pinmux {
- mux_mdio {
- pins = "gpio53";
- function = "mdio";
- bias-pull-up;
- };
-
- mux_mdc {
- pins = "gpio52";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- serial0_pins: serial0_pinmux {
- mux_uart {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi0_pins: spi0_pinmux {
- mux_spi {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
-
- mux_cs {
- function = "gpio";
- pins = "gpio54", "gpio4";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
-
- label = "lan";
-};
-
-&swport5 {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "ALFA-Network-AP120C-AC";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/* Copyright (c) 2020, Robert Marko <robimarko@gmail.com> */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "MikroTik cAP ac";
- compatible = "mikrotik,cap-ac";
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x08000000>;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- aliases {
- led-boot = &led_user;
- led-failsafe = &led_user;
- led-running = &led_user;
- led-upgrade = &led_user;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- counter@4a1000 {
- compatible = "qcom,qca-gcnt";
- reg = <0x4a1000 0x4>;
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
-
- mode {
- label = "mode";
- gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_LIGHTS_TOGGLE>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
- default-state = "keep";
- };
-
- led_user: user {
- label = "green:user";
- gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
- panic-indicator;
- };
-
- wlan2g {
- label = "green:wlan2g";
- gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
- };
-
- wlan5g {
- label = "green:wlan5g";
- gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;
- };
-
- eth1 {
- label = "green:eth1";
- gpios = <ðphy4 1 GPIO_ACTIVE_HIGH>;
- };
-
- eth2 {
- label = "green:eth2";
- gpios = <ðphy3 1 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pin {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <2>;
- bias-disable;
- };
- pin_cs {
- function = "gpio";
- pins = "gpio54";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- status = "okay";
-
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- reg = <0>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <40000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "Qualcomm";
- reg = <0x0 0x80000>;
- read-only;
- };
-
- partition@80000 {
- compatible = "mikrotik,routerboot-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
- label = "RouterBoot";
- reg = <0x80000 0x80000>;
-
- hard_config {
- read-only;
- };
-
- dtb_config {
- read-only;
- };
-
- soft_config {
- };
- };
-
- partition@100000 {
- compatible = "mikrotik,minor";
- label = "firmware";
- reg = <0x100000 0xf00000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- status = "okay";
-
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&mdio {
- status = "okay";
-};
-
-ðphy3 {
- gpio-controller;
- #gpio-cells = <2>;
-};
-
-ðphy4 {
- gpio-controller;
- #gpio-cells = <2>;
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
-
- label = "lan";
-};
-
-&swport5 {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
-
- qcom,ath10k-calibration-variant = "MikroTik-cAP-ac";
-};
-
-&wifi1 {
- status = "okay";
-
- qcom,ath10k-calibration-variant = "MikroTik-cAP-ac";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "EZVIZ CS-W3-WD1200G EUP";
- compatible = "ezviz,cs-w3-wd1200g-eup";
-
- aliases {
- led-boot = &led_status_green;
- led-failsafe = &led_status_red;
- led-running = &led_status_blue;
- led-upgrade = &led_status_green;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- reset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
- reset-delay-us = <5000>;
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_status_red: status_red {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_RED>;
- gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
- };
-
- led_status_green: status_green {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
- };
-
- led_status_blue: status_blue {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio53";
- function = "mdio";
- bias-pull-up;
- };
-
- mux_2 {
- pins = "gpio52";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pin {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
- pin_cs {
- function = "gpio";
- pins = "gpio54";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition0@0 {
- label = "SBL1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
-
- partition1@40000 {
- label = "MIBIB";
- reg = <0x00040000 0x00020000>;
- read-only;
- };
-
- partition2@60000 {
- label = "QSEE";
- reg = <0x00060000 0x00060000>;
- read-only;
- };
-
- partition3@c0000 {
- label = "CDT";
- reg = <0x000c0000 0x00010000>;
- read-only;
- };
-
- partition4@d0000 {
- label = "DDRPARAMS";
- reg = <0x000d0000 0x00010000>;
- read-only;
- };
-
- partition5@E0000 {
- label = "APPSBLENV";
- reg = <0x000e0000 0x00010000>;
- read-only;
- };
-
- partition6@F0000 {
- label = "APPSBL";
- reg = <0x000f0000 0x00080000>;
- read-only;
- };
-
- partition7@170000 {
- label = "ART";
- reg = <0x00170000 0x00010000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_art_0: macaddr@0 {
- reg = <0x0 0x6>;
- };
-
- macaddr_art_6: macaddr@6 {
- reg = <0x6 0x6>;
- };
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- partition9@580000 {
- compatible = "denx,fit";
- label = "firmware";
- reg = <0x00180000 0x00e80000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
- nvmem-cells = <&macaddr_art_0>;
- nvmem-cell-names = "mac-address";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport2 {
- status = "okay";
- label = "lan3";
-};
-
-&swport3 {
- status = "okay";
- label = "lan2";
-};
-
-&swport4 {
- status = "okay";
- label = "lan1";
-};
-
-&swport5 {
- status = "okay";
- label = "wan";
- nvmem-cells = <&macaddr_art_6>;
- nvmem-cell-names = "mac-address";
-};
-
-ðphy0 {
- status = "disabled";
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "ezviz-cs-w3-wd1200g-eup";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "ezviz-cs-w3-wd1200g-eup";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "D-Link DAP 2610";
- compatible = "dlink,dap-2610";
-
- aliases {
- led-boot = &led_red;
- led-failsafe = &led_red;
- led-running = &led_green;
- led-upgrade = &led_red;
- };
-
- soc {
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- rng@22000 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_red: red {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_RED>;
- gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
- };
-
- led_green: green {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "fixed-partitions";
-
- partition@0 {
- label = "SBL1";
- reg = <0x0 0x40000>;
- read-only;
- };
- partition@40000 {
- label = "MIBIB";
- reg = <0x40000 0x20000>;
- read-only;
- };
- partition@60000 {
- label = "QSEE";
- reg = <0x60000 0x60000>;
- read-only;
- };
- partition@c0000 {
- label = "CDT";
- reg = <0xc0000 0x10000>;
- read-only;
- };
- partition@d0000 {
- label = "DDRPARAMS";
- reg = <0xd0000 0x10000>;
- read-only;
- };
- partition@e0000 {
- label = "APPSBLENV";
- reg = <0xe0000 0x10000>;
- read-only;
- };
- partition@f0000 {
- label = "APPSBL";
- reg = <0xf0000 0x80000>;
- read-only;
- };
- partition@170000 {
- label = "ART";
- reg = <0x170000 0x10000>;
- read-only;
- };
- partition@180000 {
- compatible = "wrg";
- label = "firmware";
- reg = <0x180000 0xdc0000>;
- };
- partition@fb0000 {
- label = "rgbd";
- reg = <0xfb0000 0x10000>;
- read-only;
- };
- partition@fc0000 {
- label = "bdcfg";
- reg = <0xfc0000 0x10000>;
- read-only;
- };
- partition@fd0000 {
- label = "langpack";
- reg = <0xfd0000 0x20000>;
- read-only;
- };
- partition@ff0000 {
- label = "certificate";
- reg = <0xff0000 0x10000>;
- read-only;
- };
- partition@f40000 {
- label = "captival";
- reg = <0xf40000 0x70000>;
- read-only;
- };
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&mdio {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport5 {
- status = "okay";
-
- label = "lan";
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- mux {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
- mux_cs {
- function = "gpio";
- pins = "gpio54";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "dlink,dap-2610";
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "dlink,dap-2610";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "Linksys EA6350v3";
- compatible = "linksys,ea6350v3";
-
- aliases {
- led-boot = &power;
- led-failsafe = &power;
- led-running = &power;
- led-upgrade = &power;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2@60f8800 {
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
-
- wps {
- label = "wps";
- gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- power: status {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport1 {
- status = "okay";
-};
-
-&swport2 {
- status = "okay";
-};
-
-&swport3 {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
-};
-
-&swport5 {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
- qcom,ath10k-calibration-variant = "linksys-ea6350v3";
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
- qcom,ath10k-calibration-variant = "linksys-ea6350v3";
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- mux {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
-
- mux_cs {
- function = "gpio";
- pins = "gpio54", "gpio59";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&blsp1_spi1 { /* BLSP1 QUP1 */
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,
- <&tlmm 59 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- SBL1@0 {
- label = "SBL1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
- MBIB@40000 {
- label = "MIBIB";
- reg = <0x00040000 0x00020000>;
- read-only;
- };
- QSEE@60000 {
- label = "QSEE";
- reg = <0x00060000 0x00060000>;
- read-only;
- };
- CDT@c0000 {
- label = "CDT";
- reg = <0x000c0000 0x00010000>;
- read-only;
- };
- APPSBLENV@d0000 {
- label = "APPSBLENV";
- reg = <0x000d0000 0x00010000>;
- read-only;
- };
- APPSBL@e0000 {
- label = "APPSBL"; /* uboot */
- reg = <0x000e0000 0x00080000>;
- read-only;
- };
- ART@160000 {
- label = "ART";
- reg = <0x00160000 0x00010000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
- u_env@170000 {
- label = "u_env";
- reg = <0x00170000 0x00020000>;
- };
- s_env@190000 {
- label = "s_env";
- reg = <0x00190000 0x00020000>;
- };
- devinfo@1b0000 {
- label = "devinfo";
- reg = <0x001b0000 0x00010000>;
- };
- /* 0x001c0000 - 0x00200000 unused */
- };
- };
-
- flash@1 {
- status = "okay";
- compatible = "spi-nand";
- reg = <1>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- kernel@0 {
- label = "kernel";
- reg = <0x00000000 0x02800000>;
- };
- rootfs@500000 {
- label = "rootfs";
- reg = <0x00500000 0x02300000>;
- };
- alt_kernel@2800000 {
- label = "alt_kernel";
- reg = <0x02800000 0x02800000>;
- };
- alt_rootfs@2d00000 {
- label = "alt_rootfs";
- reg = <0x02d00000 0x02300000>;
- };
- sysdiag@5000000 {
- label = "sysdiag";
- reg = <0x05000000 0x00100000>;
- };
- syscfg@5100000 {
- label = "syscfg";
- reg = <0x05100000 0x02F00000>;
- };
- /* 0x00000000 - 0x08000000: 128 MiB */
- };
- };
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "EnGenius EAP1300";
- compatible = "engenius,eap1300";
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- aliases {
- led-boot = &power;
- led-failsafe = &power;
- led-running = &power;
- led-upgrade = &power;
- };
-
- leds {
- compatible = "gpio-leds";
-
- power: orange {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_ORANGE>;
- gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
- };
-
- lan {
- function = LED_FUNCTION_LAN;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
- };
-
- mesh {
- label = "blue:mesh";
- gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
- };
-
- wlan2g {
- label = "blue:wlan2g";
- gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
- };
-
- wlan5g {
- label = "yellow:wlan5g";
- gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pin {
- function = "blsp_spi0";
- pins = "gpio54", "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
- pin_cs {
- function = "gpio";
- pins = "gpio54";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
- m25p80@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
- partition1@40000 {
- label = "0:MIBIB";
- reg = <0x00040000 0x00020000>;
- read-only;
- };
- partition2@60000 {
- label = "0:QSEE";
- reg = <0x00060000 0x00060000>;
- read-only;
- };
- partition3@c0000 {
- label = "0:CDT";
- reg = <0x000c0000 0x00010000>;
- read-only;
- };
- partition4@d0000 {
- label = "0:DDRPARAMS";
- reg = <0x000d0000 0x00010000>;
- read-only;
- };
- partition5@e0000 {
- label = "0:APPSBLENV";
- reg = <0x000e0000 0x00010000>;
- read-only;
- };
- partition6@f0000 {
- label = "0:APPSBL";
- reg = <0x000f0000 0x00090000>;
- read-only;
- };
- partition7@180000 {
- label = "0:ART";
- reg = <0x00180000 0x00010000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
- partition8@190000 {
- compatible = "denx,fit";
- label = "firmware";
- reg = <0x190000 0x1dc0000>;
- };
- partition9@1f50000 {
- label = "u-boot-env";
- reg = <0x01f50000 0x00010000>;
- };
- partition10@1f60000 {
- label = "userconfig";
- reg = <0x01f60000 0x000a0000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
- qcom,ath10k-calibration-variant = "EnGenius-EAP1300";
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
- qcom,ath10k-calibration-variant = "EnGenius-EAP1300";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "Edgecore ECW5211";
- compatible = "edgecore,ecw5211";
-
- aliases {
- led-boot = &led_power;
- led-failsafe = &led_power;
- led-running = &led_power;
- led-upgrade = &led_power;
- ethernet0 = &swport5;
- ethernet1 = &gmac;
- };
-
- chosen {
- bootargs-append = " root=/dev/ubiblock0_1";
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_power: power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_YELLOW>;
- gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
- };
-
- wlan2g {
- label = "green:wlan2g";
- gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy0tpt";
- };
-
- wlan5g {
- label = "green:wlan5g";
- gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy1tpt";
- };
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- counter@4a1000 {
- compatible = "qcom,qca-gcnt";
- reg = <0x4a1000 0x4>;
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2@60f8800 {
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
-
- dwc3@8a00000 {
- phys = <&usb3_hs_phy>;
- phy-names = "usb2-phy";
- };
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-};
-
-&tlmm {
- mdio_pins: mdio_pinmux {
- mux_mdio {
- pins = "gpio53";
- function = "mdio";
- bias-pull-up;
- };
-
- mux_mdc {
- pins = "gpio52";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi0_pins: spi0_pinmux {
- pin {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <2>;
- bias-disable;
- };
-
- pin_cs {
- function = "gpio";
- pins = "gpio54", "gpio4";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-
- i2c0_pins: i2c0_pinmux {
- mux_i2c {
- function = "blsp_i2c0";
- pins = "gpio58", "gpio59";
- drive-strength = <16>;
- bias-disable;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- status = "okay";
-
- pinctrl-0 = <&spi0_pins>;
- pinctrl-names = "default";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 4 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
-
- partition@40000 {
- label = "0:MIBIB";
- reg = <0x00040000 0x00020000>;
- read-only;
- };
-
- partition@60000 {
- label = "0:QSEE";
- reg = <0x00060000 0x00060000>;
- read-only;
- };
-
- partition@c0000 {
- label = "0:CDT";
- reg = <0x000c0000 0x00010000>;
- read-only;
- };
-
- partition@d0000 {
- label = "0:DDRPARAMS";
- reg = <0x000d0000 0x00010000>;
- read-only;
- };
-
- partition@e0000 {
- label = "0:APPSBLENV"; /* uboot env */
- reg = <0x000e0000 0x00010000>;
- };
-
- partition@f0000 {
- label = "0:APPSBL"; /* uboot */
- reg = <0x000f0000 0x00080000>;
- read-only;
- };
-
- partition@170000 {
- label = "0:ART";
- reg = <0x00170000 0x00010000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
- };
- };
-
- flash@1 {
- compatible = "spi-nand";
- reg = <1>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "rootfs";
- reg = <0x00000000 0x04000000>;
- };
- };
- };
-};
-
-&blsp1_i2c3 {
- status = "okay";
-
- pinctrl-0 = <&i2c0_pins>;
- pinctrl-names = "default";
-
- tpm@29 {
- compatible = "atmel,at97sc3204t";
- reg = <0x29>;
- };
-};
-
-&blsp1_uart1 {
- status = "okay";
-
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&mdio {
- status = "okay";
-
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
-
- label = "lan";
-};
-
-&swport5 {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
- qcom,ath10k-calibration-variant = "ALFA-Network-AP120C-AC";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "EnGenius EMD1";
- compatible = "engenius,emd1";
-
- aliases {
- led-boot = &led_power;
- led-failsafe = &led_power;
- led-running = &led_power;
- led-upgrade = &led_power;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_power: power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
- };
-
- wlan2g {
- label = "red:wlan2g";
- gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy0tpt";
- };
-
- wlan5g {
- label = "blue:wlan5g";
- gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy1tpt";
- };
-
- mesh {
- label = "orange:mesh";
- gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pin {
- function = "blsp_spi0";
- pins = "gpio54", "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
-
- pin_cs {
- function = "gpio";
- pins = "gpio54";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition0@0 {
- label = "0:SBL1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
- partition1@40000 {
- label = "0:MIBIB";
- reg = <0x00040000 0x00020000>;
- read-only;
- };
- partition2@60000 {
- label = "0:QSEE";
- reg = <0x00060000 0x00060000>;
- read-only;
- };
- partition3@c0000 {
- label = "0:CDT";
- reg = <0x000c0000 0x00010000>;
- read-only;
- };
- partition4@d0000 {
- label = "0:DDRPARAMS";
- reg = <0x000d0000 0x00010000>;
- read-only;
- };
- partition5@e0000 {
- label = "0:APPSBLENV";
- reg = <0x000e0000 0x00010000>;
- read-only;
- };
- partition6@f0000 {
- label = "0:APPSBL";
- reg = <0x000f0000 0x00080000>;
- read-only;
- };
- partition7@170000 {
- label = "0:ART";
- reg = <0x00170000 0x00010000>;
- read-only;
- };
- partition8@180000 {
- label = "userconfig";
- reg = <0x00180000 0x00080000>;
- read-only;
- };
- partition9@200000 {
- compatible = "denx,fit";
- label = "firmware";
- reg = <0x200000 0x01e00000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "EnGenius-EMD1";
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "EnGenius-EMD1";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "EnGenius EMR3500";
- compatible = "engenius,emr3500";
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2_hs_phy: hsphy@a8000 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- aliases {
- led-boot = &power;
- led-failsafe = &power;
- led-running = &power;
- led-upgrade = &power;
- };
-
- leds {
- compatible = "gpio-leds";
-
- power: white {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
- };
-
- blue {
- label = "blue";
- gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
- };
-
- red {
- label = "red";
- gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
- };
-
- orange {
- label = "orange";
- gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pin {
- function = "blsp_spi0";
- pins = "gpio54", "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
- pin_cs {
- function = "gpio";
- pins = "gpio54";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
- m25p80@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
- partition@40000 {
- label = "0:MIBIB";
- reg = <0x00040000 0x00020000>;
- read-only;
- };
- partition@60000 {
- label = "0:QSEE";
- reg = <0x00060000 0x00060000>;
- read-only;
- };
- partition@c0000 {
- label = "0:CDT";
- reg = <0x000c0000 0x00010000>;
- read-only;
- };
- partition@d0000 {
- label = "0:DDRPARAMS";
- reg = <0x000d0000 0x00010000>;
- read-only;
- };
- partition@e0000 {
- label = "0:APPSBLENV";
- reg = <0x000e0000 0x00010000>;
- read-only;
- };
- partition@f0000 {
- label = "0:APPSBL";
- reg = <0x000f0000 0x00080000>;
- read-only;
- };
- partition@170000 {
- label = "0:ART";
- reg = <0x00170000 0x00010000>;
- read-only;
- };
- partition@180000 {
- label = "userconfig";
- reg = <0x00180000 0x00080000>;
- read-only;
- };
- partition@200000 {
- compatible = "denx,fit";
- label = "firmware";
- reg = <0x200000 0x1e00000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "EnGenius-EMR3500";
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "EnGenius-EMR3500";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "EnGenius ENS620EXT";
- compatible = "engenius,ens620ext";
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x10000000>;
- };
-
- aliases {
- led-boot = &power;
- led-failsafe = &power;
- led-running = &power;
- led-upgrade = &power;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
-
- /*
- * Disable the broken restart as a workaround for the buggy
- * 3.0.0/3.0.1 U-boots that ship with the device.
- * Note: The watchdog is now used to restart this device.
- */
- restart@4ab000 {
- status = "disabled";
- };
- };
-
- buttons {
- compatible = "gpio-keys";
-
- wps {
- label = "wps";
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- power: power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_AMBER>;
- gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
- };
-
- lan1 {
- label = "green:lan1";
- gpios = <&tlmm 1 GPIO_ACTIVE_LOW>;
- };
-
- lan2 {
- label = "green:lan2";
- gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
- };
-
- wlan2g {
- label = "green:wlan2g";
- gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
- };
-
- wlan5g {
- label = "green:wlan5g";
- gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- mux {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
-
- mux_cs {
- function = "gpio";
- pins = "gpio54";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&blsp1_spi1 { /* BLSP1 QUP1 */
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <50000000>;
- m25p,fast-read;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SBL1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
- partition@40000 {
- label = "MIBIB";
- reg = <0x00040000 0x00020000>;
- read-only;
- };
- partition@60000 {
- label = "QSEE";
- reg = <0x00060000 0x00060000>;
- read-only;
- };
- partition@c0000 {
- label = "CDT";
- reg = <0x000c0000 0x00010000>;
- read-only;
- };
- partition@d0000 {
- label = "DDRPARAMS";
- reg = <0x000d0000 0x00010000>;
- read-only;
- };
- partition@e0000 {
- label = "APPSBLENV"; /* uboot env*/
- reg = <0x000e0000 0x00010000>;
- read-only;
- };
- partition@f0000 {
- label = "APPSBL"; /* uboot */
- reg = <0x000f0000 0x00090000>;
- read-only;
- };
- partition@180000 {
- label = "ART";
- reg = <0x00180000 0x00010000>;
- read-only;
- };
- partition@190000 {
- compatible = "denx,fit";
- label = "firmware";
- reg = <0x00190000 0x14d0000>;
- };
- partition@1660000 {
- label = "failsafe";
- reg = <0x01660000 0x008F0000>;
- read-only;
- };
- partition@1f50000 {
- label = "u-boot-env";
- reg = <0x01f50000 0x00010000>;
- read-only;
- };
- partition@1f60000 {
- label = "userconfig";
- reg = <0x01f60000 0x000a0000>;
- read-only;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "EnGenius-ENS620EXT";
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "EnGenius-ENS620EXT";
-};
+++ /dev/null
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
- * Copyright (c) 2018, David Bauer <mail@david-bauer.net>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "qcom-ipq4018-ex61x0v2.dtsi"
-
-/ {
- model = "Netgear EX6100v2";
- compatible = "netgear,ex6100v2";
-};
-
-&wifi0 {
- qcom,ath10k-calibration-variant = "Netgear-EX6100v2";
-};
-
-&wifi1 {
- qcom,ath10k-calibration-variant = "Netgear-EX6100v2";
-};
+++ /dev/null
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
- * Copyright (c) 2018, David Bauer <mail@david-bauer.net>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "qcom-ipq4018-ex61x0v2.dtsi"
-
-/ {
- model = "Netgear EX6150v2";
- compatible = "netgear,ex6150v2";
-};
-
-&wifi0 {
- qcom,ath10k-calibration-variant = "Netgear-EX6150v2";
-};
-
-&wifi1 {
- qcom,ath10k-calibration-variant = "Netgear-EX6150v2";
-};
+++ /dev/null
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
- * Copyright (c) 2018, David Bauer <mail@david-bauer.net>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "Netgear EX61X0v2";
- compatible = "netgear,ex61x0v2";
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- aliases {
- led-boot = &power_amber;
- led-failsafe = &power_amber;
- led-running = &power_green;
- led-upgrade = &power_amber;
- label-mac-device = &gmac;
- };
-
- keys {
- compatible = "gpio-keys";
-
- wps {
- label = "wps";
- gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- };
-
- reset {
- label = "reset";
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- led_spi {
- compatible = "spi-gpio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- sck-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
- mosi-gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
- num-chipselects = <0>;
-
- led_gpio: led_gpio@0 {
- compatible = "fairchild,74hc595";
- reg = <0>;
- gpio-controller;
- #gpio-cells = <2>;
- registers-number = <1>;
- spi-max-frequency = <1000000>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- power_amber: power_amber {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_AMBER>;
- gpios = <&led_gpio 7 GPIO_ACTIVE_LOW>;
- };
-
- power_green: power_green {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;
- };
-
- right {
- label = "blue:right";
- gpios = <&led_gpio 5 GPIO_ACTIVE_LOW>;
- };
-
- left {
- label = "blue:left";
- gpios = <&led_gpio 4 GPIO_ACTIVE_LOW>;
- };
-
- client_green {
- label = "green:client";
- gpios = <&led_gpio 3 GPIO_ACTIVE_LOW>;
- };
-
- client_red {
- label = "red:client";
- gpios = <&led_gpio 2 GPIO_ACTIVE_LOW>;
- };
-
- router_green {
- label = "green:router";
- gpios = <&led_gpio 1 GPIO_ACTIVE_LOW>;
- };
-
- router_red {
- label = "red:router";
- gpios = <&led_gpio 0 GPIO_ACTIVE_LOW>;
- };
-
- wps {
- function = LED_FUNCTION_WPS;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 1 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pin {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
- pin_cs {
- function = "gpio";
- pins = "gpio54";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
- mx25l12805d@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <45000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition0@0 {
- label = "SBL1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
-
- partition1@40000 {
- label = "MIBIB";
- reg = <0x00040000 0x00020000>;
- read-only;
- };
-
- partition2@60000 {
- label = "QSEE";
- reg = <0x00060000 0x00060000>;
- read-only;
- };
-
- partition3@c0000 {
- label = "CDT";
- reg = <0x000c0000 0x00010000>;
- read-only;
- };
-
- partition4@d0000 {
- label = "DDRPARAMS";
- reg = <0x000d0000 0x00010000>;
- read-only;
- };
-
- partition5@E0000 {
- label = "APPSBLENV";
- reg = <0x000e0000 0x00010000>;
- read-only;
- };
-
- partition6@F0000 {
- label = "APPSBL";
- reg = <0x000f0000 0x00080000>;
- read-only;
- };
-
- partition7@170000 {
- label = "ART";
- reg = <0x00170000 0x00010000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- partition8@180000 {
- label = "config";
- reg = <0x00180000 0x00010000>;
- read-only;
- };
-
- partition9@190000 {
- label = "pot";
- reg = <0x00190000 0x00010000>;
- read-only;
- };
-
- partition10@1a0000 {
- label = "dnidata";
- reg = <0x001a0000 0x00010000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_dnidata_0: macaddr@0 {
- reg = <0x0 0x6>;
- };
-
- macaddr_dnidata_c: macaddr@c {
- reg = <0xc 0x6>;
- };
- };
- };
-
- partition11@1b0000 {
- compatible = "denx,fit";
- label = "firmware";
- reg = <0x001b0000 0x00e10000>;
- };
-
- partition12@fc0000 {
- label = "language";
- reg = <0x00fc0000 0x00040000>;
- read-only;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_1000>, <&macaddr_dnidata_0>;
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_5000>, <&macaddr_dnidata_c>;
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
- label = "lan";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "AVM FRITZ!Box 4040";
- compatible = "avm,fritzbox-4040";
-
- aliases {
- led-boot = &power;
- led-failsafe = &flash;
- led-running = &power;
- led-upgrade = &flash;
- label-mac-device = &gmac;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2@60f8800 {
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- wlan {
- label = "wlan";
- gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RFKILL>;
- };
-
- wps {
- label = "wps";
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- };
- };
-
- switch-leds {
- compatible = "gpio-leds";
-
- wlan {
- function = LED_FUNCTION_WLAN;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <ðphy0 0 GPIO_ACTIVE_HIGH>;
- };
-
- panic: info_red {
- label = "red:info";
- gpios = <ðphy0 1 GPIO_ACTIVE_HIGH>;
- panic-indicator;
- };
-
- wan {
- function = LED_FUNCTION_WAN;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <ðphy1 0 GPIO_ACTIVE_HIGH>;
- };
-
- power: power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <ðphy2 1 GPIO_ACTIVE_HIGH>;
- };
-
- lan {
- function = LED_FUNCTION_LAN;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <ðphy3 0 GPIO_ACTIVE_HIGH>;
- };
-
- flash: info_amber {
- label = "amber:info";
- gpios = <ðphy3 1 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- mux {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
-
- mux_cs {
- function = "gpio";
- pins = "gpio54";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 { /* BLSP1 QUP1 */
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
- status = "okay";
- m25p,fast-read;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition0@0 {
- label = "SBL1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
- partition1@40000 {
- label = "MIBIB";
- reg = <0x00040000 0x00020000>;
- read-only;
- };
- partition2@60000 {
- label = "QSEE";
- reg = <0x00060000 0x00060000>;
- read-only;
- };
- partition3@c0000 {
- label = "CDT";
- reg = <0x000c0000 0x00010000>;
- read-only;
- };
- partition4@d0000 {
- label = "DDRPARAMS";
- reg = <0x000d0000 0x00010000>;
- read-only;
- };
- partition5@e0000 {
- label = "APPSBLENV"; /* uboot env - empty */
- reg = <0x000e0000 0x00010000>;
- read-only;
- };
- partition6@f0000 {
- label = "urlader"; /* APPSBL */
- reg = <0x000f0000 0x0002dc000>;
- read-only;
- };
- partition7@11dc00 {
- /* make a backup of this partition! */
- label = "urlader_config";
- reg = <0x0011dc00 0x00002400>;
- read-only;
- };
- partition8@120000 {
- label = "tffs1";
- reg = <0x00120000 0x00080000>;
- read-only;
- };
- partition9@1a0000 {
- label = "tffs2";
- reg = <0x001a0000 0x00080000>;
- read-only;
- };
- partition10@220000 {
- label = "uboot";
- reg = <0x00220000 0x00080000>;
- read-only;
- };
- partition11@2A0000 {
- compatible = "denx,fit";
- label = "firmware";
- reg = <0x002a0000 0x01c60000>;
- };
- partition12@1f00000 {
- label = "jffs2";
- reg = <0x01f00000 0x00100000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-ðphy0 {
- gpio-controller;
- #gpio-cells = <2>;
-};
-
-ðphy1 {
- gpio-controller;
- #gpio-cells = <2>;
-
- enable-usb-power {
- gpio-hog;
- line-name = "enable USB3 power";
- gpios = <1 GPIO_ACTIVE_HIGH>;
- output-high;
- };
-};
-
-ðphy2 {
- gpio-controller;
- #gpio-cells = <2>;
-};
-
-ðphy3 {
- gpio-controller;
- #gpio-cells = <2>;
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport1 {
- status = "okay";
-};
-
-&swport2 {
- status = "okay";
-};
-
-&swport3 {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
-};
-
-&swport5 {
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "AVM-FRITZBox-4040";
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "AVM-FRITZBox-4040";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "GL.iNet GL-A1300";
- compatible = "glinet,gl-a1300", "qcom,ipq4019";
-
- aliases {
- led-boot = &led_run;
- led-failsafe = &led_run;
- led-running = &led_run;
- led-upgrade = &led_run;
- label-mac-device = &swport4;
- };
-
- chosen {
- bootargs-append = " ubi.mtd=ubi root=/dev/ubiblock0_1";
- };
-
- soc {
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- /* select hostmode */
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
-
- switch {
- label = "switch-button";
- gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_SETUP>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_run: blue {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
- };
-
- white {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
- };
- };
-
- gpio_export {
- compatible = "gpio-export";
-
- usb {
- gpio-export,name = "usb_power";
- gpio-export,output = <1>;
- gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&prng {
- status = "okay";
-};
-
-&mdio {
- status = "okay";
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&watchdog {
- status = "okay";
-};
-
-&crypto {
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&blsp1_spi1 {
- status = "okay";
-
- pinctrl-0 = <&spi0_pins>;
- pinctrl-names = "default";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 5 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SBL1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
-
- partition@40000 {
- label = "MIBIB";
- reg = <0x00040000 0x00020000>;
- read-only;
- };
-
- partition@60000 {
- label = "QSEE";
- reg = <0x00060000 0x00060000>;
- read-only;
- };
-
- partition@c0000 {
- label = "CDT";
- reg = <0x000c0000 0x00010000>;
- read-only;
- };
-
- partition@d0000 {
- label = "DDRPARAMS";
- reg = <0x000d0000 0x00010000>;
- read-only;
- };
-
- partition@e0000 {
- label = "APPSBLENV"; /* uboot env*/
- reg = <0x000e0000 0x00010000>;
- };
-
- partition@f0000 {
- label = "APPSBL"; /* uboot */
- reg = <0x000f0000 0x00080000>;
- read-only;
- };
-
- partition@170000 {
- label = "ART";
- reg = <0x00170000 0x00010000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_gmac0: macaddr@0 {
- compatible = "mac-base";
- reg = <0x0 0x6>;
- #nvmem-cell-cells = <1>;
- };
-
- macaddr_gmac1: macaddr@6 {
- reg = <0x6 0x6>;
- };
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- partition@180000 {
- label = "log";
- reg = <0x00180000 0x00020000>;
- };
- };
- };
-
- spi-nand@1 {
- compatible = "spi-nand";
- reg = <1>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "ubi";
- reg = <0x00000000 0x08000000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- i2c_0_pins: i2c_0_pinmux {
- pinmux {
- pins = "gpio58", "gpio59";
- function = "blsp_i2c0";
- bias-disable;
- };
- };
-
- spi0_pins: spi0_pinmux {
- mux_spi {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
-
- mux_cs {
- function = "gpio";
- pins = "gpio54", "gpio5";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&blsp1_i2c3 {
- status = "okay";
- pinctrl-0 = <&i2c_0_pins>;
- pinctrl-names = "default";
-};
-
-&usb2 {
- status = "okay";
-};
-
-&usb3 {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport3 {
- status = "okay";
-
- label = "lan2";
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_gmac0 2>;
-};
-
-&swport4 {
- status = "okay";
-
- label = "lan1";
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_gmac0 0>;
-};
-
-&swport5 {
- status = "okay";
-
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_gmac1>;
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
- qcom,ath10k-calibration-variant = "GL-A1300";
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
- qcom,ath10k-calibration-variant = "GL-A1300";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "GL.iNet GL-AP1300";
- compatible = "glinet,gl-ap1300";
-
- aliases {
- led-boot = &led_power;
- led-failsafe = &led_power;
- led-running = &led_power;
- led-upgrade = &led_power;
- };
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x10000000>;
- };
-
- chosen {
- bootargs-append = " ubi.mtd=ubi root=/dev/ubiblock0_1";
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- /* select hostmode */
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2@60f8800 {
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_power: power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- };
-
- wan {
- function = LED_FUNCTION_WAN;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&blsp1_spi1 {
- status = "okay";
-
- pinctrl-0 = <&spi0_pins>;
- pinctrl-names = "default";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 5 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- status = "okay";
-
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SBL1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
-
- partition@40000 {
- label = "MIBIB";
- reg = <0x00040000 0x00020000>;
- read-only;
- };
-
- partition@60000 {
- label = "QSEE";
- reg = <0x00060000 0x00060000>;
- read-only;
- };
-
- partition@c0000 {
- label = "CDT";
- reg = <0x000c0000 0x00010000>;
- read-only;
- };
-
- partition@d0000 {
- label = "DDRPARAMS";
- reg = <0x000d0000 0x00010000>;
- read-only;
- };
-
- partition@e0000 {
- label = "APPSBLENV"; /* uboot env*/
- reg = <0x000e0000 0x00010000>;
- };
-
- partition@f0000 {
- label = "APPSBL"; /* uboot */
- reg = <0x000f0000 0x00080000>;
- read-only;
- };
-
- partition@170000 {
- label = "ART";
- reg = <0x00170000 0x00010000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_art_0: mac-address@0 {
- reg = <0x0 0x6>;
- };
-
- macaddr_art_6: mac-address@6 {
- reg = <0x6 0x6>;
- };
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
- };
- };
-
- spi-nand@1 {
- status = "okay";
-
- compatible = "spi-nand";
- reg = <1>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "ubi";
- reg = <0x00000000 0x08000000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi0_pins: spi0_pinmux {
- mux_spi {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
-
- mux_cs {
- function = "gpio";
- pins = "gpio54", "gpio5";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
- label = "lan";
-
- nvmem-cells = <&macaddr_art_0>;
- nvmem-cell-names = "mac-address";
-};
-
-&swport5 {
- status = "okay";
- label = "wan";
-
- nvmem-cells = <&macaddr_art_6>;
- nvmem-cell-names = "mac-address";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
- qcom,ath10k-calibration-variant = "GL-AP1300";
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
- qcom,ath10k-calibration-variant = "GL-AP1300";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/* Copyright (c) 2020, Robert Marko <robimarko@gmail.com> */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "MikroTik hAP ac2";
- compatible = "mikrotik,hap-ac2";
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x08000000>;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- aliases {
- led-boot = &led_user;
- led-failsafe = &led_user;
- led-running = &led_user;
- led-upgrade = &led_user;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- counter@4a1000 {
- compatible = "qcom,qca-gcnt";
- reg = <0x4a1000 0x4>;
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- /* select hostmode */
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb3@8af8800 {
- status = "okay";
-
- dwc3@8a00000 {
- phys = <&usb3_hs_phy>;
- phy-names = "usb2-phy";
- };
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
-
- mode {
- label = "mode";
- gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RFKILL>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
- default-state = "keep";
- panic-indicator;
- };
-
- led_user: user {
- label = "green:user";
- gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pin {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <2>;
- bias-disable;
- };
- pin_cs {
- function = "gpio";
- pins = "gpio54";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-
- enable-usb-power {
- gpio-hog;
- gpios = <2 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "enable USB power";
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- status = "okay";
-
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- reg = <0>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <40000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "Qualcomm";
- reg = <0x0 0x80000>;
- read-only;
- };
-
- partition@80000 {
- compatible = "mikrotik,routerboot-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
- label = "RouterBoot";
- reg = <0x80000 0x80000>;
-
- hard_config {
- read-only;
- size = <0x2000>;
- };
-
- dtb_config {
- read-only;
- };
-
- soft_config {
- };
- };
-
- partition@100000 {
- compatible = "mikrotik,minor";
- label = "firmware";
- reg = <0x100000 0xf00000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- status = "okay";
-
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&mdio {
- status = "okay";
-};
-
-ðphy0 {
- qcom,single-led-1000;
- qcom,single-led-100;
- qcom,single-led-10;
-};
-
-ðphy1 {
- qcom,single-led-1000;
- qcom,single-led-100;
- qcom,single-led-10;
-};
-
-ðphy2 {
- qcom,single-led-1000;
- qcom,single-led-100;
- qcom,single-led-10;
-};
-
-ðphy3 {
- qcom,single-led-1000;
- qcom,single-led-100;
- qcom,single-led-10;
-};
-
-ðphy4 {
- qcom,single-led-1000;
- qcom,single-led-100;
- qcom,single-led-10;
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport1 {
- status = "okay";
- label = "lan4";
-};
-
-&swport2 {
- status = "okay";
- label = "lan3";
-};
-
-&swport3 {
- status = "okay";
- label = "lan2";
-};
-
-&swport4 {
- status = "okay";
- label = "lan1";
-};
-
-&swport5 {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
-
- qcom,ath10k-calibration-variant = "MikroTik-hAP-ac2";
-};
-
-&wifi1 {
- status = "okay";
-
- qcom,ath10k-calibration-variant = "MikroTik-hAP-ac2";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-// Copyright (c) 2018, Robert Marko <robimarko@gmail.com>
-
-#include "qcom-ipq4018-jalapeno.dtsi"
-
-/ {
- model = "8devices Jalapeno";
- compatible = "8dev,jalapeno";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-// Copyright (c) 2018, Robert Marko <robimarko@gmail.com>
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- aliases {
- ethernet1 = &swport5;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
-
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- };
-
- counter@4a1000 {
- compatible = "qcom,qca-gcnt";
- reg = <0x4a1000 0x4>;
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- status = "okay";
-
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2: usb2@60f8800 {
- status = "okay";
- };
-
- usb3: usb3@8af8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-};
-
-&tlmm {
- mdio_pins: mdio_pinmux {
- pinmux_1 {
- pins = "gpio53";
- function = "mdio";
- };
-
- pinmux_2 {
- pins = "gpio52";
- function = "mdc";
- };
-
- pinconf {
- pins = "gpio52", "gpio53";
- bias-pull-up;
- };
- };
-
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pin {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <2>;
- bias-disable;
- };
-
- pin_cs {
- function = "gpio";
- pins = "gpio54", "gpio59";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- status = "okay";
-
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 59 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- status = "okay";
-
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SBL1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
-
- partition@40000 {
- label = "MIBIB";
- reg = <0x00040000 0x00020000>;
- read-only;
- };
-
- partition@60000 {
- label = "QSEE";
- reg = <0x00060000 0x00060000>;
- read-only;
- };
-
- partition@c0000 {
- label = "CDT";
- reg = <0x000c0000 0x00010000>;
- read-only;
- };
-
- partition@d0000 {
- label = "DDRPARAMS";
- reg = <0x000d0000 0x00010000>;
- read-only;
- };
-
- partition@e0000 {
- label = "APPSBLENV"; /* uboot env*/
- reg = <0x000e0000 0x00010000>;
- read-only;
- };
-
- partition@f0000 {
- label = "APPSBL"; /* uboot */
- reg = <0x000f0000 0x00080000>;
- read-only;
- };
-
- partition@170000 {
- label = "ART";
- reg = <0x00170000 0x00010000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
- };
- };
-
- spi-nand@1 {
- status = "okay";
-
- compatible = "spi-nand";
- reg = <1>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "ubi";
- reg = <0x00000000 0x08000000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- status = "okay";
-
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
-
- label = "lan";
-};
-
-&swport5 {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
- qcom,ath10k-calibration-variant = "8devices-Jalapeno";
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
- qcom,ath10k-calibration-variant = "8devices-Jalapeno";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "devolo Magic 2 WiFi next";
- compatible = "devolo,magic-2-wifi-next";
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x10000000>;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- reset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
- reset-delay-us = <2000>;
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
-
- gpio_export {
- compatible = "gpio-export";
- #size-cells = <0>;
-
- plc {
- gpio-export,name = "plc-enable";
- gpio-export,output = <1>;
- gpios = <&tlmm 63 GPIO_ACTIVE_HIGH>;
- };
- };
-
- };
-
- keys {
- compatible = "gpio-keys";
-
- wlan {
- label = "WLAN";
- gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- };
-
- reset {
- label = "Reset";
- gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- status_dlan {
- label = "white:dlan";
- gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
- default-state = "keep";
- };
-
- status_wlan {
- function = LED_FUNCTION_WLAN;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
- default-state = "keep";
- };
-
- error_dlan {
- label = "red:dlan";
- gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
- default-state = "keep";
- };
- };
-};
-
-&tlmm {
- spi_0_pins: spi_0_pinmux {
- mux {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
-
- mux_cs {
- function = "gpio";
- pins = "gpio54";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio53";
- function = "mdio";
- bias-pull-up;
- };
- mux_2 {
- pins = "gpio52";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio61", "gpio60";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- button_pins: button_pinmux {
- mux {
- function = "gpio";
- pins = "gpio0", "gpio5";
- bias-disable;
- input;
- };
- };
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-ðphy0 {
- status = "disabled";
-};
-
-ðphy1 {
- status = "disabled";
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "devolo,magic-2-wifi-next";
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "devolo,magic-2-wifi-next";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- linux,modalias = "n25q128a11";
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SBL1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
- partition@40000 {
- label = "MIBIB";
- reg = <0x00040000 0x00020000>;
- read-only;
- };
- partition@60000 {
- label = "QSEE";
- reg = <0x00060000 0x00060000>;
- read-only;
- };
- partition@c0000 {
- label = "CDT";
- reg = <0x000c0000 0x00010000>;
- read-only;
- };
- partition@d0000 {
- label = "DDRPARAMS";
- reg = <0x000d0000 0x00010000>;
- read-only;
- };
- partition@e0000 {
- label = "APPSBLENV"; /* uboot env*/
- reg = <0x000e0000 0x00010000>;
- };
- partition@f0000 {
- label = "APPSBL"; /* uboot */
- reg = <0x000f0000 0x00080000>;
- read-only;
- };
- partition@170000 {
- label = "ART";
- reg = <0x00170000 0x00010000>;
- read-only;
- };
- firmware@180000 {
- compatible = "denx,fit";
- label = "firmware";
- reg = <0x00180000 0x01a80000>;
- };
- };
- };
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport5 {
- status = "okay";
- label = "lan1";
-};
-
-&swport3 {
- status = "okay";
- label = "lan2";
-};
-
-&swport4 {
- status = "okay";
- label = "ghn";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/* Copyright (c) 2019, CRISIS INNOVATION LAB d.o.o.
- * Author: Robert Marko <robert@meshpoint.me>
- */
-
-#include <dt-bindings/leds/common.h>
-
-#include "qcom-ipq4018-jalapeno.dtsi"
-
-/ {
- model = "Crisis Innovation Lab MeshPoint.One";
- compatible = "cilab,meshpoint-one";
-
- aliases {
- led-boot = &led_status;
- led-failsafe = &led_status;
- led-running = &led_status;
- led-upgrade = &led_status;
- };
-
- soc {
- i2c-gpio {
- status = "okay";
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- compatible = "i2c-gpio";
- gpios = <&tlmm 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) /* sda */
- &tlmm 4 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN) /* scl */
- >;
-
- bme280@76 {
- status = "okay";
-
- compatible = "bosch,bme280";
- reg = <0x76>;
- };
-
- pcf2129@51 {
- status = "okay";
-
- compatible = "nxp,pcf2129";
- reg = <0x51>;
- };
-
- ina230@40 {
- status = "okay";
-
- compatible = "ti,ina230";
- reg = <0x40>;
- shunt-resistor = <2000>;
- };
-
- ina230@44 {
- status = "okay";
-
- compatible = "ti,ina230";
- reg = <0x44>;
- shunt-resistor = <2000>;
- };
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART >;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_status: status {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 63 GPIO_ACTIVE_HIGH>;
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-// Copyright (c) 2022, Pawel Dembicki <paweldembicki@gmail.com>.
-// Copyright (c) 2022, Giammarco Marzano <stich86@gmail.com>.
-// Copyright (c) 2023, Andreas Böhler <dev@aboehler.at>
-
-#include "qcom-ipq4018-mf287_common.dtsi"
-
-/ {
- model = "ZTE MF287";
- compatible = "zte,mf287";
-};
-
-&gpio_modem_reset {
- gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
-};
-
-&key_reset {
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
-};
-
-&key_wps {
- gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
-};
-
-&led_status {
- gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,
- <&tlmm 59 GPIO_ACTIVE_HIGH>,
- <&tlmm 1 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x0 0x40000>;
- read-only;
- };
-
- partition@40000 {
- label = "0:MIBIB";
- reg = <0x40000 0x20000>;
- read-only;
- };
-
- partition@60000 {
- label = "0:QSEE";
- reg = <0x60000 0x60000>;
- read-only;
- };
-
- partition@c0000 {
- label = "0:CDT";
- reg = <0xc0000 0x10000>;
- read-only;
- };
-
- partition@d0000 {
- label = "0:DDRPARAMS";
- reg = <0xd0000 0x10000>;
- read-only;
- };
-
- partition@e0000 {
- label = "0:APPSBLENV";
- reg = <0xe0000 0x10000>;
- read-only;
- };
-
- partition@f0000 {
- label = "0:APPSBL";
- reg = <0xf0000 0xc0000>;
- read-only;
- };
-
- partition@1b0000 {
- label = "0:reserved1";
- reg = <0x1b0000 0x50000>;
- read-only;
- };
- };
- };
-
- spi-nand@1 { /* flash@1 ? */
- compatible = "spi-nand";
- reg = <1>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "fota-flag";
- reg = <0x0 0x140000>;
- read-only;
- };
-
- partition@140000 {
- label = "ART";
- reg = <0x140000 0x140000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- partition@280000 {
- label = "mac";
- reg = <0x280000 0x140000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_mac_0: macaddr@0 {
- compatible = "mac-base";
- reg = <0x0 0x6>;
- #nvmem-cell-cells = <1>;
- };
- };
- };
-
- partition@3c0000 {
- label = "cfg-param";
- reg = <0x3c0000 0x600000>;
- read-only;
- };
-
- partition@9c0000 {
- label = "oops";
- reg = <0x9c0000 0x140000>;
- };
-
- partition@b00000 {
- label = "web";
- reg = <0xb00000 0x800000>;
- };
-
- partition@1300000 {
- label = "rootfs";
- reg = <0x1300000 0x2200000>;
- };
-
- partition@3500000 {
- label = "data";
- reg = <0x3500000 0x1900000>;
- };
-
- partition@4e00000 {
- label = "fota";
- reg = <0x4e00000 0x3200000>;
- };
- };
- };
-
- zigbee@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- compatible = "silabs,em3581";
- reg = <2>;
- spi-max-frequency = <12000000>;
- };
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
-
- pinmux_cs {
- function = "gpio";
- pins = "gpio54", "gpio59", "gpio1";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&wifi0 {
- qcom,ath10k-calibration-variant = "zte,mf287";
-};
-
-&wifi1{
- qcom,ath10k-calibration-variant = "zte,mf287";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-// Copyright (c) 2022, Pawel Dembicki <paweldembicki@gmail.com>.
-// Copyright (c) 2022, Giammarco Marzano <stich86@gmail.com>.
-// Copyright (c) 2023, Andreas Böhler <dev@aboehler.at>
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/soc/qcom,tcsr.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- aliases {
- led-boot = &led_status;
- led-failsafe = &led_status;
- led-running = &led_status;
- led-upgrade = &led_status;
- };
-
- chosen {
- /*
- * bootargs forced by u-boot bootipq command:
- * 'ubi.mtd=rootfs root=mtd:ubi_rootfs rootfstype=squashfs rootwait'
- */
- bootargs-append = " root=/dev/ubiblock0_1";
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_status: led-0 {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_BLUE>;
- };
- };
-
- gpio_export {
- compatible = "gpio-export";
- #size-cells = <0>;
-
- gpio_modem_reset: modem {
- gpio-export,name = "modem-reset";
- gpio-export,output = <0>;
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- key_reset: key-reset {
- label = "reset";
- linux,code = <KEY_RESTART>;
- };
-
- key_wps: key-wps {
- label = "wps";
- linux,code = <KEY_WPS_BUTTON>;
- };
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- /* select hostmode */
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
- };
-};
-
-&mdio {
- status = "okay";
-};
-
-&watchdog {
- status = "okay";
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&usb2 {
- status = "okay";
-};
-
-&usb3 {
- status = "okay";
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&crypto {
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_mac_0 2>;
-};
-
-&switch {
- status = "okay";
-};
-
-&swport2 {
- status = "okay";
-
- label = "lan1";
-};
-
-&swport3 {
- status = "okay";
-
- label = "lan2";
-};
-
-&swport4 {
- status = "okay";
-
- label = "lan3";
-};
-
-&swport5 {
- status = "okay";
-
- label = "lan4";
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_1000>, <&macaddr_mac_0 0>;
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_5000>, <&macaddr_mac_0 1>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-// Copyright (c) 2022, Pawel Dembicki <paweldembicki@gmail.com>.
-// Copyright (c) 2022, Giammarco Marzano <stich86@gmail.com>.
-// Copyright (c) 2023, Andreas Böhler <dev@aboehler.at>
-
-#include "qcom-ipq4018-mf287_common.dtsi"
-
-/ {
- model = "ZTE MF287Plus";
- compatible = "zte,mf287plus";
-};
-
-&gpio_modem_reset {
- gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
-};
-
-&key_reset {
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
-};
-
-&key_wps {
- gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
-};
-
-&led_status {
- gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,
- <&tlmm 59 GPIO_ACTIVE_HIGH>,
- <&tlmm 1 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x0 0x40000>;
- read-only;
- };
-
- partition@40000 {
- label = "0:MIBIB";
- reg = <0x40000 0x20000>;
- read-only;
- };
-
- partition@60000 {
- label = "0:QSEE";
- reg = <0x60000 0x60000>;
- read-only;
- };
-
- partition@c0000 {
- label = "0:CDT";
- reg = <0xc0000 0x10000>;
- read-only;
- };
-
- partition@d0000 {
- label = "0:DDRPARAMS";
- reg = <0xd0000 0x10000>;
- read-only;
- };
-
- partition@e0000 {
- label = "0:APPSBLENV";
- reg = <0xe0000 0x10000>;
- read-only;
- };
-
- partition@f0000 {
- label = "0:APPSBL";
- reg = <0xf0000 0xc0000>;
- read-only;
- };
-
- partition@1b0000 {
- label = "0:reserved1";
- reg = <0x1b0000 0x50000>;
- read-only;
- };
- };
- };
-
- spi-nand@1 { /* flash@1 ? */
- compatible = "spi-nand";
- reg = <1>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "fota-flag";
- reg = <0x0 0x140000>;
- read-only;
- };
-
- partition@140000 {
- label = "ART";
- reg = <0x140000 0x140000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- partition@280000 {
- label = "mac";
- reg = <0x280000 0x140000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_mac_0: macaddr@0 {
- compatible = "mac-base";
- reg = <0x0 0x6>;
- #nvmem-cell-cells = <1>;
- };
- };
- };
-
- partition@3c0000 {
- label = "cfg-param";
- reg = <0x3c0000 0x600000>;
- read-only;
- };
-
- partition@9c0000 {
- label = "oops";
- reg = <0x9c0000 0x140000>;
- };
-
- partition@b00000 {
- label = "web";
- reg = <0xb00000 0x800000>;
- };
-
- partition@1300000 {
- label = "rootfs";
- reg = <0x1300000 0x2200000>;
- };
-
- partition@3500000 {
- label = "data";
- reg = <0x3500000 0x1900000>;
- };
-
- partition@4e00000 {
- label = "fota";
- reg = <0x4e00000 0x3200000>;
- };
- };
- };
-
- zigbee@2 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- compatible = "silabs,em3581";
- reg = <2>;
- spi-max-frequency = <12000000>;
- };
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
-
- pinmux_cs {
- function = "gpio";
- pins = "gpio54", "gpio59", "gpio1";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&wifi0 {
- qcom,ath10k-calibration-variant = "zte,mf287plus";
-};
-
-&wifi1{
- qcom,ath10k-calibration-variant = "zte,mf287plus";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-// Copyright (c) 2022, Pawel Dembicki <paweldembicki@gmail.com>.
-// Copyright (c) 2022, Giammarco Marzano <stich86@gmail.com>.
-// Copyright (c) 2023, Andreas Böhler <dev@aboehler.at>
-
-#include "qcom-ipq4018-mf287_common.dtsi"
-
-/ {
- model = "ZTE MF287Pro";
- compatible = "zte,mf287pro";
-
- regulator-usb-vbus {
- compatible = "regulator-fixed";
- regulator-name = "USB_VBUS";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- regulator-boot-on;
- gpio = <&tlmm 25 GPIO_ACTIVE_LOW>;
- };
-};
-
-&gpio_modem_reset {
- gpios = <&tlmm 8 GPIO_ACTIVE_HIGH>;
-};
-
-&key_reset {
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
-};
-
-&key_wps {
- gpios = <&tlmm 68 GPIO_ACTIVE_LOW>;
-};
-
-&led_status {
- gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
-};
-
-&mdio {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
- reset-delay-us = <2000>;
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>,
- <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x0 0x40000>;
- read-only;
- };
-
- partition@40000 {
- label = "0:MIBIB";
- reg = <0x40000 0x20000>;
- read-only;
- };
-
- partition@60000 {
- label = "0:QSEE";
- reg = <0x60000 0x60000>;
- read-only;
- };
-
- partition@c0000 {
- label = "0:CDT";
- reg = <0xc0000 0x10000>;
- read-only;
- };
-
- partition@d0000 {
- label = "0:DDRPARAMS";
- reg = <0xd0000 0x10000>;
- read-only;
- };
-
- partition@e0000 {
- label = "0:APPSBLENV";
- reg = <0xe0000 0x10000>;
- read-only;
- };
-
- partition@f0000 {
- label = "0:APPSBL";
- reg = <0xf0000 0xc0000>;
- read-only;
- };
-
- partition@1b0000 {
- label = "0:reserved1";
- reg = <0x1b0000 0x50000>;
- read-only;
- };
- };
- };
-
- spi-nand@1 { /* flash@1 ? */
- compatible = "spi-nand";
- reg = <1>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "fota-flag";
- reg = <0x0 0xa0000>;
- read-only;
- };
-
- partition@a0000 {
- label = "ART";
- reg = <0xa0000 0x80000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- partition@120000 {
- label = "mac";
- reg = <0x120000 0x80000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_mac_0: macaddr@0 {
- compatible = "mac-base";
- reg = <0x0 0x6>;
- #nvmem-cell-cells = <1>;
- };
- };
- };
-
- partition@1a0000 {
- label = "reserved2";
- reg = <0x1a0000 0xc0000>;
- };
-
- partition@260000 {
- label = "cfg-param";
- reg = <0x260000 0x400000>;
- read-only;
- };
-
- partition@660000 {
- label = "log";
- reg = <0x660000 0x400000>;
- };
-
- partition@a60000 {
- label = "oops";
- reg = <0xa60000 0xa0000>;
- };
-
- partition@b00000 {
- label = "reserved3";
- reg = <0xb00000 0x500000>;
- };
-
- partition@1000000 {
- label = "web";
- reg = <0x1000000 0x800000>;
- };
-
- partition@1800000 {
- label = "rootfs";
- reg = <0x1800000 0x1d00000>;
- };
-
- partition@3500000 {
- label = "data";
- reg = <0x3500000 0x1900000>;
- };
-
- partition@4e00000 {
- label = "fota";
- reg = <0x4e00000 0x3200000>;
- };
- };
- };
-};
-
-&tlmm {
- i2c_0_pins: i2c_0_pinmux {
- mux {
- pins = "gpio20", "gpio21";
- function = "blsp_i2c0";
- bias-disable;
- };
- };
-
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
-
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio12", "gpio13", "gpio14", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
-
- pinmux_cs {
- function = "gpio";
- pins = "gpio12", "gpio54";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-/* The MF287Plus and MF287Pro share the same board data file */
-&wifi0 {
- qcom,ath10k-calibration-variant = "zte,mf287plus";
-};
-
-/* The MF287Plus and MF287Pro share the same board data file */
-&wifi1{
- qcom,ath10k-calibration-variant = "zte,mf287plus";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/input/linux-event-codes.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "ZyXEL NBG6617";
- compatible = "zyxel,nbg6617";
-
- chosen {
- /*
- * the vendor u-boot adds root and mtdparts cmdline parameters
- * which we don't want... but we have to overwrite them or else
- * the kernel will take them at face value.
- */
- bootargs-append = " mtdparts= root=31:13";
- };
-
- aliases {
- led-boot = &power;
- led-failsafe = &power;
- led-running = &power;
- led-upgrade = &power;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2@60f8800 {
- status = "okay";
-
- dwc3@6000000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- usb2_port1: port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
- };
- };
-
- usb3@8af8800 {
- status = "okay";
-
- dwc3@8a00000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- usb3_port1: port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
-
- usb3_port2: port@2 {
- reg = <2>;
- #trigger-source-cells = <0>;
- };
- };
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- wlan {
- label = "wlan";
- gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
- linux,code = <KEY_RFKILL>;
- linux,input-type = <EV_SW>;
- };
-
- wps {
- label = "wps";
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- };
-
- reset {
- label = "reset";
- gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- power: power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
- };
-
- usb {
- function = LED_FUNCTION_USB;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
- trigger-sources = <&usb2_port1>, <&usb3_port1>, <&usb3_port2>;
- linux,default-trigger = "usbport";
- };
-
- wlan2g {
- label = "green:wlan2g";
- gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;
- };
-
- wlan5g {
- label = "green:wlan5g";
- gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
- };
-
- wps {
- function = LED_FUNCTION_WPS;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
- spi_0_pins: spi_0_pinmux {
- mux {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
-
- mux_cs {
- function = "gpio";
- pins = "gpio54";
- drive-strength = <2>;
- bias-disable;
- output-low;
- };
- };
- led_pins: led_pinmux {
- mux {
- pins = "gpio0", "gpio1", "gpio3", "gpio5", "gpio58";
- drive-strength = <0x8>;
- bias-disable;
- output-low;
- };
- };
-};
-
-&blsp1_spi1 { /* BLSP1 QUP1 */
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <50000000>;
- status = "okay";
- m25p,fast-read;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition0@0 {
- label = "SBL1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
- partition1@40000 {
- label = "MIBIB";
- reg = <0x00040000 0x00020000>;
- read-only;
- };
- partition2@60000 {
- label = "QSEE";
- reg = <0x00060000 0x00060000>;
- read-only;
- };
- partition3@c0000 {
- label = "CDT";
- reg = <0x000c0000 0x00010000>;
- read-only;
- };
- partition4@d0000 {
- label = "DDRPARAMS";
- reg = <0x000d0000 0x00010000>;
- read-only;
- };
- partition5@e0000 {
- label = "APPSBL"; /* u-boot */
- reg = <0x000e0000 0x00080000>;
- /* U-Boot Standalone App "zloader" is located at 0x64000 */
- read-only;
- };
- partition6@160000 {
- label = "APPSBLENV"; /* u-boot env */
- reg = <0x00160000 0x00010000>;
- };
- partition7@170000 {
- /* make a backup of this partition! */
- label = "ART";
- reg = <0x00170000 0x00010000>;
- read-only;
- };
- partition8@180000 {
- label = "kernel";
- reg = <0x00180000 0x00400000>;
- };
- partition9@580000 {
- label = "dualflag";
- reg = <0x00580000 0x00010000>;
- read-only;
- };
- partition10@590000 {
- label = "header";
- reg = <0x00590000 0x00010000>;
- };
- partition11@5a0000 {
- label = "romd";
- reg = <0x005a0000 0x00100000>;
- read-only;
- };
- partition12@6a0000 {
- label = "not_root_data";
- /*
- * for some strange reason, someone at ZyXEL
- * had the "great" idea to put the rootfs_data
- * in front of rootfs... Don't do that!
- * As a result this one, full MebiByte remains
- * unused.
- */
- reg = <0x006a0000 0x00100000>;
- };
- partition13@7a0000 {
- label = "rootfs";
- reg = <0x007a0000 0x01860000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport1 {
- status = "okay";
-
- label = "lan4";
-};
-
-&swport2 {
- status = "okay";
-
- label = "lan3";
-};
-
-&swport3 {
- status = "okay";
-
- label = "lan2";
-};
-
-&swport4 {
- status = "okay";
-
- label = "lan1";
-};
-
-&swport5 {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "ZyXEL-NBG6617";
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "ZyXEL-NBG6617";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/* Copyright (c) 2017-2020, Sven Eckelmann <sven@narfation.org>
- * Copyright (c) 2018, Marek Lindner <marek.lindner@kaiwoo.ai>
- */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "Plasma Cloud PA1200";
- compatible = "plasmacloud,pa1200";
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- tcsr@194b000 {
- /* select hostmode */
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2: usb2@60f8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- aliases {
- led-boot = &led_status_purple;
- led-failsafe = &led_status_yellow;
- led-running = &led_status_cyan;
- led-upgrade = &led_status_yellow;
- label-mac-device = &swport5;
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_status_cyan: status_cyan {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_CYAN>;
- gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
- };
-
- led_status_purple: status_purple {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_PURPLE>;
- gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
- };
-
- led_status_yellow: status_yellow {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_YELLOW>;
- gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
- };
- };
-
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pin {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
- pin_cs {
- function = "gpio";
- pins = "gpio54";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- /* partitions are passed via bootloader */
- partitions {
- partition-art {
- label = "0:ART";
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_gmac0: macaddr@0 {
- reg = <0x0 0x6>;
- };
-
- macaddr_gmac1: macaddr@6 {
- reg = <0x6 0x6>;
- };
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&mdio {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
- label = "ethernet2";
-
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_gmac1>;
-};
-
-&swport5 {
- status = "okay";
- label = "ethernet1";
-
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_gmac0>;
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "PlasmaCloud-PA1200";
-
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "PlasmaCloud-PA1200";
-
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "ASUS RT-AC58U";
- compatible = "asus,rt-ac58u";
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x8000000>;
- };
-
- aliases {
- led-boot = &led_power;
- led-failsafe = &led_power;
- led-running = &led_power;
- led-upgrade = &led_power;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb3@8af8800 {
- status = "okay";
-
- dwc3@8a00000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- usb3_port1: port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
-
- usb3_port2: port@2 {
- reg = <2>;
- #trigger-source-cells = <0>;
- };
- };
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
-
- wps {
- label = "wps";
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_power: led-0 {
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_POWER;
- gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
- panic-indicator;
- };
-
- led-1 {
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_WAN;
- gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
- /*
- * linux,default-trigger = "90000.mdio-1:04:link";
- * sadly still lacks rx+tx
- */
- };
-
- led-2 {
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_WLAN;
- function-enumerator = <2>;
- gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy0tpt";
- };
-
- led-3 {
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_WLAN;
- function-enumerator = <5>;
- gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy1tpt";
- };
-
- led-4 {
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_USB;
- gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
- trigger-sources = <&usb3_port1>, <&usb3_port2>;
- linux,default-trigger = "usbport";
- };
-
- led-5 {
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_LAN;
- gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- mux {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
-
- mux_cs {
- function = "gpio";
- pins = "gpio54", "gpio59";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&blsp1_spi1 { /* BLSP1 QUP1 */
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,
- <&tlmm 59 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- /*
- * U-boot looks for "n25q128a11" node,
- * if we don't have it, it will spit out the following warning:
- * "ipq: fdt fixup unable to find compatible node".
- */
- compatible = "jedec,spi-nor";
- reg = <0>;
- linux,modalias = "m25p80", "mx25l1606e", "n25q128a11";
- spi-max-frequency = <30000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SBL1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
- partition@40000 {
- label = "MIBIB";
- reg = <0x00040000 0x00020000>;
- read-only;
- };
- partition@60000 {
- label = "QSEE";
- reg = <0x00060000 0x00060000>;
- read-only;
- };
- partition@c0000 {
- label = "CDT";
- reg = <0x000c0000 0x00010000>;
- read-only;
- };
- partition@d0000 {
- label = "DDRPARAMS";
- reg = <0x000d0000 0x00010000>;
- read-only;
- };
- partition@e0000 {
- label = "APPSBLENV"; /* uboot env*/
- reg = <0x000e0000 0x00010000>;
- read-only;
- };
- partition@f0000 {
- label = "APPSBL"; /* uboot */
- reg = <0x000f0000 0x00080000>;
- read-only;
- };
- partition@170000 {
- label = "ART";
- reg = <0x00170000 0x00010000>;
- read-only;
- };
- /* 0x00180000 - 0x00200000 unused */
- };
- };
-
- spi-nand@1 {
- compatible = "spi-nand";
- reg = <1>;
- spi-max-frequency = <30000000>;
-
- /*
- * U-boot looks for "spinand,mt29f" node,
- * if we don't have it, it will spit out the following warning:
- * "ipq: fdt fixup unable to find compatible node".
- */
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "ubi";
- reg = <0x00000000 0x08000000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport1 {
- status = "okay";
-};
-
-&swport2 {
- status = "okay";
-};
-
-&swport3 {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
-};
-
-&swport5 {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "RT-AC58U";
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "RT-AC58U";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- memory {
- device_type = "memory";
- reg = <0x80000000 0x10000000>;
- };
-
- aliases {
- serial0 = &blsp1_uart1;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- soc {
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- status = "okay";
-
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 4 1>;
- linux,code = <KEY_RESTART>;
- };
- };
- };
-};
-
-&prng {
- status = "okay";
-};
-
-&watchdog {
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&crypto {
- status = "okay";
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- };
- pinmux_cs {
- function = "gpio";
- pins = "gpio54";
- };
- pinconf {
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
- pinconf_cs {
- pins = "gpio54";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio53";
- function = "mdio";
- bias-pull-up;
- };
- mux_2 {
- pins = "gpio52";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- i2c_0_pins: i2c_0_pinmux {
- mux {
- pins = "gpio58", "gpio59";
- function = "blsp_i2c0";
- bias-disable;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- cs-gpios = <&tlmm 54 0>, <&tlmm 63 0>;
- num-cs = <2>;
- status = "okay";
-
- xt25f128b@0 {
- /*
- * Factory U-boot looks in 0:BOOTCONFIG partition for active
- * partitions settings and mangles the partition config so
- * 0:QSEE/0:QSEE_1, 0:CDT/0:CDT_1 and 0:APPSBL/0:APPSBL_1 pairs
- * can be swaped. It isn't a problem but we never can be sure where
- * OFW put factory images. "n25q128a11" is required for proper nor
- * recognition in u-boot.
- */
- compatible = "jedec,spi-nor", "n25q128a11";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x0 0x40000>;
- read-only;
- };
-
- partition@40000 {
- label = "0:MIBIB";
- reg = <0x40000 0x20000>;
- read-only;
- };
-
- partition@60000 {
- label = "0:BOOTCONFIG";
- reg = <0x60000 0x20000>;
- read-only;
- };
-
- partition@80000 {
- label = "0:BOOTCONFIG1";
- reg = <0x80000 0x20000>;
- read-only;
- };
-
- partition@a0000 {
- label = "0:QSEE";
- reg = <0xa0000 0x60000>;
- read-only;
- };
-
- partition@100000 {
- label = "0:QSEE_1";
- reg = <0x100000 0x60000>;
- read-only;
- };
-
- partition@160000 {
- label = "0:CDT";
- reg = <0x160000 0x10000>;
- read-only;
- };
-
- partition@170000 {
- label = "0:CDT_1";
- reg = <0x170000 0x10000>;
- read-only;
- };
-
- partition@180000 {
- label = "0:DDRPARAMS";
- reg = <0x180000 0x10000>;
- read-only;
- };
-
- partition@190000 {
- label = "0:APPSBLENV";
- reg = <0x190000 0x10000>;
- read-only;
- };
-
- partition@1a0000 {
- label = "0:APPSBL";
- reg = <0x1a0000 0xa0000>;
- read-only;
- };
-
- partition@240000 {
- label = "0:APPSBL_1";
- reg = <0x240000 0xa0000>;
- read-only;
- };
-
- partition@2e0000 {
- label = "0:ART";
- reg = <0x2e0000 0x10000>;
- read-only;
- };
-
- config: partition@2f0000 {
- label = "0:CONFIG";
- reg = <0x2f0000 0x10000>;
- read-only;
- };
-
- partition@300000 {
- label = "0:CONFIG_RW";
- reg = <0x300000 0x10000>;
- read-only;
- };
-
- partition@310000 {
- label = "0:EVENTSLOG";
- reg = <0x310000 0x90000>;
- read-only;
- };
- };
- };
-
- xt26g02a@1 {
- /*
- * Factory U-boot looks in 0:BOOTCONFIG partition for active
- * partitions settings and mangles the partition config so
- * rootfs/rootfs_1 pairs can be swaped.
- * It isn't a problem but we never can be sure where OFW put
- * factory images. "spinand,mt29f" value is required for proper
- * nand recognition in u-boot.
- */
- compatible = "spi-nand", "spinand,mt29f";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <1>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "rootfs_1";
- reg = <0x00000000 0x08000000>;
- };
-
- partition@8000000 {
- label = "rootfs";
- reg = <0x08000000 0x08000000>;
- };
- };
- };
-};
-
-&mdio {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- phy-reset-gpio = <&tlmm 62 0>;
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb3 {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&usb2 {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4018-rutx.dtsi"
-
-/ {
- model = "Teltonika RUTX10";
- compatible = "teltonika,rutx10";
-
- soc {
- leds {
- compatible = "gpio-leds";
-
- wifi2g {
- label = "green:wifi2g";
- gpios = <&stm32_io 19 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy0tpt";
- };
-
- wifi5g {
- label = "green:wifi5g";
- gpios = <&stm32_io 18 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy1tpt";
- };
- };
-
- gpio_export {
- compatible = "gpio-export";
- #size-cells = <0>;
-
- gpio_out {
- gpio-export,name = "gpio_out";
- gpio-export,output = <0>;
- gpio-export,direction_may_change = <0>;
- gpios = <&stm32_io 23 GPIO_ACTIVE_HIGH>;
- };
-
- gpio_in {
- gpio-export,name = "gpio_in";
- gpio-export,input = <0>;
- gpio-export,direction_may_change = <0>;
- gpios = <&stm32_io 24 GPIO_ACTIVE_LOW>;
- };
- };
- };
-};
-
-&blsp1_i2c3 {
- status = "okay";
- pinctrl-0 = <&i2c_0_pins>;
- pinctrl-names = "default";
- clock-frequency = <400000>;
-
- stm32_io: stm32@74 {
- compatible = "tlt,stm32v1";
- #gpio-cells = <2>;
- #interrupt-cells = <2>;
- gpio-controller;
- interrupt-controller;
- interrupt-parent = <&tlmm>;
- interrupts = <5 2>;
- reg = <0x74>;
- };
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "Teltonika-RUTX10";
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "Teltonika-RUTX10";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4018-rutx.dtsi"
-
-/ {
- model = "Teltonika RUTX50";
- compatible = "teltonika,rutx50";
-
- aliases {
- led-boot = &led_rssi0;
- led-failsafe = &led_rssi0;
- led-running = &led_rssi0;
- led-upgrade = &led_rssi0;
- label-mac-device = &gmac;
- };
-
- soc {
- gpio-export {
- compatible = "gpio-export";
- #size-cells = <0>;
-
- gpio_modem_reset {
- gpio-export,name = "modem_reset";
- gpio-export,output = <0>;
- gpios = <&shift_io 8 GPIO_ACTIVE_HIGH>;
- };
-
- gpio_modem_power {
- gpio-export,name = "modem_power";
- gpio-export,output = <0>;
- gpios = <&shift_io 9 GPIO_ACTIVE_HIGH>;
- };
-
- gpio_out_1 {
- gpio-export,name = "sim-select";
- /* 0 = SIM1 ; 1 = SIM2 */
- gpio-export,output = <0>;
- gpios = <&shift_io 10 GPIO_ACTIVE_HIGH>;
- };
-
- gpio_in_1 {
- gpio-export,name = "sim-detect";
- gpio-export,input = <0>;
- gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led-0 {
- label = "green:sim1";
- gpios = <&shift_io 14 GPIO_ACTIVE_HIGH>;
- };
-
- led-1 {
- label = "green:sim2";
- gpios = <&shift_io 15 GPIO_ACTIVE_HIGH>;
- };
-
- led-2 {
- label = "green:eth";
- gpios = <&shift_io 6 GPIO_ACTIVE_HIGH>;
- };
-
- led-3 {
- label = "green:wifi";
- gpios = <&shift_io 7 GPIO_ACTIVE_HIGH>;
- };
-
- led-4 {
- label = "green:3g";
- gpios = <&shift_io 5 GPIO_ACTIVE_HIGH>;
- };
-
- led-5 {
- label = "green:4g";
- gpios = <&shift_io 4 GPIO_ACTIVE_HIGH>;
- };
-
- led-6 {
- label = "green:5g";
- gpios = <&shift_io 3 GPIO_ACTIVE_HIGH>;
- };
-
- led_rssi0: led-7 {
- label = "green:rssi0";
- gpios = <&shift_io 0 GPIO_ACTIVE_HIGH>;
- };
-
- led-8 {
- label = "green:rssi1";
- gpios = <&shift_io 1 GPIO_ACTIVE_HIGH>;
- };
-
- led-9 {
- label = "green:rssi2";
- gpios = <&shift_io 2 GPIO_ACTIVE_HIGH>;
- };
-
- led-10 {
- label = "green:wifi2g";
- gpios = <&shift_io 12 GPIO_ACTIVE_HIGH>;
- };
-
- led-11 {
- label = "green:wifi5g";
- gpios = <&shift_io 13 GPIO_ACTIVE_HIGH>;
- };
- };
-
- spi-gpio {
- compatible = "spi-gpio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- gpio-sck = <&tlmm 1 GPIO_ACTIVE_HIGH>;
- gpio-mosi = <&tlmm 3 GPIO_ACTIVE_HIGH>;
- cs-gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
- num-chipselects = <1>;
-
- shift_io: shift_io@0 {
- compatible = "fairchild,74hc595";
- reg = <0>;
- gpio-controller;
- #gpio-cells = <2>;
- /* Attn: This is specific to RUTX50 in Teltonika GPL */
- registers-number = <2>;
- spi-max-frequency = <10000000>;
- };
- };
- };
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "Teltonika-RUTX10";
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "Teltonika-RUTX10";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport1 {
- status = "okay";
-
- label = "lan1";
-};
-
-&swport2 {
- status = "okay";
-
- label = "lan2";
-};
-
-&swport3 {
- status = "okay";
-
- label = "lan3";
-};
-
-&swport4 {
- status = "okay";
-
- label = "lan4";
-};
-
-&swport5 {
- status = "okay";
-
- label = "wan";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/* Copyright (c) 2020, Robert Marko <robimarko@gmail.com> */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "MikroTik SXTsq 5 ac (RBSXTsqG-5acD)";
- compatible = "mikrotik,sxtsq-5-ac";
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x10000000>;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- aliases {
- led-boot = &led_user;
- led-failsafe = &led_user;
- led-running = &led_user;
- led-upgrade = &led_user;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
- counter@4a1000 {
- compatible = "qcom,qca-gcnt";
- reg = <0x4a1000 0x4>;
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII_RGMII4>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
- default-state = "keep";
- panic-indicator;
- };
-
- led_user: user {
- label = "green:user";
- gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
- };
-
- rssilow {
- label = "green:rssilow";
- gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;
- };
-
- rssimediumlow {
- label = "green:rssimediumlow";
- gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
- };
-
- rssimedium {
- label = "green:rssimedium";
- gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
- };
-
- rssimediumhigh {
- label = "green:rssimediumhigh";
- gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
- };
-
- rssihigh {
- label = "green:rssihigh";
- gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pin {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <2>;
- bias-disable;
- };
- pin_cs {
- function = "gpio";
- pins = "gpio54";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- status = "okay";
-
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- reg = <0>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <40000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "Qualcomm";
- reg = <0x0 0x80000>;
- read-only;
- };
-
- partition@80000 {
- compatible = "mikrotik,routerboot-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
- label = "RouterBoot";
- reg = <0x80000 0x80000>;
-
- hard_config {
- read-only;
- };
-
- dtb_config {
- read-only;
- };
-
- soft_config {
- };
- };
-
- partition@100000 {
- compatible = "mikrotik,minor";
- label = "firmware";
- reg = <0x100000 0xf00000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- status = "okay";
-
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&wifi1 {
- status = "okay";
-
- qcom,ath10k-calibration-variant = "MikroTik-SXTsq-5-ac";
-};
-
-&mdio {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-
- /delete-property/ psgmii-ethphy;
-};
-
-&swport5 {
- status = "okay";
-
- label = "lan";
- phy-mode = "rgmii";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/* Copyright (c) 2020, Robert Marko <robimarko@gmail.com> */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "Netgear WAC510";
- compatible = "netgear,wac510";
-
- aliases {
- led-boot = &led_power_amber;
- led-failsafe = &led_power_amber;
- led-running = &led_power_green;
- led-upgrade = &led_power_amber;
- ethernet1 = &swport5;
- };
-
- chosen {
- bootargs-append = " root=/dev/ubiblock0_1";
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- counter@4a1000 {
- compatible = "qcom,qca-gcnt";
- reg = <0x4a1000 0x4>;
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- led_spi {
- compatible = "spi-gpio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- sck-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
- mosi-gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
- num-chipselects = <0>;
-
- ssr: ssr@0 {
- compatible = "fairchild,74hc595";
- reg = <0>;
- gpio-controller;
- #gpio-cells = <2>;
- registers-number = <1>;
- spi-max-frequency = <1000000>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_power_amber: led-0 {
- color = <LED_COLOR_ID_AMBER>;
- function = LED_FUNCTION_POWER;
- gpios = <&ssr 6 GPIO_ACTIVE_LOW>;
- panic-indicator;
- };
-
- led_power_green: led-1 {
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_POWER;
- gpios = <&ssr 5 GPIO_ACTIVE_LOW>;
- };
-
- led-2 {
- /* 2.4GHz blue - activity */
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_WLAN;
- function-enumerator = <0>;
- gpios = <&ssr 4 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy0tpt";
- };
-
- led-3 {
- /* 2.4GHz green - link */
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_WLAN;
- function-enumerator = <0>;
- gpios = <&ssr 3 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy0radio";
- };
-
- led-4 {
- /* 5GHz blue - activity */
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_WLAN;
- function-enumerator = <1>;
- gpios = <&ssr 2 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy1tpt";
- };
-
- led-5 {
- /* 5GHz green - link */
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_WLAN;
- function-enumerator = <1>;
- gpios = <&ssr 1 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy1radio";
- };
-
- led-6 {
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_ACTIVITY;
- gpios = <&ssr 0 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&tlmm {
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio53";
- function = "mdio";
- bias-pull-up;
- };
-
- mux_2 {
- pins = "gpio52";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
-
- pinmux_cs {
- function = "gpio";
- pins = "gpio54", "gpio59";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- status = "okay";
-
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,
- <&tlmm 59 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- spi-max-frequency = <50000000>;
- reg = <0>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
-
- partition@40000 {
- label = "0:MIBIB";
- reg = <0x00040000 0x00020000>;
- read-only;
- };
-
- partition@60000 {
- label = "0:QSEE";
- reg = <0x00060000 0x00060000>;
- read-only;
- };
-
- partition@c0000 {
- label = "0:CDT";
- reg = <0x000c0000 0x00010000>;
- read-only;
- };
-
- partition@d0000 {
- label = "0:DDRPARAMS";
- reg = <0x000d0000 0x00010000>;
- read-only;
- };
-
- partition@e0000 {
- label = "0:APPSBLENV";
- reg = <0x000e0000 0x00010000>;
- };
-
- partition@f0000 {
- label = "0:APPSBL";
- reg = <0x000f0000 0x000f0000>;
- read-only;
- };
-
- partition@1e0000 {
- label = "0:MANUDATA";
- reg = <0x001e0000 0x00010000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_manudata_6: macaddr@6 {
- compatible = "mac-base";
- reg = <0x6 0x6>;
- #nvmem-cell-cells = <1>;
- };
- };
- };
-
- partition@1f0000 {
- label = "0:ART";
- reg = <0x001f0000 0x00010000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
- };
- };
-
- nand@1 {
- compatible = "spi-nand";
- reg = <1>;
- spi-max-frequency = <48000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "rootfs";
- reg = <0x00000000 0x03800000>;
- };
-
- partition@3800000 {
- label = "rootfs_1";
- reg = <0x03800000 0x03800000>;
- };
-
- partition@7000000 {
- label = "var_config";
- reg = <0x07000000 0x00f00000>;
- read-only;
- };
-
- partition@7f00000 {
- label = "Oops_log";
- reg = <0x07f00000 0x000c0000>;
- read-only;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- status = "okay";
-
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
-
- label = "lan";
-};
-
-&swport5 {
- status = "okay";
-};
-
-&mdio {
- status = "okay";
-
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- reset-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>;
- reset-delay-us = <2000>;
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_1000>, <&macaddr_manudata_6 0>;
- qcom,ath10k-calibration-variant = "Netgear-WAC510";
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_5000>, <&macaddr_manudata_6 16>;
- qcom,ath10k-calibration-variant = "Netgear-WAC510";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/* Copyright (c) 2022, Alexander Couzens <lynxis@fe80.eu> */
-
-#include "qcom-ipq4018-wap-ac.dtsi"
-
-/ {
- model = "MikroTik wAP ac LTE";
- compatible = "mikrotik,wap-ac-lte";
-
- soc {
- tcsr@194b000 {
- /* select hostmode */
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
-
- dwc3@8a00000 {
- phys = <&usb3_hs_phy>;
- phy-names = "usb2-phy";
- };
- };
- };
-};
-
-&tlmm {
- enable-usb-power {
- gpio-hog;
- gpios = <2 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "enable USB power";
- };
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb3 {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/* Copyright (c) 2020, Robert Marko <robimarko@gmail.com> */
-
-#include "qcom-ipq4018-wap-ac.dtsi"
-
-/ {
- model = "MikroTik wAP ac";
- compatible = "mikrotik,wap-ac";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/* Copyright (c) 2020, Robert Marko <robimarko@gmail.com> */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- memory {
- device_type = "memory";
- reg = <0x80000000 0x08000000>;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- aliases {
- led-boot = &led_user;
- led-failsafe = &led_user;
- led-running = &led_user;
- led-upgrade = &led_user;
- };
-
- soc {
- counter@4a1000 {
- compatible = "qcom,qca-gcnt";
- reg = <0x4a1000 0x4>;
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
- default-state = "keep";
- };
-
- led_user: user {
- label = "green:user";
- gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
- panic-indicator;
- };
- };
-};
-
-&prng {
- status = "okay";
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pin {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <2>;
- bias-disable;
- };
- pin_cs {
- function = "gpio";
- pins = "gpio54";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- status = "okay";
-
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- reg = <0>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <40000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "Qualcomm";
- reg = <0x0 0x80000>;
- read-only;
- };
-
- partition@80000 {
- compatible = "mikrotik,routerboot-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
- label = "RouterBoot";
- reg = <0x80000 0x80000>;
-
- hard_config {
- read-only;
- size = <0x2000>;
- };
-
- dtb_config {
- read-only;
- };
-
- soft_config {
- };
- };
-
- partition@100000 {
- compatible = "mikrotik,minor";
- label = "firmware";
- reg = <0x100000 0xf00000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- status = "okay";
-
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&crypto {
- status = "okay";
-};
-
-&watchdog {
- status = "okay";
-};
-
-&mdio {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
- label = "sw-eth2";
-};
-
-&swport5 {
- status = "okay";
- label = "sw-eth1";
-};
-
-&wifi0 {
- status = "okay";
-
- qcom,ath10k-calibration-variant = "MikroTik-wAP-ac";
-};
-
-&wifi1 {
- status = "okay";
-
- qcom,ath10k-calibration-variant = "MikroTik-wAP-ac";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/* Copyright (c) 2022, Alexander Couzens <lynxis@fe80.eu> */
-
-#include "qcom-ipq4018-wap-ac.dtsi"
-
-/ {
- model = "MikroTik wAP R ac";
- compatible = "mikrotik,wap-r-ac";
-
- soc {
- tcsr@194b000 {
- /* select hostmode */
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
-
- dwc3@8a00000 {
- phys = <&usb3_hs_phy>;
- phy-names = "usb2-phy";
- };
- };
- };
-};
-
-&tlmm {
- enable-usb-power {
- gpio-hog;
- gpios = <2 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "enable USB power";
- };
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb3 {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/ {
- model = "Linksys WHW01";
- compatible = "linksys,whw01";
-
- aliases {
- serial0 = &blsp1_uart1;
- led-boot = &led_system_blue;
- led-running = &led_system_blue;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- bootargs-append = " root=/dev/ubiblock0_0";
- };
-
- soc {
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- ess_tcsr@1953000 {
- status = "okay";
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_i2c3 {
- status = "okay";
- pinctrl-0 = <&i2c_0_pins>;
- pinctrl-1 = <&i2c_0_pins>;
- pinctrl-names = "i2c_active", "i2c_sleep";
-
- leds@62 {
- compatible = "nxp,pca9633";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x62>;
-
- /* RGB? */
- led@0 {
- reg = <0>;
- color = <LED_COLOR_ID_RED>;
- function = LED_FUNCTION_POWER;
- };
-
- led@1 {
- reg = <1>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_POWER;
- };
-
- led_system_blue: led@2 {
- reg = <2>;
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_POWER;
- linux,default-trigger = "default-on";
- };
- };
-};
-
-&blsp1_spi1 {
- status = "okay";
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 4 GPIO_ACTIVE_HIGH>;
-
- nor@0 {
- reg = <0>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x0 0x40000>;
- read-only;
- };
-
- partition@40000 {
- label = "0:MIBIB";
- reg = <0x40000 0x20000>;
- read-only;
- };
-
- partition@60000 {
- label = "0:QSEE";
- reg = <0x60000 0x60000>;
- read-only;
- };
-
- partition@c0000 {
- label = "0:CDT";
- reg = <0xc0000 0x10000>;
- read-only;
- };
-
- partition@d0000 {
- label = "APPSBL";
- reg = <0xd0000 0xa0000>;
- read-only;
- };
-
- partition@170000 {
- label = "0:ART";
- reg = <0x170000 0x10000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- partition@180000 {
- label = "u_env";
- reg = <0x180000 0x40000>;
- };
-
- partition@1c0000 {
- label = "s_env";
- reg = <0x1c0000 0x20000>;
- };
-
- partition@1e0000 {
- label = "devinfo";
- reg = <0x1e0000 0x20000>;
- read-only;
- };
- };
- };
-
- nand@1 {
- reg = <1>;
- compatible = "spi-nand";
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "kernel";
- reg = <0x0000000 0x5000000>;
- };
-
- partition@600000 {
- label = "rootfs";
- reg = <0x0600000 0x4a00000>;
- };
-
- partition@5000000 {
- label = "alt_kernel";
- reg = <0x5000000 0x5000000>;
- };
-
- partition@5600000 {
- label = "alt_rootfs";
- reg = <0x5600000 0x4a00000>;
- };
-
- partition@a000000 {
- label = "sysdiag";
- reg = <0xa000000 0x0200000>;
- read-only;
- };
-
- partition@a200000 {
- label = "syscfg";
- reg = <0xa200000 0x5e00000>;
- read-only;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&mdio {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- phy-reset-gpio = <&tlmm 62 GPIO_ACTIVE_HIGH>;
-};
-
-&tlmm {
- mdio_pins: mdio_pinmux {
- mux_mdio {
- pins = "gpio53";
- function = "mdio";
- bias-pull-up;
- };
-
- mux_mdc {
- pins = "gpio52";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- };
-
- pinmux_cs {
- function = "gpio";
- pins = "gpio54", "gpio4";
- };
-
- pinconf {
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
-
- pinconf_cs {
- pins = "gpio54", "gpio4";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-
- i2c_0_pins: i2c_0_pinmux {
- mux {
- function = "blsp_i2c0";
- pins = "gpio58", "gpio59";
- bias-disable;
- };
- };
-
- reset_pinmux {
- mux {
- pins = "gpio63";
- bias-pull-up;
- };
- };
-};
-
-&usb2 {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&usb3 {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&watchdog {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "linksys-whw01-v1";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "linksys-whw01-v1";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
- label = "eth1";
-};
-
-&swport5 {
- status = "okay";
- label = "eth2";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "Pakedge WR-1";
- compatible = "pakedge,wr-1";
-
- aliases {
- label-mac-device = &gmac;
- led-boot = &led_power;
- led-failsafe = &led_power;
- led-running = &led_power;
- led-upgrade = &led_power;
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&key_pins>;
- pinctrl-names = "default";
-
- reset {
- label = "reset";
- gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- led_power: power {
- gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_POWER;
- };
-
- wlan2g {
- gpios = <&tlmm 1 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_WLAN;
- linux,default-trigger = "phy0tpt";
- };
-
- wlan5g {
- gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_WLAN;
- linux,default-trigger = "phy1tpt";
- };
- };
-
- soc {
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- status = "okay";
-
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x0000000 0x0040000>;
- read-only;
- };
-
- partition@40000 {
- label = "0:MIBIB";
- reg = <0x0040000 0x0020000>;
- read-only;
- };
-
- partition@60000 {
- label = "0:QSEE";
- reg = <0x0060000 0x0060000>;
- read-only;
- };
-
- partition@c0000 {
- label = "0:CDT";
- reg = <0x00c0000 0x0010000>;
- read-only;
- };
-
- partition@d0000 {
- label = "0:DDRPARAMS";
- reg = <0x00d0000 0x0010000>;
- read-only;
- };
-
- partition@e0000 {
- label = "0:APPSBLENV";
- reg = <0x00e0000 0x0010000>;
- read-only;
- };
-
- partition@f0000 {
- label = "0:APPSBL";
- reg = <0x00f0000 0x0080000>;
- read-only;
- };
-
- partition@170000 {
- label = "0:ART";
- reg = <0x0170000 0x0010000>;
- read-only;
- };
-
- partition@180000 {
- label = "firmware";
- reg = <0x0180000 0x1e80000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- status = "okay";
-
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
-};
-
-&crypto {
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&mdio {
- status = "okay";
-};
-
-&prng {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport1 {
- status = "okay";
-
- label = "lan4";
-};
-
-&swport2 {
- status = "okay";
-
- label = "lan3";
-};
-
-&swport3 {
- status = "okay";
-
- label = "lan2";
-};
-
-&swport4 {
- status = "okay";
-
- label = "lan1";
-};
-
-&swport5 {
- status = "okay";
-};
-
-&tlmm {
- key_pins: key_pinmux {
- mux {
- function = "gpio";
- pins = "gpio59";
- bias-pull-up;
- };
- };
-
- led_pins: led_pinmux {
- mux {
- function = "gpio";
- pins = "gpio0", "gpio1", "gpio2";
- bias-none;
- drive-strength = <2>;
- output-low;
- };
- };
-
- serial_pins: serial_pinmux {
- mux {
- function = "blsp_uart0";
- pins = "gpio60", "gpio61";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- mux {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- bias-disable;
- drive-strength = <12>;
- };
-
- mux_cs {
- function = "gpio";
- pins = "gpio54";
- bias-disable;
- drive-strength = <2>;
- output-high;
- };
- };
-};
-
-&usb2 {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&watchdog {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
-
- qcom,ath10k-calibration-variant = "Pakedge-WR-1";
-};
-
-&wifi1 {
- status = "okay";
-
- qcom,ath10k-calibration-variant = "Pakedge-WR-1";
-};
+++ /dev/null
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
- * Copyright (c) 2018, David Bauer <mail@david-bauer.net>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "ZyXEL WRE6606";
- compatible = "zyxel,wre6606";
-
- aliases {
- led-boot = &power;
- led-failsafe = &power;
- led-running = &power;
- led-upgrade = &power;
- };
-
- chosen {
- bootargs-append = " mtdparts=";
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- wps {
- function = LED_FUNCTION_WPS;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
- };
-
- wlan5g_green {
- label = "green:wlan5g";
- gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
- };
-
- power: power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
- };
-
- wlan5g_red {
- label = "red:wlan5g";
- gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
- };
-
- wlan2g_red {
- label = "red:wlan2g";
- gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;
- };
-
- wlan2g_green {
- label = "green:wlan2g";
- gpios = <&tlmm 59 GPIO_ACTIVE_HIGH>;
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- wps {
- label = "wps";
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- };
- };
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pin {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
- pin_cs {
- function = "gpio";
- pins = "gpio54";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
- mx25l12805d@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition0@0 {
- label = "SBL1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
-
- partition1@40000 {
- label = "MIBIB";
- reg = <0x00040000 0x00020000>;
- read-only;
- };
-
- partition2@60000 {
- label = "QSEE";
- reg = <0x00060000 0x00060000>;
- read-only;
- };
-
- partition3@c0000 {
- label = "CDT";
- reg = <0x000c0000 0x00010000>;
- read-only;
- };
-
- partition4@d0000 {
- label = "DDRPARAMS";
- reg = <0x000d0000 0x00010000>;
- read-only;
- };
-
- partition5@E0000 {
- label = "APPSBLENV";
- reg = <0x000e0000 0x00010000>;
- read-only;
- };
-
- partition6@F0000 {
- label = "APPSBL";
- reg = <0x000f0000 0x00080000>;
- read-only;
- };
-
- partition7@170000 {
- label = "ART";
- reg = <0x00170000 0x00010000>;
- read-only;
- };
-
- partition8@180000 {
- compatible = "denx,fit";
- label = "firmware";
- reg = <0x00180000 0x00ce0000>;
- };
-
- partition9@e60000 {
- label = "manufacture";
- reg = <0x00e60000 0x00050000>;
- read-only;
- };
-
- partition10@eb0000 {
- label = "storage";
- reg = <0x00eb0000 0x00150000>;
- read-only;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "ZyXEL-WRE6606";
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "ZyXEL-WRE6606";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "Luma Home WRTQ-329ACN";
- compatible = "luma,wrtq-329acn";
-
- i2c-gpio {
- compatible = "i2c-gpio";
- sda-gpios = <&tlmm 1 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
- scl-gpios = <&tlmm 0 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- /* No driver exists */
- led_ring@48 {
- compatible = "ti,msp430";
- reg = <0x48>;
- };
-
- eeprom@50 {
- compatible = "atmel,24c16";
- reg = <0x50>;
- pagesize = <16>;
- read-only;
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2@60f8800 {
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-
-&blsp1_spi1 {
- status = "okay";
-
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>,
- <&tlmm 59 GPIO_ACTIVE_HIGH>;
- pinctrl-0 = <&spi0_pins>;
- pinctrl-names = "default";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x000000 0x040000>;
- read-only;
- };
-
- partition@40000 {
- label = "0:MIBIB";
- reg = <0x040000 0x020000>;
- read-only;
- };
-
- partition@60000 {
- label = "0:QSEE";
- reg = <0x060000 0x060000>;
- read-only;
- };
-
- partition@c0000 {
- label = "0:CDT";
- reg = <0x0c0000 0x010000>;
- read-only;
- };
-
- partition@d0000 {
- label = "0:DDRPARAMS";
- reg = <0x0d0000 0x010000>;
- read-only;
- };
-
- partition@e0000 {
- label = "0:APPSBLENV";
- reg = <0x0e0000 0x010000>;
- };
-
- partition@f0000 {
- label = "0:APPSBL";
- reg = <0x0f0000 0x080000>;
- read-only;
- };
-
- partition@170000 {
- label = "0:ART";
- reg = <0x170000 0x010000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_art_0: macaddr@0{
- reg = <0x0000 0x0006>;
- };
-
- macaddr_art_6: macaddr@6{
- reg = <0x0006 0x0006>;
- };
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
- };
- };
-
- flash@1 {
- status = "okay";
-
- compatible = "spi-nand";
- reg = <1>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "ubi";
- reg = <0x0000000 0x8000000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- status = "okay";
-
- pinctrl-0 = <&serial0_pins>;
- pinctrl-names = "default";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-ðphy0 {
- status = "disabled";
-};
-
-ðphy1 {
- status = "disabled";
-};
-
-ðphy3 {
- status = "disabled";
-};
-
-&mdio {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport3 {
- status = "okay";
-
- label = "lan";
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_art_6>;
-};
-
-&swport5 {
- status = "okay";
-
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_art_0>;
-};
-
-&tlmm {
- serial0_pins: serial0_pinmux {
- mux {
- function = "blsp_uart0";
- pins = "gpio60", "gpio61";
- bias-disable;
- };
- };
-
- spi0_pins: spi0_pinmux {
- mux {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- bias-disable;
- drive-strength = <12>;
- };
-
- mux_cs {
- function = "gpio";
- pins = "gpio54", "gpio59";
- bias-disable;
- drive-strength = <2>;
- output-high;
- };
- };
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
- qcom,ath10k-calibration-variant = "Luma-WRTQ-329ACN";
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
- qcom,ath10k-calibration-variant = "Luma-WRTQ-329ACN";
-};
+++ /dev/null
-// SPDX-License-Identifier: ISC
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
- * Copyright (c) 2017-2018, Sven Eckelmann <sven.eckelmann@openmesh.com>
- */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "OpenMesh A62";
- compatible = "openmesh,a62";
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- tcsr@194b000 {
- /* select hostmode */
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2: usb2@60f8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART >;
- };
- };
-
- aliases {
- led-boot = &led_status_green;
- led-failsafe = &led_status_green;
- led-running = &led_status_green;
- led-upgrade = &led_status_green;
- label-mac-device = &swport4;
- };
-
- leds {
- compatible = "gpio-leds";
-
- status_red {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_RED>;
- gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>;
- };
-
- led_status_green: status_green {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
- };
-
- status_blue {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
- };
- };
-
- watchdog {
- compatible = "linux,wdt-gpio";
- gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
- hw_algo = "toggle";
- /* hw_margin_ms is actually 300s but driver limits it to 60s */
- hw_margin_ms = <60000>;
- always-running;
- };
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pin {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
- pin_cs {
- function = "gpio";
- pins = "gpio12";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-
- enable-usb-power {
- gpio-hog;
- gpios = <58 GPIO_ACTIVE_HIGH>;
- output-low;
- line-name = "enable USB2 power";
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- /* partitions are passed via bootloader */
- partitions {
- partition-art {
- label = "0:ART";
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_gmac0: macaddr@0 {
- reg = <0x0 0x6>;
- };
-
- macaddr_gmac1: macaddr@6 {
- reg = <0x6 0x6>;
- };
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
-
- precal_art_9000: precal@9000 {
- reg = <0x9000 0x2f20>;
- };
- };
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
- perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
- wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi2: wifi@1,0 {
- compatible = "qcom,ath10k";
- status = "okay";
- reg = <0x00010000 0 0 0 0>;
- qcom,ath10k-calibration-variant = "OM-A62";
- ieee80211-freq-limit = <5170000 5350000>;
-
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_9000>;
- };
- };
-};
-
-&mdio {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
- label = "ethernet1";
-
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_gmac0>;
-};
-
-&swport5 {
- status = "okay";
- label = "ethernet2";
-
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_gmac1>;
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "OM-A62";
-
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "OM-A62";
- ieee80211-freq-limit = <5470000 5875000>;
-
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "MobiPromo CM520-79F";
- compatible = "mobipromo,cm520-79f";
-
- aliases {
- led-boot = &led_sys;
- led-failsafe = &led_sys;
- led-running = &led_sys;
- led-upgrade = &led_sys;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
- reset-delay-us = <1000>;
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2@60f8800 {
- status = "okay";
-
- dwc3@6000000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- usb2_port1: port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
- };
- };
-
- usb3@8af8800 {
- status = "okay";
-
- dwc3@8a00000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- usb3_port1: port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
-
- usb3_port2: port@2 {
- reg = <2>;
- #trigger-source-cells = <0>;
- };
- };
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- led_spi {
- compatible = "spi-gpio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- sck-gpios = <&tlmm 40 GPIO_ACTIVE_HIGH>;
- mosi-gpios = <&tlmm 36 GPIO_ACTIVE_HIGH>;
- num-chipselects = <0>;
-
- led_gpio: led_gpio@0 {
- compatible = "fairchild,74hc595";
- reg = <0>;
- gpio-controller;
- #gpio-cells = <2>;
- registers-number = <1>;
- spi-max-frequency = <1000000>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- usb {
- function = LED_FUNCTION_USB;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 10 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "usbport";
- trigger-sources = <&usb3_port1>, <&usb3_port2>, <&usb2_port1>;
- };
-
- led_sys: can {
- label = "blue:can";
- gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;
- };
-
- wan {
- function = LED_FUNCTION_WAN;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&led_gpio 0 GPIO_ACTIVE_LOW>;
- };
-
- lan1 {
- label = "blue:lan1";
- gpios = <&led_gpio 1 GPIO_ACTIVE_LOW>;
- };
-
- lan2 {
- label = "blue:lan2";
- gpios = <&led_gpio 2 GPIO_ACTIVE_LOW>;
- };
-
- wlan2g {
- label = "blue:wlan2g";
- gpios = <&led_gpio 5 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy0tpt";
- };
-
- wlan5g {
- label = "blue:wlan5g";
- gpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy1tpt";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_uart1 {
- status = "okay";
-};
-
-&blsp1_uart2 {
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&nand {
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- nand@0 {
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SBL1";
- reg = <0x0 0x100000>;
- read-only;
- };
-
- partition@100000 {
- label = "MIBIB";
- reg = <0x100000 0x100000>;
- read-only;
- };
-
- partition@200000 {
- label = "BOOTCONFIG";
- reg = <0x200000 0x100000>;
- };
-
- partition@300000 {
- label = "QSEE";
- reg = <0x300000 0x100000>;
- read-only;
- };
-
- partition@400000 {
- label = "QSEE_1";
- reg = <0x400000 0x100000>;
- read-only;
- };
-
- partition@500000 {
- label = "CDT";
- reg = <0x500000 0x80000>;
- read-only;
- };
-
- partition@580000 {
- label = "CDT_1";
- reg = <0x580000 0x80000>;
- read-only;
- };
-
- partition@600000 {
- label = "BOOTCONFIG1";
- reg = <0x600000 0x80000>;
- };
-
- partition@680000 {
- label = "APPSBLENV";
- reg = <0x680000 0x80000>;
- };
-
- partition@700000 {
- label = "APPSBL";
- reg = <0x700000 0x200000>;
- read-only;
- };
-
- partition@900000 {
- label = "APPSBL_1";
- reg = <0x900000 0x200000>;
- read-only;
- };
-
- art: partition@b00000 {
- label = "ART";
- reg = <0xb00000 0x80000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- macaddr_art_1006: macaddr@1006 {
- reg = <0x1006 0x6>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
-
- macaddr_art_5006: macaddr@5006 {
- reg = <0x5006 0x6>;
- };
- };
- };
-
- partition@b80000 {
- label = "ubi";
- reg = <0xb80000 0x7480000>;
- };
- };
- };
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&tlmm {
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
-
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- nand_pins: nand_pins {
- pullups {
- pins = "gpio52", "gpio53", "gpio58",
- "gpio59";
- function = "qpic";
- bias-pull-up;
- };
-
- pulldowns {
- pins = "gpio54", "gpio55", "gpio56",
- "gpio57", "gpio60", "gpio61",
- "gpio62", "gpio63", "gpio64",
- "gpio65", "gpio66", "gpio67",
- "gpio68", "gpio69";
- function = "qpic";
- bias-pull-down;
- };
- };
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-
- nvmem-cells = <&macaddr_art_1006>;
- nvmem-cell-names = "mac-address";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport3 {
- status = "okay";
-
- label = "lan2";
-};
-
-&swport4 {
- status = "okay";
-
- label = "lan1";
-};
-
-&swport5 {
- status = "okay";
-
- nvmem-cells = <&macaddr_art_5006>;
- nvmem-cell-names = "mac-address";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
- qcom,ath10k-calibration-variant = "CM520-79F";
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
- qcom,ath10k-calibration-variant = "CM520-79F";
-};
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT
- *
- * Copyright (c) 2018 Peng Zhang <sd20@qxwlan.com>
- *
- */
-
-#include "qcom-ipq4019-e2600ac.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/ {
- model = "Qxwlan E2600AC c1";
- compatible = "qxwlan,e2600ac-c1";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
-
- flash@0 {
- reg = <0>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x0 0x40000>;
- read-only;
- };
- partition@40000 {
- label = "0:MIBIB";
- reg = <0x40000 0x20000>;
- read-only;
- };
- partition@60000 {
- label = "0:QSEE";
- reg = <0x60000 0x60000>;
- read-only;
- };
- partition@c0000 {
- label = "0:CDT";
- reg = <0xc0000 0x10000>;
- read-only;
- };
- partition@d0000 {
- label = "0:DDRPARAMS";
- reg = <0xd0000 0x10000>;
- read-only;
- };
- partition@e0000 {
- label = "0:APPSBLENV";
- reg = <0xe0000 0x10000>;
- read-only;
- };
- partition@f0000 {
- label = "0:APPSBL";
- reg = <0xf0000 0x80000>;
- read-only;
- };
- partition@170000 {
- label = "0:ART";
- reg = <0x170000 0x10000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_gmac0: macaddr@0 {
- reg = <0x0 0x6>;
- };
-
- macaddr_gmac1: macaddr@6 {
- reg = <0x6 0x6>;
- };
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
- partition@180000 {
- compatible = "denx,fit";
- label = "firmware";
- reg = <0x180000 0x1e80000>;
- };
- };
- };
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
- qcom,ath10k-calibration-variant = "Qxwlan-E2600AC-C1";
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
- qcom,ath10k-calibration-variant = "Qxwlan-E2600AC-C1";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
- label = "sw-eth1";
-
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_gmac0>;
-};
-
-&swport5 {
- status = "okay";
-
- label = "sw-eth2";
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_gmac1>;
-};
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT
- *
- * Copyright (c) 2018 Peng Zhang <sd20@qxwlan.com>
- *
- */
-
-#include "qcom-ipq4019-e2600ac.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/ {
- model = "Qxwlan E2600AC c2";
- compatible = "qxwlan,e2600ac-c2";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
-
- flash@0 {
- reg = <0>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x0 0x40000>;
- read-only;
- };
- partition@40000 {
- label = "0:MIBIB";
- reg = <0x40000 0x20000>;
- read-only;
- };
- partition@60000 {
- label = "0:QSEE";
- reg = <0x60000 0x60000>;
- read-only;
- };
- partition@c0000 {
- label = "0:CDT";
- reg = <0xc0000 0x10000>;
- read-only;
- };
- partition@d0000 {
- label = "0:DDRPARAMS";
- reg = <0xd0000 0x10000>;
- read-only;
- };
- partition@e0000 {
- label = "0:APPSBLENV";
- reg = <0xe0000 0x10000>;
- read-only;
- };
- partition@f0000 {
- label = "0:APPSBL";
- reg = <0xf0000 0x80000>;
- read-only;
- };
- partition@170000 {
- label = "0:ART";
- reg = <0x170000 0x10000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_gmac0: macaddr@0 {
- reg = <0x0 0x6>;
- };
-
- macaddr_gmac1: macaddr@6 {
- reg = <0x6 0x6>;
- };
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
- };
- };
-};
-
-&nand {
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- nand@0 {
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "ubi";
- reg = <0x00000000 0x04000000>;
- };
- };
- };
-};
-
-&tlmm {
- nand_pins: nand-pins {
-
- pullups {
- pins = "gpio53", "gpio58", "gpio59";
- function = "qpic";
- bias-pull-up;
- };
-
- pulldowns {
- pins = "gpio54", "gpio55", "gpio56",
- "gpio57", "gpio60", "gpio61",
- "gpio62", "gpio63", "gpio64",
- "gpio65", "gpio66", "gpio67",
- "gpio68", "gpio69";
- function = "qpic";
- bias-pull-down;
- };
- };
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
- qcom,ath10k-calibration-variant = "Qxwlan-E2600AC-C2";
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
- qcom,ath10k-calibration-variant = "Qxwlan-E2600AC-C2";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport2 {
- status = "okay";
- label = "sw-eth1";
-
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_gmac0>;
-};
-
-&swport4 {
- status = "okay";
- label = "sw-eth2";
-
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_gmac0>;
-};
-
-&swport5 {
- status = "okay";
-
- label = "sw-eth3";
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_gmac1>;
-};
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT
- *
- * Copyright (c) 2018 Peng Zhang <sd20@qxwlan.com>
- *
- */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
-
- model = "Qxwlan E2600AC";
- compatible = "qcom,ipq4019";
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x10000000>; /* 256MB */
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- /* select hostmode */
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2: usb2@60f8800 {
- status = "okay";
-
- dwc3@6000000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- usb2_port1: port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
- };
- };
-
- serial@78af000 {
- pinctrl-0 = <&serial_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- };
-
- serial@78b0000 {
- pinctrl-0 = <&serial_1_pins>;
- pinctrl-names = "default";
- status = "okay";
- };
-
- i2c@78b7000 { /* BLSP1 QUP2 */
- pinctrl-0 = <&i2c_0_pins>;
- pinctrl-names = "default";
-
- status = "okay";
- };
-
- usb3: usb3@8af8800 {
- status = "okay";
-
- dwc3@8a00000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- usb3_port1: port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
-
- usb3_port2: port@2 {
- reg = <2>;
- #trigger-source-cells = <0>;
- };
- };
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
-
- leds {
- compatible = "gpio-leds";
-
- led1 {
- label = "green:wlan0";
- gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
- };
-
- led2 {
- label = "green:wlan1";
- gpios = <&tlmm 36 GPIO_ACTIVE_LOW>;
- };
-
- led3 {
- function = LED_FUNCTION_USB;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
- trigger-sources = <&usb2_port1>, <&usb3_port1>, <&usb3_port2>;
- linux,default-trigger = "usbport";
- };
-
- led4 {
- label = "green:ctrl1";
- gpios = <&tlmm 51 GPIO_ACTIVE_LOW>;
- };
-
- led5 {
- label = "green:ctrl2";
- gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
- };
-
- led6 {
- label = "green:ctrl3";
- gpios = <&tlmm 31 GPIO_ACTIVE_LOW>;
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&tlmm {
- i2c_0_pins: i2c-0-pinmux {
- mux {
- pins = "gpio20", "gpio21";
- function = "blsp_i2c0";
- bias-disable;
- };
- };
-
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- serial_0_pins: serial0-pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- serial_1_pins: serial1_pinmux {
- mux {
- pins = "gpio8", "gpio9";
- function = "blsp_uart1";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
- pinmux_cs {
- function = "gpio";
- pins = "gpio12";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include <dt-bindings/leds/common.h>
-
-#include "qcom-ipq4019-xx8300.dtsi"
-
-/ {
- model = "Linksys EA8300 (Dallas)";
- compatible = "linksys,ea8300", "qcom,ipq4019";
-
-
- aliases {
- led-boot = &led_wps_amber;
- led-failsafe = &led_wps;
- led-running = &led_linksys;
- led-upgrade = &led_world;
- serial0 = &blsp1_uart1;
- };
-
-
- leds {
- compatible = "gpio-leds";
-
- // Retain node names from running OEM on EA8300
-
- // Front panel LEDs, top to bottom
-
- led_plug: diag {
- label = "amber:plug";
- gpios = <&tlmm 47 GPIO_ACTIVE_HIGH>;
- };
-
- led_world: internet {
- label = "amber:world";
- gpios = <&tlmm 49 GPIO_ACTIVE_HIGH>;
- };
-
- led_wps: wps {
- function = LED_FUNCTION_WPS;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
- };
-
- led_wps_amber: wps_amber {
- function = LED_FUNCTION_WPS;
- color = <LED_COLOR_ID_AMBER>;
- gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
- panic-indicator;
- };
-
- led_linksys: pwr {
- label = "white:linksys";
- gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
- };
-
- // On back panel, above USB socket
-
- led_usb: usb {
- function = LED_FUNCTION_USB;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
- trigger-sources = <&usb3_port1>, <&usb3_port2>,
- <&usb2_port1>;
- linux,default-trigger = "usbport";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- linux,code = <KEY_RESTART>;
- gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
- };
-
- wps {
- label = "wps";
- linux,code = <KEY_WPS_BUTTON>;
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "linksys-ea8300-fcc";
-};
-
-&wifi1 {
- status = "okay";
- ieee80211-freq-limit = <5170000 5330000>;
- qcom,ath10k-calibration-variant = "linksys-ea8300-fcc";
-};
-
-&wifi2 {
- status = "okay";
- ieee80211-freq-limit = <5490000 5835000>;
- qcom,ath10k-calibration-variant = "linksys-ea8300-fcc";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "EnGenius EAP2200";
- compatible = "engenius,eap2200";
-
- aliases {
- led-boot = &led_power;
- led-failsafe = &led_power;
- led-running = &led_power;
- led-upgrade = &led_power;
- };
-
- keys {
- compatible = "gpio-keys";
-
- wps {
- label = "wps";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_power: power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_AMBER>;
- gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
- };
-
- lan1 {
- label = "blue:lan1";
- gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
- };
-
- lan2 {
- label = "blue:lan2";
- gpios = <&tlmm 45 GPIO_ACTIVE_LOW>;
- };
-
- wlan2g {
- label = "blue:wlan2g";
- gpios = <&tlmm 46 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy0tpt";
- };
-
- wlan5g {
- label = "yellow:wlan5g";
- gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy1tpt";
- };
-
- wlan5g2 {
- label = "yellow:wlan5g2";
- gpios = <&tlmm 48 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy2tpt";
- };
-
- mode {
- label = "blue:mode";
- gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
- };
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition0@0 {
- label = "0:SBL1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
- partition1@40000 {
- label = "0:MIBIB";
- reg = <0x00040000 0x00020000>;
- read-only;
- };
- partition2@60000 {
- label = "0:QSEE";
- reg = <0x00060000 0x00060000>;
- read-only;
- };
- partition3@c0000 {
- label = "0:CDT";
- reg = <0x000c0000 0x00010000>;
- read-only;
- };
- partition4@d0000 {
- label = "0:DDRPARAMS";
- reg = <0x000d0000 0x00010000>;
- read-only;
- };
- partition5@e0000 {
- label = "0:APPSBLENV";
- reg = <0x000e0000 0x00010000>;
- read-only;
- };
- partition6@f0000 {
- label = "0:APPSBL";
- reg = <0x000f0000 0x00080000>;
- read-only;
- };
- partition7@170000 {
- label = "0:ART";
- reg = <0x00170000 0x00010000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
-
- precal_art_9000: precal@9000 {
- reg = <0x9000 0x2f20>;
- };
- };
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&nand {
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- nand@0 {
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "rootfs1";
- reg = <0x00000000 0x04000000>;
- };
- partition@40000000 {
- label = "ubi";
- reg = <0x04000000 0x04000000>;
- };
-
- };
- };
-};
-
-&pcie0 {
- status = "okay";
- perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
- wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi2: wifi@1,0 {
- compatible = "qcom,ath10k";
- reg = <0x00010000 0 0 0 0>;
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_9000>;
- ieee80211-freq-limit = <5470000 5875000>;
- qcom,ath10k-calibration-variant = "EnGenius-EAP2200";
- };
- };
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&tlmm {
- nand_pins: nand_pins {
- pullups {
- pins = "gpio53", "gpio58", "gpio59";
- function = "qpic";
- bias-pull-up;
- };
-
- pulldowns {
- pins = "gpio54", "gpio55", "gpio56",
- "gpio57", "gpio60", "gpio61",
- "gpio62", "gpio63", "gpio64",
- "gpio65", "gpio66", "gpio67",
- "gpio68", "gpio69";
- function = "qpic";
- bias-pull-down;
- };
- };
-
- serial_0_pins: serial_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
- pinmux_cs {
- function = "gpio";
- pins = "gpio12";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
- qcom,ath10k-calibration-variant = "EnGenius-EAP2200";
-};
-
-&wifi1 {
- status = "okay";
- ieee80211-freq-limit = <5170000 5350000>;
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
- qcom,ath10k-calibration-variant = "EnGenius-EAP2200";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "AVM FRITZ!Box 7530";
- compatible = "avm,fritzbox-7530";
-
- chosen {
- bootargs-append = " coherent_pool=4M";
- };
-
- aliases {
- led-boot = &power_green;
- led-failsafe = &info_red;
- led-running = &power_green;
- led-upgrade = &info_red;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb3@8af8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- wlan {
- label = "wlan";
- gpios = <&tlmm 42 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RFKILL>;
- };
-
- wps {
- label = "wps";
- gpios = <&tlmm 41 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- };
-
- dect {
- label = "dect";
- gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_PHONE>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- info_red: info_red {
- label = "red:info";
- gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
- };
-
- info {
- label = "green:info";
- gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
- };
-
- wlan {
- function = LED_FUNCTION_WLAN;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 34 GPIO_ACTIVE_LOW>;
- };
-
- fon {
- label = "green:fon";
- gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
- };
-
- power_green: power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
- };
-
- wps {
- function = LED_FUNCTION_WPS;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 45 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&tlmm {
- serial_0_pins: serial_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- nand_pins: nand_pins {
- pullups {
- pins = "gpio53", "gpio58", "gpio59";
- function = "qpic";
- bias-pull-up;
- };
-
- pulldowns {
- pins = "gpio54", "gpio55", "gpio56",
- "gpio57", "gpio60", "gpio61",
- "gpio62", "gpio63", "gpio64",
- "gpio65", "gpio66", "gpio67",
- "gpio68", "gpio69";
- function = "qpic";
- bias-pull-down;
- };
- };
-
- usb-power {
- line-name = "enable USB3 power";
- gpios = <49 GPIO_ACTIVE_HIGH>;
- gpio-hog;
- output-high;
- };
-};
-
-&nand {
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- nand@0 {
- /delete-property/ nand-ecc-strength;
- /delete-property/ nand-ecc-step-size;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SBL1";
- reg = <0x000000 0x80000>;
- read-only;
- };
-
- partition@80000 {
- label = "MIBIB";
- reg = <0x080000 0x80000>;
- read-only;
- };
-
- partition@100000 {
- label = "QSEE";
- reg = <0x100000 0x80000>;
- read-only;
- };
-
- partition@180000 {
- label = "CDT";
- reg = <0x180000 0x40000>;
- read-only;
- };
-
- partition@1c0000 {
- label = "QSEE_B";
- reg = <0x1c0000 0x80000>;
- read-only;
- };
-
- partition@240000 {
- label = "urlader0";
- reg = <0x240000 0x40000>;
- read-only;
- };
-
- partition@280000 {
- label = "urlader1";
- reg = <0x280000 0x40000>;
- read-only;
- };
-
- partition@2c0000 {
- label = "nand-tffs";
- reg = <0x2c0000 0x840000>;
- read-only;
- };
-
- partition@b00000 {
- /* 'kernel1' in AVM firmware */
- label = "uboot0";
- reg = <0xb00000 0x400000>;
- };
-
- partition@f00000 {
- /* 'kernel2' in AVM firmware */
- label = "uboot1";
- reg = <0xf00000 0x400000>;
- };
-
- partition@1300000 {
- label = "ubi";
- reg = <0x1300000 0x6d00000>;
- };
- };
- };
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport1 {
- status = "okay";
-};
-
-&swport2 {
- status = "okay";
-};
-
-&swport3 {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "AVM-FRITZBox-7530";
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "AVM-FRITZBox-7530";
-};
-
-&pcie0 {
- status = "okay";
-
- perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
- wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- dsl@1,0 {
- compatible = "intel,vrx518";
- status = "okay";
- reg = <0x00010000 0 0 0 0>;
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "AVM FRITZ!Repeater 1200";
- compatible = "avm,fritzrepeater-1200";
-
- aliases {
- led-boot = &power_green;
- led-failsafe = &power_red;
- led-running = &power_green;
- led-upgrade = &power_red;
- label-mac-device = &wifi0;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
-
- ethphy: ethernet-phy@0 {
- reg = <0x0>;
- };
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII_RGMII5>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- key {
- compatible = "gpio-keys";
-
- wps {
- label = "WPS button";
- gpios = <&tlmm 10 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- power_red: power_red {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_RED>;
- gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
- };
-
- power_green: power_green {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
- };
-
- power_yellow {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_YELLOW>;
- gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&tlmm {
- serial_0_pins: serial_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- nand_pins: nand_pins {
- pullups {
- pins = "gpio53", "gpio58", "gpio59";
- function = "qpic";
- bias-pull-up;
- };
-
- pulldowns {
- pins = "gpio54", "gpio55", "gpio56",
- "gpio57", "gpio60", "gpio61",
- "gpio62", "gpio63", "gpio64",
- "gpio65", "gpio66", "gpio67",
- "gpio68", "gpio69";
- function = "qpic";
- bias-pull-down;
- };
- };
-
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- phy-reset {
- line-name = "PHY-reset";
- gpios = <19 GPIO_ACTIVE_HIGH>;
- gpio-hog;
- output-high;
- };
-
- phy-reset-2 {
- line-name = "PHY-reset-2";
- gpios = <47 GPIO_ACTIVE_HIGH>;
- gpio-hog;
- output-high;
- };
-};
-
-&nand {
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- nand@0 {
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SBL1";
- reg = <0x0 0x80000>;
- read-only;
- };
-
- partition@80000 {
- label = "MIBIB";
- reg = <0x80000 0x80000>;
- read-only;
- };
-
- partition@100000 {
- label = "QSEE";
- reg = <0x100000 0x80000>;
- read-only;
- };
-
- partition@180000 {
- label = "CDT";
- reg = <0x180000 0x40000>;
- read-only;
- };
-
- partition@1c0000 {
- label = "QSEE_B";
- reg = <0x1c0000 0x80000>;
- read-only;
- };
-
- partition@240000 {
- label = "urlader0";
- reg = <0x240000 0x40000>;
- read-only;
- };
-
- partition@280000 {
- label = "urlader1";
- reg = <0x280000 0x40000>;
- read-only;
- };
-
- partition@2c0000 {
- label = "nand-tffs";
- reg = <0x2c0000 0x840000>;
- read-only;
- };
-
- partition@b00000 {
- /* 'kernel1' in AVM firmware */
- label = "uboot0";
- reg = <0xb00000 0x400000>;
- };
-
- partition@f00000 {
- /* 'kernel2' in AVM firmware */
- label = "uboot1";
- reg = <0xf00000 0x400000>;
- };
-
- partition@1300000 {
- label = "ubi";
- reg = <0x1300000 0x6d00000>;
- };
- };
- };
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "AVM-FRITZRepeater-1200";
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "AVM-FRITZRepeater-1200";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-
- /delete-property/ psgmii-ethphy;
-};
-
-&swport5 {
- status = "okay";
-
- label = "lan";
- phy-handle = <ðphy>;
- phy-mode = "rgmii-id";
-};
-
-ðphy1 {
- status = "disabled";
-};
-
-ðphy2 {
- status = "disabled";
-};
-
-ðphy3 {
- status = "disabled";
-};
-
-ðphy4 {
- status = "disabled";
-};
-
-&psgmiiphy {
- status = "disabled";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "AVM FRITZ!Repeater 3000";
- compatible = "avm,fritzrepeater-3000";
-
- aliases {
- led-boot = &power_led;
- led-failsafe = &power_led;
- led-running = &power_led;
- led-upgrade = &power_led;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- key {
- compatible = "gpio-keys";
-
- connect {
- label = "Connect";
- gpios = <&tlmm 10 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- connect_red {
- label = "red:connect";
- gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
- };
-
- connect_green {
- label = "green:connect";
- gpios = <&tlmm 31 GPIO_ACTIVE_LOW>;
- };
-
- connect_blue {
- label = "blue:connect";
- gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
- };
-
- power_led: power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&tlmm {
- serial_0_pins: serial_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- nand_pins: nand_pins {
- pullups {
- pins = "gpio53", "gpio58", "gpio59";
- function = "qpic";
- bias-pull-up;
- };
-
- pulldowns {
- pins = "gpio54", "gpio55", "gpio56",
- "gpio57", "gpio60", "gpio61",
- "gpio62", "gpio63", "gpio64",
- "gpio65", "gpio66", "gpio67",
- "gpio68", "gpio69";
- function = "qpic";
- bias-pull-down;
- };
- };
-};
-
-&nand {
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- nand@0 {
- /delete-property/ nand-ecc-strength;
- /delete-property/ nand-ecc-step-size;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SBL1";
- reg = <0x000000 0x80000>;
- read-only;
- };
-
- partition@80000 {
- label = "MIBIB";
- reg = <0x080000 0x80000>;
- read-only;
- };
-
- partition@100000 {
- label = "QSEE";
- reg = <0x100000 0x80000>;
- read-only;
- };
-
- partition@180000 {
- label = "CDT";
- reg = <0x180000 0x40000>;
- read-only;
- };
-
- partition@1c0000 {
- label = "QSEE_B";
- reg = <0x1c0000 0x80000>;
- read-only;
- };
-
- partition@240000 {
- label = "urlader0";
- reg = <0x240000 0x40000>;
- read-only;
- };
-
- partition@280000 {
- label = "urlader1";
- reg = <0x280000 0x40000>;
- read-only;
- };
-
- partition@2c0000 {
- label = "nand-tffs";
- reg = <0x2c0000 0x840000>;
- read-only;
- };
-
- partition@b00000 {
- /* 'kernel1' in AVM firmware */
- label = "uboot0";
- reg = <0xb00000 0x400000>;
- };
-
- partition@f00000 {
- /* 'kernel2' in AVM firmware */
- label = "uboot1";
- reg = <0xf00000 0x400000>;
- };
-
- partition@1300000 {
- label = "ubi";
- reg = <0x1300000 0x6d00000>;
- };
- };
- };
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- /* BDFs are identical for the FRITZ!Box 7530 and the FRITZ!Repeater 3000 */
- qcom,ath10k-calibration-variant = "AVM-FRITZRepeater-3000";
-};
-
-&wifi1 {
- status = "okay";
- ieee80211-freq-limit = <5170000 5350000>;
- /* BDFs are identical for the FRITZ!Box 7530 and the FRITZ!Repeater 3000 */
- qcom,ath10k-calibration-variant = "AVM-FRITZRepeater-3000";
-};
-
-&pcie0 {
- status = "okay";
-
- perst-gpio = <&tlmm 35 GPIO_ACTIVE_LOW>;
- wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- /* QCA9984 */
- compatible = "qcom,ath10k";
- status = "okay";
- reg = <0x00010000 0 0 0 0>;
- ieee80211-freq-limit = <5470000 5875000>;
- /* Uses the reference BDF */
- };
- };
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
-
- label = "lan1";
-};
-
-&swport5 {
- status = "okay";
-
- label = "lan2";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "GL.iNet GL-B2200";
- compatible = "glinet,gl-b2200", "qcom,ipq4019";
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x10000000>;
- };
-
- chosen {
- bootargs-append = " root=/dev/mmcblk0p2 rw rootwait clk_ignore_unused";
- };
-
- aliases {
- ethernet1 = &swport4;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- /* select hostmode */
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- wps {
- label = "wps";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- linux,input-type = <1>;
- };
-
- reset {
- label = "reset";
- gpios = <&tlmm 40 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- linux,input-type = <1>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- power_blue {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 57 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- };
- internet_blue {
- label = "blue:internet";
- gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>;
- };
- power_white {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
- };
- internet_white {
- label = "white:internet";
- gpios = <&tlmm 66 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&vqmmc {
- status = "okay";
-};
-
-&sdhci {
- status = "okay";
- pinctrl-0 = <&sd_pins>;
- pinctrl-names = "default";
- cd-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
- vqmmc-supply = <&vqmmc>;
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SBL1";
- reg = <0x0 0x40000>;
- read-only;
- };
-
- partition@40000 {
- label = "MIBIB";
- reg = <0x40000 0x20000>;
- read-only;
- };
-
- partition@60000 {
- label = "QSEE";
- reg = <0x60000 0x60000>;
- read-only;
- };
-
- partition@c0000 {
- label = "CDT";
- reg = <0xc0000 0x10000>;
- read-only;
- };
-
- partition@d0000 {
- label = "DDRPARAMS";
- reg = <0xd0000 0x10000>;
- read-only;
- };
-
- partition@e0000 {
- label = "APPSBLENV";
- reg = <0xe0000 0x10000>;
- read-only;
- };
-
- partition@f0000 {
- label = "APPSBL";
- reg = <0xf0000 0x80000>;
- read-only;
- };
-
- partition@170000 {
- label = "ART";
- reg = <0x170000 0x10000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
-
- precal_art_9000: precal@9000 {
- reg = <0x9000 0x2f20>;
- };
- };
- };
- };
- };
-};
-
-&blsp1_spi2 {
- pinctrl-0 = <&spi_1_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- spidev1: spi@0 {
- compatible = "silabs,si3210";
- reg = <0>;
- spi-max-frequency = <24000000>;
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&blsp1_uart2 {
- pinctrl-0 = <&serial_1_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- serial_1_pins: serial1_pinmux {
- mux {
- pins = "gpio8", "gpio9",
- "gpio10", "gpio11";
- function = "blsp_uart1";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- };
- pinmux_cs {
- function = "gpio";
- pins = "gpio12";
- };
- pinconf {
- pins = "gpio13", "gpio14", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
- pinconf_cs {
- pins = "gpio12";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-
- spi_1_pins: spi_1_pinmux {
- mux {
- pins = "gpio44", "gpio46", "gpio47";
- function = "blsp_spi1";
- bias-disable;
- };
- cs {
- pins = "gpio45";
- function = "gpio";
- bias-pull-up;
- };
- reset {
- pins = "gpio43";
- function = "gpio";
- output-high;
- };
- mux_2 {
- pins = "gpio35";
- function = "gpio";
- output-high;
- };
- host_int {
- pins = "gpio2";
- function = "gpio";
- input;
- };
- wake {
- pins = "gpio48";
- function = "gpio";
- output-high;
- };
- };
-
- sd_pins: sd_pins {
- pinmux {
- function = "sdio";
- pins = "gpio23", "gpio24", "gpio25", "gpio26",
- "gpio29", "gpio30", "gpio31", "gpio32";
- drive-strength = <10>;
- };
-
- pinmux_sd_clk {
- function = "sdio";
- pins = "gpio27";
- drive-strength = <16>;
- };
-
- pinmux_sd7 {
- function = "sdio";
- pins = "gpio28";
- drive-strength = <10>;
- bias-disable;
- };
- };
-
-};
-
-&pcie0 {
- status = "okay";
- perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
- wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi2: wifi@1,0 {
- status = "okay";
- /* Bootlog shows this is a 168c:0056 - QCA 9888v2 */
- compatible = "qcom,ath10k";
- reg = <0x00010000 0 0 0 0>;
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_9000>;
- qcom,ath10k-calibration-variant = "GL-B2200";
- ieee80211-freq-limit = <5450000 5900000>;
- };
- };
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
-
- label = "wan";
-};
-
-&swport5 {
- status = "okay";
-
- label = "lan";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
- qcom,ath10k-calibration-variant = "GL-B2200";
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
- qcom,ath10k-calibration-variant = "GL-B2200";
- ieee80211-freq-limit = <5100000 5400000>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/* Copyright (c) 2019, Robert Marko <robimarko@gmail.com> */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "8devices Habanero DVK";
- compatible = "8dev,habanero-dvk";
-
- aliases {
- led-boot = &led_status;
- led-failsafe = &led_status;
- led-running = &led_status;
- led-upgrade = &led_upgrade;
- ethernet1 = &swport5;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
-
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- };
-
- counter@4a1000 {
- compatible = "qcom,qca-gcnt";
- reg = <0x4a1000 0x4>;
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- status = "okay";
-
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2: usb2@60f8800 {
- status = "okay";
- };
-
- usb3: usb3@8af8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 8 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_status: status {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
- panic-indicator;
- };
-
- led_upgrade: upgrade {
- label = "green:upgrade";
- gpios = <&tlmm 40 GPIO_ACTIVE_HIGH>;
- };
-
- wlan2g {
- label = "green:wlan2g";
- gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy0tpt";
- };
-
- wlan5g {
- label = "green:wlan5g";
- gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy1tpt";
- };
- };
-};
-
-&vqmmc {
- status = "okay";
-};
-
-&sdhci {
- status = "okay";
-
- pinctrl-0 = <&sd_pins>;
- pinctrl-names = "default";
- cd-gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
- vqmmc-supply = <&vqmmc>;
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&tlmm {
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
-
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
-
- pinmux_cs {
- function = "gpio";
- pins = "gpio12";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-
- nand_pins: nand_pins {
- pullups {
- pins = "gpio52", "gpio53", "gpio58", "gpio59";
- function = "qpic";
- bias-pull-up;
- };
-
- pulldowns {
- pins = "gpio54", "gpio55", "gpio56", "gpio57",
- "gpio60", "gpio62", "gpio63", "gpio64",
- "gpio65", "gpio66", "gpio67", "gpio68",
- "gpio69";
- function = "qpic";
- bias-pull-down;
- };
- };
-
- sd_pins: sd_pins {
- pinmux {
- function = "sdio";
- pins = "gpio23", "gpio24", "gpio25", "gpio26",
- "gpio28", "gpio29", "gpio30", "gpio31";
- drive-strength = <10>;
- };
-
- pinmux_sd_clk {
- function = "sdio";
- pins = "gpio27";
- drive-strength = <16>;
- };
-
- pinmux_sd7 {
- function = "sdio";
- pins = "gpio32";
- drive-strength = <10>;
- bias-disable;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- status = "okay";
-
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- spi-max-frequency = <24000000>;
- reg = <0>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SBL1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
- partition@40000 {
- label = "MIBIB";
- reg = <0x00040000 0x00020000>;
- read-only;
- };
- partition@60000 {
- label = "QSEE";
- reg = <0x00060000 0x00060000>;
- read-only;
- };
- partition@c0000 {
- label = "CDT";
- reg = <0x000c0000 0x00010000>;
- read-only;
- };
- partition@d0000 {
- label = "DDRPARAMS";
- reg = <0x000d0000 0x00010000>;
- read-only;
- };
- partition@e0000 {
- label = "APPSBLENV"; /* uboot env */
- reg = <0x000e0000 0x00010000>;
- read-only;
- };
- partition@f0000 {
- label = "APPSBL"; /* uboot */
- reg = <0x000f0000 0x00080000>;
- read-only;
- };
- partition@170000 {
- label = "ART";
- reg = <0x00170000 0x00010000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
- partition@180000 {
- label = "cfg";
- reg = <0x00180000 0x00040000>;
- };
- partition@1c0000 {
- label = "firmware";
- compatible = "denx,fit";
- reg = <0x001c0000 0x01e40000>;
- };
- };
- };
-};
-
-/* Some DVK boards ship without NAND */
-&nand {
- status = "okay";
-
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
-};
-
-&blsp1_uart1 {
- status = "okay";
-
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
-
- perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
- wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
-
- /* Free slot for use */
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
- };
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport1 {
- status = "okay";
-};
-
-&swport2 {
- status = "okay";
-};
-
-&swport3 {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
-};
-
-&swport5 {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
- qcom,ath10k-calibration-variant = "8devices-Habanero";
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
- qcom,ath10k-calibration-variant = "8devices-Habanero";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/* Copyright (c) 2021, Robert Marko <robimarko@gmail.com> */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "MikroTik hAP ac3 LTE6 kit";
- compatible = "mikrotik,hap-ac3-lte6-kit";
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x10000000>;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- aliases {
- led-boot = &led_status_blue;
- led-failsafe = &led_status_red;
- led-running = &led_status_blue;
- led-upgrade = &led_status_red;
- };
-
- soc {
- counter@4a1000 {
- compatible = "qcom,qca-gcnt";
- reg = <0x4a1000 0x4>;
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- /* select hostmode */
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_status_blue: status-blue {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
- };
-
- led_status_red: status-red {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_RED>;
- gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
- panic-indicator;
- };
-
- led_status_green: status-green {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
- };
-
- wlan {
- function = LED_FUNCTION_WLAN;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 23 GPIO_ACTIVE_HIGH>;
- };
-
- ethernet {
- label = "green:ethernet";
- gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
- };
-
- wan {
- function = LED_FUNCTION_WAN;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>;
- };
-
- lan1 {
- label = "green:lan1";
- gpios = <&tlmm 29 GPIO_ACTIVE_HIGH>;
- };
-
- lan2 {
- label = "green:lan2";
- gpios = <&tlmm 30 GPIO_ACTIVE_HIGH>;
- };
-
- lan3 {
- label = "green:lan3";
- gpios = <&tlmm 31 GPIO_ACTIVE_HIGH>;
- };
-
- lan4 {
- label = "green:lan4";
- gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pin {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
-
- pin_cs {
- function = "gpio";
- pins = "gpio12";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-
- enable-usb-power {
- gpio-hog;
- gpios = <44 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "enable USB power";
- };
-
- enable-mpcie-power {
- gpio-hog;
- gpios = <51 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "enable mPCI-E power";
- };
-
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- status = "okay";
-
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- reg = <0>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <10000000>;
- #address-cells = <1>;
- #size-cells = <1>;
-
-
- partitions {
- compatible = "fixed-partitions";
-
- partition@0 {
- label = "Qualcomm";
- reg = <0x0 0x80000>;
- read-only;
- };
-
- partition@80000 {
- compatible = "mikrotik,routerboot-partitions";
- label = "RouterBoot";
- reg = <0x80000 0x80000>;
-
- hard_config {
- size = <0x2000>;
- };
-
- dtb_config {
- read-only;
- };
-
- soft_config {
- };
- };
-
- partition@110000 {
- compatible = "mikrotik,minor";
- label = "firmware";
- reg = <0x110000 0xef0000>;
- };
- };
- };
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&blsp1_uart1 {
- status = "okay";
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb3 {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&usb2 {
- status = "okay";
-};
-
-&mdio {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport1 {
- status = "okay";
- label = "lan4";
-};
-
-&swport2 {
- status = "okay";
- label = "lan3";
-};
-
-&swport3 {
- status = "okay";
- label = "lan2";
-};
-
-&swport4 {
- status = "okay";
- label = "lan1";
-};
-
-&swport5 {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
-};
-
-&wifi1 {
- status = "okay";
-};
-
-&crypto {
- status = "okay";
-};
-
-&watchdog {
- status = "okay";
-};
-
-&prng {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/* Copyright (c) 2021, Robert Marko <robimarko@gmail.com> */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "MikroTik hAP ac3";
- compatible = "mikrotik,hap-ac3";
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x10000000>;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- aliases {
- led-boot = &led_status_blue;
- led-failsafe = &led_status_red;
- led-running = &led_status_blue;
- led-upgrade = &led_status_red;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- counter@4a1000 {
- compatible = "qcom,qca-gcnt";
- reg = <0x4a1000 0x4>;
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- /* select hostmode */
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2: usb2@60f8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
-
- mode {
- label = "mode";
- gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RFKILL>;
- };
-
- led {
- label = "led";
- gpios = <&tlmm 42 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_status_blue: status-blue {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
- };
-
- led_status_red: status-red {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_RED>;
- gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
- panic-indicator;
- };
-
- led_status_green: status-green {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
- };
-
- wlan {
- function = LED_FUNCTION_WLAN;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 23 GPIO_ACTIVE_HIGH>;
- };
-
- ethernet {
- label = "green:ethernet";
- gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
- };
-
- wan {
- function = LED_FUNCTION_WAN;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>;
- };
-
- lan1 {
- label = "green:lan1";
- gpios = <&tlmm 29 GPIO_ACTIVE_HIGH>;
- };
-
- lan2 {
- label = "green:lan2";
- gpios = <&tlmm 30 GPIO_ACTIVE_HIGH>;
- };
-
- lan3 {
- label = "green:lan3";
- gpios = <&tlmm 31 GPIO_ACTIVE_HIGH>;
- };
-
- lan4 {
- label = "green:lan4";
- gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>;
- };
-
- poe {
- label = "red:poe";
- gpios = <&tlmm 36 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pin {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
-
- pin_cs {
- function = "gpio";
- pins = "gpio12";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-
- nand_pins: nand_pins {
- pullups {
- pins = "gpio53", "gpio58", "gpio59";
- function = "qpic";
- bias-pull-up;
- };
-
- pulldowns {
- pins = "gpio55", "gpio56", "gpio57", "gpio60",
- "gpio62", "gpio63", "gpio64", "gpio65",
- "gpio66", "gpio67", "gpio68", "gpio69";
- function = "qpic";
- bias-pull-down;
- };
- };
-
- enable-usb-power {
- gpio-hog;
- gpios = <44 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "enable USB power";
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- status = "okay";
-
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- reg = <0>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <40000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "Qualcomm";
- reg = <0x0 0x80000>;
- read-only;
- };
-
- partition@80000 {
- compatible = "mikrotik,routerboot-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
- label = "RouterBoot";
- reg = <0x80000 0x80000>;
-
- hard_config {
- read-only;
- size = <0x2000>;
- };
-
- dtb_config {
- read-only;
- };
-
- soft_config {
- };
- };
- };
- };
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&nand {
- status = "okay";
-
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
-
- nand@0 {
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "kernel";
- reg = <0x0 0xa00000>;
- };
-
- partition@a00000 {
- label = "ubi";
- reg = <0xa00000 0x7600000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- status = "okay";
-
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&mdio {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport1 {
- status = "okay";
- label = "lan4";
-};
-
-&swport2 {
- status = "okay";
- label = "lan3";
-};
-
-&swport3 {
- status = "okay";
- label = "lan2";
-};
-
-&swport4 {
- status = "okay";
- label = "lan1";
-};
-
-&swport5 {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
-
- qcom,ath10k-calibration-variant = "MikroTik-hAP-ac3";
-};
-
-&wifi1 {
- status = "okay";
-
- qcom,ath10k-calibration-variant = "MikroTik-hAP-ac3";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "Netgear LBR20";
- compatible = "netgear,lbr20";
-
- chosen {
- bootargs-append = "ubi.mtd=ubi root=/dev/ubiblock0_0";
- };
-
- aliases {
- led-boot = &led_backlight_white;
- led-failsafe = &led_status_green;
- led-running = &led_status_green;
- led-upgrade = &led_status_red;
- label-mac-device = &gmac;
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
-
- wps {
- label = "wps";
- gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_status_green: led-status-green {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
- default-state = "keep";
- };
-
- led_status_red: led-status-red {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_RED>;
- gpios = <&tlmm 23 GPIO_ACTIVE_LOW>;
- };
- };
-
- gpio_export {
- compatible = "gpio-export";
- #size-cells = <0>;
-
- lte_rst {
- gpio-export,name = "lte_rst";
- gpio-export,output = <1>;
- gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>;
- };
-
- lte_pwrkey {
- gpio-export,name = "lte_pwrkey";
- gpio-export,output = <1>;
- gpios = <&tlmm 29 GPIO_ACTIVE_HIGH>;
- };
-
- lte_usb_boot {
- gpio-export,name = "lte_usb_boot";
- gpio-export,output = <0>;
- gpios = <&tlmm 30 GPIO_ACTIVE_HIGH>;
- };
-
- lte_pwm {
- gpio-export,name = "lte_pwm";
- gpio-export,output = <1>;
- gpios = <&tlmm 31 GPIO_ACTIVE_HIGH>;
- };
-
- };
-
- soc {
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- status = "okay";
-
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- };
-};
-
-&prng {
- status = "okay";
-};
-
-&mdio {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
-};
-
-&crypto {
- status = "okay";
-};
-
-&watchdog {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&usb2 {
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb3 {
- status = "okay";
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&tlmm {
- mdio_pins: mdio-pinmux {
- mux_mdio {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
-
- mux_mdc {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- serial_pins: serial-pinmux {
- function = "blsp_uart0";
- pins = "gpio16", "gpio17";
- bias-disable;
- };
-
- nand_pins: nand-pins {
- pullups {
- pins = "gpio52", "gpio53", "gpio58", "gpio59";
- function = "qpic";
- bias-pull-up;
- };
-
- pulldowns {
- pins = "gpio54", "gpio55", "gpio56",
- "gpio57", "gpio60", "gpio61",
- "gpio62", "gpio63", "gpio64",
- "gpio65", "gpio66", "gpio67",
- "gpio68", "gpio69";
- function = "qpic";
- bias-pull-down;
- };
- };
-};
-
-&nand {
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- nand@0 {
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x00000000 0x00100000>;
- read-only;
- };
-
- partition@100000 {
- label = "0:MIBIB";
- reg = <0x00100000 0x00100000>;
- read-only;
- };
-
- partition@200000 {
- label = "0:BOOTCONFIG";
- reg = <0x00200000 0x00100000>;
- read-only;
- };
-
- partition@300000 {
- label = "0:QSEE";
- reg = <0x00300000 0x00100000>;
- read-only;
- };
-
- partition@400000 {
- label = "0:QSEE_1";
- reg = <0x00400000 0x00100000>;
- read-only;
- };
-
- partition@500000 {
- label = "0:CDT";
- reg = <0x00500000 0x00080000>;
- read-only;
- };
-
- partition@580000 {
- label = "0:CDT_1";
- reg = <0x00580000 0x00080000>;
- read-only;
- };
-
- partition@600000 {
- label = "0:BOOTCONFIG1";
- reg = <0x00600000 0x00080000>;
- read-only;
- };
-
- partition@680000 {
- label = "0:APPSBLENV";
- reg = <0x00680000 0x00080000>;
- };
-
- partition@700000 {
- label = "0:APPSBL";
- reg = <0x00700000 0x00200000>;
- read-only;
- };
-
- partition@900000 {
- label = "0:APPSBL_1";
- reg = <0x00900000 0x00200000>;
- read-only;
- };
-
- partition@b00000 {
- label = "0:ART";
- reg = <0x00b00000 0x00080000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
-
- precal_art_9000: precal@9000 {
- reg = <0x9000 0x2f20>;
- };
-
- };
- };
-
- partition@b80000 {
- label = "0:ART.bak";
- reg = <0x00b80000 0x00080000>;
- read-only;
- };
-
- partition@c00000 {
- label = "config";
- reg = <0x00c00000 0x00100000>;
- read-only;
- };
-
- partition@d00000 {
- label = "boarddata1";
- reg = <0x00d00000 0x00080000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- mac_address_lan: macaddr@0 {
- compatible = "mac-base";
- reg = <0x0 0x6>;
- #nvmem-cell-cells = <1>;
- };
-
- mac_address_wan: macaddr@6 {
- compatible = "mac-base";
- reg = <0x6 0x6>;
- #nvmem-cell-cells = <1>;
- };
-
- mac_address_wlan_5g: macaddr@c {
- compatible = "mac-base";
- reg = <0xc 0x6>;
- #nvmem-cell-cells = <1>;
- };
-
- mac_address_wlan_2nd5g: macaddr@12 {
- compatible = "mac-base";
- reg = <0x12 0x6>;
- #nvmem-cell-cells = <1>;
- };
-
- };
- };
-
- partition@d80000 {
- label = "boarddata2";
- reg = <0x00d80000 0x00040000>;
- read-only;
- };
-
- partition@dc0000 {
- label = "pot";
- reg = <0x00dc0000 0x00100000>;
- read-only;
- };
-
- partition@ec0000 {
- label = "boarddata1.bak";
- reg = <0x00ec0000 0x00080000>;
- read-only;
- };
-
- partition@f40000 {
- label = "boarddata2.bak";
- reg = <0x00f40000 0x00040000>;
- read-only;
- };
-
- partition@f80000 {
- label = "language";
- reg = <0x00f80000 0x00300000>;
- read-only;
- };
-
- partition@1280000 {
- label = "cert";
- reg = <0x01280000 0x00080000>;
- read-only;
- };
-
- partition@1300000 {
- label = "ntgrdata";
- reg = <0x01300000 0x09300000>;
- };
-
- partition@a600000 {
- label = "kernel";
- reg = <0x0a600000 0x00700000>;
- };
-
- partition@a9c0000 {
- label = "ubi";
- reg = <0x0ad00000 0x05300000>;
- };
-
- };
- };
-};
-
-&blsp1_i2c3 {
- status = "okay";
-
- led-controller {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "ti,tlc59108"; /* really is tlc59208f */
- reg = <0x27>;
-
- led_backlight_green: led-backlight-green {
- function = LED_FUNCTION_BACKLIGHT;
- color = <LED_COLOR_ID_GREEN>;
- reg = <0x0>;
- linux,default-trigger = "default-off";
- };
-
- led_backlight_red: led-backlight-red {
- function = LED_FUNCTION_BACKLIGHT;
- color = <LED_COLOR_ID_RED>;
- reg = <0x1>;
- linux,default-trigger = "default-off";
- };
-
- led_backlight_blue: led-backlight-blue {
- function = LED_FUNCTION_BACKLIGHT;
- color = <LED_COLOR_ID_BLUE>;
- reg = <0x2>;
- linux,default-trigger = "default-off";
- };
-
- led_backlight_white: led-backlight-white {
- function = LED_FUNCTION_BACKLIGHT;
- color = <LED_COLOR_ID_WHITE>;
- reg = <0x3>;
- linux,default-trigger = "default-off";
- };
-
- };
-};
-
-&blsp1_uart1 {
- status = "okay";
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&mac_address_lan 0>;
-};
-
-&switch {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
- label = "lan1";
-};
-
-&swport5 {
- status = "okay";
- label = "lan2";
-};
-
-&pcie0 {
- status = "okay";
- perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- compatible = "qcom,ath10k";
- status = "okay";
- reg = <0x00010000 0 0 0 0>;
- ieee80211-freq-limit = <5170000 5350000>;
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_9000>, <&mac_address_wlan_2nd5g 0>;
- qcom,ath10k-calibration-variant = "Netgear-LBR20";
- };
- };
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_1000>, <&mac_address_lan 0>;
- qcom,ath10k-calibration-variant = "Netgear-LBR20";
-};
-
-&wifi1 {
- status = "okay";
- ieee80211-freq-limit = <5470000 5815000>;
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_5000>, <&mac_address_wlan_5g 0>;
- qcom,ath10k-calibration-variant = "Netgear-LBR20";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "YYeTs LE1";
- compatible = "yyets,le1";
-
- aliases {
- led-boot = &led_usb;
- led-failsafe = &led_usb;
- led-upgrade = &led_usb;
-
- ethernet0 = &swport5;
- ethernet1 = &gmac;
- label-mac-device = &gmac;
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_usb: usb {
- function = LED_FUNCTION_USB;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 36 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "usbport";
- trigger-sources = <&usb3_port1>, <&usb3_port2>, <&usb2_port1>;
- };
-
- wlan2g {
- label = "green:wlan2g";
- gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy0tpt";
- };
-
- wlan5g {
- label = "green:wlan5g";
- gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy1tpt";
- };
- };
-
- soc {
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SBL1";
- reg = <0x0 0x40000>;
- read-only;
- };
-
- partition@40000 {
- label = "MIBIB";
- reg = <0x40000 0x20000>;
- read-only;
- };
-
- partition@60000 {
- label = "QSEE";
- reg = <0x60000 0x60000>;
- read-only;
- };
-
- partition@c0000 {
- label = "CDT";
- reg = <0xc0000 0x10000>;
- read-only;
- };
-
- partition@d0000 {
- label = "DDRPARAMS";
- reg = <0xd0000 0x10000>;
- read-only;
- };
-
- partition@e0000 {
- label = "APPSBLENV";
- reg = <0xe0000 0x10000>;
- read-only;
- };
-
- partition@f0000 {
- label = "APPSBL";
- reg = <0xf0000 0x80000>;
- read-only;
- };
-
- partition@170000 {
- label = "ART";
- reg = <0x170000 0x10000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- partition@180000 {
- compatible = "denx,fit";
- label = "firmware";
- reg = <0x180000 0x1e80000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&crypto {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&mdio {
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&prng {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport1 {
- status = "okay";
-};
-
-&swport2 {
- status = "okay";
-};
-
-&swport3 {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
-};
-
-&swport5 {
- status = "okay";
-};
-
-&tlmm {
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
-
- pinmux_cs {
- function = "gpio";
- pins = "gpio12";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&usb2 {
- status = "okay";
-
- dwc3@6000000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- usb2_port1: port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
- };
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&usb3 {
- status = "okay";
-
- dwc3@8a00000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- usb3_port1: port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
-
- usb3_port2: port@2 {
- reg = <2>;
- #trigger-source-cells = <0>;
- };
- };
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&watchdog {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cells = <&precal_art_1000>;
- nvmem-cell-names = "pre-calibration";
- qcom,ath10k-calibration-variant = "YYeTs-LE1";
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cells = <&precal_art_5000>;
- nvmem-cell-names = "pre-calibration";
- qcom,ath10k-calibration-variant = "YYeTs-LE1";
-};
+++ /dev/null
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
- * Copyright (c) 2019, Robert Marko <robimarko@gmail.com>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "Mikrotik Wireless Wire Dish LHGG-60ad";
- compatible = "mikrotik,lhgg-60ad";
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x10000000>;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- aliases {
- led-boot = &user;
- led-failsafe = &user;
- led-running = &user;
- led-upgrade = &user;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
- counter@4a1000 {
- compatible = "qcom,qca-gcnt";
- reg = <0x4a1000 0x4>;
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII_RGMII5>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- power: power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
- default-state = "keep";
- panic-indicator;
- };
-
- user: user {
- label = "yellow:user";
- gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
- };
-
- wlan {
- function = LED_FUNCTION_WLAN;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;
- };
-
- align-left {
- label = "green:align-left";
- gpios = <&tlmm 1 GPIO_ACTIVE_HIGH>;
- };
-
- align-right {
- label = "green:align-right";
- gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
- };
-
- wlan-rx {
- label = "green:align-down";
- gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
- };
-
- wlan-tx {
- label = "green:align-up";
- gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi-0-pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- bias-disable;
- };
-
- pinmux_cs {
- function = "gpio";
- pins = "gpio12";
- bias-disable;
- output-high;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
- status = "okay";
-
- m25p80@0 {
- reg = <0>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "Qualcomm";
- reg = <0x0 0x80000>;
- read-only;
- };
-
- partition@80000 {
- compatible = "mikrotik,routerboot-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
- label = "RouterBoot";
- reg = <0x80000 0x80000>;
-
- hard_config {
- read-only;
- size = <0x2000>;
- };
-
- dtb_config {
- read-only;
- };
-
- soft_config {
- };
- };
-
- partition@100000 {
- compatible = "mikrotik,minor";
- label = "firmware";
- reg = <0x100000 0xf00000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
- perst-gpio = <&tlmm 42 GPIO_ACTIVE_HIGH>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- /* wil6210 802.11ad card */
- wifi: wifi@1,0 {
- status = "okay";
- /* wil6210 driver has no compatible */
- reg = <0x00010000 0 0 0 0>;
- };
- };
-};
-
-ðphy1 {
- status = "disabled";
-};
-
-ðphy2 {
- status = "disabled";
-};
-
-ðphy3 {
- status = "disabled";
-};
-
-ðphy4 {
- status = "disabled";
-};
-
-&psgmiiphy {
- status = "disabled";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-
- /delete-property/ psgmii-ethphy;
-};
-
-&swport5 {
- status = "okay";
-
- label = "lan";
- phy-handle = <ðphy0>;
- phy-mode = "rgmii-id";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "ASUS Lyra MAP-AC2200";
- compatible = "asus,map-ac2200";
-
- aliases {
- led-boot = &led_blue0;
- led-failsafe = &led_red0;
- led-running = &led_blue0;
- led-upgrade = &led_red0;
- ethernet1 = &swport4;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2@60f8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 34 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
-
- wps {
- label = "wps";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- };
- };
-};
-
-&nand {
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- nand@0 {
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SBL1";
- reg = <0x0 0x80000>;
- read-only;
- };
-
- partition@80000 {
- label = "MIBIB";
- reg = <0x80000 0x80000>;
- read-only;
- };
-
- partition@100000 {
- label = "QSEE";
- reg = <0x100000 0x100000>;
- read-only;
- };
-
- partition@200000 {
- label = "CDT";
- reg = <0x200000 0x80000>;
- read-only;
- };
-
- partition@280000 {
- label = "APPSBL";
- reg = <0x280000 0x140000>;
- read-only;
- };
-
- partition@3c0000 {
- label = "APPSBLENV";
- reg = <0x3c0000 0x40000>;
- read-only;
- };
-
- partition@400000 {
- label = "ubi";
- reg = <0x400000 0x7c00000>;
- };
- };
- };
-};
-
-&tlmm {
- i2c_0_pins: i2c_0_pinmux {
- pinmux {
- function = "blsp_i2c0";
- pins = "gpio20", "gpio21";
- drive-strength = <16>;
- bias-disable;
- };
- };
-
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- nand_pins: nand_pins {
- pullups {
- pins = "gpio52", "gpio53", "gpio58",
- "gpio59";
- function = "qpic";
- bias-pull-up;
- };
-
- pulldowns {
- pins = "gpio54", "gpio55", "gpio56",
- "gpio57", "gpio60", "gpio61",
- "gpio62", "gpio63", "gpio64",
- "gpio65", "gpio66", "gpio67",
- "gpio68", "gpio69";
- function = "qpic";
- bias-pull-down;
- };
- };
- enable_ext_pa_high {
- gpio-hog;
- gpios = <44 GPIO_ACTIVE_HIGH>,
- <46 GPIO_ACTIVE_HIGH>;
- output-high;
- bias-pull-down;
- line-name = "enable external PA output-high";
- };
- enable_ext_pa_low {
- gpio-hog;
- gpios = <45 GPIO_ACTIVE_HIGH>,
- <47 GPIO_ACTIVE_HIGH>;
- output-low;
- bias-pull-down;
- line-name = "enable external PA output-low";
- };
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "ASUS-MAP-AC2200";
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "ASUS-MAP-AC2200";
- ieee80211-freq-limit = <5470000 5875000>;
-};
-
-&pcie0 {
- status = "okay";
- perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
- wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi2: wifi@1,0 {
- compatible = "qcom,ath10k";
- status = "okay";
- reg = <0x00010000 0 0 0 0>;
- qcom,ath10k-calibration-variant = "ASUS-MAP-AC2200";
- ieee80211-freq-limit = <5170000 5350000>;
- };
- };
-};
-
-&usb2_hs_phy {
- /* Bluetooth module attached via USB */
- status = "okay";
-};
-
-&blsp1_i2c3 {
- pinctrl-0 = <&i2c_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- led-controller@32 {
- /* 9-channel RGB LED controller */
- compatible = "national,lp5523";
- reg = <0x32>;
- clock-mode = /bits/ 8 <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- /*
- * There is only one single extremely bright RGB-LED.
- * The RGB-color channels are running in parallel to
- * increase the current delivery capabilities beyond
- * what a single PWM-output of the controller can do.
- */
-
- led_blue0: led@0 {
- chan-name = "blue-0";
- led-cur = /bits/ 8 <0xfa>;
- max-cur = /bits/ 8 <0xff>;
- reg = <0>;
- color = <LED_COLOR_ID_BLUE>;
- function-enumerator = <0>;
- };
-
- led@1 {
- chan-name = "blue-1";
- led-cur = /bits/ 8 <0xfa>;
- max-cur = /bits/ 8 <0xff>;
- reg = <1>;
- color = <LED_COLOR_ID_BLUE>;
- function-enumerator = <1>;
- };
-
- led@2 {
- chan-name = "blue-2";
- led-cur = /bits/ 8 <0xfa>;
- max-cur = /bits/ 8 <0xff>;
- reg = <2>;
- color = <LED_COLOR_ID_BLUE>;
- function-enumerator = <2>;
- };
-
- led_green0: led@3 {
- chan-name = "green-0";
- led-cur = /bits/ 8 <0xfa>;
- max-cur = /bits/ 8 <0xff>;
- reg = <3>;
- color = <LED_COLOR_ID_GREEN>;
- function-enumerator = <0>;
- };
-
- led@4 {
- chan-name = "green-1";
- led-cur = /bits/ 8 <0xfa>;
- max-cur = /bits/ 8 <0xff>;
- reg = <4>;
- color = <LED_COLOR_ID_GREEN>;
- function-enumerator = <1>;
- };
-
- led@5 {
- chan-name = "green-2";
- led-cur = /bits/ 8 <0xfa>;
- max-cur = /bits/ 8 <0xff>;
- reg = <5>;
- color = <LED_COLOR_ID_GREEN>;
- function-enumerator = <2>;
- };
-
- led_red0: led@6 {
- chan-name = "red-0";
- led-cur = /bits/ 8 <0xfa>;
- max-cur = /bits/ 8 <0xff>;
- reg = <6>;
- color = <LED_COLOR_ID_RED>;
- function-enumerator = <0>;
- };
-
- led@7 {
- chan-name = "red-1";
- led-cur = /bits/ 8 <0xfa>;
- max-cur = /bits/ 8 <0xff>;
- reg = <7>;
- color = <LED_COLOR_ID_RED>;
- function-enumerator = <1>;
- };
-
- led@8 {
- chan-name = "red-2";
- led-cur = /bits/ 8 <0xfa>;
- max-cur = /bits/ 8 <0xff>;
- reg = <8>;
- color = <LED_COLOR_ID_RED>;
- function-enumerator = <2>;
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
-
- label = "wan";
-};
-
-&swport5 {
- status = "okay";
-
- label = "lan";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-// Copyright (c) 2022, Pawel Dembicki <paweldembicki@gmail.com>.
-// Copyright (c) 2022, Marcin Gajda <mgajda@o2.pl>.
-
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/soc/qcom,tcsr.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "ZTE MF18A";
- compatible = "zte,mf18a";
-
- aliases {
- led-boot = &led_power;
- led-failsafe = &led_power;
- led-running = &led_power;
- led-upgrade = &led_power;
- };
-
- chosen {
- /*
- * bootargs forced by u-boot bootipq command:
- * 'ubi.mtd=rootfs root=mtd:ubi_rootfs rootfstype=squashfs rootwait'
- */
- bootargs-append = " root=/dev/ubiblock0_1";
- };
-
- gpio-restart {
- compatible = "gpio-restart";
- gpios = <&tlmm 8 GPIO_ACTIVE_HIGH>;
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_internal: led-0 {
- label = "blue:internal";
- gpios = <&tlmm 10 GPIO_ACTIVE_LOW>;
- default-state = "keep";
- };
-
- led_power: led-1 {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 48 GPIO_ACTIVE_HIGH>;
- default-state = "keep";
- };
-
- led-2 {
- function = LED_FUNCTION_WLAN;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 23 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy0tpt";
- };
-
- led-3 {
- function = LED_FUNCTION_WLAN;
- color = <LED_COLOR_ID_RED>;
- gpios = <&tlmm 26 GPIO_ACTIVE_HIGH>;
- };
-
- led-4 {
- function = LED_FUNCTION_WLAN;
- label = "blue:smart";
- gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy1tpt";
- };
-
- led-5 {
- label = "red:smart";
- gpios = <&tlmm 25 GPIO_ACTIVE_HIGH>;
- };
-
- resetzwave {
- label = "resetzwave";
- gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- linux,code = <KEY_RESTART>;
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- };
-
- wps {
- label = "wps";
- linux,code = <KEY_WPS_BUTTON>;
- gpios = <&tlmm 68 GPIO_ACTIVE_LOW>;
- };
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
- reset-delay-us = <2000>;
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- /* select hostmode */
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2@60f8800 {
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- /* u-boot is looking for "n25q128a11" property */
- compatible = "jedec,spi-nor", "n25q128a11";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x0 0x40000>;
- read-only;
- };
-
- partition@40000 {
- label = "0:MIBIB";
- reg = <0x40000 0x20000>;
- read-only;
- };
-
- partition@60000 {
- label = "0:QSEE";
- reg = <0x60000 0x60000>;
- read-only;
- };
-
- partition@c0000 {
- label = "0:CDT";
- reg = <0xc0000 0x10000>;
- read-only;
- };
-
- partition@d0000 {
- label = "0:DDRPARAMS";
- reg = <0xd0000 0x10000>;
- read-only;
- };
-
- partition@e0000 {
- label = "0:APPSBLENV";
- reg = <0xe0000 0x10000>;
- read-only;
- };
-
- partition@f0000 {
- label = "0:APPSBL";
- reg = <0xf0000 0xc0000>;
- read-only;
- };
-
- partition@1b0000 {
- label = "0:reserved1";
- reg = <0x1b0000 0x50000>;
- read-only;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_config_0 0>;
-};
-
-&switch {
- status = "okay";
-};
-
-&swport2 {
- status = "okay";
-
- label = "wan";
-
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_config_0 1>;
-};
-
-&swport3 {
- status = "okay";
-
- label = "lan";
-};
-
-&nand {
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- nand@0 {
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "fota-flag";
- reg = <0x0 0xa0000>;
- read-only;
- };
-
- partition@a0000 {
- label = "ART";
- reg = <0xa0000 0x80000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_9000: precal@9000 {
- reg = <0x9000 0x2f20>;
- };
- };
- };
-
- partition@120000 {
- label = "mac";
- reg = <0x120000 0x80000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_config_0: macaddr@0 {
- compatible = "mac-base";
- reg = <0x0 0x6>;
- #nvmem-cell-cells = <1>;
- };
- };
- };
-
- partition@1a0000 {
- label = "reserved2";
- reg = <0x1a0000 0xc0000>;
- read-only;
- };
-
- partition@260000 {
- label = "cfg-param";
- reg = <0x260000 0x400000>;
- read-only;
- };
-
- partition@660000 {
- label = "log";
- reg = <0x660000 0x400000>;
- };
-
- partition@a60000 {
- label = "oops";
- reg = <0xa60000 0xa0000>;
- };
-
- partition@b00000 {
- label = "reserved3";
- reg = <0xb00000 0x500000>;
- read-only;
- };
-
- partition@1000000 {
- label = "web";
- reg = <0x1000000 0x800000>;
- };
-
- partition@1800000 {
- label = "rootfs";
- reg = <0x1800000 0x1d00000>;
- };
-
- partition@3500000 {
- label = "data";
- reg = <0x3500000 0x1900000>;
- };
-
- partition@4e00000 {
- label = "fota";
- reg = <0x4e00000 0x2800000>;
-
- };
- partition@7600000 {
- label = "iot-db";
- reg = <0x7600000 0xa00000>;
- };
- };
- };
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&tlmm {
- i2c_0_pins: i2c_0_pinmux {
- mux {
- pins = "gpio20", "gpio21";
- function = "blsp_i2c0";
- bias-disable;
- };
- };
-
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
-
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- nand_pins: nand_pins {
- pullups {
- pins = "gpio52", "gpio53", "gpio58",
- "gpio59";
- function = "qpic";
- bias-pull-up;
- };
-
- pulldowns {
- pins = "gpio54", "gpio55", "gpio56",
- "gpio57", "gpio60",
- "gpio62", "gpio63", "gpio64",
- "gpio65", "gpio66", "gpio67",
- "gpio69";
- function = "qpic";
- bias-pull-down;
- };
- };
-
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
-
- pinmux_cs {
- function = "gpio";
- pins = "gpio12";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_1000>, <&macaddr_config_0 2>;
- qcom,ath10k-calibration-variant = "ZTE-MF18A";
-};
-
-//* This node is used for 5Ghz on QCA9982 */
-&pcie0 {
- status = "okay";
- perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
- wake-gpio = <&tlmm 40 GPIO_ACTIVE_LOW>;
- clkreq-gpio = <&tlmm 39 GPIO_ACTIVE_LOW>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi2: wifi@1,0 {
- compatible = "pci168c,0040";
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_9000>, <&macaddr_config_0 3>;
- qcom,ath10k-calibration-variant = "ZTE-MF18A";
- reg = <0x00010000 0 0 0 0>;
- };
- };
-};
-
-
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-// Copyright (c) 2022, Pawel Dembicki <paweldembicki@gmail.com>.
-// Copyright (c) 2023, Andreas Böhler <dev@aboehler.at>
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/soc/qcom,tcsr.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "ZTE MF282Plus";
- compatible = "zte,mf282plus";
-
- aliases {
- led-boot = &led_internal;
- led-failsafe = &led_internal;
- led-running = &led_internal;
- led-upgrade = &led_internal;
- };
-
- chosen {
- /*
- * bootargs forced by u-boot bootipq command:
- * 'ubi.mtd=rootfs root=mtd:ubi_rootfs rootfstype=squashfs rootwait'
- */
- bootargs-append = " root=/dev/ubiblock0_1";
- };
-
- gpio_export {
- compatible = "gpio-export";
- #size-cells = <0>;
-
- modem {
- gpio-export,name = "modem-reset";
- gpio-export,output = <0>;
- gpios = <&tlmm 8 GPIO_ACTIVE_HIGH>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_internal: led-0 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 10 GPIO_ACTIVE_LOW>;
- label = "blue:internal_led";
- default-state = "keep";
- };
-
- led-1 {
- function = LED_FUNCTION_WLAN;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy0tpt";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- wifi {
- label = "wifi";
- linux,code = <KEY_RFKILL>;
- gpios = <&tlmm 11 GPIO_ACTIVE_LOW>;
- };
-
- reset {
- label = "reset";
- linux,code = <KEY_RESTART>;
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- };
-
- wps {
- label = "wps";
- linux,code = <KEY_WPS_BUTTON>;
- gpios = <&tlmm 68 GPIO_ACTIVE_LOW>;
- };
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
- reset-delay-us = <2000>;
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- /* select hostmode */
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2@60f8800 {
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- /* u-boot is looking for "n25q128a11" property */
- compatible = "jedec,spi-nor", "n25q128a11";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x0 0x40000>;
- read-only;
- };
-
- partition@40000 {
- label = "0:MIBIB";
- reg = <0x40000 0x20000>;
- read-only;
- };
-
- partition@60000 {
- label = "0:QSEE";
- reg = <0x60000 0x60000>;
- read-only;
- };
-
- partition@c0000 {
- label = "0:CDT";
- reg = <0xc0000 0x10000>;
- read-only;
- };
-
- partition@d0000 {
- label = "0:DDRPARAMS";
- reg = <0xd0000 0x10000>;
- read-only;
- };
-
- partition@e0000 {
- label = "0:APPSBLENV";
- reg = <0xe0000 0x10000>;
- read-only;
- };
-
- partition@f0000 {
- label = "0:APPSBL";
- reg = <0xf0000 0xc0000>;
- read-only;
- };
-
- partition@1b0000 {
- label = "0:reserved1";
- reg = <0x1b0000 0x50000>;
- read-only;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_config_0 0>;
-};
-
-&nand {
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- nand@0 {
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "fota-flag";
- reg = <0x0 0xa0000>;
- read-only;
- };
-
- partition@a0000 {
- label = "ART";
- reg = <0xa0000 0x80000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- partition@120000 {
- label = "mac";
- reg = <0x120000 0x80000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_config_0: macaddr@0 {
- compatible = "mac-base";
- reg = <0x0 0x6>;
- #nvmem-cell-cells = <1>;
- };
- };
- };
-
- partition@1a0000 {
- label = "reserved2";
- reg = <0x1a0000 0xc0000>;
- read-only;
- };
-
- partition@260000 {
- label = "cfg-param";
- reg = <0x260000 0x400000>;
- read-only;
- };
-
- partition@660000 {
- label = "log";
- reg = <0x660000 0x400000>;
- };
-
- partition@a60000 {
- label = "oops";
- reg = <0xa60000 0xa0000>;
- };
-
- partition@b00000 {
- label = "reserved3";
- reg = <0xb00000 0x500000>;
- read-only;
- };
-
- partition@1000000 {
- label = "web";
- reg = <0x1000000 0x800000>;
- };
-
- partition@1800000 {
- label = "rootfs";
- reg = <0x1800000 0x1d00000>;
- };
-
- partition@3500000 {
- label = "data";
- reg = <0x3500000 0x1900000>;
- };
-
- partition@4e00000 {
- label = "fota";
- reg = <0x4e00000 0x2800000>;
- };
-
- partition@7600000 {
- label = "extra-cfg";
- reg = <0x7600000 0xa00000>;
- };
- };
- };
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
-
- label = "lan";
-};
-
-&tlmm {
- i2c_0_pins: i2c_0_pinmux {
- mux {
- pins = "gpio20", "gpio21";
- function = "blsp_i2c0";
- bias-disable;
- };
- };
-
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
-
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- nand_pins: nand_pins {
- pullups {
- pins = "gpio52", "gpio53", "gpio58",
- "gpio59";
- function = "qpic";
- bias-pull-up;
- };
-
- pulldowns {
- pins = "gpio54", "gpio55", "gpio56",
- "gpio57", "gpio60",
- "gpio62", "gpio63", "gpio64",
- "gpio65", "gpio66", "gpio67",
- "gpio69";
- function = "qpic";
- bias-pull-down;
- };
- };
-
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
-
- pinmux_cs {
- function = "gpio";
- pins = "gpio12";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-/*
- * The MD5 sum of the board file of the MF286D is identical to the board
- * file in the OEM firmware
- */
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_1000>, <&macaddr_config_0 1>;
- qcom,ath10k-calibration-variant = "zte,mf286d";
-};
-
-/*
- * The MD5 sum of the board file of the MF286D is identical to the board
- * file in the OEM firmware
- */
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_5000>, <&macaddr_config_0 1>;
- qcom,ath10k-calibration-variant = "zte,mf286d";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-// Copyright (c) 2022, Pawel Dembicki <paweldembicki@gmail.com>.
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/soc/qcom,tcsr.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "ZTE MF286D";
- compatible = "zte,mf286d";
-
- aliases {
- led-boot = &led_internal;
- led-failsafe = &led_internal;
- led-running = &led_internal;
- led-upgrade = &led_internal;
- };
-
- chosen {
- /*
- * bootargs forced by u-boot bootipq command:
- * 'ubi.mtd=rootfs root=mtd:ubi_rootfs rootfstype=squashfs rootwait'
- */
- bootargs-append = " root=/dev/ubiblock0_1";
- };
-
- gpio-restart {
- compatible = "gpio-restart";
- gpios = <&tlmm 8 GPIO_ACTIVE_HIGH>;
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_internal: led-0 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 10 GPIO_ACTIVE_LOW>;
- label = "blue:internal_led";
- default-state = "keep";
- };
-
- led-1 {
- function = LED_FUNCTION_WLAN;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy0tpt";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- wifi {
- label = "wifi";
- linux,code = <KEY_RFKILL>;
- gpios = <&tlmm 11 GPIO_ACTIVE_LOW>;
- };
-
- reset {
- label = "reset";
- linux,code = <KEY_RESTART>;
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- };
-
- wps {
- label = "wps";
- linux,code = <KEY_WPS_BUTTON>;
- gpios = <&tlmm 68 GPIO_ACTIVE_LOW>;
- };
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
- reset-delay-us = <2000>;
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- /* select hostmode */
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2@60f8800 {
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- /* u-boot is looking for "n25q128a11" property */
- compatible = "jedec,spi-nor", "n25q128a11";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x0 0x40000>;
- read-only;
- };
-
- partition@40000 {
- label = "0:MIBIB";
- reg = <0x40000 0x20000>;
- read-only;
- };
-
- partition@60000 {
- label = "0:QSEE";
- reg = <0x60000 0x60000>;
- read-only;
- };
-
- partition@c0000 {
- label = "0:CDT";
- reg = <0xc0000 0x10000>;
- read-only;
- };
-
- partition@d0000 {
- label = "0:DDRPARAMS";
- reg = <0xd0000 0x10000>;
- read-only;
- };
-
- partition@e0000 {
- label = "0:APPSBLENV";
- reg = <0xe0000 0x10000>;
- read-only;
- };
-
- partition@f0000 {
- label = "0:APPSBL";
- reg = <0xf0000 0xc0000>;
- read-only;
- };
-
- partition@1b0000 {
- label = "0:reserved1";
- reg = <0x1b0000 0x50000>;
- read-only;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_config_0 0>;
-};
-
-&nand {
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- nand@0 {
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "fota-flag";
- reg = <0x0 0xa0000>;
- read-only;
- };
-
- partition@a0000 {
- label = "ART";
- reg = <0xa0000 0x80000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- partition@120000 {
- label = "mac";
- reg = <0x120000 0x80000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_config_0: macaddr@0 {
- compatible = "mac-base";
- reg = <0x0 0x6>;
- #nvmem-cell-cells = <1>;
- };
- };
- };
-
- partition@1a0000 {
- label = "reserved2";
- reg = <0x1a0000 0xc0000>;
- read-only;
- };
-
- partition@260000 {
- label = "cfg-param";
- reg = <0x260000 0x400000>;
- read-only;
- };
-
- partition@660000 {
- label = "log";
- reg = <0x660000 0x400000>;
- };
-
- partition@a60000 {
- label = "oops";
- reg = <0xa60000 0xa0000>;
- };
-
- partition@b00000 {
- label = "reserved3";
- reg = <0xb00000 0x500000>;
- read-only;
- };
-
- partition@1000000 {
- label = "web";
- reg = <0x1000000 0x800000>;
- };
-
- partition@1800000 {
- label = "rootfs";
- reg = <0x1800000 0x1d00000>;
- };
-
- partition@3500000 {
- label = "data";
- reg = <0x3500000 0x1900000>;
- };
-
- partition@4e00000 {
- label = "fota";
- reg = <0x4e00000 0x3200000>;
- };
- };
- };
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport2 {
- status = "okay";
-
- label = "lan4";
-};
-
-&swport3 {
- status = "okay";
-
- label = "lan3";
-};
-
-&swport4 {
- status = "okay";
-
- label = "lan2";
-};
-
-&swport5 {
- status = "okay";
-
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_config_0 1>;
-};
-
-&tlmm {
- i2c_0_pins: i2c_0_pinmux {
- mux {
- pins = "gpio20", "gpio21";
- function = "blsp_i2c0";
- bias-disable;
- };
- };
-
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
-
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- nand_pins: nand_pins {
- pullups {
- pins = "gpio52", "gpio53", "gpio58",
- "gpio59";
- function = "qpic";
- bias-pull-up;
- };
-
- pulldowns {
- pins = "gpio54", "gpio55", "gpio56",
- "gpio57", "gpio60",
- "gpio62", "gpio63", "gpio64",
- "gpio65", "gpio66", "gpio67",
- "gpio69";
- function = "qpic";
- bias-pull-down;
- };
- };
-
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
-
- pinmux_cs {
- function = "gpio";
- pins = "gpio12";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_1000>, <&macaddr_config_0 2>;
- qcom,ath10k-calibration-variant = "zte,mf286d";
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_5000>, <&macaddr_config_0 3>;
- qcom,ath10k-calibration-variant = "zte,mf286d";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-// Copyright (c) 2022, Pawel Dembicki <paweldembicki@gmail.com>.
-// Copyright (c) 2022, Giammarco Marzano <stich86@gmail.com>.
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/soc/qcom,tcsr.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "ZTE MF289F";
- compatible = "zte,mf289f";
-
- aliases {
- led-boot = &led_status;
- led-failsafe = &led_status;
- led-running = &led_status;
- led-upgrade = &led_status;
- };
-
- chosen {
- /*
- * bootargs forced by u-boot bootipq command:
- * 'ubi.mtd=rootfs root=mtd:ubi_rootfs rootfstype=squashfs rootwait'
- */
- bootargs-append = " root=/dev/ubiblock0_1";
- };
-
- /*
- * This node is used to restart modem module to avoid anomalous
- * behaviours on initial communication.
- */
- gpio-restart {
- compatible = "gpio-restart";
- gpios = <&tlmm 8 GPIO_ACTIVE_HIGH>;
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_status: led-0 {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
- };
-
- led-1 {
- function = LED_FUNCTION_WLAN;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy0tpt";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- key-reset {
- label = "reset";
- linux,code = <KEY_RESTART>;
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- };
-
- key-wps {
- label = "wps";
- linux,code = <KEY_WPS_BUTTON>;
- gpios = <&tlmm 68 GPIO_ACTIVE_LOW>;
- };
- };
-
- soc {
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- /* select hostmode */
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
- };
-};
-
-&prng {
- status = "okay";
-};
-
-&mdio {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
- reset-delay-us = <2000>;
-};
-
-&watchdog {
- status = "okay";
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&usb2 {
- status = "okay";
-};
-
-&usb3 {
- status = "okay";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>,
- <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x0 0x40000>;
- read-only;
- };
-
- partition@40000 {
- label = "0:MIBIB";
- reg = <0x40000 0x20000>;
- read-only;
- };
-
- partition@60000 {
- label = "0:QSEE";
- reg = <0x60000 0x60000>;
- read-only;
- };
-
- partition@c0000 {
- label = "0:CDT";
- reg = <0xc0000 0x10000>;
- read-only;
- };
-
- partition@d0000 {
- label = "0:DDRPARAMS";
- reg = <0xd0000 0x10000>;
- read-only;
- };
-
- partition@e0000 {
- label = "0:APPSBLENV";
- reg = <0xe0000 0x10000>;
- read-only;
- };
-
- partition@f0000 {
- label = "0:APPSBL";
- reg = <0xf0000 0xc0000>;
- read-only;
- };
-
- partition@1b0000 {
- label = "0:reserved1";
- reg = <0x1b0000 0x50000>;
- read-only;
- };
- };
- };
-
- spi-nand@1 { /* flash@1 ? */
- compatible = "spi-nand";
- reg = <1>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "fota-flag";
- reg = <0x0 0xa0000>;
- read-only;
- };
-
- partition@a0000 {
- label = "ART";
- reg = <0xa0000 0x80000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- partition@120000 {
- label = "mac";
- reg = <0x120000 0x80000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_mac_0: macaddr@0 {
- compatible = "mac-base";
- reg = <0x0 0x6>;
- #nvmem-cell-cells = <1>;
- };
- };
- };
-
- partition@1a0000 {
- label = "reserved2";
- reg = <0x1a0000 0xc0000>;
- read-only;
- };
-
- partition@260000 {
- label = "cfg-param";
- reg = <0x260000 0x400000>;
- read-only;
- };
-
- partition@660000 {
- label = "log";
- reg = <0x660000 0x400000>;
- };
-
- partition@a60000 {
- label = "oops";
- reg = <0xa60000 0xa0000>;
- };
-
- partition@b00000 {
- label = "reserved3";
- reg = <0xb00000 0x500000>;
- read-only;
- };
-
- partition@1000000 {
- label = "web";
- reg = <0x1000000 0x800000>;
- };
-
- partition@1800000 {
- label = "rootfs";
- reg = <0x1800000 0x1d00000>;
- };
-
- partition@3500000 {
- label = "data";
- reg = <0x3500000 0x1900000>;
- };
-
- partition@4e00000 {
- label = "fota";
- reg = <0x4e00000 0x3200000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&crypto {
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_mac_0 0>;
-};
-
-&switch {
- status = "okay";
-};
-
-&swport2 {
- status = "okay";
-
- label = "wan";
-
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_mac_0 1>;
-};
-
-&swport5 {
- status = "okay";
-
- label = "lan";
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&tlmm {
- i2c_0_pins: i2c_0_pinmux {
- mux {
- pins = "gpio20", "gpio21";
- function = "blsp_i2c0";
- bias-disable;
- };
- };
-
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
-
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
-
- pinmux_cs {
- function = "gpio";
- pins = "gpio12", "gpio54";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_1000>, <&macaddr_mac_0 2>;
- qcom,ath10k-calibration-variant = "zte,mf289f";
-};
-
-/* This node is used only on AT2 version for 5Ghz on IPQ4019 with board-id=21 */
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_5000>, <&macaddr_mac_0 3>;
- qcom,ath10k-calibration-variant = "zte,mf289f";
-};
-
-/* This node is used only on AT1 version for 5Ghz on QCA9984 */
-&pcie0 {
- status = "okay";
- perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
- wake-gpio = <&tlmm 40 GPIO_ACTIVE_LOW>;
- clkreq-gpio = <&tlmm 39 GPIO_ACTIVE_LOW>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi2: wifi@1,0 {
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_mac_0 4>;
- compatible = "qcom,ath10k";
- reg = <0x00010000 0 0 0 0>;
- qcom,ath10k-calibration-variant = "zte,mf289f";
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include <dt-bindings/leds/common.h>
-
-#include "qcom-ipq4019-xx8300.dtsi"
-
-/ {
- model = "Linksys MR8300 (Dallas)";
- compatible = "linksys,mr8300", "qcom,ipq4019";
-
- aliases {
- led-boot = &led_blue;
- led-failsafe = &led_red;
- led-running = &led_blue;
- led-upgrade = &led_amber;
- serial0 = &blsp1_uart1;
- };
-
- // Top panel LEDs, above Linksys logo
- leds {
- compatible = "gpio-leds";
-
- led_red: red {
- function = LED_FUNCTION_ALARM;
- color = <LED_COLOR_ID_RED>;
- gpios = <&tlmm 47 GPIO_ACTIVE_HIGH>;
- };
-
- led_amber: amber {
- function = LED_FUNCTION_PROGRAMMING;
- color = <LED_COLOR_ID_AMBER>;
- gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
- panic-indicator;
- };
-
- led_blue: blue {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
- };
-
- // On back panel, above USB socket
-
- led_usb: usb {
- function = LED_FUNCTION_USB;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
- trigger-sources = <&usb3_port1>, <&usb3_port2>,
- <&usb2_port1>;
- linux,default-trigger = "usbport";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- linux,code = <KEY_RESTART>;
- gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
- };
-
- wps {
- label = "wps";
- linux,code = <KEY_WPS_BUTTON>;
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "linksys-mr8300-v0-fcc";
-};
-
-&wifi1 {
- status = "okay";
- ieee80211-freq-limit = <5170000 5330000>;
- qcom,ath10k-calibration-variant = "linksys-mr8300-v0-fcc";
-};
-
-&wifi2 {
- status = "okay";
- ieee80211-freq-limit = <5490000 5835000>;
- qcom,ath10k-calibration-variant = "linksys-mr8300-v0-fcc";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-
-#include "qcom-ipq4019.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "Sony NCP-HG100/Cellular";
- compatible = "sony,ncp-hg100-cellular";
-
- aliases {
- led-boot = &led_cloud_green;
- led-failsafe = &led_cloud_red;
- led-running = &led_cloud_green;
- led-upgrade = &led_cloud_green;
- label-mac-device = &gmac;
- };
-
- chosen {
- bootargs = "console=ttyMSM0,115200n8 root=/dev/mmcblk0p15 rootfstype=squashfs,ext4";
- };
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x20000000>;
- };
-
- soc {
- tcsr@1949000 {
- status = "okay";
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- status = "okay";
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- ess_tcsr@1953000 {
- status = "okay";
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- status = "okay";
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- dma@7984000 {
- status = "okay";
- };
- };
-
- keys-repeat {
- compatible = "gpio-keys";
- pinctrl-0 = <&keys_pins>;
- pinctrl-names = "default";
- autorepeat;
-
- key-volup {
- label = "volume up";
- linux,code = <KEY_VOLUMEUP>;
- gpios = <&tlmm 39 GPIO_ACTIVE_HIGH>;
- linux,input-type = <EV_KEY>;
- };
-
- key-voldown {
- label = "volume down";
- linux,code = <KEY_VOLUMEDOWN>;
- gpios = <&tlmm 40 GPIO_ACTIVE_HIGH>;
- linux,input-type = <EV_KEY>;
- };
-
- key-alexatrigger {
- label = "alexa trigger";
- linux,code = <BTN_0>;
- gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
- linux,input-type = <EV_KEY>;
- };
-
- key-mute {
- label = "mic mute";
- linux,code = <BTN_1>;
- gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
- linux,input-type = <EV_SW>;
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- key-reset {
- label = "reset";
- gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
-
- key-wps {
- label = "setup";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- };
- };
-};
-
-&tlmm {
- pinctrl-0 = <&bt_pins>, <&aud_pins>, <&mcu_pins>;
- pinctrl-names = "default";
-
- /*
- * uart0 is shared for debug console and Z-Wave,
- * use only for debug console in OpenWrt.
- *
- * 1: debug console
- * 0: Z-Wave
- */
- uart0_ctrl_pins: uart0_ctrl_pinmux {
- mux {
- pins = "gpio15";
- function = "gpio";
- output-high;
- };
- };
-
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- /*
- * reset pin for Z-Wave
- * active-low, >= 20ns
- */
- zwave_pins: zwave_pinmux {
- mux {
- pins = "gpio59";
- function = "gpio";
- output-high;
- };
- };
-
- serial_1_pins: serial1_pinmux {
- mux {
- pins = "gpio8", "gpio9",
- "gpio10", "gpio11";
- function = "blsp_uart1";
- bias-disable;
- };
- };
-
- bt_pins: bt_pinmux {
- mux_reset {
- pins = "gpio66";
- function = "gpio";
- output-high;
- };
-
- mux_pwr {
- pins = "gpio68";
- function = "gpio";
- output-high;
- };
- };
-
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
-
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- i2c_1_pins: i2c_1_pinmux {
- mux {
- pins = "gpio12", "gpio13";
- function = "blsp_i2c1";
- bias-disable;
- };
- };
-
- keys_pins: keys_pinmux {
- mux_1 {
- pins = "gpio39", "gpio40", "gpio42", "gpio47";
- function = "gpio";
- bias-disable;
- };
-
- mux_2 {
- pins = "gpio2";
- function = "gpio";
- input;
- };
- };
-
- sd_pins: sd_pins {
- mux {
- function = "sdio";
- pins = "gpio23", "gpio24", "gpio25", "gpio26",
- "gpio28", "gpio29", "gpio30", "gpio31";
- drive-strength = <4>;
- };
-
- mux_sd_clk {
- function = "sdio";
- pins = "gpio27";
- drive-strength = <16>;
- };
-
- mux_sd7 {
- function = "sdio";
- pins = "gpio32";
- drive-strength = <4>;
- bias-disable;
- };
- };
-
- aud_pins: aud_pinmux {
- mux {
- pins = "gpio48", "gpio49", "gpio50", "gpio51";
- function = "aud_pin";
- };
- };
-
- alc1304_pins: alc1304_pinmux {
- mux_1 {
- pins = "gpio44";
- function = "gpio";
- bias-disable;
- };
-
- mux_2 {
- pins = "gpio45";
- function = "gpio";
- bias-disable;
- };
- };
-
- cx2902x_reset: cx2902x_pinmux {
- mux_1 {
- pins = "gpio64";
- function = "gpio";
- bias-disable;
- };
-
- mux_2 {
- pins = "gpio65";
- function = "gpio";
- bias-disable;
- };
- };
-
- lte_pins: lte_pinmux {
- mux_en {
- pins = "gpio20";
- function = "gpio";
- output-high;
- };
-
- mux_reset {
- pins = "gpio35";
- function = "gpio";
- input;
- };
- };
-
- usb3_pins: usb3_pinmux {
- mux_en {
- pins = "gpio36";
- function = "gpio";
- output-high;
- };
-
- mux_flt {
- pins = "gpio4";
- function = "gpio";
- input;
- };
- };
-
- mcu_pins: mcu_pinmux {
- mux_boot {
- pins = "gpio38";
- function = "gpio";
- output-low;
- };
-
- mux_reset {
- pins = "gpio5";
- function = "gpio";
- output-high;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_i2c4 {
- /*
- * There is no driver for the following devices:
- * - CY8C4014LQI@14 : Touch-Sensor for buttons on top
- * - MINI54FDE@15 : MCU for Fan/RGB LED/Thermal control
- * - ALC5629@18 : I2S/PCM Audio DAC
- * - CX20924@41 : Voice Input Processor
- */
- pinctrl-0 = <&i2c_1_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- led-controller@32 {
- compatible = "ti,lp55231";
- reg = <0x32>;
- clock-mode = /bits/ 8 <0>;
- enable-gpio = <&tlmm 1 GPIO_ACTIVE_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- led@0 {
- chan-name = "green:wan";
- led-cur = /bits/ 8 <50>;
- max-cur = /bits/ 8 <100>;
- reg = <0x0>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_WAN;
- };
-
- led@1 {
- chan-name = "blue:wan";
- led-cur = /bits/ 8 <50>;
- max-cur = /bits/ 8 <100>;
- reg = <0x1>;
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_WAN;
- };
-
- led@2 {
- chan-name = "green:lan";
- led-cur = /bits/ 8 <50>;
- max-cur = /bits/ 8 <100>;
- reg = <0x2>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_LAN;
- };
-
- led@3 {
- chan-name = "blue:lan";
- led-cur = /bits/ 8 <50>;
- max-cur = /bits/ 8 <100>;
- reg = <0x3>;
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_LAN;
- };
-
- led@4 {
- chan-name = "green:wlan-2";
- led-cur = /bits/ 8 <50>;
- max-cur = /bits/ 8 <100>;
- reg = <0x4>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_WLAN;
- function-enumerator = <2>;
- linux,default-trigger = "phy0tpt";
- };
-
- led@5 {
- chan-name = "blue:wlan-2";
- led-cur = /bits/ 8 <50>;
- max-cur = /bits/ 8 <100>;
- reg = <0x5>;
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_WLAN;
- function-enumerator = <2>;
- };
-
- led@6 {
- chan-name = "red:wan";
- led-cur = /bits/ 8 <50>;
- max-cur = /bits/ 8 <100>;
- reg = <0x6>;
- color = <LED_COLOR_ID_RED>;
- function = LED_FUNCTION_WAN;
- };
-
- led@7 {
- chan-name = "red:lan";
- led-cur = /bits/ 8 <50>;
- max-cur = /bits/ 8 <100>;
- reg = <0x7>;
- color = <LED_COLOR_ID_RED>;
- function = LED_FUNCTION_LAN;
- };
-
- led@8 {
- chan-name = "red:wlan-2";
- led-cur = /bits/ 8 <50>;
- max-cur = /bits/ 8 <100>;
- reg = <0x8>;
- color = <LED_COLOR_ID_RED>;
- function = LED_FUNCTION_WLAN;
- function-enumerator = <2>;
- };
- };
-
- led-controller@33 {
- compatible = "ti,lp55231";
- reg = <0x33>;
- clock-mode = /bits/ 8 <0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- led@0 {
- chan-name = "green:wlan-5";
- led-cur = /bits/ 8 <50>;
- max-cur = /bits/ 8 <100>;
- reg = <0x0>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_WLAN;
- linux,default-trigger = "phy1tpt";
- function-enumerator = <5>;
- };
-
- led@1 {
- chan-name = "blue:wlan-5";
- led-cur = /bits/ 8 <50>;
- max-cur = /bits/ 8 <100>;
- reg = <0x1>;
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_WLAN;
- function-enumerator = <5>;
- };
-
- led@2 {
- chan-name = "green:wan-4";
- led-cur = /bits/ 8 <50>;
- max-cur = /bits/ 8 <100>;
- reg = <0x2>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_WAN; /* WWAN/LTE/4G */
- function-enumerator = <4>; /* WWAN/LTE/4G */
- };
-
- led@3 {
- chan-name = "blue:wan-4";
- led-cur = /bits/ 8 <50>;
- max-cur = /bits/ 8 <100>;
- reg = <0x3>;
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_WAN; /* WWAN/LTE/4G */
- function-enumerator = <4>; /* WWAN/LTE/4G */
- };
-
- led_cloud_green: led@4 {
- chan-name = "green:power";
- led-cur = /bits/ 8 <50>;
- max-cur = /bits/ 8 <100>;
- reg = <0x4>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_POWER;
- };
-
- led@5 {
- chan-name = "blue:power";
- led-cur = /bits/ 8 <50>;
- max-cur = /bits/ 8 <100>;
- reg = <0x5>;
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_POWER;
- };
-
- led@6 {
- chan-name = "red:wlan-5";
- led-cur = /bits/ 8 <50>;
- max-cur = /bits/ 8 <100>;
- reg = <0x6>;
- color = <LED_COLOR_ID_RED>;
- function = LED_FUNCTION_WLAN;
- function-enumerator = <5>;
- };
-
- led@7 {
- chan-name = "red:wan-4";
- led-cur = /bits/ 8 <50>;
- max-cur = /bits/ 8 <100>;
- reg = <0x7>;
- color = <LED_COLOR_ID_RED>;
- function = LED_FUNCTION_WAN; /* WWAN/LTE/4G */
- function-enumerator = <4>; /* WWAN/LTE/4G */
- };
-
- led_cloud_red: led@8 {
- chan-name = "red:power";
- led-cur = /bits/ 8 <50>;
- max-cur = /bits/ 8 <100>;
- reg = <0x8>;
- color = <LED_COLOR_ID_RED>;
- function = LED_FUNCTION_POWER;
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>, <&uart0_ctrl_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&blsp1_uart2 {
- pinctrl-0 = <&serial_1_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&crypto {
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&mdio {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- reset-gpios = <&tlmm 41 GPIO_ACTIVE_LOW>;
-};
-
-&prng {
- status = "okay";
-};
-
-&vqmmc {
- status = "okay";
-};
-
-&sdhci {
- status = "okay";
- pinctrl-0 = <&sd_pins>;
- pinctrl-names = "default";
- vqmmc-supply = <&vqmmc>;
- non-removable;
- #address-cells = <1>;
- #size-cells = <0>;
-
- emmc@0 {
- compatible = "mmc-card";
- reg = <0>;
- };
-};
-
-&usb2 {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&usb3 {
- status = "okay";
-
- pinctrl-0 = <&usb3_pins>, <<e_pins>;
- pinctrl-names = "default";
-
- dwc3@8a00000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- device@1 {
- compatible = "usb1bc7,1900";
- reg = <1>;
- };
- };
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
- label = "lan";
-};
-
-&swport5 {
- status = "okay";
- label = "wan";
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "Sony-NCP-HG100-Cellular";
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "Sony-NCP-HG100-Cellular";
-};
-
-&watchdog {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "EdgeCore OAP-100";
- compatible = "edgecore,oap100";
-
- aliases {
- led-boot = &led_system;
- led-failsafe = &led_system;
- led-running = &led_system;
- led-upgrade = &led_system;
- };
-
- chosen {
- bootargs-append = " root=/dev/ubiblock0_1";
- };
-
- soc {
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- tcsr@194b000 {
- /* select hostmode */
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- usb2@60f8800 {
- status = "okay";
-
- dwc3@6000000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- usb2_port1: port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
- };
- };
-
- usb3@8af8800 {
- status = "okay";
-
- dwc3@8a00000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- usb3_port1: port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
-
- usb3_port2: port@2 {
- reg = <2>;
- #trigger-source-cells = <0>;
- };
- };
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- key {
- compatible = "gpio-keys";
-
- button@1 {
- label = "reset";
- linux,code = <KEY_RESTART>;
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,input-type = <1>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_system: led_system {
- label = "green:system";
- gpios = <&tlmm 22 GPIO_ACTIVE_HIGH>;
- };
-
- led_2g {
- label = "blue:wlan2g";
- gpios = <&tlmm 34 GPIO_ACTIVE_HIGH>;
- };
-
- led_5g {
- label = "blue:wlan5g";
- gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>;
- };
- };
-
- gpio_export {
- compatible = "gpio-export";
- #size-cells = <0>;
-
- usb {
- gpio-export,name = "usb-power";
- gpio-export,output = <1>;
- gpios = <&tlmm 44 GPIO_ACTIVE_HIGH>;
- };
-
- poe {
- gpio-export,name = "poe-power";
- gpio-export,output = <0>;
- gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&tlmm {
- serial_0_pins: serial_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
-
- pinmux_cs {
- function = "gpio";
- pins = "gpio12";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-
- nand_pins: nand_pins {
- pullups {
- pins = "gpio53", "gpio58", "gpio59";
- function = "qpic";
- bias-pull-up;
- };
-
- pulldowns {
- pins = "gpio54", "gpio55", "gpio56",
- "gpio57", "gpio60", "gpio61",
- "gpio62", "gpio63", "gpio64",
- "gpio65", "gpio66", "gpio67",
- "gpio68", "gpio69";
- function = "qpic";
- bias-pull-down;
- };
- };
-
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- reg = <0>;
- linux,modalias = "m25p80", "gd25q256";
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition0@0 {
- label = "0:SBL1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
- partition1@40000 {
- label = "0:MIBIB";
- reg = <0x00040000 0x00020000>;
- read-only;
- };
- partition2@60000 {
- label = "0:QSEE";
- reg = <0x00060000 0x00060000>;
- read-only;
- };
- partition3@c0000 {
- label = "0:CDT";
- reg = <0x000c0000 0x00010000>;
- read-only;
- };
- partition4@d0000 {
- label = "0:DDRPARAMS";
- reg = <0x000d0000 0x00010000>;
- read-only;
- };
- partition5@e0000 {
- label = "0:APPSBLENV";
- reg = <0x000e0000 0x00010000>;
- read-only;
- };
- partition6@f0000 {
- label = "0:APPSBL";
- reg = <0x000f0000 0x00080000>;
- read-only;
- };
- partition7@170000 {
- label = "0:ART";
- reg = <0x00170000 0x00010000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
- };
- };
-};
-
-&nand {
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- nand@0 {
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "rootfs";
- reg = <0x00000000 0x4000000>;
- };
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
- qcom,ath10k-calibration-variant = "Edgecore OAP100";
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
- qcom,ath10k-calibration-variant = "Edgecore OAP100";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- aliases {
- led-boot = &led_status_white;
- led-failsafe = &led_status_red;
- led-running = &led_status_green;
- led-upgrade = &led_status_blue;
- label-mac-device = &gmac;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
-
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- };
-
- counter@4a1000 {
- compatible = "qcom,qca-gcnt";
- reg = <0x4a1000 0x4>;
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- status = "okay";
-
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
-
- wps {
- label = "wps";
- gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led-0 {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 63 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- };
-
- led-1 {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_RED>;
- gpios = <&tlmm 64 GPIO_ACTIVE_HIGH>;
- panic-indicator;
- };
-
- led_status_green: led-2 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 53 GPIO_ACTIVE_HIGH>;
- };
-
- led_status_red: led-3 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_RED>;
- gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
- };
-
- led_status_blue: led-4 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 57 GPIO_ACTIVE_HIGH>;
- };
-
- led_status_white: led-5 {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&vqmmc {
- status = "okay";
-};
-
-&sdhci {
- status = "okay";
-
- pinctrl-0 = <&sd_pins>;
- pinctrl-names = "default";
- cd-gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
- vqmmc-supply = <&vqmmc>;
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&tlmm {
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
-
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- i2c_0_pins: i2c_0_pinmux {
- pinmux {
- function = "blsp_i2c0";
- pins = "gpio58", "gpio59";
- bias-disable;
- };
- };
-
- sd_pins: sd_pins {
- pinmux {
- function = "sdio";
- pins = "gpio23", "gpio24", "gpio25", "gpio26",
- "gpio28", "gpio29", "gpio30", "gpio31";
- drive-strength = <10>;
- };
-
- pinmux_sd_clk {
- function = "sdio";
- pins = "gpio27";
- drive-strength = <16>;
- };
-
- pinmux_sd7 {
- function = "sdio";
- pins = "gpio32";
- drive-strength = <10>;
- bias-disable;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_i2c3 {
- pinctrl-0 = <&i2c_0_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-
- led-controller@27 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "ti,tlc59108"; /* really is tlc59208f */
- reg = <0x27>;
-
- led0@0 {
- label = "rgb:led0";
- reg = <0x0>;
- linux,default-trigger = "default-on";
- };
-
- led1@1 {
- label = "rgb:led1";
- reg = <0x1>;
- linux,default-trigger = "default-on";
- };
-
- led2@2 {
- label = "rgb:led2";
- reg = <0x2>;
- linux,default-trigger = "default-on";
- };
-
- led3@3 {
- label = "rgb:led3";
- reg = <0x3>;
- linux,default-trigger = "default-on";
- };
-
- led4@4 {
- label = "rgb:led4";
- reg = <0x4>;
- linux,default-trigger = "default-on";
- };
-
- led5@5 {
- label = "rgb:led5";
- reg = <0x5>;
- linux,default-trigger = "default-on";
- };
-
- led6@6 {
- label = "rgb:led6";
- reg = <0x6>;
- linux,default-trigger = "default-on";
- };
-
- led7@7 {
- label = "rgb:led7";
- reg = <0x7>;
- linux,default-trigger = "default-on";
- };
- };
-};
-
-&blsp1_uart1 {
- status = "okay";
-
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport1 {
- status = "okay";
-
- label = "wan";
-};
-
-&swport2 {
- status = "okay";
-
- label = "lan1";
-};
-
-&swport3 {
- status = "okay";
-
- label = "lan2";
-};
-
-&swport4 {
- status = "okay";
-
- label = "lan3";
-};
-
-ðphy4 {
- status = "disabled";
-};
-
-&pcie0 {
- status = "okay";
-
- perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
- wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- compatible = "qcom,ath10k";
- status = "okay";
- reg = <0x00010000 0 0 0 0>;
- ieee80211-freq-limit = <5470000 5875000>;
- qcom,ath10k-calibration-variant = "Netgear-Orbi-Pro-SRK60";
- };
- };
-};
-
-&wifi0 {
- status = "okay";
-
- qcom,ath10k-calibration-variant = "Netgear-Orbi-Pro-SRK60";
-};
-
-&wifi1 {
- status = "okay";
-
- qcom,ath10k-calibration-variant = "Netgear-Orbi-Pro-SRK60";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/* Copyright (c) 2017-2020, Sven Eckelmann <sven@narfation.org>
- * Copyright (c) 2018, Marek Lindner <marek.lindner@kaiwoo.ai>
- */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "Plasma Cloud PA2200";
- compatible = "plasmacloud,pa2200";
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART >;
- };
- };
-
- aliases {
- led-boot = &led_power_orange;
- led-failsafe = &led_status_blue;
- led-running = &led_power_orange;
- led-upgrade = &led_status_blue;
- label-mac-device = &swport4;
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_power_orange: power_orange {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_ORANGE>;
- gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
- };
-
- 2g_blue {
- label = "blue:2g";
- gpios = <&tlmm 46 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy1tpt";
- };
-
- 2g_green {
- label = "green:5g1";
- gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy0tpt";
- };
-
- 5g2_green {
- label = "green:5g2";
- gpios = <&tlmm 48 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy2tpt";
- };
-
- led_status_blue: status_blue {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pin {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
- pin_cs {
- function = "gpio";
- pins = "gpio12";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- /* partitions are passed via bootloader */
- partitions {
- partition-art {
- label = "0:ART";
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_gmac0: macaddr@0 {
- reg = <0x0 0x6>;
- };
-
- macaddr_gmac1: macaddr@6 {
- reg = <0x6 0x6>;
- };
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
-
- precal_art_9000: precal@9000 {
- reg = <0x9000 0x2f20>;
- };
- };
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
- perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
- wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi2: wifi@1,0 {
- compatible = "qcom,ath10k";
- status = "okay";
- reg = <0x00010000 0 0 0 0>;
- qcom,ath10k-calibration-variant = "PlasmaCloud-PA2200";
- ieee80211-freq-limit = <5170000 5350000>;
-
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_9000>;
- };
- };
-};
-
-&mdio {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
- label = "ethernet1";
-
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_gmac0>;
-};
-
-&swport5 {
- status = "okay";
- label = "ethernet2";
-
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_gmac1>;
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "PlasmaCloud-PA2200";
-
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "PlasmaCloud-PA2200";
- ieee80211-freq-limit = <5470000 5875000>;
-
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019-r619ac.dtsi"
-
-/ {
- model = "P&W R619AC 128M";
- compatible = "p2w,r619ac-128m";
-};
-
-&nand_rootfs {
- /*
- * Watch out: stock MIBIB is set up for a 64MiB chip.
- * If a 128MiB flash chip is used, make sure to have
- * the right values in MIBIB or the device might not
- * boot.
- */
- reg = <0x0 0x8000000>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019-r619ac.dtsi"
-
-/ {
- model = "P&W R619AC 64M";
- compatible = "p2w,r619ac-64m";
-};
-
-&nand_rootfs {
- reg = <0x0 0x4000000>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- chosen {
- bootargs-append = " ubi.mtd=ubi root=/dev/ubiblock0_1";
- };
-
- aliases {
- led-boot = &led_sys;
- led-failsafe = &led_sys;
- led-running = &led_sys;
- led-upgrade = &led_sys;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2@60f8800 {
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_sys: led-0 {
- gpios = <&tlmm 39 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_POWER;
- };
-
- led-1 {
- gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy0tpt";
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_WLAN;
- function-enumerator = <0>;
- };
-
- led-2 {
- gpios = <&tlmm 50 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy1tpt";
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_WLAN;
- function-enumerator = <1>;
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- status = "okay";
-
- flash@0 {
- reg = <0>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SBL1";
- reg = <0x0 0x40000>;
- read-only;
- };
-
- partition@40000 {
- label = "MIBIB";
- reg = <0x40000 0x20000>;
- read-only;
- };
-
- partition@60000 {
- label = "QSEE";
- reg = <0x60000 0x60000>;
- read-only;
- };
-
- partition@c0000 {
- label = "CDT";
- reg = <0xc0000 0x10000>;
- read-only;
- };
-
- partition@d0000 {
- label = "DDRPARAMS";
- reg = <0xd0000 0x10000>;
- read-only;
- };
-
- partition@e0000 {
- label = "APPSBLENV";
- reg = <0xe0000 0x10000>;
- read-only;
- };
-
- partition@f0000 {
- label = "APPSBL";
- reg = <0xf0000 0x80000>;
- read-only;
- };
-
- partition@170000 {
- label = "ART";
- reg = <0x170000 0x10000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
- };
- };
-};
-
-&nand {
- status = "okay";
-
- nand@0 {
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- nand_rootfs: partition@0 {
- label = "ubi";
- /* reg defined in 64M/128M variant dts. */
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&pcie_pins>;
- perst-gpio = <&tlmm 4 GPIO_ACTIVE_LOW>;
- wake-gpio = <&tlmm 40 GPIO_ACTIVE_HIGH>;
-
- /* Free slot for use */
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
- };
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&sdhci {
- pinctrl-0 = <&sd_0_pins>;
- pinctrl-names = "default";
- vqmmc-supply = <&vqmmc>;
- status = "okay";
-};
-
-&tlmm {
- pcie_pins: pcie_pinmux {
- mux {
- pins = "gpio2";
- function = "gpio";
- output-low;
- bias-pull-down;
- };
- };
-
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
-
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- sd_0_pins: sd_0_pinmux {
- mux_1 {
- pins = "gpio23", "gpio24", "gpio25", "gpio26", "gpio28";
- function = "sdio";
- drive-strength = <10>;
- };
-
- mux_2 {
- pins = "gpio27";
- function = "sdio";
- drive-strength = <16>;
- };
- };
-
- serial_0_pins: serial0-pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-};
-
-ðphy0 {
- qcom,single-led-1000;
- qcom,single-led-100;
- qcom,single-led-10;
-};
-
-ðphy1 {
- qcom,single-led-1000;
- qcom,single-led-100;
- qcom,single-led-10;
-};
-
-ðphy2 {
- qcom,single-led-1000;
- qcom,single-led-100;
- qcom,single-led-10;
-};
-
-ðphy3 {
- qcom,single-led-1000;
- qcom,single-led-100;
- qcom,single-led-10;
-};
-
-ðphy4 {
- qcom,single-led-1000;
- qcom,single-led-100;
- qcom,single-led-10;
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport1 {
- status = "okay";
-
- label = "lan4";
-};
-
-&swport2 {
- status = "okay";
-
- label = "lan3";
-};
-
-&swport3 {
- status = "okay";
-
- label = "lan2";
-};
-
-&swport4 {
- status = "okay";
-
- label = "lan1";
-};
-
-&swport5 {
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&vqmmc {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
- qcom,ath10k-calibration-variant = "P&W-R619AC";
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
- qcom,ath10k-calibration-variant = "P&W-R619AC";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019-orbi.dtsi"
-
-/ {
- model = "NETGEAR RBR40";
- compatible = "netgear,rbr40";
-
- chosen {
- bootargs = "root=/dev/mmcblk0p20 blkdevparts=mmcblk0:512K@17K(0:SBL1)ro,512K(0:BOOTCONFIG)ro,512K(0:QSEE)ro,512K(0:QSEE_ALT)ro,256K(0:CDT)ro,256K(0:CDT_ALT)ro,256K(0:DDRPARAMS)ro,256K(0:APPSBLENV)ro,1M(0:APPSBL)ro,1M(0:APPSBL_ALT)ro,256K(0:ART)ro,256K(ARTMTD)ro,2M(language)ro,256K(config)ro,256K(pot)ro,256K(traffic_meter)ro,256K(pot_bak)ro,256K(traffic_meter.bak)ro,3840K(kernel),31488K(rootfs),35328K@9233K(firmware),256K(mtdoops)ro,1457651200(reserved)ro,-(unallocated) rootfstype=squashfs,ext4 rootwait";
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019-orbi.dtsi"
-
-/ {
- model = "NETGEAR RBR50";
- compatible = "netgear,rbr50";
-
- chosen {
- bootargs = "root=/dev/mmcblk0p20 blkdevparts=mmcblk0:512K@17K(0:SBL1)ro,512K(0:BOOTCONFIG)ro,512K(0:QSEE)ro,512K(0:QSEE_ALT)ro,256K(0:CDT)ro,256K(0:CDT_ALT)ro,256K(0:DDRPARAMS)ro,256K(0:APPSBLENV)ro,1M(0:APPSBL)ro,1M(0:APPSBL_ALT)ro,256K(0:ART)ro,256K(ARTMTD)ro,2M(language)ro,256K(config)ro,256K(pot)ro,256K(traffic_meter)ro,256K(pot_bak)ro,256K(traffic_meter.bak)ro,3840K(kernel),31488K(rootfs),35328K@9233K(firmware),256K(mtdoops)ro,1457651200(reserved)ro,-(unallocated) rootfstype=squashfs,ext4 rootwait";
- };
-
- soc {
- usb2@60f8800 {
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
- };
- };
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019-orbi.dtsi"
-
-/ {
- model = "NETGEAR RBS40";
- compatible = "netgear,rbs40";
-
- chosen {
- bootargs = "root=/dev/mmcblk0p20 blkdevparts=mmcblk0:512K@17K(0:SBL1)ro,512K(0:BOOTCONFIG)ro,512K(0:QSEE)ro,512K(0:QSEE_ALT)ro,256K(0:CDT)ro,256K(0:CDT_ALT)ro,256K(0:DDRPARAMS)ro,256K(0:APPSBLENV)ro,1M(0:APPSBL)ro,1M(0:APPSBL_ALT)ro,256K(0:ART)ro,256K(ARTMTD)ro,2M(language)ro,256K(config)ro,256K(pot)ro,256K(traffic_meter)ro,256K(pot_bak)ro,256K(traffic_meter.bak)ro,3840K(kernel),31488K(rootfs),35328K@9233K(firmware),256K(mtdoops)ro,1457651200(reserved)ro,-(unallocated) rootfstype=squashfs,ext4 rootwait";
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019-orbi.dtsi"
-
-/ {
- model = "NETGEAR RBS50";
- compatible = "netgear,rbs50";
-
- chosen {
- bootargs = "root=/dev/mmcblk0p20 blkdevparts=mmcblk0:512K@17K(0:SBL1)ro,512K(0:BOOTCONFIG)ro,512K(0:QSEE)ro,512K(0:QSEE_ALT)ro,256K(0:CDT)ro,256K(0:CDT_ALT)ro,256K(0:DDRPARAMS)ro,256K(0:APPSBLENV)ro,1M(0:APPSBL)ro,1M(0:APPSBL_ALT)ro,256K(0:ART)ro,256K(ARTMTD)ro,2M(language)ro,256K(config)ro,256K(pot)ro,256K(traffic_meter)ro,256K(pot_bak)ro,256K(traffic_meter.bak)ro,3840K(kernel),31488K(rootfs),35328K@9233K(firmware),256K(mtdoops)ro,1457651200(reserved)ro,-(unallocated) rootfstype=squashfs,ext4 rootwait";
- };
-
- soc {
- usb2@60f8800 {
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
- };
- };
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "ASUS RT-AC42U";
- compatible = "asus,rt-ac42u";
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x10000000>; /* 256MB */
- };
-
- aliases {
- led-boot = &led_power;
- led-failsafe = &led_power;
- led-running = &led_power;
- led-upgrade = &led_power;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb3@8af8800 {
- status = "okay";
-
- dwc3@8a00000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- usb3_port1: port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
-
- usb3_port2: port@2 {
- reg = <2>;
- #trigger-source-cells = <0>;
- };
- };
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
-
- wps {
- label = "wps";
- gpios = <&tlmm 11 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_power: led-0 {
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_STATUS;
- gpios = <&tlmm 40 GPIO_ACTIVE_LOW>;
- };
-
- led-1 {
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_WAN;
- gpios = <&tlmm 61 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "90000.mdio-1:04:link";
- };
-
- led-2 {
- color = <LED_COLOR_ID_RED>;
- function = LED_FUNCTION_WAN;
- gpios = <&tlmm 68 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "none";
- };
-
- led-3 {
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_WLAN;
- function-enumerator = <0>;
- gpios = <&tlmm 52 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy1tpt";
- };
-
- led-4 {
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_WLAN;
- function-enumerator = <1>;
- gpios = <&tlmm 54 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy0tpt";
- };
-
- led-5 {
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_LAN;
- function-enumerator = <1>;
- gpios = <&tlmm 45 GPIO_ACTIVE_LOW>;
- };
-
- led-6 {
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_LAN;
- function-enumerator = <2>;
- gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
- };
-
- led-7 {
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_LAN;
- function-enumerator = <3>;
- gpios = <&tlmm 42 GPIO_ACTIVE_LOW>;
- };
-
- led-8 {
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_LAN;
- function-enumerator = <4>;
- gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&tlmm {
- serial_0_pins: serial0_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- nand_pins: nand_pins {
- pullups {
- pins = "gpio53", "gpio58", "gpio59";
- function = "qpic";
- bias-pull-up;
- };
-
- pulldowns {
- pins = "gpio55", "gpio56", "gpio57", "gpio60",
- "gpio62", "gpio63", "gpio64", "gpio65",
- "gpio66", "gpio67", "gpio69";
- function = "qpic";
- bias-pull-down;
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&nand {
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- nand@0 {
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SBL1";
- reg = <0x00000000 0x00080000>;
- read-only;
- };
- partition@80000 {
- label = "MIBIB";
- reg = <0x00080000 0x00080000>;
- read-only;
- };
- partition@100000 {
- label = "QSEE";
- reg = <0x00100000 0x00100000>;
- read-only;
- };
- partition@200000 {
- label = "CDT";
- reg = <0x00200000 0x00080000>;
- read-only;
- };
- partition@280000 {
- label = "APPSBL";
- reg = <0x00280000 0x00140000>;
- read-only;
- };
- partition@3C0000 {
- label = "APPSBLENV";
- reg = <0x003C0000 0x00040000>;
- read-only;
- };
- partition@400000 {
- label = "ubi";
- reg = <0x00400000 0x07C00000>;
- };
- };
- };
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport1 {
- status = "okay";
-};
-
-&swport2 {
- status = "okay";
-};
-
-&swport3 {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
-};
-
-&swport5 {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "ASUS-RT-AC42U";
-};
-
-&pcie0 {
- status = "okay";
- perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
- wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
- clkreq-gpio = <&tlmm 39 GPIO_ACTIVE_LOW>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi2: wifi@1,0 {
- compatible = "qcom,ath10k";
- reg = <0x00010000 0 0 0 0>;
-
- qcom,ath10k-calibration-variant = "ASUS-RT-AC42U";
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: ISC
-// Copyright (c) 2015, The Linux Foundation. All rights reserved.
-// Copyright (c) 2019, Cezary Jackiewicz <cezary@eko.one.pl>.
-// Copyright (c) 2020, Pawel Dembicki <paweldembicki@gmail.com>.
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/soc/qcom,tcsr.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "Cell C RTL30VW";
- compatible = "cellc,rtl30vw";
-
- aliases {
- led-boot = &led_power_blue;
- led-failsafe = &led_power_red;
- led-running = &led_power_blue;
- led-upgrade = &led_power_red;
- };
-
- chosen {
- bootargs-append = "ubi.mtd=ubifs root=/dev/ubiblock0_0 rootfstype=squashfs ro";
- };
-
- led_spi {
- compatible = "spi-gpio";
- #address-cells = <1>;
- #size-cells = <0>;
- num-chipselects = <1>;
-
- mosi-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
- cs-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>;
- sck-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
-
- led_gpio: led_gpio@0 {
- compatible = "fairchild,74hc595";
- reg = <0>;
- gpio-controller;
- #gpio-cells = <2>;
- registers-number = <2>;
- spi-max-frequency = <1000000>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_power_blue: power_blue {
- gpios = <&led_gpio 0 GPIO_ACTIVE_HIGH>;
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_BLUE>;
- default-state = "on";
- };
-
- led_power_red: power_red {
- gpios = <&led_gpio 1 GPIO_ACTIVE_HIGH>;
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_RED>;
- };
-
- tp28 {
- gpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;
- label = "ext:tp28";
- default-state = "keep";
- };
-
- tp27 {
- gpios = <&led_gpio 7 GPIO_ACTIVE_LOW>;
- label = "ext:tp27";
- default-state = "keep";
- };
-
- wlan2g {
- gpios = <&led_gpio 8 GPIO_ACTIVE_HIGH>;
- label = "blue:wlan2g";
- linux,default-trigger = "phy0tpt";
- };
-
- wlan5g {
- gpios = <&led_gpio 9 GPIO_ACTIVE_HIGH>;
- label = "blue:wlan5g";
- linux,default-trigger = "phy1tpt";
- };
-
- wps {
- gpios = <&led_gpio 10 GPIO_ACTIVE_HIGH>;
- function = LED_FUNCTION_WPS;
- color = <LED_COLOR_ID_BLUE>;
- };
-
- voip {
- gpios = <&led_gpio 11 GPIO_ACTIVE_HIGH>;
- label = "blue:voip";
- };
-
- s1 {
- gpios = <&led_gpio 12 GPIO_ACTIVE_HIGH>;
- label = "blue:s1";
- };
-
- s2 {
- gpios = <&led_gpio 13 GPIO_ACTIVE_HIGH>;
- label = "blue:s2";
- };
-
- s3 {
- gpios = <&led_gpio 14 GPIO_ACTIVE_HIGH>;
- label = "blue:s3";
- };
-
- s4 {
- gpios = <&led_gpio 15 GPIO_ACTIVE_HIGH>;
- label = "blue:s4";
- };
-
- signal {
- gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
- label = "red:signal";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- wps {
- label = "wps";
- linux,code = <KEY_WPS_BUTTON>;
- gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
- };
-
- reset {
- label = "reset";
- linux,code = <KEY_RESTART>;
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- };
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- /* select hostmode */
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2@60f8800 {
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>, <&tlmm 59 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- /*"n25q128a11" is required for proper nand recognition in u-boot. */
- compatible = "jedec,spi-nor", "n25q128a11";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x0 0x40000>;
- read-only;
- };
-
- partition@40000 {
- label = "0:MIBIB";
- reg = <0x40000 0x20000>;
- read-only;
- };
-
- partition@60000 {
- label = "0:QSEE";
- reg = <0x60000 0x60000>;
- read-only;
- };
-
- partition@c0000 {
- label = "0:CDT";
- reg = <0xc0000 0x10000>;
- read-only;
- };
-
- partition@d0000 {
- label = "0:DDRPARAMS";
- reg = <0xd0000 0x10000>;
- read-only;
- };
-
- partition@e0000 {
- label = "0:APPSBLENV";
- reg = <0xe0000 0x10000>;
- read-only;
- };
-
- partition@f0000 {
- label = "0:APPSBL";
- reg = <0xf0000 0x80000>;
- read-only;
- };
-
- partition@170000 {
- label = "0:ART";
- reg = <0x170000 0x10000>;
- read-only;
- };
-
- partition@180000 {
- label = "0:BOOTCONFIG";
- reg = <0x180000 0x10000>;
- read-only;
- };
- };
- };
-
- flash@1 {
- /*
- * Factory U-boot looks in 0:BOOTCONFIG partition for active
- * partitions settings and mangle partition config. So kernel
- * /kernel_1 and rootfs/rootfs_1 pairs can be swaped.
- * It isn't a problem but we never can be sure where OFW put
- * factory images. "spinand,mt29f" value is required for proper
- * nand recognition in u-boot.
- */
- compatible = "spi-nand","spinand,mt29f";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "kernel";
- reg = <0x0 0x400000>;
- };
-
- partition@400000 {
- label = "rootfs";
- reg = <0x400000 0x2000000>;
- };
-
- partition@2400000 {
- label = "kernel_1";
- reg = <0x2400000 0x400000>;
- };
-
- partition@2800000 {
- label = "rootfs_1";
- reg = <0x2800000 0x2000000>;
- };
-
- partition@4800000 {
- label = "ubifs";
- reg = <0x4800000 0x3800000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
-
- pinmux_cs {
- function = "gpio";
- pins = "gpio54", "gpio59";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "cellc,rtl30vw";
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "cellc,rtl30vw";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport3 {
- status = "okay";
-
- label = "lan1";
-};
-
-&swport4 {
- status = "okay";
-
- label = "lan2";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019-orbi.dtsi"
-
-/ {
- model = "NETGEAR SRR60";
- compatible = "netgear,srr60";
-
- chosen {
- bootargs = "root=/dev/mmcblk0p20 blkdevparts=mmcblk0:512K@17K(0:SBL1)ro,512K(0:BOOTCONFIG)ro,512K(0:QSEE)ro,512K(0:QSEE_1)ro,256K(0:CDT)ro,256K(0:CDT_1)ro,512K(0:BOOTCONFIG1)ro,256K(0:APPSBLENV)ro,1M(0:APPSBL)ro,1M(0:APPSBL_1)ro,256K(0:ART)ro,256K(ARTMTD)ro,2M(language)ro,256K(config)ro,256K(pot)ro,256K(traffic_meter)ro,256K(pot_bak)ro,256K(traffic_meter.bak)ro,3840K(kernel),31488K(rootfs),35328K@9233K(firmware),256K(mtdoops)ro,64K(cert)ro,3840K(kernel-2)ro,31488K(rootfs-2)ro,35328K@44881K(firmware-2)ro,5M(device_table)ro,17M(cp_file)ro,102737K(reserved)ro,-(unallocated) rootfstype=squashfs,ext4 rootwait";
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019-orbi.dtsi"
-
-/ {
- model = "NETGEAR SRS60";
- compatible = "netgear,srs60";
-
- chosen {
- bootargs = "root=/dev/mmcblk0p20 blkdevparts=mmcblk0:512K@17K(0:SBL1)ro,512K(0:BOOTCONFIG)ro,512K(0:QSEE)ro,512K(0:QSEE_1)ro,256K(0:CDT)ro,256K(0:CDT_1)ro,512K(0:BOOTCONFIG1)ro,256K(0:APPSBLENV)ro,1M(0:APPSBL)ro,1M(0:APPSBL_1)ro,256K(0:ART)ro,256K(ARTMTD)ro,2M(language)ro,256K(config)ro,256K(pot)ro,256K(traffic_meter)ro,256K(pot_bak)ro,256K(traffic_meter.bak)ro,3840K(kernel),31488K(rootfs),35328K@9233K(firmware),256K(mtdoops)ro,64K(cert)ro,3840K(kernel-2)ro,31488K(rootfs-2)ro,35328K@44881K(firmware-2)ro,5M(device_table)ro,17M(cp_file)ro,102737K(reserved)ro,-(unallocated) rootfstype=squashfs,ext4 rootwait";
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019-u4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/ {
- model = "Unielec U4019 (32M)";
- compatible = "unielec,u4019-32m","unielec,u4019","qcom,ipq4019";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
-
- flash@0 {
- reg = <0>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <24000000>;
- broken-flash-reset;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x0 0x40000>;
- read-only;
- };
- partition@40000 {
- label = "0:MIBIB";
- reg = <0x40000 0x20000>;
- read-only;
- };
- partition@60000 {
- label = "0:QSEE";
- reg = <0x60000 0x60000>;
- read-only;
- };
- partition@c0000 {
- label = "0:CDT";
- reg = <0xc0000 0x10000>;
- read-only;
- };
- partition@d0000 {
- label = "0:DDRPARAMS";
- reg = <0xd0000 0x10000>;
- read-only;
- };
- partition@e0000 {
- label = "0:APPSBLENV";
- reg = <0xe0000 0x10000>;
- read-only;
- };
- partition@f0000 {
- label = "0:APPSBL";
- reg = <0xf0000 0x80000>;
- read-only;
- };
- partition@170000 {
- label = "0:ART";
- reg = <0x170000 0x10000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
- partition@180000 {
- compatible = "denx,fit";
- label = "firmware";
- reg = <0x180000 0x1e80000>;
- };
- };
- };
-};
-
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- compatible = "unielec,u4019","qcom,ipq4019";
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
- reset-delay-us = <2000>;
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2@60f8800 {
- status = "okay";
-
- dwc3@6000000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
- };
- };
-
- usb3@8af8800 {
- status = "okay";
-
- dwc3@8a00000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
-
- port@2 {
- reg = <2>;
- #trigger-source-cells = <0>;
- };
- };
- };
-
- watchdog@b017000 {
- status = "okay";
- };
-
- aliases {
- led-boot = &led_status;
- led-failsafe = &led_status;
- led-running = &led_status;
- led-upgrade = &led_status;
- serial0 = &blsp1_uart1;
- serial1 = &blsp1_uart2;
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- led_status: led2 {
- label = "green:led2";
- gpios = <&tlmm 68 GPIO_ACTIVE_LOW>;
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&blsp1_uart2 {
- pinctrl-0 = <&serial_1_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&tlmm {
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- serial_0_pins: serial0-pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
- serial_1_pins: serial1_pinmux {
- mux {
- pins = "gpio8", "gpio9";
- function = "blsp_uart1";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
-
- pinmux_cs {
- function = "gpio";
- pins = "gpio12";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-
- led_pins: led_pinmux {
- mux {
- function = "gpio";
- pins = "gpio68";
- bias-disabled;
- output-low;
- };
- };
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "Linksys WHW03 V2 (Velop)";
- compatible = "linksys,whw03v2", "qcom,ipq4019";
-
- aliases {
- led-boot = &led_blue;
- led-failsafe = &led_red;
- led-running = &led_blue;
- led-upgrade = &led_red;
- };
-
- // The arguments rootfstype and ro are needed
- // to override the default bootargs
- chosen {
- bootargs-append = " root=/dev/ubiblock0_0 rootfstype=squashfs ro";
- stdout-path = &blsp1_uart1;
- };
-
- soc {
- ess-tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
- };
-
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-};
-
-
-&tlmm {
- mdio_pins: mdio-pinmux {
- mux-1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
-
- mux-2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- i2c_0_pins: i2c-0-pinmux {
- mux {
- function = "blsp_i2c0";
- pins = "gpio20", "gpio21";
- bias-disable;
- };
- };
-
- serial_0_pins: serial0-pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- serial_1_pins: serial1-pinmux {
- mux {
- pins = "gpio8", "gpio9", "gpio10", "gpio11";
- function = "blsp_uart1";
- bias-disable;
- };
- };
-
- spi_0_pins: spi-0-pinmux {
- mux {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
-
- mux-cs {
- pins = "gpio12";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-
- spi_1_pins: spi-1-pinmux {
- mux-1 {
- function = "blsp_spi1";
- pins = "gpio44", "gpio46","gpio47";
- bias-disable;
- };
-
- mux-2 {
- pins = "gpio31", "gpio45", "gpio49";
- function = "gpio";
- bias-pull-up;
- output-high;
- };
-
- host-interrupt {
- pins = "gpio42";
- function = "gpio";
- input;
- };
- };
-
- wifi_0_pins: wifi0-pinmux {
- btcoexist {
- bias-pull-up;
- drive-strength = <6>;
- function = "gpio";
- output-high;
- pins = "gpio52";
- };
- };
-
- zigbee-0 {
- gpio-hog;
- gpios = <29 GPIO_ACTIVE_HIGH>;
- bias-disable;
- output-low;
- };
-
- zigbee-1 {
- gpio-hog;
- gpios = <50 GPIO_ACTIVE_HIGH>;
- bias-disable;
- input;
- };
-
- bluetooth-enable {
- gpio-hog;
- gpios = <32 GPIO_ACTIVE_HIGH>;
- output-high;
- };
-};
-
-&mdio {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- phy-reset-gpios = <&tlmm 19 GPIO_ACTIVE_LOW>;
-};
-
-ðphy0 {
- status = "disabled";
-};
-
-ðphy1 {
- status = "disabled";
-};
-
-ðphy2 {
- status = "disabled";
-};
-
-ðphy3 {
- reg = <0x1b>;
-};
-
-ðphy4 {
- reg = <0x1c>;
-};
-
-&psgmiiphy {
- reg = <0x1d>;
-};
-
-&watchdog {
- status = "okay";
-};
-
-&prng {
- status = "okay";
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&cryptobam {
- num-channels = <4>;
- qcom,num-ees = <2>;
-
- status = "okay";
-};
-
-&crypto {
- status = "okay";
-};
-
-&blsp1_uart1 {
- status = "okay";
- pinctrl-0 = <&serial_0_pins>;
- pinctrl-names = "default";
-};
-
-&blsp1_uart2 {
- status = "okay";
- pinctrl-0 = <&serial_1_pins>;
- pinctrl-names = "default";
-
- bluetooth {
- compatible = "csr,8811";
-
- enable-gpios = <&tlmm 32 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&blsp1_spi2 {
- pinctrl-0 = <&spi_1_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- cs-gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
-
- zigbee@0 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- compatible = "silabs,em3581";
- reg = <0>;
- spi-max-frequency = <12000000>;
- };
-};
-
-&blsp1_i2c3 {
- pinctrl-0 = <&i2c_0_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-
- // RGB LEDs
- pca9633: led-controller@62 {
- compatible = "nxp,pca9633";
- nxp,hw-blink;
- reg = <0x62>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- led_red: red@0 {
- color = <LED_COLOR_ID_RED>;
- function = LED_FUNCTION_INDICATOR;
- reg = <0>;
- };
-
- led_green: green@1 {
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_INDICATOR;
- reg = <1>;
- };
-
- led_blue: blue@2 {
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_INDICATOR;
- reg = <2>;
- };
- };
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&nand {
- status = "okay";
-
- nand@0 {
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SBL1";
- reg = <0x0 0x100000>;
- read-only;
- };
-
- partition@100000 {
- label = "MIBIB";
- reg = <0x100000 0x100000>;
- read-only;
- };
-
- partition@200000 {
- label = "QSEE";
- reg = <0x200000 0x100000>;
- read-only;
- };
-
- partition@300000 {
- label = "CDT";
- reg = <0x300000 0x80000>;
- read-only;
- };
-
- partition@380000 {
- label = "APPSBL";
- reg = <0x380000 0x200000>;
- read-only;
- };
-
- partition@580000 {
- label = "ART";
- reg = <0x580000 0x80000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_gmac0: macaddr@0 {
- compatible = "mac-base";
- reg = <0x0 0x6>;
- #nvmem-cell-cells = <1>;
- };
-
- macaddr_gmac1: macaddr@6 {
- reg = <0x6 0x6>;
- };
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
-
- precal_art_9000: precal@9000 {
- reg = <0x9000 0x2f20>;
- };
- };
- };
-
- partition@600000 {
- label = "u_env";
- reg = <0x600000 0x80000>;
- };
-
- partition@680000 {
- label = "s_env";
- reg = <0x680000 0x40000>;
- };
-
- partition@6c0000 {
- label = "devinfo";
- reg = <0x6c0000 0x40000>;
- read-only;
- };
-
- partition@700000 {
- label = "kernel";
- reg = <0x700000 0xa100000>;
- };
-
- partition@d00000 {
- label = "rootfs";
- reg = <0xd00000 0x9b00000>;
- };
-
- partition@a800000 {
- label = "alt_kernel";
- reg = <0xa800000 0xa100000>;
- };
-
- partition@ae00000 {
- label = "alt_rootfs";
- reg = <0xae00000 0x9b00000>;
- };
-
- partition@14900000 {
- label = "sysdiag";
- reg = <0x14900000 0x200000>;
- read-only;
- };
-
- partition@14b00000 {
- label = "syscfg";
- reg = <0x14b00000 0xb500000>;
- read-only;
- };
- };
- };
-};
-
-&pcie0 {
- status = "okay";
-
- perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 40 GPIO_ACTIVE_LOW>;
- clkreq-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi2: wifi@1,0 {
- compatible = "qcom,ath10k";
- reg = <0x00010000 0 0 0 0>;
- };
- };
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
- label = "lan";
-
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_gmac1>;
-};
-
-&swport5 {
- status = "okay";
- label = "wan";
-
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_gmac0 0>;
-};
-
-&wifi0 {
- pinctrl-0 = <&wifi_0_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-
- qcom,coexist-support = <1>;
- qcom,coexist-gpio-pin = <0x34>;
-
- qcom,ath10k-calibration-variant = "linksys-whw03v2";
-
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_1000>, <&macaddr_gmac0 1>;
-};
-
-&wifi1 {
- status = "okay";
-
- ieee80211-freq-limit = <5170000 5330000>;
- qcom,ath10k-calibration-variant = "linksys-whw03v2";
-
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_5000>, <&macaddr_gmac0 2>;
-};
-
-&wifi2 {
- status = "okay";
-
- ieee80211-freq-limit = <5490000 5835000>;
- qcom,ath10k-calibration-variant = "linksys-whw03v2";
-
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_9000>, <&macaddr_gmac0 3>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (c) 2016, 2018 The Linux Foundation. All rights reserved.
- * Copyright (c) 2016 Google, Inc
- */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "Google WiFi (Gale)";
- compatible = "google,wifi", "google,gale-v2", "qcom,ipq4019";
-
- aliases {
- label-mac-device = &gmac0;
- led-boot = &led0_blue;
- led-failsafe = &led0_red;
- led-running = &led0_blue;
- led-upgrade = &led0_red;
- };
-
- chosen {
- /*
- * rootwait: in case we're booting from slow/async USB storage.
- */
- bootargs-append = " rootwait";
- stdout-path = &blsp1_uart1;
- };
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x20000000>; /* 512MB */
- };
-
- soc {
- edma@c080000 {
- /*
- * Factory bootloader (depthcharge) will fail to boot
- * if this exact path (soc/edma@c080000/gmac0) doesn't
- * exist.
- */
- gmac0: gmac0 {
- };
-
- /*
- * Factory bootloader (depthcharge) will fail to boot
- * if this exact path (soc/edma@c080000/gmac1) doesn't
- * exist.
- */
- gmac1 {
- };
- };
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&fw_pinmux>;
- pinctrl-names = "default";
-
- reset {
- label = "reset";
- gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-};
-
-&scm {
- qcom,sdi-enabled;
-};
-
-&tlmm {
- fw_pinmux: fw_pinmux {
- wp {
- pins = "gpio53";
- output-low;
- };
- recovery {
- pins = "gpio57";
- function = "gpio";
- bias-none;
- };
- developer {
- pins = "gpio41";
- bias-none;
- };
- };
-
- reset802_15_4 {
- pins = "gpio60";
- };
-
- led_reset {
- pins = "gpio22";
- output-high;
- };
-
- sys_reset {
- pins = "gpio19";
- output-high;
- };
-
- rx_active {
- pins = "gpio43";
- bias-pull,down;
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14","gpio15";
- };
- pinmux_cs {
- function = "gpio";
- pins = "gpio12";
- };
- pinconf {
- pins = "gpio13", "gpio14","gpio15";
- drive-strength = <12>;
- bias-disable;
- };
- pinconf_cs {
- pins = "gpio12";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-
- spi_1_pins: spi_1_pinmux {
- pinmux {
- function = "blsp_spi1";
- pins = "gpio44", "gpio46","gpio47";
- };
- pinmux_cs {
- function = "gpio";
- pins = "gpio45";
- };
- pinconf {
- pins = "gpio44", "gpio46","gpio47";
- drive-strength = <12>;
- bias-disable;
- };
- pinconf_cs {
- pins = "gpio45";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-
- serial_0_pins: serial0_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- serial_1_pins: serial1_pinmux {
- mux {
- pins = "gpio8", "gpio9", "gpio10", "gpio11";
- function = "blsp_uart1";
- bias-disable;
- };
- };
-
- i2c_0_pins: i2c_0_pinmux {
- mux {
- pins = "gpio20", "gpio21";
- function = "blsp_i2c0";
- drive-open-drain;
- };
- };
-
- i2c_1_pins: i2c_1_pinmux {
- mux {
- pins = "gpio34", "gpio35";
- function = "blsp_i2c1";
- drive-open-drain;
- };
- };
-
- sd_0_pins: sd_0_pinmux {
- sd0 {
- pins = "gpio23", "gpio24", "gpio25", "gpio26", "gpio29", "gpio30", "gpio31", "gpio32";
- function = "sdio";
- drive-strength = <10>;
- bias-pull-up;
- pull-up-res = <0>;
- };
- sdclk {
- pins = "gpio27";
- function = "sdio";
- drive-strength = <2>;
- bias-pull-up;
- pull-up-res = <0>;
- };
- sdcmd {
- pins = "gpio28";
- function = "sdio";
- drive-strength = <10>;
- bias-pull-up;
- pull-up-res = <0>;
- };
- };
-
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-disable;
- };
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-disable;
- };
- mux_3 {
- pins = "gpio40";
- function = "gpio";
- bias-disable;
- output-high;
- };
- };
-
- wifi1_1_pins: wifi2_pinmux {
- mux {
- pins = "gpio58";
- output-low;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_i2c3 {
- pinctrl-0 = <&i2c_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- tpm@20 {
- compatible = "infineon,slb9645tt";
- reg = <0x20>;
- powered-while-suspended;
- };
-};
-
-&blsp1_i2c4 {
- pinctrl-0 = <&i2c_1_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- led-controller@32 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "national,lp5523";
- reg = <0x32>;
- clock-mode = /bits/ 8 <1>;
-
-#if 1
- led0_red: led@0 {
- reg = <0>;
- chan-name = "LED0_Red";
- led-cur = /bits/ 8 <0x64>;
- max-cur = /bits/ 8 <0x78>;
- color = <LED_COLOR_ID_RED>;
- function = LED_FUNCTION_FAULT;
- };
-
- led@1 {
- reg = <1>;
- chan-name = "LED0_Green";
- led-cur = /bits/ 8 <0x64>;
- max-cur = /bits/ 8 <0x78>;
- color = <LED_COLOR_ID_GREEN>;
- };
-
- led0_blue: led@2 {
- reg = <2>;
- chan-name = "LED0_Blue";
- led-cur = /bits/ 8 <0x64>;
- max-cur = /bits/ 8 <0x78>;
- color = <LED_COLOR_ID_BLUE>;
- function = LED_FUNCTION_POWER;
- };
-#else
- /*
- * openwrt isn't ready to handle multi-intensity leds yet
- * # echo 255 255 255 > /sys/class/leds/tricolor/multi_intensity
- * # echo 255 > /sys/class/leds/tricolor/brightness
- */
- multi-led@2 {
- function = LED_FUNCTION_POWER;
- reg = <2>;
- color = <LED_COLOR_ID_RGB>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- led@0 {
- reg = <0>;
- chan-name = "tricolor";
- led-cur = /bits/ 8 <0x64>;
- max-cur = /bits/ 8 <0x78>;
- color = <LED_COLOR_ID_RED>;
- };
-
- led@1 {
- reg = <1>;
- chan-name = "tricolor";
- led-cur = /bits/ 8 <0x64>;
- max-cur = /bits/ 8 <0x78>;
- color = <LED_COLOR_ID_GREEN>;
- };
-
- led@2 {
- reg = <2>;
- chan-name = "tricolor";
- led-cur = /bits/ 8 <0x64>;
- max-cur = /bits/ 8 <0x78>;
- color = <LED_COLOR_ID_BLUE>;
- };
- };
-#endif
- };
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
- };
-};
-
-&blsp1_spi2 {
- pinctrl-0 = <&spi_1_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
-
- /*
- * This "spidev" was included in the manufacturer device tree. I
- * suspect it's the (unused; and removed from later HW spins) Zigbee
- * radio -- SiliconLabs EM3581 Zigbee? There's no driver or binding for
- * this at the moment.
- */
- spidev@0 {
- compatible = "spidev";
- reg = <0>;
- spi-max-frequency = <24000000>;
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&blsp1_uart2 {
- pinctrl-0 = <&serial_1_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&mdio {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
-};
-
-&prng {
- status = "okay";
-};
-
-&sdhci {
- status = "okay";
- pinctrl-0 = <&sd_0_pins>;
- pinctrl-names = "default";
- clock-frequency = <192000000>;
- vqmmc-supply = <&vqmmc>;
- non-removable;
-};
-
-&switch {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
-
- label = "lan";
-};
-
-&swport5 {
- status = "okay";
-};
-
-&usb2 {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&usb3 {
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&vqmmc {
- status = "okay";
-};
-
-&watchdog {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "GO_GALE";
-};
-
-&wifi1 {
- status = "okay";
- pinctrl-0 = <&wifi1_1_pins>;
- pinctrl-names = "default";
- qcom,ath10k-calibration-variant = "GO_GALE";
-};
+++ /dev/null
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
- * Copyright (c) 2019, Nguyen Dinh Phi <phi_nguyen@compex.com.sg>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "Compex WPJ419";
- compatible = "compex,wpj419", "qcom,ipq4019";
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x10000000>;
- };
-
- reserved-memory {
- ranges;
- rsvd1@87000000 {
- /* Reserved for other subsystem */
- reg = <0x87000000 0x500000>;
- no-map;
- };
- wifi_dump@87500000 {
- reg = <0x87500000 0x600000>;
- no-map;
- };
-
- rsvd2@87B00000 {
- /* Reserved for other subsystem */
- reg = <0x87B00000 0x500000>;
- no-map;
- };
- };
-
- chosen {
- bootargs-append = " ubi.mtd=ubi root=/dev/ubiblock0_1";
- };
-
- soc {
- pinctrl@1000000 {
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
-
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- serial_0_pins: serial_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- serial_1_pins: serial1_pinmux {
- mux {
- pins = "gpio8", "gpio9", "gpio10", "gpio11";
- function = "blsp_uart1";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- bias-disable;
- };
-
- pinmux_cs {
- function = "gpio";
- pins = "gpio12";
- bias-disable;
- output-high;
- };
- };
-
- i2c_0_pins: i2c_0_pinmux {
- mux {
- pins = "gpio20", "gpio21";
- function = "blsp_i2c0";
- bias-disable;
- };
- };
-
- nand_pins: nand_pins {
- pullups {
- pins = "gpio52", "gpio53", "gpio58", "gpio59";
- function = "qpic";
- bias-pull-up;
- };
-
- pulldowns {
- pins = "gpio54", "gpio55", "gpio56",
- "gpio57", "gpio60", "gpio61",
- "gpio62", "gpio63", "gpio64",
- "gpio65", "gpio66", "gpio67",
- "gpio68", "gpio69";
- function = "qpic";
- bias-pull-down;
- };
- };
-
- led_0_pins: led0_pinmux {
- mux_1 {
- pins = "gpio36";
- function = "led0";
- bias-pull-down;
- };
- mux_2 {
- pins = "gpio40";
- function = "led4";
- bias-pull-down;
- };
- };
- };
-
- blsp_dma: dma@7884000 {
- status = "okay";
- };
-
- spi_0: spi@78b5000 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>, <&tlmm 41 GPIO_ACTIVE_HIGH>;
- num-cs = <2>;
-
- flash0@0 {
- reg = <0>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <24000000>;
- broken-flash-reset;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x000000 0x040000>;
- read-only;
- };
-
- partition@40000 {
- label = "0:MIBIB";
- reg = <0x040000 0x020000>;
- read-only;
- };
-
- partition@60000 {
- label = "0:QSEE";
- reg = <0x060000 0x060000>;
- read-only;
- };
-
- partition@c0000 {
- label = "0:CDT";
- reg = <0x0c0000 0x010000>;
- read-only;
- };
-
- partition@d0000 {
- label = "0:DDRPARAMS";
- reg = <0x0d0000 0x010000>;
- read-only;
- };
-
- partition@e0000 {
- label = "u-boot-env";
- reg = <0x0e0000 0x010000>;
- };
-
- partition@f0000 {
- label = "u-boot";
- reg = <0x0f0000 0x080000>;
- read-only;
- };
-
- partition@170000 {
- label = "0:ART";
- reg = <0x170000 0x010000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
- };
- };
-
- nand@1 {
- reg = <1>;
- status = "okay";
- compatible = "spi-nand";
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- /* The device has 128MB, but we can only address
- * 64MB because of the bootloader's default settings.
- * This is due to the old mt29f driver,
- * which detected the deivce with only 64MB
- */
- partition@0 {
- label = "ubi";
- reg = <0x0000000 0x4000000>;
- };
- };
- };
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
- reset-delay-us = <5000>;
- };
-
- tcsr@194b000 {
- /* select hostmode */
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- i2c_0: i2c@78b7000 {
- pinctrl-0 = <&i2c_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- };
-
- serial@78af000 {
- pinctrl-0 = <&serial_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- };
-
- serial@78b0000 {
- pinctrl-0 = <&serial_1_pins>;
- pinctrl-names = "default";
- status = "okay";
- };
-
- usb3_ss_phy: ssphy@9a000 {
- status = "okay";
- };
-
- usb3_hs_phy: hsphy@a6000 {
- status = "okay";
- };
-
- usb3: usb3@8af8800 {
- status = "okay";
- };
-
- usb2_hs_phy: hsphy@a8000 {
- status = "okay";
- };
-
- usb2: usb2@60f8800 {
- status = "okay";
- };
-
- cryptobam: dma@8e04000 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
-
- qpic_bam: dma@7984000 {
- status = "okay";
- };
-
- pcie0: pci@40000000 {
- status = "okay";
- perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
- wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-};
-
-&nand {
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
-};
+++ /dev/null
-// SPDX-License-Identifier: ISC
-/*
- * Copyright (c) 2015 - 2016, The Linux Foundation. All rights reserved.
- * Copyright (c) 2020 Yanase Yuki <dev@zpc.sakura.ne.jp>
- */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "Buffalo WTR-M2133HP";
- compatible = "buffalo,wtr-m2133hp", "qcom,ipq4019";
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x20000000>;
- };
-
- chosen {
- /*
- * U-Boot adds "ubi.mtd=rootfs root=mtd:ubi_rootfs" to
- * kernel command line. But we use different partition names,
- * so we have to set correct parameters.
- */
- bootargs-append = " ubi.mtd=ubi root=/dev/ubiblock0_1";
- };
-
- aliases {
- led-boot = &led_power_blue;
- led-failsafe = &led_power_orange;
- led-running = &led_power_white;
- led-upgrade = &led_power_blue;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_power_white: power_white {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&tlmm 40 GPIO_ACTIVE_HIGH>;
- };
-
- led_power_orange: power_orange {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_ORANGE>;
- gpios = <&tlmm 25 GPIO_ACTIVE_HIGH>;
- };
-
- led_power_blue: power_blue {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&tlmm 43 GPIO_ACTIVE_HIGH>;
- };
-
- router_white {
- label = "white:router";
- gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>;
- };
-
- router_orange {
- label = "orange:router";
- gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
- };
-
- internet_white {
- label = "white:internet";
- gpios = <&tlmm 27 GPIO_ACTIVE_HIGH>;
- };
-
- internet_orange {
- label = "orange:internet";
- gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
- };
-
- wireless_white {
- label = "white:wireless";
- gpios = <&tlmm 24 GPIO_ACTIVE_HIGH>;
- };
-
- wireless_orange {
- label = "orange:wireless";
- gpios = <&tlmm 44 GPIO_ACTIVE_HIGH>;
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- auto_mode {
- label = "auto_mode";
- gpios = <&tlmm 9 GPIO_ACTIVE_LOW>;
- linux,code = <BTN_0>;
- linux,input-type = <EV_SW>;
- };
-
- router_mode {
- label = "router_mode";
- gpios = <&tlmm 10 GPIO_ACTIVE_LOW>;
- linux,code = <BTN_1>;
- linux,input-type = <EV_SW>;
- };
-
- ap_mode {
- label = "ap_mode";
- gpios = <&tlmm 11 GPIO_ACTIVE_LOW>;
- linux,code = <BTN_2>;
- linux,input-type = <EV_SW>;
- };
-
- reset {
- label = "reset";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
-
- wps {
- label = "AOSS Button";
- gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- };
- };
-};
-
-&tlmm {
- serial_0_pins: serial0_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
-
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- nand_pins: nand_pins {
- pullups {
- pins = "gpio52", "gpio53", "gpio58",
- "gpio59";
- function = "qpic";
- bias-pull-up;
- };
-
- pulldowns {
- pins = "gpio54", "gpio55", "gpio56",
- "gpio57", "gpio60", "gpio61",
- "gpio62", "gpio63", "gpio64",
- "gpio65", "gpio66", "gpio67",
- "gpio68", "gpio69";
- function = "qpic";
- bias-pull-down;
- };
- };
-
- usb_power {
- line-name = "USB power";
- gpios = <34 GPIO_ACTIVE_HIGH>;
- gpio-hog;
- output-high;
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@0,0 {
- compatible = "qcom,ath10k";
- reg = <0 0 0 0 0>;
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_9000>, <&macaddr_orgdata_32>;
- qcom,ath10k-calibration-variant = "Buffalo-WTR-M2133HP";
- };
- };
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&nand {
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- nand@0 {
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SBL1";
- reg = <0x0000000 0x0100000>;
- read-only;
- };
-
- partition@100000 {
- label = "MIBIB";
- reg = <0x0100000 0x0100000>;
- read-only;
- };
-
- partition@200000 {
- label = "BOOTCONFIG";
- reg = <0x0200000 0x0100000>;
- read-only;
- };
-
- partition@300000 {
- label = "QSEE";
- reg = <0x0300000 0x0100000>;
- read-only;
- };
-
- partition@400000 {
- label = "QSEE_1";
- reg = <0x0400000 0x0100000>;
- read-only;
- };
-
- partition@500000 {
- label = "CDT";
- reg = <0x0500000 0x0080000>;
- read-only;
- };
-
- partition@580000 {
- label = "CDT_1";
- reg = <0x0580000 0x0080000>;
- read-only;
- };
-
- partition@600000 {
- label = "BOOTCONFIG1";
- reg = <0x0600000 0x0080000>;
- read-only;
- };
-
- partition@680000 {
- label = "APPSBLENV";
- reg = <0x0680000 0x0080000>;
- };
-
- partition@700000 {
- label = "APPSBL";
- reg = <0x0700000 0x0200000>;
- read-only;
- };
-
- partition@900000 {
- label = "APPSBL_1";
- reg = <0x0900000 0x0200000>;
- read-only;
- };
-
- partition@b00000 {
- label = "ART";
- reg = <0x0b00000 0x0080000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
-
- precal_art_9000: precal@9000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- partition@b80000 {
- label = "ART_1";
- reg = <0x0b80000 0x0080000>;
- read-only;
- };
-
- orgdata: partition@c00000 {
- label = "ORGDATA";
- reg = <0x0c00000 0x0080000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_orgdata_20: macaddr@20 {
- reg = <0x20 0x6>;
- };
- macaddr_orgdata_26: macaddr@26 {
- reg = <0x26 0x6>;
- };
- macaddr_orgdata_2c: macaddr@2c {
- reg = <0x2c 0x6>;
- };
- macaddr_orgdata_32: macaddr@32 {
- reg = <0x32 0x6>;
- };
- };
- };
-
- partition@c80000 {
- label = "ORGDATA_1";
- reg = <0x0c80000 0x0080000>;
- read-only;
- };
-
- partition@d00000 {
- label = "ubi";
- reg = <0x0d00000 0x2900000>;
- };
-
- partition@3600000 {
- label = "rootfs_recover";
- reg = <0x3600000 0x2900000>;
- read-only;
- };
-
- partition@5f00000 {
- label = "user_property";
- reg = <0x5f00000 0x1a20000>;
- read-only;
- };
- };
- };
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_1000>, <&macaddr_orgdata_26>;
- qcom,ath10k-calibration-variant = "Buffalo-WTR-M2133HP";
- ieee80211-freq-limit = <2400000 2483000>;
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_5000>, <&macaddr_orgdata_2c>;
- qcom,ath10k-calibration-variant = "Buffalo-WTR-M2133HP";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport2 {
- status = "okay";
- label = "lan3";
-};
-
-&swport3 {
- status = "okay";
- label = "lan2";
-};
-
-&swport4 {
- status = "okay";
- label = "lan1";
-};
-
-&swport5 {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_orgdata_20>;
-};
-
-&mdio {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-/dts-v1/;
-
-#include "qcom-ipq4019-x1pro.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/ {
- model = "Telco X1 Pro";
- compatible = "tel,x1pro","qcom,ipq4019";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
-
- flash@0 {
- reg = <0>;
- compatible = "jedec,spi-nor";
- spi-max-frequency = <24000000>;
- broken-flash-reset;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x0 0x40000>;
- read-only;
- };
- partition@40000 {
- label = "0:MIBIB";
- reg = <0x40000 0x20000>;
- read-only;
- };
- partition@60000 {
- label = "0:QSEE";
- reg = <0x60000 0x60000>;
- read-only;
- };
- partition@c0000 {
- label = "0:CDT";
- reg = <0xc0000 0x10000>;
- read-only;
- };
- partition@d0000 {
- label = "0:DDRPARAMS";
- reg = <0xd0000 0x10000>;
- read-only;
- };
- partition@e0000 {
- label = "0:APPSBLENV";
- reg = <0xe0000 0x10000>;
- read-only;
- };
- partition@f0000 {
- label = "0:APPSBL";
- reg = <0xf0000 0x80000>;
- read-only;
- };
- art: partition@170000 {
- label = "0:ART";
- reg = <0x170000 0x10000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
- partition@180000 {
- compatible = "denx,fit";
- label = "firmware";
- reg = <0x180000 0x1e80000>;
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- compatible = "tel,x1pro","qcom,ipq4019";
- aliases {
- led-boot = &led_status;
- led-failsafe = &led_status;
- led-running = &led_status;
- led-upgrade = &led_status;
- serial0 = &blsp1_uart1;
- serial1 = &blsp1_uart2;
- };
-
- soc {
-
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
- reset-delay-us = <2000>;
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2@60f8800 {
- status = "okay";
-
- dwc3@6000000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
- };
- };
-
- usb3@8af8800 {
- status = "okay";
-
- dwc3@8a00000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
-
- port@2 {
- reg = <2>;
- #trigger-source-cells = <0>;
- };
- };
- };
-
- watchdog@b017000 {
- status = "okay";
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- led_status: status {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 68 GPIO_ACTIVE_LOW>;
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&blsp1_uart2 {
- pinctrl-0 = <&serial_1_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&tlmm {
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- serial_0_pins: serial0-pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
- serial_1_pins: serial1_pinmux {
- mux {
- pins = "gpio8", "gpio9";
- function = "blsp_uart1";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
-
- pinmux_cs {
- function = "gpio";
- pins = "gpio12";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-
- led_pins: led_pinmux {
- mux {
- function = "gpio";
- pins = "gpio68";
- bias-disabled;
- output-low;
- };
- };
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-/*
- * Device Tree Source for Linksys xx8300 (Dallas)
- *
- * Copyright (C) 2019, 2022 Jeff Kletsky
- * Updated 2020 Hans Geiblinger
- *
- */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
- //
- // OEM U-Boot provides either
- // init=/sbin/init rootfstype=ubifs ubi.mtd=11,2048 \
- // root=ubi0:ubifs rootwait rw
- // or the same with ubi.mtd=13,2048
- //
-
-/ {
- chosen {
- bootargs-append = " root=/dev/ubiblock0_0 rootfstype=squashfs ro";
- };
-
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2@60f8800 {
- status = "okay";
-
- dwc3@6000000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- usb2_port1: port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
- };
- };
-
- usb3@8af8800 {
- status = "okay";
-
- dwc3@8a00000 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- usb3_port1: port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
-
- usb3_port2: port@2 {
- reg = <2>;
- #trigger-source-cells = <0>;
- };
- };
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- regulator-usb-vbus {
- compatible = "regulator-fixed";
- regulator-name = "USB_VBUS";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- regulator-boot-on;
- gpio = <&tlmm 68 GPIO_ACTIVE_LOW>;
- };
-};
-
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_uart1 {
- status = "okay";
- pinctrl-0 = <&serial_0_pins>;
- pinctrl-names = "default";
-
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&nand {
- status = "okay";
-
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
-
- nand@0 {
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "sbl1";
- reg = <0x0 0x100000>;
- read-only;
- };
-
- partition@100000 {
- label = "mibib";
- reg = <0x100000 0x100000>;
- read-only;
- };
-
- partition@200000 {
- label = "qsee";
- reg = <0x200000 0x100000>;
- read-only;
- };
-
- partition@300000 {
- label = "cdt";
- reg = <0x300000 0x80000>;
- read-only;
- };
-
- partition@380000 {
- label = "appsblenv";
- reg = <0x380000 0x80000>;
- read-only;
- };
-
- partition@400000 {
- label = "ART";
- reg = <0x400000 0x80000>;
- read-only;
- };
-
- partition@480000 {
- label = "appsbl";
- reg = <0x480000 0x200000>;
- read-only;
- };
-
- partition@680000 {
- label = "u_env";
- reg = <0x680000 0x80000>;
- // writable -- U-Boot environment
- };
-
- partition@700000 {
- label = "s_env";
- reg = <0x700000 0x40000>;
- // writable -- Boot counter records
- };
-
- partition@740000 {
- label = "devinfo";
- reg = <0x740000 0x40000>;
- read-only;
- };
-
- partition@780000 {
- label = "kernel";
- reg = <0x780000 0x5800000>;
- };
-
- partition@c80000 {
- label = "rootfs";
- reg = <0xc80000 0x5300000>;
- };
-
- partition@5f80000 {
- label = "alt_kernel";
- reg = <0x5f80000 0x5800000>;
- };
-
- partition@6480000 {
- label = "alt_rootfs";
- reg = <0x6480000 0x5300000>;
- };
-
- partition@b780000 {
- label = "sysdiag";
- reg = <0xb780000 0x100000>;
- read-only;
- };
-
- partition@b880000 {
- label = "syscfg";
- reg = <0xb880000 0x4680000>;
- read-only;
- };
- };
- };
-};
-
-&pcie0 {
- status = "okay";
-
- perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
- wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi2: wifi@1,0 {
- compatible = "qcom,ath10k";
- reg = <0x00010000 0 0 0 0>;
- };
- };
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&tlmm {
- serial_0_pins: serial0-pinmux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
-
- nand_pins: nand_pins {
- pullups {
- pins = "gpio53", "gpio58", "gpio59";
- function = "qpic";
- bias-pull-up;
- };
-
- // gpio61 controls led_usb
-
- pulldowns {
- pins = "gpio55", "gpio56", "gpio57",
- "gpio60", "gpio62", "gpio63",
- "gpio64", "gpio65", "gpio66",
- "gpio67", "gpio69";
- function = "qpic";
- bias-pull-down;
- };
- };
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport1 {
- status = "okay";
-};
-
-&swport2 {
- status = "okay";
-};
-
-&swport3 {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
-};
-
-&swport5 {
- status = "okay";
-};
+++ /dev/null
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
- * Copyright (c) 2017, Christian Mehlis <christian@m3hlis.de>
- * Copyright (c) 2017-2018, Sven Eckelmann <sven.eckelmann@openmesh.com>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "Compex WPJ428";
- compatible = "compex,wpj428";
-
- chosen {
- /*
- * There's a chance that SPI reads fail even though the data itself is alright.
- * The read result is cached and squashfs can't recover.
- * Just panic when that happens and hope that next time it doesn't.
- */
- bootargs-append = " rootflags=errors=panic";
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- reset-gpios = <&tlmm 59 GPIO_ACTIVE_LOW>;
- reset-delay-us = <2000>;
- };
-
- tcsr@194b000 {
- /* select hostmode */
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2: usb2@60f8800 {
- status = "okay";
- };
-
- usb3: usb3@8af8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- aliases {
- led-boot = &status;
- led-failsafe = &status;
- led-upgrade = &status;
- };
-
- leds {
- compatible = "gpio-leds";
-
- status: rss4 {
- label = "green:rss4";
- gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
- };
-
- rss3 {
- label = "green:rss3";
- gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
- };
- };
-
- beeper: beeper {
- compatible = "gpio-beeper";
- gpios = <&tlmm 58 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&tlmm {
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio53";
- function = "mdio";
- bias-pull-up;
- };
-
- mux_2 {
- pins = "gpio52";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pin {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
- pin_cs {
- function = "gpio";
- pins = "gpio54";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
- m25p80@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition0@0 {
- label = "0:SBL1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
- partition1@40000 {
- label = "0:MIBIB";
- reg = <0x00040000 0x00020000>;
- read-only;
- };
- partition2@60000 {
- label = "0:QSEE";
- reg = <0x00060000 0x00060000>;
- read-only;
- };
- partition3@c0000 {
- label = "0:CDT";
- reg = <0x000c0000 0x00010000>;
- read-only;
- };
- partition4@d0000 {
- label = "0:DDRPARAMS";
- reg = <0x000d0000 0x00010000>;
- read-only;
- };
- partition5@e0000 {
- label = "0:APPSBLENV"; /* uboot env*/
- reg = <0x000e0000 0x00010000>;
- read-only;
- };
- partition5@f0000 {
- label = "0:APPSBL"; /* uboot */
- reg = <0x000f0000 0x00080000>;
- read-only;
- };
- partition5@170000 {
- label = "0:ART";
- reg = <0x00170000 0x00010000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_art_e010: mac-address@e010 {
- reg = <0xe010 0x6>;
- };
-
- macaddr_art_e018: mac-address@e018 {
- reg = <0xe018 0x6>;
- };
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
- partition6@180000 {
- compatible = "denx,fit";
- label = "firmware";
- reg = <0x00180000 0x01e80000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
- label = "lan1";
-
- nvmem-cells = <&macaddr_art_e018>;
- nvmem-cell-names = "mac-address";
-};
-
-&swport5 {
- status = "okay";
- label = "lan2";
-
- nvmem-cells = <&macaddr_art_e010>;
- nvmem-cell-names = "mac-address";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-
-#include "qcom-ipq4029-aruba-glenmorangie.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- model = "Aruba AP-303";
- compatible = "aruba,ap-303";
-
- aliases {
- led-boot = &led_system_green;
- led-failsafe = &led_system_red;
- led-running = &led_system_green;
- led-upgrade = &led_system_red;
- };
-
- leds {
- compatible = "gpio-leds";
-
- wifi_green {
- label = "green:wifi";
- gpios = <&tlmm 39 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy0tpt";
- };
-
- wifi_amber {
- label = "amber:wifi";
- gpios = <&tlmm 40 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy1tpt";
- };
-
- led_system_red: system_red {
- label = "red:system";
- gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
- };
-
- led_system_green: system_green {
- label = "green:system";
- gpios = <&tlmm 47 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&tlmm {
- /*
- * In addition to the Pins listed below,
- * the following GPIOs have "features":
- * 54 - out - active low to force HW reset
- * 41 - out - active low to reset TPM
- * 43 - out - active low to reset BLE radio
- * 19 - in - active high when DC powered
- */
-
- phy-reset {
- line-name = "PHY-reset";
- gpios = <42 GPIO_ACTIVE_HIGH>;
- gpio-hog;
- output-high;
- };
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- /*
- * There is no partition map for the NOR flash
- * in the stock firmware.
- *
- * All partitions here are based on offsets
- * found in the U-Boot GPL code and information
- * from smem.
- */
-
- partition@0 {
- label = "sbl1";
- reg = <0x0 0x40000>;
- read-only;
- };
-
- partition@40000 {
- label = "mibib";
- reg = <0x40000 0x20000>;
- read-only;
- };
-
- partition@60000 {
- label = "qsee";
- reg = <0x60000 0x60000>;
- read-only;
- };
-
- partition@c0000 {
- label = "cdt";
- reg = <0xc0000 0x10000>;
- read-only;
- };
-
- partition@d0000 {
- label = "ddrparams";
- reg = <0xd0000 0x10000>;
- read-only;
- };
-
- partition@e0000 {
- label = "ART";
- reg = <0xe0000 0x10000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- partition@f0000 {
- label = "appsbl";
- reg = <0xf0000 0xf0000>;
- read-only;
- };
-
- partition@1e0000 {
- label = "mfginfo";
- reg = <0x1e0000 0x10000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_mfginfo_1d: macaddr@1d {
- compatible = "mac-base";
- reg = <0x1d 0x6>;
- #nvmem-cell-cells = <1>;
- };
- };
- };
-
- partition@1f0000 {
- label = "apcd";
- reg = <0x1f0000 0x10000>;
- read-only;
- };
-
- partition@200000 {
- label = "osss";
- reg = <0x200000 0x180000>;
- read-only;
- };
-
- partition@380000 {
- label = "appsblenv";
- reg = <0x380000 0x10000>;
- };
-
- partition@390000 {
- label = "pds";
- reg = <0x390000 0x10000>;
- read-only;
- };
-
- partition@3a0000 {
- label = "fcache";
- reg = <0x3a0000 0x10000>;
- read-only;
- };
-
- partition@3b0000 {
- /* Called osss1 in smem */
- label = "u-boot-env-bak";
- reg = <0x3b0000 0x10000>;
- read-only;
- };
-
- partition@3f0000 {
- label = "u-boot-env";
- reg = <0x3f0000 0x10000>;
- read-only;
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "Aruba AP-303H";
- compatible = "aruba,ap-303h";
-
- aliases {
- led-boot = &led_system_green;
- led-failsafe = &led_system_red;
- led-running = &led_system_green;
- led-upgrade = &led_system_amber;
- };
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x10000000>;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
-
- reset-gpios = <&tlmm 19 GPIO_ACTIVE_LOW>;
- reset-delay-us = <2000>;
- };
-
- counter@4a1000 {
- compatible = "qcom,qca-gcnt";
- reg = <0x4a1000 0x4>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2@60f8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
-
- i2c_0: i2c@78b7000 {
- pinctrl-0 = <&i2c_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- tpm@29 {
- /* No Driver */
- compatible = "atmel,at97sc3203";
- reg = <0x29>;
- read-only;
- };
-
- power-monitor@40 {
- /* No driver */
- compatible = "isl,isl28022";
- reg = <0x40>;
- };
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- wifi_green {
- label = "green:wifi";
- gpios = <&tlmm 27 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy0tpt";
- };
-
- wifi_amber {
- label = "amber:wifi";
- gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy1tpt";
- };
-
- pse {
- label = "green:pse";
- gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
- };
-
- led_system_red: system_red {
- label = "red:system";
- gpios = <&tlmm 25 GPIO_ACTIVE_HIGH>;
- };
-
- led_system_green: system_green {
- label = "green:system";
- gpios = <&tlmm 24 GPIO_ACTIVE_HIGH>;
- };
-
- led_system_amber: system_amber {
- label = "amber:system";
- gpios = <&tlmm 26 GPIO_ACTIVE_HIGH>;
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "Reset button";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&blsp1_uart2 {
- /* Texas Instruments CC2540T BLE radio */
- pinctrl-0 = <&serial_1_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&tlmm {
- /*
- * In addition to the Pins listed below,
- * the following GPIOs have "features":
- * 39 - out - active low to force HW reset
- * 32 - out - active low to reset TPM
- * 43 - out - active low to reset BLE radio
- * 41 - out - pulse to set warm reset status
- * 34 - out - active low to enable PSE port
- * 22 - in - active low when 802.3at powered
- * 29 - in - active high when DC powered
- * 40 - in - active low when reset due to cold HW reset
- * 30 - in - active low when USB overcurrent detected
- * 35 - in - interrupt line for power monitor chip
- * 31 - in - active low when PSE port active
- */
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pin {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
- pin_cs {
- function = "gpio";
- pins = "gpio12", "gpio59";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-
- i2c_0_pins: i2c_0_pinmux {
- mux {
- pins = "gpio20", "gpio21";
- function = "blsp_i2c0";
- drive-strength = <4>;
- bias-disable;
- };
- };
-
- serial_0_pins: serial_0_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- serial_1_pins: serial_1_pinmux {
- mux {
- pins = "gpio8", "gpio9";
- function = "blsp_uart1";
- bias-disable;
- };
- };
-
- usb-power {
- line-name = "USB-power";
- gpios = <23 GPIO_ACTIVE_HIGH>;
- gpio-hog;
- output-high;
- };
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>, <&tlmm 59 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- /*
- * There is no partition map for the NOR flash
- * in the stock firmware.
- *
- * All partitions here are based on offsets
- * found in the U-Boot GPL code and information
- * from smem.
- */
-
- partition@0 {
- label = "sbl1";
- reg = <0x0 0x40000>;
- read-only;
- };
-
- partition@40000 {
- label = "mibib";
- reg = <0x40000 0x20000>;
- read-only;
- };
-
- partition@60000 {
- label = "qsee";
- reg = <0x60000 0x60000>;
- read-only;
- };
-
- partition@c0000 {
- label = "cdt";
- reg = <0xc0000 0x10000>;
- read-only;
- };
-
- partition@d0000 {
- label = "ddrparams";
- reg = <0xd0000 0x10000>;
- read-only;
- };
-
- partition@e0000 {
- label = "appsblenv";
- reg = <0xe0000 0x10000>;
- read-only;
- };
-
- partition@f0000 {
- label = "appsbl";
- reg = <0xf0000 0x100000>;
- read-only;
- };
-
- partition@1e0000 {
- label = "ART";
- reg = <0x1f0000 0x10000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- partition@1f0000 {
- label = "osss";
- reg = <0x200000 0x170000>;
- read-only;
- };
-
- partition@200000 {
- label = "pds";
- reg = <0x370000 0x10000>;
- read-only;
- };
-
- partition@380000 {
- label = "apcd";
- reg = <0x380000 0x10000>;
- read-only;
- };
-
- partition@390000 {
- label = "mfginfo";
- reg = <0x390000 0x10000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_mfginfo_1d: macaddr@1d {
- reg = <0x1d 0x6>;
- };
-
- macaddr_mfginfo_45: macaddr@45 {
- compatible = "mac-base";
- reg = <0x45 0x6>;
- #nvmem-cell-cells = <1>;
- };
- };
- };
-
- partition@3a0000 {
- label = "fcache";
- reg = <0x3a0000 0x10000>;
- read-only;
- };
-
- partition@3b0000 {
- /* Called osss1 in smem */
- label = "u-boot-env-bak";
- reg = <0x3b0000 0x10000>;
- read-only;
- };
-
- partition@3f0000 {
- label = "u-boot-env";
- reg = <0x3c0000 0x40000>;
- read-only;
- };
- };
- };
-
- flash@1 {
- status = "okay";
-
- compatible = "spi-nand";
- reg = <1>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- /* 'aos0' in Aruba firmware */
- label = "aos0";
- reg = <0x0 0x2000000>;
- read-only;
- };
-
- partition@2000000 {
- /* 'aos1' in Aruba firmware */
- label = "ubi";
- reg = <0x2000000 0x2000000>;
- };
-
- partition@4000000 {
- label = "aruba-ubifs";
- reg = <0x4000000 0x4000000>;
- read-only;
- };
- };
- };
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport2 {
- status = "okay";
-
- label = "lan1";
-};
-
-&swport3 {
- status = "okay";
-
- label = "lan2";
-};
-
-&swport4 {
- status = "okay";
-
- label = "lan3";
-};
-
-&swport5 {
- status = "okay";
-
- label = "wan";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_1000>, <&macaddr_mfginfo_45 0>;
- qcom,ath10k-calibration-variant = "Aruba-AP-303";
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_5000>, <&macaddr_mfginfo_45 1>;
- qcom,ath10k-calibration-variant = "Aruba-AP-303";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-
-#include "qcom-ipq4029-aruba-glenmorangie.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- model = "Aruba AP-365";
- compatible = "aruba,ap-365";
-
- aliases {
- led-boot = &led_system_green;
- led-failsafe = &led_system_red;
- led-running = &led_system_green;
- led-upgrade = &led_system_red;
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_system_red: system_red {
- label = "red:system";
- gpios = <&tlmm 46 GPIO_ACTIVE_LOW>;
- };
-
- led_system_green: system_green {
- label = "green:system";
- gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
- };
-
- system_amber {
- label = "amber:system";
- gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
- };
- };
-
- watchdog {
- compatible = "linux,wdt-gpio";
- gpios = <&tlmm 41 GPIO_ACTIVE_LOW>;
- hw_algo = "toggle";
- hw_margin_ms = <1000>;
- always-running;
- };
-};
-
-&tlmm {
- /*
- * In addition to the Pins listed below,
- * the following GPIOs have "features":
- * 39 - out - pulse low to reset watchdog status flipflop
- * 40 - out - active high to enable watchdog
- * 41 - out - watchdog poke
- * 42 - out - active low to reset BLE radio
- * 43 - out - active low to reset TPM
- * 47 - out - pulse low to reset warm reset status
- * 54 - out - active low to force HW reset
- * 18 - in - PHY interrupt line
- * 45 - in - power monitor interrupt
- * 48 - in - active low when cold reset
- * 52 - in - active high when watchdog reset
- */
-
- phy-reset {
- line-name = "PHY-reset";
- gpios = <42 GPIO_ACTIVE_HIGH>;
- gpio-hog;
- output-high;
- };
-};
-
-&i2c_0 {
- power-monitor@40 {
- /* No driver */
- compatible = "isl,isl28022";
- reg = <0x40>;
- };
-
- temperature-sensor@48 {
- compatible = "adi,ad7416";
- reg = <0x48>;
- };
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- /*
- * There is no partition map for the NOR flash
- * in the stock firmware.
- *
- * All partitions here are based on offsets
- * found in the U-Boot GPL code and information
- * from smem.
- */
-
- partition@0 {
- label = "sbl1";
- reg = <0x0 0x40000>;
- read-only;
- };
-
- partition@40000 {
- label = "mibib";
- reg = <0x40000 0x20000>;
- read-only;
- };
-
- partition@60000 {
- label = "qsee";
- reg = <0x60000 0x60000>;
- read-only;
- };
-
- partition@c0000 {
- label = "cdt";
- reg = <0xc0000 0x10000>;
- read-only;
- };
-
- partition@d0000 {
- label = "ddrparams";
- reg = <0xd0000 0x10000>;
- read-only;
- };
-
- partition@e0000 {
- label = "u-boot-env";
- reg = <0xe0000 0x10000>;
- };
-
- partition@f0000 {
- label = "appsbl";
- reg = <0xf0000 0x100000>;
- read-only;
- };
-
- partition@1f0000 {
- label = "ART";
- reg = <0x1f0000 0x10000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- partition@200000 {
- label = "osss";
- reg = <0x200000 0x170000>;
- read-only;
- };
-
- partition@370000 {
- label = "pds";
- reg = <0x370000 0x10000>;
- read-only;
- };
-
- partition@380000 {
- label = "apcd";
- reg = <0x380000 0x10000>;
- read-only;
- };
-
- partition@390000 {
- label = "mfginfo";
- reg = <0x390000 0x10000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_mfginfo_1d: macaddr@1d {
- compatible = "mac-base";
- reg = <0x1d 0x6>;
- #nvmem-cell-cells = <1>;
- };
- };
- };
-
- partition@3a0000 {
- label = "fcache";
- reg = <0x3a0000 0x10000>;
- read-only;
- };
-
- partition@3b0000 {
- label = "osss1";
- reg = <0x3b0000 0x50000>;
- read-only;
- };
- };
- };
-};
-
-&wifi0 {
- qcom,ath10k-calibration-variant = "Aruba-AP-365";
-};
-
-&wifi1 {
- qcom,ath10k-calibration-variant = "Aruba-AP-365";
-};
-
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- memory {
- device_type = "memory";
- reg = <0x80000000 0x10000000>;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
-
- ethphy: ethernet-phy@5 {
- reg = <0x5>;
- };
- };
-
- counter@4a1000 {
- compatible = "qcom,qca-gcnt";
- reg = <0x4a1000 0x4>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII_RGMII5>;
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
-
- i2c_0: i2c@78b7000 {
- pinctrl-0 = <&i2c_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- tpm@29 {
- /* No Driver */
- compatible = "atmel,at97sc3203";
- reg = <0x29>;
- read-only;
- };
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "Reset button";
- gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_uart1 {
- /* Texas Instruments CC2540T BLE radio */
- pinctrl-0 = <&serial_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&blsp1_uart2 {
- pinctrl-0 = <&serial_1_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&tlmm {
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- nand_pins: nand_pins {
- pullups {
- pins = "gpio53", "gpio58", "gpio59";
- function = "qpic";
- bias-pull-up;
- };
-
- pulldowns {
- pins = "gpio54", "gpio55", "gpio56",
- "gpio57", "gpio60", "gpio61",
- "gpio62", "gpio63", "gpio64",
- "gpio65", "gpio66", "gpio67",
- "gpio68", "gpio69";
- function = "qpic";
- bias-pull-down;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pin {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
- pin_cs {
- function = "gpio";
- pins = "gpio12";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-
- i2c_0_pins: i2c_0_pinmux {
- mux {
- pins = "gpio10", "gpio11";
- function = "blsp_i2c0";
- drive-strength = <4>;
- bias-disable;
- };
- };
-
- serial_0_pins: serial_0_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- serial_1_pins: serial_1_pinmux {
- mux {
- pins = "gpio8", "gpio9";
- function = "blsp_uart1";
- bias-disable;
- };
- };
-};
-
-&nand {
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- nand@0 {
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- /* 'aos0' in Aruba firmware */
- label = "aos0";
- reg = <0x0 0x2000000>;
- read-only;
- };
-
- partition@2000000 {
- /* 'aos1' in Aruba firmware */
- label = "ubi";
- reg = <0x2000000 0x2000000>;
- };
-
- partition@4000000 {
- label = "aruba-ubifs";
- reg = <0x4000000 0x4000000>;
- read-only;
- };
- };
- };
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-
- /delete-property/ psgmii-ethphy;
-};
-
-&swport5 {
- status = "okay";
-
- label = "lan";
- phy-handle = <ðphy>;
- phy-mode = "rgmii-id";
-};
-
-ðphy0 {
- status = "disabled";
-};
-
-ðphy1 {
- status = "disabled";
-};
-
-ðphy2 {
- status = "disabled";
-};
-
-ðphy3 {
- status = "disabled";
-};
-
-ðphy4 {
- status = "disabled";
-};
-
-&psgmiiphy {
- status = "disabled";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_1000>, <&macaddr_mfginfo_1d 0>;
- qcom,ath10k-calibration-variant = "Aruba-AP-303";
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_5000>, <&macaddr_mfginfo_1d 1>;
- qcom,ath10k-calibration-variant = "Aruba-AP-303";
-};
+++ /dev/null
-/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- *
- */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "GL.iNet GL-B1300";
- compatible = "glinet,gl-b1300";
-
- aliases {
- led-boot = &power;
- led-failsafe = &power;
- led-running = &power;
- led-upgrade = &power;
- label-mac-device = &swport4;
- };
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x10000000>;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- /* select hostmode */
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2@60f8800 {
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- wps {
- label = "wps";
- gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- };
-
- reset {
- label = "reset";
- gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- power: power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- };
-
- mesh {
- label = "green:mesh";
- gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
- };
-
- wlan {
- function = LED_FUNCTION_WLAN;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
-
- mx25l25635f@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- SBL1@0 {
- label = "SBL1";
- reg = <0x0 0x40000>;
- read-only;
- };
-
- MIBIB@40000 {
- label = "MIBIB";
- reg = <0x40000 0x20000>;
- read-only;
- };
-
- QSEE@60000 {
- label = "QSEE";
- reg = <0x60000 0x60000>;
- read-only;
- };
-
- CDT@c0000 {
- label = "CDT";
- reg = <0xc0000 0x10000>;
- read-only;
- };
-
- DDRPARAMS@d0000 {
- label = "DDRPARAMS";
- reg = <0xd0000 0x10000>;
- read-only;
- };
-
- APPSBLENV@e0000 {
- label = "APPSBLENV";
- reg = <0xe0000 0x10000>;
- read-only;
- };
-
- APPSBL@f0000 {
- label = "APPSBL";
- reg = <0xf0000 0x80000>;
- read-only;
- };
-
- ART@170000 {
- label = "ART";
- reg = <0x170000 0x10000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_gmac0: macaddr@0 {
- compatible = "mac-base";
- reg = <0x0 0x6>;
- #nvmem-cell-cells = <1>;
- };
-
- macaddr_gmac1: macaddr@6 {
- reg = <0x6 0x6>;
- };
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- firmware@180000 {
- compatible = "denx,fit";
- label = "firmware";
- reg = <0x180000 0x1e80000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio60", "gpio61";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio55", "gpio56", "gpio57";
- };
- pinmux_cs {
- function = "gpio";
- pins = "gpio54";
- };
- pinconf {
- pins = "gpio55", "gpio56", "gpio57";
- drive-strength = <12>;
- bias-disable;
- };
- pinconf_cs {
- pins = "gpio54";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport3 {
- status = "okay";
-
- label = "lan2";
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_gmac0 2>;
-};
-
-&swport4 {
- status = "okay";
-
- label = "lan1";
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_gmac0 0>;
-};
-
-&swport5 {
- status = "okay";
-
- nvmem-cell-names = "mac-address";
- nvmem-cells = <&macaddr_gmac1>;
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
- qcom,ath10k-calibration-variant = "GL-B1300";
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
- qcom,ath10k-calibration-variant = "GL-B1300";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "GL.iNet GL-S1300";
- compatible = "glinet,gl-s1300";
-
- aliases {
- led-boot = &led_power;
- led-failsafe = &led_power;
- led-running = &led_power;
- led-upgrade = &led_power;
- };
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x10000000>;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- /* select hostmode */
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- status = "okay";
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- usb2@60f8800 {
- status = "okay";
- };
-
- usb3@8af8800 {
- status = "okay";
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- wps {
- label = "wps";
- gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- };
-
- reset {
- label = "reset";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_power: power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 57 GPIO_ACTIVE_HIGH>;
- default-state = "on";
- };
-
- mesh {
- label = "green:mesh";
- gpios = <&tlmm 59 GPIO_ACTIVE_HIGH>;
- };
-
- wlan {
- function = LED_FUNCTION_WLAN;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&tlmm 60 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy0tpt";
- };
- };
-};
-
-&vqmmc {
- status = "okay";
-};
-
-&sdhci {
- status = "okay";
- pinctrl-0 = <&sd_pins>;
- pinctrl-names = "default";
- cd-gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
- vqmmc-supply = <&vqmmc>;
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- SBL1@0 {
- label = "SBL1";
- reg = <0x0 0x40000>;
- read-only;
- };
-
- MIBIB@40000 {
- label = "MIBIB";
- reg = <0x40000 0x20000>;
- read-only;
- };
-
- QSEE@60000 {
- label = "QSEE";
- reg = <0x60000 0x60000>;
- read-only;
- };
-
- CDT@c0000 {
- label = "CDT";
- reg = <0xc0000 0x10000>;
- read-only;
- };
-
- DDRPARAMS@d0000 {
- label = "DDRPARAMS";
- reg = <0xd0000 0x10000>;
- read-only;
- };
-
- APPSBLENV@e0000 {
- label = "APPSBLENV";
- reg = <0xe0000 0x10000>;
- read-only;
- };
-
- APPSBL@f0000 {
- label = "APPSBL";
- reg = <0xf0000 0x80000>;
- read-only;
- };
-
- ART@170000 {
- label = "ART";
- reg = <0x170000 0x10000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- firmware@180000 {
- compatible = "denx,fit";
- label = "firmware";
- reg = <0x180000 0xe80000>;
- };
- };
- };
-};
-
-&blsp1_spi2 {
- pinctrl-0 = <&spi_1_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- spidev1: spi@0 {
- compatible = "silabs,si3210";
- reg = <0>;
- spi-max-frequency = <24000000>;
- };
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&blsp1_uart2 {
- pinctrl-0 = <&serial_1_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&tlmm {
- serial_pins: serial_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- serial_1_pins: serial1_pinmux {
- mux {
- pins = "gpio8", "gpio9",
- "gpio10", "gpio11";
- function = "blsp_uart1";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- };
- pinmux_cs {
- function = "gpio";
- pins = "gpio12";
- };
- pinconf {
- pins = "gpio13", "gpio14", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
- pinconf_cs {
- pins = "gpio12";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-
- spi_1_pins: spi_1_pinmux {
- mux {
- pins = "gpio44", "gpio46", "gpio47";
- function = "blsp_spi1";
- bias-disable;
- };
- host_int {
- pins = "gpio42";
- function = "gpio";
- input;
- };
- cs {
- pins = "gpio45";
- function = "gpio";
- bias-pull-up;
- };
- wake {
- pins = "gpio40";
- function = "gpio";
- output-high;
- };
- reset {
- pins = "gpio49";
- function = "gpio";
- output-high;
- };
- };
-
- sd_pins: sd_pins {
- pinmux {
- function = "sdio";
- pins = "gpio23", "gpio24", "gpio25", "gpio26",
- "gpio28", "gpio29", "gpio30", "gpio31";
- drive-strength = <10>;
- };
-
- pinmux_sd_clk {
- function = "sdio";
- pins = "gpio27";
- drive-strength = <16>;
- };
-
- pinmux_sd7 {
- function = "sdio";
- pins = "gpio32";
- drive-strength = <10>;
- bias-disable;
- };
- };
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_1000>;
- qcom,ath10k-calibration-variant = "GL-S1300";
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration";
- nvmem-cells = <&precal_art_5000>;
- qcom,ath10k-calibration-variant = "GL-S1300";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Device Tree Source for Meraki "Insect" series
- *
- * Copyright (C) 2017 Chris Blake <chrisrblake93@gmail.com>
- * Copyright (C) 2017 Christian Lamparter <chunkeey@googlemail.com>
- *
- * Based on Cisco Meraki DTS from GPL release r25-linux-3.14-20170427
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without
- * any warranty of any kind, whether express or implied.
- */
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- aliases {
- led-boot = &status_green;
- led-failsafe = &status_red;
- led-running = &status_green;
- led-upgrade = &power_orange;
- };
-
- /* Do we really need this defined? */
- memory {
- device_type = "memory";
- reg = <0x80000000 0x10000000>;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- };
-
- /* It is a 56-bit counter that supplies the count to the ARM arch
- timers and without upstream driver */
- counter@4a1000 {
- compatible = "qcom,qca-gcnt";
- reg = <0x4a1000 0x4>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII_RGMII5>;
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- serial@78b0000 {
- pinctrl-0 = <&serial_1_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- bluetooth {
- compatible = "ti,cc2650";
- enable-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
- };
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- power_orange: power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_ORANGE>;
- gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
- panic-indicator;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&blsp1_i2c3 {
- pinctrl-0 = <&i2c_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- eeprom@50 {
- compatible = "atmel,24c64";
- pagesize = <32>;
- reg = <0x50>;
- read-only; /* This holds our MAC & Meraki board-data */
- #address-cells = <1>;
- #size-cells = <1>;
-
- mac_address: mac-address@66 {
- compatible = "mac-base";
- reg = <0x66 0x6>;
- #nvmem-cell-cells = <1>;
- };
- };
-};
-
-&blsp1_i2c4 {
- pinctrl-0 = <&i2c_1_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- tricolor: led-controller@30 {
- compatible = "ti,lp5562";
- reg = <0x30>;
- clock-mode = /bits/8 <2>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- /* RGB led */
- status_red: chan@0 {
- chan-name = "red:status";
- led-cur = /bits/ 8 <0x20>;
- max-cur = /bits/ 8 <0x60>;
- reg = <0>;
- color = <LED_COLOR_ID_RED>;
- };
-
- status_green: chan@1 {
- chan-name = "green:status";
- led-cur = /bits/ 8 <0x20>;
- max-cur = /bits/ 8 <0x60>;
- reg = <1>;
- color = <LED_COLOR_ID_GREEN>;
- };
-
- chan@2 {
- chan-name = "blue:status";
- led-cur = /bits/ 8 <0x20>;
- max-cur = /bits/ 8 <0x60>;
- reg = <2>;
- color = <LED_COLOR_ID_BLUE>;
- };
-
- chan@3 {
- chan-name = "white:status";
- led-cur = /bits/ 8 <0x20>;
- max-cur = /bits/ 8 <0x60>;
- reg = <3>;
- color = <LED_COLOR_ID_WHITE>;
- };
- };
-};
-
-&nand {
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- nand@0 {
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "sbl1";
- reg = <0x00000000 0x00100000>;
- read-only;
- };
- partition@100000 {
- label = "mibib";
- reg = <0x00100000 0x00100000>;
- read-only;
- };
- partition@200000 {
- label = "bootconfig";
- reg = <0x00200000 0x00100000>;
- read-only;
- };
- partition@300000 {
- label = "qsee";
- reg = <0x00300000 0x00100000>;
- read-only;
- };
- partition@400000 {
- label = "qsee_alt";
- reg = <0x00400000 0x00100000>;
- read-only;
- };
- partition@500000 {
- label = "cdt";
- reg = <0x00500000 0x00080000>;
- read-only;
- };
- partition@580000 {
- label = "cdt_alt";
- reg = <0x00580000 0x00080000>;
- read-only;
- };
- partition@600000 {
- label = "ddrparams";
- reg = <0x00600000 0x00080000>;
- read-only;
- };
- partition@700000 {
- label = "u-boot";
- reg = <0x00700000 0x00200000>;
- read-only;
- };
- partition@900000 {
- label = "u-boot-backup";
- reg = <0x00900000 0x00200000>;
- read-only;
- };
- partition@b00000 {
- label = "ART";
- reg = <0x00b00000 0x00080000>;
- read-only;
- };
- partition@c00000 {
- label = "ubi";
- reg = <0x00c00000 0x07000000>;
- /*
- * Do not try to allocate the remaining
- * 4 MiB to this ubi partition. It will
- * confuse the u-boot and it might not
- * find the kernel partition anymore.
- */
- };
- };
- };
-};
-
-&pcie0 {
- status = "okay";
- perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
- wake-gpio = <&tlmm 50 GPIO_ACTIVE_LOW>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi2: wifi@1,0 {
- compatible = "qcom,ath10k";
- status = "okay";
- reg = <0x00010000 0 0 0 0>;
- nvmem-cells = <&mac_address 1>;
- nvmem-cell-names = "mac-address";
- };
- };
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&tlmm {
- /*
- * GPIO43 should be 0/1 whenever the unit is
- * powered through PoE or AC-Adapter.
- * That said, playing with this seems to
- * reset the AP.
- */
-
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- serial_0_pins: serial_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- serial_1_pins: serial1_pinmux {
- mux {
- /* We use the i2c-0 pins for serial_1 */
- pins = "gpio8", "gpio9";
- function = "blsp_uart1";
- bias-disable;
- };
- };
-
- i2c_0_pins: i2c_0_pinmux {
- pinmux {
- function = "blsp_i2c0";
- pins = "gpio20", "gpio21";
- };
- pinconf {
- pins = "gpio20", "gpio21";
- drive-strength = <16>;
- bias-disable;
- };
- };
-
- i2c_1_pins: i2c_1_pinmux {
- pinmux {
- function = "blsp_i2c1";
- pins = "gpio34", "gpio35";
- };
- pinconf {
- pins = "gpio34", "gpio35";
- drive-strength = <16>;
- bias-disable;
- };
- };
-
- nand_pins: nand_pins {
- /*
- * There are 18 pins. 15 pins are common between LCD and NAND.
- * The QPIC controller arbitrates between LCD and NAND. Of the
- * remaining 4, 2 are for NAND and 2 are for LCD exclusively.
- *
- * The meraki source hints that the bluetooth module claims
- * pin 52 as well. But sadly, there's no data whenever this
- * is a NAND or LCD exclusive pin or not.
- */
-
- pullups {
- pins = "gpio52", "gpio53", "gpio58",
- "gpio59";
- function = "qpic";
- bias-pull-up;
- };
-
- pulldowns {
- pins = "gpio54", "gpio55", "gpio56",
- "gpio57", "gpio60", "gpio61",
- "gpio62", "gpio63", "gpio64",
- "gpio65", "gpio66", "gpio67",
- "gpio68", "gpio69";
- function = "qpic";
- bias-pull-down;
- };
- };
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "Meraki-MR33";
- nvmem-cells = <&mac_address 2>;
- nvmem-cell-names = "mac-address";
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "Meraki-MR33";
- nvmem-cells = <&mac_address 3>;
- nvmem-cell-names = "mac-address";
-};
-
-&gmac {
- status = "okay";
- nvmem-cells = <&mac_address 0>;
- nvmem-cell-names = "mac-address";
-};
-
-&switch {
- status = "okay";
-
- /delete-property/ psgmii-ethphy;
-};
-
-&swport5 {
- status = "okay";
-
- label = "lan";
- phy-handle = <ðphy1>;
- phy-mode = "rgmii-rxid";
-};
-
-ðphy0 {
- status = "disabled";
-};
-
-ðphy2 {
- status = "disabled";
-};
-
-ðphy3 {
- status = "disabled";
-};
-
-ðphy4 {
- status = "disabled";
-};
-
-&psgmiiphy {
- status = "disabled";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only
-// Device Tree Source for Meraki MR33 (Stinkbug)
-
-#include "qcom-ipq4029-insect-common.dtsi"
-
-/ {
- model = "Meraki MR33 Access Point";
- compatible = "meraki,mr33";
-};
-
-&tricolor {
- enable-gpio = <&tlmm 48 GPIO_ACTIVE_HIGH>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only
-// Device Tree Source for Meraki MR74 (Ladybug)
-
-#include "qcom-ipq4029-insect-common.dtsi"
-
-/ {
- model = "Meraki MR74 Access Point";
- compatible = "meraki,mr74";
-};
-
-&tricolor {
- enable-gpio = <&tlmm 14 GPIO_ACTIVE_LOW>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "Extreme Networks WS-AP3915i";
- compatible = "extreme-networks,ws-ap3915i";
-
- aliases {
- led-boot = &led_system_green;
- led-failsafe = &led_system_amber;
- led-running = &led_system_green;
- led-upgrade = &led_system_amber;
- };
-
- soc {
- rng@22000 {
- status = "okay";
- };
-
- mdio@90000 {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- crypto@8e3a000 {
- status = "okay";
- };
-
- watchdog@b017000 {
- status = "okay";
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_system_green: system_green {
- label = "green:system";
- gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
- };
-
- led_system_amber: system_amber {
- label = "amber:system";
- gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
- };
-
- led_wlan24_green: wlan24_green {
- label = "green:wlan24";
- gpios = <&tlmm 23 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy0tpt";
- };
-
- led_wlan24_amber: wlan24_amber {
- label = "amber:wlan24";
- gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
- };
-
- led_wlan5_green: wlan5_green {
- label = "green:wlan5";
- gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy1tpt";
- };
-
- led_wlan5_amber: wlan5_amber {
- label = "amber:wlan5";
- gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
- };
-
- iot {
- label = "blue:iot";
- gpios = <&tlmm 10 GPIO_ACTIVE_LOW>;
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART >;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport5 {
- status = "okay";
-
- label = "lan";
-};
-
-&tlmm {
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pin {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
- pin_cs {
- function = "gpio";
- pins = "gpio12";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-
- serial_pins: serial_0_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "Extreme-Networks-WS-AP3915i";
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "Extreme-Networks-WS-AP3915i";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- /* Layout for 0x0 - 0xe0000 unknown */
-
- partition@e0000 {
- label = "CFG1";
- reg = <0xe0000 0x10000>;
- read-only;
- };
-
- partition@f0000 {
- label = "BootBAK";
- reg = <0xf0000 0x70000>;
- read-only;
- };
-
- partition@160000 {
- label = "WINGCFG1";
- reg = <0x160000 0x10000>;
- read-only;
- };
-
- partition@170000 {
- label = "ART";
- reg = <0x170000 0x10000>;
- read-only;
- };
-
- partition@180000 {
- label = "BootPRI";
- reg = <0x180000 0x70000>;
- read-only;
- };
-
- partition@1f0000 {
- label = "WINGCFG2";
- reg = <0x1f0000 0x10000>;
- read-only;
- };
-
- partition@200000 {
- label = "FS";
- reg = <0x200000 0x80000>;
- read-only;
- };
-
- partition@280000 {
- label = "firmware";
- reg = <0x280000 0x1d60000>;
- };
-
- partition@1fe0000 {
- label = "CFG2";
- reg = <0x1fe0000 0x10000>;
- read-only;
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "Extreme Networks WS-AP391x";
- compatible = "extreme-networks,ws-ap391x";
-
- aliases {
- led-boot = &led_system_green;
- led-failsafe = &led_system_red;
- led-running = &led_system_green;
- led-upgrade = &led_system_red;
- };
-
- soc {
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
-
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_system_green: system_green {
- label = "system:green";
- gpios = <&tlmm 49 GPIO_ACTIVE_LOW>;
- };
-
- /*
- * system:amber ==> AP3917
- * system:red ==> AP3916
- * */
- led_system_red: system_red {
- label = "system:red_or_system:amber";
- gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
- };
-
- led_wlan24_green: wlan24_green {
- label = "wlan24:green";
- gpios = <&tlmm 23 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy0tpt";
- };
-
- /*
- * wlan24:amber ==> AP3915/AP3917
- * pse:green ==> AP3912
- * */
- led_wlan24_amber: wlan24_amber {
- label = "wlan24:amber_or_pse:green";
- gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
- };
-
- led_wlan5_green: wlan5_green {
- label = "wlan5:green";
- gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy1tpt";
- };
-
- /* iot:blue ==> AP3917 */
- led_iot_green: iot_green {
- label = "iot:green_or_iot:blue";
- gpios = <&tlmm 10 GPIO_ACTIVE_LOW>;
- };
-
- /* eth:green ==> only AP3912/AP3916 */
- led_eth_green: eth_green {
- label = "eth:green";
- gpios = <&tlmm 41 GPIO_ACTIVE_LOW>;
- };
-
- /*
- * eth:amber ==> only AP3912/AP3916
- * usb_enable ==> only AP3915e
- */
- led_eth_amber: eth_amber {
- label = "eth:amber_or_usb_enable";
- gpios = <&tlmm 52 GPIO_ACTIVE_LOW>;
- };
-
- /*
- * wlan5:amber ==> AP3915/AP3917
- * cam:green ==> only AP3916
- */
- led_wlan5_amber: wlan5_amber {
- label = "wlan5:amber_or_cam:green";
- gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
- };
-
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART >;
- };
- };
-};
-
-&prng {
- status = "okay";
-};
-
-&mdio {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
-};
-
-&crypto {
- status = "okay";
-};
-
-&watchdog {
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&usb3 {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&usb2 {
- status = "okay";
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_uart1 {
- pinctrl-0 = <&serial_pins>;
- pinctrl-names = "default";
- status = "okay";
-};
-
-&cryptobam {
- status = "okay";
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport1 {
- status = "okay";
- label = "sw-eth1";
-};
-
-&swport2 {
- status = "okay";
- label = "sw-eth2";
-};
-
-&swport3 {
- status = "okay";
- label = "sw-eth3";
-};
-
-/* "GE2" on AP3917/AP3916/WiNG-AP7662 */
-&swport4 {
- status = "okay";
- label = "sw-eth4";
-};
-
-/*
- * "GE1" on AP3917/AP3916/AP3915/AP7662
- * "LAN1" on EXTR-AP3912
- */
-&swport5 {
- status = "okay";
- label = "sw-eth5";
-};
-
-&tlmm {
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pin {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
- pin_cs {
- function = "gpio";
- pins = "gpio12";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-
- serial_pins: serial_0_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-};
-
-&wifi0 {
- status = "okay";
- qcom,ath10k-calibration-variant = "Extreme-Networks-WS-AP3915i";
-};
-
-&wifi1 {
- status = "okay";
- qcom,ath10k-calibration-variant = "Extreme-Networks-WS-AP3915i";
-};
-
-&blsp1_spi1 {
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
- status = "okay";
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <24000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- /* Layout for 0x0 - 0xe0000 unknown */
-
- partition@e0000 {
- label = "CFG1";
- compatible = "u-boot,env-redundant-bool";
- reg = <0xe0000 0x10000>;
- read-only;
- };
-
- partition@f0000 {
- label = "BootBAK";
- reg = <0xf0000 0x70000>;
- read-only;
- };
-
- partition@160000 {
- label = "WINGCFG1";
- reg = <0x160000 0x10000>;
- read-only;
- };
-
- partition@170000 {
- label = "ART";
- reg = <0x170000 0x10000>;
- read-only;
- };
-
- partition@180000 {
- label = "BootPRI";
- reg = <0x180000 0x70000>;
- read-only;
- };
-
- partition@1f0000 {
- label = "WINGCFG2";
- reg = <0x1f0000 0x10000>;
- read-only;
- };
-
- partition@200000 {
- label = "FS";
- reg = <0x200000 0x80000>;
- read-only;
- };
-
- partition@280000 {
- label = "firmware";
- reg = <0x280000 0xeb0000>;
- };
-
- partition@1130000 {
- label = "firmware2";
- reg = <0x1130000 0xeb0000>;
- };
-
- partition@1fe0000 {
- label = "CFG2";
- compatible = "u-boot,env-redundant-bool";
- reg = <0x1fe0000 0x10000>;
- read-only;
- };
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq4019.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "Wallystech DR40X9";
- compatible = "wallys,dr40x9";
-
- chosen {
- bootargs-append = " ubi.mtd=ubi root=/dev/ubiblock0_1";
- };
-
- soc {
- counter@4a1000 {
- compatible = "qcom,qca-gcnt";
- reg = <0x4a1000 0x4>;
- };
-
- tcsr@1949000 {
- compatible = "qcom,tcsr";
- reg = <0x1949000 0x100>;
- qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
- };
-
- tcsr@194b000 {
- status = "okay";
-
- /* select hostmode */
- compatible = "qcom,tcsr";
- reg = <0x194b000 0x100>;
- qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
- };
-
- ess_tcsr@1953000 {
- compatible = "qcom,tcsr";
- reg = <0x1953000 0x1000>;
- qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
- };
-
- tcsr@1957000 {
- compatible = "qcom,tcsr";
- reg = <0x1957000 0x100>;
- qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- reset {
- label = "reset";
- gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- wlan2g {
- label = "dr4029:green:wlan2g";
- gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy0tpt";
- };
-
- wlan5g {
- label = "dr4029:green:wlan5g";
- gpios = <&tlmm 50 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy1tpt";
- };
-
- wlan2g-strength {
- label = "dr4029:green:wlan2g-strength";
- gpios = <&tlmm 36 GPIO_ACTIVE_LOW>;
- };
-
- wlan5g-strength {
- label = "dr4029:green:wlan5g-strength";
- gpios = <&tlmm 39 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&tlmm {
- mdio_pins: mdio_pinmux {
- mux_1 {
- pins = "gpio6";
- function = "mdio";
- bias-pull-up;
- };
- mux_2 {
- pins = "gpio7";
- function = "mdc";
- bias-pull-up;
- };
- };
-
- serial0_pins: serial0_pinmux {
- mux {
- pins = "gpio16", "gpio17";
- function = "blsp_uart0";
- bias-disable;
- };
- };
-
- serial1_pins: serial1_pinmux {
- mux {
- pins = "gpio8", "gpio9";
- function = "blsp_uart1";
- bias-disable;
- };
- };
-
- spi_0_pins: spi_0_pinmux {
- pinmux {
- function = "blsp_spi0";
- pins = "gpio13", "gpio14", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
- pinmux_cs {
- function = "gpio";
- pins = "gpio12";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-
- nand_pins: nand_pins {
- pullups {
- pins = "gpio52", "gpio53", "gpio58", "gpio59";
- function = "qpic";
- bias-pull-up;
- };
-
- pulldowns {
- pins = "gpio54", "gpio55", "gpio56", "gpio57",
- "gpio60", "gpio62", "gpio63", "gpio64",
- "gpio65", "gpio66", "gpio67", "gpio68",
- "gpio69";
- function = "qpic";
- bias-pull-down;
- };
- };
-
- sd_pins: sd_pins {
- pinmux {
- function = "sdio";
- pins = "gpio23", "gpio24", "gpio25", "gpio26",
- "gpio28", "gpio29", "gpio30", "gpio31";
- drive-strength = <10>;
- };
- pinmux_sd_clk {
- function = "sdio";
- pins = "gpio27";
- drive-strength = <16>;
- };
- pinmux_sd7 {
- function = "sdio";
- pins = "gpio32";
- drive-strength = <10>;
- bias-disable;
- };
- };
-};
-
-&blsp_dma {
- status = "okay";
-};
-
-&blsp1_spi1 {
- status = "okay";
-
- pinctrl-0 = <&spi_0_pins>;
- pinctrl-names = "default";
-
- cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- spi-max-frequency = <24000000>;
- reg = <0>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition0@0 {
- label = "0:SBL1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
-
- partition1@40000 {
- label = "0:MIBIB";
- reg = <0x00040000 0x00020000>;
- read-only;
- };
-
- partition2@60000 {
- label = "0:QSEE";
- reg = <0x00060000 0x00060000>;
- read-only;
- };
-
- partition3@c0000 {
- label = "0:CDT";
- reg = <0x000c0000 0x00010000>;
- read-only;
- };
-
- partition4@d0000 {
- label = "0:DDRPARAMS";
- reg = <0x000d0000 0x00010000>;
- read-only;
- };
-
- partition5@e0000 {
- label = "0:APPSBLENV"; /* uboot env */
- reg = <0x000e0000 0x00010000>;
- read-only;
- };
-
- partition6@f0000 {
- label = "0:APPSBL"; /* uboot */
- reg = <0x000f0000 0x00080000>;
- read-only;
- };
-
- partition7@170000 {
- label = "0:ART";
- reg = <0x00170000 0x00010000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_art_0: mac-address@0 {
- reg = <0x0 0x6>;
- };
-
- macaddr_art_6: mac-address@6 {
- reg = <0x6 0x6>;
- };
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- macaddr_art_1006: mac-address@1006 {
- reg = <0x1006 0x6>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
-
- macaddr_art_5006: mac-address@5006 {
- reg = <0x5006 0x6>;
- };
- };
- };
-
- partition8@180000 {
- label = "0:CONFIG";
- reg = <0x00180000 0x00010000>;
- read-only;
- };
- };
- };
-};
-
-&qpic_bam {
- status = "okay";
-};
-
-&nand {
- status = "okay";
-
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
-
- nand@0 {
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "ubi";
- reg = <0x00000000 0x04000000>;
- };
- };
- };
-};
-
-&blsp1_uart1 {
- status = "okay";
- pinctrl-0 = <&serial0_pins>;
- pinctrl-names = "default";
-};
-
-&blsp1_uart2 {
- status = "okay";
- pinctrl-0 = <&serial1_pins>;
- pinctrl-names = "default";
-};
-
-&crypto {
- status = "okay";
-};
-
-&cryptobam {
- num-channels = <4>;
- qcom,num-ees = <2>;
- status = "okay";
-};
-
-&mdio {
- status = "okay";
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
- reset-gpios = <&tlmm 41 GPIO_ACTIVE_LOW>;
- reset-delay-us = <2000>;
-};
-
-&pcie0 {
- status = "okay";
-
- perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
- wake-gpio = <&tlmm 40 GPIO_ACTIVE_LOW>;
-
- /* Unpolulated slot */
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
- };
-};
-
-&vqmmc {
- status = "okay";
-};
-
-&sdhci {
- status = "okay";
- pinctrl-0 = <&sd_pins>;
- pinctrl-names = "default";
- cd-gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
- vqmmc-supply = <&vqmmc>;
-};
-
-&gmac {
- status = "okay";
-};
-
-&switch {
- status = "okay";
-};
-
-&swport4 {
- status = "okay";
- label = "wan";
- nvmem-cells = <&macaddr_art_0>;
- nvmem-cell-names = "mac-address";
-};
-
-&swport5 {
- status = "okay";
- label = "lan";
- nvmem-cells = <&macaddr_art_6>;
- nvmem-cell-names = "mac-address";
-};
-
-&wifi0 {
- status = "okay";
- nvmem-cells = <&precal_art_1000>, <&macaddr_art_1006>;
- nvmem-cell-names = "pre-calibration", "mac-address";
- qcom,ath10k-calibration-variant = "Wallys-DR40X9";
-};
-
-&wifi1 {
- status = "okay";
- nvmem-cell-names = "pre-calibration", "mac-address";
- nvmem-cells = <&precal_art_5000>, <&macaddr_art_5006>;
- qcom,ath10k-calibration-variant = "Wallys-DR40X9";
-};
-
-&usb2 {
- status = "okay";
-};
-
-&usb2_hs_phy {
- status = "okay";
-};
-
-&usb3 {
- status = "okay";
-};
-
-&usb3_ss_phy {
- status = "okay";
-};
-
-&usb3_hs_phy {
- status = "okay";
-};
-
-&prng {
- status = "okay";
-};
-
-&watchdog {
- status = "okay";
-};
-
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
- usb2@60f8800 {
- status = "okay";
- };
-
crypto@8e3a000 {
status = "okay";
};
watchdog@b017000 {
status = "okay";
};
-
- i2c_0: i2c@78b7000 {
- pinctrl-0 = <&i2c_0_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- tpm@29 {
- /* No Driver */
- compatible = "atmel,at97sc3203";
- reg = <0x29>;
- read-only;
- };
-
- power-monitor@40 {
- /* No driver */
- compatible = "isl,isl28022";
- reg = <0x40>;
- };
- };
};
leds {
pins = "gpio20", "gpio21";
function = "blsp_i2c0";
drive-strength = <4>;
- bias-disable;
+ bias-pull-up;
};
};
};
};
+&blsp1_i2c3 {
+ pinctrl-0 = <&i2c_0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tpm@29 {
+ /* No Driver */
+ compatible = "atmel,at97sc3203";
+ reg = <0x29>;
+ read-only;
+ };
+
+ power-monitor@40 {
+ /* No driver */
+ /* Device also replies on address 0x3f, see */
+ /* ISL28022 datasheet, "Broadcast Addressing" */
+ compatible = "isl,isl28022";
+ reg = <0x40>;
+ };
+};
+
&blsp1_spi1 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
#size-cells = <1>;
macaddr_mfginfo_1d: macaddr@1d {
+ compatible = "mac-base";
reg = <0x1d 0x6>;
+ #nvmem-cell-cells = <1>;
};
macaddr_mfginfo_45: macaddr@45 {
};
};
-&usb2_hs_phy {
+&usb3 {
+ status = "okay";
+};
+
+&usb3_dwc {
+ phys = <&usb3_hs_phy>;
+ phy-names = "usb2-phy";
+};
+
+&usb3_hs_phy {
status = "okay";
};
&gmac {
status = "okay";
+
+ nvmem-cell-names = "mac-address";
+ nvmem-cells = <&macaddr_mfginfo_1d 1>;
};
&switch {
status = "okay";
label = "wan";
+ nvmem-cell-names = "mac-address";
+ nvmem-cells = <&macaddr_mfginfo_1d 0>;
};
&wifi0 {
PROFILES := Default
KERNEL_DEPENDS = $$(wildcard $(DTS_DIR)/$$(DEVICE_DTS).dts)
KERNEL_LOADADDR := 0x80208000
- DEVICE_DTS_DIR = $(if $(CONFIG_TESTING_KERNEL),$$(DTS_DIR)/qcom,$$(DTS_DIR))
+ DEVICE_DTS_DIR = $$(DTS_DIR)/qcom
DEVICE_DTS = $$(SOC)-$(lastword $(subst _, ,$(1)))
DEVICE_DTS_CONFIG := config@1
IMAGES := sysupgrade.bin
+++ /dev/null
-From be59072c6eeb7535bf9a339fb9d5a8bfae17ac22 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robert.marko@sartura.hr>
-Date: Mon, 14 Aug 2023 12:40:23 +0200
-Subject: [PATCH] dt-bindings: clock: qcom: ipq4019: add missing networking
- resets
-
-Add bindings for the missing networking resets found in IPQ4019 GCC.
-
-Signed-off-by: Robert Marko <robert.marko@sartura.hr>
-Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Link: https://lore.kernel.org/r/20230814104119.96858-1-robert.marko@sartura.hr
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
----
- include/dt-bindings/clock/qcom,gcc-ipq4019.h | 6 ++++++
- 1 file changed, 6 insertions(+)
-
---- a/include/dt-bindings/clock/qcom,gcc-ipq4019.h
-+++ b/include/dt-bindings/clock/qcom,gcc-ipq4019.h
-@@ -165,5 +165,11 @@
- #define GCC_QDSS_BCR 69
- #define GCC_MPM_BCR 70
- #define GCC_SPDM_BCR 71
-+#define ESS_MAC1_ARES 72
-+#define ESS_MAC2_ARES 73
-+#define ESS_MAC3_ARES 74
-+#define ESS_MAC4_ARES 75
-+#define ESS_MAC5_ARES 76
-+#define ESS_PSGMII_ARES 77
-
- #endif
+++ /dev/null
-From 20014461691efc9e274c3870357152db7f091820 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robert.marko@sartura.hr>
-Date: Mon, 14 Aug 2023 12:40:24 +0200
-Subject: [PATCH] clk: qcom: gcc-ipq4019: add missing networking resets
-
-IPQ4019 has more networking related resets that will be required for future
-wired networking support, so lets add them.
-
-Signed-off-by: Robert Marko <robert.marko@sartura.hr>
-Link: https://lore.kernel.org/r/20230814104119.96858-2-robert.marko@sartura.hr
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
----
- drivers/clk/qcom/gcc-ipq4019.c | 6 ++++++
- 1 file changed, 6 insertions(+)
-
---- a/drivers/clk/qcom/gcc-ipq4019.c
-+++ b/drivers/clk/qcom/gcc-ipq4019.c
-@@ -1707,6 +1707,12 @@ static const struct qcom_reset_map gcc_i
- [GCC_TCSR_BCR] = {0x22000, 0},
- [GCC_MPM_BCR] = {0x24000, 0},
- [GCC_SPDM_BCR] = {0x25000, 0},
-+ [ESS_MAC1_ARES] = {0x1200C, 0},
-+ [ESS_MAC2_ARES] = {0x1200C, 1},
-+ [ESS_MAC3_ARES] = {0x1200C, 2},
-+ [ESS_MAC4_ARES] = {0x1200C, 3},
-+ [ESS_MAC5_ARES] = {0x1200C, 4},
-+ [ESS_PSGMII_ARES] = {0x1200C, 5},
- };
-
- static const struct regmap_config gcc_ipq4019_regmap_config = {
+++ /dev/null
-From ff4aa3bc98258a240b9bbab53fd8d2fb8184c485 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Wed, 16 Aug 2023 18:45:39 +0200
-Subject: [PATCH] firmware: qcom_scm: disable SDI if required
-
-IPQ5018 has SDI (Secure Debug Image) enabled by TZ by default, and that
-means that WDT being asserted or just trying to reboot will hang the board
-in the debug mode and only pulling the power and repowering will help.
-Some IPQ4019 boards like Google WiFI have it enabled as well.
-
-Luckily, SDI can be disabled via an SCM call.
-
-So, lets use the boolean DT property to identify boards that have SDI
-enabled by default and use the SCM call to disable SDI during SCM probe.
-It is important to disable it as soon as possible as we might have a WDT
-assertion at any time which would then leave the board in debug mode,
-thus disabling it during SCM removal is not enough.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Reviewed-by: Guru Das Srinagesh <quic_gurus@quicinc.com>
-Link: https://lore.kernel.org/r/20230816164641.3371878-2-robimarko@gmail.com
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
----
- drivers/firmware/qcom_scm.c | 30 ++++++++++++++++++++++++++++++
- drivers/firmware/qcom_scm.h | 1 +
- 2 files changed, 31 insertions(+)
-
---- a/drivers/firmware/qcom_scm.c
-+++ b/drivers/firmware/qcom_scm.c
-@@ -407,6 +407,29 @@ int qcom_scm_set_remote_state(u32 state,
- }
- EXPORT_SYMBOL(qcom_scm_set_remote_state);
-
-+static int qcom_scm_disable_sdi(void)
-+{
-+ int ret;
-+ struct qcom_scm_desc desc = {
-+ .svc = QCOM_SCM_SVC_BOOT,
-+ .cmd = QCOM_SCM_BOOT_SDI_CONFIG,
-+ .args[0] = 1, /* Disable watchdog debug */
-+ .args[1] = 0, /* Disable SDI */
-+ .arginfo = QCOM_SCM_ARGS(2),
-+ .owner = ARM_SMCCC_OWNER_SIP,
-+ };
-+ struct qcom_scm_res res;
-+
-+ ret = qcom_scm_clk_enable();
-+ if (ret)
-+ return ret;
-+ ret = qcom_scm_call(__scm->dev, &desc, &res);
-+
-+ qcom_scm_clk_disable();
-+
-+ return ret ? : res.result[0];
-+}
-+
- static int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
- {
- struct qcom_scm_desc desc = {
-@@ -1411,6 +1434,13 @@ static int qcom_scm_probe(struct platfor
-
- __get_convention();
-
-+
-+ /*
-+ * Disable SDI if indicated by DT that it is enabled by default.
-+ */
-+ if (of_property_read_bool(pdev->dev.of_node, "qcom,sdi-enabled"))
-+ qcom_scm_disable_sdi();
-+
- /*
- * If requested enable "download mode", from this point on warmboot
- * will cause the boot stages to enter download mode, unless
---- a/drivers/firmware/qcom_scm.h
-+++ b/drivers/firmware/qcom_scm.h
-@@ -77,6 +77,7 @@ extern int scm_legacy_call(struct device
- #define QCOM_SCM_SVC_BOOT 0x01
- #define QCOM_SCM_BOOT_SET_ADDR 0x01
- #define QCOM_SCM_BOOT_TERMINATE_PC 0x02
-+#define QCOM_SCM_BOOT_SDI_CONFIG 0x09
- #define QCOM_SCM_BOOT_SET_DLOAD_MODE 0x10
- #define QCOM_SCM_BOOT_SET_ADDR_MC 0x11
- #define QCOM_SCM_BOOT_SET_REMOTE_STATE 0x0a
+++ /dev/null
-From ea9fba16d972becc84cd2a82d25030975dc609a5 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Sat, 30 Sep 2023 13:09:27 +0200
-Subject: [PATCH] ARM: dts: qcom: ipq4019: add label to SCM
-
-Some IPQ4019 boards require SDI to be disabled by adding a property to the
-SCM node, so lets make that easy by adding a label to the SCM node.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -155,7 +155,7 @@
- };
-
- firmware {
-- scm {
-+ scm: scm {
- compatible = "qcom,scm-ipq4019", "qcom,scm";
- };
- };
+++ /dev/null
-From f2b87dc1028b710ec8ce25808b9d21f92b376184 Mon Sep 17 00:00:00 2001
-From: Christian Lamparter <chunkeey@googlemail.com>
-Date: Sun, 11 Mar 2018 14:41:31 +0100
-Subject: [PATCH 2/2] clk: fix apss cpu overclocking
-
-There's an interaction issue between the clk changes:"
-clk: qcom: ipq4019: Add the apss cpu pll divider clock node
-clk: qcom: ipq4019: remove fixed clocks and add pll clocks
-" and the cpufreq-dt.
-
-cpufreq-dt is now spamming the kernel-log with the following:
-
-[ 1099.190658] cpu cpu0: dev_pm_opp_set_rate: failed to find current OPP
-for freq 761142857 (-34)
-
-This only happens on certain devices like the Compex WPJ428
-and AVM FritzBox!4040. However, other devices like the Asus
-RT-AC58U and Meraki MR33 work just fine.
-
-The issue stem from the fact that all higher CPU-Clocks
-are achieved by switching the clock-parent to the P_DDRPLLAPSS
-(ddrpllapss). Which is set by Qualcomm's proprietary bootcode
-as part of the DDR calibration.
-
-For example, the FB4040 uses 256 MiB Nanya NT5CC128M16IP clocked
-at round 533 MHz (ddrpllsdcc = 190285714 Hz).
-
-whereas the 128 MiB Nanya NT5CC64M16GP-DI in the ASUS RT-AC58U is
-clocked at a slightly higher 537 MHz ( ddrpllsdcc = 192000000 Hz).
-
-This patch attempts to fix the issue by modifying
-clk_cpu_div_round_rate(), clk_cpu_div_set_rate(), clk_cpu_div_recalc_rate()
-to use a new qcom_find_freq_close() function, which returns the closest
-matching frequency, instead of the next higher. This way, the SoC in
-the FB4040 (with its max clock speed of 710.4 MHz) will no longer
-try to overclock to 761 MHz.
-
-Fixes: d83dcacea18 ("clk: qcom: ipq4019: Add the apss cpu pll divider clock node")
-Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
-Signed-off-by: John Crispin <john@phrozen.org>
----
- drivers/clk/qcom/gcc-ipq4019.c | 34 +++++++++++++++++++++++++++++++---
- 1 file changed, 31 insertions(+), 3 deletions(-)
-
---- a/drivers/clk/qcom/gcc-ipq4019.c
-+++ b/drivers/clk/qcom/gcc-ipq4019.c
-@@ -1243,6 +1243,29 @@ static const struct clk_fepll_vco gcc_fe
- .reg = 0x2f020,
- };
-
-+
-+const struct freq_tbl *qcom_find_freq_close(const struct freq_tbl *f,
-+ unsigned long rate)
-+{
-+ const struct freq_tbl *last = NULL;
-+
-+ for ( ; f->freq; f++) {
-+ if (rate == f->freq)
-+ return f;
-+
-+ if (f->freq > rate) {
-+ if (!last ||
-+ (f->freq - rate) < (rate - last->freq))
-+ return f;
-+ else
-+ return last;
-+ }
-+ last = f;
-+ }
-+
-+ return last;
-+}
-+
- /*
- * Round rate function for APSS CPU PLL Clock divider.
- * It looks up the frequency table and returns the next higher frequency
-@@ -1255,7 +1278,7 @@ static long clk_cpu_div_round_rate(struc
- struct clk_hw *p_hw;
- const struct freq_tbl *f;
-
-- f = qcom_find_freq(pll->freq_tbl, rate);
-+ f = qcom_find_freq_close(pll->freq_tbl, rate);
- if (!f)
- return -EINVAL;
-
-@@ -1277,7 +1300,7 @@ static int clk_cpu_div_set_rate(struct c
- const struct freq_tbl *f;
- u32 mask;
-
-- f = qcom_find_freq(pll->freq_tbl, rate);
-+ f = qcom_find_freq_close(pll->freq_tbl, rate);
- if (!f)
- return -EINVAL;
-
-@@ -1304,6 +1327,7 @@ static unsigned long
- clk_cpu_div_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
- {
-+ const struct freq_tbl *f;
- struct clk_fepll *pll = to_clk_fepll(hw);
- u32 cdiv, pre_div;
- u64 rate;
-@@ -1324,7 +1348,11 @@ clk_cpu_div_recalc_rate(struct clk_hw *h
- rate = clk_fepll_vco_calc_rate(pll, parent_rate) * 2;
- do_div(rate, pre_div);
-
-- return rate;
-+ f = qcom_find_freq_close(pll->freq_tbl, rate);
-+ if (!f)
-+ return rate;
-+
-+ return f->freq;
- };
-
- static const struct clk_ops clk_regmap_cpu_div_ops = {
+++ /dev/null
-From 0843a61d6913bdac8889eb048ed89f7903059787 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Fri, 30 Oct 2020 13:36:31 +0100
-Subject: [PATCH] arm: compressed: add appended DTB section
-
-This adds a appended_dtb section to the ARM decompressor
-linker script.
-
-This allows using the existing ARM zImage appended DTB support for
-appending a DTB to the raw ELF kernel.
-
-Its size is set to 1MB max to match the zImage appended DTB size limit.
-
-To use it to pass the DTB to the kernel, objcopy is used:
-
-objcopy --set-section-flags=.appended_dtb=alloc,contents \
- --update-section=.appended_dtb=<target>.dtb vmlinux
-
-This is based off the following patch:
-https://github.com/openwrt/openwrt/commit/c063e27e02a9dcac0e7f5877fb154e58fa3e1a69
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- arch/arm/boot/compressed/vmlinux.lds.S | 9 ++++++++-
- 1 file changed, 8 insertions(+), 1 deletion(-)
-
---- a/arch/arm/boot/compressed/vmlinux.lds.S
-+++ b/arch/arm/boot/compressed/vmlinux.lds.S
-@@ -103,6 +103,13 @@ SECTIONS
-
- _edata = .;
-
-+ .appended_dtb : {
-+ /* leave space for appended DTB */
-+ . += 0x100000;
-+ }
-+
-+ _edata_dtb = .;
-+
- /*
- * The image_end section appears after any additional loadable sections
- * that the linker may decide to insert in the binary image. Having
-@@ -140,4 +147,4 @@ SECTIONS
-
- ARM_ASSERTS
- }
--ASSERT(_edata_real == _edata, "error: zImage file size is incorrect");
-+ASSERT(_edata_real == _edata_dtb, "error: zImage file size is incorrect");
+++ /dev/null
-From 11d6a6128a5a07c429941afc202b6e62a19771be Mon Sep 17 00:00:00 2001
-From: John Thomson <git@johnthomson.fastmail.com.au>
-Date: Fri, 23 Oct 2020 19:42:36 +1000
-Subject: [PATCH 2/2] arm: compressed: set ipq40xx watchdog to allow boot
-
-For IPQ40XX systems where the SoC watchdog is activated before linux,
-the watchdog timer may be too small for linux to finish uncompress,
-boot, and watchdog management start.
-If the watchdog is enabled, set the timeout for it to 30 seconds.
-The functionality and offsets were copied from:
-drivers/watchdog/qcom-wdt.c qcom_wdt_set_timeout & qcom_wdt_start
-The watchdog memory address was taken from:
-arch/arm/boot/dts/qcom-ipq4019.dtsi
-
-This was required on Mikrotik IPQ40XX consumer hardware using Mikrotik's
-RouterBoot bootloader.
-
-Signed-off-by: John Thomson <git@johnthomson.fastmail.com.au>
----
- arch/arm/boot/compressed/head.S | 35 +++++++++++++++++++++++++++++++++
- 1 file changed, 35 insertions(+)
-
---- a/arch/arm/boot/compressed/head.S
-+++ b/arch/arm/boot/compressed/head.S
-@@ -620,6 +620,41 @@ not_relocated: mov r0, #0
- bic r4, r4, #1
- blne cache_on
-
-+/* Set the Qualcom IPQ40xx watchdog timeout to 30 seconds
-+ * if it is enabled, so that there is time for kernel
-+ * to decompress, boot, and take over the watchdog.
-+ * data and functionality from drivers/watchdog/qcom-wdt.c
-+ * address from arch/arm/boot/dts/qcom-ipq4019.dtsi
-+ */
-+#ifdef CONFIG_ARCH_IPQ40XX
-+watchdog_set:
-+ /* offsets:
-+ * 0x04 reset (=1 resets countdown)
-+ * 0x08 enable (=0 disables)
-+ * 0x0c status (=1 when SoC was reset by watchdog)
-+ * 0x10 bark (=timeout warning in ticks)
-+ * 0x14 bite (=timeout reset in ticks)
-+ * clock rate is 1<<15 hertz
-+ */
-+ .equ watchdog, 0x0b017000 @Store watchdog base address
-+ movw r0, #:lower16:watchdog
-+ movt r0, #:upper16:watchdog
-+ ldr r1, [r0, #0x08] @Get enabled?
-+ cmp r1, #1 @If not enabled, do not change
-+ bne watchdog_finished
-+ mov r1, #0
-+ str r1, [r0, #0x08] @Disable the watchdog
-+ mov r1, #1
-+ str r1, [r0, #0x04] @Pet the watchdog
-+ mov r1, #30 @30 seconds timeout
-+ lsl r1, r1, #15 @converted to ticks
-+ str r1, [r0, #0x10] @Set the bark timeout
-+ str r1, [r0, #0x14] @Set the bite timeout
-+ mov r1, #1
-+ str r1, [r0, #0x08] @Enable the watchdog
-+watchdog_finished:
-+#endif /* CONFIG_ARCH_IPQ40XX */
-+
- /*
- * The C runtime environment should now be setup sufficiently.
- * Set up some pointers, and start decompressing.
+++ /dev/null
-From f63ea127643a605da97090ce585fdd7c2d17fa42 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robert.marko@sartura.hr>
-Date: Mon, 14 Dec 2020 13:35:35 +0100
-Subject: [PATCH] mmc: sdhci-msm: use sdhci_set_clock
-
-When using sdhci_msm_set_clock clock setting will fail, so lets
-use the generic sdhci_set_clock.
-
-Signed-off-by: Robert Marko <robert.marko@sartura.hr>
----
- drivers/mmc/host/sdhci-msm.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/mmc/host/sdhci-msm.c
-+++ b/drivers/mmc/host/sdhci-msm.c
-@@ -2451,7 +2451,7 @@ MODULE_DEVICE_TABLE(of, sdhci_msm_dt_mat
-
- static const struct sdhci_ops sdhci_msm_ops = {
- .reset = sdhci_msm_reset,
-- .set_clock = sdhci_msm_set_clock,
-+ .set_clock = sdhci_set_clock,
- .get_min_clock = sdhci_msm_get_min_clock,
- .get_max_clock = sdhci_msm_get_max_clock,
- .set_bus_width = sdhci_set_bus_width,
+++ /dev/null
-From 28edd829133766eb3cefaf2e49d3ee701968061b Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Tue, 9 May 2023 01:57:17 +0200
-Subject: [PATCH] mmc: sdhci-msm: comment unused sdhci_msm_set_clock
-
-comment unused sdhci_msm_set_clock and __sdhci_msm_set_clock as due to some
-current problem, we are forced to use sdhci_set_clock.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- drivers/mmc/host/sdhci-msm.c | 86 ++++++++++++++++++------------------
- 1 file changed, 43 insertions(+), 43 deletions(-)
-
---- a/drivers/mmc/host/sdhci-msm.c
-+++ b/drivers/mmc/host/sdhci-msm.c
-@@ -1751,49 +1751,49 @@ static unsigned int sdhci_msm_get_min_cl
- return SDHCI_MSM_MIN_CLOCK;
- }
-
--/*
-- * __sdhci_msm_set_clock - sdhci_msm clock control.
-- *
-- * Description:
-- * MSM controller does not use internal divider and
-- * instead directly control the GCC clock as per
-- * HW recommendation.
-- **/
--static void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
--{
-- u16 clk;
--
-- sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
--
-- if (clock == 0)
-- return;
--
-- /*
-- * MSM controller do not use clock divider.
-- * Thus read SDHCI_CLOCK_CONTROL and only enable
-- * clock with no divider value programmed.
-- */
-- clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
-- sdhci_enable_clk(host, clk);
--}
--
--/* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
--static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
--{
-- struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
-- struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
--
-- if (!clock) {
-- host->mmc->actual_clock = msm_host->clk_rate = 0;
-- goto out;
-- }
--
-- sdhci_msm_hc_select_mode(host);
--
-- msm_set_clock_rate_for_bus_mode(host, clock);
--out:
-- __sdhci_msm_set_clock(host, clock);
--}
-+// /*
-+// * __sdhci_msm_set_clock - sdhci_msm clock control.
-+// *
-+// * Description:
-+// * MSM controller does not use internal divider and
-+// * instead directly control the GCC clock as per
-+// * HW recommendation.
-+// **/
-+// static void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
-+// {
-+// u16 clk;
-+
-+// sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
-+
-+// if (clock == 0)
-+// return;
-+
-+// /*
-+// * MSM controller do not use clock divider.
-+// * Thus read SDHCI_CLOCK_CONTROL and only enable
-+// * clock with no divider value programmed.
-+// */
-+// clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
-+// sdhci_enable_clk(host, clk);
-+// }
-+
-+// /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
-+// static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
-+// {
-+// struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
-+// struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
-+
-+// if (!clock) {
-+// host->mmc->actual_clock = msm_host->clk_rate = 0;
-+// goto out;
-+// }
-+
-+// sdhci_msm_hc_select_mode(host);
-+
-+// msm_set_clock_rate_for_bus_mode(host, clock);
-+// out:
-+// __sdhci_msm_set_clock(host, clock);
-+// }
-
- /*****************************************************************************\
- * *
+++ /dev/null
-From aaa675f07e781e248fcf169ce9a917b48bc2cc9b Mon Sep 17 00:00:00 2001
-From: Brian Norris <computersforpeace@gmail.com>
-Date: Fri, 28 Jul 2023 12:06:23 +0200
-Subject: [PATCH 3/3] firmware: qcom: scm: fix SCM cold boot address
-
-This effectively reverts upstream Linux commit 13e77747800e ("firmware:
-qcom: scm: Use atomic SCM for cold boot"), because Google WiFi boot
-firmwares don't support the atomic variant.
-
-This fixes SMP support for Google WiFi.
-
-Signed-off-by: Brian Norris <computersforpeace@gmail.com>
----
- drivers/firmware/qcom_scm-legacy.c | 62 +++++++++++++++++++++++++-----
- drivers/firmware/qcom_scm.c | 11 ++++++
- 2 files changed, 63 insertions(+), 10 deletions(-)
-
---- a/drivers/firmware/qcom_scm-legacy.c
-+++ b/drivers/firmware/qcom_scm-legacy.c
-@@ -13,6 +13,9 @@
- #include <linux/arm-smccc.h>
- #include <linux/dma-mapping.h>
-
-+#include <asm/cacheflush.h>
-+#include <asm/outercache.h>
-+
- #include "qcom_scm.h"
-
- static DEFINE_MUTEX(qcom_scm_lock);
-@@ -117,6 +120,25 @@ static void __scm_legacy_do(const struct
- } while (res->a0 == QCOM_SCM_INTERRUPTED);
- }
-
-+static void qcom_scm_inv_range(unsigned long start, unsigned long end)
-+{
-+ u32 cacheline_size, ctr;
-+
-+ asm volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (ctr));
-+ cacheline_size = 4 << ((ctr >> 16) & 0xf);
-+
-+ start = round_down(start, cacheline_size);
-+ end = round_up(end, cacheline_size);
-+ outer_inv_range(start, end);
-+ while (start < end) {
-+ asm ("mcr p15, 0, %0, c7, c6, 1" : : "r" (start)
-+ : "memory");
-+ start += cacheline_size;
-+ }
-+ dsb();
-+ isb();
-+}
-+
- /**
- * scm_legacy_call() - Sends a command to the SCM and waits for the command to
- * finish processing.
-@@ -163,10 +185,16 @@ int scm_legacy_call(struct device *dev,
-
- rsp = scm_legacy_command_to_response(cmd);
-
-- cmd_phys = dma_map_single(dev, cmd, alloc_len, DMA_TO_DEVICE);
-- if (dma_mapping_error(dev, cmd_phys)) {
-- kfree(cmd);
-- return -ENOMEM;
-+ if (dev) {
-+ cmd_phys = dma_map_single(dev, cmd, alloc_len, DMA_TO_DEVICE);
-+ if (dma_mapping_error(dev, cmd_phys)) {
-+ kfree(cmd);
-+ return -ENOMEM;
-+ }
-+ } else {
-+ cmd_phys = virt_to_phys(cmd);
-+ __cpuc_flush_dcache_area(cmd, alloc_len);
-+ outer_flush_range(cmd_phys, cmd_phys + alloc_len);
- }
-
- smc.args[0] = 1;
-@@ -182,13 +210,26 @@ int scm_legacy_call(struct device *dev,
- goto out;
-
- do {
-- dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len,
-- sizeof(*rsp), DMA_FROM_DEVICE);
-+ if (dev) {
-+ dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) +
-+ cmd_len, sizeof(*rsp),
-+ DMA_FROM_DEVICE);
-+ } else {
-+ unsigned long start = (uintptr_t)cmd + sizeof(*cmd) +
-+ cmd_len;
-+ qcom_scm_inv_range(start, start + sizeof(*rsp));
-+ }
- } while (!rsp->is_complete);
-
-- dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len +
-- le32_to_cpu(rsp->buf_offset),
-- resp_len, DMA_FROM_DEVICE);
-+ if (dev) {
-+ dma_sync_single_for_cpu(dev, cmd_phys + sizeof(*cmd) + cmd_len +
-+ le32_to_cpu(rsp->buf_offset),
-+ resp_len, DMA_FROM_DEVICE);
-+ } else {
-+ unsigned long start = (uintptr_t)cmd + sizeof(*cmd) + cmd_len +
-+ le32_to_cpu(rsp->buf_offset);
-+ qcom_scm_inv_range(start, start + resp_len);
-+ }
-
- if (res) {
- res_buf = scm_legacy_get_response_buffer(rsp);
-@@ -196,7 +237,8 @@ int scm_legacy_call(struct device *dev,
- res->result[i] = le32_to_cpu(res_buf[i]);
- }
- out:
-- dma_unmap_single(dev, cmd_phys, alloc_len, DMA_TO_DEVICE);
-+ if (dev)
-+ dma_unmap_single(dev, cmd_phys, alloc_len, DMA_TO_DEVICE);
- kfree(cmd);
- return ret;
- }
---- a/drivers/firmware/qcom_scm.c
-+++ b/drivers/firmware/qcom_scm.c
-@@ -312,6 +312,17 @@ static int qcom_scm_set_boot_addr(void *
- desc.args[0] = flags;
- desc.args[1] = virt_to_phys(entry);
-
-+ /*
-+ * Factory firmware doesn't support the atomic variant. Non-atomic SCMs
-+ * require ugly DMA invalidation support that was dropped upstream a
-+ * while ago. For more info, see:
-+ *
-+ * [RFC] qcom_scm: IPQ4019 firmware does not support atomic API?
-+ * https://lore.kernel.org/linux-arm-msm/20200913201608.GA3162100@bDebian/
-+ */
-+ if (of_machine_is_compatible("google,wifi"))
-+ return qcom_scm_call(__scm ? __scm->dev : NULL, &desc, NULL);
-+
- return qcom_scm_call_atomic(__scm ? __scm->dev : NULL, &desc, NULL);
- }
-
+++ /dev/null
-From 35ca7e3e6ccd120d694a3425f37fc6374ad2e11e Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Andreas=20B=C3=B6hler?= <dev@aboehler.at>
-Date: Wed, 20 Apr 2022 12:08:38 +0200
-Subject: [PATCH] mtd: rawnand: add support for Toshiba TC58NVG0S3HTA00
- NAND flash
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The Toshiba TC58NVG0S3HTA00 is detected with 64 byte OOB while the flash
-has 128 bytes OOB. This adds a static NAND ID entry to correct this.
-
-Tested on FRITZ!Box 7530 flashed with OpenWrt.
-
-Signed-off-by: Andreas Böhler <dev@aboehler.at>
-(changed id_len to 8, added comment about possible counterfeits)
----
---- a/drivers/mtd/nand/raw/nand_ids.c
-+++ b/drivers/mtd/nand/raw/nand_ids.c
-@@ -29,6 +29,9 @@ struct nand_flash_dev nand_flash_ids[] =
- {"TC58NVG0S3E 1G 3.3V 8-bit",
- { .id = {0x98, 0xd1, 0x90, 0x15, 0x76, 0x14, 0x01, 0x00} },
- SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), },
-+ {"TC58NVG0S3HTA00 1G 3.3V 8-bit", /* possibly counterfeit chip - see commit */
-+ { .id = {0x98, 0xf1, 0x80, 0x15} }, /* should be more bytes */
-+ SZ_2K, SZ_128, SZ_128K, 0, 8, 128, NAND_ECC_INFO(8, SZ_512), },
- {"TC58NVG2S0F 4G 3.3V 8-bit",
- { .id = {0x98, 0xdc, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08} },
- SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) },
+++ /dev/null
-From 76e25c1f46456416ba5358be8a0677f1ab8196b6 Mon Sep 17 00:00:00 2001
-From: Maxime Chevallier <maxime.chevallier@bootlin.com>
-Date: Fri, 4 Nov 2022 18:41:48 +0100
-Subject: [PATCH] net: ipqess: introduce the Qualcomm IPQESS driver
-
-The Qualcomm IPQESS controller is a simple 1G Ethernet controller found
-on the IPQ4019 chip. This controller has some specificities, in that the
-IPQ4019 platform that includes that controller also has an internal
-switch, based on the QCA8K IP.
-
-It is connected to that switch through an internal link, and doesn't
-expose directly any external interface, hence it only supports the
-PHY_INTERFACE_MODE_INTERNAL for now.
-
-It has 16 RX and TX queues, with a very basic RSS fanout configured at
-init time.
-
-Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
----
- MAINTAINERS | 7 +
- drivers/net/ethernet/qualcomm/Kconfig | 11 +
- drivers/net/ethernet/qualcomm/Makefile | 2 +
- drivers/net/ethernet/qualcomm/ipqess/Makefile | 8 +
- drivers/net/ethernet/qualcomm/ipqess/ipqess.c | 1246 +++++++++++++++++
- drivers/net/ethernet/qualcomm/ipqess/ipqess.h | 518 +++++++
- .../ethernet/qualcomm/ipqess/ipqess_ethtool.c | 164 +++
- 7 files changed, 1956 insertions(+)
- create mode 100644 drivers/net/ethernet/qualcomm/ipqess/Makefile
- create mode 100644 drivers/net/ethernet/qualcomm/ipqess/ipqess.c
- create mode 100644 drivers/net/ethernet/qualcomm/ipqess/ipqess.h
- create mode 100644 drivers/net/ethernet/qualcomm/ipqess/ipqess_ethtool.c
-
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -17075,6 +17075,13 @@ L: netdev@vger.kernel.org
- S: Maintained
- F: drivers/net/ethernet/qualcomm/emac/
-
-+QUALCOMM IPQESS ETHERNET DRIVER
-+M: Maxime Chevallier <maxime.chevallier@bootlin.com>
-+L: netdev@vger.kernel.org
-+S: Maintained
-+F: Documentation/devicetree/bindings/net/qcom,ipq4019-ess-edma.yaml
-+F: drivers/net/ethernet/qualcomm/ipqess/
-+
- QUALCOMM ETHQOS ETHERNET DRIVER
- M: Vinod Koul <vkoul@kernel.org>
- R: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---- a/drivers/net/ethernet/qualcomm/Kconfig
-+++ b/drivers/net/ethernet/qualcomm/Kconfig
-@@ -60,6 +60,17 @@ config QCOM_EMAC
- low power, Receive-Side Scaling (RSS), and IEEE 1588-2008
- Precision Clock Synchronization Protocol.
-
-+config QCOM_IPQ4019_ESS_EDMA
-+ tristate "Qualcomm Atheros IPQ4019 ESS EDMA support"
-+ depends on (OF && ARCH_QCOM) || COMPILE_TEST
-+ select PHYLINK
-+ help
-+ This driver supports the Qualcomm Atheros IPQ40xx built-in
-+ ESS EDMA ethernet controller.
-+
-+ To compile this driver as a module, choose M here: the
-+ module will be called ipqess.
-+
- source "drivers/net/ethernet/qualcomm/rmnet/Kconfig"
-
- endif # NET_VENDOR_QUALCOMM
---- a/drivers/net/ethernet/qualcomm/Makefile
-+++ b/drivers/net/ethernet/qualcomm/Makefile
-@@ -11,4 +11,6 @@ qcauart-objs := qca_uart.o
-
- obj-y += emac/
-
-+obj-$(CONFIG_QCOM_IPQ4019_ESS_EDMA) += ipqess/
-+
- obj-$(CONFIG_RMNET) += rmnet/
---- /dev/null
-+++ b/drivers/net/ethernet/qualcomm/ipqess/Makefile
-@@ -0,0 +1,8 @@
-+# SPDX-License-Identifier: GPL-2.0-only
-+#
-+# Makefile for the IPQ ESS driver
-+#
-+
-+obj-$(CONFIG_QCOM_IPQ4019_ESS_EDMA) += ipq_ess.o
-+
-+ipq_ess-objs := ipqess.o ipqess_ethtool.o
---- /dev/null
-+++ b/drivers/net/ethernet/qualcomm/ipqess/ipqess.c
-@@ -0,0 +1,1246 @@
-+// SPDX-License-Identifier: GPL-2.0 OR ISC
-+/* Copyright (c) 2014 - 2017, The Linux Foundation. All rights reserved.
-+ * Copyright (c) 2017 - 2018, John Crispin <john@phrozen.org>
-+ * Copyright (c) 2018 - 2019, Christian Lamparter <chunkeey@gmail.com>
-+ * Copyright (c) 2020 - 2021, Gabor Juhos <j4g8y7@gmail.com>
-+ * Copyright (c) 2021 - 2022, Maxime Chevallier <maxime.chevallier@bootlin.com>
-+ *
-+ */
-+
-+#include <linux/bitfield.h>
-+#include <linux/clk.h>
-+#include <linux/if_vlan.h>
-+#include <linux/interrupt.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/of_device.h>
-+#include <linux/of_mdio.h>
-+#include <linux/of_net.h>
-+#include <linux/phylink.h>
-+#include <linux/platform_device.h>
-+#include <linux/reset.h>
-+#include <linux/skbuff.h>
-+#include <linux/vmalloc.h>
-+#include <net/checksum.h>
-+#include <net/ip6_checksum.h>
-+
-+#include "ipqess.h"
-+
-+#define IPQESS_RRD_SIZE 16
-+#define IPQESS_NEXT_IDX(X, Y) (((X) + 1) & ((Y) - 1))
-+#define IPQESS_TX_DMA_BUF_LEN 0x3fff
-+
-+static void ipqess_w32(struct ipqess *ess, u32 reg, u32 val)
-+{
-+ writel(val, ess->hw_addr + reg);
-+}
-+
-+static u32 ipqess_r32(struct ipqess *ess, u16 reg)
-+{
-+ return readl(ess->hw_addr + reg);
-+}
-+
-+static void ipqess_m32(struct ipqess *ess, u32 mask, u32 val, u16 reg)
-+{
-+ u32 _val = ipqess_r32(ess, reg);
-+
-+ _val &= ~mask;
-+ _val |= val;
-+
-+ ipqess_w32(ess, reg, _val);
-+}
-+
-+void ipqess_update_hw_stats(struct ipqess *ess)
-+{
-+ u32 *p;
-+ u32 stat;
-+ int i;
-+
-+ lockdep_assert_held(&ess->stats_lock);
-+
-+ p = (u32 *)&ess->ipqess_stats;
-+ for (i = 0; i < IPQESS_MAX_TX_QUEUE; i++) {
-+ stat = ipqess_r32(ess, IPQESS_REG_TX_STAT_PKT_Q(i));
-+ *p += stat;
-+ p++;
-+ }
-+
-+ for (i = 0; i < IPQESS_MAX_TX_QUEUE; i++) {
-+ stat = ipqess_r32(ess, IPQESS_REG_TX_STAT_BYTE_Q(i));
-+ *p += stat;
-+ p++;
-+ }
-+
-+ for (i = 0; i < IPQESS_MAX_RX_QUEUE; i++) {
-+ stat = ipqess_r32(ess, IPQESS_REG_RX_STAT_PKT_Q(i));
-+ *p += stat;
-+ p++;
-+ }
-+
-+ for (i = 0; i < IPQESS_MAX_RX_QUEUE; i++) {
-+ stat = ipqess_r32(ess, IPQESS_REG_RX_STAT_BYTE_Q(i));
-+ *p += stat;
-+ p++;
-+ }
-+}
-+
-+static int ipqess_tx_ring_alloc(struct ipqess *ess)
-+{
-+ struct device *dev = &ess->pdev->dev;
-+ int i;
-+
-+ for (i = 0; i < IPQESS_NETDEV_QUEUES; i++) {
-+ struct ipqess_tx_ring *tx_ring = &ess->tx_ring[i];
-+ size_t size;
-+ u32 idx;
-+
-+ tx_ring->ess = ess;
-+ tx_ring->ring_id = i;
-+ tx_ring->idx = i * 4;
-+ tx_ring->count = IPQESS_TX_RING_SIZE;
-+ tx_ring->nq = netdev_get_tx_queue(ess->netdev, i);
-+
-+ size = sizeof(struct ipqess_buf) * IPQESS_TX_RING_SIZE;
-+ tx_ring->buf = devm_kzalloc(dev, size, GFP_KERNEL);
-+ if (!tx_ring->buf)
-+ return -ENOMEM;
-+
-+ size = sizeof(struct ipqess_tx_desc) * IPQESS_TX_RING_SIZE;
-+ tx_ring->hw_desc = dmam_alloc_coherent(dev, size, &tx_ring->dma,
-+ GFP_KERNEL);
-+ if (!tx_ring->hw_desc)
-+ return -ENOMEM;
-+
-+ ipqess_w32(ess, IPQESS_REG_TPD_BASE_ADDR_Q(tx_ring->idx),
-+ (u32)tx_ring->dma);
-+
-+ idx = ipqess_r32(ess, IPQESS_REG_TPD_IDX_Q(tx_ring->idx));
-+ idx >>= IPQESS_TPD_CONS_IDX_SHIFT; /* need u32 here */
-+ idx &= 0xffff;
-+ tx_ring->head = idx;
-+ tx_ring->tail = idx;
-+
-+ ipqess_m32(ess, IPQESS_TPD_PROD_IDX_MASK << IPQESS_TPD_PROD_IDX_SHIFT,
-+ idx, IPQESS_REG_TPD_IDX_Q(tx_ring->idx));
-+ ipqess_w32(ess, IPQESS_REG_TX_SW_CONS_IDX_Q(tx_ring->idx), idx);
-+ ipqess_w32(ess, IPQESS_REG_TPD_RING_SIZE, IPQESS_TX_RING_SIZE);
-+ }
-+
-+ return 0;
-+}
-+
-+static int ipqess_tx_unmap_and_free(struct device *dev, struct ipqess_buf *buf)
-+{
-+ int len = 0;
-+
-+ if (buf->flags & IPQESS_DESC_SINGLE)
-+ dma_unmap_single(dev, buf->dma, buf->length, DMA_TO_DEVICE);
-+ else if (buf->flags & IPQESS_DESC_PAGE)
-+ dma_unmap_page(dev, buf->dma, buf->length, DMA_TO_DEVICE);
-+
-+ if (buf->flags & IPQESS_DESC_LAST) {
-+ len = buf->skb->len;
-+ dev_kfree_skb_any(buf->skb);
-+ }
-+
-+ buf->flags = 0;
-+
-+ return len;
-+}
-+
-+static void ipqess_tx_ring_free(struct ipqess *ess)
-+{
-+ int i;
-+
-+ for (i = 0; i < IPQESS_NETDEV_QUEUES; i++) {
-+ int j;
-+
-+ if (ess->tx_ring[i].hw_desc)
-+ continue;
-+
-+ for (j = 0; j < IPQESS_TX_RING_SIZE; j++) {
-+ struct ipqess_buf *buf = &ess->tx_ring[i].buf[j];
-+
-+ ipqess_tx_unmap_and_free(&ess->pdev->dev, buf);
-+ }
-+
-+ ess->tx_ring[i].buf = NULL;
-+ }
-+}
-+
-+static int ipqess_rx_buf_prepare(struct ipqess_buf *buf,
-+ struct ipqess_rx_ring *rx_ring)
-+{
-+ memset(buf->skb->data, 0, sizeof(struct ipqess_rx_desc));
-+
-+ buf->dma = dma_map_single(rx_ring->ppdev, buf->skb->data,
-+ IPQESS_RX_HEAD_BUFF_SIZE, DMA_FROM_DEVICE);
-+ if (dma_mapping_error(rx_ring->ppdev, buf->dma)) {
-+ dev_kfree_skb_any(buf->skb);
-+ buf->skb = NULL;
-+ return -EFAULT;
-+ }
-+
-+ buf->length = IPQESS_RX_HEAD_BUFF_SIZE;
-+ rx_ring->hw_desc[rx_ring->head] = (struct ipqess_rx_desc *)buf->dma;
-+ rx_ring->head = (rx_ring->head + 1) % IPQESS_RX_RING_SIZE;
-+
-+ ipqess_m32(rx_ring->ess, IPQESS_RFD_PROD_IDX_BITS,
-+ (rx_ring->head + IPQESS_RX_RING_SIZE - 1) % IPQESS_RX_RING_SIZE,
-+ IPQESS_REG_RFD_IDX_Q(rx_ring->idx));
-+
-+ return 0;
-+}
-+
-+/* locking is handled by the caller */
-+static int ipqess_rx_buf_alloc_napi(struct ipqess_rx_ring *rx_ring)
-+{
-+ struct ipqess_buf *buf = &rx_ring->buf[rx_ring->head];
-+
-+ buf->skb = napi_alloc_skb(&rx_ring->napi_rx, IPQESS_RX_HEAD_BUFF_SIZE);
-+ if (!buf->skb)
-+ return -ENOMEM;
-+
-+ return ipqess_rx_buf_prepare(buf, rx_ring);
-+}
-+
-+static int ipqess_rx_buf_alloc(struct ipqess_rx_ring *rx_ring)
-+{
-+ struct ipqess_buf *buf = &rx_ring->buf[rx_ring->head];
-+
-+ buf->skb = netdev_alloc_skb_ip_align(rx_ring->ess->netdev,
-+ IPQESS_RX_HEAD_BUFF_SIZE);
-+
-+ if (!buf->skb)
-+ return -ENOMEM;
-+
-+ return ipqess_rx_buf_prepare(buf, rx_ring);
-+}
-+
-+static void ipqess_refill_work(struct work_struct *work)
-+{
-+ struct ipqess_rx_ring_refill *rx_refill = container_of(work,
-+ struct ipqess_rx_ring_refill, refill_work);
-+ struct ipqess_rx_ring *rx_ring = rx_refill->rx_ring;
-+ int refill = 0;
-+
-+ /* don't let this loop by accident. */
-+ while (atomic_dec_and_test(&rx_ring->refill_count)) {
-+ napi_disable(&rx_ring->napi_rx);
-+ if (ipqess_rx_buf_alloc(rx_ring)) {
-+ refill++;
-+ dev_dbg(rx_ring->ppdev,
-+ "Not all buffers were reallocated");
-+ }
-+ napi_enable(&rx_ring->napi_rx);
-+ }
-+
-+ if (atomic_add_return(refill, &rx_ring->refill_count))
-+ schedule_work(&rx_refill->refill_work);
-+}
-+
-+static int ipqess_rx_ring_alloc(struct ipqess *ess)
-+{
-+ int i;
-+
-+ for (i = 0; i < IPQESS_NETDEV_QUEUES; i++) {
-+ int j;
-+
-+ ess->rx_ring[i].ess = ess;
-+ ess->rx_ring[i].ppdev = &ess->pdev->dev;
-+ ess->rx_ring[i].ring_id = i;
-+ ess->rx_ring[i].idx = i * 2;
-+
-+ ess->rx_ring[i].buf = devm_kzalloc(&ess->pdev->dev,
-+ sizeof(struct ipqess_buf) * IPQESS_RX_RING_SIZE,
-+ GFP_KERNEL);
-+
-+ if (!ess->rx_ring[i].buf)
-+ return -ENOMEM;
-+
-+ ess->rx_ring[i].hw_desc =
-+ dmam_alloc_coherent(&ess->pdev->dev,
-+ sizeof(struct ipqess_rx_desc) * IPQESS_RX_RING_SIZE,
-+ &ess->rx_ring[i].dma, GFP_KERNEL);
-+
-+ if (!ess->rx_ring[i].hw_desc)
-+ return -ENOMEM;
-+
-+ for (j = 0; j < IPQESS_RX_RING_SIZE; j++)
-+ if (ipqess_rx_buf_alloc(&ess->rx_ring[i]) < 0)
-+ return -ENOMEM;
-+
-+ ess->rx_refill[i].rx_ring = &ess->rx_ring[i];
-+ INIT_WORK(&ess->rx_refill[i].refill_work, ipqess_refill_work);
-+
-+ ipqess_w32(ess, IPQESS_REG_RFD_BASE_ADDR_Q(ess->rx_ring[i].idx),
-+ (u32)(ess->rx_ring[i].dma));
-+ }
-+
-+ ipqess_w32(ess, IPQESS_REG_RX_DESC0,
-+ (IPQESS_RX_HEAD_BUFF_SIZE << IPQESS_RX_BUF_SIZE_SHIFT) |
-+ (IPQESS_RX_RING_SIZE << IPQESS_RFD_RING_SIZE_SHIFT));
-+
-+ return 0;
-+}
-+
-+static void ipqess_rx_ring_free(struct ipqess *ess)
-+{
-+ int i;
-+
-+ for (i = 0; i < IPQESS_NETDEV_QUEUES; i++) {
-+ int j;
-+
-+ cancel_work_sync(&ess->rx_refill[i].refill_work);
-+ atomic_set(&ess->rx_ring[i].refill_count, 0);
-+
-+ for (j = 0; j < IPQESS_RX_RING_SIZE; j++) {
-+ dma_unmap_single(&ess->pdev->dev,
-+ ess->rx_ring[i].buf[j].dma,
-+ ess->rx_ring[i].buf[j].length,
-+ DMA_FROM_DEVICE);
-+ dev_kfree_skb_any(ess->rx_ring[i].buf[j].skb);
-+ }
-+ }
-+}
-+
-+static struct net_device_stats *ipqess_get_stats(struct net_device *netdev)
-+{
-+ struct ipqess *ess = netdev_priv(netdev);
-+
-+ spin_lock(&ess->stats_lock);
-+ ipqess_update_hw_stats(ess);
-+ spin_unlock(&ess->stats_lock);
-+
-+ return &ess->stats;
-+}
-+
-+static int ipqess_rx_poll(struct ipqess_rx_ring *rx_ring, int budget)
-+{
-+ u32 length = 0, num_desc, tail, rx_ring_tail;
-+ int done = 0;
-+
-+ rx_ring_tail = rx_ring->tail;
-+
-+ tail = ipqess_r32(rx_ring->ess, IPQESS_REG_RFD_IDX_Q(rx_ring->idx));
-+ tail >>= IPQESS_RFD_CONS_IDX_SHIFT;
-+ tail &= IPQESS_RFD_CONS_IDX_MASK;
-+
-+ while (done < budget) {
-+ struct ipqess_rx_desc *rd;
-+ struct sk_buff *skb;
-+
-+ if (rx_ring_tail == tail)
-+ break;
-+
-+ dma_unmap_single(rx_ring->ppdev,
-+ rx_ring->buf[rx_ring_tail].dma,
-+ rx_ring->buf[rx_ring_tail].length,
-+ DMA_FROM_DEVICE);
-+
-+ skb = xchg(&rx_ring->buf[rx_ring_tail].skb, NULL);
-+ rd = (struct ipqess_rx_desc *)skb->data;
-+ rx_ring_tail = IPQESS_NEXT_IDX(rx_ring_tail, IPQESS_RX_RING_SIZE);
-+
-+ /* Check if RRD is valid */
-+ if (!(rd->rrd7 & cpu_to_le16(IPQESS_RRD_DESC_VALID))) {
-+ num_desc = 1;
-+ dev_kfree_skb_any(skb);
-+ goto skip;
-+ }
-+
-+ num_desc = le16_to_cpu(rd->rrd1) & IPQESS_RRD_NUM_RFD_MASK;
-+ length = le16_to_cpu(rd->rrd6) & IPQESS_RRD_PKT_SIZE_MASK;
-+
-+ skb_reserve(skb, IPQESS_RRD_SIZE);
-+ if (num_desc > 1) {
-+ struct sk_buff *skb_prev = NULL;
-+ int size_remaining;
-+ int i;
-+
-+ skb->data_len = 0;
-+ skb->tail += (IPQESS_RX_HEAD_BUFF_SIZE - IPQESS_RRD_SIZE);
-+ skb->len = length;
-+ skb->truesize = length;
-+ size_remaining = length - (IPQESS_RX_HEAD_BUFF_SIZE - IPQESS_RRD_SIZE);
-+
-+ for (i = 1; i < num_desc; i++) {
-+ struct sk_buff *skb_temp = rx_ring->buf[rx_ring_tail].skb;
-+
-+ dma_unmap_single(rx_ring->ppdev,
-+ rx_ring->buf[rx_ring_tail].dma,
-+ rx_ring->buf[rx_ring_tail].length,
-+ DMA_FROM_DEVICE);
-+
-+ skb_put(skb_temp, min(size_remaining, IPQESS_RX_HEAD_BUFF_SIZE));
-+ if (skb_prev)
-+ skb_prev->next = rx_ring->buf[rx_ring_tail].skb;
-+ else
-+ skb_shinfo(skb)->frag_list = rx_ring->buf[rx_ring_tail].skb;
-+ skb_prev = rx_ring->buf[rx_ring_tail].skb;
-+ rx_ring->buf[rx_ring_tail].skb->next = NULL;
-+
-+ skb->data_len += rx_ring->buf[rx_ring_tail].skb->len;
-+ size_remaining -= rx_ring->buf[rx_ring_tail].skb->len;
-+
-+ rx_ring_tail = IPQESS_NEXT_IDX(rx_ring_tail, IPQESS_RX_RING_SIZE);
-+ }
-+
-+ } else {
-+ skb_put(skb, length);
-+ }
-+
-+ skb->dev = rx_ring->ess->netdev;
-+ skb->protocol = eth_type_trans(skb, rx_ring->ess->netdev);
-+ skb_record_rx_queue(skb, rx_ring->ring_id);
-+
-+ if (rd->rrd6 & cpu_to_le16(IPQESS_RRD_CSUM_FAIL_MASK))
-+ skb_checksum_none_assert(skb);
-+ else
-+ skb->ip_summed = CHECKSUM_UNNECESSARY;
-+
-+ if (rd->rrd7 & cpu_to_le16(IPQESS_RRD_CVLAN))
-+ __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
-+ le16_to_cpu(rd->rrd4));
-+ else if (rd->rrd1 & cpu_to_le16(IPQESS_RRD_SVLAN))
-+ __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021AD),
-+ le16_to_cpu(rd->rrd4));
-+
-+ napi_gro_receive(&rx_ring->napi_rx, skb);
-+
-+ rx_ring->ess->stats.rx_packets++;
-+ rx_ring->ess->stats.rx_bytes += length;
-+
-+ done++;
-+skip:
-+
-+ num_desc += atomic_xchg(&rx_ring->refill_count, 0);
-+ while (num_desc) {
-+ if (ipqess_rx_buf_alloc_napi(rx_ring)) {
-+ num_desc = atomic_add_return(num_desc,
-+ &rx_ring->refill_count);
-+ if (num_desc >= DIV_ROUND_UP(IPQESS_RX_RING_SIZE * 4, 7))
-+ schedule_work(&rx_ring->ess->rx_refill[rx_ring->ring_id].refill_work);
-+ break;
-+ }
-+ num_desc--;
-+ }
-+ }
-+
-+ ipqess_w32(rx_ring->ess, IPQESS_REG_RX_SW_CONS_IDX_Q(rx_ring->idx),
-+ rx_ring_tail);
-+ rx_ring->tail = rx_ring_tail;
-+
-+ return done;
-+}
-+
-+static int ipqess_tx_complete(struct ipqess_tx_ring *tx_ring, int budget)
-+{
-+ int total = 0, ret;
-+ int done = 0;
-+ u32 tail;
-+
-+ tail = ipqess_r32(tx_ring->ess, IPQESS_REG_TPD_IDX_Q(tx_ring->idx));
-+ tail >>= IPQESS_TPD_CONS_IDX_SHIFT;
-+ tail &= IPQESS_TPD_CONS_IDX_MASK;
-+
-+ do {
-+ ret = ipqess_tx_unmap_and_free(&tx_ring->ess->pdev->dev,
-+ &tx_ring->buf[tx_ring->tail]);
-+ tx_ring->tail = IPQESS_NEXT_IDX(tx_ring->tail, tx_ring->count);
-+
-+ total += ret;
-+ } while ((++done < budget) && (tx_ring->tail != tail));
-+
-+ ipqess_w32(tx_ring->ess, IPQESS_REG_TX_SW_CONS_IDX_Q(tx_ring->idx),
-+ tx_ring->tail);
-+
-+ if (netif_tx_queue_stopped(tx_ring->nq)) {
-+ netdev_dbg(tx_ring->ess->netdev, "waking up tx queue %d\n",
-+ tx_ring->idx);
-+ netif_tx_wake_queue(tx_ring->nq);
-+ }
-+
-+ netdev_tx_completed_queue(tx_ring->nq, done, total);
-+
-+ return done;
-+}
-+
-+static int ipqess_tx_napi(struct napi_struct *napi, int budget)
-+{
-+ struct ipqess_tx_ring *tx_ring = container_of(napi, struct ipqess_tx_ring,
-+ napi_tx);
-+ int work_done = 0;
-+ u32 tx_status;
-+
-+ tx_status = ipqess_r32(tx_ring->ess, IPQESS_REG_TX_ISR);
-+ tx_status &= BIT(tx_ring->idx);
-+
-+ work_done = ipqess_tx_complete(tx_ring, budget);
-+
-+ ipqess_w32(tx_ring->ess, IPQESS_REG_TX_ISR, tx_status);
-+
-+ if (likely(work_done < budget)) {
-+ if (napi_complete_done(napi, work_done))
-+ ipqess_w32(tx_ring->ess,
-+ IPQESS_REG_TX_INT_MASK_Q(tx_ring->idx), 0x1);
-+ }
-+
-+ return work_done;
-+}
-+
-+static int ipqess_rx_napi(struct napi_struct *napi, int budget)
-+{
-+ struct ipqess_rx_ring *rx_ring = container_of(napi, struct ipqess_rx_ring,
-+ napi_rx);
-+ struct ipqess *ess = rx_ring->ess;
-+ u32 rx_mask = BIT(rx_ring->idx);
-+ int remaining_budget = budget;
-+ int rx_done;
-+ u32 status;
-+
-+ do {
-+ ipqess_w32(ess, IPQESS_REG_RX_ISR, rx_mask);
-+ rx_done = ipqess_rx_poll(rx_ring, remaining_budget);
-+ remaining_budget -= rx_done;
-+
-+ status = ipqess_r32(ess, IPQESS_REG_RX_ISR);
-+ } while (remaining_budget > 0 && (status & rx_mask));
-+
-+ if (remaining_budget <= 0)
-+ return budget;
-+
-+ if (napi_complete_done(napi, budget - remaining_budget))
-+ ipqess_w32(ess, IPQESS_REG_RX_INT_MASK_Q(rx_ring->idx), 0x1);
-+
-+ return budget - remaining_budget;
-+}
-+
-+static irqreturn_t ipqess_interrupt_tx(int irq, void *priv)
-+{
-+ struct ipqess_tx_ring *tx_ring = (struct ipqess_tx_ring *)priv;
-+
-+ if (likely(napi_schedule_prep(&tx_ring->napi_tx))) {
-+ __napi_schedule(&tx_ring->napi_tx);
-+ ipqess_w32(tx_ring->ess, IPQESS_REG_TX_INT_MASK_Q(tx_ring->idx),
-+ 0x0);
-+ }
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static irqreturn_t ipqess_interrupt_rx(int irq, void *priv)
-+{
-+ struct ipqess_rx_ring *rx_ring = (struct ipqess_rx_ring *)priv;
-+
-+ if (likely(napi_schedule_prep(&rx_ring->napi_rx))) {
-+ __napi_schedule(&rx_ring->napi_rx);
-+ ipqess_w32(rx_ring->ess, IPQESS_REG_RX_INT_MASK_Q(rx_ring->idx),
-+ 0x0);
-+ }
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static void ipqess_irq_enable(struct ipqess *ess)
-+{
-+ int i;
-+
-+ ipqess_w32(ess, IPQESS_REG_RX_ISR, 0xff);
-+ ipqess_w32(ess, IPQESS_REG_TX_ISR, 0xffff);
-+ for (i = 0; i < IPQESS_NETDEV_QUEUES; i++) {
-+ ipqess_w32(ess, IPQESS_REG_RX_INT_MASK_Q(ess->rx_ring[i].idx), 1);
-+ ipqess_w32(ess, IPQESS_REG_TX_INT_MASK_Q(ess->tx_ring[i].idx), 1);
-+ }
-+}
-+
-+static void ipqess_irq_disable(struct ipqess *ess)
-+{
-+ int i;
-+
-+ for (i = 0; i < IPQESS_NETDEV_QUEUES; i++) {
-+ ipqess_w32(ess, IPQESS_REG_RX_INT_MASK_Q(ess->rx_ring[i].idx), 0);
-+ ipqess_w32(ess, IPQESS_REG_TX_INT_MASK_Q(ess->tx_ring[i].idx), 0);
-+ }
-+}
-+
-+static int __init ipqess_init(struct net_device *netdev)
-+{
-+ struct ipqess *ess = netdev_priv(netdev);
-+ struct device_node *of_node = ess->pdev->dev.of_node;
-+ int ret;
-+
-+ ret = of_get_ethdev_address(of_node, netdev);
-+ if (ret)
-+ eth_hw_addr_random(netdev);
-+
-+ return phylink_of_phy_connect(ess->phylink, of_node, 0);
-+}
-+
-+static void ipqess_uninit(struct net_device *netdev)
-+{
-+ struct ipqess *ess = netdev_priv(netdev);
-+
-+ phylink_disconnect_phy(ess->phylink);
-+}
-+
-+static int ipqess_open(struct net_device *netdev)
-+{
-+ struct ipqess *ess = netdev_priv(netdev);
-+ int i, err;
-+
-+ for (i = 0; i < IPQESS_NETDEV_QUEUES; i++) {
-+ int qid;
-+
-+ qid = ess->tx_ring[i].idx;
-+ err = devm_request_irq(&netdev->dev, ess->tx_irq[qid],
-+ ipqess_interrupt_tx, 0,
-+ ess->tx_irq_names[qid],
-+ &ess->tx_ring[i]);
-+ if (err)
-+ return err;
-+
-+ qid = ess->rx_ring[i].idx;
-+ err = devm_request_irq(&netdev->dev, ess->rx_irq[qid],
-+ ipqess_interrupt_rx, 0,
-+ ess->rx_irq_names[qid],
-+ &ess->rx_ring[i]);
-+ if (err)
-+ return err;
-+
-+ napi_enable(&ess->tx_ring[i].napi_tx);
-+ napi_enable(&ess->rx_ring[i].napi_rx);
-+ }
-+
-+ ipqess_irq_enable(ess);
-+ phylink_start(ess->phylink);
-+ netif_tx_start_all_queues(netdev);
-+
-+ return 0;
-+}
-+
-+static int ipqess_stop(struct net_device *netdev)
-+{
-+ struct ipqess *ess = netdev_priv(netdev);
-+ int i;
-+
-+ netif_tx_stop_all_queues(netdev);
-+ phylink_stop(ess->phylink);
-+ ipqess_irq_disable(ess);
-+ for (i = 0; i < IPQESS_NETDEV_QUEUES; i++) {
-+ napi_disable(&ess->tx_ring[i].napi_tx);
-+ napi_disable(&ess->rx_ring[i].napi_rx);
-+ }
-+
-+ return 0;
-+}
-+
-+static int ipqess_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
-+{
-+ struct ipqess *ess = netdev_priv(netdev);
-+
-+ return phylink_mii_ioctl(ess->phylink, ifr, cmd);
-+}
-+
-+static u16 ipqess_tx_desc_available(struct ipqess_tx_ring *tx_ring)
-+{
-+ u16 count = 0;
-+
-+ if (tx_ring->tail <= tx_ring->head)
-+ count = IPQESS_TX_RING_SIZE;
-+
-+ count += tx_ring->tail - tx_ring->head - 1;
-+
-+ return count;
-+}
-+
-+static int ipqess_cal_txd_req(struct sk_buff *skb)
-+{
-+ int tpds;
-+
-+ /* one TPD for the header, and one for each fragments */
-+ tpds = 1 + skb_shinfo(skb)->nr_frags;
-+ if (skb_is_gso(skb) && skb_is_gso_v6(skb)) {
-+ /* for LSOv2 one extra TPD is needed */
-+ tpds++;
-+ }
-+
-+ return tpds;
-+}
-+
-+static struct ipqess_buf *ipqess_get_tx_buffer(struct ipqess_tx_ring *tx_ring,
-+ struct ipqess_tx_desc *desc)
-+{
-+ return &tx_ring->buf[desc - tx_ring->hw_desc];
-+}
-+
-+static struct ipqess_tx_desc *ipqess_tx_desc_next(struct ipqess_tx_ring *tx_ring)
-+{
-+ struct ipqess_tx_desc *desc;
-+
-+ desc = &tx_ring->hw_desc[tx_ring->head];
-+ tx_ring->head = IPQESS_NEXT_IDX(tx_ring->head, tx_ring->count);
-+
-+ return desc;
-+}
-+
-+static void ipqess_rollback_tx(struct ipqess *eth,
-+ struct ipqess_tx_desc *first_desc, int ring_id)
-+{
-+ struct ipqess_tx_ring *tx_ring = ð->tx_ring[ring_id];
-+ struct ipqess_tx_desc *desc = NULL;
-+ struct ipqess_buf *buf;
-+ u16 start_index, index;
-+
-+ start_index = first_desc - tx_ring->hw_desc;
-+
-+ index = start_index;
-+ while (index != tx_ring->head) {
-+ desc = &tx_ring->hw_desc[index];
-+ buf = &tx_ring->buf[index];
-+ ipqess_tx_unmap_and_free(ð->pdev->dev, buf);
-+ memset(desc, 0, sizeof(*desc));
-+ if (++index == tx_ring->count)
-+ index = 0;
-+ }
-+ tx_ring->head = start_index;
-+}
-+
-+static int ipqess_tx_map_and_fill(struct ipqess_tx_ring *tx_ring,
-+ struct sk_buff *skb)
-+{
-+ struct ipqess_tx_desc *desc = NULL, *first_desc = NULL;
-+ u32 word1 = 0, word3 = 0, lso_word1 = 0, svlan_tag = 0;
-+ struct platform_device *pdev = tx_ring->ess->pdev;
-+ struct ipqess_buf *buf = NULL;
-+ u16 len;
-+ int i;
-+
-+ if (skb_is_gso(skb)) {
-+ if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4) {
-+ lso_word1 |= IPQESS_TPD_IPV4_EN;
-+ ip_hdr(skb)->check = 0;
-+ tcp_hdr(skb)->check = ~csum_tcpudp_magic(ip_hdr(skb)->saddr,
-+ ip_hdr(skb)->daddr,
-+ 0, IPPROTO_TCP, 0);
-+ } else if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
-+ lso_word1 |= IPQESS_TPD_LSO_V2_EN;
-+ ipv6_hdr(skb)->payload_len = 0;
-+ tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
-+ &ipv6_hdr(skb)->daddr,
-+ 0, IPPROTO_TCP, 0);
-+ }
-+
-+ lso_word1 |= IPQESS_TPD_LSO_EN |
-+ ((skb_shinfo(skb)->gso_size & IPQESS_TPD_MSS_MASK) <<
-+ IPQESS_TPD_MSS_SHIFT) |
-+ (skb_transport_offset(skb) << IPQESS_TPD_HDR_SHIFT);
-+ } else if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
-+ u8 css, cso;
-+
-+ cso = skb_checksum_start_offset(skb);
-+ css = cso + skb->csum_offset;
-+
-+ word1 |= (IPQESS_TPD_CUSTOM_CSUM_EN);
-+ word1 |= (cso >> 1) << IPQESS_TPD_HDR_SHIFT;
-+ word1 |= ((css >> 1) << IPQESS_TPD_CUSTOM_CSUM_SHIFT);
-+ }
-+
-+ if (skb_vlan_tag_present(skb)) {
-+ switch (skb->vlan_proto) {
-+ case htons(ETH_P_8021Q):
-+ word3 |= BIT(IPQESS_TX_INS_CVLAN);
-+ word3 |= skb_vlan_tag_get(skb) << IPQESS_TX_CVLAN_TAG_SHIFT;
-+ break;
-+ case htons(ETH_P_8021AD):
-+ word1 |= BIT(IPQESS_TX_INS_SVLAN);
-+ svlan_tag = skb_vlan_tag_get(skb);
-+ break;
-+ default:
-+ dev_err(&pdev->dev, "no ctag or stag present\n");
-+ goto vlan_tag_error;
-+ }
-+ }
-+
-+ if (eth_type_vlan(skb->protocol))
-+ word1 |= IPQESS_TPD_VLAN_TAGGED;
-+
-+ if (skb->protocol == htons(ETH_P_PPP_SES))
-+ word1 |= IPQESS_TPD_PPPOE_EN;
-+
-+ len = skb_headlen(skb);
-+
-+ first_desc = ipqess_tx_desc_next(tx_ring);
-+ desc = first_desc;
-+ if (lso_word1 & IPQESS_TPD_LSO_V2_EN) {
-+ desc->addr = cpu_to_le32(skb->len);
-+ desc->word1 = cpu_to_le32(word1 | lso_word1);
-+ desc->svlan_tag = cpu_to_le16(svlan_tag);
-+ desc->word3 = cpu_to_le32(word3);
-+ desc = ipqess_tx_desc_next(tx_ring);
-+ }
-+
-+ buf = ipqess_get_tx_buffer(tx_ring, desc);
-+ buf->length = len;
-+ buf->dma = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
-+
-+ if (dma_mapping_error(&pdev->dev, buf->dma))
-+ goto dma_error;
-+
-+ desc->addr = cpu_to_le32(buf->dma);
-+ desc->len = cpu_to_le16(len);
-+
-+ buf->flags |= IPQESS_DESC_SINGLE;
-+ desc->word1 = cpu_to_le32(word1 | lso_word1);
-+ desc->svlan_tag = cpu_to_le16(svlan_tag);
-+ desc->word3 = cpu_to_le32(word3);
-+
-+ for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
-+ skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
-+
-+ len = skb_frag_size(frag);
-+ desc = ipqess_tx_desc_next(tx_ring);
-+ buf = ipqess_get_tx_buffer(tx_ring, desc);
-+ buf->length = len;
-+ buf->flags |= IPQESS_DESC_PAGE;
-+ buf->dma = skb_frag_dma_map(&pdev->dev, frag, 0, len,
-+ DMA_TO_DEVICE);
-+
-+ if (dma_mapping_error(&pdev->dev, buf->dma))
-+ goto dma_error;
-+
-+ desc->addr = cpu_to_le32(buf->dma);
-+ desc->len = cpu_to_le16(len);
-+ desc->svlan_tag = cpu_to_le16(svlan_tag);
-+ desc->word1 = cpu_to_le32(word1 | lso_word1);
-+ desc->word3 = cpu_to_le32(word3);
-+ }
-+ desc->word1 |= cpu_to_le32(1 << IPQESS_TPD_EOP_SHIFT);
-+ buf->skb = skb;
-+ buf->flags |= IPQESS_DESC_LAST;
-+
-+ return 0;
-+
-+dma_error:
-+ ipqess_rollback_tx(tx_ring->ess, first_desc, tx_ring->ring_id);
-+ dev_err(&pdev->dev, "TX DMA map failed\n");
-+
-+vlan_tag_error:
-+ return -ENOMEM;
-+}
-+
-+static void ipqess_kick_tx(struct ipqess_tx_ring *tx_ring)
-+{
-+ /* Ensure that all TPDs has been written completely */
-+ dma_wmb();
-+
-+ /* update software producer index */
-+ ipqess_w32(tx_ring->ess, IPQESS_REG_TPD_IDX_Q(tx_ring->idx),
-+ tx_ring->head);
-+}
-+
-+static netdev_tx_t ipqess_xmit(struct sk_buff *skb, struct net_device *netdev)
-+{
-+ struct ipqess *ess = netdev_priv(netdev);
-+ struct ipqess_tx_ring *tx_ring;
-+ int avail;
-+ int tx_num;
-+ int ret;
-+
-+ tx_ring = &ess->tx_ring[skb_get_queue_mapping(skb)];
-+ tx_num = ipqess_cal_txd_req(skb);
-+ avail = ipqess_tx_desc_available(tx_ring);
-+ if (avail < tx_num) {
-+ netdev_dbg(netdev,
-+ "stopping tx queue %d, avail=%d req=%d im=%x\n",
-+ tx_ring->idx, avail, tx_num,
-+ ipqess_r32(tx_ring->ess,
-+ IPQESS_REG_TX_INT_MASK_Q(tx_ring->idx)));
-+ netif_tx_stop_queue(tx_ring->nq);
-+ ipqess_w32(tx_ring->ess, IPQESS_REG_TX_INT_MASK_Q(tx_ring->idx), 0x1);
-+ ipqess_kick_tx(tx_ring);
-+ return NETDEV_TX_BUSY;
-+ }
-+
-+ ret = ipqess_tx_map_and_fill(tx_ring, skb);
-+ if (ret) {
-+ dev_kfree_skb_any(skb);
-+ ess->stats.tx_errors++;
-+ goto err_out;
-+ }
-+
-+ ess->stats.tx_packets++;
-+ ess->stats.tx_bytes += skb->len;
-+ netdev_tx_sent_queue(tx_ring->nq, skb->len);
-+
-+ if (!netdev_xmit_more() || netif_xmit_stopped(tx_ring->nq))
-+ ipqess_kick_tx(tx_ring);
-+
-+err_out:
-+ return NETDEV_TX_OK;
-+}
-+
-+static int ipqess_set_mac_address(struct net_device *netdev, void *p)
-+{
-+ struct ipqess *ess = netdev_priv(netdev);
-+ const char *macaddr = netdev->dev_addr;
-+ int ret = eth_mac_addr(netdev, p);
-+
-+ if (ret)
-+ return ret;
-+
-+ ipqess_w32(ess, IPQESS_REG_MAC_CTRL1, (macaddr[0] << 8) | macaddr[1]);
-+ ipqess_w32(ess, IPQESS_REG_MAC_CTRL0,
-+ (macaddr[2] << 24) | (macaddr[3] << 16) | (macaddr[4] << 8) |
-+ macaddr[5]);
-+
-+ return 0;
-+}
-+
-+static void ipqess_tx_timeout(struct net_device *netdev, unsigned int txq_id)
-+{
-+ struct ipqess *ess = netdev_priv(netdev);
-+ struct ipqess_tx_ring *tr = &ess->tx_ring[txq_id];
-+
-+ netdev_warn(netdev, "TX timeout on queue %d\n", tr->idx);
-+}
-+
-+static const struct net_device_ops ipqess_axi_netdev_ops = {
-+ .ndo_init = ipqess_init,
-+ .ndo_uninit = ipqess_uninit,
-+ .ndo_open = ipqess_open,
-+ .ndo_stop = ipqess_stop,
-+ .ndo_do_ioctl = ipqess_do_ioctl,
-+ .ndo_start_xmit = ipqess_xmit,
-+ .ndo_get_stats = ipqess_get_stats,
-+ .ndo_set_mac_address = ipqess_set_mac_address,
-+ .ndo_tx_timeout = ipqess_tx_timeout,
-+};
-+
-+static void ipqess_hw_stop(struct ipqess *ess)
-+{
-+ int i;
-+
-+ /* disable all RX queue IRQs */
-+ for (i = 0; i < IPQESS_MAX_RX_QUEUE; i++)
-+ ipqess_w32(ess, IPQESS_REG_RX_INT_MASK_Q(i), 0);
-+
-+ /* disable all TX queue IRQs */
-+ for (i = 0; i < IPQESS_MAX_TX_QUEUE; i++)
-+ ipqess_w32(ess, IPQESS_REG_TX_INT_MASK_Q(i), 0);
-+
-+ /* disable all other IRQs */
-+ ipqess_w32(ess, IPQESS_REG_MISC_IMR, 0);
-+ ipqess_w32(ess, IPQESS_REG_WOL_IMR, 0);
-+
-+ /* clear the IRQ status registers */
-+ ipqess_w32(ess, IPQESS_REG_RX_ISR, 0xff);
-+ ipqess_w32(ess, IPQESS_REG_TX_ISR, 0xffff);
-+ ipqess_w32(ess, IPQESS_REG_MISC_ISR, 0x1fff);
-+ ipqess_w32(ess, IPQESS_REG_WOL_ISR, 0x1);
-+ ipqess_w32(ess, IPQESS_REG_WOL_CTRL, 0);
-+
-+ /* disable RX and TX queues */
-+ ipqess_m32(ess, IPQESS_RXQ_CTRL_EN_MASK, 0, IPQESS_REG_RXQ_CTRL);
-+ ipqess_m32(ess, IPQESS_TXQ_CTRL_TXQ_EN, 0, IPQESS_REG_TXQ_CTRL);
-+}
-+
-+static int ipqess_hw_init(struct ipqess *ess)
-+{
-+ int i, err;
-+ u32 tmp;
-+
-+ ipqess_hw_stop(ess);
-+
-+ ipqess_m32(ess, BIT(IPQESS_INTR_SW_IDX_W_TYP_SHIFT),
-+ IPQESS_INTR_SW_IDX_W_TYPE << IPQESS_INTR_SW_IDX_W_TYP_SHIFT,
-+ IPQESS_REG_INTR_CTRL);
-+
-+ /* enable IRQ delay slot */
-+ ipqess_w32(ess, IPQESS_REG_IRQ_MODRT_TIMER_INIT,
-+ (IPQESS_TX_IMT << IPQESS_IRQ_MODRT_TX_TIMER_SHIFT) |
-+ (IPQESS_RX_IMT << IPQESS_IRQ_MODRT_RX_TIMER_SHIFT));
-+
-+ /* Set Customer and Service VLAN TPIDs */
-+ ipqess_w32(ess, IPQESS_REG_VLAN_CFG,
-+ (ETH_P_8021Q << IPQESS_VLAN_CFG_CVLAN_TPID_SHIFT) |
-+ (ETH_P_8021AD << IPQESS_VLAN_CFG_SVLAN_TPID_SHIFT));
-+
-+ /* Configure the TX Queue bursting */
-+ ipqess_w32(ess, IPQESS_REG_TXQ_CTRL,
-+ (IPQESS_TPD_BURST << IPQESS_TXQ_NUM_TPD_BURST_SHIFT) |
-+ (IPQESS_TXF_BURST << IPQESS_TXQ_TXF_BURST_NUM_SHIFT) |
-+ IPQESS_TXQ_CTRL_TPD_BURST_EN);
-+
-+ /* Set RSS type */
-+ ipqess_w32(ess, IPQESS_REG_RSS_TYPE,
-+ IPQESS_RSS_TYPE_IPV4TCP | IPQESS_RSS_TYPE_IPV6_TCP |
-+ IPQESS_RSS_TYPE_IPV4_UDP | IPQESS_RSS_TYPE_IPV6UDP |
-+ IPQESS_RSS_TYPE_IPV4 | IPQESS_RSS_TYPE_IPV6);
-+
-+ /* Set RFD ring burst and threshold */
-+ ipqess_w32(ess, IPQESS_REG_RX_DESC1,
-+ (IPQESS_RFD_BURST << IPQESS_RXQ_RFD_BURST_NUM_SHIFT) |
-+ (IPQESS_RFD_THR << IPQESS_RXQ_RFD_PF_THRESH_SHIFT) |
-+ (IPQESS_RFD_LTHR << IPQESS_RXQ_RFD_LOW_THRESH_SHIFT));
-+
-+ /* Set Rx FIFO
-+ * - threshold to start to DMA data to host
-+ */
-+ ipqess_w32(ess, IPQESS_REG_RXQ_CTRL,
-+ IPQESS_FIFO_THRESH_128_BYTE | IPQESS_RXQ_CTRL_RMV_VLAN);
-+
-+ err = ipqess_rx_ring_alloc(ess);
-+ if (err)
-+ return err;
-+
-+ err = ipqess_tx_ring_alloc(ess);
-+ if (err)
-+ goto err_rx_ring_free;
-+
-+ /* Load all of ring base addresses above into the dma engine */
-+ ipqess_m32(ess, 0, BIT(IPQESS_LOAD_PTR_SHIFT), IPQESS_REG_TX_SRAM_PART);
-+
-+ /* Disable TX FIFO low watermark and high watermark */
-+ ipqess_w32(ess, IPQESS_REG_TXF_WATER_MARK, 0);
-+
-+ /* Configure RSS indirection table.
-+ * 128 hash will be configured in the following
-+ * pattern: hash{0,1,2,3} = {Q0,Q2,Q4,Q6} respectively
-+ * and so on
-+ */
-+ for (i = 0; i < IPQESS_NUM_IDT; i++)
-+ ipqess_w32(ess, IPQESS_REG_RSS_IDT(i), IPQESS_RSS_IDT_VALUE);
-+
-+ /* Configure load balance mapping table.
-+ * 4 table entry will be configured according to the
-+ * following pattern: load_balance{0,1,2,3} = {Q0,Q1,Q3,Q4}
-+ * respectively.
-+ */
-+ ipqess_w32(ess, IPQESS_REG_LB_RING, IPQESS_LB_REG_VALUE);
-+
-+ /* Configure Virtual queue for Tx rings */
-+ ipqess_w32(ess, IPQESS_REG_VQ_CTRL0, IPQESS_VQ_REG_VALUE);
-+ ipqess_w32(ess, IPQESS_REG_VQ_CTRL1, IPQESS_VQ_REG_VALUE);
-+
-+ /* Configure Max AXI Burst write size to 128 bytes*/
-+ ipqess_w32(ess, IPQESS_REG_AXIW_CTRL_MAXWRSIZE,
-+ IPQESS_AXIW_MAXWRSIZE_VALUE);
-+
-+ /* Enable TX queues */
-+ ipqess_m32(ess, 0, IPQESS_TXQ_CTRL_TXQ_EN, IPQESS_REG_TXQ_CTRL);
-+
-+ /* Enable RX queues */
-+ tmp = 0;
-+ for (i = 0; i < IPQESS_NETDEV_QUEUES; i++)
-+ tmp |= IPQESS_RXQ_CTRL_EN(ess->rx_ring[i].idx);
-+
-+ ipqess_m32(ess, IPQESS_RXQ_CTRL_EN_MASK, tmp, IPQESS_REG_RXQ_CTRL);
-+
-+ return 0;
-+
-+err_rx_ring_free:
-+
-+ ipqess_rx_ring_free(ess);
-+ return err;
-+}
-+
-+static void ipqess_mac_config(struct phylink_config *config, unsigned int mode,
-+ const struct phylink_link_state *state)
-+{
-+ /* Nothing to do, use fixed Internal mode */
-+}
-+
-+static void ipqess_mac_link_down(struct phylink_config *config,
-+ unsigned int mode,
-+ phy_interface_t interface)
-+{
-+ /* Nothing to do, use fixed Internal mode */
-+}
-+
-+static void ipqess_mac_link_up(struct phylink_config *config,
-+ struct phy_device *phy, unsigned int mode,
-+ phy_interface_t interface,
-+ int speed, int duplex,
-+ bool tx_pause, bool rx_pause)
-+{
-+ /* Nothing to do, use fixed Internal mode */
-+}
-+
-+static struct phylink_mac_ops ipqess_phylink_mac_ops = {
-+ .validate = phylink_generic_validate,
-+ .mac_config = ipqess_mac_config,
-+ .mac_link_up = ipqess_mac_link_up,
-+ .mac_link_down = ipqess_mac_link_down,
-+};
-+
-+static void ipqess_reset(struct ipqess *ess)
-+{
-+ reset_control_assert(ess->ess_rst);
-+
-+ mdelay(10);
-+
-+ reset_control_deassert(ess->ess_rst);
-+
-+ /* Waiting for all inner tables to be flushed and reinitialized.
-+ * This takes between 5 and 10 ms
-+ */
-+
-+ mdelay(10);
-+}
-+
-+static int ipqess_axi_probe(struct platform_device *pdev)
-+{
-+ struct device_node *np = pdev->dev.of_node;
-+ struct net_device *netdev;
-+ phy_interface_t phy_mode;
-+ struct ipqess *ess;
-+ int i, err = 0;
-+
-+ netdev = devm_alloc_etherdev_mqs(&pdev->dev, sizeof(*ess),
-+ IPQESS_NETDEV_QUEUES,
-+ IPQESS_NETDEV_QUEUES);
-+ if (!netdev)
-+ return -ENOMEM;
-+
-+ ess = netdev_priv(netdev);
-+ ess->netdev = netdev;
-+ ess->pdev = pdev;
-+ spin_lock_init(&ess->stats_lock);
-+ SET_NETDEV_DEV(netdev, &pdev->dev);
-+ platform_set_drvdata(pdev, netdev);
-+
-+ ess->hw_addr = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
-+ if (IS_ERR(ess->hw_addr))
-+ return PTR_ERR(ess->hw_addr);
-+
-+ err = of_get_phy_mode(np, &phy_mode);
-+ if (err) {
-+ dev_err(&pdev->dev, "incorrect phy-mode\n");
-+ return err;
-+ }
-+
-+ ess->ess_clk = devm_clk_get(&pdev->dev, NULL);
-+ if (!IS_ERR(ess->ess_clk))
-+ clk_prepare_enable(ess->ess_clk);
-+
-+ ess->ess_rst = devm_reset_control_get(&pdev->dev, NULL);
-+ if (IS_ERR(ess->ess_rst))
-+ goto err_clk;
-+
-+ ipqess_reset(ess);
-+
-+ ess->phylink_config.dev = &netdev->dev;
-+ ess->phylink_config.type = PHYLINK_NETDEV;
-+ ess->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_10 |
-+ MAC_100 | MAC_1000FD;
-+
-+ __set_bit(PHY_INTERFACE_MODE_INTERNAL,
-+ ess->phylink_config.supported_interfaces);
-+
-+ ess->phylink = phylink_create(&ess->phylink_config,
-+ of_fwnode_handle(np), phy_mode,
-+ &ipqess_phylink_mac_ops);
-+ if (IS_ERR(ess->phylink)) {
-+ err = PTR_ERR(ess->phylink);
-+ goto err_clk;
-+ }
-+
-+ for (i = 0; i < IPQESS_MAX_TX_QUEUE; i++) {
-+ ess->tx_irq[i] = platform_get_irq(pdev, i);
-+ scnprintf(ess->tx_irq_names[i], sizeof(ess->tx_irq_names[i]),
-+ "%s:txq%d", pdev->name, i);
-+ }
-+
-+ for (i = 0; i < IPQESS_MAX_RX_QUEUE; i++) {
-+ ess->rx_irq[i] = platform_get_irq(pdev, i + IPQESS_MAX_TX_QUEUE);
-+ scnprintf(ess->rx_irq_names[i], sizeof(ess->rx_irq_names[i]),
-+ "%s:rxq%d", pdev->name, i);
-+ }
-+
-+ netdev->netdev_ops = &ipqess_axi_netdev_ops;
-+ netdev->features = NETIF_F_HW_CSUM | NETIF_F_RXCSUM |
-+ NETIF_F_HW_VLAN_CTAG_RX |
-+ NETIF_F_HW_VLAN_CTAG_TX |
-+ NETIF_F_TSO | NETIF_F_GRO | NETIF_F_SG;
-+ /* feature change is not supported yet */
-+ netdev->hw_features = 0;
-+ netdev->vlan_features = NETIF_F_HW_CSUM | NETIF_F_SG | NETIF_F_RXCSUM |
-+ NETIF_F_TSO |
-+ NETIF_F_GRO;
-+ netdev->watchdog_timeo = 5 * HZ;
-+ netdev->base_addr = (u32)ess->hw_addr;
-+ netdev->max_mtu = 9000;
-+ netdev->gso_max_segs = IPQESS_TX_RING_SIZE / 2;
-+
-+ ipqess_set_ethtool_ops(netdev);
-+
-+ err = ipqess_hw_init(ess);
-+ if (err)
-+ goto err_phylink;
-+
-+ for (i = 0; i < IPQESS_NETDEV_QUEUES; i++) {
-+ netif_napi_add_tx(netdev, &ess->tx_ring[i].napi_tx, ipqess_tx_napi);
-+ netif_napi_add(netdev, &ess->rx_ring[i].napi_rx, ipqess_rx_napi);
-+ }
-+
-+ err = register_netdev(netdev);
-+ if (err)
-+ goto err_hw_stop;
-+
-+ return 0;
-+
-+err_hw_stop:
-+ ipqess_hw_stop(ess);
-+
-+ ipqess_tx_ring_free(ess);
-+ ipqess_rx_ring_free(ess);
-+err_phylink:
-+ phylink_destroy(ess->phylink);
-+
-+err_clk:
-+ clk_disable_unprepare(ess->ess_clk);
-+
-+ return err;
-+}
-+
-+static int ipqess_axi_remove(struct platform_device *pdev)
-+{
-+ const struct net_device *netdev = platform_get_drvdata(pdev);
-+ struct ipqess *ess = netdev_priv(netdev);
-+
-+ unregister_netdev(ess->netdev);
-+ ipqess_hw_stop(ess);
-+
-+ ipqess_tx_ring_free(ess);
-+ ipqess_rx_ring_free(ess);
-+
-+ phylink_destroy(ess->phylink);
-+ clk_disable_unprepare(ess->ess_clk);
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id ipqess_of_mtable[] = {
-+ {.compatible = "qcom,ipq4019-ess-edma" },
-+ {}
-+};
-+MODULE_DEVICE_TABLE(of, ipqess_of_mtable);
-+
-+static struct platform_driver ipqess_axi_driver = {
-+ .driver = {
-+ .name = "ipqess-edma",
-+ .of_match_table = ipqess_of_mtable,
-+ },
-+ .probe = ipqess_axi_probe,
-+ .remove = ipqess_axi_remove,
-+};
-+
-+module_platform_driver(ipqess_axi_driver);
-+
-+MODULE_AUTHOR("Qualcomm Atheros Inc");
-+MODULE_AUTHOR("John Crispin <john@phrozen.org>");
-+MODULE_AUTHOR("Christian Lamparter <chunkeey@gmail.com>");
-+MODULE_AUTHOR("Gabor Juhos <j4g8y7@gmail.com>");
-+MODULE_AUTHOR("Maxime Chevallier <maxime.chevallier@bootlin.com>");
-+MODULE_LICENSE("GPL");
---- /dev/null
-+++ b/drivers/net/ethernet/qualcomm/ipqess/ipqess.h
-@@ -0,0 +1,518 @@
-+/* SPDX-License-Identifier: (GPL-2.0 OR ISC) */
-+/* Copyright (c) 2014 - 2016, The Linux Foundation. All rights reserved.
-+ * Copyright (c) 2017 - 2018, John Crispin <john@phrozen.org>
-+ * Copyright (c) 2018 - 2019, Christian Lamparter <chunkeey@gmail.com>
-+ * Copyright (c) 2020 - 2021, Gabor Juhos <j4g8y7@gmail.com>
-+ * Copyright (c) 2021 - 2022, Maxime Chevallier <maxime.chevallier@bootlin.com>
-+ *
-+ */
-+
-+#ifndef _IPQESS_H_
-+#define _IPQESS_H_
-+
-+#define IPQESS_NETDEV_QUEUES 4
-+
-+#define IPQESS_TPD_EOP_SHIFT 31
-+
-+#define IPQESS_PORT_ID_SHIFT 12
-+#define IPQESS_PORT_ID_MASK 0x7
-+
-+/* tpd word 3 bit 18-28 */
-+#define IPQESS_TPD_PORT_BITMAP_SHIFT 18
-+
-+#define IPQESS_TPD_FROM_CPU_SHIFT 25
-+
-+#define IPQESS_RX_RING_SIZE 128
-+#define IPQESS_RX_HEAD_BUFF_SIZE 1540
-+#define IPQESS_TX_RING_SIZE 128
-+#define IPQESS_MAX_RX_QUEUE 8
-+#define IPQESS_MAX_TX_QUEUE 16
-+
-+/* Configurations */
-+#define IPQESS_INTR_CLEAR_TYPE 0
-+#define IPQESS_INTR_SW_IDX_W_TYPE 0
-+#define IPQESS_FIFO_THRESH_TYPE 0
-+#define IPQESS_RSS_TYPE 0
-+#define IPQESS_RX_IMT 0x0020
-+#define IPQESS_TX_IMT 0x0050
-+#define IPQESS_TPD_BURST 5
-+#define IPQESS_TXF_BURST 0x100
-+#define IPQESS_RFD_BURST 8
-+#define IPQESS_RFD_THR 16
-+#define IPQESS_RFD_LTHR 0
-+
-+/* Flags used in transmit direction */
-+#define IPQESS_DESC_LAST 0x1
-+#define IPQESS_DESC_SINGLE 0x2
-+#define IPQESS_DESC_PAGE 0x4
-+
-+struct ipqess_statistics {
-+ u32 tx_q0_pkt;
-+ u32 tx_q1_pkt;
-+ u32 tx_q2_pkt;
-+ u32 tx_q3_pkt;
-+ u32 tx_q4_pkt;
-+ u32 tx_q5_pkt;
-+ u32 tx_q6_pkt;
-+ u32 tx_q7_pkt;
-+ u32 tx_q8_pkt;
-+ u32 tx_q9_pkt;
-+ u32 tx_q10_pkt;
-+ u32 tx_q11_pkt;
-+ u32 tx_q12_pkt;
-+ u32 tx_q13_pkt;
-+ u32 tx_q14_pkt;
-+ u32 tx_q15_pkt;
-+ u32 tx_q0_byte;
-+ u32 tx_q1_byte;
-+ u32 tx_q2_byte;
-+ u32 tx_q3_byte;
-+ u32 tx_q4_byte;
-+ u32 tx_q5_byte;
-+ u32 tx_q6_byte;
-+ u32 tx_q7_byte;
-+ u32 tx_q8_byte;
-+ u32 tx_q9_byte;
-+ u32 tx_q10_byte;
-+ u32 tx_q11_byte;
-+ u32 tx_q12_byte;
-+ u32 tx_q13_byte;
-+ u32 tx_q14_byte;
-+ u32 tx_q15_byte;
-+ u32 rx_q0_pkt;
-+ u32 rx_q1_pkt;
-+ u32 rx_q2_pkt;
-+ u32 rx_q3_pkt;
-+ u32 rx_q4_pkt;
-+ u32 rx_q5_pkt;
-+ u32 rx_q6_pkt;
-+ u32 rx_q7_pkt;
-+ u32 rx_q0_byte;
-+ u32 rx_q1_byte;
-+ u32 rx_q2_byte;
-+ u32 rx_q3_byte;
-+ u32 rx_q4_byte;
-+ u32 rx_q5_byte;
-+ u32 rx_q6_byte;
-+ u32 rx_q7_byte;
-+ u32 tx_desc_error;
-+};
-+
-+struct ipqess_tx_desc {
-+ __le16 len;
-+ __le16 svlan_tag;
-+ __le32 word1;
-+ __le32 addr;
-+ __le32 word3;
-+} __aligned(16) __packed;
-+
-+struct ipqess_rx_desc {
-+ __le16 rrd0;
-+ __le16 rrd1;
-+ __le16 rrd2;
-+ __le16 rrd3;
-+ __le16 rrd4;
-+ __le16 rrd5;
-+ __le16 rrd6;
-+ __le16 rrd7;
-+} __aligned(16) __packed;
-+
-+struct ipqess_buf {
-+ struct sk_buff *skb;
-+ dma_addr_t dma;
-+ u32 flags;
-+ u16 length;
-+};
-+
-+struct ipqess_tx_ring {
-+ struct napi_struct napi_tx;
-+ u32 idx;
-+ int ring_id;
-+ struct ipqess *ess;
-+ struct netdev_queue *nq;
-+ struct ipqess_tx_desc *hw_desc;
-+ struct ipqess_buf *buf;
-+ dma_addr_t dma;
-+ u16 count;
-+ u16 head;
-+ u16 tail;
-+};
-+
-+struct ipqess_rx_ring {
-+ struct napi_struct napi_rx;
-+ u32 idx;
-+ int ring_id;
-+ struct ipqess *ess;
-+ struct device *ppdev;
-+ struct ipqess_rx_desc **hw_desc;
-+ struct ipqess_buf *buf;
-+ dma_addr_t dma;
-+ u16 head;
-+ u16 tail;
-+ atomic_t refill_count;
-+};
-+
-+struct ipqess_rx_ring_refill {
-+ struct ipqess_rx_ring *rx_ring;
-+ struct work_struct refill_work;
-+};
-+
-+#define IPQESS_IRQ_NAME_LEN 32
-+
-+struct ipqess {
-+ struct net_device *netdev;
-+ void __iomem *hw_addr;
-+
-+ struct clk *ess_clk;
-+ struct reset_control *ess_rst;
-+
-+ struct ipqess_rx_ring rx_ring[IPQESS_NETDEV_QUEUES];
-+
-+ struct platform_device *pdev;
-+ struct phylink *phylink;
-+ struct phylink_config phylink_config;
-+ struct ipqess_tx_ring tx_ring[IPQESS_NETDEV_QUEUES];
-+
-+ struct ipqess_statistics ipqess_stats;
-+
-+ /* Protects stats */
-+ spinlock_t stats_lock;
-+ struct net_device_stats stats;
-+
-+ struct ipqess_rx_ring_refill rx_refill[IPQESS_NETDEV_QUEUES];
-+ u32 tx_irq[IPQESS_MAX_TX_QUEUE];
-+ char tx_irq_names[IPQESS_MAX_TX_QUEUE][IPQESS_IRQ_NAME_LEN];
-+ u32 rx_irq[IPQESS_MAX_RX_QUEUE];
-+ char rx_irq_names[IPQESS_MAX_TX_QUEUE][IPQESS_IRQ_NAME_LEN];
-+};
-+
-+void ipqess_set_ethtool_ops(struct net_device *netdev);
-+void ipqess_update_hw_stats(struct ipqess *ess);
-+
-+/* register definition */
-+#define IPQESS_REG_MAS_CTRL 0x0
-+#define IPQESS_REG_TIMEOUT_CTRL 0x004
-+#define IPQESS_REG_DBG0 0x008
-+#define IPQESS_REG_DBG1 0x00C
-+#define IPQESS_REG_SW_CTRL0 0x100
-+#define IPQESS_REG_SW_CTRL1 0x104
-+
-+/* Interrupt Status Register */
-+#define IPQESS_REG_RX_ISR 0x200
-+#define IPQESS_REG_TX_ISR 0x208
-+#define IPQESS_REG_MISC_ISR 0x210
-+#define IPQESS_REG_WOL_ISR 0x218
-+
-+#define IPQESS_MISC_ISR_RX_URG_Q(x) (1 << (x))
-+
-+#define IPQESS_MISC_ISR_AXIR_TIMEOUT 0x00000100
-+#define IPQESS_MISC_ISR_AXIR_ERR 0x00000200
-+#define IPQESS_MISC_ISR_TXF_DEAD 0x00000400
-+#define IPQESS_MISC_ISR_AXIW_ERR 0x00000800
-+#define IPQESS_MISC_ISR_AXIW_TIMEOUT 0x00001000
-+
-+#define IPQESS_WOL_ISR 0x00000001
-+
-+/* Interrupt Mask Register */
-+#define IPQESS_REG_MISC_IMR 0x214
-+#define IPQESS_REG_WOL_IMR 0x218
-+
-+#define IPQESS_RX_IMR_NORMAL_MASK 0x1
-+#define IPQESS_TX_IMR_NORMAL_MASK 0x1
-+#define IPQESS_MISC_IMR_NORMAL_MASK 0x80001FFF
-+#define IPQESS_WOL_IMR_NORMAL_MASK 0x1
-+
-+/* Edma receive consumer index */
-+#define IPQESS_REG_RX_SW_CONS_IDX_Q(x) (0x220 + ((x) << 2)) /* x is the queue id */
-+
-+/* Edma transmit consumer index */
-+#define IPQESS_REG_TX_SW_CONS_IDX_Q(x) (0x240 + ((x) << 2)) /* x is the queue id */
-+
-+/* IRQ Moderator Initial Timer Register */
-+#define IPQESS_REG_IRQ_MODRT_TIMER_INIT 0x280
-+#define IPQESS_IRQ_MODRT_TIMER_MASK 0xFFFF
-+#define IPQESS_IRQ_MODRT_RX_TIMER_SHIFT 0
-+#define IPQESS_IRQ_MODRT_TX_TIMER_SHIFT 16
-+
-+/* Interrupt Control Register */
-+#define IPQESS_REG_INTR_CTRL 0x284
-+#define IPQESS_INTR_CLR_TYP_SHIFT 0
-+#define IPQESS_INTR_SW_IDX_W_TYP_SHIFT 1
-+#define IPQESS_INTR_CLEAR_TYPE_W1 0
-+#define IPQESS_INTR_CLEAR_TYPE_R 1
-+
-+/* RX Interrupt Mask Register */
-+#define IPQESS_REG_RX_INT_MASK_Q(x) (0x300 + ((x) << 2)) /* x = queue id */
-+
-+/* TX Interrupt mask register */
-+#define IPQESS_REG_TX_INT_MASK_Q(x) (0x340 + ((x) << 2)) /* x = queue id */
-+
-+/* Load Ptr Register
-+ * Software sets this bit after the initialization of the head and tail
-+ */
-+#define IPQESS_REG_TX_SRAM_PART 0x400
-+#define IPQESS_LOAD_PTR_SHIFT 16
-+
-+/* TXQ Control Register */
-+#define IPQESS_REG_TXQ_CTRL 0x404
-+#define IPQESS_TXQ_CTRL_IP_OPTION_EN 0x10
-+#define IPQESS_TXQ_CTRL_TXQ_EN 0x20
-+#define IPQESS_TXQ_CTRL_ENH_MODE 0x40
-+#define IPQESS_TXQ_CTRL_LS_8023_EN 0x80
-+#define IPQESS_TXQ_CTRL_TPD_BURST_EN 0x100
-+#define IPQESS_TXQ_CTRL_LSO_BREAK_EN 0x200
-+#define IPQESS_TXQ_NUM_TPD_BURST_MASK 0xF
-+#define IPQESS_TXQ_TXF_BURST_NUM_MASK 0xFFFF
-+#define IPQESS_TXQ_NUM_TPD_BURST_SHIFT 0
-+#define IPQESS_TXQ_TXF_BURST_NUM_SHIFT 16
-+
-+#define IPQESS_REG_TXF_WATER_MARK 0x408 /* In 8-bytes */
-+#define IPQESS_TXF_WATER_MARK_MASK 0x0FFF
-+#define IPQESS_TXF_LOW_WATER_MARK_SHIFT 0
-+#define IPQESS_TXF_HIGH_WATER_MARK_SHIFT 16
-+#define IPQESS_TXQ_CTRL_BURST_MODE_EN 0x80000000
-+
-+/* WRR Control Register */
-+#define IPQESS_REG_WRR_CTRL_Q0_Q3 0x40c
-+#define IPQESS_REG_WRR_CTRL_Q4_Q7 0x410
-+#define IPQESS_REG_WRR_CTRL_Q8_Q11 0x414
-+#define IPQESS_REG_WRR_CTRL_Q12_Q15 0x418
-+
-+/* Weight round robin(WRR), it takes queue as input, and computes
-+ * starting bits where we need to write the weight for a particular
-+ * queue
-+ */
-+#define IPQESS_WRR_SHIFT(x) (((x) * 5) % 20)
-+
-+/* Tx Descriptor Control Register */
-+#define IPQESS_REG_TPD_RING_SIZE 0x41C
-+#define IPQESS_TPD_RING_SIZE_SHIFT 0
-+#define IPQESS_TPD_RING_SIZE_MASK 0xFFFF
-+
-+/* Transmit descriptor base address */
-+#define IPQESS_REG_TPD_BASE_ADDR_Q(x) (0x420 + ((x) << 2)) /* x = queue id */
-+
-+/* TPD Index Register */
-+#define IPQESS_REG_TPD_IDX_Q(x) (0x460 + ((x) << 2)) /* x = queue id */
-+
-+#define IPQESS_TPD_PROD_IDX_BITS 0x0000FFFF
-+#define IPQESS_TPD_CONS_IDX_BITS 0xFFFF0000
-+#define IPQESS_TPD_PROD_IDX_MASK 0xFFFF
-+#define IPQESS_TPD_CONS_IDX_MASK 0xFFFF
-+#define IPQESS_TPD_PROD_IDX_SHIFT 0
-+#define IPQESS_TPD_CONS_IDX_SHIFT 16
-+
-+/* TX Virtual Queue Mapping Control Register */
-+#define IPQESS_REG_VQ_CTRL0 0x4A0
-+#define IPQESS_REG_VQ_CTRL1 0x4A4
-+
-+/* Virtual QID shift, it takes queue as input, and computes
-+ * Virtual QID position in virtual qid control register
-+ */
-+#define IPQESS_VQ_ID_SHIFT(i) (((i) * 3) % 24)
-+
-+/* Virtual Queue Default Value */
-+#define IPQESS_VQ_REG_VALUE 0x240240
-+
-+/* Tx side Port Interface Control Register */
-+#define IPQESS_REG_PORT_CTRL 0x4A8
-+#define IPQESS_PAD_EN_SHIFT 15
-+
-+/* Tx side VLAN Configuration Register */
-+#define IPQESS_REG_VLAN_CFG 0x4AC
-+
-+#define IPQESS_VLAN_CFG_SVLAN_TPID_SHIFT 0
-+#define IPQESS_VLAN_CFG_SVLAN_TPID_MASK 0xffff
-+#define IPQESS_VLAN_CFG_CVLAN_TPID_SHIFT 16
-+#define IPQESS_VLAN_CFG_CVLAN_TPID_MASK 0xffff
-+
-+#define IPQESS_TX_CVLAN 16
-+#define IPQESS_TX_INS_CVLAN 17
-+#define IPQESS_TX_CVLAN_TAG_SHIFT 0
-+
-+#define IPQESS_TX_SVLAN 14
-+#define IPQESS_TX_INS_SVLAN 15
-+#define IPQESS_TX_SVLAN_TAG_SHIFT 16
-+
-+/* Tx Queue Packet Statistic Register */
-+#define IPQESS_REG_TX_STAT_PKT_Q(x) (0x700 + ((x) << 3)) /* x = queue id */
-+
-+#define IPQESS_TX_STAT_PKT_MASK 0xFFFFFF
-+
-+/* Tx Queue Byte Statistic Register */
-+#define IPQESS_REG_TX_STAT_BYTE_Q(x) (0x704 + ((x) << 3)) /* x = queue id */
-+
-+/* Load Balance Based Ring Offset Register */
-+#define IPQESS_REG_LB_RING 0x800
-+#define IPQESS_LB_RING_ENTRY_MASK 0xff
-+#define IPQESS_LB_RING_ID_MASK 0x7
-+#define IPQESS_LB_RING_PROFILE_ID_MASK 0x3
-+#define IPQESS_LB_RING_ENTRY_BIT_OFFSET 8
-+#define IPQESS_LB_RING_ID_OFFSET 0
-+#define IPQESS_LB_RING_PROFILE_ID_OFFSET 3
-+#define IPQESS_LB_REG_VALUE 0x6040200
-+
-+/* Load Balance Priority Mapping Register */
-+#define IPQESS_REG_LB_PRI_START 0x804
-+#define IPQESS_REG_LB_PRI_END 0x810
-+#define IPQESS_LB_PRI_REG_INC 4
-+#define IPQESS_LB_PRI_ENTRY_BIT_OFFSET 4
-+#define IPQESS_LB_PRI_ENTRY_MASK 0xf
-+
-+/* RSS Priority Mapping Register */
-+#define IPQESS_REG_RSS_PRI 0x820
-+#define IPQESS_RSS_PRI_ENTRY_MASK 0xf
-+#define IPQESS_RSS_RING_ID_MASK 0x7
-+#define IPQESS_RSS_PRI_ENTRY_BIT_OFFSET 4
-+
-+/* RSS Indirection Register */
-+#define IPQESS_REG_RSS_IDT(x) (0x840 + ((x) << 2)) /* x = No. of indirection table */
-+#define IPQESS_NUM_IDT 16
-+#define IPQESS_RSS_IDT_VALUE 0x64206420
-+
-+/* Default RSS Ring Register */
-+#define IPQESS_REG_DEF_RSS 0x890
-+#define IPQESS_DEF_RSS_MASK 0x7
-+
-+/* RSS Hash Function Type Register */
-+#define IPQESS_REG_RSS_TYPE 0x894
-+#define IPQESS_RSS_TYPE_NONE 0x01
-+#define IPQESS_RSS_TYPE_IPV4TCP 0x02
-+#define IPQESS_RSS_TYPE_IPV6_TCP 0x04
-+#define IPQESS_RSS_TYPE_IPV4_UDP 0x08
-+#define IPQESS_RSS_TYPE_IPV6UDP 0x10
-+#define IPQESS_RSS_TYPE_IPV4 0x20
-+#define IPQESS_RSS_TYPE_IPV6 0x40
-+#define IPQESS_RSS_HASH_MODE_MASK 0x7f
-+
-+#define IPQESS_REG_RSS_HASH_VALUE 0x8C0
-+
-+#define IPQESS_REG_RSS_TYPE_RESULT 0x8C4
-+
-+#define IPQESS_HASH_TYPE_START 0
-+#define IPQESS_HASH_TYPE_END 5
-+#define IPQESS_HASH_TYPE_SHIFT 12
-+
-+#define IPQESS_RFS_FLOW_ENTRIES 1024
-+#define IPQESS_RFS_FLOW_ENTRIES_MASK (IPQESS_RFS_FLOW_ENTRIES - 1)
-+#define IPQESS_RFS_EXPIRE_COUNT_PER_CALL 128
-+
-+/* RFD Base Address Register */
-+#define IPQESS_REG_RFD_BASE_ADDR_Q(x) (0x950 + ((x) << 2)) /* x = queue id */
-+
-+/* RFD Index Register */
-+#define IPQESS_REG_RFD_IDX_Q(x) (0x9B0 + ((x) << 2)) /* x = queue id */
-+
-+#define IPQESS_RFD_PROD_IDX_BITS 0x00000FFF
-+#define IPQESS_RFD_CONS_IDX_BITS 0x0FFF0000
-+#define IPQESS_RFD_PROD_IDX_MASK 0xFFF
-+#define IPQESS_RFD_CONS_IDX_MASK 0xFFF
-+#define IPQESS_RFD_PROD_IDX_SHIFT 0
-+#define IPQESS_RFD_CONS_IDX_SHIFT 16
-+
-+/* Rx Descriptor Control Register */
-+#define IPQESS_REG_RX_DESC0 0xA10
-+#define IPQESS_RFD_RING_SIZE_MASK 0xFFF
-+#define IPQESS_RX_BUF_SIZE_MASK 0xFFFF
-+#define IPQESS_RFD_RING_SIZE_SHIFT 0
-+#define IPQESS_RX_BUF_SIZE_SHIFT 16
-+
-+#define IPQESS_REG_RX_DESC1 0xA14
-+#define IPQESS_RXQ_RFD_BURST_NUM_MASK 0x3F
-+#define IPQESS_RXQ_RFD_PF_THRESH_MASK 0x1F
-+#define IPQESS_RXQ_RFD_LOW_THRESH_MASK 0xFFF
-+#define IPQESS_RXQ_RFD_BURST_NUM_SHIFT 0
-+#define IPQESS_RXQ_RFD_PF_THRESH_SHIFT 8
-+#define IPQESS_RXQ_RFD_LOW_THRESH_SHIFT 16
-+
-+/* RXQ Control Register */
-+#define IPQESS_REG_RXQ_CTRL 0xA18
-+#define IPQESS_FIFO_THRESH_TYPE_SHIF 0
-+#define IPQESS_FIFO_THRESH_128_BYTE 0x0
-+#define IPQESS_FIFO_THRESH_64_BYTE 0x1
-+#define IPQESS_RXQ_CTRL_RMV_VLAN 0x00000002
-+#define IPQESS_RXQ_CTRL_EN_MASK GENMASK(15, 8)
-+#define IPQESS_RXQ_CTRL_EN(__qid) BIT(8 + (__qid))
-+
-+/* AXI Burst Size Config */
-+#define IPQESS_REG_AXIW_CTRL_MAXWRSIZE 0xA1C
-+#define IPQESS_AXIW_MAXWRSIZE_VALUE 0x0
-+
-+/* Rx Statistics Register */
-+#define IPQESS_REG_RX_STAT_BYTE_Q(x) (0xA30 + ((x) << 2)) /* x = queue id */
-+#define IPQESS_REG_RX_STAT_PKT_Q(x) (0xA50 + ((x) << 2)) /* x = queue id */
-+
-+/* WoL Pattern Length Register */
-+#define IPQESS_REG_WOL_PATTERN_LEN0 0xC00
-+#define IPQESS_WOL_PT_LEN_MASK 0xFF
-+#define IPQESS_WOL_PT0_LEN_SHIFT 0
-+#define IPQESS_WOL_PT1_LEN_SHIFT 8
-+#define IPQESS_WOL_PT2_LEN_SHIFT 16
-+#define IPQESS_WOL_PT3_LEN_SHIFT 24
-+
-+#define IPQESS_REG_WOL_PATTERN_LEN1 0xC04
-+#define IPQESS_WOL_PT4_LEN_SHIFT 0
-+#define IPQESS_WOL_PT5_LEN_SHIFT 8
-+#define IPQESS_WOL_PT6_LEN_SHIFT 16
-+
-+/* WoL Control Register */
-+#define IPQESS_REG_WOL_CTRL 0xC08
-+#define IPQESS_WOL_WK_EN 0x00000001
-+#define IPQESS_WOL_MG_EN 0x00000002
-+#define IPQESS_WOL_PT0_EN 0x00000004
-+#define IPQESS_WOL_PT1_EN 0x00000008
-+#define IPQESS_WOL_PT2_EN 0x00000010
-+#define IPQESS_WOL_PT3_EN 0x00000020
-+#define IPQESS_WOL_PT4_EN 0x00000040
-+#define IPQESS_WOL_PT5_EN 0x00000080
-+#define IPQESS_WOL_PT6_EN 0x00000100
-+
-+/* MAC Control Register */
-+#define IPQESS_REG_MAC_CTRL0 0xC20
-+#define IPQESS_REG_MAC_CTRL1 0xC24
-+
-+/* WoL Pattern Register */
-+#define IPQESS_REG_WOL_PATTERN_START 0x5000
-+#define IPQESS_PATTERN_PART_REG_OFFSET 0x40
-+
-+/* TX descriptor fields */
-+#define IPQESS_TPD_HDR_SHIFT 0
-+#define IPQESS_TPD_PPPOE_EN 0x00000100
-+#define IPQESS_TPD_IP_CSUM_EN 0x00000200
-+#define IPQESS_TPD_TCP_CSUM_EN 0x0000400
-+#define IPQESS_TPD_UDP_CSUM_EN 0x00000800
-+#define IPQESS_TPD_CUSTOM_CSUM_EN 0x00000C00
-+#define IPQESS_TPD_LSO_EN 0x00001000
-+#define IPQESS_TPD_LSO_V2_EN 0x00002000
-+/* The VLAN_TAGGED bit is not used in the publicly available
-+ * drivers. The definition has been stolen from the Atheros
-+ * 'alx' driver (drivers/net/ethernet/atheros/alx/hw.h). It
-+ * seems that it has the same meaning in regard to the EDMA
-+ * hardware.
-+ */
-+#define IPQESS_TPD_VLAN_TAGGED 0x00004000
-+#define IPQESS_TPD_IPV4_EN 0x00010000
-+#define IPQESS_TPD_MSS_MASK 0x1FFF
-+#define IPQESS_TPD_MSS_SHIFT 18
-+#define IPQESS_TPD_CUSTOM_CSUM_SHIFT 18
-+
-+/* RRD descriptor fields */
-+#define IPQESS_RRD_NUM_RFD_MASK 0x000F
-+#define IPQESS_RRD_PKT_SIZE_MASK 0x3FFF
-+#define IPQESS_RRD_SRC_PORT_NUM_MASK 0x4000
-+#define IPQESS_RRD_SVLAN 0x8000
-+#define IPQESS_RRD_FLOW_COOKIE_MASK 0x07FF
-+
-+#define IPQESS_RRD_PKT_SIZE_MASK 0x3FFF
-+#define IPQESS_RRD_CSUM_FAIL_MASK 0xC000
-+#define IPQESS_RRD_CVLAN 0x0001
-+#define IPQESS_RRD_DESC_VALID 0x8000
-+
-+#define IPQESS_RRD_PRIORITY_SHIFT 4
-+#define IPQESS_RRD_PRIORITY_MASK 0x7
-+#define IPQESS_RRD_PORT_TYPE_SHIFT 7
-+#define IPQESS_RRD_PORT_TYPE_MASK 0x1F
-+
-+#define IPQESS_RRD_PORT_ID_MASK 0x7000
-+
-+#endif
---- /dev/null
-+++ b/drivers/net/ethernet/qualcomm/ipqess/ipqess_ethtool.c
-@@ -0,0 +1,164 @@
-+// SPDX-License-Identifier: GPL-2.0 OR ISC
-+/* Copyright (c) 2015 - 2016, The Linux Foundation. All rights reserved.
-+ * Copyright (c) 2017 - 2018, John Crispin <john@phrozen.org>
-+ * Copyright (c) 2021 - 2022, Maxime Chevallier <maxime.chevallier@bootlin.com>
-+ *
-+ */
-+
-+#include <linux/ethtool.h>
-+#include <linux/netdevice.h>
-+#include <linux/string.h>
-+#include <linux/phylink.h>
-+
-+#include "ipqess.h"
-+
-+struct ipqess_ethtool_stats {
-+ u8 string[ETH_GSTRING_LEN];
-+ u32 offset;
-+};
-+
-+#define IPQESS_STAT(m) offsetof(struct ipqess_statistics, m)
-+#define DRVINFO_LEN 32
-+
-+static const struct ipqess_ethtool_stats ipqess_stats[] = {
-+ {"tx_q0_pkt", IPQESS_STAT(tx_q0_pkt)},
-+ {"tx_q1_pkt", IPQESS_STAT(tx_q1_pkt)},
-+ {"tx_q2_pkt", IPQESS_STAT(tx_q2_pkt)},
-+ {"tx_q3_pkt", IPQESS_STAT(tx_q3_pkt)},
-+ {"tx_q4_pkt", IPQESS_STAT(tx_q4_pkt)},
-+ {"tx_q5_pkt", IPQESS_STAT(tx_q5_pkt)},
-+ {"tx_q6_pkt", IPQESS_STAT(tx_q6_pkt)},
-+ {"tx_q7_pkt", IPQESS_STAT(tx_q7_pkt)},
-+ {"tx_q8_pkt", IPQESS_STAT(tx_q8_pkt)},
-+ {"tx_q9_pkt", IPQESS_STAT(tx_q9_pkt)},
-+ {"tx_q10_pkt", IPQESS_STAT(tx_q10_pkt)},
-+ {"tx_q11_pkt", IPQESS_STAT(tx_q11_pkt)},
-+ {"tx_q12_pkt", IPQESS_STAT(tx_q12_pkt)},
-+ {"tx_q13_pkt", IPQESS_STAT(tx_q13_pkt)},
-+ {"tx_q14_pkt", IPQESS_STAT(tx_q14_pkt)},
-+ {"tx_q15_pkt", IPQESS_STAT(tx_q15_pkt)},
-+ {"tx_q0_byte", IPQESS_STAT(tx_q0_byte)},
-+ {"tx_q1_byte", IPQESS_STAT(tx_q1_byte)},
-+ {"tx_q2_byte", IPQESS_STAT(tx_q2_byte)},
-+ {"tx_q3_byte", IPQESS_STAT(tx_q3_byte)},
-+ {"tx_q4_byte", IPQESS_STAT(tx_q4_byte)},
-+ {"tx_q5_byte", IPQESS_STAT(tx_q5_byte)},
-+ {"tx_q6_byte", IPQESS_STAT(tx_q6_byte)},
-+ {"tx_q7_byte", IPQESS_STAT(tx_q7_byte)},
-+ {"tx_q8_byte", IPQESS_STAT(tx_q8_byte)},
-+ {"tx_q9_byte", IPQESS_STAT(tx_q9_byte)},
-+ {"tx_q10_byte", IPQESS_STAT(tx_q10_byte)},
-+ {"tx_q11_byte", IPQESS_STAT(tx_q11_byte)},
-+ {"tx_q12_byte", IPQESS_STAT(tx_q12_byte)},
-+ {"tx_q13_byte", IPQESS_STAT(tx_q13_byte)},
-+ {"tx_q14_byte", IPQESS_STAT(tx_q14_byte)},
-+ {"tx_q15_byte", IPQESS_STAT(tx_q15_byte)},
-+ {"rx_q0_pkt", IPQESS_STAT(rx_q0_pkt)},
-+ {"rx_q1_pkt", IPQESS_STAT(rx_q1_pkt)},
-+ {"rx_q2_pkt", IPQESS_STAT(rx_q2_pkt)},
-+ {"rx_q3_pkt", IPQESS_STAT(rx_q3_pkt)},
-+ {"rx_q4_pkt", IPQESS_STAT(rx_q4_pkt)},
-+ {"rx_q5_pkt", IPQESS_STAT(rx_q5_pkt)},
-+ {"rx_q6_pkt", IPQESS_STAT(rx_q6_pkt)},
-+ {"rx_q7_pkt", IPQESS_STAT(rx_q7_pkt)},
-+ {"rx_q0_byte", IPQESS_STAT(rx_q0_byte)},
-+ {"rx_q1_byte", IPQESS_STAT(rx_q1_byte)},
-+ {"rx_q2_byte", IPQESS_STAT(rx_q2_byte)},
-+ {"rx_q3_byte", IPQESS_STAT(rx_q3_byte)},
-+ {"rx_q4_byte", IPQESS_STAT(rx_q4_byte)},
-+ {"rx_q5_byte", IPQESS_STAT(rx_q5_byte)},
-+ {"rx_q6_byte", IPQESS_STAT(rx_q6_byte)},
-+ {"rx_q7_byte", IPQESS_STAT(rx_q7_byte)},
-+ {"tx_desc_error", IPQESS_STAT(tx_desc_error)},
-+};
-+
-+static int ipqess_get_strset_count(struct net_device *netdev, int sset)
-+{
-+ switch (sset) {
-+ case ETH_SS_STATS:
-+ return ARRAY_SIZE(ipqess_stats);
-+ default:
-+ netdev_dbg(netdev, "%s: Unsupported string set", __func__);
-+ return -EOPNOTSUPP;
-+ }
-+}
-+
-+static void ipqess_get_strings(struct net_device *netdev, u32 stringset,
-+ u8 *data)
-+{
-+ u8 *p = data;
-+ u32 i;
-+
-+ switch (stringset) {
-+ case ETH_SS_STATS:
-+ for (i = 0; i < ARRAY_SIZE(ipqess_stats); i++)
-+ ethtool_puts(&p, ipqess_stats[i].string);
-+ break;
-+ }
-+}
-+
-+static void ipqess_get_ethtool_stats(struct net_device *netdev,
-+ struct ethtool_stats *stats,
-+ uint64_t *data)
-+{
-+ struct ipqess *ess = netdev_priv(netdev);
-+ u32 *essstats = (u32 *)&ess->ipqess_stats;
-+ int i;
-+
-+ spin_lock(&ess->stats_lock);
-+
-+ ipqess_update_hw_stats(ess);
-+
-+ for (i = 0; i < ARRAY_SIZE(ipqess_stats); i++)
-+ data[i] = *(u32 *)(essstats + (ipqess_stats[i].offset / sizeof(u32)));
-+
-+ spin_unlock(&ess->stats_lock);
-+}
-+
-+static void ipqess_get_drvinfo(struct net_device *dev,
-+ struct ethtool_drvinfo *info)
-+{
-+ strscpy(info->driver, "qca_ipqess", DRVINFO_LEN);
-+ strscpy(info->bus_info, "axi", ETHTOOL_BUSINFO_LEN);
-+}
-+
-+static int ipqess_get_link_ksettings(struct net_device *netdev,
-+ struct ethtool_link_ksettings *cmd)
-+{
-+ struct ipqess *ess = netdev_priv(netdev);
-+
-+ return phylink_ethtool_ksettings_get(ess->phylink, cmd);
-+}
-+
-+static int ipqess_set_link_ksettings(struct net_device *netdev,
-+ const struct ethtool_link_ksettings *cmd)
-+{
-+ struct ipqess *ess = netdev_priv(netdev);
-+
-+ return phylink_ethtool_ksettings_set(ess->phylink, cmd);
-+}
-+
-+static void ipqess_get_ringparam(struct net_device *netdev,
-+ struct ethtool_ringparam *ring,
-+ struct kernel_ethtool_ringparam *kernel_ering,
-+ struct netlink_ext_ack *extack)
-+{
-+ ring->tx_max_pending = IPQESS_TX_RING_SIZE;
-+ ring->rx_max_pending = IPQESS_RX_RING_SIZE;
-+}
-+
-+static const struct ethtool_ops ipqesstool_ops = {
-+ .get_drvinfo = &ipqess_get_drvinfo,
-+ .get_link = ðtool_op_get_link,
-+ .get_link_ksettings = &ipqess_get_link_ksettings,
-+ .set_link_ksettings = &ipqess_set_link_ksettings,
-+ .get_strings = &ipqess_get_strings,
-+ .get_sset_count = &ipqess_get_strset_count,
-+ .get_ethtool_stats = &ipqess_get_ethtool_stats,
-+ .get_ringparam = ipqess_get_ringparam,
-+};
-+
-+void ipqess_set_ethtool_ops(struct net_device *netdev)
-+{
-+ netdev->ethtool_ops = &ipqesstool_ops;
-+}
+++ /dev/null
-From a32e16b3c2fc1954ad6e09737439f60e5890278e Mon Sep 17 00:00:00 2001
-From: Maxime Chevallier <maxime.chevallier@bootlin.com>
-Date: Fri, 4 Nov 2022 18:41:49 +0100
-Subject: [PATCH] net: dsa: add out-of-band tagging protocol
-
-This tagging protocol is designed for the situation where the link
-between the MAC and the Switch is designed such that the Destination
-Port, which is usually embedded in some part of the Ethernet Header, is
-sent out-of-band, and isn't present at all in the Ethernet frame.
-
-This can happen when the MAC and Switch are tightly integrated on an
-SoC, as is the case with the Qualcomm IPQ4019 for example, where the DSA
-tag is inserted directly into the DMA descriptors. In that case,
-the MAC driver is responsible for sending the tag to the switch using
-the out-of-band medium. To do so, the MAC driver needs to have the
-information of the destination port for that skb.
-
-Add a new tagging protocol based on SKB extensions to convey the
-information about the destination port to the MAC driver
-
-Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
----
- Documentation/networking/dsa/dsa.rst | 13 +++++++-
- MAINTAINERS | 1 +
- include/linux/dsa/oob.h | 16 +++++++++
- include/linux/skbuff.h | 3 ++
- include/net/dsa.h | 2 ++
- net/core/skbuff.c | 10 ++++++
- net/dsa/Kconfig | 9 +++++
- net/dsa/Makefile | 1 +
- net/dsa/tag_oob.c | 49 ++++++++++++++++++++++++++++
- 9 files changed, 103 insertions(+), 1 deletion(-)
- create mode 100644 include/linux/dsa/oob.h
- create mode 100644 net/dsa/tag_oob.c
-
---- a/Documentation/networking/dsa/dsa.rst
-+++ b/Documentation/networking/dsa/dsa.rst
-@@ -66,7 +66,8 @@ Switch tagging protocols
- ------------------------
-
- DSA supports many vendor-specific tagging protocols, one software-defined
--tagging protocol, and a tag-less mode as well (``DSA_TAG_PROTO_NONE``).
-+tagging protocol, a tag-less mode as well (``DSA_TAG_PROTO_NONE``) and an
-+out-of-band tagging protocol (``DSA_TAG_PROTO_OOB``).
-
- The exact format of the tag protocol is vendor specific, but in general, they
- all contain something which:
-@@ -217,6 +218,16 @@ receive all frames regardless of the val
- setting the ``promisc_on_master`` property of the ``struct dsa_device_ops``.
- Note that this assumes a DSA-unaware master driver, which is the norm.
-
-+Some SoCs have a tight integration between the conduit network interface and the
-+embedded switch, such that the DSA tag isn't transmitted in the packet data,
-+but through another media, using so-called out-of-band tagging. In that case,
-+the host MAC driver is in charge of transmitting the tag to the switch.
-+An example is the IPQ4019 SoC, that transmits the tag between the ipqess
-+ethernet controller and the qca8k switch using the DMA descriptor. In that
-+configuration, tag-chaining is permitted, but the OOB tag will always be the
-+top-most switch in the tree. The tagger (``DSA_TAG_PROTO_OOB``) uses skb
-+extensions to transmit the tag to and from the MAC driver.
-+
- Master network devices
- ----------------------
-
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -17081,6 +17081,7 @@ L: netdev@vger.kernel.org
- S: Maintained
- F: Documentation/devicetree/bindings/net/qcom,ipq4019-ess-edma.yaml
- F: drivers/net/ethernet/qualcomm/ipqess/
-+F: net/dsa/tag_oob.c
-
- QUALCOMM ETHQOS ETHERNET DRIVER
- M: Vinod Koul <vkoul@kernel.org>
---- /dev/null
-+++ b/include/linux/dsa/oob.h
-@@ -0,0 +1,16 @@
-+/* SPDX-License-Identifier: GPL-2.0-only
-+ * Copyright (C) 2022 Maxime Chevallier <maxime.chevallier@bootlin.com>
-+ */
-+
-+#ifndef _NET_DSA_OOB_H
-+#define _NET_DSA_OOB_H
-+
-+#include <linux/skbuff.h>
-+
-+struct dsa_oob_tag_info {
-+ u16 port;
-+};
-+
-+int dsa_oob_tag_push(struct sk_buff *skb, struct dsa_oob_tag_info *ti);
-+int dsa_oob_tag_pop(struct sk_buff *skb, struct dsa_oob_tag_info *ti);
-+#endif
---- a/include/linux/skbuff.h
-+++ b/include/linux/skbuff.h
-@@ -4594,6 +4594,9 @@ enum skb_ext_id {
- #if IS_ENABLED(CONFIG_MCTP_FLOWS)
- SKB_EXT_MCTP,
- #endif
-+#if IS_ENABLED(CONFIG_NET_DSA_TAG_OOB)
-+ SKB_EXT_DSA_OOB,
-+#endif
- SKB_EXT_NUM, /* must be last */
- };
-
---- a/include/net/dsa.h
-+++ b/include/net/dsa.h
-@@ -55,6 +55,7 @@ struct phylink_link_state;
- #define DSA_TAG_PROTO_RTL8_4T_VALUE 25
- #define DSA_TAG_PROTO_RZN1_A5PSW_VALUE 26
- #define DSA_TAG_PROTO_LAN937X_VALUE 27
-+#define DSA_TAG_PROTO_OOB_VALUE 28
-
- enum dsa_tag_protocol {
- DSA_TAG_PROTO_NONE = DSA_TAG_PROTO_NONE_VALUE,
-@@ -85,6 +86,7 @@ enum dsa_tag_protocol {
- DSA_TAG_PROTO_RTL8_4T = DSA_TAG_PROTO_RTL8_4T_VALUE,
- DSA_TAG_PROTO_RZN1_A5PSW = DSA_TAG_PROTO_RZN1_A5PSW_VALUE,
- DSA_TAG_PROTO_LAN937X = DSA_TAG_PROTO_LAN937X_VALUE,
-+ DSA_TAG_PROTO_OOB = DSA_TAG_PROTO_OOB_VALUE,
- };
-
- struct dsa_switch;
---- a/net/core/skbuff.c
-+++ b/net/core/skbuff.c
-@@ -62,8 +62,12 @@
- #include <linux/mpls.h>
- #include <linux/kcov.h>
- #include <linux/if.h>
-+#ifdef CONFIG_NET_DSA_TAG_OOB
-+#include <linux/dsa/oob.h>
-+#endif
-
- #include <net/protocol.h>
-+#include <net/dsa.h>
- #include <net/dst.h>
- #include <net/sock.h>
- #include <net/checksum.h>
-@@ -4517,6 +4521,9 @@ static const u8 skb_ext_type_len[] = {
- #if IS_ENABLED(CONFIG_MCTP_FLOWS)
- [SKB_EXT_MCTP] = SKB_EXT_CHUNKSIZEOF(struct mctp_flow),
- #endif
-+#if IS_ENABLED(CONFIG_NET_DSA_TAG_OOB)
-+ [SKB_EXT_DSA_OOB] = SKB_EXT_CHUNKSIZEOF(struct dsa_oob_tag_info),
-+#endif
- };
-
- static __always_inline unsigned int skb_ext_total_length(void)
-@@ -4537,6 +4544,9 @@ static __always_inline unsigned int skb_
- #if IS_ENABLED(CONFIG_MCTP_FLOWS)
- skb_ext_type_len[SKB_EXT_MCTP] +
- #endif
-+#if IS_ENABLED(CONFIG_NET_DSA_TAG_OOB)
-+ skb_ext_type_len[SKB_EXT_DSA_OOB] +
-+#endif
- 0;
- }
-
---- a/net/dsa/Kconfig
-+++ b/net/dsa/Kconfig
-@@ -113,6 +113,15 @@ config NET_DSA_TAG_OCELOT_8021Q
- this mode, less TCAM resources (VCAP IS1, IS2, ES0) are available for
- use with tc-flower.
-
-+config NET_DSA_TAG_OOB
-+ select SKB_EXTENSIONS
-+ tristate "Tag driver for Out-of-band tagging drivers"
-+ help
-+ Say Y or M if you want to enable support for pairs of embedded
-+ switches and host MAC drivers which perform demultiplexing and
-+ packet steering to ports using out of band metadata processed
-+ by the DSA master, rather than tags present in the packets.
-+
- config NET_DSA_TAG_QCA
- tristate "Tag driver for Qualcomm Atheros QCA8K switches"
- help
---- a/net/dsa/Makefile
-+++ b/net/dsa/Makefile
-@@ -22,6 +22,7 @@ obj-$(CONFIG_NET_DSA_TAG_LAN9303) += tag
- obj-$(CONFIG_NET_DSA_TAG_MTK) += tag_mtk.o
- obj-$(CONFIG_NET_DSA_TAG_OCELOT) += tag_ocelot.o
- obj-$(CONFIG_NET_DSA_TAG_OCELOT_8021Q) += tag_ocelot_8021q.o
-+obj-$(CONFIG_NET_DSA_TAG_OOB) += tag_oob.o
- obj-$(CONFIG_NET_DSA_TAG_QCA) += tag_qca.o
- obj-$(CONFIG_NET_DSA_TAG_RTL4_A) += tag_rtl4_a.o
- obj-$(CONFIG_NET_DSA_TAG_RTL8_4) += tag_rtl8_4.o
---- /dev/null
-+++ b/net/dsa/tag_oob.c
-@@ -0,0 +1,49 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+
-+/* Copyright (c) 2022, Maxime Chevallier <maxime.chevallier@bootlin.com> */
-+
-+#include <linux/bitfield.h>
-+#include <linux/dsa/oob.h>
-+#include <linux/skbuff.h>
-+
-+#include "dsa_priv.h"
-+
-+static struct sk_buff *oob_tag_xmit(struct sk_buff *skb,
-+ struct net_device *dev)
-+{
-+ struct dsa_oob_tag_info *tag_info = skb_ext_add(skb, SKB_EXT_DSA_OOB);
-+ struct dsa_port *dp = dsa_slave_to_port(dev);
-+
-+ tag_info->port = dp->index;
-+
-+ return skb;
-+}
-+
-+static struct sk_buff *oob_tag_rcv(struct sk_buff *skb,
-+ struct net_device *dev)
-+{
-+ struct dsa_oob_tag_info *tag_info = skb_ext_find(skb, SKB_EXT_DSA_OOB);
-+
-+ if (!tag_info)
-+ return NULL;
-+
-+ skb->dev = dsa_master_find_slave(dev, 0, tag_info->port);
-+ if (!skb->dev)
-+ return NULL;
-+
-+ return skb;
-+}
-+
-+static const struct dsa_device_ops oob_tag_dsa_ops = {
-+ .name = "oob",
-+ .proto = DSA_TAG_PROTO_OOB,
-+ .xmit = oob_tag_xmit,
-+ .rcv = oob_tag_rcv,
-+};
-+
-+MODULE_LICENSE("GPL");
-+MODULE_DESCRIPTION("DSA tag driver for out-of-band tagging");
-+MODULE_AUTHOR("Maxime Chevallier <maxime.chevallier@bootlin.com>");
-+MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_OOB);
-+
-+module_dsa_tag_driver(oob_tag_dsa_ops);
+++ /dev/null
-From 4975e2b3f1d37bba04f262784cef0d5b7e0a30a4 Mon Sep 17 00:00:00 2001
-From: Maxime Chevallier <maxime.chevallier@bootlin.com>
-Date: Fri, 4 Nov 2022 18:41:50 +0100
-Subject: [PATCH] net: ipqess: Add out-of-band DSA tagging support
-
-On the IPQ4019, there's an 5 ports switch connected to the CPU through
-the IPQESS Ethernet controller. The way the DSA tag is sent-out to that
-switch is through the DMA descriptor, due to how tightly it is
-integrated with the switch.
-
-We use the out-of-band tagging protocol by getting the source
-port from the descriptor, push it into the skb extensions, and have the
-tagger pull it to infer the destination netdev. The reverse process is
-done on the TX side, where the driver pulls the tag from the skb and
-builds the descriptor accordingly.
-
-Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
----
- drivers/net/ethernet/qualcomm/Kconfig | 1 +
- drivers/net/ethernet/qualcomm/ipqess/ipqess.c | 64 ++++++++++++++++++-
- drivers/net/ethernet/qualcomm/ipqess/ipqess.h | 4 ++
- 3 files changed, 68 insertions(+), 1 deletion(-)
-
---- a/drivers/net/ethernet/qualcomm/Kconfig
-+++ b/drivers/net/ethernet/qualcomm/Kconfig
-@@ -64,6 +64,7 @@ config QCOM_IPQ4019_ESS_EDMA
- tristate "Qualcomm Atheros IPQ4019 ESS EDMA support"
- depends on (OF && ARCH_QCOM) || COMPILE_TEST
- select PHYLINK
-+ select NET_DSA_TAG_OOB
- help
- This driver supports the Qualcomm Atheros IPQ40xx built-in
- ESS EDMA ethernet controller.
---- a/drivers/net/ethernet/qualcomm/ipqess/ipqess.c
-+++ b/drivers/net/ethernet/qualcomm/ipqess/ipqess.c
-@@ -9,6 +9,7 @@
-
- #include <linux/bitfield.h>
- #include <linux/clk.h>
-+#include <linux/dsa/oob.h>
- #include <linux/if_vlan.h>
- #include <linux/interrupt.h>
- #include <linux/module.h>
-@@ -22,6 +23,7 @@
- #include <linux/skbuff.h>
- #include <linux/vmalloc.h>
- #include <net/checksum.h>
-+#include <net/dsa.h>
- #include <net/ip6_checksum.h>
-
- #include "ipqess.h"
-@@ -327,6 +329,7 @@ static int ipqess_rx_poll(struct ipqess_
- tail &= IPQESS_RFD_CONS_IDX_MASK;
-
- while (done < budget) {
-+ struct dsa_oob_tag_info *tag_info;
- struct ipqess_rx_desc *rd;
- struct sk_buff *skb;
-
-@@ -406,6 +409,12 @@ static int ipqess_rx_poll(struct ipqess_
- __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021AD),
- le16_to_cpu(rd->rrd4));
-
-+ if (likely(rx_ring->ess->dsa_ports)) {
-+ tag_info = skb_ext_add(skb, SKB_EXT_DSA_OOB);
-+ tag_info->port = FIELD_GET(IPQESS_RRD_PORT_ID_MASK,
-+ le16_to_cpu(rd->rrd1));
-+ }
-+
- napi_gro_receive(&rx_ring->napi_rx, skb);
-
- rx_ring->ess->stats.rx_packets++;
-@@ -706,6 +715,23 @@ static void ipqess_rollback_tx(struct ip
- tx_ring->head = start_index;
- }
-
-+static void ipqess_process_dsa_tag_sh(struct ipqess *ess, struct sk_buff *skb,
-+ u32 *word3)
-+{
-+ struct dsa_oob_tag_info *tag_info;
-+
-+ if (unlikely(!ess->dsa_ports))
-+ return;
-+
-+ tag_info = skb_ext_find(skb, SKB_EXT_DSA_OOB);
-+ if (!tag_info)
-+ return;
-+
-+ *word3 |= tag_info->port << IPQESS_TPD_PORT_BITMAP_SHIFT;
-+ *word3 |= BIT(IPQESS_TPD_FROM_CPU_SHIFT);
-+ *word3 |= 0x3e << IPQESS_TPD_PORT_BITMAP_SHIFT;
-+}
-+
- static int ipqess_tx_map_and_fill(struct ipqess_tx_ring *tx_ring,
- struct sk_buff *skb)
- {
-@@ -716,6 +742,8 @@ static int ipqess_tx_map_and_fill(struct
- u16 len;
- int i;
-
-+ ipqess_process_dsa_tag_sh(tx_ring->ess, skb, &word3);
-+
- if (skb_is_gso(skb)) {
- if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV4) {
- lso_word1 |= IPQESS_TPD_IPV4_EN;
-@@ -917,6 +945,33 @@ static const struct net_device_ops ipqes
- .ndo_tx_timeout = ipqess_tx_timeout,
- };
-
-+static int ipqess_netdevice_event(struct notifier_block *nb,
-+ unsigned long event, void *ptr)
-+{
-+ struct ipqess *ess = container_of(nb, struct ipqess, netdev_notifier);
-+ struct net_device *dev = netdev_notifier_info_to_dev(ptr);
-+ struct netdev_notifier_changeupper_info *info;
-+
-+ if (dev != ess->netdev)
-+ return NOTIFY_DONE;
-+
-+ switch (event) {
-+ case NETDEV_CHANGEUPPER:
-+ info = ptr;
-+
-+ if (!dsa_slave_dev_check(info->upper_dev))
-+ return NOTIFY_DONE;
-+
-+ if (info->linking)
-+ ess->dsa_ports++;
-+ else
-+ ess->dsa_ports--;
-+
-+ return NOTIFY_DONE;
-+ }
-+ return NOTIFY_OK;
-+}
-+
- static void ipqess_hw_stop(struct ipqess *ess)
- {
- int i;
-@@ -1184,12 +1239,19 @@ static int ipqess_axi_probe(struct platf
- netif_napi_add(netdev, &ess->rx_ring[i].napi_rx, ipqess_rx_napi);
- }
-
-- err = register_netdev(netdev);
-+ ess->netdev_notifier.notifier_call = ipqess_netdevice_event;
-+ err = register_netdevice_notifier(&ess->netdev_notifier);
- if (err)
- goto err_hw_stop;
-
-+ err = register_netdev(netdev);
-+ if (err)
-+ goto err_notifier_unregister;
-+
- return 0;
-
-+err_notifier_unregister:
-+ unregister_netdevice_notifier(&ess->netdev_notifier);
- err_hw_stop:
- ipqess_hw_stop(ess);
-
---- a/drivers/net/ethernet/qualcomm/ipqess/ipqess.h
-+++ b/drivers/net/ethernet/qualcomm/ipqess/ipqess.h
-@@ -171,6 +171,10 @@ struct ipqess {
- struct platform_device *pdev;
- struct phylink *phylink;
- struct phylink_config phylink_config;
-+
-+ struct notifier_block netdev_notifier;
-+ int dsa_ports;
-+
- struct ipqess_tx_ring tx_ring[IPQESS_NETDEV_QUEUES];
-
- struct ipqess_statistics ipqess_stats;
+++ /dev/null
-From 5f15f7f170c76220dfd36cb9037d7848d1fc4aaf Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Tue, 15 Aug 2023 14:30:50 +0200
-Subject: [PATCH] net: qualcomm: ipqess: release IRQ-s on network device stop
-
-Currently, IPQESS driver is obtaining the IRQ-s during ndo_open, but they
-are never freed as they are device managed.
-
-However, it is not enough for them to be released when device is removed
-as the same network device can be stopped and started multiple times which
-on the second start would lead to IRQ request to fail with -EBUSY as they
-have already been requested before and are not of the shared type with:
-[ 34.480769] ipqess-edma c080000.ethernet eth0: Link is Down
-[ 34.488070] ipqess-edma c080000.ethernet eth0: ipqess_open
-[ 34.488131] genirq: Flags mismatch irq 37. 00000001 (c080000.ethernet:txq0) vs. 00000001 (c080000.ethernet:txq0)
-[ 34.494527] ipqess-edma c080000.ethernet eth0: ipqess_open
-[ 34.502892] genirq: Flags mismatch irq 37. 00000001 (c080000.ethernet:txq0) vs. 00000001 (c080000.ethernet:txq0)
-[ 34.508137] qca8k-ipq4019 c000000.switch lan1: failed to open master eth0
-[ 34.518966] br-lan: port 1(lan1) entered blocking state
-[ 34.525165] br-lan: port 1(lan1) entered disabled state
-[ 34.530633] device lan1 entered promiscuous mode
-[ 34.548598] ipqess-edma c080000.ethernet eth0: ipqess_open
-[ 34.548660] genirq: Flags mismatch irq 37. 00000001 (c080000.ethernet:txq0) vs. 00000001 (c080000.ethernet:txq0)
-[ 34.553111] qca8k-ipq4019 c000000.switch lan2: failed to open master eth0
-[ 34.563841] br-lan: port 2(lan2) entered blocking state
-[ 34.570083] br-lan: port 2(lan2) entered disabled state
-[ 34.575530] device lan2 entered promiscuous mode
-[ 34.587067] ipqess-edma c080000.ethernet eth0: ipqess_open
-[ 34.587132] genirq: Flags mismatch irq 37. 00000001 (c080000.ethernet:txq0) vs. 00000001 (c080000.ethernet:txq0)
-[ 34.591579] qca8k-ipq4019 c000000.switch lan3: failed to open master eth0
-[ 34.602451] br-lan: port 3(lan3) entered blocking state
-[ 34.608496] br-lan: port 3(lan3) entered disabled state
-[ 34.614084] device lan3 entered promiscuous mode
-[ 34.626405] ipqess-edma c080000.ethernet eth0: ipqess_open
-[ 34.626468] genirq: Flags mismatch irq 37. 00000001 (c080000.ethernet:txq0) vs. 00000001 (c080000.ethernet:txq0)
-[ 34.630871] qca8k-ipq4019 c000000.switch lan4: failed to open master eth0
-[ 34.641689] br-lan: port 4(lan4) entered blocking state
-[ 34.647834] br-lan: port 4(lan4) entered disabled state
-[ 34.653455] device lan4 entered promiscuous mode
-[ 34.667282] ipqess-edma c080000.ethernet eth0: ipqess_open
-[ 34.667364] genirq: Flags mismatch irq 37. 00000001 (c080000.ethernet:txq0) vs. 00000001 (c080000.ethernet:txq0)
-[ 34.671830] qca8k-ipq4019 c000000.switch wan: failed to open master eth0
-
-So, lets free the IRQ-s on ndo_stop after stopping NAPI and HW IRQ-s.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- drivers/net/ethernet/qualcomm/ipqess/ipqess.c | 13 +++++++++++++
- 1 file changed, 13 insertions(+)
-
---- a/drivers/net/ethernet/qualcomm/ipqess/ipqess.c
-+++ b/drivers/net/ethernet/qualcomm/ipqess/ipqess.c
-@@ -636,9 +636,22 @@ static int ipqess_stop(struct net_device
- netif_tx_stop_all_queues(netdev);
- phylink_stop(ess->phylink);
- ipqess_irq_disable(ess);
-+
- for (i = 0; i < IPQESS_NETDEV_QUEUES; i++) {
-+ int qid;
-+
- napi_disable(&ess->tx_ring[i].napi_tx);
- napi_disable(&ess->rx_ring[i].napi_rx);
-+
-+ qid = ess->tx_ring[i].idx;
-+ devm_free_irq(&netdev->dev,
-+ ess->tx_irq[qid],
-+ &ess->tx_ring[i]);
-+
-+ qid = ess->rx_ring[i].idx;
-+ devm_free_irq(&netdev->dev,
-+ ess->rx_irq[qid],
-+ &ess->rx_ring[i]);
- }
-
- return 0;
+++ /dev/null
-From 9fa4a57a65e270e4d579cace4de5c438f46c7d12 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Tue, 15 Aug 2023 14:38:44 +0200
-Subject: [PATCH] net: qualcomm: ipqess: enable threaded NAPI by default
-
-Threaded NAPI provides a nice performance boost, so lets enable it by
-default.
-
-We do however need to move the __napi_schedule() after HW IRQ has been
-cleared in order to avoid concurency issues.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- drivers/net/ethernet/qualcomm/ipqess/ipqess.c | 6 ++++--
- 1 file changed, 4 insertions(+), 2 deletions(-)
-
---- a/drivers/net/ethernet/qualcomm/ipqess/ipqess.c
-+++ b/drivers/net/ethernet/qualcomm/ipqess/ipqess.c
-@@ -530,9 +530,9 @@ static irqreturn_t ipqess_interrupt_tx(i
- struct ipqess_tx_ring *tx_ring = (struct ipqess_tx_ring *)priv;
-
- if (likely(napi_schedule_prep(&tx_ring->napi_tx))) {
-- __napi_schedule(&tx_ring->napi_tx);
- ipqess_w32(tx_ring->ess, IPQESS_REG_TX_INT_MASK_Q(tx_ring->idx),
- 0x0);
-+ __napi_schedule(&tx_ring->napi_tx);
- }
-
- return IRQ_HANDLED;
-@@ -543,9 +543,9 @@ static irqreturn_t ipqess_interrupt_rx(i
- struct ipqess_rx_ring *rx_ring = (struct ipqess_rx_ring *)priv;
-
- if (likely(napi_schedule_prep(&rx_ring->napi_rx))) {
-- __napi_schedule(&rx_ring->napi_rx);
- ipqess_w32(rx_ring->ess, IPQESS_REG_RX_INT_MASK_Q(rx_ring->idx),
- 0x0);
-+ __napi_schedule(&rx_ring->napi_rx);
- }
-
- return IRQ_HANDLED;
-@@ -1261,6 +1261,8 @@ static int ipqess_axi_probe(struct platf
- if (err)
- goto err_notifier_unregister;
-
-+ dev_set_threaded(netdev, true);
-+
- return 0;
-
- err_notifier_unregister:
+++ /dev/null
-From 5b71dbb867680887d47954ce1cc145cb747cbce6 Mon Sep 17 00:00:00 2001
-From: Maxime Chevallier <maxime.chevallier@bootlin.com>
-Date: Fri, 4 Nov 2022 18:41:51 +0100
-Subject: [PATCH] ARM: dts: qcom: ipq4019: Add description for the IPQESS
- Ethernet controller
-
-The Qualcomm IPQ4019 includes an internal 5 ports switch, which is
-connected to the CPU through the internal IPQESS Ethernet controller.
-
-Add support for this internal interface, which is internally connected to a
-modified version of the QCA8K Ethernet switch.
-
-This Ethernet controller only support a specific internal interface mode
-for connection to the switch.
-
-Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
-Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
----
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 48 +++++++++++++++++++++++++++++
- 1 file changed, 48 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -594,6 +594,54 @@
- status = "disabled";
- };
-
-+ gmac: ethernet@c080000 {
-+ compatible = "qcom,ipq4019-ess-edma";
-+ reg = <0xc080000 0x8000>;
-+ resets = <&gcc ESS_RESET>;
-+ reset-names = "ess";
-+ clocks = <&gcc GCC_ESS_CLK>;
-+ clock-names = "ess";
-+ interrupts = <GIC_SPI 65 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 69 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 71 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 240 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 242 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 243 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 244 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 246 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 249 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 252 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 253 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 254 IRQ_TYPE_EDGE_RISING>,
-+ <GIC_SPI 255 IRQ_TYPE_EDGE_RISING>;
-+ phy-mode = "internal";
-+ status = "disabled";
-+ fixed-link {
-+ speed = <1000>;
-+ full-duplex;
-+ pause;
-+ };
-+ };
-+
- mdio: mdio@90000 {
- #address-cells = <1>;
- #size-cells = <0>;
+++ /dev/null
-From a38126870488398932e017dd9d76174b4aadbbbb Mon Sep 17 00:00:00 2001
-From: Robert Marko <robert.marko@sartura.hr>
-Date: Sat, 10 Sep 2022 15:46:09 +0200
-Subject: [PATCH] net: dsa: qca8k: add IPQ4019 built-in switch support
-
-Qualcomm IPQ40xx SoC-s have a variant of QCA8337N switch built-in.
-
-It shares most of the stuff with its external counterpart, however it is
-modified for the SoC.
-Namely, it doesn't have second CPU port (Port 6), so it has 6 ports
-instead of 7.
-It also has no built-in PHY-s but rather requires external PSGMII based
-companion PHY-s (QCA8072 and QCA8075) for which it first needs to carry
-out calibration before using them.
-PSGMII has a SoC built-in PHY that is used to connect to the PHY-s which
-unfortunately requires some magic values as the datasheet doesnt document
-the bits that are being set or the register at all.
-
-Since its built-in it is MMIO like other peripherals and doesn't have its
-own MDIO bus but depends on the SoC provided one.
-
-CPU connection is at Port 0 and it uses some kind of a internal connection
-and no traditional RGMII/SGMII.
-
-It also doesn't use in-band tagging like other qca8k switches so a out of
-band based tagger is used.
-
-Signed-off-by: Robert Marko <robert.marko@sartura.hr>
----
- drivers/net/dsa/qca/Kconfig | 8 +
- drivers/net/dsa/qca/Makefile | 1 +
- drivers/net/dsa/qca/qca8k-common.c | 6 +-
- drivers/net/dsa/qca/qca8k-ipq4019.c | 948 ++++++++++++++++++++++++++++
- drivers/net/dsa/qca/qca8k.h | 56 ++
- 5 files changed, 1016 insertions(+), 3 deletions(-)
- create mode 100644 drivers/net/dsa/qca/qca8k-ipq4019.c
-
---- a/drivers/net/dsa/qca/Kconfig
-+++ b/drivers/net/dsa/qca/Kconfig
-@@ -23,3 +23,11 @@ config NET_DSA_QCA8K_LEDS_SUPPORT
- help
- This enabled support for LEDs present on the Qualcomm Atheros
- QCA8K Ethernet switch chips.
-+
-+config NET_DSA_QCA8K_IPQ4019
-+ tristate "Qualcomm Atheros IPQ4019 Ethernet switch support"
-+ select NET_DSA_TAG_OOB
-+ select REGMAP_MMIO
-+ help
-+ This enables support for the switch built-into Qualcomm Atheros
-+ IPQ4019 SoCs.
---- a/drivers/net/dsa/qca/Makefile
-+++ b/drivers/net/dsa/qca/Makefile
-@@ -5,3 +5,4 @@ qca8k-y += qca8k-common.o qca8k-8xxx.
- ifdef CONFIG_NET_DSA_QCA8K_LEDS_SUPPORT
- qca8k-y += qca8k-leds.o
- endif
-+obj-$(CONFIG_NET_DSA_QCA8K_IPQ4019) += qca8k-ipq4019.o qca8k-common.o
---- a/drivers/net/dsa/qca/qca8k-common.c
-+++ b/drivers/net/dsa/qca/qca8k-common.c
-@@ -412,7 +412,7 @@ static int qca8k_vlan_del(struct qca8k_p
-
- /* Check if we're the last member to be removed */
- del = true;
-- for (i = 0; i < QCA8K_NUM_PORTS; i++) {
-+ for (i = 0; i < priv->ds->num_ports; i++) {
- mask = QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(i);
-
- if ((reg & mask) != mask) {
-@@ -653,7 +653,7 @@ int qca8k_port_bridge_join(struct dsa_sw
- cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
- port_mask = BIT(cpu_port);
-
-- for (i = 0; i < QCA8K_NUM_PORTS; i++) {
-+ for (i = 0; i < ds->num_ports; i++) {
- if (dsa_is_cpu_port(ds, i))
- continue;
- if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
-@@ -685,7 +685,7 @@ void qca8k_port_bridge_leave(struct dsa_
-
- cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
-
-- for (i = 0; i < QCA8K_NUM_PORTS; i++) {
-+ for (i = 0; i < ds->num_ports; i++) {
- if (dsa_is_cpu_port(ds, i))
- continue;
- if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
---- /dev/null
-+++ b/drivers/net/dsa/qca/qca8k-ipq4019.c
-@@ -0,0 +1,948 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
-+ * Copyright (C) 2011-2012, 2020-2021 Gabor Juhos <juhosg@openwrt.org>
-+ * Copyright (c) 2015, 2019, The Linux Foundation. All rights reserved.
-+ * Copyright (c) 2016 John Crispin <john@phrozen.org>
-+ * Copyright (c) 2022 Robert Marko <robert.marko@sartura.hr>
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/phy.h>
-+#include <linux/netdevice.h>
-+#include <linux/bitfield.h>
-+#include <linux/regmap.h>
-+#include <net/dsa.h>
-+#include <linux/of_net.h>
-+#include <linux/of_mdio.h>
-+#include <linux/of_platform.h>
-+#include <linux/mdio.h>
-+#include <linux/phylink.h>
-+
-+#include "qca8k.h"
-+
-+static struct regmap_config qca8k_ipq4019_regmap_config = {
-+ .reg_bits = 32,
-+ .val_bits = 32,
-+ .reg_stride = 4,
-+ .max_register = 0x16ac, /* end MIB - Port6 range */
-+ .rd_table = &qca8k_readable_table,
-+};
-+
-+static struct regmap_config qca8k_ipq4019_psgmii_phy_regmap_config = {
-+ .name = "psgmii-phy",
-+ .reg_bits = 32,
-+ .val_bits = 32,
-+ .reg_stride = 4,
-+ .max_register = 0x7fc,
-+};
-+
-+static enum dsa_tag_protocol
-+qca8k_ipq4019_get_tag_protocol(struct dsa_switch *ds, int port,
-+ enum dsa_tag_protocol mp)
-+{
-+ return DSA_TAG_PROTO_OOB;
-+}
-+
-+static struct phylink_pcs *
-+qca8k_ipq4019_phylink_mac_select_pcs(struct dsa_switch *ds, int port,
-+ phy_interface_t interface)
-+{
-+ struct qca8k_priv *priv = ds->priv;
-+ struct phylink_pcs *pcs = NULL;
-+
-+ switch (interface) {
-+ case PHY_INTERFACE_MODE_PSGMII:
-+ switch (port) {
-+ case 0:
-+ pcs = &priv->pcs_port_0.pcs;
-+ break;
-+ }
-+ break;
-+ default:
-+ break;
-+ }
-+
-+ return pcs;
-+}
-+
-+static int qca8k_ipq4019_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
-+ phy_interface_t interface,
-+ const unsigned long *advertising,
-+ bool permit_pause_to_mac)
-+{
-+ return 0;
-+}
-+
-+static void qca8k_ipq4019_pcs_an_restart(struct phylink_pcs *pcs)
-+{
-+}
-+
-+static struct qca8k_pcs *pcs_to_qca8k_pcs(struct phylink_pcs *pcs)
-+{
-+ return container_of(pcs, struct qca8k_pcs, pcs);
-+}
-+
-+static void qca8k_ipq4019_pcs_get_state(struct phylink_pcs *pcs,
-+ struct phylink_link_state *state)
-+{
-+ struct qca8k_priv *priv = pcs_to_qca8k_pcs(pcs)->priv;
-+ int port = pcs_to_qca8k_pcs(pcs)->port;
-+ u32 reg;
-+ int ret;
-+
-+ ret = qca8k_read(priv, QCA8K_REG_PORT_STATUS(port), ®);
-+ if (ret < 0) {
-+ state->link = false;
-+ return;
-+ }
-+
-+ state->link = !!(reg & QCA8K_PORT_STATUS_LINK_UP);
-+ state->an_complete = state->link;
-+ state->duplex = (reg & QCA8K_PORT_STATUS_DUPLEX) ? DUPLEX_FULL :
-+ DUPLEX_HALF;
-+
-+ switch (reg & QCA8K_PORT_STATUS_SPEED) {
-+ case QCA8K_PORT_STATUS_SPEED_10:
-+ state->speed = SPEED_10;
-+ break;
-+ case QCA8K_PORT_STATUS_SPEED_100:
-+ state->speed = SPEED_100;
-+ break;
-+ case QCA8K_PORT_STATUS_SPEED_1000:
-+ state->speed = SPEED_1000;
-+ break;
-+ default:
-+ state->speed = SPEED_UNKNOWN;
-+ break;
-+ }
-+
-+ if (reg & QCA8K_PORT_STATUS_RXFLOW)
-+ state->pause |= MLO_PAUSE_RX;
-+ if (reg & QCA8K_PORT_STATUS_TXFLOW)
-+ state->pause |= MLO_PAUSE_TX;
-+}
-+
-+static const struct phylink_pcs_ops qca8k_pcs_ops = {
-+ .pcs_get_state = qca8k_ipq4019_pcs_get_state,
-+ .pcs_config = qca8k_ipq4019_pcs_config,
-+ .pcs_an_restart = qca8k_ipq4019_pcs_an_restart,
-+};
-+
-+static void qca8k_ipq4019_setup_pcs(struct qca8k_priv *priv,
-+ struct qca8k_pcs *qpcs,
-+ int port)
-+{
-+ qpcs->pcs.ops = &qca8k_pcs_ops;
-+
-+ /* We don't have interrupts for link changes, so we need to poll */
-+ qpcs->pcs.poll = true;
-+ qpcs->priv = priv;
-+ qpcs->port = port;
-+}
-+
-+static void qca8k_ipq4019_phylink_get_caps(struct dsa_switch *ds, int port,
-+ struct phylink_config *config)
-+{
-+ switch (port) {
-+ case 0: /* CPU port */
-+ __set_bit(PHY_INTERFACE_MODE_INTERNAL,
-+ config->supported_interfaces);
-+ break;
-+
-+ case 1:
-+ case 2:
-+ case 3:
-+ __set_bit(PHY_INTERFACE_MODE_PSGMII,
-+ config->supported_interfaces);
-+ break;
-+ case 4:
-+ case 5:
-+ phy_interface_set_rgmii(config->supported_interfaces);
-+ __set_bit(PHY_INTERFACE_MODE_PSGMII,
-+ config->supported_interfaces);
-+ break;
-+ }
-+
-+ config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
-+ MAC_10 | MAC_100 | MAC_1000FD;
-+
-+ config->legacy_pre_march2020 = false;
-+}
-+
-+static void
-+qca8k_phylink_ipq4019_mac_link_down(struct dsa_switch *ds, int port,
-+ unsigned int mode,
-+ phy_interface_t interface)
-+{
-+ struct qca8k_priv *priv = ds->priv;
-+
-+ qca8k_port_set_status(priv, port, 0);
-+}
-+
-+static void
-+qca8k_phylink_ipq4019_mac_link_up(struct dsa_switch *ds, int port,
-+ unsigned int mode, phy_interface_t interface,
-+ struct phy_device *phydev, int speed,
-+ int duplex, bool tx_pause, bool rx_pause)
-+{
-+ struct qca8k_priv *priv = ds->priv;
-+ u32 reg;
-+
-+ if (phylink_autoneg_inband(mode)) {
-+ reg = QCA8K_PORT_STATUS_LINK_AUTO;
-+ } else {
-+ switch (speed) {
-+ case SPEED_10:
-+ reg = QCA8K_PORT_STATUS_SPEED_10;
-+ break;
-+ case SPEED_100:
-+ reg = QCA8K_PORT_STATUS_SPEED_100;
-+ break;
-+ case SPEED_1000:
-+ reg = QCA8K_PORT_STATUS_SPEED_1000;
-+ break;
-+ default:
-+ reg = QCA8K_PORT_STATUS_LINK_AUTO;
-+ break;
-+ }
-+
-+ if (duplex == DUPLEX_FULL)
-+ reg |= QCA8K_PORT_STATUS_DUPLEX;
-+
-+ if (rx_pause || dsa_is_cpu_port(ds, port))
-+ reg |= QCA8K_PORT_STATUS_RXFLOW;
-+
-+ if (tx_pause || dsa_is_cpu_port(ds, port))
-+ reg |= QCA8K_PORT_STATUS_TXFLOW;
-+ }
-+
-+ reg |= QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;
-+
-+ qca8k_write(priv, QCA8K_REG_PORT_STATUS(port), reg);
-+}
-+
-+static int psgmii_vco_calibrate(struct qca8k_priv *priv)
-+{
-+ int val, ret;
-+
-+ if (!priv->psgmii_ethphy) {
-+ dev_err(priv->dev, "PSGMII eth PHY missing, calibration failed!\n");
-+ return -ENODEV;
-+ }
-+
-+ /* Fix PSGMII RX 20bit */
-+ ret = phy_write(priv->psgmii_ethphy, MII_BMCR, 0x5b);
-+ /* Reset PHY PSGMII */
-+ ret = phy_write(priv->psgmii_ethphy, MII_BMCR, 0x1b);
-+ /* Release PHY PSGMII reset */
-+ ret = phy_write(priv->psgmii_ethphy, MII_BMCR, 0x5b);
-+
-+ /* Poll for VCO PLL calibration finish - Malibu(QCA8075) */
-+ ret = phy_read_mmd_poll_timeout(priv->psgmii_ethphy,
-+ MDIO_MMD_PMAPMD,
-+ 0x28, val,
-+ (val & BIT(0)),
-+ 10000, 1000000,
-+ false);
-+ if (ret) {
-+ dev_err(priv->dev, "QCA807x PSGMII VCO calibration PLL not ready\n");
-+ return ret;
-+ }
-+ mdelay(50);
-+
-+ /* Freeze PSGMII RX CDR */
-+ ret = phy_write(priv->psgmii_ethphy, MII_RESV2, 0x2230);
-+
-+ /* Start PSGMIIPHY VCO PLL calibration */
-+ ret = regmap_set_bits(priv->psgmii,
-+ PSGMIIPHY_VCO_CALIBRATION_CONTROL_REGISTER_1,
-+ PSGMIIPHY_REG_PLL_VCO_CALIB_RESTART);
-+
-+ /* Poll for PSGMIIPHY PLL calibration finish - Dakota(IPQ40xx) */
-+ ret = regmap_read_poll_timeout(priv->psgmii,
-+ PSGMIIPHY_VCO_CALIBRATION_CONTROL_REGISTER_2,
-+ val, val & PSGMIIPHY_REG_PLL_VCO_CALIB_READY,
-+ 10000, 1000000);
-+ if (ret) {
-+ dev_err(priv->dev, "IPQ PSGMIIPHY VCO calibration PLL not ready\n");
-+ return ret;
-+ }
-+ mdelay(50);
-+
-+ /* Release PSGMII RX CDR */
-+ ret = phy_write(priv->psgmii_ethphy, MII_RESV2, 0x3230);
-+ /* Release PSGMII RX 20bit */
-+ ret = phy_write(priv->psgmii_ethphy, MII_BMCR, 0x5f);
-+ mdelay(200);
-+
-+ return ret;
-+}
-+
-+static void
-+qca8k_switch_port_loopback_on_off(struct qca8k_priv *priv, int port, int on)
-+{
-+ u32 val = QCA8K_PORT_LOOKUP_LOOPBACK_EN;
-+
-+ if (on == 0)
-+ val = 0;
-+
-+ qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
-+ QCA8K_PORT_LOOKUP_LOOPBACK_EN, val);
-+}
-+
-+static int
-+qca8k_wait_for_phy_link_state(struct phy_device *phy, int need_status)
-+{
-+ int a;
-+ u16 status;
-+
-+ for (a = 0; a < 100; a++) {
-+ status = phy_read(phy, MII_QCA8075_SSTATUS);
-+ status &= QCA8075_PHY_SPEC_STATUS_LINK;
-+ status = !!status;
-+ if (status == need_status)
-+ return 0;
-+ mdelay(8);
-+ }
-+
-+ return -1;
-+}
-+
-+static void
-+qca8k_phy_loopback_on_off(struct qca8k_priv *priv, struct phy_device *phy,
-+ int sw_port, int on)
-+{
-+ if (on) {
-+ phy_write(phy, MII_BMCR, BMCR_ANENABLE | BMCR_RESET);
-+ phy_modify(phy, MII_BMCR, BMCR_PDOWN, BMCR_PDOWN);
-+ qca8k_wait_for_phy_link_state(phy, 0);
-+ qca8k_write(priv, QCA8K_REG_PORT_STATUS(sw_port), 0);
-+ phy_write(phy, MII_BMCR,
-+ BMCR_SPEED1000 |
-+ BMCR_FULLDPLX |
-+ BMCR_LOOPBACK);
-+ qca8k_wait_for_phy_link_state(phy, 1);
-+ qca8k_write(priv, QCA8K_REG_PORT_STATUS(sw_port),
-+ QCA8K_PORT_STATUS_SPEED_1000 |
-+ QCA8K_PORT_STATUS_TXMAC |
-+ QCA8K_PORT_STATUS_RXMAC |
-+ QCA8K_PORT_STATUS_DUPLEX);
-+ qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(sw_port),
-+ QCA8K_PORT_LOOKUP_STATE_FORWARD,
-+ QCA8K_PORT_LOOKUP_STATE_FORWARD);
-+ } else { /* off */
-+ qca8k_write(priv, QCA8K_REG_PORT_STATUS(sw_port), 0);
-+ qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(sw_port),
-+ QCA8K_PORT_LOOKUP_STATE_DISABLED,
-+ QCA8K_PORT_LOOKUP_STATE_DISABLED);
-+ phy_write(phy, MII_BMCR, BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_RESET);
-+ /* turn off the power of the phys - so that unused
-+ ports do not raise links */
-+ phy_modify(phy, MII_BMCR, BMCR_PDOWN, BMCR_PDOWN);
-+ }
-+}
-+
-+static void
-+qca8k_phy_pkt_gen_prep(struct qca8k_priv *priv, struct phy_device *phy,
-+ int pkts_num, int on)
-+{
-+ if (on) {
-+ /* enable CRC checker and packets counters */
-+ phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_CRC_AND_PKTS_COUNT, 0);
-+ phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_CRC_AND_PKTS_COUNT,
-+ QCA8075_MMD7_CNT_FRAME_CHK_EN | QCA8075_MMD7_CNT_SELFCLR);
-+ qca8k_wait_for_phy_link_state(phy, 1);
-+ /* packet number */
-+ phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_PKT_GEN_PKT_NUMB, pkts_num);
-+ /* pkt size - 1504 bytes + 20 bytes */
-+ phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_PKT_GEN_PKT_SIZE, 1504);
-+ } else { /* off */
-+ /* packet number */
-+ phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_PKT_GEN_PKT_NUMB, 0);
-+ /* disable CRC checker and packet counter */
-+ phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_CRC_AND_PKTS_COUNT, 0);
-+ /* disable traffic gen */
-+ phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_PKT_GEN_CTRL, 0);
-+ }
-+}
-+
-+static void
-+qca8k_wait_for_phy_pkt_gen_fin(struct qca8k_priv *priv, struct phy_device *phy)
-+{
-+ int val;
-+ /* wait for all traffic end: 4096(pkt num)*1524(size)*8ns(125MHz)=49938us */
-+ phy_read_mmd_poll_timeout(phy, MDIO_MMD_AN, QCA8075_MMD7_PKT_GEN_CTRL,
-+ val, !(val & QCA8075_MMD7_PKT_GEN_INPROGR),
-+ 50000, 1000000, true);
-+}
-+
-+static void
-+qca8k_start_phy_pkt_gen(struct phy_device *phy)
-+{
-+ /* start traffic gen */
-+ phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_PKT_GEN_CTRL,
-+ QCA8075_MMD7_PKT_GEN_START | QCA8075_MMD7_PKT_GEN_INPROGR);
-+}
-+
-+static int
-+qca8k_start_all_phys_pkt_gens(struct qca8k_priv *priv)
-+{
-+ struct phy_device *phy;
-+ phy = phy_device_create(priv->bus, QCA8075_MDIO_BRDCST_PHY_ADDR,
-+ 0, 0, NULL);
-+ if (!phy) {
-+ dev_err(priv->dev, "unable to create mdio broadcast PHY(0x%x)\n",
-+ QCA8075_MDIO_BRDCST_PHY_ADDR);
-+ return -ENODEV;
-+ }
-+
-+ qca8k_start_phy_pkt_gen(phy);
-+
-+ phy_device_free(phy);
-+ return 0;
-+}
-+
-+static int
-+qca8k_get_phy_pkt_gen_test_result(struct phy_device *phy, int pkts_num)
-+{
-+ u32 tx_ok, tx_error;
-+ u32 rx_ok, rx_error;
-+ u32 tx_ok_high16;
-+ u32 rx_ok_high16;
-+ u32 tx_all_ok, rx_all_ok;
-+
-+ /* check counters */
-+ tx_ok = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_EG_FRAME_RECV_CNT_LO);
-+ tx_ok_high16 = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_EG_FRAME_RECV_CNT_HI);
-+ tx_error = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_EG_FRAME_ERR_CNT);
-+ rx_ok = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_IG_FRAME_RECV_CNT_LO);
-+ rx_ok_high16 = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_IG_FRAME_RECV_CNT_HI);
-+ rx_error = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_IG_FRAME_ERR_CNT);
-+ tx_all_ok = tx_ok + (tx_ok_high16 << 16);
-+ rx_all_ok = rx_ok + (rx_ok_high16 << 16);
-+
-+ if (tx_all_ok < pkts_num)
-+ return -1;
-+ if(rx_all_ok < pkts_num)
-+ return -2;
-+ if(tx_error)
-+ return -3;
-+ if(rx_error)
-+ return -4;
-+ return 0; /* test is ok */
-+}
-+
-+static
-+void qca8k_phy_broadcast_write_on_off(struct qca8k_priv *priv,
-+ struct phy_device *phy, int on)
-+{
-+ u32 val;
-+
-+ val = phy_read_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_MDIO_BRDCST_WRITE);
-+
-+ if (on == 0)
-+ val &= ~QCA8075_MMD7_MDIO_BRDCST_WRITE_EN;
-+ else
-+ val |= QCA8075_MMD7_MDIO_BRDCST_WRITE_EN;
-+
-+ phy_write_mmd(phy, MDIO_MMD_AN, QCA8075_MMD7_MDIO_BRDCST_WRITE, val);
-+}
-+
-+static int
-+qca8k_test_dsa_port_for_errors(struct qca8k_priv *priv, struct phy_device *phy,
-+ int port, int test_phase)
-+{
-+ int res = 0;
-+ const int test_pkts_num = QCA8075_PKT_GEN_PKTS_COUNT;
-+
-+ if (test_phase == 1) { /* start test preps */
-+ qca8k_phy_loopback_on_off(priv, phy, port, 1);
-+ qca8k_switch_port_loopback_on_off(priv, port, 1);
-+ qca8k_phy_broadcast_write_on_off(priv, phy, 1);
-+ qca8k_phy_pkt_gen_prep(priv, phy, test_pkts_num, 1);
-+ } else if (test_phase == 2) {
-+ /* wait for test results, collect it and cleanup */
-+ qca8k_wait_for_phy_pkt_gen_fin(priv, phy);
-+ res = qca8k_get_phy_pkt_gen_test_result(phy, test_pkts_num);
-+ qca8k_phy_pkt_gen_prep(priv, phy, test_pkts_num, 0);
-+ qca8k_phy_broadcast_write_on_off(priv, phy, 0);
-+ qca8k_switch_port_loopback_on_off(priv, port, 0);
-+ qca8k_phy_loopback_on_off(priv, phy, port, 0);
-+ }
-+
-+ return res;
-+}
-+
-+static int
-+qca8k_do_dsa_sw_ports_self_test(struct qca8k_priv *priv, int parallel_test)
-+{
-+ struct device_node *dn = priv->dev->of_node;
-+ struct device_node *ports, *port;
-+ struct device_node *phy_dn;
-+ struct phy_device *phy;
-+ int reg, err = 0, test_phase;
-+ u32 tests_result = 0;
-+
-+ ports = of_get_child_by_name(dn, "ports");
-+ if (!ports) {
-+ dev_err(priv->dev, "no ports child node found\n");
-+ return -EINVAL;
-+ }
-+
-+ for (test_phase = 1; test_phase <= 2; test_phase++) {
-+ if (parallel_test && test_phase == 2) {
-+ err = qca8k_start_all_phys_pkt_gens(priv);
-+ if (err)
-+ goto error;
-+ }
-+ for_each_available_child_of_node(ports, port) {
-+ err = of_property_read_u32(port, "reg", ®);
-+ if (err)
-+ goto error;
-+ if (reg >= QCA8K_NUM_PORTS) {
-+ err = -EINVAL;
-+ goto error;
-+ }
-+ phy_dn = of_parse_phandle(port, "phy-handle", 0);
-+ if (phy_dn) {
-+ phy = of_phy_find_device(phy_dn);
-+ of_node_put(phy_dn);
-+ if (phy) {
-+ int result;
-+ result = qca8k_test_dsa_port_for_errors(priv,
-+ phy, reg, test_phase);
-+ if (!parallel_test && test_phase == 1)
-+ qca8k_start_phy_pkt_gen(phy);
-+ put_device(&phy->mdio.dev);
-+ if (test_phase == 2) {
-+ tests_result <<= 1;
-+ if (result)
-+ tests_result |= 1;
-+ }
-+ }
-+ }
-+ }
-+ }
-+
-+end:
-+ of_node_put(ports);
-+ qca8k_fdb_flush(priv);
-+ return tests_result;
-+error:
-+ tests_result |= 0xf000;
-+ goto end;
-+}
-+
-+static int
-+psgmii_vco_calibrate_and_test(struct dsa_switch *ds)
-+{
-+ int ret, a, test_result;
-+ struct qca8k_priv *priv = ds->priv;
-+
-+ for (a = 0; a <= QCA8K_PSGMII_CALB_NUM; a++) {
-+ ret = psgmii_vco_calibrate(priv);
-+ if (ret)
-+ return ret;
-+ /* first we run serial test */
-+ test_result = qca8k_do_dsa_sw_ports_self_test(priv, 0);
-+ /* and if it is ok then we run the test in parallel */
-+ if (!test_result)
-+ test_result = qca8k_do_dsa_sw_ports_self_test(priv, 1);
-+ if (!test_result) {
-+ if (a > 0) {
-+ dev_warn(priv->dev, "PSGMII work was stabilized after %d "
-+ "calibration retries !\n", a);
-+ }
-+ return 0;
-+ } else {
-+ schedule();
-+ if (a > 0 && a % 10 == 0) {
-+ dev_err(priv->dev, "PSGMII work is unstable !!! "
-+ "Let's try to wait a bit ... %d\n", a);
-+ set_current_state(TASK_INTERRUPTIBLE);
-+ schedule_timeout(msecs_to_jiffies(a * 100));
-+ }
-+ }
-+ }
-+
-+ panic("PSGMII work is unstable !!! "
-+ "Repeated recalibration attempts did not help(0x%x) !\n",
-+ test_result);
-+
-+ return -EFAULT;
-+}
-+
-+static int
-+ipq4019_psgmii_configure(struct dsa_switch *ds)
-+{
-+ struct qca8k_priv *priv = ds->priv;
-+ int ret;
-+
-+ if (!priv->psgmii_calibrated) {
-+ dev_info(ds->dev, "PSGMII calibration!\n");
-+ ret = psgmii_vco_calibrate_and_test(ds);
-+
-+ ret = regmap_clear_bits(priv->psgmii, PSGMIIPHY_MODE_CONTROL,
-+ PSGMIIPHY_MODE_ATHR_CSCO_MODE_25M);
-+ ret = regmap_write(priv->psgmii, PSGMIIPHY_TX_CONTROL,
-+ PSGMIIPHY_TX_CONTROL_MAGIC_VALUE);
-+
-+ priv->psgmii_calibrated = true;
-+
-+ return ret;
-+ }
-+
-+ return 0;
-+}
-+
-+static void
-+qca8k_phylink_ipq4019_mac_config(struct dsa_switch *ds, int port,
-+ unsigned int mode,
-+ const struct phylink_link_state *state)
-+{
-+ struct qca8k_priv *priv = ds->priv;
-+
-+ switch (port) {
-+ case 0:
-+ /* CPU port, no configuration needed */
-+ return;
-+ case 1:
-+ case 2:
-+ case 3:
-+ if (state->interface == PHY_INTERFACE_MODE_PSGMII)
-+ if (ipq4019_psgmii_configure(ds))
-+ dev_err(ds->dev, "PSGMII configuration failed!\n");
-+ return;
-+ case 4:
-+ case 5:
-+ if (state->interface == PHY_INTERFACE_MODE_RGMII ||
-+ state->interface == PHY_INTERFACE_MODE_RGMII_ID ||
-+ state->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
-+ state->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
-+ regmap_set_bits(priv->regmap,
-+ QCA8K_IPQ4019_REG_RGMII_CTRL,
-+ QCA8K_IPQ4019_RGMII_CTRL_CLK);
-+ }
-+
-+ if (state->interface == PHY_INTERFACE_MODE_PSGMII)
-+ if (ipq4019_psgmii_configure(ds))
-+ dev_err(ds->dev, "PSGMII configuration failed!\n");
-+ return;
-+ default:
-+ dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port);
-+ return;
-+ }
-+}
-+
-+static int
-+qca8k_ipq4019_setup_port(struct dsa_switch *ds, int port)
-+{
-+ struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
-+ int ret;
-+
-+ /* CPU port gets connected to all user ports of the switch */
-+ if (dsa_is_cpu_port(ds, port)) {
-+ ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
-+ QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds));
-+ if (ret)
-+ return ret;
-+
-+ /* Disable CPU ARP Auto-learning by default */
-+ ret = regmap_clear_bits(priv->regmap,
-+ QCA8K_PORT_LOOKUP_CTRL(port),
-+ QCA8K_PORT_LOOKUP_LEARN);
-+ if (ret)
-+ return ret;
-+ }
-+
-+ /* Individual user ports get connected to CPU port only */
-+ if (dsa_is_user_port(ds, port)) {
-+ ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
-+ QCA8K_PORT_LOOKUP_MEMBER,
-+ BIT(QCA8K_IPQ4019_CPU_PORT));
-+ if (ret)
-+ return ret;
-+
-+ /* Enable ARP Auto-learning by default */
-+ ret = regmap_set_bits(priv->regmap, QCA8K_PORT_LOOKUP_CTRL(port),
-+ QCA8K_PORT_LOOKUP_LEARN);
-+ if (ret)
-+ return ret;
-+
-+ /* For port based vlans to work we need to set the
-+ * default egress vid
-+ */
-+ ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(port),
-+ QCA8K_EGREES_VLAN_PORT_MASK(port),
-+ QCA8K_EGREES_VLAN_PORT(port, QCA8K_PORT_VID_DEF));
-+ if (ret)
-+ return ret;
-+
-+ ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(port),
-+ QCA8K_PORT_VLAN_CVID(QCA8K_PORT_VID_DEF) |
-+ QCA8K_PORT_VLAN_SVID(QCA8K_PORT_VID_DEF));
-+ if (ret)
-+ return ret;
-+ }
-+
-+ return 0;
-+}
-+
-+static int
-+qca8k_ipq4019_setup(struct dsa_switch *ds)
-+{
-+ struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
-+ int ret, i;
-+
-+ /* Make sure that port 0 is the cpu port */
-+ if (!dsa_is_cpu_port(ds, QCA8K_IPQ4019_CPU_PORT)) {
-+ dev_err(priv->dev, "port %d is not the CPU port",
-+ QCA8K_IPQ4019_CPU_PORT);
-+ return -EINVAL;
-+ }
-+
-+ qca8k_ipq4019_setup_pcs(priv, &priv->pcs_port_0, 0);
-+
-+ /* Enable CPU Port */
-+ ret = regmap_set_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0,
-+ QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
-+ if (ret) {
-+ dev_err(priv->dev, "failed enabling CPU port");
-+ return ret;
-+ }
-+
-+ /* Enable MIB counters */
-+ ret = qca8k_mib_init(priv);
-+ if (ret)
-+ dev_warn(priv->dev, "MIB init failed");
-+
-+ /* Disable forwarding by default on all ports */
-+ for (i = 0; i < QCA8K_IPQ4019_NUM_PORTS; i++) {
-+ ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
-+ QCA8K_PORT_LOOKUP_MEMBER, 0);
-+ if (ret)
-+ return ret;
-+ }
-+
-+ /* Enable QCA header mode on the CPU port */
-+ ret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(QCA8K_IPQ4019_CPU_PORT),
-+ FIELD_PREP(QCA8K_PORT_HDR_CTRL_TX_MASK, QCA8K_PORT_HDR_CTRL_ALL) |
-+ FIELD_PREP(QCA8K_PORT_HDR_CTRL_RX_MASK, QCA8K_PORT_HDR_CTRL_ALL));
-+ if (ret) {
-+ dev_err(priv->dev, "failed enabling QCA header mode");
-+ return ret;
-+ }
-+
-+ /* Disable MAC by default on all ports */
-+ for (i = 0; i < QCA8K_IPQ4019_NUM_PORTS; i++) {
-+ if (dsa_is_user_port(ds, i))
-+ qca8k_port_set_status(priv, i, 0);
-+ }
-+
-+ /* Forward all unknown frames to CPU port for Linux processing */
-+ ret = qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,
-+ FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_MASK, BIT(QCA8K_IPQ4019_CPU_PORT)) |
-+ FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_BC_DP_MASK, BIT(QCA8K_IPQ4019_CPU_PORT)) |
-+ FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_MC_DP_MASK, BIT(QCA8K_IPQ4019_CPU_PORT)) |
-+ FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_UC_DP_MASK, BIT(QCA8K_IPQ4019_CPU_PORT)));
-+ if (ret)
-+ return ret;
-+
-+ /* Setup connection between CPU port & user ports */
-+ for (i = 0; i < QCA8K_IPQ4019_NUM_PORTS; i++) {
-+ ret = qca8k_ipq4019_setup_port(ds, i);
-+ if (ret)
-+ return ret;
-+ }
-+
-+ /* Setup our port MTUs to match power on defaults */
-+ ret = qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, ETH_FRAME_LEN + ETH_FCS_LEN);
-+ if (ret)
-+ dev_warn(priv->dev, "failed setting MTU settings");
-+
-+ /* Flush the FDB table */
-+ qca8k_fdb_flush(priv);
-+
-+ /* Set min a max ageing value supported */
-+ ds->ageing_time_min = 7000;
-+ ds->ageing_time_max = 458745000;
-+
-+ /* Set max number of LAGs supported */
-+ ds->num_lag_ids = QCA8K_NUM_LAGS;
-+
-+ /* CPU port HW learning doesnt work correctly, so let DSA handle it */
-+ ds->assisted_learning_on_cpu_port = true;
-+
-+ return 0;
-+}
-+
-+static const struct dsa_switch_ops qca8k_ipq4019_switch_ops = {
-+ .get_tag_protocol = qca8k_ipq4019_get_tag_protocol,
-+ .setup = qca8k_ipq4019_setup,
-+ .get_strings = qca8k_get_strings,
-+ .get_ethtool_stats = qca8k_get_ethtool_stats,
-+ .get_sset_count = qca8k_get_sset_count,
-+ .set_ageing_time = qca8k_set_ageing_time,
-+ .get_mac_eee = qca8k_get_mac_eee,
-+ .set_mac_eee = qca8k_set_mac_eee,
-+ .port_enable = qca8k_port_enable,
-+ .port_disable = qca8k_port_disable,
-+ .port_change_mtu = qca8k_port_change_mtu,
-+ .port_max_mtu = qca8k_port_max_mtu,
-+ .port_stp_state_set = qca8k_port_stp_state_set,
-+ .port_bridge_join = qca8k_port_bridge_join,
-+ .port_bridge_leave = qca8k_port_bridge_leave,
-+ .port_fast_age = qca8k_port_fast_age,
-+ .port_fdb_add = qca8k_port_fdb_add,
-+ .port_fdb_del = qca8k_port_fdb_del,
-+ .port_fdb_dump = qca8k_port_fdb_dump,
-+ .port_mdb_add = qca8k_port_mdb_add,
-+ .port_mdb_del = qca8k_port_mdb_del,
-+ .port_mirror_add = qca8k_port_mirror_add,
-+ .port_mirror_del = qca8k_port_mirror_del,
-+ .port_vlan_filtering = qca8k_port_vlan_filtering,
-+ .port_vlan_add = qca8k_port_vlan_add,
-+ .port_vlan_del = qca8k_port_vlan_del,
-+ .phylink_mac_select_pcs = qca8k_ipq4019_phylink_mac_select_pcs,
-+ .phylink_get_caps = qca8k_ipq4019_phylink_get_caps,
-+ .phylink_mac_config = qca8k_phylink_ipq4019_mac_config,
-+ .phylink_mac_link_down = qca8k_phylink_ipq4019_mac_link_down,
-+ .phylink_mac_link_up = qca8k_phylink_ipq4019_mac_link_up,
-+ .port_lag_join = qca8k_port_lag_join,
-+ .port_lag_leave = qca8k_port_lag_leave,
-+};
-+
-+static const struct qca8k_match_data ipq4019 = {
-+ .id = QCA8K_ID_IPQ4019,
-+ .mib_count = QCA8K_QCA833X_MIB_COUNT,
-+};
-+
-+static int
-+qca8k_ipq4019_probe(struct platform_device *pdev)
-+{
-+ struct device *dev = &pdev->dev;
-+ struct qca8k_priv *priv;
-+ void __iomem *base, *psgmii;
-+ struct device_node *np = dev->of_node, *mdio_np, *psgmii_ethphy_np;
-+ int ret;
-+
-+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
-+ if (!priv)
-+ return -ENOMEM;
-+
-+ priv->dev = dev;
-+ priv->info = &ipq4019;
-+
-+ /* Start by setting up the register mapping */
-+ base = devm_platform_ioremap_resource_byname(pdev, "base");
-+ if (IS_ERR(base))
-+ return PTR_ERR(base);
-+
-+ priv->regmap = devm_regmap_init_mmio(dev, base,
-+ &qca8k_ipq4019_regmap_config);
-+ if (IS_ERR(priv->regmap)) {
-+ ret = PTR_ERR(priv->regmap);
-+ dev_err(dev, "base regmap initialization failed, %d\n", ret);
-+ return ret;
-+ }
-+
-+ psgmii = devm_platform_ioremap_resource_byname(pdev, "psgmii_phy");
-+ if (IS_ERR(psgmii))
-+ return PTR_ERR(psgmii);
-+
-+ priv->psgmii = devm_regmap_init_mmio(dev, psgmii,
-+ &qca8k_ipq4019_psgmii_phy_regmap_config);
-+ if (IS_ERR(priv->psgmii)) {
-+ ret = PTR_ERR(priv->psgmii);
-+ dev_err(dev, "PSGMII regmap initialization failed, %d\n", ret);
-+ return ret;
-+ }
-+
-+ mdio_np = of_parse_phandle(np, "mdio", 0);
-+ if (!mdio_np) {
-+ dev_err(dev, "unable to get MDIO bus phandle\n");
-+ of_node_put(mdio_np);
-+ return -EINVAL;
-+ }
-+
-+ priv->bus = of_mdio_find_bus(mdio_np);
-+ of_node_put(mdio_np);
-+ if (!priv->bus) {
-+ dev_err(dev, "unable to find MDIO bus\n");
-+ return -EPROBE_DEFER;
-+ }
-+
-+ psgmii_ethphy_np = of_parse_phandle(np, "psgmii-ethphy", 0);
-+ if (!psgmii_ethphy_np) {
-+ dev_dbg(dev, "unable to get PSGMII eth PHY phandle\n");
-+ of_node_put(psgmii_ethphy_np);
-+ }
-+
-+ if (psgmii_ethphy_np) {
-+ priv->psgmii_ethphy = of_phy_find_device(psgmii_ethphy_np);
-+ of_node_put(psgmii_ethphy_np);
-+ if (!priv->psgmii_ethphy) {
-+ dev_err(dev, "unable to get PSGMII eth PHY\n");
-+ return -ENODEV;
-+ }
-+ }
-+
-+ /* Check the detected switch id */
-+ ret = qca8k_read_switch_id(priv);
-+ if (ret)
-+ return ret;
-+
-+ priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL);
-+ if (!priv->ds)
-+ return -ENOMEM;
-+
-+ priv->ds->dev = dev;
-+ priv->ds->num_ports = QCA8K_IPQ4019_NUM_PORTS;
-+ priv->ds->priv = priv;
-+ priv->ds->ops = &qca8k_ipq4019_switch_ops;
-+ mutex_init(&priv->reg_mutex);
-+ platform_set_drvdata(pdev, priv);
-+
-+ return dsa_register_switch(priv->ds);
-+}
-+
-+static int
-+qca8k_ipq4019_remove(struct platform_device *pdev)
-+{
-+ struct qca8k_priv *priv = dev_get_drvdata(&pdev->dev);
-+ int i;
-+
-+ if (!priv)
-+ return 0;
-+
-+ for (i = 0; i < QCA8K_IPQ4019_NUM_PORTS; i++)
-+ qca8k_port_set_status(priv, i, 0);
-+
-+ dsa_unregister_switch(priv->ds);
-+
-+ platform_set_drvdata(pdev, NULL);
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id qca8k_ipq4019_of_match[] = {
-+ { .compatible = "qca,ipq4019-qca8337n", },
-+ { /* sentinel */ },
-+};
-+
-+static struct platform_driver qca8k_ipq4019_driver = {
-+ .probe = qca8k_ipq4019_probe,
-+ .remove = qca8k_ipq4019_remove,
-+ .driver = {
-+ .name = "qca8k-ipq4019",
-+ .of_match_table = qca8k_ipq4019_of_match,
-+ },
-+};
-+
-+module_platform_driver(qca8k_ipq4019_driver);
-+
-+MODULE_AUTHOR("Mathieu Olivari, John Crispin <john@phrozen.org>");
-+MODULE_AUTHOR("Gabor Juhos <j4g8y7@gmail.com>, Robert Marko <robert.marko@sartura.hr>");
-+MODULE_DESCRIPTION("Qualcomm IPQ4019 built-in switch driver");
-+MODULE_LICENSE("GPL");
---- a/drivers/net/dsa/qca/qca8k.h
-+++ b/drivers/net/dsa/qca/qca8k.h
-@@ -19,7 +19,10 @@
- #define QCA8K_ETHERNET_TIMEOUT 5
-
- #define QCA8K_NUM_PORTS 7
-+#define QCA8K_IPQ4019_NUM_PORTS 6
- #define QCA8K_NUM_CPU_PORTS 2
-+#define QCA8K_IPQ4019_NUM_CPU_PORTS 1
-+#define QCA8K_IPQ4019_CPU_PORT 0
- #define QCA8K_MAX_MTU 9000
- #define QCA8K_NUM_LAGS 4
- #define QCA8K_NUM_PORTS_FOR_LAG 4
-@@ -28,6 +31,7 @@
- #define QCA8K_ID_QCA8327 0x12
- #define PHY_ID_QCA8337 0x004dd036
- #define QCA8K_ID_QCA8337 0x13
-+#define QCA8K_ID_IPQ4019 0x14
-
- #define QCA8K_QCA832X_MIB_COUNT 39
- #define QCA8K_QCA833X_MIB_COUNT 41
-@@ -265,6 +269,7 @@
- #define QCA8K_PORT_LOOKUP_STATE_LEARNING QCA8K_PORT_LOOKUP_STATE(0x3)
- #define QCA8K_PORT_LOOKUP_STATE_FORWARD QCA8K_PORT_LOOKUP_STATE(0x4)
- #define QCA8K_PORT_LOOKUP_LEARN BIT(20)
-+#define QCA8K_PORT_LOOKUP_LOOPBACK_EN BIT(21)
- #define QCA8K_PORT_LOOKUP_ING_MIRROR_EN BIT(25)
-
- #define QCA8K_REG_GOL_TRUNK_CTRL0 0x700
-@@ -341,6 +346,53 @@
- #define MII_ATH_MMD_ADDR 0x0d
- #define MII_ATH_MMD_DATA 0x0e
-
-+/* IPQ4019 PSGMII PHY registers */
-+#define QCA8K_IPQ4019_REG_RGMII_CTRL 0x004
-+#define QCA8K_IPQ4019_RGMII_CTRL_RGMII_RXC GENMASK(1, 0)
-+#define QCA8K_IPQ4019_RGMII_CTRL_RGMII_TXC GENMASK(9, 8)
-+/* Some kind of CLK selection
-+ * 0: gcc_ess_dly2ns
-+ * 1: gcc_ess_clk
-+ */
-+#define QCA8K_IPQ4019_RGMII_CTRL_CLK BIT(10)
-+#define QCA8K_IPQ4019_RGMII_CTRL_DELAY_RMII0 GENMASK(17, 16)
-+#define QCA8K_IPQ4019_RGMII_CTRL_INVERT_RMII0_REF_CLK BIT(18)
-+#define QCA8K_IPQ4019_RGMII_CTRL_DELAY_RMII1 GENMASK(20, 19)
-+#define QCA8K_IPQ4019_RGMII_CTRL_INVERT_RMII1_REF_CLK BIT(21)
-+#define QCA8K_IPQ4019_RGMII_CTRL_INVERT_RMII0_MASTER_EN BIT(24)
-+#define QCA8K_IPQ4019_RGMII_CTRL_INVERT_RMII1_MASTER_EN BIT(25)
-+
-+#define PSGMIIPHY_MODE_CONTROL 0x1b4
-+#define PSGMIIPHY_MODE_ATHR_CSCO_MODE_25M BIT(0)
-+#define PSGMIIPHY_TX_CONTROL 0x288
-+#define PSGMIIPHY_TX_CONTROL_MAGIC_VALUE 0x8380
-+#define PSGMIIPHY_VCO_CALIBRATION_CONTROL_REGISTER_1 0x9c
-+#define PSGMIIPHY_REG_PLL_VCO_CALIB_RESTART BIT(14)
-+#define PSGMIIPHY_VCO_CALIBRATION_CONTROL_REGISTER_2 0xa0
-+#define PSGMIIPHY_REG_PLL_VCO_CALIB_READY BIT(0)
-+
-+#define QCA8K_PSGMII_CALB_NUM 100
-+#define MII_QCA8075_SSTATUS 0x11
-+#define QCA8075_PHY_SPEC_STATUS_LINK BIT(10)
-+#define QCA8075_MMD7_CRC_AND_PKTS_COUNT 0x8029
-+#define QCA8075_MMD7_PKT_GEN_PKT_NUMB 0x8021
-+#define QCA8075_MMD7_PKT_GEN_PKT_SIZE 0x8062
-+#define QCA8075_MMD7_PKT_GEN_CTRL 0x8020
-+#define QCA8075_MMD7_CNT_SELFCLR BIT(1)
-+#define QCA8075_MMD7_CNT_FRAME_CHK_EN BIT(0)
-+#define QCA8075_MMD7_PKT_GEN_START BIT(13)
-+#define QCA8075_MMD7_PKT_GEN_INPROGR BIT(15)
-+#define QCA8075_MMD7_IG_FRAME_RECV_CNT_HI 0x802a
-+#define QCA8075_MMD7_IG_FRAME_RECV_CNT_LO 0x802b
-+#define QCA8075_MMD7_IG_FRAME_ERR_CNT 0x802c
-+#define QCA8075_MMD7_EG_FRAME_RECV_CNT_HI 0x802d
-+#define QCA8075_MMD7_EG_FRAME_RECV_CNT_LO 0x802e
-+#define QCA8075_MMD7_EG_FRAME_ERR_CNT 0x802f
-+#define QCA8075_MMD7_MDIO_BRDCST_WRITE 0x8028
-+#define QCA8075_MMD7_MDIO_BRDCST_WRITE_EN BIT(15)
-+#define QCA8075_MDIO_BRDCST_PHY_ADDR 0x1f
-+#define QCA8075_PKT_GEN_PKTS_COUNT 4096
-+
- enum {
- QCA8K_PORT_SPEED_10M = 0,
- QCA8K_PORT_SPEED_100M = 1,
-@@ -466,6 +518,10 @@ struct qca8k_priv {
- struct qca8k_pcs pcs_port_6;
- const struct qca8k_match_data *info;
- struct qca8k_led ports_led[QCA8K_LED_COUNT];
-+ /* IPQ4019 specific */
-+ struct regmap *psgmii;
-+ struct phy_device *psgmii_ethphy;
-+ bool psgmii_calibrated;
- };
-
- struct qca8k_mib_desc {
+++ /dev/null
-From 19c507c3fe4a6fc60317dcae2c55de452aecb7d5 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robert.marko@sartura.hr>
-Date: Mon, 1 Nov 2021 18:15:04 +0100
-Subject: [PATCH] arm: dts: ipq4019: add switch node
-
-Since the built-in IPQ40xx switch now has a driver, add the required node
-for it to work.
-
-Signed-off-by: Robert Marko <robert.marko@sartura.hr>
----
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 76 +++++++++++++++++++++++++++++
- 1 file changed, 76 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -594,6 +594,82 @@
- status = "disabled";
- };
-
-+ switch: switch@c000000 {
-+ compatible = "qca,ipq4019-qca8337n";
-+ reg = <0xc000000 0x80000>, <0x98000 0x800>;
-+ reg-names = "base", "psgmii_phy";
-+ resets = <&gcc ESS_PSGMII_ARES>;
-+ reset-names = "psgmii_rst";
-+ mdio = <&mdio>;
-+ psgmii-ethphy = <&psgmiiphy>;
-+
-+ status = "disabled";
-+
-+ ports {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ port@0 { /* MAC0 */
-+ reg = <0>;
-+ label = "cpu";
-+ ethernet = <&gmac>;
-+ phy-mode = "internal";
-+
-+ fixed-link {
-+ speed = <1000>;
-+ full-duplex;
-+ pause;
-+ asym-pause;
-+ };
-+ };
-+
-+ swport1: port@1 { /* MAC1 */
-+ reg = <1>;
-+ label = "lan1";
-+ phy-handle = <ðphy0>;
-+ phy-mode = "psgmii";
-+
-+ status = "disabled";
-+ };
-+
-+ swport2: port@2 { /* MAC2 */
-+ reg = <2>;
-+ label = "lan2";
-+ phy-handle = <ðphy1>;
-+ phy-mode = "psgmii";
-+
-+ status = "disabled";
-+ };
-+
-+ swport3: port@3 { /* MAC3 */
-+ reg = <3>;
-+ label = "lan3";
-+ phy-handle = <ðphy2>;
-+ phy-mode = "psgmii";
-+
-+ status = "disabled";
-+ };
-+
-+ swport4: port@4 { /* MAC4 */
-+ reg = <4>;
-+ label = "lan4";
-+ phy-handle = <ðphy3>;
-+ phy-mode = "psgmii";
-+
-+ status = "disabled";
-+ };
-+
-+ swport5: port@5 { /* MAC5 */
-+ reg = <5>;
-+ label = "wan";
-+ phy-handle = <ðphy4>;
-+ phy-mode = "psgmii";
-+
-+ status = "disabled";
-+ };
-+ };
-+ };
-+
- gmac: ethernet@c080000 {
- compatible = "qcom,ipq4019-ess-edma";
- reg = <0xc080000 0x8000>;
+++ /dev/null
-From 5ac078c8fe18f3e8318547b8ed0ed782730c5039 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Sat, 10 Feb 2024 22:28:27 +0100
-Subject: [PATCH] ARM: dts: qcom: ipq4019: add QCA8075 PHY Package nodes
-
-Add QCA8075 PHY Package nodes. The PHY nodes that were previously
-defined never worked and actually never had a driver to correctly setup
-these PHY. Now that we have a correct driver, correctly add the PHY
-Package node and set the default value of 300mw for tx driver strength
-following specification of ipq4019 SoC.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- arch/arm/boot/dts//qcom-ipq4019.dtsi | 35 +++++++++++++++---------
- 1 file changed, 22 insertions(+), 13 deletions(-)
-
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -725,24 +725,33 @@
- reg = <0x90000 0x64>;
- status = "disabled";
-
-- ethphy0: ethernet-phy@0 {
-+ ethernet-phy-package@0 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ compatible = "qcom,qca8075-package";
- reg = <0>;
-- };
--
-- ethphy1: ethernet-phy@1 {
-- reg = <1>;
-- };
-
-- ethphy2: ethernet-phy@2 {
-- reg = <2>;
-- };
--
-- ethphy3: ethernet-phy@3 {
-- reg = <3>;
-- };
-+ qcom,tx-drive-strength-milliwatt = <300>;
-
-- ethphy4: ethernet-phy@4 {
-- reg = <4>;
-+ ethphy0: ethernet-phy@0 {
-+ reg = <0>;
-+ };
-+
-+ ethphy1: ethernet-phy@1 {
-+ reg = <1>;
-+ };
-+
-+ ethphy2: ethernet-phy@2 {
-+ reg = <2>;
-+ };
-+
-+ ethphy3: ethernet-phy@3 {
-+ reg = <3>;
-+ };
-+
-+ ethphy4: ethernet-phy@4 {
-+ reg = <4>;
-+ };
- };
- };
-
+++ /dev/null
-From 79b38b9f85da868ca59b66715c20aa55104b640b Mon Sep 17 00:00:00 2001
-From: Robert Marko <robert.marko@sartura.hr>
-Date: Fri, 2 Oct 2020 10:43:26 +0200
-Subject: [PATCH] arm: dts: ipq4019: QCA807x properties
-
-This adds necessary DT properties for QCA807x PHY-s to IPQ4019 DTSI.
-
-Signed-off-by: Robert Marko <robert.marko@sartura.hr>
----
- arch/arm/boot/dts/qcom-ipq4019.dtsi | 17 +++++++++++++++++
- 1 file changed, 17 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
-@@ -752,6 +752,10 @@
- ethphy4: ethernet-phy@4 {
- reg = <4>;
- };
-+
-+ psgmiiphy: psgmii-phy@5 {
-+ reg = <5>;
-+ };
- };
- };
-
+++ /dev/null
-From d0055b03d9c8d48ad2b971821989b09ba95c39f8 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Sun, 17 Sep 2023 20:18:31 +0200
-Subject: [PATCH] net: qualcomm: ipqess: fix TX timeout errors
-
-Currently logic to handle napi tx completion is flawed and on the long
-run on loaded condition cause TX timeout error with the queue not being
-able to handle any new packet.
-
-There are 2 main cause of this:
-- incrementing the packet done value wrongly
-- handling 2 times the tx_ring tail
-
-ipqess_tx_unmap_and_free may return 2 kind values:
-- 0: we are handling first and middle descriptor for the packet
-- packet len: we are at the last descriptor for the packet
-
-Done value was wrongly incremented also for first and intermediate
-descriptor for the packet resulting causing panic and TX timeouts by
-comunicating to the kernel an inconsistent value of packet handling not
-matching the expected ones.
-
-Tx_ring tail was handled twice for ipqess_tx_complete run resulting in
-again done value incremented wrongly and also problem with idx handling
-by actually skipping descriptor for some packets.
-
-Rework the loop logic to fix these 2 problem and also add some comments
-to make sure ipqess_tx_unmap_and_free ret value is better
-understandable.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- drivers/net/ethernet/qualcomm/ipqess/ipqess.c | 13 ++++++++++---
- 1 file changed, 10 insertions(+), 3 deletions(-)
-
---- a/drivers/net/ethernet/qualcomm/ipqess/ipqess.c
-+++ b/drivers/net/ethernet/qualcomm/ipqess/ipqess.c
-@@ -453,13 +453,22 @@ static int ipqess_tx_complete(struct ipq
- tail >>= IPQESS_TPD_CONS_IDX_SHIFT;
- tail &= IPQESS_TPD_CONS_IDX_MASK;
-
-- do {
-+ while ((tx_ring->tail != tail) && (done < budget)) {
- ret = ipqess_tx_unmap_and_free(&tx_ring->ess->pdev->dev,
- &tx_ring->buf[tx_ring->tail]);
-- tx_ring->tail = IPQESS_NEXT_IDX(tx_ring->tail, tx_ring->count);
-+ /* ipqess_tx_unmap_and_free may return 2 kind values:
-+ * - 0: we are handling first and middle descriptor for the packet
-+ * - packet len: we are at the last descriptor for the packet
-+ * Increment total bytes handled and packet done only if we are
-+ * handling the last descriptor for the packet.
-+ */
-+ if (ret) {
-+ total += ret;
-+ done++;
-+ }
-
-- total += ret;
-- } while ((++done < budget) && (tx_ring->tail != tail));
-+ tx_ring->tail = IPQESS_NEXT_IDX(tx_ring->tail, tx_ring->count);
-+ };
-
- ipqess_w32(tx_ring->ess, IPQESS_REG_TX_SW_CONS_IDX_Q(tx_ring->idx),
- tx_ring->tail);
+++ /dev/null
-From: Christian Lamparter <chunkeey@googlemail.com>
-Subject: SoC: add qualcomm syscon
---- a/drivers/soc/qcom/Kconfig
-+++ b/drivers/soc/qcom/Kconfig
-@@ -248,4 +248,11 @@ config QCOM_ICC_BWMON
- the fixed bandwidth votes from cpufreq (CPU nodes) thus achieve high
- memory throughput even with lower CPU frequencies.
-
-+config QCOM_TCSR
-+ tristate "QCOM Top Control and Status Registers"
-+ depends on ARCH_QCOM
-+ help
-+ Say y here to enable TCSR support. The TCSR provides control
-+ functions for various peripherals.
-+
- endmenu
---- a/drivers/soc/qcom/Makefile
-+++ b/drivers/soc/qcom/Makefile
-@@ -29,3 +29,4 @@ obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o
- obj-$(CONFIG_QCOM_RPMPD) += rpmpd.o
- obj-$(CONFIG_QCOM_KRYO_L2_ACCESSORS) += kryo-l2-accessors.o
- obj-$(CONFIG_QCOM_ICC_BWMON) += icc-bwmon.o
-+obj-$(CONFIG_QCOM_TCSR) += qcom_tcsr.o
---- /dev/null
-+++ b/drivers/soc/qcom/qcom_tcsr.c
-@@ -0,0 +1,98 @@
-+/*
-+ * Copyright (c) 2014, The Linux foundation. All rights reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License rev 2 and
-+ * only rev 2 as published by the free Software foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/err.h>
-+#include <linux/io.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/of_platform.h>
-+#include <linux/platform_device.h>
-+
-+#define TCSR_USB_PORT_SEL 0xb0
-+#define TCSR_USB_HSPHY_CONFIG 0xC
-+
-+#define TCSR_ESS_INTERFACE_SEL_OFFSET 0x0
-+#define TCSR_ESS_INTERFACE_SEL_MASK 0xf
-+
-+#define TCSR_WIFI0_GLB_CFG_OFFSET 0x0
-+#define TCSR_WIFI1_GLB_CFG_OFFSET 0x4
-+#define TCSR_PNOC_SNOC_MEMTYPE_M0_M2 0x4
-+
-+static int tcsr_probe(struct platform_device *pdev)
-+{
-+ struct resource *res;
-+ const struct device_node *node = pdev->dev.of_node;
-+ void __iomem *base;
-+ u32 val;
-+
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ base = devm_ioremap_resource(&pdev->dev, res);
-+ if (IS_ERR(base))
-+ return PTR_ERR(base);
-+
-+ if (!of_property_read_u32(node, "qcom,usb-ctrl-select", &val)) {
-+ dev_err(&pdev->dev, "setting usb port select = %d\n", val);
-+ writel(val, base + TCSR_USB_PORT_SEL);
-+ }
-+
-+ if (!of_property_read_u32(node, "qcom,usb-hsphy-mode-select", &val)) {
-+ dev_info(&pdev->dev, "setting usb hs phy mode select = %x\n", val);
-+ writel(val, base + TCSR_USB_HSPHY_CONFIG);
-+ }
-+
-+ if (!of_property_read_u32(node, "qcom,ess-interface-select", &val)) {
-+ u32 tmp = 0;
-+ dev_info(&pdev->dev, "setting ess interface select = %x\n", val);
-+ tmp = readl(base + TCSR_ESS_INTERFACE_SEL_OFFSET);
-+ tmp = tmp & (~TCSR_ESS_INTERFACE_SEL_MASK);
-+ tmp = tmp | (val&TCSR_ESS_INTERFACE_SEL_MASK);
-+ writel(tmp, base + TCSR_ESS_INTERFACE_SEL_OFFSET);
-+ }
-+
-+ if (!of_property_read_u32(node, "qcom,wifi_glb_cfg", &val)) {
-+ dev_info(&pdev->dev, "setting wifi_glb_cfg = %x\n", val);
-+ writel(val, base + TCSR_WIFI0_GLB_CFG_OFFSET);
-+ writel(val, base + TCSR_WIFI1_GLB_CFG_OFFSET);
-+ }
-+
-+ if (!of_property_read_u32(node, "qcom,wifi_noc_memtype_m0_m2", &val)) {
-+ dev_info(&pdev->dev,
-+ "setting wifi_noc_memtype_m0_m2 = %x\n", val);
-+ writel(val, base + TCSR_PNOC_SNOC_MEMTYPE_M0_M2);
-+ }
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id tcsr_dt_match[] = {
-+ { .compatible = "qcom,tcsr", },
-+ { },
-+};
-+
-+MODULE_DEVICE_TABLE(of, tcsr_dt_match);
-+
-+static struct platform_driver tcsr_driver = {
-+ .driver = {
-+ .name = "tcsr",
-+ .owner = THIS_MODULE,
-+ .of_match_table = tcsr_dt_match,
-+ },
-+ .probe = tcsr_probe,
-+};
-+
-+module_platform_driver(tcsr_driver);
-+
-+MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
-+MODULE_DESCRIPTION("QCOM TCSR driver");
-+MODULE_LICENSE("GPL v2");
---- /dev/null
-+++ b/include/dt-bindings/soc/qcom,tcsr.h
-@@ -0,0 +1,48 @@
-+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 and
-+ * only version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ */
-+#ifndef __DT_BINDINGS_QCOM_TCSR_H
-+#define __DT_BINDINGS_QCOM_TCSR_H
-+
-+#define TCSR_USB_SELECT_USB3_P0 0x1
-+#define TCSR_USB_SELECT_USB3_P1 0x2
-+#define TCSR_USB_SELECT_USB3_DUAL 0x3
-+
-+/* IPQ40xx HS PHY Mode Select */
-+#define TCSR_USB_HSPHY_HOST_MODE 0x00E700E7
-+#define TCSR_USB_HSPHY_DEVICE_MODE 0x00C700E7
-+
-+/* IPQ40xx ess interface mode select */
-+#define TCSR_ESS_PSGMII 0
-+#define TCSR_ESS_PSGMII_RGMII5 1
-+#define TCSR_ESS_PSGMII_RMII0 2
-+#define TCSR_ESS_PSGMII_RMII1 4
-+#define TCSR_ESS_PSGMII_RMII0_RMII1 6
-+#define TCSR_ESS_PSGMII_RGMII4 9
-+
-+/*
-+ * IPQ40xx WiFi Global Config
-+ * Bit 30:AXID_EN
-+ * Enable AXI master bus Axid translating to confirm all txn submitted by order
-+ * Bit 24: Use locally generated socslv_wxi_bvalid
-+ * 1: use locally generate socslv_wxi_bvalid for performance.
-+ * 0: use SNOC socslv_wxi_bvalid.
-+ */
-+#define TCSR_WIFI_GLB_CFG 0x41000000
-+
-+/* IPQ40xx MEM_TYPE_SEL_M0_M2 Select Bit 26:24 - 2 NORMAL */
-+#define TCSR_WIFI_NOC_MEMTYPE_M0_M2 0x02222222
-+
-+/* TCSR A/B REG */
-+#define IPQ806X_TCSR_REG_A_ADM_CRCI_MUX_SEL 0
-+#define IPQ806X_TCSR_REG_B_ADM_CRCI_MUX_SEL 1
-+
-+#endif
+++ /dev/null
-From c668fd2c4d9ad4a510fd214a2da83bd9b67a2508 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Sun, 13 Aug 2023 18:13:08 +0200
-Subject: [PATCH] Revert "firmware: qcom_scm: Clear download bit during reboot"
-
-This reverts commit a3ea89b5978dbcd0fa55f675c5a1e04611093709.
-
-It is breaking reboot on IPQ4019 boards, so revert until a proper fix
-is found.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
----
- drivers/firmware/qcom_scm.c | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
---- a/drivers/firmware/qcom_scm.c
-+++ b/drivers/firmware/qcom_scm.c
-@@ -1466,7 +1466,8 @@ static int qcom_scm_probe(struct platfor
- static void qcom_scm_shutdown(struct platform_device *pdev)
- {
- /* Clean shutdown, disable download mode to allow normal restart */
-- qcom_scm_set_download_mode(false);
-+ if (download_mode)
-+ qcom_scm_set_download_mode(false);
- }
-
- static const struct of_device_id qcom_scm_dt_match[] = {
+++ /dev/null
-From: John Crispin <blogic@openwrt.org>
-Date: Fri, 3 Aug 2012 10:27:25 +0200
-Subject: [PATCH 04/36] MIPS: lantiq: add atm hack
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
---- a/include/uapi/linux/atm.h
-+++ b/include/uapi/linux/atm.h
-@@ -131,8 +131,14 @@
- #define ATM_ABR 4
- #define ATM_ANYCLASS 5 /* compatible with everything */
-
-+#define ATM_VBR_NRT ATM_VBR
-+#define ATM_VBR_RT 6
-+#define ATM_UBR_PLUS 7
-+#define ATM_GFR 8
-+
- #define ATM_MAX_PCR -1 /* maximum available PCR */
-
-+
- struct atm_trafprm {
- unsigned char traffic_class; /* traffic class (ATM_UBR, ...) */
- int max_pcr; /* maximum PCR in cells per second */
-@@ -155,6 +161,9 @@ struct atm_trafprm {
- unsigned int adtf :10; /* ACR Decrease Time Factor (10-bit) */
- unsigned int cdf :3; /* Cutoff Decrease Factor (3-bit) */
- unsigned int spare :9; /* spare bits */
-+ int scr; /* sustained rate in cells per second */
-+ int mbs; /* maximum burst size (MBS) in cells */
-+ int cdv; /* Cell delay variation */
- };
-
- struct atm_qos {
---- a/net/atm/proc.c
-+++ b/net/atm/proc.c
-@@ -141,7 +141,7 @@ static void *vcc_seq_next(struct seq_fil
- static void pvc_info(struct seq_file *seq, struct atm_vcc *vcc)
- {
- static const char *const class_name[] = {
-- "off", "UBR", "CBR", "VBR", "ABR"};
-+ "off","UBR","CBR","NTR-VBR","ABR","ANY","RT-VBR","UBR+","GFR"};
- static const char *const aal_name[] = {
- "---", "1", "2", "3/4", /* 0- 3 */
- "???", "5", "???", "???", /* 4- 7 */
+++ /dev/null
-From: Subhra Banerjee <subhrax.banerjee@intel.com>
-Date: Fri, 31 Aug 2018 12:01:19 +0530
-Subject: [PATCH] UGW_SW-29163: ATM oam support
-
---- a/drivers/net/ppp/ppp_generic.c
-+++ b/drivers/net/ppp/ppp_generic.c
-@@ -2953,6 +2953,22 @@ char *ppp_dev_name(struct ppp_channel *c
- return name;
- }
-
-+/*
-+ * Return the PPP device interface pointer
-+ */
-+struct net_device *ppp_device(struct ppp_channel *chan)
-+{
-+ struct channel *pch = chan->ppp;
-+ struct net_device *dev = NULL;
-+
-+ if (pch) {
-+ read_lock_bh(&pch->upl);
-+ if (pch->ppp && pch->ppp->dev)
-+ dev = pch->ppp->dev;
-+ read_unlock_bh(&pch->upl);
-+ }
-+ return dev;
-+}
-
- /*
- * Disconnect a channel from the generic layer.
-@@ -3599,6 +3615,7 @@ EXPORT_SYMBOL(ppp_unregister_channel);
- EXPORT_SYMBOL(ppp_channel_index);
- EXPORT_SYMBOL(ppp_unit_number);
- EXPORT_SYMBOL(ppp_dev_name);
-+EXPORT_SYMBOL(ppp_device);
- EXPORT_SYMBOL(ppp_input);
- EXPORT_SYMBOL(ppp_input_error);
- EXPORT_SYMBOL(ppp_output_wakeup);
---- a/include/linux/ppp_channel.h
-+++ b/include/linux/ppp_channel.h
-@@ -76,6 +76,9 @@ extern int ppp_unit_number(struct ppp_ch
- /* Get the device name associated with a channel, or NULL if none */
- extern char *ppp_dev_name(struct ppp_channel *);
-
-+/* Get the device pointer associated with a channel, or NULL if none */
-+extern struct net_device *ppp_device(struct ppp_channel *);
-+
- /*
- * SMP locking notes:
- * The channel code must ensure that when it calls ppp_unregister_channel,
---- a/net/atm/Kconfig
-+++ b/net/atm/Kconfig
-@@ -56,6 +56,12 @@ config ATM_MPOA
- subnetwork boundaries. These shortcut connections bypass routers
- enhancing overall network performance.
-
-+config ATM_MPOA_INTEL_DSL_PHY_SUPPORT
-+ bool "Intel DSL Phy MPOA support"
-+ depends on ATM && INET && ATM_MPOA!=n
-+ help
-+ Add support for Intel DSL Phy ATM MPOA
-+
- config ATM_BR2684
- tristate "RFC1483/2684 Bridged protocols"
- depends on ATM && INET
---- a/net/atm/br2684.c
-+++ b/net/atm/br2684.c
-@@ -598,6 +598,11 @@ static int br2684_regvcc(struct atm_vcc
- atmvcc->push = br2684_push;
- atmvcc->pop = br2684_pop;
- atmvcc->release_cb = br2684_release_cb;
-+#if IS_ENABLED(CONFIG_ATM_MPOA_INTEL_DSL_PHY_SUPPORT)
-+ if (atm_hook_mpoa_setup) /* IPoA or EoA w/o FCS */
-+ atm_hook_mpoa_setup(atmvcc, brdev->payload == p_routed ? 3 : 0,
-+ brvcc->encaps == BR2684_ENCAPS_LLC ? 1 : 0, net_dev);
-+#endif
- atmvcc->owner = THIS_MODULE;
-
- /* initialize netdev carrier state */
---- a/net/atm/common.c
-+++ b/net/atm/common.c
-@@ -137,6 +137,11 @@ static struct proto vcc_proto = {
- .release_cb = vcc_release_cb,
- };
-
-+#if IS_ENABLED(CONFIG_ATM_MPOA_INTEL_DSL_PHY_SUPPORT)
-+void (*atm_hook_mpoa_setup)(struct atm_vcc *, int, int, struct net_device *) = NULL;
-+EXPORT_SYMBOL(atm_hook_mpoa_setup);
-+#endif
-+
- int vcc_create(struct net *net, struct socket *sock, int protocol, int family, int kern)
- {
- struct sock *sk;
---- a/net/atm/common.h
-+++ b/net/atm/common.h
-@@ -53,4 +53,6 @@ int svc_change_qos(struct atm_vcc *vcc,s
-
- void atm_dev_release_vccs(struct atm_dev *dev);
-
-+extern void (*atm_hook_mpoa_setup)(struct atm_vcc *, int, int, struct net_device *);
-+
- #endif
---- a/net/atm/mpc.c
-+++ b/net/atm/mpc.c
-@@ -31,6 +31,7 @@
- /* Modular too */
- #include <linux/module.h>
-
-+#include "common.h"
- #include "lec.h"
- #include "mpc.h"
- #include "resources.h"
-@@ -645,6 +646,10 @@ static int atm_mpoa_vcc_attach(struct at
- vcc->proto_data = mpc->dev;
- vcc->push = mpc_push;
-
-+#if IS_ENABLED(CONFIG_ATM_MPOA_INTEL_DSL_PHY_SUPPORT)
-+ if (atm_hook_mpoa_setup) /* IPoA, LLC */
-+ atm_hook_mpoa_setup(vcc, 3, 1, mpc->dev);
-+#endif
- return 0;
- }
-
---- a/net/atm/pppoatm.c
-+++ b/net/atm/pppoatm.c
-@@ -422,6 +422,12 @@ static int pppoatm_assign_vcc(struct atm
- atmvcc->user_back = pvcc;
- atmvcc->push = pppoatm_push;
- atmvcc->pop = pppoatm_pop;
-+#if IS_ENABLED(CONFIG_ATM_MPOA_INTEL_DSL_PHY_SUPPORT)
-+ if (atm_hook_mpoa_setup) /* PPPoA */
-+ atm_hook_mpoa_setup(atmvcc, 2,
-+ pvcc->encaps == e_llc ? 1 : 0,
-+ ppp_device(&pvcc->chan));
-+#endif
- atmvcc->release_cb = pppoatm_release_cb;
- __module_get(THIS_MODULE);
- atmvcc->owner = THIS_MODULE;
+#endif
--- a/include/linux/skbuff.h
+++ b/include/linux/skbuff.h
-@@ -4643,6 +4643,9 @@ enum skb_ext_id {
+@@ -4642,6 +4642,9 @@ enum skb_ext_id {
#if IS_ENABLED(CONFIG_MCTP_FLOWS)
SKB_EXT_MCTP,
#endif
#include <net/dst.h>
#include <net/sock.h>
#include <net/checksum.h>
-@@ -4812,6 +4816,9 @@ static const u8 skb_ext_type_len[] = {
+@@ -4823,6 +4827,9 @@ static const u8 skb_ext_type_len[] = {
#if IS_ENABLED(CONFIG_MCTP_FLOWS)
[SKB_EXT_MCTP] = SKB_EXT_CHUNKSIZEOF(struct mctp_flow),
#endif
CPU_SUBTYPE:=neon-vfpv4
SUBTARGETS:=generic chromium
-KERNEL_PATCHVER:=6.1
-KERNEL_TESTING_PATCHVER:=6.6
+KERNEL_PATCHVER:=6.6
KERNELNAME:=zImage Image dtbs
+++ /dev/null
-CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_APQ_GCC_8084 is not set
-# CONFIG_APQ_MMCC_8084 is not set
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-# CONFIG_ARCH_IPQ40XX is not set
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-# CONFIG_ARCH_MDM9615 is not set
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-# CONFIG_ARCH_MSM8909 is not set
-# CONFIG_ARCH_MSM8916 is not set
-CONFIG_ARCH_MSM8960=y
-CONFIG_ARCH_MSM8974=y
-CONFIG_ARCH_MSM8X60=y
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_QCOM=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_ATAG_DTB_COMPAT=y
-# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set
-CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE=y
-CONFIG_ARM_ATAG_DTB_COMPAT_IGNORE_MEM=y
-CONFIG_ARM_CPUIDLE=y
-CONFIG_ARM_CPU_SUSPEND=y
-# CONFIG_ARM_CPU_TOPOLOGY is not set
-CONFIG_ARM_GIC=y
-CONFIG_ARM_HAS_GROUP_RELOCS=y
-CONFIG_ARM_IPQ806X_FAB_DEVFREQ=y
-CONFIG_ARM_KRAIT_CACHE_DEVFREQ=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-CONFIG_ARM_PATCH_IDIV=y
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-# CONFIG_ARM_QCOM_CPUFREQ_HW is not set
-CONFIG_ARM_QCOM_CPUFREQ_NVMEM=y
-CONFIG_ARM_QCOM_SPM_CPUIDLE=y
-# CONFIG_ARM_SMMU is not set
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BOUNCE=y
-# CONFIG_CACHE_L2X0 is not set
-CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_CC_NO_ARRAY_BOUNDS=y
-CONFIG_CLKSRC_QCOM=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE_OVERRIDE=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_QCOM=y
-CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONTEXT_TRACKING=y
-CONFIG_CONTEXT_TRACKING_IDLE=y
-CONFIG_CPUFREQ_DT=y
-CONFIG_CPUFREQ_DT_PLATDEV=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
-CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
-# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_SPECTRE=y
-CONFIG_CPU_THERMAL=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRC16=y
-# CONFIG_CRC32_SARWATE is not set
-CONFIG_CRC32_SLICEBY8=y
-CONFIG_CRC8=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_DEV_QCOM_RNG=y
-CONFIG_CRYPTO_DRBG=y
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_MENU=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_JITTERENTROPY=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_SHA1=y
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_LIB_UTILS=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_GPIO=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-CONFIG_DEVFREQ_GOV_PASSIVE=y
-# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set
-# CONFIG_DEVFREQ_GOV_POWERSAVE is not set
-# CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND is not set
-# CONFIG_DEVFREQ_GOV_USERSPACE is not set
-# CONFIG_DEVFREQ_THERMAL is not set
-CONFIG_DMADEVICES=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_OPS=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DTC=y
-CONFIG_DT_IDLE_STATES=y
-# CONFIG_DWMAC_GENERIC is not set
-CONFIG_DWMAC_IPQ806X=y
-# CONFIG_DWMAC_QCOM_ETHQOS is not set
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MIGRATION=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GENERIC_VDSO_32=y
-CONFIG_GLOB=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GRO_CELLS=y
-CONFIG_HARDEN_BRANCH_PREDICTOR=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAVE_SMP=y
-CONFIG_HIGHMEM=y
-# CONFIG_HIGHPTE is not set
-CONFIG_HOTPLUG_CPU=y
-CONFIG_HWMON=y
-CONFIG_HWSPINLOCK=y
-CONFIG_HWSPINLOCK_QCOM=y
-CONFIG_HW_RANDOM=y
-CONFIG_HZ_FIXED=0
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_HELPER_AUTO=y
-# CONFIG_I2C_QCOM_CCI is not set
-CONFIG_I2C_QUP=y
-CONFIG_INITRAMFS_SOURCE=""
-# CONFIG_IOMMU_DEBUGFS is not set
-# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
-# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
-CONFIG_IOMMU_SUPPORT=y
-# CONFIG_IPQ_APSS_PLL is not set
-# CONFIG_IPQ_GCC_4019 is not set
-# CONFIG_IPQ_GCC_6018 is not set
-CONFIG_IPQ_GCC_806X=y
-# CONFIG_IPQ_GCC_8074 is not set
-# CONFIG_IPQ_LCC_806X is not set
-CONFIG_IRQCHIP=y
-CONFIG_IRQSTACKS=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_KMAP_LOCAL=y
-CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
-CONFIG_KPSS_XCC=y
-CONFIG_KRAITCC=y
-CONFIG_KRAIT_CLOCKS=y
-CONFIG_KRAIT_L2_ACCESSORS=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MDIO_BITBANG=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MDIO_GPIO=y
-CONFIG_MDIO_IPQ8064=y
-# CONFIG_MDM_GCC_9615 is not set
-# CONFIG_MDM_LCC_9615 is not set
-CONFIG_MEMFD_CREATE=y
-# CONFIG_MFD_HI6421_SPMI is not set
-CONFIG_MFD_QCOM_RPM=y
-# CONFIG_MFD_SPMI_PMIC is not set
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_ARMMMCI=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_BLOCK_MINORS=16
-CONFIG_MMC_CQHCI=y
-CONFIG_MMC_QCOM_DML=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_IO_ACCESSORS=y
-CONFIG_MMC_SDHCI_MSM=y
-# CONFIG_MMC_SDHCI_PCI is not set
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MSM_GCC_8660=y
-# CONFIG_MSM_GCC_8909 is not set
-# CONFIG_MSM_GCC_8916 is not set
-# CONFIG_MSM_GCC_8939 is not set
-# CONFIG_MSM_GCC_8960 is not set
-# CONFIG_MSM_GCC_8974 is not set
-# CONFIG_MSM_GCC_8976 is not set
-# CONFIG_MSM_GCC_8994 is not set
-# CONFIG_MSM_GCC_8996 is not set
-# CONFIG_MSM_GCC_8998 is not set
-# CONFIG_MSM_GPUCC_8998 is not set
-# CONFIG_MSM_IOMMU is not set
-# CONFIG_MSM_LCC_8960 is not set
-# CONFIG_MSM_MMCC_8960 is not set
-# CONFIG_MSM_MMCC_8974 is not set
-# CONFIG_MSM_MMCC_8996 is not set
-# CONFIG_MSM_MMCC_8998 is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
-CONFIG_MTD_NAND_QCOM=y
-CONFIG_MTD_QCOMSMEM_PARTS=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_FIT_FW=y
-CONFIG_MTD_SPLIT_UIMAGE_FW=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEON=y
-CONFIG_NET_DEVLINK=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_QCA8K=y
-CONFIG_NET_DSA_QCA8K_LEDS_SUPPORT=y
-CONFIG_NET_DSA_TAG_QCA=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NLS=y
-CONFIG_NO_HZ=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=2
-CONFIG_NVMEM=y
-CONFIG_NVMEM_LAYOUTS=y
-CONFIG_NVMEM_QCOM_QFPROM=y
-# CONFIG_NVMEM_QCOM_SEC_QFPROM is not set
-# CONFIG_NVMEM_SPMI_SDAM is not set
-CONFIG_NVMEM_SYSFS=y
-CONFIG_NVMEM_U_BOOT_ENV=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_PADATA=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_DW=y
-CONFIG_PCIE_DW_HOST=y
-CONFIG_PCIE_QCOM=y
-CONFIG_PCI_DEBUG=y
-CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PCS_XPCS=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_LEDS=y
-CONFIG_PHYLINK=y
-# CONFIG_PHY_QCOM_APQ8064_SATA is not set
-# CONFIG_PHY_QCOM_EDP is not set
-# CONFIG_PHY_QCOM_IPQ4019_USB is not set
-CONFIG_PHY_QCOM_IPQ806X_SATA=y
-# CONFIG_PHY_QCOM_IPQ806X_USB is not set
-# CONFIG_PHY_QCOM_PCIE2 is not set
-# CONFIG_PHY_QCOM_QMP is not set
-# CONFIG_PHY_QCOM_QUSB2 is not set
-# CONFIG_PHY_QCOM_USB_HS_28NM is not set
-# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set
-# CONFIG_PHY_QCOM_USB_SS is not set
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_APQ8064 is not set
-# CONFIG_PINCTRL_APQ8084 is not set
-# CONFIG_PINCTRL_IPQ4019 is not set
-CONFIG_PINCTRL_IPQ8064=y
-# CONFIG_PINCTRL_MDM9615 is not set
-CONFIG_PINCTRL_MSM=y
-# CONFIG_PINCTRL_MSM8226 is not set
-# CONFIG_PINCTRL_MSM8660 is not set
-# CONFIG_PINCTRL_MSM8909 is not set
-# CONFIG_PINCTRL_MSM8916 is not set
-# CONFIG_PINCTRL_MSM8960 is not set
-# CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set
-# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set
-# CONFIG_PINCTRL_SDX65 is not set
-CONFIG_PM_DEVFREQ=y
-# CONFIG_PM_DEVFREQ_EVENT is not set
-CONFIG_PM_OPP=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_MSM=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PPS=y
-CONFIG_PREEMPT_NONE_BUILD=y
-CONFIG_PRINTK_TIME=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_QCA83XX_PHY=y
-# CONFIG_QCM_DISPCC_2290 is not set
-# CONFIG_QCM_GCC_2290 is not set
-# CONFIG_QCOM_A53PLL is not set
-CONFIG_QCOM_ADM=y
-CONFIG_QCOM_BAM_DMA=y
-CONFIG_QCOM_CLK_RPM=y
-# CONFIG_QCOM_COMMAND_DB is not set
-# CONFIG_QCOM_CPR is not set
-# CONFIG_QCOM_EBI2 is not set
-# CONFIG_QCOM_GENI_SE is not set
-CONFIG_QCOM_GSBI=y
-CONFIG_QCOM_HFPLL=y
-# CONFIG_QCOM_ICC_BWMON is not set
-# CONFIG_QCOM_IOMMU is not set
-# CONFIG_QCOM_LLCC is not set
-CONFIG_QCOM_NET_PHYLIB=y
-# CONFIG_QCOM_OCMEM is not set
-# CONFIG_QCOM_PDC is not set
-# CONFIG_QCOM_RMTFS_MEM is not set
-CONFIG_QCOM_RPMCC=y
-# CONFIG_QCOM_RPMH is not set
-CONFIG_QCOM_SCM=y
-# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set
-CONFIG_QCOM_SMEM=y
-# CONFIG_QCOM_SMSM is not set
-CONFIG_QCOM_SOCINFO=y
-CONFIG_QCOM_SPM=y
-# CONFIG_QCOM_STATS is not set
-CONFIG_QCOM_TCSR=y
-CONFIG_QCOM_TSENS=y
-CONFIG_QCOM_WDT=y
-# CONFIG_QCS_GCC_404 is not set
-# CONFIG_QCS_Q6SSTOP_404 is not set
-# CONFIG_QCS_TURING_404 is not set
-CONFIG_RANDSTRUCT_NONE=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-CONFIG_RCU_CPU_STALL_TIMEOUT=21
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-# CONFIG_REGULATOR_QCOM_LABIBB is not set
-CONFIG_REGULATOR_QCOM_RPM=y
-# CONFIG_REGULATOR_QCOM_SPMI is not set
-# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
-# CONFIG_REGULATOR_VQMMC_IPQ4019 is not set
-CONFIG_RESET_CONTROLLER=y
-# CONFIG_RESET_QCOM_AOSS is not set
-# CONFIG_RESET_QCOM_PDC is not set
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RTC_MC146818_LIB=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-# CONFIG_SC_CAMCC_7280 is not set
-# CONFIG_SC_DISPCC_7180 is not set
-# CONFIG_SC_GCC_7180 is not set
-# CONFIG_SC_GCC_8280XP is not set
-# CONFIG_SC_GPUCC_7180 is not set
-# CONFIG_SC_LPASSCC_7280 is not set
-# CONFIG_SC_LPASS_CORECC_7180 is not set
-# CONFIG_SC_LPASS_CORECC_7280 is not set
-# CONFIG_SC_MSS_7180 is not set
-# CONFIG_SC_VIDEOCC_7180 is not set
-# CONFIG_SDM_CAMCC_845 is not set
-# CONFIG_SDM_DISPCC_845 is not set
-# CONFIG_SDM_GCC_660 is not set
-# CONFIG_SDM_GCC_845 is not set
-# CONFIG_SDM_GPUCC_845 is not set
-# CONFIG_SDM_LPASSCC_845 is not set
-# CONFIG_SDM_VIDEOCC_845 is not set
-# CONFIG_SDX_GCC_65 is not set
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_MSM=y
-CONFIG_SERIAL_MSM_CONSOLE=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-# CONFIG_SM_CAMCC_8450 is not set
-# CONFIG_SM_GCC_8150 is not set
-# CONFIG_SM_GCC_8250 is not set
-# CONFIG_SM_GCC_8450 is not set
-# CONFIG_SM_GPUCC_6350 is not set
-# CONFIG_SM_GPUCC_8150 is not set
-# CONFIG_SM_GPUCC_8250 is not set
-# CONFIG_SM_GPUCC_8350 is not set
-# CONFIG_SM_VIDEOCC_8150 is not set
-# CONFIG_SM_VIDEOCC_8250 is not set
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SOC_BUS=y
-CONFIG_SOFTIRQ_ON_OWN_STACK=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_QUP=y
-CONFIG_SPMI=y
-# CONFIG_SPMI_HISI3670 is not set
-CONFIG_SPMI_MSM_PMIC_ARB=y
-# CONFIG_SPMI_PMIC_CLKDIV is not set
-CONFIG_SRCU=y
-CONFIG_STMMAC_ETH=y
-CONFIG_STMMAC_PLATFORM=y
-CONFIG_SWPHY=y
-CONFIG_SWP_EMULATE=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_HWMON=y
-CONFIG_THERMAL_OF=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UBIFS_FS=y
-CONFIG_UBIFS_FS_ADVANCED_COMPR=y
-# CONFIG_UCLAMP_TASK is not set
-CONFIG_UEVENT_HELPER_PATH=""
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZSTD_COMMON=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq8062-smb208.dtsi"
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "NEC Platforms Aterm WG2600HP3";
- compatible = "nec,wg2600hp3", "qcom,ipq8062", "qcom,ipq8064";
-
- memory {
- device_type = "memory";
- reg = <0x42000000 0x1e000000>;
- };
-
- aliases {
- label-mac-device = &gmac2;
-
- led-boot = &led_power_green;
- led-failsafe = &led_power_red;
- led-running = &led_power_green;
- led-upgrade = &led_power_red;
- };
-
- keys {
- compatible = "gpio-keys";
-
- pinctrl-0 = <&buttons_pins>;
- pinctrl-names = "default";
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 24 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- wps {
- label = "wps";
- gpios = <&qcom_pinmux 22 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- mode0 {
- label = "mode0";
- gpios = <&qcom_pinmux 40 GPIO_ACTIVE_LOW>;
- linux,code = <BTN_0>;
- linux,input-type = <EV_SW>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- mode1 {
- label = "mode1";
- gpios = <&qcom_pinmux 41 GPIO_ACTIVE_LOW>;
- linux,code = <BTN_1>;
- linux,input-type = <EV_SW>;
- debounce-interval = <60>;
- wakeup-source;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- pinctrl-0 = <&leds_pins>;
- pinctrl-names = "default";
-
- led_power_green: power_green {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&qcom_pinmux 14 GPIO_ACTIVE_HIGH>;
- };
-
- led_power_red: power_red {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_RED>;
- gpios = <&qcom_pinmux 35 GPIO_ACTIVE_HIGH>;
- };
-
- active_green {
- label = "green:active";
- gpios = <&qcom_pinmux 42 GPIO_ACTIVE_HIGH>;
- };
-
- active_red {
- label = "red:active";
- gpios = <&qcom_pinmux 38 GPIO_ACTIVE_HIGH>;
- };
-
- wlan2g_green {
- label = "green:wlan2g";
- gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy1tpt";
- };
-
- wlan2g_red {
- label = "red:wlan2g";
- gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>;
- };
-
- wlan5g_green {
- label = "green:wlan5g";
- gpios = <&qcom_pinmux 57 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "phy0tpt";
- };
-
- wlan5g_red {
- label = "red:wlan5g";
- gpios = <&qcom_pinmux 58 GPIO_ACTIVE_HIGH>;
- };
-
- tv_green {
- label = "green:tv";
- gpios = <&qcom_pinmux 46 GPIO_ACTIVE_HIGH>;
- };
-
- tv_red {
- label = "red:tv";
- gpios = <&qcom_pinmux 36 GPIO_ACTIVE_HIGH>;
- };
-
- converter_green {
- label = "green:converter";
- gpios = <&qcom_pinmux 43 GPIO_ACTIVE_HIGH>;
- };
-
- converter_red {
- label = "red:converter";
- gpios = <&qcom_pinmux 15 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-/* nand_pins are used for leds_pins, empty the node
- * from ipq8064.dtsi
- */
-&nand_pins {
- /delete-property/ disable;
- /delete-property/ pullups;
- /delete-property/ hold;
-};
-
-&qcom_pinmux {
- pinctrl-0 = <&akro_pins>;
- pinctrl-names = "default";
-
- spi_pins: spi_pins {
- mux {
- pins = "gpio18", "gpio19", "gpio21";
- function = "gsbi5";
- bias-pull-down;
- };
-
- data {
- pins = "gpio18", "gpio19";
- drive-strength = <10>;
- };
-
- cs {
- pins = "gpio20";
- drive-strength = <10>;
- };
-
- clk {
- pins = "gpio21";
- drive-strength = <12>;
- };
- };
-
- buttons_pins: buttons_pins {
- mux {
- pins = "gpio22", "gpio24", "gpio40",
- "gpio41";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- leds_pins: leds_pins {
- mux {
- pins = "gpio14", "gpio15", "gpio35",
- "gpio36", "gpio38", "gpio42",
- "gpio43", "gpio46", "gpio55",
- "gpio56", "gpio57", "gpio58";
- function = "gpio";
- bias-pull-down;
- };
-
- akro2 {
- pins = "gpio15", "gpio35", "gpio38",
- "gpio42", "gpio43", "gpio46",
- "gpio55", "gpio56", "gpio57",
- "gpio58";
- drive-strength = <2>;
- };
-
- akro4 {
- pins = "gpio14", "gpio36";
- drive-strength = <4>;
- };
- };
-
- /*
- * Stock firmware has the following settings, so let's do the same.
- * I don't sure why these are required.
- */
- akro_pins: akro_pinmux {
- akro {
- pins = "gpio17", "gpio26", "gpio47";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-down;
- };
-
- reset {
- pins = "gpio45";
- function = "gpio";
- drive-strength = <2>;
- bias-disable;
- output-low;
- };
-
- gmac0_rgmii {
- pins = "gpio25";
- function = "gpio";
- drive-strength = <8>;
- bias-disable;
- };
- };
-};
-
-&gsbi5 {
- status = "okay";
- qcom,mode = <GSBI_PROT_SPI>;
-
- spi@1a280000 {
- status = "okay";
-
- pinctrl-0 = <&spi_pins>;
- pinctrl-names = "default";
-
- cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <50000000>;
- m25p,fast-read;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SBL1";
- reg = <0x0000000 0x0020000>;
- read-only;
- };
-
- partition@20000 {
- label = "MIBIB";
- reg = <0x0020000 0x0020000>;
- read-only;
- };
-
- partition@40000 {
- label = "SBL2";
- reg = <0x0040000 0x0040000>;
- read-only;
- };
-
- partition@80000 {
- label = "SBL3";
- reg = <0x0080000 0x0080000>;
- read-only;
- };
-
- partition@100000 {
- label = "DDRCONFIG";
- reg = <0x0100000 0x0010000>;
- read-only;
- };
-
- partition@110000 {
- label = "SSD";
- reg = <0x0110000 0x0010000>;
- read-only;
- };
-
- partition@120000 {
- label = "TZ";
- reg = <0x0120000 0x0080000>;
- read-only;
- };
-
- partition@1a0000 {
- label = "RPM";
- reg = <0x01a0000 0x0080000>;
- read-only;
- };
-
- partition@220000 {
- label = "APPSBL";
- reg = <0x0220000 0x0080000>;
- read-only;
- };
-
- partition@2a0000 {
- label = "APPSBLENV";
- reg = <0x02a0000 0x0010000>;
- read-only;
- };
-
- factory: partition@2b0000 {
- label = "PRODUCTDATA";
- reg = <0x02b0000 0x0030000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_factory_0: macaddr@0 {
- reg = <0x0 0x6>;
- };
-
- macaddr_factory_6: macaddr@6 {
- reg = <0x6 0x6>;
- };
-
- macaddr_PRODUCTDATA_c: macaddr@c {
- reg = <0xc 0x6>;
- };
-
- macaddr_PRODUCTDATA_12: macaddr@12 {
- reg = <0x12 0x6>;
- };
- };
- };
-
- partition@2e0000 {
- label = "ART";
- reg = <0x02e0000 0x0040000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_ART_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_ART_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- partition@320000 {
- label = "TP";
- reg = <0x0320000 0x0040000>;
- read-only;
- };
-
- partition@360000 {
- label = "TINY";
- reg = <0x0360000 0x0500000>;
- read-only;
- };
-
- partition@860000 {
- compatible = "denx,uimage";
- label = "firmware";
- reg = <0x0860000 0x17a0000>;
- };
- };
- };
- };
-};
-
-&adm_dma {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- compatible = "qcom,ath10k";
- reg = <0x00010000 0 0 0 0>;
-
- qcom,ath10k-calibration-variant = "NEC-Platforms-WG2600HP3";
-
- nvmem-cells = <&macaddr_PRODUCTDATA_12>, <&precal_ART_1000>;
- nvmem-cell-names = "mac-address", "pre-calibration";
- };
- };
-};
-
-&pcie1 {
- status = "okay";
- force_gen1 = <1>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- compatible = "qcom,ath10k";
- reg = <0x00010000 0 0 0 0>;
-
- ieee80211-freq-limit = <2400000 2483000>;
- qcom,ath10k-calibration-variant = "NEC-Platforms-WG2600HP3";
-
- nvmem-cells = <&macaddr_PRODUCTDATA_c>, <&precal_ART_5000>;
- nvmem-cell-names = "mac-address", "pre-calibration";
- };
- };
-};
-
-&mdio0 {
- status = "okay";
-
- pinctrl-0 = <&mdio0_pins>;
- pinctrl-names = "default";
-
- switch@10 {
- compatible = "qca,qca8337";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x10>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "cpu";
- ethernet = <&gmac1>;
- phy-mode = "rgmii";
- tx-internal-delay-ps = <1000>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- port@1 {
- reg = <1>;
- label = "wan";
- phy-mode = "internal";
- phy-handle = <&phy_port1>;
-
- leds {
- #address-cells = <1>;
- #size-cells = <0>;
-
- led@0 {
- reg = <0>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_WAN;
- function-enumerator = <1>;
- default-state = "keep";
- };
-
- led@1 {
- reg = <1>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_WAN;
- function-enumerator = <2>;
- default-state = "keep";
- };
-
- led@2 {
- reg = <2>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_WAN;
- function-enumerator = <3>;
- default-state = "keep";
- };
- };
- };
-
- port@2 {
- reg = <2>;
- label = "lan1";
- phy-mode = "internal";
- phy-handle = <&phy_port2>;
-
- leds {
- #address-cells = <1>;
- #size-cells = <0>;
-
- led@0 {
- reg = <0>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_LAN;
- function-enumerator = <1>;
- default-state = "keep";
- };
-
- led@1 {
- reg = <1>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_LAN;
- function-enumerator = <2>;
- default-state = "keep";
- };
-
- led@2 {
- reg = <2>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_LAN;
- function-enumerator = <3>;
- default-state = "keep";
- };
- };
- };
-
- port@3 {
- reg = <3>;
- label = "lan2";
- phy-mode = "internal";
- phy-handle = <&phy_port3>;
-
- leds {
- #address-cells = <1>;
- #size-cells = <0>;
-
- led@0 {
- reg = <0>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_LAN;
- function-enumerator = <1>;
- default-state = "keep";
- };
-
- led@1 {
- reg = <1>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_LAN;
- function-enumerator = <2>;
- default-state = "keep";
- };
-
- led@2 {
- reg = <2>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_LAN;
- function-enumerator = <3>;
- default-state = "keep";
- };
- };
- };
-
- port@4 {
- reg = <4>;
- label = "lan3";
- phy-mode = "internal";
- phy-handle = <&phy_port4>;
-
- leds {
- #address-cells = <1>;
- #size-cells = <0>;
-
- led@0 {
- reg = <0>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_LAN;
- function-enumerator = <1>;
- default-state = "keep";
- };
-
- led@1 {
- reg = <1>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_LAN;
- function-enumerator = <2>;
- default-state = "keep";
- };
-
- led@2 {
- reg = <2>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_LAN;
- function-enumerator = <3>;
- default-state = "keep";
- };
- };
- };
-
- port@5 {
- reg = <5>;
- label = "lan4";
- phy-mode = "internal";
- phy-handle = <&phy_port5>;
-
- leds {
- #address-cells = <1>;
- #size-cells = <0>;
-
- led@0 {
- reg = <0>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_LAN;
- function-enumerator = <1>;
- default-state = "keep";
- };
-
- led@1 {
- reg = <1>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_LAN;
- function-enumerator = <2>;
- default-state = "keep";
- };
-
- led@2 {
- reg = <2>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_LAN;
- function-enumerator = <3>;
- default-state = "keep";
- };
- };
- };
-
- port@6 {
- reg = <6>;
- label = "cpu";
- ethernet = <&gmac2>;
- phy-mode = "sgmii";
- qca,sgmii-enable-pll;
- qca,sgmii-rxclk-falling-edge;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy_port1: phy@0 {
- reg = <0>;
- };
-
- phy_port2: phy@1 {
- reg = <1>;
- };
-
- phy_port3: phy@2 {
- reg = <2>;
- };
-
- phy_port4: phy@3 {
- reg = <3>;
- };
-
- phy_port5: phy@4 {
- reg = <4>;
- };
- };
- };
-};
-
-&gmac1 {
- status = "okay";
-
- pinctrl-0 = <&rgmii2_pins>;
- pinctrl-names = "default";
-
- phy-mode = "rgmii";
- qcom,id = <1>;
- mdiobus = <&mdio0>;
- nvmem-cells = <&macaddr_factory_0>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gmac2 {
- status = "okay";
- phy-mode = "sgmii";
- qcom,id = <2>;
- mdiobus = <&mdio0>;
- nvmem-cells = <&macaddr_factory_6>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&hs_phy_0 {
- status = "okay";
-};
-
-&ss_phy_0 {
- status = "okay";
-};
-
-&usb3_0 {
- status = "okay";
-};
-
-&hs_phy_1 {
- status = "okay";
-};
-
-&ss_phy_1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq8064-v2.0-smb208.dtsi"
-
-#include <dt-bindings/input/input.h>
-
-/ {
- memory@0 {
- reg = <0x42000000 0x1e000000>;
- device_type = "memory";
- };
-
- reserved-memory {
- ramoops@42100000 {
- compatible = "ramoops";
- reg = <0x42100000 0x40000>;
- record-size = <0x4000>;
- console-size = <0x4000>;
- ftrace-size = <0x4000>;
- pmsg-size = <0x4000>;
- };
- };
-
- aliases {
- mdio-gpio0 = &mdio0;
- label-mac-device = &gmac2;
- };
-};
-
-&qcom_pinmux {
- spi_pins: spi_pins {
- mux {
- pins = "gpio18", "gpio19", "gpio21";
- function = "gsbi5";
- bias-pull-down;
- };
-
- data {
- pins = "gpio18", "gpio19";
- drive-strength = <10>;
- };
-
- cs {
- pins = "gpio20";
- function = "gpio";
- drive-strength = <10>;
- bias-pull-up;
- };
-
- clk {
- pins = "gpio21";
- drive-strength = <12>;
- };
- };
-
- usb0_pwr_en_pin: usb0_pwr_en_pin {
- mux {
- pins = "gpio25";
- function = "gpio";
- drive-strength = <10>;
- bias-pull-up;
- output-high;
- };
- };
-
- usb1_pwr_en_pin: usb1_pwr_en_pin {
- mux {
- pins = "gpio23";
- function = "gpio";
- drive-strength = <10>;
- bias-pull-up;
- output-high;
- };
- };
-};
-
-&gsbi5 {
- qcom,mode = <GSBI_PROT_SPI>;
- status = "okay";
-
- spi@1a280000 {
- status = "okay";
-
- pinctrl-0 = <&spi_pins>;
- pinctrl-names = "default";
-
- cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- #address-cells = <1>;
- #size-cells = <1>;
- spi-max-frequency = <50000000>;
- reg = <0>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SBL1";
- reg = <0x0 0x20000>;
- read-only;
- };
-
- partition@20000 {
- label = "MIBIB";
- reg = <0x20000 0x20000>;
- read-only;
- };
-
- partition@40000 {
- label = "SBL2";
- reg = <0x40000 0x20000>;
- read-only;
- };
-
- partition@60000 {
- label = "SBL3";
- reg = <0x60000 0x30000>;
- read-only;
- };
-
- partition@90000 {
- label = "DDRCONFIG";
- reg = <0x90000 0x10000>;
- read-only;
- };
-
- partition@a0000 {
- label = "SSD";
- reg = <0xa0000 0x10000>;
- read-only;
- };
-
- partition@b0000 {
- label = "TZ";
- reg = <0xb0000 0x30000>;
- read-only;
- };
-
- partition@e0000 {
- label = "RPM";
- reg = <0xe0000 0x20000>;
- read-only;
- };
-
- partition@100000 {
- label = "fs-uboot";
- reg = <0x100000 0x70000>;
- read-only;
- };
-
- partition@170000 {
- label = "uboot-env";
- reg = <0x170000 0x40000>;
- read-only;
- };
-
- partition@1b0000 {
- label = "radio";
- reg = <0x1b0000 0x40000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_radio_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_radio_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- partition@1f0000 {
- label = "os-image";
- reg = <0x1f0000 0x400000>;
- };
-
- partition@5f0000 {
- label = "rootfs";
- reg = <0x5f0000 0x1900000>;
- };
-
- defaultmac: partition@1ef0000 {
- label = "default-mac";
- reg = <0x1ef0000 0x00200>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_defaultmac_8: macaddr@8 {
- compatible = "mac-base";
- reg = <0x8 0x6>;
- #nvmem-cell-cells = <1>;
- };
- };
- };
-
- partition@1ef0200 {
- label = "pin";
- reg = <0x1ef0200 0x00200>;
- read-only;
- };
-
- partition@1ef0400 {
- label = "product-info";
- reg = <0x1ef0400 0x0fc00>;
- read-only;
- };
-
- partition@1f00000 {
- label = "partition-table";
- reg = <0x1f00000 0x10000>;
- read-only;
- };
-
- partition@1f10000 {
- label = "soft-version";
- reg = <0x1f10000 0x10000>;
- read-only;
- };
-
- partition@1f20000 {
- label = "support-list";
- reg = <0x1f20000 0x10000>;
- read-only;
- };
-
- partition@1f30000 {
- label = "profile";
- reg = <0x1f30000 0x10000>;
- read-only;
- };
-
- partition@1f40000 {
- label = "default-config";
- reg = <0x1f40000 0x10000>;
- read-only;
- };
-
- partition@1f50000 {
- label = "user-config";
- reg = <0x1f50000 0x40000>;
- read-only;
- };
-
- partition@1f90000 {
- label = "qos-db";
- reg = <0x1f90000 0x40000>;
- read-only;
- };
-
- partition@1fd0000 {
- label = "usb-config";
- reg = <0x1fd0000 0x10000>;
- read-only;
- };
-
- partition@1fe0000 {
- label = "log";
- reg = <0x1fe0000 0x20000>;
- read-only;
- };
- };
- };
- };
-};
-
-&hs_phy_0 {
- status = "okay";
-};
-
-&ss_phy_0 {
- status = "okay";
-};
-
-&usb3_0 {
- status = "okay";
-
- pinctrl-0 = <&usb0_pwr_en_pin>;
- pinctrl-names = "default";
-};
-
-&hs_phy_1 {
- status = "okay";
-};
-
-&ss_phy_1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-
- pinctrl-0 = <&usb1_pwr_en_pin>;
- pinctrl-names = "default";
-};
-
-&pcie0 {
- status = "okay";
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- compatible = "pci168c,0040";
- reg = <0x00010000 0 0 0 0>;
-
- nvmem-cells = <&macaddr_defaultmac_8 (-1)>, <&precal_radio_1000>;
- nvmem-cell-names = "mac-address", "pre-calibration";
- };
- };
-};
-
-&pcie1 {
- status = "okay";
- max-link-speed = <1>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- compatible = "pci168c,0040";
- reg = <0x00010000 0 0 0 0>;
-
- nvmem-cells = <&macaddr_defaultmac_8 0>, <&precal_radio_5000>;
- nvmem-cell-names = "mac-address", "pre-calibration";
- };
- };
-};
-
-&mdio0 {
- status = "okay";
-
- pinctrl-0 = <&mdio0_pins>;
- pinctrl-names = "default";
-
- switch@10 {
- compatible = "qca,qca8337";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x10>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "cpu";
- ethernet = <&gmac1>;
- phy-mode = "rgmii";
- tx-internal-delay-ps = <1000>;
- rx-internal-delay-ps = <1000>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- port@1 {
- reg = <1>;
- label = "lan4";
- phy-mode = "internal";
- phy-handle = <&phy_port1>;
- };
-
- port@2 {
- reg = <2>;
- label = "lan3";
- phy-mode = "internal";
- phy-handle = <&phy_port2>;
- };
-
- port@3 {
- reg = <3>;
- label = "lan2";
- phy-mode = "internal";
- phy-handle = <&phy_port3>;
- };
-
- port@4 {
- reg = <4>;
- label = "lan1";
- phy-mode = "internal";
- phy-handle = <&phy_port4>;
- };
-
- port@5 {
- reg = <5>;
- label = "wan";
- phy-mode = "internal";
- phy-handle = <&phy_port5>;
- };
-
- port@6 {
- reg = <6>;
- label = "cpu";
- ethernet = <&gmac2>;
- phy-mode = "sgmii";
- qca,sgmii-enable-pll;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy_port1: phy@0 {
- reg = <0>;
- };
-
- phy_port2: phy@1 {
- reg = <1>;
- };
-
- phy_port3: phy@2 {
- reg = <2>;
- };
-
- phy_port4: phy@3 {
- reg = <3>;
- };
-
- phy_port5: phy@4 {
- reg = <4>;
- };
- };
- };
-};
-
-&gmac1 {
- status = "okay";
- phy-mode = "rgmii";
- qcom,id = <1>;
-
- pinctrl-0 = <&rgmii2_pins>;
- pinctrl-names = "default";
-
- nvmem-cells = <&macaddr_defaultmac_8 1>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gmac2 {
- status = "okay";
- phy-mode = "sgmii";
- qcom,id = <2>;
-
- nvmem-cells = <&macaddr_defaultmac_8 0>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&adm_dma {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include <dt-bindings/leds/common.h>
-
-#include "qcom-ipq8064-ad7200-c2600.dtsi"
-
-/ {
- model = "TP-Link Talon AD7200";
- compatible = "tplink,ad7200", "qcom,ipq8064";
-
- aliases {
- led-boot = &led_status;
- led-failsafe = &led_status;
- led-running = &led_status;
- led-upgrade = &led_status;
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&button_pins>;
- pinctrl-names = "default";
-
- wifi {
- label = "wifi";
- gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RFKILL>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 7 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- wps {
- label = "wps";
- gpios = <&qcom_pinmux 67 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- led_enable {
- label = "led-enable";
- gpios = <&qcom_pinmux 53 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_LIGHTS_TOGGLE>;
- debounce-interval = <60>;
- wakeup-source;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- lan {
- function = LED_FUNCTION_LAN;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&qcom_pinmux 2 GPIO_ACTIVE_HIGH>;
- };
-
- usb1 {
- label = "blue:usb1";
- gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
- };
-
- wlan5g {
- label = "blue:wlan5g";
- gpios = <&qcom_pinmux 15 GPIO_ACTIVE_HIGH>;
- };
-
- usb3 {
- label = "blue:usb3";
- gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>;
- };
-
- wlan2g {
- label = "blue:wlan2g";
- gpios = <&qcom_pinmux 17 GPIO_ACTIVE_HIGH>;
- };
-
- wan_orange {
- function = LED_FUNCTION_WAN;
- color = <LED_COLOR_ID_ORANGE>;
- gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;
- };
-
- wan_blue {
- function = LED_FUNCTION_WAN;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&qcom_pinmux 33 GPIO_ACTIVE_LOW>;
- };
-
- wps {
- function = LED_FUNCTION_WPS;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>;
- };
-
- wlan60g {
- label = "blue:wlan60g";
- gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>;
- };
-
- led_status: status {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&qcom_pinmux 66 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&qcom_pinmux {
- button_pins: button_pins {
- mux {
- pins = "gpio53", "gpio54", "gpio67";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- led_pins: led_pins {
- mux {
- pins = "gpio2", "gpio8", "gpio15", "gpio16", "gpio17", "gpio26",
- "gpio33", "gpio55", "gpio56", "gpio66";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-};
-
-&mdio0 {
- switch@10 {
- ports {
- port@1 {
- label = "wan";
- };
-
- port@2 {
- label = "lan1";
- };
-
- port@3 {
- label = "lan2";
- };
-
- port@4 {
- label = "lan3";
- };
-
- port@5 {
- label = "lan4";
- };
- };
- };
-};
-
-&pcie2 {
- status = "okay";
- max-link-speed = <1>;
-};
+++ /dev/null
-#include "qcom-ipq8064-v1.0.dtsi"
-
-/ {
- model = "Qualcomm Technologies, Inc. IPQ8064/AP-148";
- compatible = "qcom,ipq8064-ap148", "qcom,ipq8064";
-
- memory@0 {
- reg = <0x42000000 0x1e000000>;
- device_type = "memory";
- };
-
- reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- rsvd@41200000 {
- reg = <0x41200000 0x300000>;
- no-map;
- };
- };
-
- aliases {
- mdio-gpio0 = &mdio0;
- };
-};
-
-&adm_dma {
- status = "okay";
-};
-
-&flash {
- partitions {
- compatible = "qcom,smem-part";
- };
-};
-
-&hs_phy_0 {
- status = "okay";
-};
-
-&ss_phy_0 {
- status = "okay";
-};
-
-&usb3_0 {
- status = "okay";
-};
-
-&hs_phy_1 {
- status = "okay";
-};
-
-&ss_phy_1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
-};
-
-&pcie1 {
- status = "okay";
- max-link-speed = <1>;
-};
-
-&nand {
- status = "okay";
-
- nand@0 {
- reg = <0>;
- compatible = "qcom,nandcs";
-
- nand-ecc-strength = <4>;
- nand-bus-width = <8>;
- nand-ecc-step-size = <512>;
-
- partitions {
- compatible = "qcom,smem-part";
- };
- };
-};
-
-&mdio0 {
- status = "okay";
-
- pinctrl-0 = <&mdio0_pins>;
- pinctrl-names = "default";
-
- switch@10 {
- compatible = "qca,qca8337";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x10>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "cpu";
- ethernet = <&gmac1>;
- phy-mode = "rgmii";
- tx-internal-delay-ps = <1000>;
- rx-internal-delay-ps = <1000>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- port@1 {
- reg = <1>;
- label = "lan1";
- phy-mode = "internal";
- phy-handle = <&phy_port1>;
- };
-
- port@2 {
- reg = <2>;
- label = "lan2";
- phy-mode = "internal";
- phy-handle = <&phy_port2>;
- };
-
- port@3 {
- reg = <3>;
- label = "lan3";
- phy-mode = "internal";
- phy-handle = <&phy_port3>;
- };
-
- port@4 {
- reg = <4>;
- label = "lan4";
- phy-mode = "internal";
- phy-handle = <&phy_port4>;
- };
-
- port@5 {
- reg = <5>;
- label = "wan";
- phy-mode = "internal";
- phy-handle = <&phy_port5>;
- };
-
- /*
- port@6 {
- reg = <0>;
- label = "cpu";
- ethernet = <&gmac2>;
- phy-mode = "rgmii";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- pause;
- asym-pause;
- };
- };
- */
- };
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy_port1: phy@0 {
- reg = <0>;
- };
-
- phy_port2: phy@1 {
- reg = <1>;
- };
-
- phy_port3: phy@2 {
- reg = <2>;
- };
-
- phy_port4: phy@3 {
- reg = <3>;
- };
-
- phy_port5: phy@4 {
- reg = <4>;
- };
- };
- };
-};
-
-&gmac1 {
- status = "okay";
- phy-mode = "rgmii";
- qcom,id = <1>;
-
- pinctrl-0 = <&rgmii2_pins>;
- pinctrl-names = "default";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gmac2 {
- status = "okay";
- phy-mode = "sgmii";
- qcom,id = <2>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
+++ /dev/null
-#include "qcom-ipq8064-v1.0.dtsi"
-
-/ {
- model = "Qualcomm IPQ8064/AP161";
- compatible = "qcom,ipq8064-ap161", "qcom,ipq8064";
-
- memory@0 {
- reg = <0x42000000 0x1e000000>;
- device_type = "memory";
- };
-
- reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- rsvd@41200000 {
- reg = <0x41200000 0x300000>;
- no-map;
- };
- };
-
- aliases {
- mdio-gpio0 = &mdio0;
- };
-};
-
-&qcom_pinmux {
- rgmii2_pins: rgmii2-pins {
- mux {
- pins = "gpio27", "gpio28", "gpio29",
- "gpio30", "gpio31", "gpio32",
- "gpio51", "gpio52", "gpio59",
- "gpio60", "gpio61", "gpio62",
- "gpio2", "gpio66";
- };
- };
-};
-
-&flash {
- partitions {
- compatible = "qcom,smem-part";
- };
-};
-
-&hs_phy_0 {
- status = "okay";
-};
-
-&ss_phy_0 {
- status = "okay";
-};
-
-&usb3_0 {
- status = "okay";
-};
-
-&hs_phy_1 {
- status = "okay";
-};
-
-&ss_phy_1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
-};
-
-&pcie1 {
- status = "okay";
- max-link-speed = <1>;
-};
-
-&pcie2 {
- status = "okay";
-};
-
-&nand {
- status = "okay";
-
- nand@0 {
- reg = <0>;
- compatible = "qcom,nandcs";
-
- nand-ecc-strength = <4>;
- nand-bus-width = <8>;
- nand-ecc-step-size = <512>;
-
- partitions {
- compatible = "qcom,smem-part";
- };
- };
-};
-
-&mdio0 {
- status = "okay";
-
- pinctrl-0 = <&mdio0_pins>;
- pinctrl-names = "default";
-
- switch@10 {
- compatible = "qca,qca8337";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x10>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "cpu";
- ethernet = <&gmac0>;
- phy-mode = "rgmii";
- tx-internal-delay-ps = <1000>;
- rx-internal-delay-ps = <1000>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- port@1 {
- reg = <1>;
- label = "lan4";
- phy-mode = "internal";
- phy-handle = <&phy_port1>;
- };
-
- port@2 {
- reg = <2>;
- label = "lan3";
- phy-mode = "internal";
- phy-handle = <&phy_port2>;
- };
-
- port@3 {
- reg = <3>;
- label = "lan2";
- phy-mode = "internal";
- phy-handle = <&phy_port3>;
- };
-
- port@4 {
- reg = <4>;
- label = "lan1";
- phy-mode = "internal";
- phy-handle = <&phy_port4>;
- };
-
- port@5 {
- reg = <5>;
- label = "wan";
- phy-mode = "internal";
- phy-handle = <&phy_port5>;
- };
-
- /*
- port@6 {
- reg = <0>;
- label = "cpu";
- ethernet = <&gmac2>;
- phy-mode = "rgmii";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- pause;
- asym-pause;
- };
- };
- */
- };
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy_port1: phy@0 {
- reg = <0>;
- };
-
- phy_port2: phy@1 {
- reg = <1>;
- };
-
- phy_port3: phy@2 {
- reg = <2>;
- };
-
- phy_port4: phy@3 {
- reg = <3>;
- };
-
- phy_port5: phy@4 {
- reg = <4>;
- };
- };
- };
-
- phy3: ethernet-phy@3 {
- device_type = "ethernet-phy";
- reg = <3>;
- };
-};
-
-&gmac0 {
- status = "okay";
- phy-mode = "rgmii";
- qcom,id = <0>;
-
- pinctrl-0 = <&rgmii2_pins>;
- pinctrl-names = "default";
- mdiobus = <&mdio0>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gmac1 {
- status = "okay";
- phy-mode = "rgmii";
- qcom,id = <1>;
- mdiobus = <&mdio0>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gmac2 {
- status = "okay";
- phy-mode = "sgmii";
- qcom,id = <2>;
- mdiobus = <&mdio0>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&adm_dma {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2014 The ChromiumOS Authors
- */
-
-#include "qcom-ipq8064-onhub.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,gsbi.h>
-
-/ {
- model = "ASUS OnHub";
- compatible = "asus,onhub", "google,arkham", "qcom,ipq8064";
-};
-
-&qcom_pinmux {
- ap3223_pins: ap3223_pinmux {
- pins = "gpio22";
- function = "gpio";
- bias-none;
- };
-
- i2c7_pins: i2c7_pinmux {
- mux {
- pins = "gpio8", "gpio9";
- function = "gsbi7";
- };
- data {
- pins = "gpio8";
- bias-disable;
- };
- clk {
- pins = "gpio9";
- bias-disable;
- };
- };
-};
-
-&gsbi7 {
- status = "okay";
- qcom,mode = <GSBI_PROT_I2C_UART>;
-};
-
-&gsbi7_i2c {
- status = "okay";
- clock-frequency = <100000>;
- pinctrl-0 = <&i2c7_pins>;
- pinctrl-names = "default";
-
- ap3223@1c {
- compatible = "dynaimage,ap3223";
- reg = <0x1c>;
-
- pinctrl-0 = <&ap3223_pins>;
- pinctrl-names = "default";
-
- int-gpio = <&qcom_pinmux 22 GPIO_ACTIVE_LOW>;
- };
-
- led-controller@32 {
- compatible = "national,lp5523";
- reg = <0x32>;
- clock-mode = /bits/ 8 <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- led@4 {
- reg = <4>;
- color = <LED_COLOR_ID_GREEN>;
- chan-name = "green:status";
- linux,default-trigger = "default-on";
- led-cur = /bits/ 8 <0xfa>;
- max-cur = /bits/ 8 <0xff>;
- };
-
- led@5 {
- reg = <5>;
- color = <LED_COLOR_ID_BLUE>;
- chan-name = "blue:status";
- led-cur = /bits/ 8 <0xfa>;
- max-cur = /bits/ 8 <0xff>;
- };
-
- led@8 {
- reg = <8>;
- color = <LED_COLOR_ID_RED>;
- chan-name = "red:status";
- led-cur = /bits/ 8 <0xfa>;
- max-cur = /bits/ 8 <0xff>;
- };
- };
-};
+++ /dev/null
-#include <dt-bindings/leds/common.h>
-
-#include "qcom-ipq8064-ad7200-c2600.dtsi"
-
-/ {
- model = "TP-Link Archer C2600";
- compatible = "tplink,c2600", "qcom,ipq8064";
-
- aliases {
- led-boot = &power;
- led-failsafe = &general;
- led-running = &power;
- led-upgrade = &general;
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&button_pins>;
- pinctrl-names = "default";
-
- wifi {
- label = "wifi";
- gpios = <&qcom_pinmux 49 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RFKILL>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- wps {
- label = "wps";
- gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- ledswitch {
- label = "ledswitch";
- gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_LIGHTS_TOGGLE>;
- debounce-interval = <60>;
- wakeup-source;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- lan {
- function = LED_FUNCTION_LAN;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 6 GPIO_ACTIVE_HIGH>;
- };
-
- usb4 {
- label = "white:usb_4";
- gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
- };
-
- usb2 {
- label = "white:usb_2";
- gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
- };
-
- wps {
- function = LED_FUNCTION_WPS;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
- };
-
- wan_amber {
- function = LED_FUNCTION_WAN;
- color = <LED_COLOR_ID_AMBER>;
- gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;
- };
-
- wan_white {
- function = LED_FUNCTION_WAN;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 33 GPIO_ACTIVE_LOW>;
- };
-
- power: power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
- default-state = "keep";
- };
-
- general: general {
- label = "white:general";
- gpios = <&qcom_pinmux 66 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&qcom_pinmux {
- button_pins: button_pins {
- mux {
- pins = "gpio16", "gpio54", "gpio65";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- led_pins: led_pins {
- mux {
- pins = "gpio6", "gpio7", "gpio8", "gpio9", "gpio26", "gpio33",
- "gpio53", "gpio66";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-};
+++ /dev/null
-#include "qcom-ipq8064-v2.0-smb208.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "Netgear Nighthawk X4 D7800";
- compatible = "netgear,d7800", "qcom,ipq8064";
-
- memory@0 {
- reg = <0x42000000 0x1e000000>;
- device_type = "memory";
- };
-
- reserved-memory {
- rsvd@5fe00000 {
- reg = <0x5fe00000 0x200000>;
- reusable;
- };
- };
-
- aliases {
- mdio-gpio0 = &mdio0;
-
- led-boot = &power_white;
- led-failsafe = &power_amber;
- led-running = &power_white;
- led-upgrade = &power_amber;
- };
-
- chosen {
- bootargs = "rootfstype=squashfs noinitrd";
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&button_pins>;
- pinctrl-names = "default";
-
- wifi {
- label = "wifi";
- gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RFKILL>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- wps {
- label = "wps";
- gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- debounce-interval = <60>;
- wakeup-source;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- usb1 {
- label = "white:usb1";
- gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
- };
-
- usb2 {
- label = "white:usb2";
- gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
- };
-
- power_amber: power_amber {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_AMBER>;
- gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
- };
-
- wan_white {
- function = LED_FUNCTION_WAN;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
- };
-
- wan_amber {
- function = LED_FUNCTION_WAN;
- color = <LED_COLOR_ID_AMBER>;
- gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
- };
-
- wps {
- function = LED_FUNCTION_WPS;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
- };
-
- esata {
- label = "white:esata";
- gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
- };
-
- power_white: power_white {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
- default-state = "keep";
- };
-
- wifi {
- label = "white:wifi";
- gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&qcom_pinmux {
- button_pins: button_pins {
- mux {
- pins = "gpio6", "gpio54", "gpio65";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- led_pins: led_pins {
- mux {
- pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23",
- "gpio24","gpio26", "gpio53", "gpio64";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- usb0_pwr_en_pins: usb0_pwr_en_pins {
- mux {
- pins = "gpio15";
- function = "gpio";
- drive-strength = <12>;
- bias-pull-down;
- output-high;
- };
- };
-
- usb1_pwr_en_pins: usb1_pwr_en_pins {
- mux {
- pins = "gpio16", "gpio68";
- function = "gpio";
- drive-strength = <12>;
- bias-pull-down;
- output-high;
- };
- };
-};
-
-&sata_phy {
- status = "okay";
-};
-
-&sata {
- status = "okay";
-};
-
-&hs_phy_0 {
- status = "okay";
-};
-
-&ss_phy_0 {
- status = "okay";
-};
-
-&usb3_0 {
- status = "okay";
-
- pinctrl-0 = <&usb0_pwr_en_pins>;
- pinctrl-names = "default";
-};
-
-&hs_phy_1 {
- status = "okay";
-};
-
-&ss_phy_1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-
- pinctrl-0 = <&usb1_pwr_en_pins>;
- pinctrl-names = "default";
-};
-
-&pcie0 {
- status = "okay";
- reset-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>;
- pinctrl-0 = <&pcie0_pins>;
- pinctrl-names = "default";
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- compatible = "pci168c,0040";
- reg = <0x00010000 0 0 0 0>;
-
- nvmem-cells = <&macaddr_art_6 1>, <&precal_art_1000>;
- nvmem-cell-names = "mac-address", "pre-calibration";
- };
- };
-};
-
-&pcie1 {
- status = "okay";
- reset-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>;
- pinctrl-0 = <&pcie1_pins>;
- pinctrl-names = "default";
- max-link-speed = <1>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- compatible = "pci168c,0040";
- reg = <0x00010000 0 0 0 0>;
-
- nvmem-cells = <&macaddr_art_6 2>, <&precal_art_5000>;
- nvmem-cell-names = "mac-address", "pre-calibration";
- };
- };
-};
-
-&pcie2 {
- status = "okay";
- reset-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_HIGH>;
- pinctrl-0 = <&pcie2_pins>;
- pinctrl-names = "default";
-};
-
-&nand {
- status = "okay";
-
- nand@0 {
- reg = <0>;
- compatible = "qcom,nandcs";
-
- nand-ecc-strength = <4>;
- nand-bus-width = <8>;
- nand-ecc-step-size = <512>;
-
- nand-is-boot-medium;
- qcom,boot-partitions = <0x0 0x1180000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- qcadata@0 {
- label = "qcadata";
- reg = <0x0000000 0x0c80000>;
- read-only;
- };
-
- APPSBL@c80000 {
- label = "APPSBL";
- reg = <0x0c80000 0x0500000>;
- read-only;
- };
-
- APPSBLENV@1180000 {
- label = "APPSBLENV";
- reg = <0x1180000 0x0080000>;
- read-only;
- };
-
- art@1200000 {
- label = "art";
- reg = <0x1200000 0x0140000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_art_0: macaddr@0 {
- reg = <0x0 0x6>;
- };
-
- macaddr_art_6: macaddr@6 {
- compatible = "mac-base";
- reg = <0x6 0x6>;
- #nvmem-cell-cells = <1>;
- };
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- artbak: art@1340000 {
- label = "artbak";
- reg = <0x1340000 0x0140000>;
- read-only;
- };
-
- kernel@1480000 {
- label = "kernel";
- reg = <0x1480000 0x0400000>;
- };
-
- ubi@1880000 {
- label = "ubi";
- reg = <0x1880000 0x6080000>;
- };
-
- reserve@7900000 {
- label = "reserve";
- reg = <0x7900000 0x0700000>;
- read-only;
- };
- };
- };
-};
-
-&mdio0 {
- status = "okay";
-
- pinctrl-0 = <&mdio0_pins>;
- pinctrl-names = "default";
-
- switch@10 {
- compatible = "qca,qca8337";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x10>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "cpu";
- ethernet = <&gmac1>;
- phy-mode = "rgmii";
- tx-internal-delay-ps = <1000>;
- rx-internal-delay-ps = <1000>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- port@1 {
- reg = <1>;
- label = "lan1";
- phy-mode = "internal";
- phy-handle = <&phy_port1>;
- };
-
- port@2 {
- reg = <2>;
- label = "lan2";
- phy-mode = "internal";
- phy-handle = <&phy_port2>;
- };
-
- port@3 {
- reg = <3>;
- label = "lan3";
- phy-mode = "internal";
- phy-handle = <&phy_port3>;
- };
-
- port@4 {
- reg = <4>;
- label = "lan4";
- phy-mode = "internal";
- phy-handle = <&phy_port4>;
- };
-
- port@5 {
- reg = <5>;
- label = "wan";
- phy-mode = "internal";
- phy-handle = <&phy_port5>;
- };
-
- port@6 {
- reg = <6>;
- label = "cpu";
- ethernet = <&gmac2>;
- phy-mode = "sgmii";
- qca,sgmii-enable-pll;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy_port1: phy@0 {
- reg = <0>;
- };
-
- phy_port2: phy@1 {
- reg = <1>;
- };
-
- phy_port3: phy@2 {
- reg = <2>;
- };
-
- phy_port4: phy@3 {
- reg = <3>;
- };
-
- phy_port5: phy@4 {
- reg = <4>;
- };
- };
- };
-};
-
-&gmac1 {
- status = "okay";
- phy-mode = "rgmii";
- qcom,id = <1>;
-
- pinctrl-0 = <&rgmii2_pins>;
- pinctrl-names = "default";
-
- nvmem-cells = <&macaddr_art_6 0>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gmac2 {
- status = "okay";
- phy-mode = "sgmii";
- qcom,id = <2>;
-
- nvmem-cells = <&macaddr_art_0>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&adm_dma {
- status = "okay";
-};
+++ /dev/null
-#include "qcom-ipq8064-v1.0.dtsi"
-
-/ {
- model = "Qualcomm IPQ8064/DB149";
- compatible = "qcom,ipq8064-db149", "qcom,ipq8064";
-
- aliases {
- serial0 = &gsbi2_serial;
- };
-
- reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- rsvd@41200000 {
- reg = <0x41200000 0x300000>;
- no-map;
- };
- };
-};
-
-&qcom_pinmux {
- rgmii0_pins: rgmii0_pins {
- mux {
- pins = "gpio2", "gpio66";
- drive-strength = <8>;
- bias-disable;
- };
- };
-};
-
-&gsbi2 {
- qcom,mode = <GSBI_PROT_I2C_UART>;
- status = "okay";
-
- gsbi2_serial: serial@12490000 {
- status = "okay";
- };
-};
-
-&gsbi4 {
- status = "disabled";
-};
-
-&gsbi4_serial {
- status = "disabled";
-};
-
-&flash {
- m25p,fast-read;
-
- partition@0 {
- label = "lowlevel_init";
- reg = <0x0 0x1b0000>;
- };
-
- partition@1 {
- label = "u-boot";
- reg = <0x1b0000 0x80000>;
- };
-
- partition@2 {
- label = "u-boot-env";
- reg = <0x230000 0x40000>;
- };
-
- partition@3 {
- label = "caldata";
- reg = <0x270000 0x40000>;
- };
-
- partition@4 {
- label = "firmware";
- reg = <0x2b0000 0x1d50000>;
- };
-};
-
-&hs_phy_0 {
- status = "okay";
-};
-
-&ss_phy_0 {
- status = "okay";
-};
-
-&usb3_0 {
- status = "okay";
-};
-
-&hs_phy_1 {
- status = "okay";
-};
-
-&ss_phy_1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
-};
-
-&pcie1 {
- status = "okay";
-};
-
-&pcie2 {
- status = "okay";
-};
-
-&mdio0 {
- status = "okay";
-
- pinctrl-0 = <&mdio0_pins>;
- pinctrl-names = "default";
-
- switch@10 {
- compatible = "qca,qca8337";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x10>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "cpu";
- ethernet = <&gmac0>;
- phy-mode = "rgmii";
- tx-internal-delay-ps = <1000>;
- rx-internal-delay-ps = <1000>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- port@1 {
- reg = <1>;
- label = "lan4";
- phy-mode = "internal";
- phy-handle = <&phy_port1>;
- };
-
- port@2 {
- reg = <2>;
- label = "lan3";
- phy-mode = "internal";
- phy-handle = <&phy_port2>;
- };
-
- port@3 {
- reg = <3>;
- label = "lan2";
- phy-mode = "internal";
- phy-handle = <&phy_port3>;
- };
-
- port@4 {
- reg = <4>;
- label = "lan1";
- phy-mode = "internal";
- phy-handle = <&phy_port4>;
- };
-
- port@5 {
- reg = <5>;
- label = "wan";
- phy-mode = "internal";
- phy-handle = <&phy_port5>;
- };
-
- /*
- port@6 {
- reg = <0>;
- label = "cpu";
- ethernet = <&gmac2>;
- phy-mode = "rgmii";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- pause;
- asym-pause;
- };
- };
- */
- };
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy_port1: phy@0 {
- reg = <0>;
- };
-
- phy_port2: phy@1 {
- reg = <1>;
- };
-
- phy_port3: phy@2 {
- reg = <2>;
- };
-
- phy_port4: phy@3 {
- reg = <3>;
- };
-
- phy_port5: phy@4 {
- reg = <4>;
- };
- };
- };
-
- phy6: ethernet-phy@6 {
- reg = <6>;
- };
-
- phy7: ethernet-phy@7 {
- reg = <7>;
- };
-};
-
-&gmac0 {
- status = "okay";
- phy-mode = "rgmii";
- qcom,id = <0>;
-
- pinctrl-0 = <&rgmii0_pins>;
- pinctrl-names = "default";
-};
-
-&gmac1 {
- status = "okay";
- phy-mode = "sgmii";
- qcom,id = <1>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gmac2 {
- status = "okay";
- phy-mode = "sgmii";
- qcom,id = <2>;
- phy-handle = <&phy6>;
-};
-
-&gmac3 {
- status = "okay";
- phy-mode = "sgmii";
- qcom,id = <3>;
- phy-handle = <&phy7>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include <dt-bindings/leds/common.h>
-
-#include "qcom-ipq8064-eax500.dtsi"
-
-/ {
- model = "Linksys EA7500 V1 WiFi Router";
- compatible = "linksys,ea7500-v1", "qcom,ipq8064";
-
- memory@0 {
- reg = <0x42000000 0xe000000>;
- device_type = "memory";
- };
-
- aliases {
- led-boot = &led_power;
- led-failsafe = &led_power;
- led-running = &led_power;
- led-upgrade = &led_power;
- };
-
- chosen {
- /* look for root deviceblock nbr in this bootarg */
- find-rootblock = "ubi.mtd=";
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&button_pins>;
- pinctrl-names = "default";
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- wps {
- label = "wps";
- gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- debounce-interval = <60>;
- wakeup-source;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- led_power: power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
- default-state = "keep";
- };
- };
-};
-
-&qcom_pinmux {
- button_pins: button_pins {
- mux {
- pins = "gpio65", "gpio68";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- led_pins: led_pins {
- mux {
- pins = "gpio6";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-};
-
-&partitions {
- partition@5f80000 {
- label = "sysdiag";
- reg = <0x5f80000 0x100000>;
- };
-
- partition@6080000 {
- label = "syscfg";
- reg = <0x6080000 0x1f80000>;
- };
-};
-
-&mdio0 {
- switch@10 {
- ports {
- port@1 {
- label = "wan";
- };
-
- port@2 {
- label = "lan1";
- };
-
- port@3 {
- label = "lan2";
- };
-
- port@4 {
- label = "lan3";
- };
-
- port@5 {
- label = "lan4";
- };
- };
- };
-};
+++ /dev/null
-#include <dt-bindings/leds/common.h>
-
-#include "qcom-ipq8064-eax500.dtsi"
-
-/ {
- model = "Linksys EA8500 WiFi Router";
- compatible = "linksys,ea8500", "qcom,ipq8064";
-
- memory@0 {
- reg = <0x42000000 0x1e000000>;
- device_type = "memory";
- };
-
- aliases {
- mdio-gpio0 = &mdio0;
-
- led-boot = &led_power;
- led-failsafe = &led_power;
- led-running = &led_power;
- led-upgrade = &led_power;
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&button_pins>;
- pinctrl-names = "default";
-
- wifi {
- label = "wifi";
- gpios = <&qcom_pinmux 67 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RFKILL>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- wps {
- label = "wps";
- gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- debounce-interval = <60>;
- wakeup-source;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- wps {
- function = LED_FUNCTION_WPS;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
- };
-
- led_power: power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
- default-state = "keep";
- };
-
- wifi {
- label = "green:wifi";
- gpios = <&qcom_pinmux 54 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&qcom_pinmux {
- button_pins: button_pins {
- mux {
- pins = "gpio65", "gpio67", "gpio68";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- led_pins: led_pins {
- mux {
- pins = "gpio6", "gpio53", "gpio54";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-};
-
-&sata_phy {
- status = "okay";
-};
-
-&sata {
- status = "okay";
-};
-
-&partitions {
- partition@5f80000 {
- label = "syscfg";
- reg = <0x5f80000 0x2080000>;
- };
-};
-
-&gmac1 {
- qcom,phy_mdio_addr = <4>;
- qcom,poll_required = <1>;
- qcom,rgmii_delay = <0>;
- qcom,emulation = <0>;
-};
-
-/* LAN */
-&gmac2 {
- qcom,phy_mdio_addr = <0>; /* none */
- qcom,poll_required = <0>; /* no polling */
- qcom,rgmii_delay = <0>;
- qcom,emulation = <0>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq8064-v2.0-smb208.dtsi"
-
-#include <dt-bindings/input/input.h>
-
-/ {
- chosen {
- bootargs = "console=ttyMSM0,115200n8";
- /* append to bootargs adding the root deviceblock nbr from bootloader */
- append-rootblock = "ubi.mtd=";
- };
-};
-
-&qcom_pinmux {
- /* eax500 routers reuse the pcie2 reset pin for switch reset pin */
- switch_reset: switch_reset_pins {
- mux {
- pins = "gpio63";
- function = "gpio";
- drive-strength = <12>;
- bias-pull-up;
- };
- };
-};
-
-&hs_phy_0 {
- status = "okay";
-};
-
-&ss_phy_0 {
- status = "okay";
-};
-
-&usb3_0 {
- status = "okay";
-};
-
-&hs_phy_1 {
- status = "okay";
-};
-
-&ss_phy_1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
-
- max-link-speed = <1>;
-};
-
-&pcie1 {
- status = "okay";
-};
-
-&nand {
- status = "okay";
-
- nand@0 {
- reg = <0>;
- compatible = "qcom,nandcs";
-
- nand-ecc-strength = <4>;
- nand-bus-width = <8>;
- nand-ecc-step-size = <512>;
-
- nand-is-boot-medium;
- qcom,boot-partitions = <0x0 0x0c80000>;
-
- partitions: partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SBL1";
- reg = <0x0000000 0x0040000>;
- read-only;
- };
-
- partition@40000 {
- label = "MIBIB";
- reg = <0x0040000 0x0140000>;
- read-only;
- };
-
- partition@180000 {
- label = "SBL2";
- reg = <0x0180000 0x0140000>;
- read-only;
- };
-
- partition@2c0000 {
- label = "SBL3";
- reg = <0x02c0000 0x0280000>;
- read-only;
- };
-
- partition@540000 {
- label = "DDRCONFIG";
- reg = <0x0540000 0x0120000>;
- read-only;
- };
-
- partition@660000 {
- label = "SSD";
- reg = <0x0660000 0x0120000>;
- read-only;
- };
-
- partition@780000 {
- label = "TZ";
- reg = <0x0780000 0x0280000>;
- read-only;
- };
-
- partition@a00000 {
- label = "RPM";
- reg = <0x0a00000 0x0280000>;
- read-only;
- };
-
- art: partition@c80000 {
- label = "art";
- reg = <0x0c80000 0x0140000>;
- read-only;
- };
-
- partition@dc0000 {
- label = "APPSBL";
- reg = <0x0dc0000 0x0100000>;
- read-only;
- };
-
- partition@ec0000 {
- label = "u_env";
- reg = <0x0ec0000 0x0040000>;
- };
-
- partition@f00000 {
- label = "s_env";
- reg = <0x0f00000 0x0040000>;
- };
-
- partition@f40000 {
- label = "devinfo";
- reg = <0x0f40000 0x0040000>;
- };
-
- partition@f80000 {
- label = "kernel1";
- reg = <0x0f80000 0x2800000>; /* 4 MB, spill to rootfs */
- };
-
- partition@1380000 {
- label = "rootfs1";
- reg = <0x1380000 0x2400000>;
- };
-
- partition@3780000 {
- label = "kernel2";
- reg = <0x3780000 0x2800000>;
- };
-
- partition@3b80000 {
- label = "rootfs2";
- reg = <0x3b80000 0x2400000>;
- };
- };
- };
-};
-
-&mdio0 {
- status = "okay";
-
- pinctrl-0 = <&mdio0_pins>;
- pinctrl-names = "default";
-
- /* Switch from documentation require at least 10ms for reset */
- reset-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_HIGH>;
- reset-post-delay-us = <12000>;
-
- switch@10 {
- compatible = "qca,qca8337";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x10>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "cpu";
- ethernet = <&gmac1>;
- phy-mode = "rgmii";
- tx-internal-delay-ps = <1000>;
- rx-internal-delay-ps = <1000>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- port@1 {
- reg = <1>;
- label = "lan1";
- phy-mode = "internal";
- phy-handle = <&phy_port1>;
- };
-
- port@2 {
- reg = <2>;
- label = "lan2";
- phy-mode = "internal";
- phy-handle = <&phy_port2>;
- };
-
- port@3 {
- reg = <3>;
- label = "lan3";
- phy-mode = "internal";
- phy-handle = <&phy_port3>;
- };
-
- port@4 {
- reg = <4>;
- label = "lan4";
- phy-mode = "internal";
- phy-handle = <&phy_port4>;
- };
-
- port@5 {
- reg = <5>;
- label = "wan";
- phy-mode = "internal";
- phy-handle = <&phy_port5>;
- };
-
- port@6 {
- reg = <6>;
- label = "cpu";
- ethernet = <&gmac2>;
- phy-mode = "sgmii";
- qca,sgmii-enable-pll;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy_port1: phy@0 {
- reg = <0>;
- };
-
- phy_port2: phy@1 {
- reg = <1>;
- };
-
- phy_port3: phy@2 {
- reg = <2>;
- };
-
- phy_port4: phy@3 {
- reg = <3>;
- };
-
- phy_port5: phy@4 {
- reg = <4>;
- };
- };
- };
-};
-
-&gmac1 {
- status = "okay";
-
- phy-mode = "rgmii";
- qcom,id = <1>;
-
- pinctrl-0 = <&rgmii2_pins>;
- pinctrl-names = "default";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gmac2 {
- status = "okay";
-
- phy-mode = "sgmii";
- qcom,id = <2>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&adm_dma {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq8064-smb208.dtsi"
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "Fortinet FAP-421E";
- compatible = "fortinet,fap-421e", "qcom,ipq8064";
-
- memory@42000000 {
- device_type = "memory";
- reg = <0x42000000 0xe000000>;
- };
-
- reserved-memory {
- rsvd@41200000 {
- no-map;
- reg = <0x41200000 0x300000>;
- };
- wifi_dump@44000000 {
- no-map;
- reg = <0x44000000 0x600000>;
- };
- };
-
- aliases {
- led-boot = &led_power_yellow;
- led-failsafe = &led_power_yellow;
- led-running = &led_power_yellow;
- led-upgrade = &led_power_yellow;
- label-mac-device = &gmac0;
- };
-
- chosen {
- bootargs-override = "console=ttyMSM0,9600n8";
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&button_pins>;
- pinctrl-names = "default";
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 56 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- eth1-amber {
- label = "amber:eth1";
- gpios = <&qcom_pinmux 27 GPIO_ACTIVE_LOW>;
- };
-
- eth1-yellow {
- label = "yellow:eth1";
- gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;
- };
-
- eth2-amber {
- label = "amber:eth2";
- gpios = <&qcom_pinmux 29 GPIO_ACTIVE_LOW>;
- };
-
- eth2-yellow {
- label = "yellow:eth2";
- gpios = <&qcom_pinmux 28 GPIO_ACTIVE_LOW>;
- };
-
- power-amber {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_AMBER>;
- gpios = <&qcom_pinmux 53 GPIO_ACTIVE_LOW>;
- };
-
- led_power_yellow: power-yellow {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_YELLOW>;
- gpios = <&qcom_pinmux 58 GPIO_ACTIVE_LOW>;
- };
-
- 2g-yellow {
- label = "yellow:2g";
- gpios = <&qcom_pinmux 30 GPIO_ACTIVE_LOW>;
- };
-
- 5g-yellow {
- label = "yellow:5g";
- gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-&qcom_pinmux {
- button_pins: button_pins {
- mux {
- bias-pull-up;
- drive-strength = <2>;
- pins = "gpio56";
- };
- };
-
- led_pins: led_pins {
- mux {
- bias-pull-down;
- drive-strength = <2>;
- function = "gpio";
- output-low;
- pins = "gpio23";
- };
- };
-
- rgmii2_pins: rgmii2-pins {
- mux {
- bias-disable;
- drive-strength = <16>;
- function = "rgmii2";
- pins = "gpio66";
- };
- };
-
- spi_pins: spi_pins {
- mux {
- pins = "gpio18", "gpio19", "gpio21";
- function = "gsbi5";
- bias-pull-down;
- };
-
- data {
- pins = "gpio18", "gpio19";
- drive-strength = <10>;
- };
-
- cs {
- pins = "gpio20";
- drive-strength = <10>;
- bias-pull-up;
- };
-
- clk {
- pins = "gpio21";
- drive-strength = <12>;
- };
- };
-
- uart0_pins: uart0_pins {
- mux {
- bias-disable;
- drive-strength = <12>;
- function = "gsbi7";
- pins = "gpio6", "gpio7";
- };
- };
-
- usb_pwr_en_pins: usb_pwr_en_pins {
- mux {
- pins = "gpio22";
- function = "gpio";
- drive-strength = <12>;
- bias-pull-down;
- output-low;
- };
- };
-};
-
-&gsbi7 {
- qcom,mode = <GSBI_PROT_I2C_UART>;
-
- status = "okay";
-};
-
-&gsbi7_serial{
- pinctrl-0 = <&uart0_pins>;
- pinctrl-names = "default";
-
- status = "okay";
-};
-
-&gsbi5 {
- qcom,mode = <GSBI_PROT_SPI>;
-
- status = "okay";
-
- spi@1a280000 {
- status = "okay";
-
- pinctrl-0 = <&spi_pins>;
- pinctrl-names = "default";
- cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- #address-cells = <1>;
- #size-cells = <1>;
- spi-max-frequency = <50000000>;
- reg = <0>;
- m25p,fast-read;
-
- partition@0 {
- label = "SBL1";
- reg = <0x0 0x20000>;
- read-only;
- };
-
- partition@20000 {
- label = "MIBIB";
- reg = <0x20000 0x20000>;
- read-only;
- };
-
- partition@40000 {
- label = "SBL2";
- reg = <0x40000 0x40000>;
- read-only;
- };
-
- partition@80000 {
- label = "SBL3";
- reg = <0x80000 0x80000>;
- read-only;
- };
-
- partition@100000 {
- label = "DDRCONFIG";
- reg = <0x100000 0x10000>;
- read-only;
- };
-
- partition@110000 {
- label = "SSD";
- reg = <0x110000 0x10000>;
- read-only;
- };
-
- partition@120000 {
- label = "TZ";
- reg = <0x120000 0x80000>;
- read-only;
- };
-
- partition@1a0000 {
- label = "RPM";
- reg = <0x1a0000 0x80000>;
- read-only;
- };
-
- partition@220000 {
- label = "APPSBL";
- reg = <0x220000 0x80000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_appsbl_7ff80: mac-address@7ff80 {
- compatible = "mac-base";
- reg = <0x7ff80 0xc>;
- #nvmem-cell-cells = <1>;
- };
- };
- };
-
- partition@2a0000 {
- label = "APPSBLENV";
- reg = <0x2a0000 0x40000>;
- };
-
- partition@2e0000 {
- label = "ART";
- reg = <0x2e0000 0x40000>;
- read-only;
- };
-
- partition@320000 {
- label = "kernel";
- reg = <0x320000 0x600000>;
- };
-
- partition@920000 {
- label = "ubi";
- reg = <0x920000 0x1400000>;
- };
-
- partition@1d20000 {
- label = "reserved";
- reg = <0x1d20000 0x260000>;
- read-only;
- };
-
- partition@1f80000 {
- label = "config";
- reg = <0x1f80000 0x80000>;
- read-only;
- };
- };
- };
-};
-
-&hs_phy_1 {
- status = "okay";
-};
-
-&ss_phy_1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-
- pinctrl-0 = <&usb_pwr_en_pins>;
- pinctrl-names = "default";
-};
-
-&pcie0 {
- status = "okay";
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- compatible = "pci168c,0040";
- reg = <0x00010000 0 0 0 0>;
-
- nvmem-cells = <&macaddr_appsbl_7ff80 8>;
- nvmem-cell-names = "mac-address";
- };
- };
-};
-
-&pcie1 {
- status = "okay";
-
- max-link-speed = <1>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- compatible = "pci168c,0040";
- reg = <0x00010000 0 0 0 0>;
-
- nvmem-cells = <&macaddr_appsbl_7ff80 16>;
- nvmem-cell-names = "mac-address";
- };
- };
-};
-
-&adm_dma {
- status = "okay";
-};
-
-&mdio0 {
- status = "okay";
-
- #address-cells = <0x1>;
- #size-cells = <0x0>;
- gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>,
- <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
- pinctrl-0 = <&mdio0_pins>;
- pinctrl-names = "default";
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
-
- phy2: ethernet-phy@2 {
- reg = <2>;
- };
-};
-
-&gmac0 {
- status = "okay";
-
- phy-mode = "rgmii";
- qcom,id = <0>;
- pinctrl-0 = <&rgmii2_pins>;
- pinctrl-names = "default";
- nvmem-cells = <&macaddr_appsbl_7ff80 0>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gmac2 {
- status = "okay";
-
- phy-mode = "sgmii";
- qcom,id = <2>;
- nvmem-cells = <&macaddr_appsbl_7ff80 1>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-#include "qcom-ipq8064-v2.0-smb208.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- compatible = "asrock,g10", "qcom,ipq8064";
- model = "ASRock G10";
-
- aliases {
- ethernet0 = &gmac1;
- ethernet1 = &gmac0;
-
- led-boot = &led_status_blue;
- led-failsafe = &led_status_amber;
- led-running = &led_status_blue;
- led-upgrade = &led_status_amber;
- };
-
- chosen {
- bootargs-override = "console=ttyMSM0,115200n8";
- };
-
- leds {
- compatible = "gpio-leds";
-
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- /*
- * this is a bit misleading. Because there are about seven
- * multicolor LEDs connected all wired together in parallel.
- */
-
- status_yellow {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_YELLOW>;
- gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
- };
-
- led_status_amber: status_amber {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_AMBER>;
- gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
- };
-
- led_status_blue: status_blue {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
- };
-
- /*
- * LED is declared in vendors boardfile but it's not
- * working and the manual doesn't mention anything
- * about the LED being white.
-
- status_white {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
- };
- */
- };
-
- i2c-gpio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- compatible = "i2c-gpio";
- gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>, /* sda */
- <&qcom_pinmux 54 GPIO_ACTIVE_HIGH>; /* scl */
- i2c-gpio,delay-us = <5>;
- i2c-gpio,scl-output-only;
-
- mcu@50 {
- reg = <0x50>;
- compatible = "sonix,sn8f25e21";
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- pinctrl-0 = <&button_pins>;
- pinctrl-names = "default";
-
- ir-remote {
- label = "ir-remote";
- gpios = <&qcom_pinmux 15 GPIO_ACTIVE_LOW>;
- linux,code = <BTN_0>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- wps5g {
- label = "wps5g";
- gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- wps2g {
- label = "wps2g";
- gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- debounce-interval = <60>;
- wakeup-source;
- };
- };
-};
-
-&adm_dma {
- status = "okay";
-};
-
-&gmac1 {
- status = "okay";
-
- pinctrl-0 = <&rgmii2_pins>;
- pinctrl-names = "default";
-
- phy-mode = "rgmii";
- qcom,id = <1>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gmac2 {
- status = "okay";
-
- phy-mode = "sgmii";
- qcom,id = <2>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gsbi4_serial {
- pinctrl-0 = <&uart0_pins>;
- pinctrl-names = "default";
-};
-
-&mdio0 {
- status = "okay";
-
- pinctrl-0 = <&mdio0_pins>;
- pinctrl-names = "default";
-
- switch@10 {
- compatible = "qca,qca8337";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x10>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "cpu";
- ethernet = <&gmac1>;
- phy-mode = "rgmii";
- tx-internal-delay-ps = <1000>;
- rx-internal-delay-ps = <1000>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- port@1 {
- reg = <1>;
- label = "wan";
- phy-mode = "internal";
- phy-handle = <&phy_port1>;
- };
-
- port@2 {
- reg = <2>;
- label = "lan1";
- phy-mode = "internal";
- phy-handle = <&phy_port2>;
- };
-
- port@3 {
- reg = <3>;
- label = "lan2";
- phy-mode = "internal";
- phy-handle = <&phy_port3>;
- };
-
- port@4 {
- reg = <4>;
- label = "lan3";
- phy-mode = "internal";
- phy-handle = <&phy_port4>;
- };
-
- port@5 {
- reg = <5>;
- label = "lan4";
- phy-mode = "internal";
- phy-handle = <&phy_port5>;
- };
-
- port@6 {
- reg = <6>;
- label = "cpu";
- ethernet = <&gmac2>;
- phy-mode = "sgmii";
- qca,sgmii-enable-pll;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy_port1: phy@0 {
- reg = <0>;
- };
-
- phy_port2: phy@1 {
- reg = <1>;
- };
-
- phy_port3: phy@2 {
- reg = <2>;
- };
-
- phy_port4: phy@3 {
- reg = <3>;
- };
-
- phy_port5: phy@4 {
- reg = <4>;
- };
- };
- };
-};
-
-&nand {
- status = "okay";
-
- nand@0 {
- reg = <0>;
- compatible = "qcom,nandcs";
-
- nand-ecc-strength = <4>;
- nand-bus-width = <8>;
- nand-ecc-step-size = <512>;
-
- nand-is-boot-medium;
- qcom,boot-partitions = <0x0 0x1200000>;
-
- partitions {
- compatible = "qcom,smem-part";
- };
- };
-};
-
-&pcie0 {
- status = "okay";
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi5g: wifi@1,0 {
- reg = <0x00010000 0 0 0 0>;
- compatible = "qcom,ath10k";
- qcom,ath10k-calibration-variant = "ASRock-G10";
- };
- };
-};
-
-&pcie1 {
- status = "okay";
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi2g: wifi@1,0 {
- reg = <0x00010000 0 0 0 0>;
- compatible = "qcom,ath10k";
- qcom,ath10k-calibration-variant = "ASRock-G10";
- };
- };
-};
-
-&qcom_pinmux {
- led_pins: led_pins {
- mux {
- pins = "gpio7", "gpio8", "gpio9", "gpio26";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- button_pins: button_pins {
- mux {
- pins = "gpio15", "gpio16", "gpio64", "gpio65";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- uart0_pins: uart0_pins {
- mux {
- pins = "gpio10", "gpio11";
- function = "gsbi4";
- drive-strength = <10>;
- bias-disable;
- };
- };
-};
-
-&rpm {
- pinctrl-0 = <&i2c4_pins>;
- pinctrl-names = "default";
-};
-
-&hs_phy_0 {
- status = "okay";
-};
-
-&ss_phy_0 {
- status = "okay";
-};
-
-&usb3_0 {
- status = "okay";
-};
-
-&hs_phy_1 {
- status = "okay";
-};
-
-&ss_phy_1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-};
-
-&tcsr {
- qcom,usb-ctrl-select = <TCSR_USB_SELECT_USB3_DUAL>;
-};
-
-/delete-node/ &pcie2_pins;
-/delete-node/ &pcie2;
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2014 The ChromiumOS Authors
- */
-
-#include "qcom-ipq8064-smb208.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- aliases {
- ethernet0 = &gmac0;
- ethernet1 = &gmac2;
- mdio-gpio0 = &mdio;
- serial0 = &gsbi4_serial;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- rsvd@41200000 {
- reg = <0x41200000 0x300000>;
- no-map;
- };
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&button_pins>;
- pinctrl-names = "default";
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- dev {
- label = "dev";
- gpios = <&qcom_pinmux 15 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_CONFIG>;
- debounce-interval = <60>;
- wakeup-source;
- };
- };
-
- mdio: mdio {
- compatible = "virtual,mdio-gpio";
- #address-cells = <1>;
- #size-cells = <0>;
- gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>,
- <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
- pinctrl-0 = <&mdio_pins>;
- pinctrl-names = "default";
-
- switch@10 {
- compatible = "qca,qca8337";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x10>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "cpu";
- ethernet = <&gmac0>;
- phy-mode = "rgmii";
- tx-internal-delay-ps = <1000>;
- rx-internal-delay-ps = <1000>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- port@1 {
- reg = <1>;
- label = "lan1";
- phy-mode = "internal";
- phy-handle = <&phy_port1>;
- };
-
- port@2 {
- reg = <2>;
- label = "wan";
- phy-mode = "internal";
- phy-handle = <&phy_port2>;
- };
-
- port@6 {
- reg = <6>;
- label = "cpu";
- ethernet = <&gmac2>;
- phy-mode = "sgmii";
- qca,sgmii-enable-pll;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy_port1: phy@0 {
- reg = <0>;
- };
-
- phy_port2: phy@1 {
- reg = <1>;
- };
- };
- };
- };
-
- soc {
- rng@1a500000 {
- status = "disabled";
- };
-
- sound {
- compatible = "google,storm-audio";
- qcom,model = "ipq806x-storm";
- cpu = <&lpass>;
- codec = <&max98357a>;
- };
-
- lpass: lpass@28100000 {
- status = "okay";
- pinctrl-names = "default", "idle";
- pinctrl-0 = <&mi2s_default>;
- pinctrl-1 = <&mi2s_idle>;
- };
-
- max98357a: max98357a {
- compatible = "maxim,max98357a";
- #sound-dai-cells = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmode_pins>;
- sdmode-gpios = <&qcom_pinmux 25 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&qcom_pinmux {
- rgmii0_pins: rgmii0_pins {
- mux {
- pins = "gpio2", "gpio66";
- drive-strength = <8>;
- bias-disable;
- };
- };
- mi2s_pins {
- mi2s_default: mi2s_default {
- dout {
- pins = "gpio32";
- function = "mi2s";
- drive-strength = <16>;
- bias-disable;
- };
- sync {
- pins = "gpio27";
- function = "mi2s";
- drive-strength = <16>;
- bias-disable;
- };
- clk {
- pins = "gpio28";
- function = "mi2s";
- drive-strength = <16>;
- bias-disable;
- };
- };
- mi2s_idle: mi2s_idle {
- dout {
- pins = "gpio32";
- function = "mi2s";
- drive-strength = <2>;
- bias-pull-down;
- };
- sync {
- pins = "gpio27";
- function = "mi2s";
- drive-strength = <2>;
- bias-pull-down;
- };
- clk {
- pins = "gpio28";
- function = "mi2s";
- drive-strength = <2>;
- bias-pull-down;
- };
- };
- };
-
- mdio_pins: mdio_pins {
- mux {
- pins = "gpio0", "gpio1";
- function = "gpio";
- drive-strength = <8>;
- bias-disable;
- };
- rst {
- pins = "gpio26";
- output-low;
- };
- };
-
- sdmode_pins: sdmode_pinmux {
- pins = "gpio25";
- function = "gpio";
- drive-strength = <16>;
- bias-disable;
- };
-
- sdcc1_pins: sdcc1_pinmux {
- mux {
- pins = "gpio38", "gpio39", "gpio40",
- "gpio41", "gpio42", "gpio43",
- "gpio44", "gpio45", "gpio46",
- "gpio47";
- function = "sdc1";
- };
- cmd {
- pins = "gpio45";
- drive-strength = <10>;
- bias-pull-up;
- };
- data {
- pins = "gpio38", "gpio39", "gpio40",
- "gpio41", "gpio43", "gpio44",
- "gpio46", "gpio47";
- drive-strength = <10>;
- bias-pull-up;
- };
- clk {
- pins = "gpio42";
- drive-strength = <16>;
- bias-pull-down;
- };
- };
-
- i2c1_pins: i2c1_pinmux {
- pins = "gpio53", "gpio54";
- function = "gsbi1";
- bias-disable;
- };
-
- rpm_i2c_pinmux: rpm_i2c_pinmux {
- mux {
- pins = "gpio12", "gpio13";
- function = "gsbi4";
- drive-strength = <12>;
- bias-disable;
- };
- };
-
- spi_pins: spi_pins {
- mux {
- pins = "gpio18", "gpio19", "gpio21";
- function = "gsbi5";
- bias-pull-down;
- /delete-property/ bias-none;
- /delete-property/ drive-strength;
- };
- data {
- pins = "gpio18", "gpio19";
- drive-strength = <10>;
- };
- cs {
- pins = "gpio20";
- drive-strength = <10>;
- bias-pull-up;
- };
- clk {
- pins = "gpio21";
- drive-strength = <12>;
- };
- };
-
- fw_pinmux {
- wp {
- pins = "gpio17";
- output-low;
- };
- };
-
- button_pins: button_pins {
- recovery {
- pins = "gpio16";
- function = "gpio";
- bias-none;
- };
- developer {
- pins = "gpio15";
- function = "gpio";
- bias-none;
- };
- };
-
- spi6_pins: spi6_pins {
- mux {
- pins = "gpio55", "gpio56", "gpio58";
- function = "gsbi6";
- bias-pull-down;
- };
- data {
- pins = "gpio55", "gpio56";
- drive-strength = <10>;
- };
- cs {
- pins = "gpio57";
- drive-strength = <10>;
- bias-pull-up;
- output-high;
- };
- clk {
- pins = "gpio58";
- drive-strength = <12>;
- };
- };
-};
-
-&adm_dma {
- status = "okay";
-};
-
-&gmac0 {
- status = "okay";
- phy-mode = "rgmii";
- qcom,id = <0>;
-
- pinctrl-0 = <&rgmii0_pins>;
- pinctrl-names = "default";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gmac2 {
- status = "okay";
- phy-mode = "sgmii";
- qcom,id = <2>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gsbi1 {
- status = "okay";
- qcom,mode = <GSBI_PROT_I2C_UART>;
-};
-
-&gsbi1_i2c {
- status = "okay";
-
- clock-frequency = <100000>;
-
- pinctrl-0 = <&i2c1_pins>;
- pinctrl-names = "default";
-
- tpm@20 {
- compatible = "infineon,slb9645tt";
- reg = <0x20>;
- powered-while-suspended;
- };
-};
-
-&gsbi4 {
- status = "okay";
- qcom,mode = <GSBI_PROT_I2C_UART>;
-};
-
-&gsbi4_serial {
- status = "okay";
-};
-
-&gsbi5 {
- status = "okay";
- qcom,mode = <GSBI_PROT_SPI>;
-
- spi4: spi@1a280000 {
- status = "okay";
- spi-max-frequency = <50000000>;
- pinctrl-0 = <&spi_pins>;
- pinctrl-names = "default";
-
- cs-gpios = <&qcom_pinmux 20 0>;
-
- flash: flash@0 {
- compatible = "jedec,spi-nor";
- spi-max-frequency = <50000000>;
- reg = <0>;
- };
- };
-};
-
-&gsbi6 {
- status = "okay";
- qcom,mode = <GSBI_PROT_SPI>;
-};
-
-&gsbi6_spi {
- status = "okay";
- spi-max-frequency = <25000000>;
-
- pinctrl-0 = <&spi6_pins>;
- pinctrl-names = "default";
-
- cs-gpios = <&qcom_pinmux 57 GPIO_ACTIVE_HIGH>;
-
- dmas = <&adm_dma 8 0xb>,
- <&adm_dma 7 0x14>;
- dma-names = "rx", "tx";
-
- /*
- * This "spidev" was included in the manufacturer device tree. I suspect
- * it's the (unused) Zigbee radio -- SiliconLabs EM3581 Zigbee? There's
- * no driver or binding for this at the moment.
- */
- spidev@0 {
- compatible = "spidev";
- reg = <0>;
- spi-max-frequency = <25000000>;
- };
-};
-
-&pcie0 {
- status = "okay";
-
- pcie@0 {
- reg = <0 0 0 0 0>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- device_type = "pci";
- interrupt-controller;
-
- ath10k@0,0 {
- reg = <0 0 0 0 0>;
- device_type = "pci";
- qcom,ath10k-sa-gpio = <2 3 4 0>;
- qcom,ath10k-sa-gpio-func = <5 5 5 0>;
- };
- };
-};
-
-&pcie1 {
- status = "okay";
-
- pcie@0 {
- reg = <0 0 0 0 0>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- device_type = "pci";
- interrupt-controller;
-
- ath10k@0,0 {
- reg = <0 0 0 0 0>;
- device_type = "pci";
- qcom,ath10k-sa-gpio = <2 3 4 0>;
- qcom,ath10k-sa-gpio-func = <5 5 5 0>;
- };
- };
-};
-
-&pcie2 {
- status = "okay";
-
- pcie@0 {
- reg = <0 0 0 0 0>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- device_type = "pci";
- interrupt-controller;
-
- ath10k@0,0 {
- reg = <0 0 0 0 0>;
- device_type = "pci";
- };
- };
-};
-
-&rpm {
- pinctrl-0 = <&rpm_i2c_pinmux>;
- pinctrl-names = "default";
-};
-
-&sdcc1 {
- status = "okay";
- pinctrl-0 = <&sdcc1_pins>;
- pinctrl-names = "default";
- /delete-property/ mmc-ddr-1_8v;
-};
-
-&tcsr {
- compatible = "qcom,tcsr-ipq8064", "qcom,tcsr", "syscon";
- qcom,usb-ctrl-select = <TCSR_USB_SELECT_USB3_DUAL>;
-};
-
-&hs_phy_0 {
- status = "okay";
-};
-
-&ss_phy_0 {
- status = "okay";
-};
-
-&usb3_0 {
- status = "okay";
-};
-
-&hs_phy_1 {
- status = "okay";
-};
-
-&ss_phy_1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-};
+++ /dev/null
-#include "qcom-ipq8064-v1.0.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "Netgear Nighthawk X4 R7500";
- compatible = "netgear,r7500", "qcom,ipq8064";
-
- memory@0 {
- reg = <0x42000000 0xe000000>;
- device_type = "memory";
- };
-
- reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- rsvd@41200000 {
- reg = <0x41200000 0x300000>;
- no-map;
- };
- };
-
- aliases {
- mdio-gpio0 = &mdio0;
-
- led-boot = &power_white;
- led-failsafe = &power_amber;
- led-running = &power_white;
- led-upgrade = &power_amber;
- };
-
- chosen {
- bootargs = "rootfstype=squashfs noinitrd";
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&button_pins>;
- pinctrl-names = "default";
-
- wifi {
- label = "wifi";
- gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RFKILL>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- wps {
- label = "wps";
- gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- debounce-interval = <60>;
- wakeup-source;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- usb1 {
- label = "white:usb1";
- gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
- };
-
- usb2 {
- label = "white:usb2";
- gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
- };
-
- power_amber: power_amber {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_AMBER>;
- gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
- };
-
- wan_white {
- function = LED_FUNCTION_WAN;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
- };
-
- wan_amber {
- function = LED_FUNCTION_WAN;
- color = <LED_COLOR_ID_AMBER>;
- gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
- };
-
- wps {
- function = LED_FUNCTION_WPS;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
- };
-
- esata {
- label = "white:esata";
- gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
- };
-
- power_white: power_white {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
- default-state = "keep";
- };
-
- wifi {
- label = "white:wifi";
- gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&qcom_pinmux {
- button_pins: button_pins {
- mux {
- pins = "gpio6", "gpio54", "gpio65";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- led_pins: led_pins {
- mux {
- pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23",
- "gpio24","gpio26", "gpio53", "gpio64";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-};
-
-&gsbi5 {
- status = "disabled";
-
- spi@1a280000 {
- status = "disabled";
- };
-};
-
-&hs_phy_0 {
- status = "okay";
-};
-
-&ss_phy_0 {
- status = "okay";
-};
-
-&usb3_0 {
- status = "okay";
-};
-
-&hs_phy_1 {
- status = "okay";
-};
-
-&ss_phy_1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
-};
-
-&pcie1 {
- status = "okay";
- max-link-speed = <1>;
-};
-
-&nand {
- status = "okay";
-
- nand@0 {
- reg = <0>;
- compatible = "qcom,nandcs";
-
- nand-ecc-strength = <4>;
- nand-bus-width = <8>;
- nand-ecc-step-size = <512>;
-
- nand-is-boot-medium;
- qcom,boot-partitions = <0x0 0x1180000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- qcadata@0 {
- label = "qcadata";
- reg = <0x0000000 0x0c80000>;
- read-only;
- };
-
- APPSBL@c80000 {
- label = "APPSBL";
- reg = <0x0c80000 0x0500000>;
- read-only;
- };
-
- APPSBLENV@1180000 {
- label = "APPSBLENV";
- reg = <0x1180000 0x0080000>;
- read-only;
- };
-
- art: art@1200000 {
- label = "art";
- reg = <0x1200000 0x0140000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_art_0: macaddr@0 {
- reg = <0x0 0x6>;
- };
-
- macaddr_art_6: macaddr@6 {
- reg = <0x6 0x6>;
- };
- };
- };
-
- kernel@1340000 {
- label = "kernel";
- reg = <0x1340000 0x0400000>;
- };
-
- ubi@1740000 {
- label = "ubi";
- reg = <0x1740000 0x1600000>;
- };
-
- netgear@2d40000 {
- label = "netgear";
- reg = <0x2d40000 0x0c00000>;
- read-only;
- };
-
- reserve@3940000 {
- label = "reserve";
- reg = <0x3940000 0x46c0000>;
- read-only;
- };
- };
- };
-};
-
-&mdio0 {
- status = "okay";
-
- pinctrl-0 = <&mdio0_pins>;
- pinctrl-names = "default";
-
- switch@10 {
- compatible = "qca,qca8337";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x10>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "cpu";
- ethernet = <&gmac1>;
- phy-mode = "rgmii";
- tx-internal-delay-ps = <1000>;
- rx-internal-delay-ps = <1000>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- port@1 {
- reg = <1>;
- label = "lan1";
- phy-mode = "internal";
- phy-handle = <&phy_port1>;
- };
-
- port@2 {
- reg = <2>;
- label = "lan2";
- phy-mode = "internal";
- phy-handle = <&phy_port2>;
- };
-
- port@3 {
- reg = <3>;
- label = "lan3";
- phy-mode = "internal";
- phy-handle = <&phy_port3>;
- };
-
- port@4 {
- reg = <4>;
- label = "lan4";
- phy-mode = "internal";
- phy-handle = <&phy_port4>;
- };
-
- port@5 {
- reg = <5>;
- label = "wan";
- phy-mode = "internal";
- phy-handle = <&phy_port5>;
- };
-
- port@6 {
- reg = <6>;
- label = "cpu";
- ethernet = <&gmac2>;
- phy-mode = "sgmii";
- qca,sgmii-enable-pll;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy_port1: phy@0 {
- reg = <0>;
- };
-
- phy_port2: phy@1 {
- reg = <1>;
- };
-
- phy_port3: phy@2 {
- reg = <2>;
- };
-
- phy_port4: phy@3 {
- reg = <3>;
- };
-
- phy_port5: phy@4 {
- reg = <4>;
- };
- };
- };
-};
-
-&gmac1 {
- status = "okay";
- phy-mode = "rgmii";
- qcom,id = <1>;
-
- pinctrl-0 = <&rgmii2_pins>;
- pinctrl-names = "default";
-
- nvmem-cells = <&macaddr_art_6>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gmac2 {
- status = "okay";
- phy-mode = "sgmii";
- qcom,id = <2>;
-
- nvmem-cells = <&macaddr_art_0>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&tcsr {
- qcom,usb-ctrl-select = <TCSR_USB_SELECT_USB3_DUAL>;
- compatible = "qcom,tcsr";
-};
-
-&adm_dma {
- status = "okay";
-};
+++ /dev/null
-#include "qcom-ipq8064-v2.0-smb208.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "Netgear Nighthawk X4 R7500v2";
- compatible = "netgear,r7500v2", "qcom,ipq8064";
-
- memory@0 {
- reg = <0x42000000 0x1e000000>;
- device_type = "memory";
- };
-
- reserved-memory {
- rsvd@5fe00000 {
- reg = <0x5fe00000 0x200000>;
- reusable;
- };
- };
-
- aliases {
- mdio-gpio0 = &mdio0;
-
- led-boot = &power;
- led-failsafe = &power;
- led-running = &power;
- led-upgrade = &power;
- };
-
- chosen {
- bootargs = "rootfstype=squashfs noinitrd";
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&button_pins>;
- pinctrl-names = "default";
-
- wifi {
- label = "wifi";
- gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RFKILL>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- wps {
- label = "wps";
- gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- debounce-interval = <60>;
- wakeup-source;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- usb1 {
- label = "amber:usb1";
- gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
- };
-
- usb3 {
- label = "amber:usb3";
- gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
- };
-
- status {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_AMBER>;
- gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
- };
-
- internet {
- label = "white:internet";
- gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
- };
-
- wan {
- function = LED_FUNCTION_WAN;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
- };
-
- wps {
- function = LED_FUNCTION_WPS;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
- };
-
- esata {
- label = "white:esata";
- gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
- };
-
- power: power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
- default-state = "keep";
- };
-
- wifi {
- label = "white:wifi";
- gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&adm_dma {
- status = "okay";
-};
-
-&qcom_pinmux {
- button_pins: button_pins {
- mux {
- pins = "gpio6", "gpio54", "gpio65";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- led_pins: led_pins {
- mux {
- pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23",
- "gpio24","gpio26", "gpio53", "gpio64";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- usb0_pwr_en_pins: usb0_pwr_en_pins {
- mux {
- pins = "gpio15";
- function = "gpio";
- drive-strength = <12>;
- bias-pull-down;
- output-high;
- };
- };
-
- usb1_pwr_en_pins: usb1_pwr_en_pins {
- mux {
- pins = "gpio16", "gpio68";
- function = "gpio";
- drive-strength = <12>;
- bias-pull-down;
- output-high;
- };
- };
-};
-
-&sata_phy {
- status = "okay";
-};
-
-&sata {
- status = "okay";
-};
-
-&hs_phy_0 {
- status = "okay";
-};
-
-&ss_phy_0 {
- status = "okay";
-};
-
-&usb3_0 {
- status = "okay";
-
- pinctrl-0 = <&usb0_pwr_en_pins>;
- pinctrl-names = "default";
-};
-
-&hs_phy_1 {
- status = "okay";
-};
-
-&ss_phy_1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-
- pinctrl-0 = <&usb1_pwr_en_pins>;
- pinctrl-names = "default";
-};
-
-&pcie0 {
- status = "okay";
- reset-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
- pinctrl-0 = <&pcie0_pins>;
- pinctrl-names = "default";
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- compatible = "pci168c,0040";
- reg = <0x00010000 0 0 0 0>;
-
- nvmem-cells = <&macaddr_art_6 1>, <&precal_art_1000>;
- nvmem-cell-names = "mac-address", "pre-calibration";
- };
- };
-};
-
-&pcie1 {
- status = "okay";
- reset-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
- pinctrl-0 = <&pcie1_pins>;
- pinctrl-names = "default";
- max-link-speed = <1>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- compatible = "pci168c,0040";
- reg = <0x00010000 0 0 0 0>;
-
- nvmem-cells = <&macaddr_art_6 2>, <&precal_art_5000>;
- nvmem-cell-names = "mac-address", "pre-calibration";
- };
- };
-};
-
-&nand {
- status = "okay";
-
- nand@0 {
- reg = <0>;
- compatible = "qcom,nandcs";
-
- nand-ecc-strength = <4>;
- nand-bus-width = <8>;
- nand-ecc-step-size = <512>;
-
- nand-is-boot-medium;
- qcom,boot-partitions = <0x0 0x1180000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- qcadata@0 {
- label = "qcadata";
- reg = <0x0000000 0x0c80000>;
- read-only;
- };
-
- APPSBL@c80000 {
- label = "APPSBL";
- reg = <0x0c80000 0x0500000>;
- read-only;
- };
-
- APPSBLENV@1180000 {
- label = "APPSBLENV";
- reg = <0x1180000 0x0080000>;
- read-only;
- };
-
- art@1200000 {
- label = "art";
- reg = <0x1200000 0x0140000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_art_0: macaddr@0 {
- reg = <0x0 0x6>;
- };
-
- macaddr_art_6: macaddr@6 {
- compatible = "mac-base";
- reg = <0x6 0x6>;
- #nvmem-cell-cells = <1>;
- };
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- artbak: art@1340000 {
- label = "artbak";
- reg = <0x1340000 0x0140000>;
- read-only;
- };
-
- kernel@1480000 {
- label = "kernel";
- reg = <0x1480000 0x0400000>;
- };
-
- ubi@1880000 {
- label = "ubi";
- reg = <0x1880000 0x6080000>;
- };
-
- reserve@7900000 {
- label = "reserve";
- reg = <0x7900000 0x0700000>;
- read-only;
- };
- };
- };
-};
-
-&mdio0 {
- status = "okay";
-
- pinctrl-0 = <&mdio0_pins>;
- pinctrl-names = "default";
-
- switch@10 {
- compatible = "qca,qca8337";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x10>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "cpu";
- ethernet = <&gmac1>;
- phy-mode = "rgmii";
- tx-internal-delay-ps = <1000>;
- rx-internal-delay-ps = <1000>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- port@1 {
- reg = <1>;
- label = "lan1";
- phy-mode = "internal";
- phy-handle = <&phy_port1>;
- };
-
- port@2 {
- reg = <2>;
- label = "lan2";
- phy-mode = "internal";
- phy-handle = <&phy_port2>;
- };
-
- port@3 {
- reg = <3>;
- label = "lan3";
- phy-mode = "internal";
- phy-handle = <&phy_port3>;
- };
-
- port@4 {
- reg = <4>;
- label = "lan4";
- phy-mode = "internal";
- phy-handle = <&phy_port4>;
- };
-
- port@5 {
- reg = <5>;
- label = "wan";
- phy-mode = "internal";
- phy-handle = <&phy_port5>;
- };
-
- port@6 {
- reg = <6>;
- label = "cpu";
- ethernet = <&gmac2>;
- phy-mode = "sgmii";
- qca,sgmii-enable-pll;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy_port1: phy@0 {
- reg = <0>;
- };
-
- phy_port2: phy@1 {
- reg = <1>;
- };
-
- phy_port3: phy@2 {
- reg = <2>;
- };
-
- phy_port4: phy@3 {
- reg = <3>;
- };
-
- phy_port5: phy@4 {
- reg = <4>;
- };
- };
- };
-};
-
-&gmac1 {
- status = "okay";
- phy-mode = "rgmii";
- qcom,id = <1>;
-
- pinctrl-0 = <&rgmii2_pins>;
- pinctrl-names = "default";
-
- nvmem-cells = <&macaddr_art_6 0>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gmac2 {
- status = "okay";
- phy-mode = "sgmii";
- qcom,id = <2>;
-
- nvmem-cells = <&macaddr_art_0>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2014 The ChromiumOS Authors
- */
-
-#include "qcom-ipq8064-onhub.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,gsbi.h>
-
-/ {
- model = "TP-Link OnHub";
- compatible = "tplink,onhub", "google,whirlwind-sp5", "qcom,ipq8064";
-};
-
-&qcom_pinmux {
- i2c7_pins: i2c7_pinmux {
- mux {
- pins = "gpio8", "gpio9";
- function = "gsbi7";
- };
- data {
- pins = "gpio8";
- bias-disable;
- };
- clk {
- pins = "gpio9";
- bias-disable;
- };
- };
-};
-
-&gsbi7 {
- status = "okay";
- qcom,mode = <GSBI_PROT_I2C_UART>;
-};
-
-&gsbi7_i2c {
- status = "okay";
- clock-frequency = <100000>;
- pinctrl-0 = <&i2c7_pins>;
- pinctrl-names = "default";
-
- led-controller@32 {
- compatible = "national,lp5523";
- reg = <0x32>;
- clock-mode = /bits/ 8 <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- led@0 {
- reg = <0>;
- color = <LED_COLOR_ID_RED>;
- chan-name = "red:status-0";
- linux,default-trigger = "default-on";
- led-cur = /bits/ 8 <0x64>;
- max-cur = /bits/ 8 <0x78>;
- };
-
- led@1 {
- reg = <1>;
- color = <LED_COLOR_ID_GREEN>;
- chan-name = "green:status-0";
- led-cur = /bits/ 8 <0x64>;
- max-cur = /bits/ 8 <0x78>;
- };
-
- led@2 {
- reg = <2>;
- color = <LED_COLOR_ID_BLUE>;
- chan-name = "blue:status-0";
- led-cur = /bits/ 8 <0x64>;
- max-cur = /bits/ 8 <0x78>;
- };
-
- led@3 {
- reg = <3>;
- color = <LED_COLOR_ID_RED>;
- chan-name = "red:status-1";
- led-cur = /bits/ 8 <0x64>;
- max-cur = /bits/ 8 <0x78>;
- };
-
- led@4 {
- reg = <4>;
- color = <LED_COLOR_ID_GREEN>;
- chan-name = "green:status-1";
- linux,default-trigger = "default-on";
- led-cur = /bits/ 8 <0x64>;
- max-cur = /bits/ 8 <0x78>;
- };
-
- led@5 {
- reg = <5>;
- color = <LED_COLOR_ID_BLUE>;
- chan-name = "blue:status-1";
- led-cur = /bits/ 8 <0x64>;
- max-cur = /bits/ 8 <0x78>;
- };
-
- led@6 {
- reg = <6>;
- color = <LED_COLOR_ID_RED>;
- chan-name = "red:status-2";
- led-cur = /bits/ 8 <0x64>;
- max-cur = /bits/ 8 <0x78>;
- };
-
- led@7 {
- reg = <7>;
- color = <LED_COLOR_ID_GREEN>;
- chan-name = "green:status-2";
- led-cur = /bits/ 8 <0x64>;
- max-cur = /bits/ 8 <0x78>;
- };
-
- led@8 {
- reg = <8>;
- color = <LED_COLOR_ID_BLUE>;
- chan-name = "blue:status-2";
- linux,default-trigger = "default-on";
- led-cur = /bits/ 8 <0x64>;
- max-cur = /bits/ 8 <0x78>;
- };
- };
-
- led-controller@33 {
- compatible = "national,lp5523";
- reg = <0x33>;
- clock-mode = /bits/ 8 <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- led@0 {
- reg = <0>;
- color = <LED_COLOR_ID_RED>;
- chan-name = "red:status-3";
- linux,default-trigger = "default-on";
- led-cur = /bits/ 8 <0x64>;
- max-cur = /bits/ 8 <0x78>;
- };
-
- led@1 {
- reg = <1>;
- color = <LED_COLOR_ID_GREEN>;
- chan-name = "green:status-3";
- led-cur = /bits/ 8 <0x64>;
- max-cur = /bits/ 8 <0x78>;
- };
-
- led@2 {
- reg = <2>;
- color = <LED_COLOR_ID_BLUE>;
- chan-name = "blue:status-3";
- led-cur = /bits/ 8 <0x64>;
- max-cur = /bits/ 8 <0x78>;
- };
-
- led@3 {
- reg = <3>;
- color = <LED_COLOR_ID_RED>;
- chan-name = "red:status-4";
- led-cur = /bits/ 8 <0x64>;
- max-cur = /bits/ 8 <0x78>;
- };
-
- led@4 {
- reg = <4>;
- color = <LED_COLOR_ID_GREEN>;
- chan-name = "green:status-4";
- linux,default-trigger = "default-on";
- led-cur = /bits/ 8 <0x64>;
- max-cur = /bits/ 8 <0x78>;
- };
-
- led@5 {
- reg = <5>;
- color = <LED_COLOR_ID_BLUE>;
- chan-name = "blue:status-4";
- led-cur = /bits/ 8 <0x64>;
- max-cur = /bits/ 8 <0x78>;
- };
-
- led@6 {
- reg = <6>;
- color = <LED_COLOR_ID_RED>;
- chan-name = "red:status-5";
- led-cur = /bits/ 8 <0x64>;
- max-cur = /bits/ 8 <0x78>;
- };
-
- led@7 {
- reg = <7>;
- color = <LED_COLOR_ID_GREEN>;
- chan-name = "green:status-5";
- led-cur = /bits/ 8 <0x64>;
- max-cur = /bits/ 8 <0x78>;
- };
-
- led@8 {
- reg = <8>;
- color = <LED_COLOR_ID_BLUE>;
- chan-name = "blue:status-5";
- linux,default-trigger = "default-on";
- led-cur = /bits/ 8 <0x64>;
- max-cur = /bits/ 8 <0x78>;
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq8064-v2.0-smb208.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/ {
- model = "Ubiquiti UniFi AC HD";
- compatible = "ubnt,unifi-ac-hd", "qcom,ipq8064";
-
- aliases {
- label-mac-device = &gmac2;
- led-boot = &led_dome_white;
- led-failsafe = &led_dome_white;
- led-running = &led_dome_blue;
- led-upgrade = &led_dome_blue;
- mdio-gpio0 = &mdio0;
- ethernet0 = &gmac2;
- ethernet1 = &gmac1;
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- led_dome_blue: dome_blue {
- label = "blue:dome";
- gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
- };
-
- led_dome_white: dome_white {
- label = "white:dome";
- gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
- };
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&button_pins>;
- pinctrl-names = "default";
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- debounce-interval = <60>;
- wakeup-source;
- };
- };
-};
-
-&qcom_pinmux {
- button_pins: button_pins {
- mux {
- pins = "gpio68";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- led_pins: led_pins {
- mux {
- pins = "gpio9", "gpio53";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-down;
- output-low;
- };
- };
-
- spi_pins: spi_pins {
- mux {
- pins = "gpio18", "gpio19", "gpio21";
- function = "gsbi5";
- drive-strength = <10>;
- bias-none;
- };
-
- cs {
- pins = "gpio20";
- drive-strength = <12>;
- };
- };
-};
-
-&CPU_SPC {
- status = "disabled";
-};
-
-&gsbi5 {
- status = "okay";
-
- qcom,mode = <GSBI_PROT_SPI>;
-
- spi@1a280000 {
- status = "okay";
-
- pinctrl-0 = <&spi_pins>;
- pinctrl-names = "default";
- cs-gpios = <&qcom_pinmux 20 0>;
-
- flash@0 {
- compatible = "mx25u25635f", "jedec,spi-nor";
- #address-cells = <1>;
- #size-cells = <1>;
- spi-max-frequency = <50000000>;
- reg = <0>;
- m25p,fast-read;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SBL1";
- reg = <0x0 0x20000>;
- read-only;
- };
-
- partition@20000 {
- label = "MIBIB";
- reg = <0x20000 0x10000>;
- read-only;
- };
-
- partition@30000 {
- label = "SBL2";
- reg = <0x30000 0x20000>;
- read-only;
- };
-
- partition@50000 {
- label = "SBL3";
- reg = <0x50000 0x30000>;
- read-only;
- };
-
- partition@80000 {
- label = "DDRCONFIG";
- reg = <0x80000 0x10000>;
- read-only;
- };
-
- partition@90000 {
- label = "SSD";
- reg = <0x90000 0x10000>;
- read-only;
- };
-
- partition@a0000 {
- label = "TZ";
- reg = <0xa0000 0x30000>;
- read-only;
- };
-
- partition@d0000 {
- label = "RPM";
- reg = <0xd0000 0x20000>;
- read-only;
- };
-
- partition@f0000 {
- label = "APPSBL";
- reg = <0xf0000 0xc0000>;
- read-only;
- };
-
- partition@1b0000 {
- label = "APPSBLENV";
- reg = <0x1b0000 0x10000>;
- read-only;
- };
-
- eeprom: partition@1c0000 {
- label = "EEPROM";
- reg = <0x1c0000 0x10000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_eeprom_0: macaddr@0 {
- reg = <0x0 0x6>;
- };
-
- macaddr_eeprom_6: macaddr@6 {
- reg = <0x6 0x6>;
- };
- };
- };
-
- partition@1d0000 {
- label = "bootselect";
- reg = <0x1d0000 0x10000>;
- };
-
- partition@1e0000 {
- compatible = "denx,fit";
- label = "firmware";
- reg = <0x1e0000 0xe70000>;
- };
-
- partition@1050000 {
- label = "kernel1";
- reg = <0x1050000 0xe70000>;
- read-only;
- };
-
- partition@1ec0000 {
- label = "debug";
- reg = <0x1ec0000 0x100000>;
- read-only;
- };
-
- partition@1fc0000 {
- label = "cfg";
- reg = <0x1fc0000 0x40000>;
- read-only;
- };
- };
- };
- };
-};
-
-&adm_dma {
- status = "okay";
-};
-
-&nand {
- status = "okay";
-
- nand-ecc-strength = <4>;
- nand-bus-width = <8>;
-};
-
-&mdio0 {
- status = "okay";
-
- pinctrl-0 = <&mdio0_pins>;
- pinctrl-names = "default";
-
- phy4: ethernet-phy@4 {
- reg = <4>;
- };
-
- phy5: ethernet-phy@5 {
- reg = <5>;
- };
-};
-
-&gmac1 {
- status = "okay";
-
- mdiobus = <&mdio0>;
- phy-handle = <&phy5>;
- phy-mode = "sgmii";
- qcom,id = <1>;
-
- nvmem-cells = <&macaddr_eeprom_6>;
- nvmem-cell-names = "mac-address";
-};
-
-&gmac2 {
- status = "okay";
-
- mdiobus = <&mdio0>;
- phy-handle = <&phy4>;
- phy-mode = "sgmii";
- qcom,id = <2>;
-
- nvmem-cells = <&macaddr_eeprom_0>;
- nvmem-cell-names = "mac-address";
-};
-
-&pcie0 {
- status = "okay";
-};
-
-&pcie1 {
- status = "okay";
-};
-
-&tcsr {
- status = "okay";
-};
-
-&hs_phy_0 {
- status = "okay";
-};
-
-&ss_phy_0 {
- status = "okay";
-};
-
-&usb3_0 {
- status = "okay";
-};
-
-&hs_phy_1 {
- status = "okay";
-};
-
-&ss_phy_1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-};
+++ /dev/null
-#include "qcom-ipq8064-v2.0-smb208.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "TP-Link Archer VR2600v";
- compatible = "tplink,vr2600v", "qcom,ipq8064";
-
- memory@0 {
- reg = <0x42000000 0x1e000000>;
- device_type = "memory";
- };
-
- aliases {
- mdio-gpio0 = &mdio0;
-
- led-boot = &power;
- led-failsafe = &general;
- led-running = &power;
- led-upgrade = &general;
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&button_pins>;
- pinctrl-names = "default";
-
- wifi {
- label = "wifi";
- gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RFKILL>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- wps {
- label = "wps";
- gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- dect {
- label = "dect";
- gpios = <&qcom_pinmux 67 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_PHONE>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- ledswitch {
- label = "ledswitch";
- gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_LIGHTS_TOGGLE>;
- debounce-interval = <60>;
- wakeup-source;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- dsl {
- label = "white:dsl";
- gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
- };
-
- usb {
- function = LED_FUNCTION_USB;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
- };
-
- lan {
- function = LED_FUNCTION_LAN;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
- };
-
- wlan2g {
- label = "white:wlan2g";
- gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>;
- };
-
- wlan5g {
- label = "white:wlan5g";
- gpios = <&qcom_pinmux 17 GPIO_ACTIVE_HIGH>;
- };
-
- power: power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
- default-state = "keep";
- };
-
- phone {
- label = "white:phone";
- gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
- };
-
- wan {
- function = LED_FUNCTION_WAN;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>;
- };
-
- general: general {
- label = "white:general";
- gpios = <&qcom_pinmux 66 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&qcom_pinmux {
- led_pins: led_pins {
- mux {
- pins = "gpio7", "gpio8", "gpio9", "gpio16", "gpio17",
- "gpio26", "gpio53", "gpio56", "gpio66";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- button_pins: button_pins {
- mux {
- pins = "gpio54", "gpio64", "gpio65", "gpio67", "gpio68";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- spi_pins: spi_pins {
- mux {
- pins = "gpio18", "gpio19", "gpio21";
- function = "gsbi5";
- bias-pull-down;
- };
-
- data {
- pins = "gpio18", "gpio19";
- drive-strength = <10>;
- };
-
- cs {
- pins = "gpio20";
- drive-strength = <10>;
- bias-pull-up;
- };
-
- clk {
- pins = "gpio21";
- drive-strength = <12>;
- };
- };
-};
-
-&gsbi5 {
- qcom,mode = <GSBI_PROT_SPI>;
- status = "okay";
-
- spi4: spi@1a280000 {
- status = "okay";
-
- pinctrl-0 = <&spi_pins>;
- pinctrl-names = "default";
-
- cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- #address-cells = <1>;
- #size-cells = <1>;
- spi-max-frequency = <50000000>;
- reg = <0>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "SBL1";
- reg = <0x0 0x20000>;
- read-only;
- };
-
- partition@20000 {
- label = "MIBIB";
- reg = <0x20000 0x20000>;
- read-only;
- };
-
- partition@40000 {
- label = "SBL2";
- reg = <0x40000 0x40000>;
- read-only;
- };
-
- partition@80000 {
- label = "SBL3";
- reg = <0x80000 0x80000>;
- read-only;
- };
-
- partition@100000 {
- label = "DDRCONFIG";
- reg = <0x100000 0x10000>;
- read-only;
- };
-
- partition@110000 {
- label = "SSD";
- reg = <0x110000 0x10000>;
- read-only;
- };
-
- partition@120000 {
- label = "TZ";
- reg = <0x120000 0x80000>;
- read-only;
- };
-
- partition@1a0000 {
- label = "RPM";
- reg = <0x1a0000 0x80000>;
- read-only;
- };
-
- partition@220000 {
- label = "APPSBL";
- reg = <0x220000 0x80000>;
- read-only;
- };
-
- partition@2a0000 {
- label = "APPSBLENV";
- reg = <0x2a0000 0x40000>;
- read-only;
- };
-
- partition@2e0000 {
- label = "OLDART";
- reg = <0x2e0000 0x40000>;
- read-only;
- };
-
- partition@320000 {
- label = "firmware";
- reg = <0x320000 0xc60000>;
- compatible = "openwrt,uimage";
- openwrt,offset = <512>; /* account for pad-extra 512 */
- };
-
- /* hole 0xf80000 - 0xfaf100 */
-
- partition@faf100 {
- label = "default-mac";
- reg = <0xfaf100 0x00200>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_defaultmac_0: macaddr@0 {
- compatible = "mac-base";
- reg = <0x0 0x6>;
- #nvmem-cell-cells = <1>;
- };
- };
- };
-
- partition@fc0000 {
- label = "ART";
- reg = <0xfc0000 0x40000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_ART_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_ART_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
- };
- };
- };
-};
-
-&hs_phy_0 {
- status = "okay";
-};
-
-&ss_phy_0 {
- status = "okay";
-};
-
-&usb3_0 {
- status = "okay";
-};
-
-&hs_phy_1 {
- status = "okay";
-};
-
-&ss_phy_1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- compatible = "pci168c,0040";
- reg = <0x00010000 0 0 0 0>;
-
- nvmem-cells = <&macaddr_defaultmac_0 (-1)>, <&precal_ART_1000>;
- nvmem-cell-names = "mac-address", "pre-calibration";
- };
- };
-};
-
-&pcie1 {
- status = "okay";
- max-link-speed = <1>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- compatible = "pci168c,0040";
- reg = <0x00010000 0 0 0 0>;
-
- nvmem-cells = <&macaddr_defaultmac_0 0>, <&precal_ART_5000>;
- nvmem-cell-names = "mac-address", "pre-calibration";
- };
- };
-};
-
-&mdio0 {
- status = "okay";
-
- pinctrl-0 = <&mdio0_pins>;
- pinctrl-names = "default";
-
- switch@10 {
- compatible = "qca,qca8337";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x10>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "cpu";
- ethernet = <&gmac1>;
- phy-mode = "rgmii";
- tx-internal-delay-ps = <1000>;
- rx-internal-delay-ps = <1000>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- port@1 {
- reg = <1>;
- label = "lan4";
- phy-mode = "internal";
- phy-handle = <&phy_port1>;
- };
-
- port@2 {
- reg = <2>;
- label = "lan3";
- phy-mode = "internal";
- phy-handle = <&phy_port2>;
- };
-
- port@3 {
- reg = <3>;
- label = "lan2";
- phy-mode = "internal";
- phy-handle = <&phy_port3>;
- };
-
- port@4 {
- reg = <4>;
- label = "lan1";
- phy-mode = "internal";
- phy-handle = <&phy_port4>;
- };
-
- port@5 {
- reg = <5>;
- label = "wan";
- phy-mode = "internal";
- phy-handle = <&phy_port5>;
- };
-
- port@6 {
- reg = <6>;
- label = "cpu";
- ethernet = <&gmac2>;
- phy-mode = "sgmii";
- qca,sgmii-enable-pll;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy_port1: phy@0 {
- reg = <0>;
- };
-
- phy_port2: phy@1 {
- reg = <1>;
- };
-
- phy_port3: phy@2 {
- reg = <2>;
- };
-
- phy_port4: phy@3 {
- reg = <3>;
- };
-
- phy_port5: phy@4 {
- reg = <4>;
- };
- };
- };
-};
-
-&gmac1 {
- status = "okay";
- phy-mode = "rgmii";
- qcom,id = <1>;
-
- pinctrl-0 = <&rgmii2_pins>;
- pinctrl-names = "default";
-
- nvmem-cells = <&macaddr_defaultmac_0 1>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gmac2 {
- status = "okay";
- phy-mode = "sgmii";
- qcom,id = <2>;
-
- nvmem-cells = <&macaddr_defaultmac_0 0>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&adm_dma {
- status = "okay";
-};
+++ /dev/null
-#include "qcom-ipq8064-v2.0-smb208.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "NEC Aterm WG2600HP";
- compatible = "nec,wg2600hp", "qcom,ipq8064";
-
- memory@0 {
- reg = <0x42000000 0x1e000000>;
- device_type = "memory";
- };
-
- aliases {
- mdio-gpio0 = &mdio0;
-
- led-boot = &power_green;
- led-failsafe = &power_red;
- led-running = &power_green;
- led-upgrade = &power_green;
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&button_pins>;
- pinctrl-names = "default";
-
- wps {
- label = "wps";
- gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- bridge {
- label = "bridge";
- gpios = <&qcom_pinmux 24 GPIO_ACTIVE_LOW>;
- linux,code = <BTN_0>;
- linux,input-type = <EV_SW>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- converter {
- label = "converter";
- gpios = <&qcom_pinmux 25 GPIO_ACTIVE_LOW>;
- linux,code = <BTN_0>;
- linux,input-type = <EV_SW>;
- debounce-interval = <60>;
- wakeup-source;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- converter_green {
- label = "green:converter";
- gpios = <&qcom_pinmux 6 GPIO_ACTIVE_HIGH>;
- };
-
- power_red: power_red {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_RED>;
- gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
- };
-
- active_green {
- label = "green:active";
- gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
- };
-
- active_red {
- label = "red:active";
- gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
- };
-
- power_green: power_green {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&qcom_pinmux 14 GPIO_ACTIVE_HIGH>;
- };
-
- converter_red {
- label = "red:converter";
- gpios = <&qcom_pinmux 15 GPIO_ACTIVE_HIGH>;
- };
-
- wlan2g_green {
- label = "green:wlan2g";
- gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>;
- };
-
- wlan2g_red {
- label = "red:wlan2g";
- gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>;
- };
-
- wlan5g_green {
- label = "green:wlan5g";
- gpios = <&qcom_pinmux 57 GPIO_ACTIVE_HIGH>;
- };
-
- wlan5g_red {
- label = "red:wlan5g";
- gpios = <&qcom_pinmux 58 GPIO_ACTIVE_HIGH>;
- };
-
- tv_green {
- label = "green:tv";
- gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
- };
-
- tv_red {
- label = "red:tv";
- gpios = <&qcom_pinmux 65 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&CPU_SPC {
- status = "disabled";
-};
-
-&adm_dma {
- status = "okay";
-};
-
-&mdio0 {
- status = "okay";
-
- pinctrl-0 = <&mdio0_pins>;
- pinctrl-names = "default";
-
-switch@10 {
- compatible = "qca,qca8337";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x10>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "cpu";
- ethernet = <&gmac1>;
- phy-mode = "rgmii";
- tx-internal-delay-ps = <1000>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- port@1 {
- reg = <1>;
- label = "wan";
- phy-mode = "internal";
- phy-handle = <&phy_port1>;
- };
-
- port@2 {
- reg = <2>;
- label = "lan1";
- phy-mode = "internal";
- phy-handle = <&phy_port2>;
- };
-
- port@3 {
- reg = <3>;
- label = "lan2";
- phy-mode = "internal";
- phy-handle = <&phy_port3>;
- };
-
- port@4 {
- reg = <4>;
- label = "lan3";
- phy-mode = "internal";
- phy-handle = <&phy_port4>;
- };
-
- port@5 {
- reg = <5>;
- label = "lan4";
- phy-mode = "internal";
- phy-handle = <&phy_port5>;
- };
-
- port@6 {
- reg = <6>;
- label = "cpu";
- ethernet = <&gmac2>;
- phy-mode = "sgmii";
- qca,sgmii-enable-pll;
- qca,sgmii-rxclk-falling-edge;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy_port1: phy@0 {
- reg = <0>;
- };
-
- phy_port2: phy@1 {
- reg = <1>;
- };
-
- phy_port3: phy@2 {
- reg = <2>;
- };
-
- phy_port4: phy@3 {
- reg = <3>;
- };
-
- phy_port5: phy@4 {
- reg = <4>;
- };
- };
- };
-};
-
-&gmac1 {
- status = "okay";
-
- phy-mode = "rgmii";
- qcom,id = <1>;
-
- pinctrl-0 = <&rgmii2_pins>;
- pinctrl-names = "default";
-
- nvmem-cells = <&macaddr_PRODUCTDATA_6>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gmac2 {
- status = "okay";
-
- phy-mode = "sgmii";
- qcom,id = <2>;
-
- nvmem-cells = <&macaddr_PRODUCTDATA_0>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gsbi5 {
- status = "okay";
-
- qcom,mode = <GSBI_PROT_SPI>;
-
- spi@1a280000 {
- status = "okay";
-
- pinctrl-0 = <&spi_pins>;
- pinctrl-names = "default";
-
- cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- spi-max-frequency = <50000000>;
- reg = <0>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- SBL1@0 {
- label = "SBL1";
- reg = <0x0 0x20000>;
- read-only;
- };
-
- MIBIB@20000 {
- label = "MIBIB";
- reg = <0x20000 0x20000>;
- read-only;
- };
-
- SBL2@40000 {
- label = "SBL2";
- reg = <0x40000 0x40000>;
- read-only;
- };
-
- SBL3@80000 {
- label = "SBL3";
- reg = <0x80000 0x80000>;
- read-only;
- };
-
- DDRCONFIG@100000 {
- label = "DDRCONFIG";
- reg = <0x100000 0x10000>;
- read-only;
- };
-
- SSD@110000 {
- label = "SSD";
- reg = <0x110000 0x10000>;
- read-only;
- };
-
- TZ@120000 {
- label = "TZ";
- reg = <0x120000 0x80000>;
- read-only;
- };
-
- RPM@1a0000 {
- label = "RPM";
- reg = <0x1a0000 0x80000>;
- read-only;
- };
-
- APPSBL@220000 {
- label = "APPSBL";
- reg = <0x220000 0x80000>;
- read-only;
- };
-
- APPSBLENV@2a0000 {
- label = "APPSBLENV";
- reg = <0x2a0000 0x10000>;
- };
-
- PRODUCTDATA: PRODUCTDATA@2b0000 {
- label = "PRODUCTDATA";
- reg = <0x2b0000 0x30000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_PRODUCTDATA_0: macaddr@0 {
- reg = <0x0 0x6>;
- };
-
- macaddr_PRODUCTDATA_6: macaddr@6 {
- reg = <0x6 0x6>;
- };
-
- macaddr_PRODUCTDATA_c: macaddr@c {
- reg = <0xc 0x6>;
- };
-
- macaddr_PRODUCTDATA_12: macaddr@12 {
- reg = <0x12 0x6>;
- };
- };
- };
-
- ART@2e0000 {
- label = "ART";
- reg = <0x2e0000 0x40000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_ART_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_ART_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- TP@320000 {
- label = "TP";
- reg = <0x320000 0x40000>;
- read-only;
- };
-
- TINY@360000 {
- label = "TINY";
- reg = <0x360000 0x500000>;
- read-only;
- };
-
- firmware@860000 {
- compatible = "denx,uimage";
- label = "firmware";
- reg = <0x860000 0x17a0000>;
- };
- };
- };
- };
-};
-
-&hs_phy_0 {
- status = "okay";
-};
-
-&ss_phy_0 {
- status = "okay";
-};
-
-&usb3_0 {
- status = "okay";
-
- pinctrl-0 = <&usb_pwr_en_pins>;
- pinctrl-names = "default";
-};
-
-&hs_phy_1 {
- status = "okay";
-};
-
-&ss_phy_1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- compatible = "pci168c,0040";
- reg = <0x00010000 0 0 0 0>;
-
- nvmem-cells = <&macaddr_PRODUCTDATA_12>, <&precal_ART_1000>;
- nvmem-cell-names = "mac-address", "pre-calibration";
- };
- };
-};
-
-&pcie1 {
- status = "okay";
- max-link-speed = <1>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- compatible = "pci168c,0040";
- reg = <0x00010000 0 0 0 0>;
-
- nvmem-cells = <&macaddr_PRODUCTDATA_c>, <&precal_ART_5000>;
- nvmem-cell-names = "mac-address", "pre-calibration";
- };
- };
-};
-
-&qcom_pinmux {
- button_pins: button_pins {
- mux {
- pins = "gpio16", "gpio54", "gpio24", "gpio25";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- led_pins: led_pins {
- mux {
- pins = "gpio6", "gpio7", "gpio8", "gpio9", "gpio14",
- "gpio15", "gpio55", "gpio56", "gpio57", "gpio58",
- "gpio64", "gpio65";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-down;
- };
- };
-
- spi_pins: spi_pins {
- mux {
- pins = "gpio18", "gpio19", "gpio21";
- function = "gsbi5";
- bias-pull-down;
- };
-
- data {
- pins = "gpio18", "gpio19";
- drive-strength = <10>;
- };
-
- cs {
- pins = "gpio20";
- drive-strength = <10>;
- bias-pull-up;
- };
-
- clk {
- pins = "gpio21";
- drive-strength = <12>;
- };
- };
-
- usb_pwr_en_pins: usb_pwr_en_pins {
- mux {
- pins = "gpio22";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-down;
- output-high;
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Copyright (C) 2017 Christian Mehlis <christian@m3hlis.de>
- * Copyright (C) 2018 Mathias Kresin <dev@kresin.me>
- * All rights reserved.
- */
-
-#include "qcom-ipq8064-v1.0.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- compatible = "compex,wpq864", "qcom,ipq8064";
- model = "Compex WPQ864";
-
- aliases {
- mdio-gpio0 = &mdio0;
- ethernet0 = &gmac1;
- ethernet1 = &gmac0;
-
- led-boot = &led_pass;
- led-failsafe = &led_fail;
- led-running = &led_pass;
- led-upgrade = &led_pass;
- };
-
- leds {
- compatible = "gpio-leds";
-
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- rss4 {
- label = "green:rss4";
- gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
- };
-
- rss3 {
- label = "green:rss3";
- gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
- default-state = "keep";
- };
-
- rss2 {
- label = "orange:rss2";
- gpios = <&qcom_pinmux 25 GPIO_ACTIVE_HIGH>;
- };
-
- rss1 {
- label = "red:rss1";
- gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
- };
-
- led_pass: pass {
- label = "green:pass";
- gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
- };
-
- led_fail: fail {
- label = "green:fail";
- gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
- };
-
- usb {
- function = LED_FUNCTION_USB;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
- };
-
- usb-pcie {
- label = "green:usb-pcie";
- gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
- };
- };
-
- keys {
- compatible = "gpio-keys";
-
- pinctrl-0 = <&button_pins>;
- pinctrl-names = "default";
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- debounce-interval = <60>;
- wakeup-source;
- };
- };
-
- beeper {
- compatible = "gpio-beeper";
-
- pinctrl-0 = <&beeper_pins>;
- pinctrl-names = "default";
-
- gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&rpm {
- pinctrl-0 = <&rpm_pins>;
- pinctrl-names = "default";
-};
-
-&nand {
- status = "okay";
-
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
-
- mt29f2g08abbeah4@0 {
- compatible = "qcom,nandcs";
-
- reg = <0>;
-
- nand-ecc-strength = <4>;
- nand-bus-width = <8>;
- nand-ecc-step-size = <512>;
-
- nand-is-boot-medium;
- qcom,boot-partitions = <0x0 0x1180000 0x5340000 0x10c0000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x0000000 0x0040000>;
- read-only;
- };
-
- partition@40000 {
- label = "0:MIBIB";
- reg = <0x0040000 0x0140000>;
- read-only;
- };
-
- partition@180000 {
- label = "0:SBL2";
- reg = <0x0180000 0x0140000>;
- read-only;
- };
-
- partition@2c0000 {
- label = "0:SBL3";
- reg = <0x02c0000 0x0280000>;
- read-only;
- };
-
- partition@540000 {
- label = "0:DDRCONFIG";
- reg = <0x0540000 0x0120000>;
- read-only;
- };
-
- partition@660000 {
- label = "0:SSD";
- reg = <0x0660000 0x0120000>;
- read-only;
- };
-
- partition@780000 {
- label = "0:TZ";
- reg = <0x0780000 0x0280000>;
- read-only;
- };
-
- partition@a00000 {
- label = "0:RPM";
- reg = <0x0a00000 0x0280000>;
- read-only;
- };
-
- partition@c80000 {
- label = "0:APPSBL";
- reg = <0x0c80000 0x0500000>;
- read-only;
- };
-
- partition@1180000 {
- label = "0:APPSBLENV";
- reg = <0x1180000 0x0080000>;
- };
-
- partition@1200000 {
- label = "0:ART";
- reg = <0x1200000 0x0140000>;
- };
-
- partition@1340000 {
- label = "ubi";
- reg = <0x1340000 0x4000000>;
- };
-
- partition@5340000 {
- label = "0:BOOTCONFIG";
- reg = <0x5340000 0x0060000>;
- };
-
- partition@53a0000 {
- label = "0:SBL2_1";
- reg = <0x53a0000 0x0140000>;
- read-only;
- };
-
- partition@54e0000 {
- label = "0:SBL3_1";
- reg = <0x54e0000 0x0280000>;
- read-only;
- };
-
- partition@5760000 {
- label = "0:DDRCONFIG_1";
- reg = <0x5760000 0x0120000>;
- read-only;
- };
-
- partition@5880000 {
- label = "0:SSD_1";
- reg = <0x5880000 0x0120000>;
- read-only;
- };
-
- partition@59a0000 {
- label = "0:TZ_1";
- reg = <0x59a0000 0x0280000>;
- read-only;
- };
-
- partition@5c20000 {
- label = "0:RPM_1";
- reg = <0x5c20000 0x0280000>;
- read-only;
- };
-
- partition@5ea0000 {
- label = "0:BOOTCONFIG1";
- reg = <0x5ea0000 0x0060000>;
- };
-
- partition@5f00000 {
- label = "0:APPSBL_1";
- reg = <0x5f00000 0x0500000>;
- read-only;
- };
-
- partition@6400000 {
- label = "ubi_1";
- reg = <0x6400000 0x4000000>;
- };
-
- partition@a400000 {
- label = "unused";
- reg = <0xa400000 0x5c00000>;
- };
- };
- };
-};
-
-&adm_dma {
- status = "okay";
-};
-
-&mdio0 {
- status = "okay";
-
- pinctrl-0 = <&mdio0_pins>;
- pinctrl-names = "default";
-
- switch@10 {
- compatible = "qca,qca8337";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x10>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "cpu";
- ethernet = <&gmac1>;
- phy-mode = "rgmii";
- tx-internal-delay-ps = <1000>;
- rx-internal-delay-ps = <1000>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- port@1 {
- reg = <1>;
- label = "lan1";
- phy-mode = "internal";
- phy-handle = <&phy_port1>;
- };
-
- port@2 {
- reg = <2>;
- label = "lan2";
- phy-mode = "internal";
- phy-handle = <&phy_port2>;
- };
-
- port@3 {
- reg = <3>;
- label = "lan3";
- phy-mode = "internal";
- phy-handle = <&phy_port3>;
- };
-
- port@4 {
- reg = <4>;
- label = "lan4";
- phy-mode = "internal";
- phy-handle = <&phy_port4>;
- };
-
- port@5 {
- reg = <5>;
- label = "wan";
- phy-mode = "internal";
- phy-handle = <&phy_port5>;
- };
-
- port@6 {
- reg = <6>;
- label = "cpu";
- ethernet = <&gmac2>;
- phy-mode = "sgmii";
- qca,sgmii-enable-pll;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy_port1: phy@0 {
- reg = <0>;
- };
-
- phy_port2: phy@1 {
- reg = <1>;
- };
-
- phy_port3: phy@2 {
- reg = <2>;
- };
-
- phy_port4: phy@3 {
- reg = <3>;
- };
-
- phy_port5: phy@4 {
- reg = <4>;
- };
- };
- };
-};
-
-&gmac1 {
- status = "okay";
-
- pinctrl-0 = <&rgmii2_pins>;
- pinctrl-names = "default";
-
- phy-mode = "rgmii";
- qcom,id = <1>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gmac2 {
- status = "okay";
-
- phy-mode = "sgmii";
- qcom,id = <2>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gsbi4_serial {
- pinctrl-0 = <&uart0_pins>;
- pinctrl-names = "default";
-};
-
-&flash {
- compatible = "jedec,spi-nor";
-};
-
-&sata_phy {
- status = "disabled";
-};
-
-&sata {
- status = "disabled";
-};
-
-&hs_phy_0 {
- status = "okay";
-};
-
-&ss_phy_0 {
- status = "okay";
-
- rx_eq = <2>;
- tx_deamp_3_5db = <32>;
- mpll = <160>;
-};
-
-&usb3_0 {
- status = "okay";
-};
-
-&hs_phy_1 {
- status = "okay";
-};
-
-&ss_phy_1 {
- status = "okay";
-
- rx_eq = <2>;
- tx_deamp_3_5db = <32>;
- mpll = <160>;
-};
-
-&usb3_1 {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
-
- /delete-property/ pinctrl-0;
- /delete-property/ pinctrl-names;
- /delete-property/ perst-gpios;
-};
-
-&pcie1 {
- status = "okay";
-};
-
-&pcie2 {
- status = "okay";
-
- /delete-property/ pinctrl-0;
- /delete-property/ pinctrl-names;
- /delete-property/ perst-gpios;
-};
-
-&qcom_pinmux {
- pinctrl-names = "default";
- pinctrl-0 = <&state_default>;
-
- state_default: pinctrl0 {
- pcie0_pcie2_perst {
- pins = "gpio3";
- function = "gpio";
- drive-strength = <2>;
- bias-disable;
- output-high;
- };
- };
-
- led_pins: led_pins {
- mux {
- pins = "gpio7", "gpio8", "gpio9", "gpio22",
- "gpio23", "gpio24", "gpio25", "gpio53";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- button_pins: button_pins {
- mux {
- pins = "gpio54";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- beeper_pins: beeper_pins {
- mux {
- pins = "gpio55";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- rpm_pins: rpm_pins {
- mux {
- pins = "gpio12", "gpio13";
- function = "gsbi4";
- drive-strength = <10>;
- bias-disable;
- };
- };
-
- uart0_pins: uart0_pins {
- mux {
- pins = "gpio10", "gpio11";
- function = "gsbi4";
- drive-strength = <10>;
- bias-disable;
- };
- };
-
- spi_pins: spi_pins {
- mux {
- pins = "gpio18", "gpio19";
- function = "gsbi5";
- drive-strength = <10>;
- bias-pull-down;
- };
-
- clk {
- pins = "gpio21";
- function = "gsbi5";
- drive-strength = <12>;
- bias-pull-down;
- };
-
- cs {
- pins = "gpio20";
- function = "gpio";
- drive-strength = <10>;
- bias-pull-up;
- };
- };
-};
-
-&tcsr {
- qcom,usb-ctrl-select = <TCSR_USB_SELECT_USB3_DUAL>;
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-#include "qcom-ipq8064-v2.0-smb208.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "Buffalo WXR-2533DHP";
- compatible = "buffalo,wxr-2533dhp", "qcom,ipq8064";
-
- memory@42000000 {
- reg = <0x42000000 0x1e000000>;
- device_type = "memory";
- };
-
- aliases {
- led-boot = &power;
- led-failsafe = &diag;
- led-running = &power;
- led-upgrade = &power;
- };
-
- chosen {
- /* use "ubi_rootfs" volume in "ubi" partition as rootfs */
- bootargs = "ubi.block=0,1 root=/dev/ubiblock0_1 rootfstype=squashfs";
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- usb {
- function = LED_FUNCTION_USB;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "usbport";
- trigger-sources = <&hub_port0 &hub_port1>;
- };
-
- guestport {
- label = "green:guestport";
- gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
- };
-
- diag: diag {
- label = "orange:diag";
- gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
- };
-
- internet_orange {
- label = "orange:internet";
- gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>;
- };
-
- internet_white {
- label = "white:internet";
- gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
- };
-
- wireless_orange {
- label = "orange:wireless";
- gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
- };
-
- wireless_white {
- label = "white:wireless";
- gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
- };
-
- router_orange {
- label = "orange:router";
- gpios = <&qcom_pinmux 25 GPIO_ACTIVE_HIGH>;
- };
-
- router_white {
- label = "white:router";
- gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;
- };
-
- power: power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
- };
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&button_pins>;
- pinctrl-names = "default";
-
- power {
- label = "power";
- gpios = <&qcom_pinmux 58 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_POWER>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- wps {
- label = "wps";
- gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- eject {
- label = "eject";
- gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_EJECTCD>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- guest {
- label = "guest";
- gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>;
- linux,code = <BTN_0>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- ap {
- label = "ap";
- gpios = <&qcom_pinmux 55 GPIO_ACTIVE_LOW>;
- linux,code = <BTN_1>;
- linux,input-type = <EV_SW>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- router {
- label = "router";
- gpios = <&qcom_pinmux 56 GPIO_ACTIVE_LOW>;
- linux,code = <BTN_1>;
- linux,input-type = <EV_SW>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- auto {
- label = "auto";
- gpios = <&qcom_pinmux 57 GPIO_ACTIVE_LOW>;
- linux,code = <BTN_1>;
- linux,input-type = <EV_SW>;
- debounce-interval = <60>;
- wakeup-source;
- };
- };
-};
-
-&nand {
- status = "okay";
-
- cs@0 {
- reg = <0>;
- compatible = "qcom,nandcs";
-
- nand-ecc-strength = <4>;
- nand-bus-width = <8>;
- nand-ecc-step-size = <512>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- ubi@0 {
- label = "ubi";
- reg = <0x0000000 0x4000000>;
- };
-
- rootfs_1@4000000 {
- label = "rootfs_1";
- reg = <0x4000000 0x4000000>;
- };
- };
- };
-};
-
-&adm_dma {
- status = "okay";
-};
-
-&mdio0 {
- status = "okay";
-
- pinctrl-0 = <&mdio0_pins>;
- pinctrl-names = "default";
-
- switch@10 {
- compatible = "qca,qca8337";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x10>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "cpu";
- ethernet = <&gmac1>;
- phy-mode = "rgmii";
- tx-internal-delay-ps = <1000>;
- rx-internal-delay-ps = <1000>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- port@1 {
- reg = <1>;
- label = "lan1";
- phy-mode = "internal";
- phy-handle = <&phy_port1>;
- };
-
- port@2 {
- reg = <2>;
- label = "lan2";
- phy-mode = "internal";
- phy-handle = <&phy_port2>;
- };
-
- port@3 {
- reg = <3>;
- label = "lan3";
- phy-mode = "internal";
- phy-handle = <&phy_port3>;
- };
-
- port@4 {
- reg = <4>;
- label = "lan4";
- phy-mode = "internal";
- phy-handle = <&phy_port4>;
- };
-
- port@5 {
- reg = <5>;
- label = "wan";
- phy-mode = "internal";
- phy-handle = <&phy_port5>;
- };
-
- port@6 {
- reg = <6>;
- label = "cpu";
- ethernet = <&gmac2>;
- phy-mode = "sgmii";
- qca,sgmii-enable-pll;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy_port1: phy@0 {
- reg = <0>;
- };
-
- phy_port2: phy@1 {
- reg = <1>;
- };
-
- phy_port3: phy@2 {
- reg = <2>;
- };
-
- phy_port4: phy@3 {
- reg = <3>;
- };
-
- phy_port5: phy@4 {
- reg = <4>;
- };
- };
- };
-};
-
-&gmac1 {
- status = "okay";
-
- phy-mode = "rgmii";
- qcom,id = <1>;
-
- pinctrl-0 = <&rgmii2_pins>;
- pinctrl-names = "default";
-
- nvmem-cells = <&macaddr_ART_6>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gmac2 {
- status = "okay";
-
- phy-mode = "sgmii";
- qcom,id = <2>;
-
- nvmem-cells = <&macaddr_ART_0>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gsbi4_serial {
- pinctrl-0 = <&uart0_pins>;
- pinctrl-names = "default";
-};
-
-&gsbi5 {
- status = "okay";
- qcom,mode = <GSBI_PROT_SPI>;
-
- spi@1a280000 {
- status = "okay";
-
- pinctrl-0 = <&spi_pins>;
- pinctrl-names = "default";
-
- cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- spi-max-frequency = <50000000>;
- reg = <0>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- SBL1@0 {
- label = "SBL1";
- reg = <0x0 0x10000>;
- read-only;
- };
-
- MIBIB@10000 {
- label = "MIBIB";
- reg = <0x10000 0x20000>;
- read-only;
- };
-
- SBL2@30000 {
- label = "SBL2";
- reg = <0x30000 0x30000>;
- read-only;
- };
-
- SBL3@60000 {
- label = "SBL3";
- reg = <0x60000 0x30000>;
- read-only;
- };
-
- DDRCONFIG@90000 {
- label = "DDRCONFIG";
- reg = <0x90000 0x10000>;
- read-only;
- };
-
- SSD@a0000 {
- label = "SSD";
- reg = <0xa0000 0x10000>;
- read-only;
- };
-
- TZ@b0000 {
- label = "TZ";
- reg = <0xb0000 0x30000>;
- read-only;
- };
-
- RPM@e0000 {
- label = "RPM";
- reg = <0xe0000 0x20000>;
- read-only;
- };
-
- APPSBL@100000 {
- label = "APPSBL";
- reg = <0x100000 0x70000>;
- read-only;
- };
-
- APPSBLENV@170000 {
- label = "APPSBLENV";
- reg = <0x170000 0x10000>;
- read-only;
- };
-
- ART@180000 {
- label = "ART";
- reg = <0x180000 0x40000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_ART_0: macaddr@0 {
- reg = <0x0 0x6>;
- };
-
- macaddr_ART_6: macaddr@6 {
- reg = <0x6 0x6>;
- };
-
- macaddr_ART_18: macaddr@18 {
- reg = <0x18 0x6>;
- };
-
- macaddr_ART_1e: macaddr@1e {
- reg = <0x1e 0x6>;
- };
-
- precal_ART_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_ART_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- BOOTCONFIG@1c0000 {
- label = "BOOTCONFIG";
- reg = <0x1c0000 0x10000>;
- read-only;
- };
-
- APPSBL_1@1d0000 {
- label = "APPSBL_1";
- reg = <0x1d0000 0x70000>;
- read-only;
- };
- };
- };
- };
-};
-
-&hs_phy_0 {
- status = "okay";
-};
-
-&ss_phy_0 {
- status = "okay";
-};
-
-&usb3_0 {
- status = "okay";
-
- pinctrl-0 = <&usb_pwr_en_pins>;
- pinctrl-names = "default";
-};
-
-&hs_phy_1 {
- status = "okay";
-};
-
-&ss_phy_1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-};
-
-&dwc3_0 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- hub_port0: port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
-};
-
-&dwc3_1 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- hub_port1: port@1 {
- reg = <1>;
- #trigger-source-cells = <0>;
- };
-};
-
-&pcie0 {
- status = "okay";
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- compatible = "pci168c,0040";
- reg = <0x00010000 0 0 0 0>;
-
- nvmem-cells = <&macaddr_ART_1e>, <&precal_ART_1000>;
- nvmem-cell-names = "mac-address", "pre-calibration";
- };
- };
-};
-
-&pcie1 {
- status = "okay";
- max-link-speed = <1>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- compatible = "pci168c,0040";
- reg = <0x00010000 0 0 0 0>;
-
- nvmem-cells = <&macaddr_ART_18>, <&precal_ART_5000>;
- nvmem-cell-names = "mac-address", "pre-calibration";
- };
- };
-};
-
-&qcom_pinmux {
- button_pins: button_pins {
- mux {
- pins = "gpio6", "gpio54", "gpio55", "gpio56", "gpio57",
- "gpio58", "gpio64", "gpio65";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- led_pins: led_pins {
- mux {
- pins = "gpio7", "gpio8", "gpio9", "gpio16", "gpio22",
- "gpio23", "gpio24", "gpio25", "gpio26", "gpio53";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- uart0_pins: uart0_pins {
- mux {
- pins = "gpio10", "gpio11";
- function = "gsbi4";
- drive-strength = <12>;
- bias-disable;
- };
- };
-
- spi_pins: spi_pins {
- mux {
- pins = "gpio18", "gpio19", "gpio21";
- function = "gsbi5";
- bias-pull-down;
- };
-
- data {
- pins = "gpio18", "gpio19";
- drive-strength = <10>;
- };
-
- cs{
- pins = "gpio20";
- drive-strength = <10>;
- bias-pull-up;
- };
-
- clk {
- pins = "gpio21";
- drive-strength = <12>;
- };
- };
-
- usb_pwr_en_pins: usb_pwr_en_pins {
- mux{
- pins = "gpio68";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- output-high;
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq8065-smb208.dtsi"
-#include <dt-bindings/input/input.h>
-
-/ {
- model = "Nokia AC400i";
- compatible = "nokia,ac400i", "qcom,ipq8065", "qcom,ipq8064";
-
- aliases {
- mdio-gpio0 = &mdio0;
- ethernet0 = &gmac0;
- ethernet1 = &gmac1;
-
- led-boot = &pwr_red;
- led-failsafe = &pwr_red;
- led-running = &pwr_green;
- led-upgrade = &pwr_green;
- };
-
- chosen {
- bootargs-override = " console=ttyMSM0,115200n8 ubi.mtd=ubi root=/dev/ubiblock0_2";
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&button_pins>;
- pinctrl-names = "default";
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 15 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- 5g_red {
- label = "red:5g";
- gpios = <&qcom_pinmux 65 GPIO_ACTIVE_HIGH>;
- };
-
- 5g_green {
- label = "green:5g";
- gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
- };
-
- 2g_red {
- label = "red:2g";
- gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
- };
-
- 2g_green {
- label = "green:2g";
- gpios = <&qcom_pinmux 54 GPIO_ACTIVE_HIGH>;
- };
-
- eth1_red {
- label = "red:eth1";
- gpios = <&qcom_pinmux 68 GPIO_ACTIVE_HIGH>;
- };
-
- eth1_green {
- label = "green:eth1";
- gpios = <&qcom_pinmux 22 GPIO_ACTIVE_LOW>;
- };
-
- eth2_red {
- label = "red:eth2";
- gpios = <&qcom_pinmux 67 GPIO_ACTIVE_HIGH>;
- };
-
- eth2_green {
- label = "green:eth2";
- gpios = <&qcom_pinmux 23 GPIO_ACTIVE_LOW>;
- };
-
- ctrl_red {
- label = "red:ctrl";
- gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>;
- };
-
- ctrl_green {
- label = "green:ctrl";
- gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>;
- };
-
- pwr_red: pwr_red {
- label = "red:pwr";
- gpios = <&qcom_pinmux 2 GPIO_ACTIVE_LOW>;
- };
-
- pwr_green: pwr_green {
- label = "green:pwr";
- gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&qcom_pinmux {
- spi_pins: spi_pins {
- mux {
- pins = "gpio18", "gpio19";
- function = "gsbi5";
- drive-strength = <10>;
- bias-pull-down;
- };
-
- clk {
- pins = "gpio21";
- function = "gsbi5";
- drive-strength = <12>;
- bias-pull-down;
- };
-
- cs {
- pins = "gpio20";
- function = "gpio";
- drive-strength = <10>;
- bias-pull-up;
- };
- };
-
- led_pins: led_pins {
- mux {
- pins = "gpio65", "gpio64",
- "gpio53", "gpio54",
- "gpio68", "gpio22",
- "gpio67", "gpio23",
- "gpio55", "gpio56",
- "gpio2", "gpio26";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- button_pins: button_pins {
- mux {
- pins = "gpio15";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
-};
-
-&gsbi5 {
- qcom,mode = <GSBI_PROT_SPI>;
- status = "okay";
-
- spi4: spi@1a280000 {
- status = "okay";
- spi-max-frequency = <50000000>;
-
- pinctrl-0 = <&spi_pins>;
- pinctrl-names = "default";
-
- cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
-
- m25p80@0 {
- compatible = "jedec,spi-nor";
- #address-cells = <1>;
- #size-cells = <1>;
- spi-max-frequency = <50000000>;
- reg = <0>;
-
- partitions {
- compatible = "qcom,smem-part";
- };
- };
- };
-};
-
-&usb3_0 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
-
- /delete-property/ pinctrl-0;
- /delete-property/ pinctrl-names;
- /delete-property/ perst-gpios;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- compatible = "qcom,ath10k";
- status = "okay";
- reg = <0x00010000 0 0 0 0>;
- qcom,ath10k-calibration-variant = "Nokia-AC400i";
- };
- };
-};
-
-&pcie1 {
- status = "okay";
-
- /delete-property/ pinctrl-0;
- /delete-property/ pinctrl-names;
- /delete-property/ perst-gpios;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- compatible = "qcom,ath10k";
- status = "okay";
- reg = <0x00010000 0 0 0 0>;
- qcom,ath10k-calibration-variant = "Nokia-AC400i";
- };
- };
-};
-
-&mdio0 {
- status = "okay";
- pinctrl-0 = <&mdio0_pins>;
- pinctrl-names = "default";
-
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
-
-};
-
-//POE
-&gmac0 {
- status = "okay";
- qcom,id = <0>;
-
- pinctrl-0 = <&rgmii2_pins>;
- pinctrl-names = "default";
-
- mdiobus = <&mdio0>;
- phy-handle = <&phy0>;
- phy-mode = "rgmii";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-//LAN1
-&gmac1 {
- status = "okay";
- qcom,id = <1>;
-
- mdiobus = <&mdio0>;
- phy-handle = <&phy1>;
- phy-mode = "rgmii";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&nand {
- status = "okay";
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
-
- nand@0 {
- reg = <0>;
- compatible = "qcom,nandcs";
-
- nand-ecc-strength = <4>;
- nand-bus-width = <8>;
- nand-ecc-step-size = <512>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- rootfs@0 {
- label = "rootfs";
- reg = <0x0000000 0x4000000>;
- };
-
- rootfs_1@4000000 {
- label = "rootfs_1";
- reg = <0x4000000 0x4000000>;
- };
-
- cfg@8000000 {
- label = "cfg";
- reg = <0x8000000 0x8000000>;
- };
- };
- };
-};
-
-&adm_dma {
- status = "okay";
-};
+++ /dev/null
-#include "qcom-ipq8065-smb208.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "ZyXEL NBG6817";
- compatible = "zyxel,nbg6817", "qcom,ipq8065", "qcom,ipq8064";
-
- memory@0 {
- reg = <0x42000000 0x1e000000>;
- device_type = "memory";
- };
-
- aliases {
- mdio-gpio0 = &mdio0;
- sdcc1 = &sdcc1;
-
- led-boot = &power;
- led-failsafe = &power;
- led-running = &power;
- led-upgrade = &power;
- };
-
- chosen {
- bootargs = "rootfstype=squashfs,ext4 rootwait noinitrd fstools_ignore_partname=1";
- append-rootblock = "root=/dev/mmcblk0p";
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&button_pins>;
- pinctrl-names = "default";
-
- wifi {
- label = "wifi";
- gpios = <&qcom_pinmux 53 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RFKILL>;
- linux,input-type = <EV_SW>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- wps {
- label = "wps";
- gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- debounce-interval = <60>;
- wakeup-source;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- internet {
- label = "white:internet";
- gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
- };
-
- power: power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
- default-state = "keep";
- };
-
- wifi2g {
- label = "amber:wifi2g";
- gpios = <&qcom_pinmux 33 GPIO_ACTIVE_HIGH>;
- };
-
- /* wifi2g amber from the manual is missing */
-
- wifi5g {
- label = "amber:wifi5g";
- gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
- };
-
- /* wifi5g amber from the manual is missing */
- };
-};
-
-&qcom_pinmux {
- button_pins: button_pins {
- mux {
- pins = "gpio53", "gpio54", "gpio65";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- led_pins: led_pins {
- mux {
- pins = "gpio9", "gpio26", "gpio33", "gpio64";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-down;
- };
- };
-
- mdio0_pins: mdio0-pins {
- clk {
- pins = "gpio1";
- input-disable;
- };
- };
-
- rgmii2_pins: rgmii2-pins {
- tx {
- pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32" ;
- input-disable;
- };
- };
-
- spi_pins: spi_pins {
- cs {
- pins = "gpio20";
- drive-strength = <12>;
- };
- };
-
- usb0_pwr_en_pins: usb0_pwr_en_pins {
- mux {
- pins = "gpio16", "gpio17";
- function = "gpio";
- drive-strength = <12>;
- };
-
- pwr {
- pins = "gpio17";
- bias-pull-down;
- output-high;
- };
-
- ovc {
- pins = "gpio16";
- bias-pull-up;
- };
- };
-
- usb1_pwr_en_pins: usb1_pwr_en_pins {
- mux {
- pins = "gpio14", "gpio15";
- function = "gpio";
- drive-strength = <12>;
- };
-
- pwr {
- pins = "gpio14";
- bias-pull-down;
- output-high;
- };
-
- ovc {
- pins = "gpio15";
- bias-pull-up;
- };
- };
-};
-
-&gsbi5 {
- qcom,mode = <GSBI_PROT_SPI>;
- status = "okay";
-
- spi4: spi@1a280000 {
- status = "okay";
-
- pinctrl-0 = <&spi_pins>;
- pinctrl-names = "default";
-
- cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
-
- m25p80@0 {
- compatible = "jedec,spi-nor";
- #address-cells = <1>;
- #size-cells = <1>;
- spi-max-frequency = <51200000>;
- reg = <0>;
-
- partitions {
- compatible = "qcom,smem-part";
- };
- };
- };
-};
-
-&hs_phy_0 {
- status = "okay";
-};
-
-&ss_phy_0 {
- status = "okay";
-};
-
-&usb3_0 {
- status = "okay";
-
- pinctrl-0 = <&usb0_pwr_en_pins>;
- pinctrl-names = "default";
-};
-
-&hs_phy_1 {
- status = "okay";
-};
-
-&ss_phy_1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-
- pinctrl-0 = <&usb1_pwr_en_pins>;
- pinctrl-names = "default";
-};
-
-&pcie0 {
- status = "okay";
- reset-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
- pinctrl-0 = <&pcie0_pins>;
- pinctrl-names = "default";
-};
-
-&pcie1 {
- status = "okay";
- reset-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
- pinctrl-0 = <&pcie1_pins>;
- pinctrl-names = "default";
- max-link-speed = <1>;
-};
-
-&mdio0 {
- status = "okay";
-
- pinctrl-0 = <&mdio0_pins>;
- pinctrl-names = "default";
-
- switch@10 {
- compatible = "qca,qca8337";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x10>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "cpu";
- ethernet = <&gmac1>;
- phy-mode = "rgmii";
- tx-internal-delay-ps = <1000>;
- rx-internal-delay-ps = <1000>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- port@1 {
- reg = <1>;
- label = "lan1";
- phy-mode = "internal";
- phy-handle = <&phy_port1>;
- };
-
- port@2 {
- reg = <2>;
- label = "lan2";
- phy-mode = "internal";
- phy-handle = <&phy_port2>;
- };
-
- port@3 {
- reg = <3>;
- label = "lan3";
- phy-mode = "internal";
- phy-handle = <&phy_port3>;
- };
-
- port@4 {
- reg = <4>;
- label = "lan4";
- phy-mode = "internal";
- phy-handle = <&phy_port4>;
- };
-
- port@5 {
- reg = <5>;
- label = "wan";
- phy-mode = "internal";
- phy-handle = <&phy_port5>;
- };
-
- port@6 {
- reg = <6>;
- label = "cpu";
- ethernet = <&gmac2>;
- phy-mode = "sgmii";
- qca,sgmii-enable-pll;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy_port1: phy@0 {
- reg = <0>;
- };
-
- phy_port2: phy@1 {
- reg = <1>;
- };
-
- phy_port3: phy@2 {
- reg = <2>;
- };
-
- phy_port4: phy@3 {
- reg = <3>;
- };
-
- phy_port5: phy@4 {
- reg = <4>;
- };
- };
- };
-};
-
-&gmac1 {
- status = "okay";
- phy-mode = "rgmii";
- qcom,id = <1>;
- qcom,phy_mdio_addr = <4>;
- qcom,poll_required = <0>;
- qcom,rgmii_delay = <1>;
- qcom,phy_mii_type = <0>;
- qcom,emulation = <0>;
- qcom,irq = <255>;
- mdiobus = <&mdio0>;
-
- pinctrl-0 = <&rgmii2_pins>;
- pinctrl-names = "default";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gmac2 {
- status = "okay";
- phy-mode = "sgmii";
- qcom,id = <2>;
- qcom,phy_mdio_addr = <0>; /* none */
- qcom,poll_required = <0>; /* no polling */
- qcom,rgmii_delay = <0>;
- qcom,phy_mii_type = <1>;
- qcom,emulation = <0>;
- qcom,irq = <258>;
- mdiobus = <&mdio0>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&sdcc1 {
- status = "okay";
-};
-
-&adm_dma {
- status = "okay";
-};
+++ /dev/null
-#include "qcom-ipq8065-smb208.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- memory@0 {
- reg = <0x42000000 0x1e000000>;
- device_type = "memory";
- };
-
- reserved-memory {
- rsvd@5fe00000 {
- reg = <0x5fe00000 0x200000>;
- reusable;
- };
-
- ramoops@42100000 {
- compatible = "ramoops";
- reg = <0x42100000 0x40000>;
- record-size = <0x4000>;
- console-size = <0x4000>;
- ftrace-size = <0x4000>;
- pmsg-size = <0x4000>;
- };
- };
-
- aliases {
- label-mac-device = &gmac2;
-
- led-boot = &power_white;
- led-failsafe = &power_amber;
- led-running = &power_white;
- led-upgrade = &power_amber;
-
- mdio-gpio0 = &mdio0;
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&button_pins>;
- pinctrl-names = "default";
-
- wifi {
- label = "wifi";
- gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RFKILL>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- wps {
- label = "wps";
- gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- debounce-interval = <60>;
- wakeup-source;
- };
- };
-
- leds: leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- power_white: power_white {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
- default-state = "keep";
- };
-
- power_amber: power_amber {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_AMBER>;
- gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
- };
-
- wan_white {
- function = LED_FUNCTION_WAN;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
- };
-
- wan_amber {
- function = LED_FUNCTION_WAN;
- color = <LED_COLOR_ID_AMBER>;
- gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
- };
-
- wifi {
- label = "white:wifi";
- gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
- };
-
- wps {
- function = LED_FUNCTION_WPS;
- color = <LED_COLOR_ID_WHITE>;
- gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&qcom_pinmux {
- button_pins: button_pins {
- mux {
- pins = "gpio6", "gpio54", "gpio65";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- led_pins: led_pins {
- mux {
- pins = "gpio7", "gpio8", "gpio9",
- "gpio22", "gpio23", "gpio24",
- "gpio26", "gpio53", "gpio64";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-down;
- };
- };
-
- mdio0_pins: mdio0-pins {
- clk {
- pins = "gpio1";
- input-disable;
- };
- };
-
- rgmii2_pins: rgmii2-pins {
- tx {
- pins = "gpio27", "gpio28", "gpio29",
- "gpio30", "gpio31", "gpio32";
- input-disable;
- };
- };
-
- spi_pins: spi_pins {
- mux {
- pins = "gpio18", "gpio19", "gpio21";
- function = "gsbi5";
- bias-pull-down;
- };
-
- data {
- pins = "gpio18", "gpio19";
- drive-strength = <10>;
- };
-
- cs {
- pins = "gpio20";
- drive-strength = <10>;
- bias-pull-up;
- };
-
- clk {
- pins = "gpio21";
- drive-strength = <12>;
- };
- };
-
- spi6_pins: spi6_pins {
- mux {
- pins = "gpio55", "gpio56", "gpio58";
- function = "gsbi6";
- bias-pull-down;
- };
-
- mosi {
- pins = "gpio55";
- drive-strength = <12>;
- };
-
- miso {
- pins = "gpio56";
- drive-strength = <14>;
- };
-
- cs {
- pins = "gpio57";
- drive-strength = <12>;
- bias-pull-up;
- };
-
- clk {
- pins = "gpio58";
- drive-strength = <12>;
- };
-
- reset {
- pins = "gpio33";
- drive-strength = <10>;
- bias-pull-down;
- output-high;
- };
- };
-
- usb0_pwr_en_pins: usb0_pwr_en_pins {
- mux {
- pins = "gpio15";
- function = "gpio";
- drive-strength = <12>;
- bias-pull-down;
- output-high;
- };
- };
-
- usb1_pwr_en_pins: usb1_pwr_en_pins {
- mux {
- pins = "gpio16", "gpio68";
- function = "gpio";
- drive-strength = <12>;
- bias-pull-down;
- output-high;
- };
- };
-};
-
-&nand {
- status = "okay";
-
- nand@0 {
- reg = <0>;
- compatible = "qcom,nandcs";
-
- nand-ecc-strength = <4>;
- nand-bus-width = <8>;
- nand-ecc-step-size = <512>;
-
- nand-is-boot-medium;
- qcom,boot-partitions = <0x0 0x1180000>;
-
- partitions: partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "qcadata";
- reg = <0x0000000 0x0c80000>;
- read-only;
- };
-
- partition@c80000 {
- label = "APPSBL";
- reg = <0x0c80000 0x0500000>;
- read-only;
- };
-
- partition@1180000 {
- label = "APPSBLENV";
- reg = <0x1180000 0x0080000>;
- read-only;
- };
-
- art: partition@1200000 {
- label = "art";
- reg = <0x1200000 0x0140000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_art_0: macaddr@0 {
- reg = <0x0 0x6>;
- };
-
- macaddr_art_6: macaddr@6 {
- compatible = "mac-base";
- reg = <0x6 0x6>;
- #nvmem-cell-cells = <1>;
- };
-
- macaddr_art_c: macaddr@c {
- reg = <0xc 0x6>;
- };
-
- precal_art_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_art_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- partition@1340000 {
- label = "artbak";
- reg = <0x1340000 0x0140000>;
- read-only;
- };
-
- partition@1480000 {
- label = "kernel";
- reg = <0x1480000 0x0400000>;
- };
- };
- };
-};
-
-&mdio0 {
- status = "okay";
-
- pinctrl-0 = <&mdio0_pins>;
- pinctrl-names = "default";
-
- switch@10 {
- compatible = "qca,qca8337";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x10>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "cpu";
- ethernet = <&gmac1>;
- phy-mode = "rgmii";
- tx-internal-delay-ps = <1000>;
- rx-internal-delay-ps = <1000>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- port@1 {
- reg = <1>;
- label = "lan4";
- phy-mode = "internal";
- phy-handle = <&phy_port1>;
- };
-
- port@2 {
- reg = <2>;
- label = "lan3";
- phy-mode = "internal";
- phy-handle = <&phy_port2>;
- };
-
- port@3 {
- reg = <3>;
- label = "lan2";
- phy-mode = "internal";
- phy-handle = <&phy_port3>;
- };
-
- port@4 {
- reg = <4>;
- label = "lan1";
- phy-mode = "internal";
- phy-handle = <&phy_port4>;
- };
-
- port@5 {
- reg = <5>;
- label = "wan";
- phy-mode = "internal";
- phy-handle = <&phy_port5>;
- };
-
- port@6 {
- reg = <6>;
- label = "cpu";
- ethernet = <&gmac2>;
- phy-mode = "sgmii";
- qca,sgmii-enable-pll;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy_port1: phy@0 {
- reg = <0>;
- };
-
- phy_port2: phy@1 {
- reg = <1>;
- };
-
- phy_port3: phy@2 {
- reg = <2>;
- };
-
- phy_port4: phy@3 {
- reg = <3>;
- };
-
- phy_port5: phy@4 {
- reg = <4>;
- };
- };
- };
-};
-
-&gmac1 {
- status = "okay";
-
- phy-mode = "rgmii";
- qcom,id = <1>;
- qcom,phy_mdio_addr = <4>;
- qcom,poll_required = <0>;
- qcom,rgmii_delay = <1>;
- qcom,phy_mii_type = <0>;
- qcom,emulation = <0>;
- qcom,irq = <255>;
- mdiobus = <&mdio0>;
-
- pinctrl-0 = <&rgmii2_pins>;
- pinctrl-names = "default";
-
- nvmem-cells = <&macaddr_art_6 0>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gmac2 {
- status = "okay";
-
- phy-mode = "sgmii";
- qcom,id = <2>;
- qcom,phy_mdio_addr = <0>; /* none */
- qcom,poll_required = <0>; /* no polling */
- qcom,rgmii_delay = <0>;
- qcom,phy_mii_type = <1>;
- qcom,emulation = <0>;
- qcom,irq = <258>;
- mdiobus = <&mdio0>;
-
- nvmem-cells = <&macaddr_art_0>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&adm_dma {
- status = "okay";
-};
-
-&sata_phy {
- status = "okay";
-};
-
-&sata {
- status = "okay";
-};
-
-&hs_phy_0 {
- status = "okay";
-};
-
-&ss_phy_0 {
- status = "okay";
-};
-
-&usb3_0 {
- status = "okay";
-
- pinctrl-0 = <&usb0_pwr_en_pins>;
- pinctrl-names = "default";
-};
-
-&hs_phy_1 {
- status = "okay";
-};
-
-&ss_phy_1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-
- pinctrl-0 = <&usb1_pwr_en_pins>;
- pinctrl-names = "default";
-};
-
-&pcie0 {
- status = "okay";
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi0: wifi@1,0 {
- compatible = "pci168c,0046";
- reg = <0x00010000 0 0 0 0>;
- };
- };
-};
-
-&pcie1 {
- status = "okay";
-
- max-link-speed = <1>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi1: wifi@1,0 {
- compatible = "pci168c,0046";
- reg = <0x00010000 0 0 0 0>;
- };
- };
-};
+++ /dev/null
-#include "qcom-ipq8065-nighthawk.dtsi"
-
-/ {
- model = "Netgear Nighthawk X4S R7800";
- compatible = "netgear,r7800", "qcom,ipq8065", "qcom,ipq8064";
-};
-
-&leds {
- usb1 {
- label = "white:usb1";
- gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
- };
-
- usb2 {
- label = "white:usb2";
- gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
- };
-
- esata {
- label = "white:esata";
- gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&partitions {
- partition@1880000 {
- label = "ubi";
- reg = <0x1880000 0x6080000>;
- };
-
- partition@7900000 {
- label = "reserve";
- reg = <0x7900000 0x0700000>;
- read-only;
- };
-};
-
-&wifi0 {
- nvmem-cells = <&macaddr_art_6 1>, <&precal_art_1000>;
- nvmem-cell-names = "mac-address", "pre-calibration";
-};
-
-&wifi1 {
- nvmem-cells = <&macaddr_art_6 2>, <&precal_art_5000>;
- nvmem-cell-names = "mac-address", "pre-calibration";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "qcom-ipq8065-smb208.dtsi"
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "Askey RT4230W REV6";
- compatible = "askey,rt4230w-rev6", "qcom,ipq8065", "qcom,ipq8064";
-
- memory@0 {
- reg = <0x42000000 0x3e000000>;
- device_type = "memory";
- };
-
- aliases {
- led-boot = &ledctrl3;
- led-failsafe = &ledctrl1;
- led-running = &ledctrl2;
- led-upgrade = &ledctrl3;
- };
-
- chosen {
- bootargs = "rootfstype=squashfs noinitrd";
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&button_pins>;
- pinctrl-names = "default";
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
-
- wps {
- label = "wps";
- gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- ledctrl1: ledctrl1 {
- label = "ledctrl1";
- gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
- };
-
- ledctrl2: ledctrl2 {
- label = "ledctrl2";
- gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
- };
-
- ledctrl3: ledctrl3 {
- label = "ledctrl3";
- gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&qcom_pinmux {
- button_pins: button_pins {
- mux {
- pins = "gpio54", "gpio68";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- led_pins: led_pins {
- mux {
- pins = "gpio22", "gpio23", "gpio24";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-down;
- };
- };
-
- rgmii2_pins: rgmii2-pins {
- mux {
- pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31",
- "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62";
- function = "rgmii2";
- drive-strength = <8>;
- bias-disable;
- };
-
- tx {
- pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32";
- input-disable;
- };
- };
-
- spi_pins: spi_pins {
- cs {
- pins = "gpio20";
- drive-strength = <12>;
- };
- };
-};
-
-&gsbi5 {
- qcom,mode = <GSBI_PROT_SPI>;
- status = "okay";
-
- spi@1a280000 {
- status = "okay";
-
- pinctrl-0 = <&spi_pins>;
- pinctrl-names = "default";
-
- cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "everspin,mr25h256";
- #address-cells = <1>;
- #size-cells = <1>;
- spi-max-frequency = <40000000>;
- reg = <0>;
- };
- };
-};
-
-&nand {
- status = "okay";
-
- nand@0 {
- reg = <0>;
- compatible = "qcom,nandcs";
-
- nand-ecc-strength = <4>;
- nand-bus-width = <8>;
- nand-ecc-step-size = <512>;
-
- qcom,boot-partitions = <0x0 0x1180000 0x1340000 0x10c0000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x0000000 0x0040000>;
- read-only;
- };
-
- partition@40000 {
- label = "0:MIBIB";
- reg = <0x0040000 0x0140000>;
- read-only;
- };
-
- partition@180000 {
- label = "0:SBL2";
- reg = <0x0180000 0x0140000>;
- read-only;
- };
-
- partition@2c0000 {
- label = "0:SBL3";
- reg = <0x02c0000 0x0280000>;
- read-only;
- };
-
- partition@540000 {
- label = "0:DDRCONFIG";
- reg = <0x0540000 0x0120000>;
- read-only;
- };
-
- partition@660000 {
- label = "0:SSD";
- reg = <0x0660000 0x0120000>;
- read-only;
- };
-
- partition@780000 {
- label = "0:TZ";
- reg = <0x0780000 0x0280000>;
- read-only;
- };
-
- partition@a00000 {
- label = "0:RPM";
- reg = <0x0a00000 0x0280000>;
- read-only;
- };
-
- partition@c80000 {
- label = "0:APPSBL";
- reg = <0x0c80000 0x0500000>;
- read-only;
- };
-
- partition@1180000 {
- label = "0:APPSBLENV";
- reg = <0x1180000 0x0080000>;
- };
-
- partition@1200000 {
- label = "0:ART";
- reg = <0x1200000 0x0140000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_ART_0: macaddr@0 {
- reg = <0x0 0x6>;
- };
-
- macaddr_ART_6: macaddr@6 {
- reg = <0x6 0x6>;
- };
-
- precal_ART_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
-
- precal_ART_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
-
- partition@1340000 {
- label = "0:BOOTCONFIG";
- reg = <0x1340000 0x0060000>;
- read-only;
- };
-
- partition@13a0000 {
- label = "0:SBL2_1";
- reg = <0x13a0000 0x0140000>;
- read-only;
- };
-
- partition@14e0000 {
- label = "0:SBL3_1";
- reg = <0x14e0000 0x0280000>;
- read-only;
- };
-
- partition@1760000 {
- label = "0:DDRCONFIG_1";
- reg = <0x1760000 0x0120000>;
- read-only;
- };
-
- partition@1880000 {
- label = "0:SSD_1";
- reg = <0x1880000 0x0120000>;
- read-only;
- };
-
- partition@19a0000 {
- label = "0:TZ_1";
- reg = <0x19a0000 0x0280000>;
- read-only;
- };
-
- partition@1c20000 {
- label = "0:RPM_1";
- reg = <0x1c20000 0x0280000>;
- read-only;
- };
-
- partition@1ea0000 {
- label = "0:BOOTCONFIG1";
- reg = <0x1ea0000 0x0060000>;
- read-only;
- };
-
- partition@1f00000 {
- label = "0:APPSBL_1";
- reg = <0x1f00000 0x0500000>;
- read-only;
- };
-
- partition@2400000 {
- label = "ubi";
- reg = <0x2400000 0x1a000000>;
- };
- };
- };
-};
-
-&mdio0 {
- status = "okay";
-
- pinctrl-0 = <&mdio0_pins>;
- pinctrl-names = "default";
-
- switch@10 {
- compatible = "qca,qca8337";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x10>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "cpu";
- ethernet = <&gmac0>;
- phy-mode = "rgmii";
- tx-internal-delay-ps = <1000>;
- rx-internal-delay-ps = <1000>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- port@1 {
- reg = <1>;
- label = "wan";
- phy-mode = "internal";
- phy-handle = <&phy_port1>;
-
- leds {
- #address-cells = <1>;
- #size-cells = <0>;
-
- led@0 {
- reg = <0>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_WAN;
- default-state = "keep";
- };
-
- led@1 {
- reg = <1>;
- color = <LED_COLOR_ID_AMBER>;
- function = LED_FUNCTION_WAN;
- default-state = "keep";
- };
- };
- };
-
- port@2 {
- reg = <2>;
- label = "lan1";
- phy-mode = "internal";
- phy-handle = <&phy_port2>;
-
- leds {
- #address-cells = <1>;
- #size-cells = <0>;
-
- led@0 {
- reg = <0>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_LAN;
- default-state = "keep";
- };
-
- led@1 {
- reg = <1>;
- color = <LED_COLOR_ID_AMBER>;
- function = LED_FUNCTION_LAN;
- default-state = "keep";
- };
- };
- };
-
- port@3 {
- reg = <3>;
- label = "lan2";
- phy-mode = "internal";
- phy-handle = <&phy_port3>;
-
- leds {
- #address-cells = <1>;
- #size-cells = <0>;
-
- led@0 {
- reg = <0>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_LAN;
- default-state = "keep";
- };
-
- led@1 {
- reg = <1>;
- color = <LED_COLOR_ID_AMBER>;
- function = LED_FUNCTION_LAN;
- default-state = "keep";
- };
- };
- };
-
- port@4 {
- reg = <4>;
- label = "lan3";
- phy-mode = "internal";
- phy-handle = <&phy_port4>;
-
- leds {
- #address-cells = <1>;
- #size-cells = <0>;
-
- led@0 {
- reg = <0>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_LAN;
- default-state = "keep";
- };
-
- led@1 {
- reg = <1>;
- color = <LED_COLOR_ID_AMBER>;
- function = LED_FUNCTION_LAN;
- default-state = "keep";
- };
- };
- };
-
- port@5 {
- reg = <5>;
- label = "lan4";
- phy-mode = "internal";
- phy-handle = <&phy_port5>;
-
- leds {
- #address-cells = <1>;
- #size-cells = <0>;
-
- led@0 {
- reg = <0>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_LAN;
- default-state = "keep";
- };
-
- led@1 {
- reg = <1>;
- color = <LED_COLOR_ID_AMBER>;
- function = LED_FUNCTION_LAN;
- default-state = "keep";
- };
- };
- };
-
- port@6 {
- reg = <6>;
- label = "cpu";
- ethernet = <&gmac1>;
- phy-mode = "sgmii";
- qca,sgmii-enable-pll;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy_port1: phy@0 {
- reg = <0>;
- };
-
- phy_port2: phy@1 {
- reg = <1>;
- };
-
- phy_port3: phy@2 {
- reg = <2>;
- };
-
- phy_port4: phy@3 {
- reg = <3>;
- };
-
- phy_port5: phy@4 {
- reg = <4>;
- };
- };
- };
-};
-
-&gmac0 {
- status = "okay";
- phy-mode = "rgmii";
- qcom,id = <0>;
-
- nvmem-cells = <&macaddr_ART_0>;
- nvmem-cell-names = "mac-address";
-
- pinctrl-0 = <&rgmii2_pins>;
- pinctrl-names = "default";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gmac1 {
- status = "okay";
- phy-mode = "sgmii";
- qcom,id = <1>;
-
- nvmem-cells = <&macaddr_ART_6>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&adm_dma {
- status = "okay";
-};
-
-&hs_phy_0 {
- status = "okay";
-};
-
-&ss_phy_0 {
- status = "okay";
-};
-
-&usb3_0 {
- status = "okay";
-};
-
-&hs_phy_1 {
- status = "okay";
-};
-
-&ss_phy_1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
- reset-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>;
- pinctrl-0 = <&pcie0_pins>;
- pinctrl-names = "default";
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi0: wifi@1,0 {
- compatible = "pci168c,0046";
- reg = <0x00010000 0 0 0 0>;
-
- nvmem-cells = <&precal_ART_1000>;
- nvmem-cell-names = "pre-calibration";
- };
- };
-};
-
-&pcie1 {
- status = "okay";
- reset-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>;
- pinctrl-0 = <&pcie1_pins>;
- pinctrl-names = "default";
- max-link-speed = <1>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi1: wifi@1,0 {
- compatible = "pci168c,0046";
- reg = <0x00010000 0 0 0 0>;
-
- nvmem-cells = <&precal_ART_5000>;
- nvmem-cell-names = "pre-calibration";
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-#include "qcom-ipq8065-smb208.dtsi"
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "Arris TR4400 v2";
- compatible = "arris,tr4400-v2", "qcom,ipq8065", "qcom,ipq8064";
-
- memory@0 {
- reg = <0x42000000 0x1e000000>;
- device_type = "memory";
- };
-
- aliases {
- led-boot = &led_status_blue;
- led-failsafe = &led_status_red;
- led-running = &led_status_blue;
- led-upgrade = &led_status_red;
- };
-
- chosen {
- bootargs = "rootfstype=squashfs noinitrd";
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&button_pins>;
- pinctrl-names = "default";
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- debounce-interval = <60>;
- wakeup-source;
- };
-
- wps {
- label = "wps";
- gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WPS_BUTTON>;
- debounce-interval = <60>;
- wakeup-source;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- led_status_red: status_red {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_RED>;
- gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
- };
-
- led_status_blue: status_blue {
- function = LED_FUNCTION_STATUS;
- color = <LED_COLOR_ID_BLUE>;
- gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&qcom_pinmux {
- button_pins: button_pins {
- mux {
- pins = "gpio6", "gpio54";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- led_pins: led_pins {
- mux {
- pins = "gpio7", "gpio8";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-down;
- };
- };
-
- rgmii2_pins: rgmii2-pins {
- tx {
- pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32";
- input-disable;
- };
- };
-
- spi_pins: spi_pins {
- cs {
- pins = "gpio20";
- drive-strength = <12>;
- };
- };
-};
-
-&gsbi5 {
- qcom,mode = <GSBI_PROT_SPI>;
- status = "okay";
-
- spi@1a280000 {
- status = "okay";
-
- pinctrl-0 = <&spi_pins>;
- pinctrl-names = "default";
-
- cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "everspin,mr25h256";
- spi-max-frequency = <40000000>;
- reg = <0>;
- };
- };
-};
-
-&nand {
- status = "okay";
-
- nand@0 {
- reg = <0>;
- compatible = "qcom,nandcs";
-
- nand-ecc-strength = <4>;
- nand-bus-width = <8>;
- nand-ecc-step-size = <512>;
-
- qcom,boot-partitions = <0x0 0x1180000 0x5340000 0x10c0000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "0:SBL1";
- reg = <0x0000000 0x0040000>;
- read-only;
- };
- partition@40000 {
- label = "0:MIBIB";
- reg = <0x0040000 0x0140000>;
- read-only;
- };
- partition@180000 {
- label = "0:SBL2";
- reg = <0x0180000 0x0140000>;
- read-only;
- };
- partition@2c0000 {
- label = "0:SBL3";
- reg = <0x02c0000 0x0280000>;
- read-only;
- };
- partition@540000 {
- label = "0:DDRCONFIG";
- reg = <0x0540000 0x0120000>;
- read-only;
- };
- partition@660000 {
- label = "0:SSD";
- reg = <0x0660000 0x0120000>;
- read-only;
- };
- partition@780000 {
- label = "0:TZ";
- reg = <0x0780000 0x0280000>;
- read-only;
- };
- partition@a00000 {
- label = "0:RPM";
- reg = <0x0a00000 0x0280000>;
- read-only;
- };
- partition@c80000 {
- label = "0:APPSBL";
- reg = <0x0c80000 0x0500000>;
- read-only;
- };
- partition@1180000 {
- label = "0:APPSBLENV";
- reg = <0x1180000 0x0080000>;
- };
- partition@1200000 {
- label = "0:ART";
- reg = <0x1200000 0x0140000>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- precal_ART_1000: precal@1000 {
- reg = <0x1000 0x2f20>;
- };
- precal_ART_5000: precal@5000 {
- reg = <0x5000 0x2f20>;
- };
- };
- };
- stock_partition@1340000 {
- label = "stock_rootfs";
- reg = <0x1340000 0x4000000>;
-
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "extra";
- reg = <0x0 0x4000000>;
- };
- };
- partition@5340000 {
- label = "0:BOOTCONFIG";
- reg = <0x5340000 0x0060000>;
- read-only;
- };
- partition@53a0000 {
- label = "0:SBL2_1";
- reg = <0x53a0000 0x0140000>;
- read-only;
- };
- partition@54e0000 {
- label = "0:SBL3_1";
- reg = <0x54e0000 0x0280000>;
- read-only;
- };
- partition@5760000 {
- label = "0:DDRCONFIG_1";
- reg = <0x5760000 0x0120000>;
- read-only;
- };
- partition@5880000 {
- label = "0:SSD_1";
- reg = <0x5880000 0x0120000>;
- read-only;
- };
- partition@59a0000 {
- label = "0:TZ_1";
- reg = <0x59a0000 0x0280000>;
- read-only;
- };
- partition@5c20000 {
- label = "0:RPM_1";
- reg = <0x5c20000 0x0280000>;
- read-only;
- };
- partition@5ea0000 {
- label = "0:BOOTCONFIG1";
- reg = <0x5ea0000 0x0060000>;
- read-only;
- };
- partition@5f00000 {
- label = "0:APPSBL_1";
- reg = <0x5f00000 0x0500000>;
- read-only;
- };
- stock_partition@6400000 {
- label = "stock_rootfs_1";
- reg = <0x6400000 0x4000000>;
-
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "fw_env";
- reg = <0x0 0x100000>;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_fw_env_0: macaddr@0 {
- reg = <0x00 0x6>;
- };
- macaddr_fw_env_6: macaddr@6 {
- reg = <0x06 0x6>;
- };
- macaddr_fw_env_c: macaddr@c {
- reg = <0x0c 0x6>;
- };
- macaddr_fw_env_12: macaddr@12 {
- reg = <0x12 0x6>;
- };
- macaddr_fw_env_18: macaddr@18 {
- reg = <0x18 0x6>;
- };
- };
- };
-
- partition@100000 {
- label = "ubi";
- reg = <0x100000 0x9b00000>;
- };
- };
- stock_partition@a400000 {
- label = "stock_fw_env";
- reg = <0xa400000 0x0100000>;
- };
- stock_partition@a500000 {
- label = "stock_config";
- reg = <0xa500000 0x0800000>;
- };
- stock_partition@ad00000 {
- label = "stock_PKI";
- reg = <0xad00000 0x0200000>;
- };
- stock_partition@af00000 {
- label = "stock_scfgmgr";
- reg = <0xaf00000 0x0100000>;
- };
- };
- };
-};
-
-&mdio0 {
- status = "okay";
-
- pinctrl-0 = <&mdio0_pins>;
- pinctrl-names = "default";
-
- switch@10 {
- compatible = "qca,qca8337";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x10>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "cpu";
- ethernet = <&gmac0>;
- phy-mode = "rgmii";
- tx-internal-delay-ps = <1000>;
- rx-internal-delay-ps = <1000>;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- port@1 {
- reg = <1>;
- label = "lan1";
- phy-mode = "internal";
- phy-handle = <&phy_port1>;
- };
-
- port@2 {
- reg = <2>;
- label = "lan2";
- phy-mode = "internal";
- phy-handle = <&phy_port2>;
- };
-
- port@3 {
- reg = <3>;
- label = "lan3";
- phy-mode = "internal";
- phy-handle = <&phy_port3>;
- };
-
- port@4 {
- reg = <4>;
- label = "lan4";
- phy-mode = "internal";
- phy-handle = <&phy_port4>;
- };
-
- port@6 {
- reg = <6>;
- label = "cpu";
- ethernet = <&gmac1>;
- phy-mode = "sgmii";
- qca,sgmii-enable-pll;
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy_port1: phy@0 {
- reg = <0>;
- };
-
- phy_port2: phy@1 {
- reg = <1>;
- };
-
- phy_port3: phy@2 {
- reg = <2>;
- };
-
- phy_port4: phy@3 {
- reg = <3>;
- };
- };
- };
-
- phy7: ethernet-phy@7 {
- reg = <7>;
- };
-};
-
-&gmac0 {
- status = "okay";
- phy-mode = "rgmii";
- qcom,id = <0>;
-
- nvmem-cells = <&macaddr_fw_env_18>;
- nvmem-cell-names = "mac-address";
-
- pinctrl-0 = <&rgmii2_pins>;
- pinctrl-names = "default";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gmac1 {
- status = "okay";
- phy-mode = "sgmii";
- qcom,id = <1>;
-
- nvmem-cells = <&macaddr_fw_env_0>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gmac3 {
- status = "okay";
- phy-mode = "sgmii";
- qcom,id = <3>;
- phy-handle = <&phy7>;
-
- nvmem-cells = <&macaddr_fw_env_6>;
- nvmem-cell-names = "mac-address";
-};
-
-&adm_dma {
- status = "okay";
-};
-
-&hs_phy_1 {
- status = "okay";
-};
-
-&ss_phy_1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
- reset-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>;
- pinctrl-0 = <&pcie0_pins>;
- pinctrl-names = "default";
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi0: wifi@1,0 {
- compatible = "pci168c,0046";
- reg = <0x00010000 0 0 0 0>;
-
- nvmem-cells = <&precal_ART_1000>, <&macaddr_fw_env_12>;
- nvmem-cell-names = "pre-calibration", "mac-address";
- };
- };
-};
-
-&pcie1 {
- status = "okay";
- reset-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>;
- pinctrl-0 = <&pcie1_pins>;
- pinctrl-names = "default";
- max-link-speed = <1>;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi1: wifi@1,0 {
- compatible = "pci168c,0040";
- reg = <0x00010000 0 0 0 0>;
-
- nvmem-cells = <&precal_ART_5000>, <&macaddr_fw_env_c>;
- nvmem-cell-names = "pre-calibration", "mac-address";
- };
- };
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq8065-nighthawk.dtsi"
-
-/ {
- model = "Netgear Nighthawk XR450";
- compatible = "netgear,xr450", "qcom,ipq8065", "qcom,ipq8064";
-
-};
-
-&leds {
- usb1 {
- label = "white:usb1";
- gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
- };
-
- usb2 {
- label = "white:usb2";
- gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&partitions {
- partition@1880000 {
- label = "ubi";
- reg = <0x1880000 0xce00000>;
- };
-
- partition@e680000 {
- label = "reserve";
- reg = <0xe680000 0x0780000>;
- read-only;
- };
-};
-
-&wifi0 {
- nvmem-cells = <&macaddr_art_c>, <&precal_art_1000>;
- nvmem-cell-names = "mac-address", "pre-calibration";
-};
-
-&wifi1 {
- nvmem-cells = <&macaddr_art_0>, <&precal_art_5000>;
- nvmem-cell-names = "mac-address", "pre-calibration";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq8065-nighthawk.dtsi"
-
-/ {
- model = "Netgear Nighthawk XR500";
- compatible = "netgear,xr500", "qcom,ipq8065", "qcom,ipq8064";
-
-};
-
-&leds {
- usb1 {
- label = "white:usb1";
- gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
- };
-
- usb2 {
- label = "white:usb2";
- gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&partitions {
- partition@1880000 {
- label = "ubi";
- reg = <0x1880000 0xce00000>;
- };
-
- partition@e680000 {
- label = "reserve";
- reg = <0xe680000 0x0780000>;
- read-only;
- };
-};
-
-&wifi0 {
- nvmem-cells = <&macaddr_art_c>, <&precal_art_1000>;
- nvmem-cell-names = "mac-address", "pre-calibration";
-};
-
-&wifi1 {
- nvmem-cells = <&macaddr_art_0>, <&precal_art_5000>;
- nvmem-cell-names = "mac-address", "pre-calibration";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-#include "qcom-ipq8064-v2.0.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "Extreme Networks AP3935";
- compatible = "extreme,ap3935", "qcom,ipq8064";
-
- memory@0 {
- reg = <0x41400000 0x3ec00000>;
- device_type = "memory";
- };
-
- aliases {
- serial0 = &gsbi7_serial;
- serial1 = &gsbi2_serial;
- mdio-gpio0 = &mdio0;
- ethernet0 = &gmac0;
- ethernet1 = &gmac2;
-
- led-boot = &led_power_green;
- led-failsafe = &led_power_orange;
- led-running = &led_power_green;
- led-upgrade = &led_power_green;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- bootargs-override = "ubi.block=0,0 root=/dev/ubiblock0_0";
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&button_pins>;
- pinctrl-names = "default";
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 56 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- debounce-interval = <60>;
- wakeup-source;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- led_power_green: power_green {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&qcom_pinmux 22 GPIO_ACTIVE_LOW>;
- };
-
- led_power_orange: power_orange {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_ORANGE>;
- gpios = <&qcom_pinmux 23 GPIO_ACTIVE_LOW>;
- };
-
- led_wlan2g_green {
- label = "green:wlan2g";
- gpios = <&qcom_pinmux 24 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy0tpt";
- };
-
- led_wlan5g_green {
- label = "green:wlan5g";
- gpios = <&qcom_pinmux 25 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "phy1tpt";
- };
-
- led_lan1_green {
- label = "green:lan1";
- gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;
- };
-
- led_lan1_orange {
- label = "orange:lan1";
- gpios = <&qcom_pinmux 27 GPIO_ACTIVE_LOW>;
- };
-
- led_lan2_green {
- label = "green:lan2";
- gpios = <&qcom_pinmux 28 GPIO_ACTIVE_LOW>;
- };
-
- led_lan2_orange {
- label = "orange:lan2";
- gpios = <&qcom_pinmux 29 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-
-&qcom_pinmux {
- spi_pins: spi_pins {
- mux {
- pins = "gpio18", "gpio19";
- function = "gsbi5";
- drive-strength = <10>;
- bias-pull-down;
- };
-
- clk {
- pins = "gpio21";
- function = "gsbi5";
- drive-strength = <12>;
- bias-pull-down;
- };
-
- cs {
- pins = "gpio20";
- function = "gpio";
- drive-strength = <10>;
- bias-pull-up;
- };
- };
-
- led_pins: led_pins {
- mux {
- pins = "gpio22", "gpio23", "gpio24", "gpio25",
- "gpio26", "gpio27", "gpio28", "gpio29";
- function = "gpio";
- drive-strength = <10>;
- bias-pull-up;
- };
- };
-
- button_pins: button_pins {
- mux {
- pins = "gpio56";
- function = "gpio";
- bias-pull-up;
- };
- };
-};
-
-&gsbi2 {
- qcom,mode = <GSBI_PROT_I2C_UART>;
- status = "okay";
-
- gsbi2_serial: serial@12490000 {
- status = "okay";
- };
-};
-
-&gsbi4 {
- qcom,mode = <GSBI_PROT_I2C_UART>;
- status = "okay";
-
- serial@16340000 {
- status = "disabled";
- };
-};
-
-&gsbi7 {
- qcom,mode = <GSBI_PROT_I2C_UART>;
- status = "okay";
-
- gsbi7_serial: serial@16640000 {
- status = "okay";
- };
-};
-
-&gsbi5 {
- qcom,mode = <GSBI_PROT_SPI>;
- status = "okay";
-
- spi4: spi@1a280000 {
- status = "okay";
- spi-max-frequency = <50000000>;
-
- pinctrl-0 = <&spi_pins>;
- pinctrl-names = "default";
-
- cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- spi-max-frequency = <50000000>;
- reg = <0>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- cfg1@2a0000 {
- compatible = "u-boot,env-redundant-bool";
- label = "CFG1";
- reg = <0x2a0000 0x0010000>;
-
- ethaddr: ethaddr {
- #nvmem-cell-cells = <1>;
- };
- };
-
- bootpri@2b0000 {
- label = "BootPRI";
- reg = <0x2b0000 0x0080000>;
- };
-
- cfg2@330000 {
- label = "CFG2";
- reg = <0x330000 0x0010000>;
- };
-
- fs@340000 {
- label = "FS";
- reg = <0x340000 0x0080000>;
- };
-
- priimg@3c0000 {
- label = "PriImg";
- reg = <0x3c0000 0x0e10000>;
- };
-
- secimg@11d0000 {
- label = "SecImg";
- reg = <0x11d0000 0x0e10000>;
- };
- };
- };
- };
-};
-
-&pcie0 {
- status = "okay";
-
- /delete-property/ pinctrl-0;
- /delete-property/ pinctrl-names;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- compatible = "qcom,ath10k";
- status = "okay";
- reg = <0x00010000 0 0 0 0>;
- };
- };
-};
-
-&pcie1 {
- status = "okay";
-
- /delete-property/ pinctrl-0;
- /delete-property/ pinctrl-names;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- compatible = "qcom,ath10k";
- status = "okay";
- reg = <0x00010000 0 0 0 0>;
- };
- };
-};
-
-&nand {
- status = "okay";
-
- pinctrl-0 = <&nand_pins>;
- pinctrl-names = "default";
-
- nand@0 {
- compatible = "qcom,nandcs";
-
- reg = <0>;
-
- nand-ecc-strength = <8>;
- nand-bus-width = <8>;
- nand-ecc-step-size = <512>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- ubi@0 {
- label = "ubi";
- reg = <0x0000000 0x20000000>;
- };
- };
- };
-};
-
-&soc {
- mdio1: mdio {
- compatible = "virtual,mdio-gpio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- status = "okay";
-
- pinctrl-0 = <&mdio0_pins>;
- pinctrl-names = "default";
-
- gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH &qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
-
- phy2: ethernet-phy@2 {
- reg = <2>;
- };
- };
-};
-
-&gmac0 {
- status = "okay";
-
- qcom,id = <0>;
- mdiobus = <&mdio1>;
-
- phy-mode = "rgmii";
- phy-handle = <&phy1>;
-
- nvmem-cells = <ðaddr 0>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&gmac2 {
- status = "okay";
-
- qcom,id = <2>;
- mdiobus = <&mdio1>;
-
- phy-mode = "sgmii";
- phy-handle = <&phy2>;
-
- nvmem-cells = <ðaddr 1>;
- nvmem-cell-names = "mac-address";
-};
-
-&adm_dma {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0 OR MIT
-
-#include "qcom-ipq8064-v2.0-smb208.dtsi"
-
-/ {
- memory {
- device_type = "memory";
- linux,usable-memory = <0x41500000 0x1ea00000>;
- reg = <0x40000000 0x20000000>;
- };
-
- cpus {
- idle-states {
- CPU_SPC: spc {
- status = "disabled";
- };
- };
- };
-
- chosen {
- bootargs-append = " console=ttyMSM0,115200n8 ubi.mtd=ubi ubi.mtd=art";
- };
-};
-
-&qcom_pinmux {
- mdio0_pins_active: mdio0_pins_active {
- mux {
- pins = "gpio0", "gpio1";
- function = "mdio";
- drive-strength = <2>;
- bias-pull-down;
- output-low;
- };
-
- clk {
- pins = "gpio1";
- input-disable;
- };
- };
-
- phy_active: phy_active {
- phy {
- pins = "gpio6", "gpio7";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-down;
- output-high;
- };
- };
-
- uart1_pins: uart1_pins {
- mux {
- pins = "gpio51", "gpio52";
- function = "gsbi1";
- drive-strength = <4>;
- bias-disable;
- };
- };
-};
-
-&gsbi1 {
- status = "okay";
- qcom,mode = <GSBI_PROT_UART_W_FC>;
-
- serial@12450000 {
- status = "okay";
-
- pinctrl-0 = <&uart1_pins>;
- pinctrl-names = "default";
- };
-};
-
-&pcie0 {
- status = "okay";
-
- /delete-property/ pinctrl-0;
- /delete-property/ pinctrl-names;
- /delete-property/ perst-gpios;
-
- bridge@0,0 {
- reg = <0x0 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi0: wifi@1,0 {
- compatible = "qcom,ath10k";
- status = "okay";
- reg = <0x10000 0 0 0 0>;
- };
- };
-};
-
-&pcie1 {
- status = "okay";
-
- /delete-property/ pinctrl-0;
- /delete-property/ pinctrl-names;
- /delete-property/ perst-gpios;
-
- bridge@0,0 {
- reg = <0x0 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi1: wifi@1,0 {
- compatible = "qcom,ath10k";
- status = "okay";
- reg = <0x10000 0 0 0 0>;
- };
- };
-};
-
-&pcie2 {
- status = "okay";
-
- /delete-property/ pinctrl-0;
- /delete-property/ pinctrl-names;
- /delete-property/ perst-gpios;
-
- bridge@0,0 {
- reg = <0x0 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi2: wifi@1,0 {
- compatible = "qcom,ath10k";
- status = "okay";
- reg = <0x10000 0 0 0 0>;
- };
- };
-};
-
-&adm_dma {
- status = "okay";
-};
-
-&nand {
- status = "okay";
-
- nand@0 {
- compatible = "qcom,nandcs";
-
- reg = <0>;
-
- nand-ecc-strength = <4>;
- nand-bus-width = <8>;
- nand-ecc-step-size = <512>;
-
- nand-is-boot-medium;
- qcom,boot-partitions = <0x0 0x2140000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "sbl1";
- reg = <0x0 0x40000>;
- read-only;
- };
-
- partition@40000 {
- label = "mibib";
- reg = <0x40000 0x140000>;
- read-only;
- };
-
- partition@180000 {
- label = "sbl2";
- reg = <0x180000 0x140000>;
- read-only;
- };
-
- partition@2c0000 {
- label = "sbl3";
- reg = <0x2c0000 0x280000>;
- read-only;
- };
-
- partition@540000 {
- label = "ddrconfig";
- reg = <0x540000 0x120000>;
- read-only;
- };
-
- partition@660000 {
- label = "ssd";
- reg = <0x660000 0x120000>;
- read-only;
- };
-
- partition@780000 {
- label = "tz";
- reg = <0x780000 0x280000>;
- read-only;
- };
-
- partition@a00000 {
- label = "rpm";
- reg = <0xa00000 0x280000>;
- read-only;
- };
-
- partition@1fc0000 {
- label = "u-boot";
- reg = <0x1fc0000 0x180000>;
- read-only;
- };
-
- partition@21c0000 {
- label = "bootkernel1";
- reg = <0x21c0000 0xa80000>;
- };
-
- partition@2c40000 {
- label = "bootkernel2";
- reg = <0x2c40000 0xa80000>;
- };
-
- partition@36c0000 {
- label = "ubi";
- reg = <0x36c0000 0x46c0000>;
- };
-
- partition@7d80000 {
- label = "art";
- reg = <0x7d80000 0x200000>;
- read-only;
- };
- };
- };
-};
+++ /dev/null
-#include "qcom-ipq8064-v2.0-smb208.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/soc/qcom,tcsr.h>
-
-/ {
- model = "Edgecore ECW5410";
- compatible = "edgecore,ecw5410", "qcom,ipq8064";
-
- reserved-memory {
- nss@40000000 {
- reg = <0x40000000 0x1000000>;
- no-map;
- };
-
- smem: smem@41000000 {
- reg = <0x41000000 0x200000>;
- no-map;
- };
-
- wifi_dump@44000000 {
- reg = <0x44000000 0x600000>;
- no-map;
- };
- };
-
- cpus {
- idle-states {
- CPU_SPC: spc {
- status = "disabled";
- };
- };
- };
-
- aliases {
- serial1 = &gsbi1_serial;
- ethernet0 = &gmac2;
- ethernet1 = &gmac3;
-
- led-boot = &led_power_green;
- led-failsafe = &led_power_red;
- led-running = &led_power_green;
- led-upgrade = &led_power_green;
- };
-
- chosen {
- bootargs-append = " console=ttyMSM0,115200n8 root=/dev/ubiblock0_1";
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&button_pins>;
- pinctrl-names = "default";
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 25 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- debounce-interval = <60>;
- wakeup-source;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- led_power_green: power_green {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_GREEN>;
- gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>;
- };
-
- wlan2g_green {
- label = "green:wlan2g";
- gpios = <&qcom_pinmux 23 GPIO_ACTIVE_LOW>;
- };
-
- wlan2g_yellow {
- label = "yellow:wlan2g";
- gpios = <&qcom_pinmux 24 GPIO_ACTIVE_LOW>;
- };
-
- wlan5g_green {
- label = "green:wlan5g";
- gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;
- };
-
- led_power_red: power_red {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_RED>;
- gpios = <&qcom_pinmux 28 GPIO_ACTIVE_LOW>;
- };
-
- wlan5g_yellow {
- label = "yellow:wlan5g";
- gpios = <&qcom_pinmux 59 GPIO_ACTIVE_LOW>;
- };
- };
-};
-
-
-&qcom_pinmux {
- spi_pins: spi_pins {
- mux {
- pins = "gpio18", "gpio19";
- function = "gsbi5";
- drive-strength = <10>;
- bias-pull-down;
- };
-
- clk {
- pins = "gpio21";
- function = "gsbi5";
- drive-strength = <12>;
- bias-pull-down;
- };
-
- cs {
- pins = "gpio20";
- function = "gpio";
- drive-strength = <10>;
- bias-pull-up;
- };
- };
-
- led_pins: led_pins {
- mux {
- pins = "gpio16", "gpio23", "gpio24", "gpio26",
- "gpio28", "gpio59";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- button_pins: button_pins {
- mux {
- pins = "gpio25";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- uart1_pins: uart1_pins {
- mux {
- pins = "gpio51", "gpio52", "gpio53", "gpio54";
- function = "gsbi1";
- drive-strength = <12>;
- bias-none;
- };
- };
-};
-
-&gsbi1 {
- qcom,mode = <GSBI_PROT_UART_W_FC>;
- status = "okay";
-
- serial@12450000 {
- status = "okay";
-
- pinctrl-0 = <&uart1_pins>;
- pinctrl-names = "default";
- };
-};
-
-&gsbi5 {
- qcom,mode = <GSBI_PROT_SPI>;
- status = "okay";
-
- spi4: spi@1a280000 {
- status = "okay";
- spi-max-frequency = <50000000>;
-
- pinctrl-0 = <&spi_pins>;
- pinctrl-names = "default";
-
- cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
-
- m25p80@0 {
- compatible = "jedec,spi-nor";
- #address-cells = <1>;
- #size-cells = <1>;
- spi-max-frequency = <50000000>;
- reg = <0>;
-
- partitions {
- compatible = "qcom,smem-part";
- };
- };
- };
-};
-
-&hs_phy_0 {
- status = "okay";
-};
-
-&ss_phy_0 {
- status = "okay";
-};
-
-&usb3_0 {
- status = "okay";
-};
-
-&hs_phy_1 {
- status = "okay";
-};
-
-&ss_phy_1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-};
-
-&pcie1 {
- status = "okay";
-
- /delete-property/ pinctrl-0;
- /delete-property/ pinctrl-names;
- /delete-property/ perst-gpios;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- compatible = "qcom,ath10k";
- status = "okay";
- reg = <0x00010000 0 0 0 0>;
- qcom,ath10k-calibration-variant = "Edgecore-ECW5410-L";
- };
- };
-};
-
-&pcie2 {
- status = "okay";
-
- /delete-property/ pinctrl-0;
- /delete-property/ pinctrl-names;
- /delete-property/ perst-gpios;
-
- bridge@0,0 {
- reg = <0x00000000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
-
- wifi@1,0 {
- compatible = "qcom,ath10k";
- status = "okay";
- reg = <0x00010000 0 0 0 0>;
- qcom,ath10k-calibration-variant = "Edgecore-ECW5410-L";
- };
- };
-};
-
-&nand {
- status = "okay";
-
- nand@0 {
- compatible = "qcom,nandcs";
-
- reg = <0>;
-
- nand-ecc-strength = <4>;
- nand-bus-width = <8>;
- nand-ecc-step-size = <512>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- rootfs1@0 {
- label = "rootfs1";
- reg = <0x0000000 0x4000000>;
- };
-
- rootfs2@4000000 {
- label = "rootfs2";
- reg = <0x4000000 0x4000000>;
- };
- };
- };
-};
-
-&mdio0 {
- status = "okay";
-
- pinctrl-0 = <&mdio0_pins>;
- pinctrl-names = "default";
-
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
-};
-
-&gmac2 {
- status = "okay";
-
- qcom,id = <2>;
- mdiobus = <&mdio0>;
-
- phy-mode = "sgmii";
- phy-handle = <&phy1>;
-};
-
-&gmac3 {
- status = "okay";
-
- qcom,id = <3>;
- mdiobus = <&mdio0>;
-
- phy-mode = "sgmii";
- phy-handle = <&phy0>;
-};
-
-&adm_dma {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0 OR MIT
-
-#include "qcom-ipq8068-cryptid-common.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "Meraki MR42";
- compatible = "meraki,mr42", "qcom,ipq8064";
-
- aliases {
- serial1 = &gsbi1_serial;
- ethernet0 = &gmac3;
-
- led-boot = &led_active;
- led-failsafe = &led_power;
- led-running = &led_active;
- led-upgrade = &led_active;
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&button_pins>;
- pinctrl-names = "default";
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- debounce-interval = <60>;
- wakeup-source;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- led_power: power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_ORANGE>;
- gpios = <&qcom_pinmux 31 GPIO_ACTIVE_HIGH>;
- };
-
- led_active: active {
- label = "white:active";
- gpios = <&qcom_pinmux 32 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&gmac3 {
- status = "okay";
-
- qcom,id = <3>;
- mdiobus = <&mdio0>;
-
- phy-mode = "sgmii";
- phy-handle = <&phy2>;
-
- nvmem-cells = <&mac_address 0>;
- nvmem-cell-names = "mac-address";
-};
-
-&gsbi2 {
- status = "okay";
- qcom,mode = <GSBI_PROT_I2C>;
-};
-
-&gsbi2_i2c {
- status = "okay";
-
- pinctrl-0 = <&i2c0_pins>;
- pinctrl-names = "default";
-
- ina2xx@40 {
- compatible = "ina219";
- shunt-resistor = <40000>;
- reg = <0x40>;
- };
-
- eeprom@56 {
- compatible = "atmel,24c64";
- pagesize = <32>;
- reg = <0x56>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- mac_address: mac-address@66 {
- compatible = "mac-base";
- reg = <0x66 0x6>;
- #nvmem-cell-cells = <1>;
- };
- };
- };
-};
-
-&gsbi6 {
- qcom,mode = <GSBI_PROT_I2C>;
- status = "okay";
-};
-
-&gsbi6_i2c {
- status = "okay";
-
- pinctrl-0 = <&i2c1_pins>;
- pinctrl-names = "default";
-
- tlc591xx@40 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "ti,tlc59108";
- reg = <0x40>;
-
- red@0 {
- label = "red:user";
- reg = <0x0>;
- };
-
- green@1 {
- label = "green:user";
- reg = <0x1>;
- };
-
- blue@2 {
- label = "blue:user";
- reg = <0x2>;
- };
- };
-};
-
-&mdio0 {
- status = "okay";
-
- pinctrl-0 = <&mdio0_pins_active>, <&phy_active>;
- pinctrl-names = "default";
-
- phy2: ethernet-phy2 {
- reg = <2>;
-
- reset-gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
- reset-assert-us = <24000>;
-
- eee-broken-100tx;
- eee-broken-1000t;
- };
-};
-
-&qcom_pinmux {
- i2c0_pins: i2c0_pins {
- mux {
- pins = "gpio24", "gpio25";
- function = "gsbi2";
- drive-strength = <2>;
- bias-pull-up;
- input;
- };
- };
-
- button_pins: button_pins {
- mux {
- pins = "gpio26";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- };
- };
-
- i2c1_pins: i2c1_pins {
- mux {
- pins = "gpio29", "gpio30";
- function = "gsbi6";
- drive-strength = <2>;
- bias-pull-up;
- input;
- };
- };
-
- led_pins: led_pins {
- mux {
- pins = "gpio31", "gpio32";
- function = "gpio";
- drive-strength = <12>;
- bias-pull-down;
- output-low;
- };
- };
-};
-
-&wifi0 {
- nvmem-cells = <&mac_address 1>;
- nvmem-cell-names = "mac-address";
-};
-
-&wifi1 {
- nvmem-cells = <&mac_address 2>;
- nvmem-cell-names = "mac-address";
-};
-
-&wifi2 {
- nvmem-cells = <&mac_address 3>;
- nvmem-cell-names = "mac-address";
-};
-
-&hs_phy_0 {
- status = "okay";
-};
-
-&ss_phy_0 {
- status = "okay";
-};
-
-&usb3_0 {
- status = "okay";
-};
-
-&hs_phy_1 {
- status = "okay";
-};
-
-&ss_phy_1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0 OR MIT
-
-#include "qcom-ipq8068-cryptid-common.dtsi"
-
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-
-/ {
- model = "Meraki MR52";
- compatible = "meraki,mr52", "qcom,ipq8064";
-
- aliases {
- serial1 = &gsbi1_serial;
- mdio-gpio0 = &mdio_gpio0;
- ethernet0 = &gmac2;
- ethernet1 = &gmac3;
-
- led-boot = &led_active;
- led-failsafe = &led_power;
- led-running = &led_active;
- led-upgrade = &led_active;
- };
-
- keys {
- compatible = "gpio-keys";
- pinctrl-0 = <&button_pins>;
- pinctrl-names = "default";
-
- reset {
- label = "reset";
- gpios = <&qcom_pinmux 25 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- debounce-interval = <60>;
- wakeup-source;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-0 = <&led_pins>;
- pinctrl-names = "default";
-
- led_power: power {
- function = LED_FUNCTION_POWER;
- color = <LED_COLOR_ID_ORANGE>;
- gpios = <&qcom_pinmux 19 GPIO_ACTIVE_HIGH>;
- };
-
- lan2_green {
- label = "green:lan2";
- gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
- };
-
- lan1_green {
- label = "green:lan1";
- gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
- };
-
- led_active: active {
- label = "white:active";
- gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;
- };
-
- lan2_orange {
- label = "orange:lan2";
- gpios = <&qcom_pinmux 60 GPIO_ACTIVE_HIGH>;
- };
-
- lan1_orange {
- label = "orange:lan1";
- gpios = <&qcom_pinmux 62 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&gmac2 {
- status = "okay";
-
- qcom,id = <2>;
- mdiobus = <&mdio0>;
-
- phy-mode = "sgmii";
- phy-handle = <&phy0>;
-
- nvmem-cells = <&mac_address 0>;
- nvmem-cell-names = "mac-address";
-};
-
-&gmac3 {
- status = "okay";
-
- qcom,id = <3>;
- mdiobus = <&mdio_gpio0>;
-
- phy-mode = "sgmii";
- phy-handle = <&phy4>;
-
- nvmem-cells = <&mac_address 1>;
- nvmem-cell-names = "mac-address";
-};
-
-&gsbi7 {
- status = "okay";
- qcom,mode = <GSBI_PROT_I2C>;
-};
-
-&gsbi7_i2c {
- status = "okay";
-
- pinctrl-0 = <&i2c_pins>;
- pinctrl-names = "default";
-
- ina2xx@45 {
- compatible = "ina219";
- shunt-resistor = <80000>;
- reg = <0x45>;
- };
-
- tlc591xx@49 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "ti,tlc59108";
- reg = <0x49>;
-
- red@0 {
- label = "red:user";
- reg = <0x0>;
- };
-
- green@1 {
- label = "green:user";
- reg = <0x1>;
- };
-
- blue@2 {
- label = "blue:user";
- reg = <0x2>;
- };
- };
-
- eeprom@52 {
- compatible = "atmel,24c64";
- pagesize = <32>;
- reg = <0x52>;
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- mac_address: mac-address@66 {
- compatible = "mac-base";
- reg = <0x66 0x6>;
- #nvmem-cell-cells = <1>;
- };
- };
- };
-};
-
-&qcom_pinmux {
- i2c_pins: i2c_pins {
- mux {
- pins = "gpio8", "gpio9";
- function = "gsbi7";
- drive-strength = <2>;
- bias-pull-up;
- input;
- };
- };
-
- led_pins: led_pins {
- mux {
- pins = "gpio19", "gpio26";
- function = "gpio";
- drive-strength = <12>;
- bias-pull-down;
- output-low;
- };
- };
-
- button_pins: button_pins {
- mux {
- pins = "gpio25";
- function = "gpio";
- drive-strength = <2>;
- bias-pull-up;
- input;
- };
- };
-};
-
-&soc {
- mdio_gpio0: mdio {
- compatible = "virtual,mdio-gpio";
- #address-cells = <1>;
- #size-cells = <0>;
-
- status = "okay";
-
- pinctrl-0 = <&mdio0_pins_active>, <&phy_active>;
- pinctrl-names = "default";
-
- gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH
- &qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
-
- phy0: ethernet-phy0 {
- reg = <0>;
- reset-gpios = <&qcom_pinmux 7 GPIO_ACTIVE_LOW>;
- reset-assert-us = <24000>;
- };
-
- phy4: ethernet-phy4 {
- reg = <4>;
- reset-gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
- reset-assert-us = <24000>;
- };
- };
-};
-
-&wifi0 {
- nvmem-cells = <&mac_address 4>;
- nvmem-cell-names = "mac-address";
-};
-
-&wifi1 {
- nvmem-cells = <&mac_address 3>;
- nvmem-cell-names = "mac-address";
-};
-
-&wifi2 {
- nvmem-cells = <&mac_address 2>;
- nvmem-cell-names = "mac-address";
-};
-
-&hs_phy_0 {
- status = "okay";
-};
-
-&ss_phy_0 {
- status = "okay";
-};
-
-&usb3_0 {
- status = "okay";
-};
-
-&hs_phy_1 {
- status = "okay";
-};
-
-&ss_phy_1 {
- status = "okay";
-};
-
-&usb3_1 {
- status = "okay";
-};
define Device/Default
PROFILES := Default
KERNEL_LOADADDR = 0x42208000
- DEVICE_DTS_DIR = $(if $(CONFIG_TESTING_KERNEL),$$(DTS_DIR)/qcom,$$(DTS_DIR))
+ DEVICE_DTS_DIR = $$(DTS_DIR)/qcom
DEVICE_DTS = $$(SOC)-$(lastword $(subst _, ,$(1)))
DEVICE_DTS_CONFIG := config@1
IMAGES := sysupgrade.bin
+++ /dev/null
-From 09be1a39e685d8c5edd471fd1cac9a8f8280d2de Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Tue, 8 Nov 2022 22:17:34 +0100
-Subject: [PATCH] clk: qcom: kpss-xcc: register it as clk provider
-
-krait-cc use this driver for the secondary mux. Register it as a clk
-provider to correctly use this clk in other drivers.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221108211734.3707-1-ansuelsmth@gmail.com
----
- drivers/clk/qcom/kpss-xcc.c | 13 +++++++++----
- 1 file changed, 9 insertions(+), 4 deletions(-)
-
---- a/drivers/clk/qcom/kpss-xcc.c
-+++ b/drivers/clk/qcom/kpss-xcc.c
-@@ -31,12 +31,13 @@ MODULE_DEVICE_TABLE(of, kpss_xcc_match_t
-
- static int kpss_xcc_driver_probe(struct platform_device *pdev)
- {
-+ struct device *dev = &pdev->dev;
- const struct of_device_id *id;
- void __iomem *base;
- struct clk_hw *hw;
- const char *name;
-
-- id = of_match_device(kpss_xcc_match_table, &pdev->dev);
-+ id = of_match_device(kpss_xcc_match_table, dev);
- if (!id)
- return -ENODEV;
-
-@@ -45,7 +46,7 @@ static int kpss_xcc_driver_probe(struct
- return PTR_ERR(base);
-
- if (id->data) {
-- if (of_property_read_string_index(pdev->dev.of_node,
-+ if (of_property_read_string_index(dev->of_node,
- "clock-output-names",
- 0, &name))
- return -ENODEV;
-@@ -55,12 +56,16 @@ static int kpss_xcc_driver_probe(struct
- base += 0x28;
- }
-
-- hw = devm_clk_hw_register_mux_parent_data_table(&pdev->dev, name, aux_parents,
-+ hw = devm_clk_hw_register_mux_parent_data_table(dev, name, aux_parents,
- ARRAY_SIZE(aux_parents), 0,
- base, 0, 0x3,
- 0, aux_parent_map, NULL);
-+ if (IS_ERR(hw))
-+ return PTR_ERR(hw);
-
-- return PTR_ERR_OR_ZERO(hw);
-+ of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, hw);
-+
-+ return 0;
- }
-
- static struct platform_driver kpss_xcc_driver = {
+++ /dev/null
-From 3198106a99e73dbc4c02bd5128cec0997c73af82 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Tue, 8 Nov 2022 22:58:27 +0100
-Subject: [PATCH 1/6] clk: qcom: krait-cc: use devm variant for clk notifier
- register
-
-Use devm variant for clk notifier register and correctly handle free
-resource on driver remove.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221108215827.30475-1-ansuelsmth@gmail.com
----
- drivers/clk/qcom/krait-cc.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/clk/qcom/krait-cc.c
-+++ b/drivers/clk/qcom/krait-cc.c
-@@ -62,7 +62,7 @@ static int krait_notifier_register(struc
- int ret = 0;
-
- mux->clk_nb.notifier_call = krait_notifier_cb;
-- ret = clk_notifier_register(clk, &mux->clk_nb);
-+ ret = devm_clk_notifier_register(dev, clk, &mux->clk_nb);
- if (ret)
- dev_err(dev, "failed to register clock notifier: %d\n", ret);
-
+++ /dev/null
-From 8e456411abcbf899c04740b9dbb3dcefcd61c946 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Wed, 9 Nov 2022 01:56:27 +0100
-Subject: [PATCH 2/6] clk: qcom: krait-cc: fix wrong parent order for secondary
- mux
-
-The secondary mux parent order is swapped.
-This currently doesn't cause problems as the secondary mux is used for idle
-clk and as a safe clk source while reprogramming the hfpll.
-
-Each mux have 2 or more output but he always have a safe source to
-switch while reprogramming the connected pll. We use a clk notifier to
-switch to the correct parent before clk core can apply the correct rate.
-The parent to switch is hardcoded in the mux struct.
-
-For the secondary mux the safe source to use is the qsb parent as it's
-the only fixed clk as the acpus_aux is a pll that can source from pxo or
-from pll8.
-
-The hardcoded safe parent for the secondary mux is set to index 0 that
-in the secondary mux map is set to 2.
-
-But the index 0 is actually acpu_aux in the parent list.
-
-Fix the swapped parents to correctly handle idle frequency and output a
-sane clk_summary report.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221109005631.3189-1-ansuelsmth@gmail.com
----
- drivers/clk/qcom/krait-cc.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/clk/qcom/krait-cc.c
-+++ b/drivers/clk/qcom/krait-cc.c
-@@ -116,8 +116,8 @@ krait_add_sec_mux(struct device *dev, in
- int ret;
- struct krait_mux_clk *mux;
- static const char *sec_mux_list[] = {
-- "acpu_aux",
- "qsb",
-+ "acpu_aux",
- };
- struct clk_init_data init = {
- .parent_names = sec_mux_list,
+++ /dev/null
-From 18ae57b1e8abee6c453381470f6e18991d2901a8 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Wed, 9 Nov 2022 01:56:28 +0100
-Subject: [PATCH 3/6] clk: qcom: krait-cc: also enable secondary mux and div
- clk
-
-clk-krait ignore any rate change if clk is not flagged as enabled.
-Correctly enable the secondary mux and div clk to correctly change rate
-instead of silently ignoring the request.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221109005631.3189-2-ansuelsmth@gmail.com
----
- drivers/clk/qcom/krait-cc.c | 21 ++++++++++++++++++++-
- 1 file changed, 20 insertions(+), 1 deletion(-)
-
---- a/drivers/clk/qcom/krait-cc.c
-+++ b/drivers/clk/qcom/krait-cc.c
-@@ -80,6 +80,7 @@ krait_add_div(struct device *dev, int id
- };
- const char *p_names[1];
- struct clk *clk;
-+ int cpu;
-
- div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
- if (!div)
-@@ -103,6 +104,17 @@ krait_add_div(struct device *dev, int id
- }
-
- clk = devm_clk_register(dev, &div->hw);
-+ if (IS_ERR(clk))
-+ goto err;
-+
-+ /* clk-krait ignore any rate change if mux is not flagged as enabled */
-+ if (id < 0)
-+ for_each_online_cpu(cpu)
-+ clk_prepare_enable(div->hw.clk);
-+ else
-+ clk_prepare_enable(div->hw.clk);
-+
-+err:
- kfree(p_names[0]);
- kfree(init.name);
-
-@@ -113,7 +125,7 @@ static int
- krait_add_sec_mux(struct device *dev, int id, const char *s,
- unsigned int offset, bool unique_aux)
- {
-- int ret;
-+ int cpu, ret;
- struct krait_mux_clk *mux;
- static const char *sec_mux_list[] = {
- "qsb",
-@@ -165,6 +177,13 @@ krait_add_sec_mux(struct device *dev, in
- if (ret)
- goto unique_aux;
-
-+ /* clk-krait ignore any rate change if mux is not flagged as enabled */
-+ if (id < 0)
-+ for_each_online_cpu(cpu)
-+ clk_prepare_enable(mux->hw.clk);
-+ else
-+ clk_prepare_enable(mux->hw.clk);
-+
- unique_aux:
- if (unique_aux)
- kfree(sec_mux_list[0]);
+++ /dev/null
-From e5dc1a4c01510da8438dddfdf4200b79d73990dc Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Wed, 9 Nov 2022 01:56:29 +0100
-Subject: [PATCH 4/6] clk: qcom: krait-cc: handle secondary mux sourcing out of
- acpu_aux
-
-Some bootloader may leave the system in an even more undefined state
-with the secondary mux of L2 or other cores sourcing out of the acpu_aux
-parent. This results in the clk set to the PXO rate or a PLL8 rate.
-
-The current logic to reset the mux and set them to a defined state only
-handle if the mux are configured to source out of QSB. Change this and
-force a new and defined state if the current clk is lower than the aux
-rate. This way we can handle any wrong configuration where the mux is
-sourcing out of QSB (rate 225MHz, currently set to a virtual rate of 1),
-PXO rate (rate 25MHz) or PLL8 (needs to be configured to run at 384Mhz).
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221109005631.3189-3-ansuelsmth@gmail.com
----
- drivers/clk/qcom/krait-cc.c | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
---- a/drivers/clk/qcom/krait-cc.c
-+++ b/drivers/clk/qcom/krait-cc.c
-@@ -383,8 +383,8 @@ static int krait_cc_probe(struct platfor
- */
- cur_rate = clk_get_rate(l2_pri_mux_clk);
- aux_rate = 384000000;
-- if (cur_rate == 1) {
-- pr_info("L2 @ QSB rate. Forcing new rate.\n");
-+ if (cur_rate < aux_rate) {
-+ pr_info("L2 @ Undefined rate. Forcing new rate.\n");
- cur_rate = aux_rate;
- }
- clk_set_rate(l2_pri_mux_clk, aux_rate);
-@@ -394,8 +394,8 @@ static int krait_cc_probe(struct platfor
- for_each_possible_cpu(cpu) {
- clk = clks[cpu];
- cur_rate = clk_get_rate(clk);
-- if (cur_rate == 1) {
-- pr_info("CPU%d @ QSB rate. Forcing new rate.\n", cpu);
-+ if (cur_rate < aux_rate) {
-+ pr_info("CPU%d @ Undefined rate. Forcing new rate.\n", cpu);
- cur_rate = aux_rate;
- }
-
+++ /dev/null
-From 8ea9fb841a7e528bc8ae79d726ce951dcf7b46e2 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Wed, 9 Nov 2022 01:56:30 +0100
-Subject: [PATCH 5/6] clk: qcom: krait-cc: convert to devm_clk_hw_register
-
-clk_register is now deprecated. Convert the driver to devm_clk_hw_register.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221109005631.3189-4-ansuelsmth@gmail.com
----
- drivers/clk/qcom/krait-cc.c | 31 +++++++++++++++++++------------
- 1 file changed, 19 insertions(+), 12 deletions(-)
-
---- a/drivers/clk/qcom/krait-cc.c
-+++ b/drivers/clk/qcom/krait-cc.c
-@@ -79,8 +79,7 @@ krait_add_div(struct device *dev, int id
- .flags = CLK_SET_RATE_PARENT,
- };
- const char *p_names[1];
-- struct clk *clk;
-- int cpu;
-+ int cpu, ret;
-
- div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
- if (!div)
-@@ -103,8 +102,8 @@ krait_add_div(struct device *dev, int id
- return -ENOMEM;
- }
-
-- clk = devm_clk_register(dev, &div->hw);
-- if (IS_ERR(clk))
-+ ret = devm_clk_hw_register(dev, &div->hw);
-+ if (ret)
- goto err;
-
- /* clk-krait ignore any rate change if mux is not flagged as enabled */
-@@ -118,7 +117,7 @@ err:
- kfree(p_names[0]);
- kfree(init.name);
-
-- return PTR_ERR_OR_ZERO(clk);
-+ return ret;
- }
-
- static int
-@@ -137,7 +136,6 @@ krait_add_sec_mux(struct device *dev, in
- .ops = &krait_mux_clk_ops,
- .flags = CLK_SET_RATE_PARENT,
- };
-- struct clk *clk;
-
- mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
- if (!mux)
-@@ -166,14 +164,16 @@ krait_add_sec_mux(struct device *dev, in
- if (unique_aux) {
- sec_mux_list[0] = kasprintf(GFP_KERNEL, "acpu%s_aux", s);
- if (!sec_mux_list[0]) {
-- clk = ERR_PTR(-ENOMEM);
-+ ret = -ENOMEM;
- goto err_aux;
- }
- }
-
-- clk = devm_clk_register(dev, &mux->hw);
-+ ret = devm_clk_hw_register(dev, &mux->hw);
-+ if (ret)
-+ goto unique_aux;
-
-- ret = krait_notifier_register(dev, clk, mux);
-+ ret = krait_notifier_register(dev, mux->hw.clk, mux);
- if (ret)
- goto unique_aux;
-
-@@ -189,7 +189,7 @@ unique_aux:
- kfree(sec_mux_list[0]);
- err_aux:
- kfree(init.name);
-- return PTR_ERR_OR_ZERO(clk);
-+ return ret;
- }
-
- static struct clk *
-@@ -241,11 +241,18 @@ krait_add_pri_mux(struct device *dev, in
- goto err_p2;
- }
-
-- clk = devm_clk_register(dev, &mux->hw);
-+ ret = devm_clk_hw_register(dev, &mux->hw);
-+ if (ret) {
-+ clk = ERR_PTR(ret);
-+ goto err_p3;
-+ }
-+
-+ clk = mux->hw.clk;
-
- ret = krait_notifier_register(dev, clk, mux);
- if (ret)
-- goto err_p3;
-+ clk = ERR_PTR(ret);
-+
- err_p3:
- kfree(p_names[2]);
- err_p2:
+++ /dev/null
-From 56a655e1c41a86445cf2de656649ad93424b2a63 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Wed, 9 Nov 2022 01:56:31 +0100
-Subject: [PATCH 6/6] clk: qcom: krait-cc: convert to parent_data API
-
-Modernize the krait-cc driver to parent-data API and refactor to drop
-any use of parent_names. From Documentation all the required clocks should
-be declared in DTS so fw_name can be correctly used to get the parents
-for all the muxes. .name is also declared to save compatibility with old
-DT.
-
-While at it also drop some hardcoded index and introduce an enum to make
-index values more clear.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221109005631.3189-5-ansuelsmth@gmail.com
----
- drivers/clk/qcom/krait-cc.c | 202 ++++++++++++++++++++----------------
- 1 file changed, 112 insertions(+), 90 deletions(-)
-
---- a/drivers/clk/qcom/krait-cc.c
-+++ b/drivers/clk/qcom/krait-cc.c
-@@ -15,6 +15,16 @@
-
- #include "clk-krait.h"
-
-+enum {
-+ cpu0_mux = 0,
-+ cpu1_mux,
-+ cpu2_mux,
-+ cpu3_mux,
-+ l2_mux,
-+
-+ clks_max,
-+};
-+
- static unsigned int sec_mux_map[] = {
- 2,
- 0,
-@@ -69,21 +79,23 @@ static int krait_notifier_register(struc
- return ret;
- }
-
--static int
-+static struct clk_hw *
- krait_add_div(struct device *dev, int id, const char *s, unsigned int offset)
- {
- struct krait_div2_clk *div;
-+ static struct clk_parent_data p_data[1];
- struct clk_init_data init = {
-- .num_parents = 1,
-+ .num_parents = ARRAY_SIZE(p_data),
- .ops = &krait_div2_clk_ops,
- .flags = CLK_SET_RATE_PARENT,
- };
-- const char *p_names[1];
-+ struct clk_hw *clk;
-+ char *parent_name;
- int cpu, ret;
-
- div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
- if (!div)
-- return -ENOMEM;
-+ return ERR_PTR(-ENOMEM);
-
- div->width = 2;
- div->shift = 6;
-@@ -93,18 +105,25 @@ krait_add_div(struct device *dev, int id
-
- init.name = kasprintf(GFP_KERNEL, "hfpll%s_div", s);
- if (!init.name)
-- return -ENOMEM;
-+ return ERR_PTR(-ENOMEM);
-
-- init.parent_names = p_names;
-- p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s);
-- if (!p_names[0]) {
-- kfree(init.name);
-- return -ENOMEM;
-+ init.parent_data = p_data;
-+ parent_name = kasprintf(GFP_KERNEL, "hfpll%s", s);
-+ if (!parent_name) {
-+ clk = ERR_PTR(-ENOMEM);
-+ goto err_parent_name;
- }
-
-+ p_data[0].fw_name = parent_name;
-+ p_data[0].name = parent_name;
-+
- ret = devm_clk_hw_register(dev, &div->hw);
-- if (ret)
-- goto err;
-+ if (ret) {
-+ clk = ERR_PTR(ret);
-+ goto err_clk;
-+ }
-+
-+ clk = &div->hw;
-
- /* clk-krait ignore any rate change if mux is not flagged as enabled */
- if (id < 0)
-@@ -113,33 +132,36 @@ krait_add_div(struct device *dev, int id
- else
- clk_prepare_enable(div->hw.clk);
-
--err:
-- kfree(p_names[0]);
-+err_clk:
-+ kfree(parent_name);
-+err_parent_name:
- kfree(init.name);
-
-- return ret;
-+ return clk;
- }
-
--static int
-+static struct clk_hw *
- krait_add_sec_mux(struct device *dev, int id, const char *s,
- unsigned int offset, bool unique_aux)
- {
- int cpu, ret;
- struct krait_mux_clk *mux;
-- static const char *sec_mux_list[] = {
-- "qsb",
-- "acpu_aux",
-+ static struct clk_parent_data sec_mux_list[2] = {
-+ { .name = "qsb", .fw_name = "qsb" },
-+ {},
- };
- struct clk_init_data init = {
-- .parent_names = sec_mux_list,
-+ .parent_data = sec_mux_list,
- .num_parents = ARRAY_SIZE(sec_mux_list),
- .ops = &krait_mux_clk_ops,
- .flags = CLK_SET_RATE_PARENT,
- };
-+ struct clk_hw *clk;
-+ char *parent_name;
-
- mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
- if (!mux)
-- return -ENOMEM;
-+ return ERR_PTR(-ENOMEM);
-
- mux->offset = offset;
- mux->lpl = id >= 0;
-@@ -159,23 +181,33 @@ krait_add_sec_mux(struct device *dev, in
-
- init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
- if (!init.name)
-- return -ENOMEM;
-+ return ERR_PTR(-ENOMEM);
-
- if (unique_aux) {
-- sec_mux_list[0] = kasprintf(GFP_KERNEL, "acpu%s_aux", s);
-- if (!sec_mux_list[0]) {
-- ret = -ENOMEM;
-+ parent_name = kasprintf(GFP_KERNEL, "acpu%s_aux", s);
-+ if (!parent_name) {
-+ clk = ERR_PTR(-ENOMEM);
- goto err_aux;
- }
-+ sec_mux_list[1].fw_name = parent_name;
-+ sec_mux_list[1].name = parent_name;
-+ } else {
-+ sec_mux_list[1].name = "apu_aux";
- }
-
- ret = devm_clk_hw_register(dev, &mux->hw);
-- if (ret)
-- goto unique_aux;
-+ if (ret) {
-+ clk = ERR_PTR(ret);
-+ goto err_clk;
-+ }
-+
-+ clk = &mux->hw;
-
- ret = krait_notifier_register(dev, mux->hw.clk, mux);
-- if (ret)
-- goto unique_aux;
-+ if (ret) {
-+ clk = ERR_PTR(ret);
-+ goto err_clk;
-+ }
-
- /* clk-krait ignore any rate change if mux is not flagged as enabled */
- if (id < 0)
-@@ -184,28 +216,29 @@ krait_add_sec_mux(struct device *dev, in
- else
- clk_prepare_enable(mux->hw.clk);
-
--unique_aux:
-+err_clk:
- if (unique_aux)
-- kfree(sec_mux_list[0]);
-+ kfree(parent_name);
- err_aux:
- kfree(init.name);
-- return ret;
-+ return clk;
- }
-
--static struct clk *
--krait_add_pri_mux(struct device *dev, int id, const char *s,
-- unsigned int offset)
-+static struct clk_hw *
-+krait_add_pri_mux(struct device *dev, struct clk_hw *hfpll_div, struct clk_hw *sec_mux,
-+ int id, const char *s, unsigned int offset)
- {
- int ret;
- struct krait_mux_clk *mux;
-- const char *p_names[3];
-+ static struct clk_parent_data p_data[3];
- struct clk_init_data init = {
-- .parent_names = p_names,
-- .num_parents = ARRAY_SIZE(p_names),
-+ .parent_data = p_data,
-+ .num_parents = ARRAY_SIZE(p_data),
- .ops = &krait_mux_clk_ops,
- .flags = CLK_SET_RATE_PARENT,
- };
-- struct clk *clk;
-+ struct clk_hw *clk;
-+ char *hfpll_name;
-
- mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
- if (!mux)
-@@ -223,55 +256,44 @@ krait_add_pri_mux(struct device *dev, in
- if (!init.name)
- return ERR_PTR(-ENOMEM);
-
-- p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s);
-- if (!p_names[0]) {
-+ hfpll_name = kasprintf(GFP_KERNEL, "hfpll%s", s);
-+ if (!hfpll_name) {
- clk = ERR_PTR(-ENOMEM);
-- goto err_p0;
-+ goto err_hfpll;
- }
-
-- p_names[1] = kasprintf(GFP_KERNEL, "hfpll%s_div", s);
-- if (!p_names[1]) {
-- clk = ERR_PTR(-ENOMEM);
-- goto err_p1;
-- }
-+ p_data[0].fw_name = hfpll_name;
-+ p_data[0].name = hfpll_name;
-
-- p_names[2] = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
-- if (!p_names[2]) {
-- clk = ERR_PTR(-ENOMEM);
-- goto err_p2;
-- }
-+ p_data[1].hw = hfpll_div;
-+ p_data[2].hw = sec_mux;
-
- ret = devm_clk_hw_register(dev, &mux->hw);
- if (ret) {
- clk = ERR_PTR(ret);
-- goto err_p3;
-+ goto err_clk;
- }
-
-- clk = mux->hw.clk;
-+ clk = &mux->hw;
-
-- ret = krait_notifier_register(dev, clk, mux);
-+ ret = krait_notifier_register(dev, mux->hw.clk, mux);
- if (ret)
- clk = ERR_PTR(ret);
-
--err_p3:
-- kfree(p_names[2]);
--err_p2:
-- kfree(p_names[1]);
--err_p1:
-- kfree(p_names[0]);
--err_p0:
-+err_clk:
-+ kfree(hfpll_name);
-+err_hfpll:
- kfree(init.name);
- return clk;
- }
-
- /* id < 0 for L2, otherwise id == physical CPU number */
--static struct clk *krait_add_clks(struct device *dev, int id, bool unique_aux)
-+static struct clk_hw *krait_add_clks(struct device *dev, int id, bool unique_aux)
- {
-- int ret;
-+ struct clk_hw *hfpll_div, *sec_mux, *pri_mux;
- unsigned int offset;
- void *p = NULL;
- const char *s;
-- struct clk *clk;
-
- if (id >= 0) {
- offset = 0x4501 + (0x1000 * id);
-@@ -283,22 +305,23 @@ static struct clk *krait_add_clks(struct
- s = "_l2";
- }
-
-- ret = krait_add_div(dev, id, s, offset);
-- if (ret) {
-- clk = ERR_PTR(ret);
-+ hfpll_div = krait_add_div(dev, id, s, offset);
-+ if (IS_ERR(hfpll_div)) {
-+ pri_mux = hfpll_div;
- goto err;
- }
-
-- ret = krait_add_sec_mux(dev, id, s, offset, unique_aux);
-- if (ret) {
-- clk = ERR_PTR(ret);
-+ sec_mux = krait_add_sec_mux(dev, id, s, offset, unique_aux);
-+ if (IS_ERR(sec_mux)) {
-+ pri_mux = sec_mux;
- goto err;
- }
-
-- clk = krait_add_pri_mux(dev, id, s, offset);
-+ pri_mux = krait_add_pri_mux(dev, hfpll_div, sec_mux, id, s, offset);
-+
- err:
- kfree(p);
-- return clk;
-+ return pri_mux;
- }
-
- static struct clk *krait_of_get(struct of_phandle_args *clkspec, void *data)
-@@ -306,7 +329,7 @@ static struct clk *krait_of_get(struct o
- unsigned int idx = clkspec->args[0];
- struct clk **clks = data;
-
-- if (idx >= 5) {
-+ if (idx >= clks_max) {
- pr_err("%s: invalid clock index %d\n", __func__, idx);
- return ERR_PTR(-EINVAL);
- }
-@@ -327,9 +350,8 @@ static int krait_cc_probe(struct platfor
- const struct of_device_id *id;
- unsigned long cur_rate, aux_rate;
- int cpu;
-- struct clk *clk;
-- struct clk **clks;
-- struct clk *l2_pri_mux_clk;
-+ struct clk_hw *mux, *l2_pri_mux;
-+ struct clk *clk, **clks;
-
- id = of_match_device(krait_cc_match_table, dev);
- if (!id)
-@@ -348,21 +370,21 @@ static int krait_cc_probe(struct platfor
- }
-
- /* Krait configurations have at most 4 CPUs and one L2 */
-- clks = devm_kcalloc(dev, 5, sizeof(*clks), GFP_KERNEL);
-+ clks = devm_kcalloc(dev, clks_max, sizeof(*clks), GFP_KERNEL);
- if (!clks)
- return -ENOMEM;
-
- for_each_possible_cpu(cpu) {
-- clk = krait_add_clks(dev, cpu, id->data);
-+ mux = krait_add_clks(dev, cpu, id->data);
- if (IS_ERR(clk))
- return PTR_ERR(clk);
-- clks[cpu] = clk;
-+ clks[cpu] = mux->clk;
- }
-
-- l2_pri_mux_clk = krait_add_clks(dev, -1, id->data);
-- if (IS_ERR(l2_pri_mux_clk))
-- return PTR_ERR(l2_pri_mux_clk);
-- clks[4] = l2_pri_mux_clk;
-+ l2_pri_mux = krait_add_clks(dev, -1, id->data);
-+ if (IS_ERR(l2_pri_mux))
-+ return PTR_ERR(l2_pri_mux);
-+ clks[l2_mux] = l2_pri_mux->clk;
-
- /*
- * We don't want the CPU or L2 clocks to be turned off at late init
-@@ -372,7 +394,7 @@ static int krait_cc_probe(struct platfor
- * they take over.
- */
- for_each_online_cpu(cpu) {
-- clk_prepare_enable(l2_pri_mux_clk);
-+ clk_prepare_enable(clks[l2_mux]);
- WARN(clk_prepare_enable(clks[cpu]),
- "Unable to turn on CPU%d clock", cpu);
- }
-@@ -388,16 +410,16 @@ static int krait_cc_probe(struct platfor
- * two different rates to force a HFPLL reinit under all
- * circumstances.
- */
-- cur_rate = clk_get_rate(l2_pri_mux_clk);
-+ cur_rate = clk_get_rate(clks[l2_mux]);
- aux_rate = 384000000;
- if (cur_rate < aux_rate) {
- pr_info("L2 @ Undefined rate. Forcing new rate.\n");
- cur_rate = aux_rate;
- }
-- clk_set_rate(l2_pri_mux_clk, aux_rate);
-- clk_set_rate(l2_pri_mux_clk, 2);
-- clk_set_rate(l2_pri_mux_clk, cur_rate);
-- pr_info("L2 @ %lu KHz\n", clk_get_rate(l2_pri_mux_clk) / 1000);
-+ clk_set_rate(clks[l2_mux], aux_rate);
-+ clk_set_rate(clks[l2_mux], 2);
-+ clk_set_rate(clks[l2_mux], cur_rate);
-+ pr_info("L2 @ %lu KHz\n", clk_get_rate(clks[l2_mux]) / 1000);
- for_each_possible_cpu(cpu) {
- clk = clks[cpu];
- cur_rate = clk_get_rate(clk);
+++ /dev/null
-From c9713e4ede1e5d044b64fe4d3cbb84223625637f Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Tue, 25 Oct 2022 01:38:17 +0200
-Subject: [PATCH] ARM: dts: qcom: ipq8064: disable mmc-ddr-1_8v for sdcc1
-
-It was reported non working mmc with this option enabled.
-Both mmc for ipq8064 are supplied by a fixed 3.3v regulator so mmc can't
-be run at 1.8v.
-Disable it to restore correct functionality of this SoC feature.
-
-Tested-by: Hendrik Koerner <koerhen@web.de>
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221024233817.27410-1-ansuelsmth@gmail.com
----
- arch/arm/boot/dts/qcom-ipq8064.dtsi | 1 -
- 1 file changed, 1 deletion(-)
-
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -756,7 +756,6 @@
- non-removable;
- cap-sd-highspeed;
- cap-mmc-highspeed;
-- mmc-ddr-1_8v;
- vmmc-supply = <&vsdcc_fixed>;
- dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
- dma-names = "tx", "rx";
+++ /dev/null
-From de48d8766afcd97d147699aaff78a338081c9973 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Sat, 22 Oct 2022 14:56:55 +0200
-Subject: [PATCH 1/3] thermal/drivers/qcom/tsens: Init debugfs only with
- successful probe
-
-Calibrate and tsens_register can fail or PROBE_DEFER. This will cause a
-double or a wrong init of the debugfs information. Init debugfs only
-with successful probe fixing warning about directory already present.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Acked-by: Thara Gopinath <thara.gopinath@linaro.org>
-Link: https://lore.kernel.org/r/20221022125657.22530-2-ansuelsmth@gmail.com
-Signed-off-by: Daniel Lezcano <daniel.lezcano@kernel.org>
----
- drivers/thermal/qcom/tsens.c | 8 +++++---
- 1 file changed, 5 insertions(+), 3 deletions(-)
-
---- a/drivers/thermal/qcom/tsens.c
-+++ b/drivers/thermal/qcom/tsens.c
-@@ -918,8 +918,6 @@ int __init init_common(struct tsens_priv
- if (tsens_version(priv) >= VER_0_1)
- tsens_enable_irq(priv);
-
-- tsens_debug_init(op);
--
- err_put_device:
- put_device(&op->dev);
- return ret;
-@@ -1156,7 +1154,11 @@ static int tsens_probe(struct platform_d
- }
- }
-
-- return tsens_register(priv);
-+ ret = tsens_register(priv);
-+ if (!ret)
-+ tsens_debug_init(pdev);
-+
-+ return ret;
- }
-
- static int tsens_remove(struct platform_device *pdev)
+++ /dev/null
-From c7e077e921fa94e0c06c8d14af6c0504c8a5f4bd Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Sat, 22 Oct 2022 14:56:56 +0200
-Subject: [PATCH 2/3] thermal/drivers/qcom/tsens: Fix wrong version id
- dbg_version_show
-
-For VER_0 the version was incorrectly reported as 0.1.0.
-
-Fix that and correctly report the major version for this old tsens
-revision.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Link: https://lore.kernel.org/r/20221022125657.22530-3-ansuelsmth@gmail.com
-Signed-off-by: Daniel Lezcano <daniel.lezcano@kernel.org>
----
- drivers/thermal/qcom/tsens.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/thermal/qcom/tsens.c
-+++ b/drivers/thermal/qcom/tsens.c
-@@ -692,7 +692,7 @@ static int dbg_version_show(struct seq_f
- return ret;
- seq_printf(s, "%d.%d.%d\n", maj_ver, min_ver, step_ver);
- } else {
-- seq_puts(s, "0.1.0\n");
-+ seq_printf(s, "0.%d.0\n", priv->feat->ver_major);
- }
-
- return 0;
+++ /dev/null
-From 89992d95ed1046338c7866ef7bbe6de543a2af91 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Sat, 22 Oct 2022 14:56:57 +0200
-Subject: [PATCH 3/3] thermal/drivers/qcom/tsens: Rework debugfs file structure
-
-The current tsens debugfs structure is composed by:
-- a tsens dir in debugfs with a version file
-- a directory for each tsens istance with sensors file to dump all the
- sensors value.
-
-This works on the assumption that we have the same version for each
-istance but this assumption seems fragile and with more than one tsens
-istance results in the version file not tracking each of them.
-
-A better approach is to just create a subdirectory for each tsens
-istance and put there version and sensors debugfs file.
-
-Using this new implementation results in less code since debugfs entry
-are created only on successful tsens probe.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Link: https://lore.kernel.org/r/20221022125657.22530-4-ansuelsmth@gmail.com
-Signed-off-by: Daniel Lezcano <daniel.lezcano@kernel.org>
----
- drivers/thermal/qcom/tsens.c | 13 +++----------
- 1 file changed, 3 insertions(+), 10 deletions(-)
-
---- a/drivers/thermal/qcom/tsens.c
-+++ b/drivers/thermal/qcom/tsens.c
-@@ -704,21 +704,14 @@ DEFINE_SHOW_ATTRIBUTE(dbg_sensors);
- static void tsens_debug_init(struct platform_device *pdev)
- {
- struct tsens_priv *priv = platform_get_drvdata(pdev);
-- struct dentry *root, *file;
-
-- root = debugfs_lookup("tsens", NULL);
-- if (!root)
-+ priv->debug_root = debugfs_lookup("tsens", NULL);
-+ if (!priv->debug_root)
- priv->debug_root = debugfs_create_dir("tsens", NULL);
-- else
-- priv->debug_root = root;
--
-- file = debugfs_lookup("version", priv->debug_root);
-- if (!file)
-- debugfs_create_file("version", 0444, priv->debug_root,
-- pdev, &dbg_version_fops);
-
- /* A directory for each instance of the TSENS IP */
- priv->debug = debugfs_create_dir(dev_name(&pdev->dev), priv->debug_root);
-+ debugfs_create_file("version", 0444, priv->debug, pdev, &dbg_version_fops);
- debugfs_create_file("sensors", 0444, priv->debug, pdev, &dbg_sensors_fops);
- }
- #else
+++ /dev/null
-From 5001f2e1a325b68dbf225bd17f69a4d3d975cca5 Mon Sep 17 00:00:00 2001
-From: John Crispin <john@phrozen.org>
-Date: Thu, 9 Mar 2017 09:31:44 +0100
-Subject: [PATCH 61/69] mtd: "rootfs" conflicts with OpenWrt auto mounting
-
-Signed-off-by: John Crispin <john@phrozen.org>
----
- drivers/mtd/mtdpart.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/drivers/mtd/mtdpart.c
-+++ b/drivers/mtd/mtdpart.c
-@@ -51,7 +51,11 @@ static struct mtd_info *allocate_partiti
-
- /* allocate the partition structure */
- child = kzalloc(sizeof(*child), GFP_KERNEL);
-- name = kstrdup(part->name, GFP_KERNEL);
-+ /* "rootfs" conflicts with OpenWrt auto mounting */
-+ if (mtd_type_is_nand(parent) && !strcmp(part->name, "rootfs"))
-+ name = "ubi";
-+ else
-+ name = kstrdup(part->name, GFP_KERNEL);
- if (!name || !child) {
- printk(KERN_ERR"memory allocation error while creating partitions for \"%s\"\n",
- parent->name);
+++ /dev/null
-From bef5018abb7cf94efafdc05087b4c998891ae4ec Mon Sep 17 00:00:00 2001
-From: Ansuel Smith <ansuelsmth@gmail.com>
-Date: Mon, 17 Jan 2022 23:39:34 +0100
-Subject: [PATCH v3 10/18] ARM: dts: qcom: add saw for l2 cache and kraitcc for
- ipq8064
-
-Add saw compatible for l2 cache and kraitcc node for ipq8064 dtsi.
-Also declare clock-output-names for acc0 and acc1 and qsb fixed clock
-for the secondary mux.
-
-Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
-Tested-by: Jonathan McDowell <noodles@earth.li>
----
- arch/arm/boot/dts/qcom-ipq8064.dtsi | 34 +++++++++++++++++++++++++++--
- 1 file changed, 32 insertions(+), 2 deletions(-)
-
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -301,6 +301,12 @@
- };
-
- clocks {
-+ qsb: qsb {
-+ compatible = "fixed-clock";
-+ clock-frequency = <225000000>;
-+ #clock-cells = <0>;
-+ };
-+
- cxo_board: cxo_board {
- compatible = "fixed-clock";
- #clock-cells = <0>;
-@@ -575,15 +581,30 @@
- clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
- clock-names = "pll8_vote", "pxo";
- clock-output-names = "acpu_l2_aux";
-+ #clock-cells = <0>;
-+ };
-+
-+ kraitcc: clock-controller {
-+ compatible = "qcom,krait-cc-v1";
-+ clocks = <&gcc PLL9>, <&gcc PLL10>, <&gcc PLL12>,
-+ <&acc0>, <&acc1>, <&l2cc>, <&qsb>, <&pxo_board>;
-+ clock-names = "hfpll0", "hfpll1", "hfpll_l2",
-+ "acpu0_aux", "acpu1_aux", "acpu_l2_aux",
-+ "qsb", "pxo";
-+ #clock-cells = <1>;
- };
-
- acc0: clock-controller@2088000 {
- compatible = "qcom,kpss-acc-v1";
- reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
-+ clock-output-names = "acpu0_aux";
-+ clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
-+ clock-names = "pll8_vote", "pxo";
-+ #clock-cells = <0>;
- };
-
- saw0: regulator@2089000 {
-- compatible = "qcom,saw2";
-+ compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
- reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
- regulator;
- };
-@@ -591,14 +612,24 @@
- acc1: clock-controller@2098000 {
- compatible = "qcom,kpss-acc-v1";
- reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
-+ clock-output-names = "acpu1_aux";
-+ clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
-+ clock-names = "pll8_vote", "pxo";
-+ #clock-cells = <0>;
- };
-
- saw1: regulator@2099000 {
-- compatible = "qcom,saw2";
-+ compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
- reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
- regulator;
- };
-
-+ saw_l2: regulator@02012000 {
-+ compatible = "qcom,saw2", "syscon";
-+ reg = <0x02012000 0x1000>;
-+ regulator;
-+ };
-+
- nss_common: syscon@03000000 {
- compatible = "syscon";
- reg = <0x03000000 0x0000FFFF>;
+++ /dev/null
-From 076ebb6e1799c4c7a1d2e07510d88b9e9b57b551 Mon Sep 17 00:00:00 2001
-From: Ansuel Smith <ansuelsmth@gmail.com>
-Date: Tue, 18 Jan 2022 00:03:47 +0100
-Subject: [PATCH v3 13/18] ARM: dts: qcom: add opp table for cpu and l2 for
- ipq8064
-
-Add opp table for cpu and l2 cache. While the current cpufreq is
-the generic one that doesn't scale the L2 cache, we add the l2
-cache opp anyway for the sake of completeness. This will be handy in the
-future when a dedicated cpufreq driver is introduced for krait cores
-that will correctly scale l2 cache with the core freq.
-
-Opp-level is set based on the logic of
-0: idle level
-1: normal level
-2: turbo level
-
-Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
-Tested-by: Jonathan McDowell <noodles@earth.li>
----
- arch/arm/boot/dts/qcom-ipq8064.dtsi | 99 +++++++++++++++++++++++++++++
- 1 file changed, 99 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -48,6 +48,105 @@
- };
- };
-
-+ opp_table_l2: opp_table_l2 {
-+ compatible = "operating-points-v2";
-+
-+ opp-384000000 {
-+ opp-hz = /bits/ 64 <384000000>;
-+ opp-microvolt = <1100000>;
-+ clock-latency-ns = <100000>;
-+ opp-level = <0>;
-+ };
-+
-+ opp-1000000000 {
-+ opp-hz = /bits/ 64 <1000000000>;
-+ opp-microvolt = <1100000>;
-+ clock-latency-ns = <100000>;
-+ opp-level = <1>;
-+ };
-+
-+ opp-1200000000 {
-+ opp-hz = /bits/ 64 <1200000000>;
-+ opp-microvolt = <1150000>;
-+ clock-latency-ns = <100000>;
-+ opp-level = <2>;
-+ };
-+ };
-+
-+ opp_table0: opp_table0 {
-+ compatible = "operating-points-v2-kryo-cpu";
-+ nvmem-cells = <&speedbin_efuse>;
-+
-+ /*
-+ * Voltage thresholds are <target min max>
-+ */
-+ opp-384000000 {
-+ opp-hz = /bits/ 64 <384000000>;
-+ opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;
-+ opp-microvolt-speed0-pvs1-v0 = <925000 878750 971250>;
-+ opp-microvolt-speed0-pvs2-v0 = <875000 831250 918750>;
-+ opp-microvolt-speed0-pvs3-v0 = <800000 760000 840000>;
-+ opp-supported-hw = <0x1>;
-+ clock-latency-ns = <100000>;
-+ opp-level = <0>;
-+ };
-+
-+ opp-600000000 {
-+ opp-hz = /bits/ 64 <600000000>;
-+ opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;
-+ opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>;
-+ opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>;
-+ opp-microvolt-speed0-pvs3-v0 = <850000 807500 892500>;
-+ opp-supported-hw = <0x1>;
-+ clock-latency-ns = <100000>;
-+ opp-level = <1>;
-+ };
-+
-+ opp-800000000 {
-+ opp-hz = /bits/ 64 <800000000>;
-+ opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;
-+ opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>;
-+ opp-microvolt-speed0-pvs2-v0 = <995000 945250 1044750>;
-+ opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>;
-+ opp-supported-hw = <0x1>;
-+ clock-latency-ns = <100000>;
-+ opp-level = <1>;
-+ };
-+
-+ opp-1000000000 {
-+ opp-hz = /bits/ 64 <1000000000>;
-+ opp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>;
-+ opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;
-+ opp-microvolt-speed0-pvs2-v0 = <1025000 973750 1076250>;
-+ opp-microvolt-speed0-pvs3-v0 = <950000 902500 997500>;
-+ opp-supported-hw = <0x1>;
-+ clock-latency-ns = <100000>;
-+ opp-level = <1>;
-+ };
-+
-+ opp-1200000000 {
-+ opp-hz = /bits/ 64 <1200000000>;
-+ opp-microvolt-speed0-pvs0-v0 = <1200000 1140000 1260000>;
-+ opp-microvolt-speed0-pvs1-v0 = <1125000 1068750 1181250>;
-+ opp-microvolt-speed0-pvs2-v0 = <1075000 1021250 1128750>;
-+ opp-microvolt-speed0-pvs3-v0 = <1000000 950000 1050000>;
-+ opp-supported-hw = <0x1>;
-+ clock-latency-ns = <100000>;
-+ opp-level = <2>;
-+ };
-+
-+ opp-1400000000 {
-+ opp-hz = /bits/ 64 <1400000000>;
-+ opp-microvolt-speed0-pvs0-v0 = <1250000 1187500 1312500>;
-+ opp-microvolt-speed0-pvs1-v0 = <1175000 1116250 1233750>;
-+ opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>;
-+ opp-microvolt-speed0-pvs3-v0 = <1050000 997500 1102500>;
-+ opp-supported-hw = <0x1>;
-+ clock-latency-ns = <100000>;
-+ opp-level = <2>;
-+ };
-+ };
-+
- thermal-zones {
- sensor0-thermal {
- polling-delay-passive = <0>;
---- a/arch/arm/boot/dts/qcom-ipq8065.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8065.dtsi
-@@ -6,3 +6,92 @@
- model = "Qualcomm Technologies, Inc. IPQ8065";
- compatible = "qcom,ipq8065", "qcom,ipq8064";
- };
-+
-+&opp_table_l2 {
-+ /delete-node/opp-1200000000;
-+
-+ opp-1400000000 {
-+ opp-hz = /bits/ 64 <1400000000>;
-+ opp-microvolt = <1150000>;
-+ clock-latency-ns = <100000>;
-+ opp-level = <2>;
-+ };
-+};
-+
-+&opp_table0 {
-+ /*
-+ * On ipq8065 1.2 ghz freq is not present
-+ * Remove it to make cpufreq work and not
-+ * complain for missing definition
-+ */
-+
-+ /delete-node/opp-1200000000;
-+
-+ /*
-+ * Voltage thresholds are <target min max>
-+ */
-+ opp-384000000 {
-+ opp-microvolt-speed0-pvs0-v0 = <975000 926250 1023750>;
-+ opp-microvolt-speed0-pvs1-v0 = <950000 902500 997500>;
-+ opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>;
-+ opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>;
-+ opp-microvolt-speed0-pvs4-v0 = <875000 831250 918750>;
-+ opp-microvolt-speed0-pvs5-v0 = <825000 783750 866250>;
-+ opp-microvolt-speed0-pvs6-v0 = <775000 736250 813750>;
-+ };
-+
-+ opp-600000000 {
-+ opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;
-+ opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>;
-+ opp-microvolt-speed0-pvs2-v0 = <950000 902500 997500>;
-+ opp-microvolt-speed0-pvs3-v0 = <925000 878750 971250>;
-+ opp-microvolt-speed0-pvs4-v0 = <900000 855000 945000>;
-+ opp-microvolt-speed0-pvs5-v0 = <850000 807500 892500>;
-+ opp-microvolt-speed0-pvs6-v0 = <800000 760000 840000>;
-+ };
-+
-+ opp-800000000 {
-+ opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;
-+ opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>;
-+ opp-microvolt-speed0-pvs2-v0 = <1000000 950000 1050000>;
-+ opp-microvolt-speed0-pvs3-v0 = <975000 926250 1023750>;
-+ opp-microvolt-speed0-pvs4-v0 = <950000 902500 997500>;
-+ opp-microvolt-speed0-pvs5-v0 = <900000 855000 945000>;
-+ opp-microvolt-speed0-pvs6-v0 = <850000 807500 892500>;
-+ };
-+
-+ opp-1000000000 {
-+ opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;
-+ opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;
-+ opp-microvolt-speed0-pvs2-v0 = <1050000 997500 1102500>;
-+ opp-microvolt-speed0-pvs3-v0 = <1025000 973750 1076250>;
-+ opp-microvolt-speed0-pvs4-v0 = <1000000 950000 1050000>;
-+ opp-microvolt-speed0-pvs5-v0 = <950000 902500 997500>;
-+ opp-microvolt-speed0-pvs6-v0 = <900000 855000 945000>;
-+ };
-+
-+ opp-1400000000 {
-+ opp-microvolt-speed0-pvs0-v0 = <1175000 1116250 1233750>;
-+ opp-microvolt-speed0-pvs1-v0 = <1150000 1092500 1207500>;
-+ opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>;
-+ opp-microvolt-speed0-pvs3-v0 = <1100000 1045000 1155000>;
-+ opp-microvolt-speed0-pvs4-v0 = <1075000 1021250 1128750>;
-+ opp-microvolt-speed0-pvs5-v0 = <1025000 973750 1076250>;
-+ opp-microvolt-speed0-pvs6-v0 = <975000 926250 1023750>;
-+ opp-level = <1>;
-+ };
-+
-+ opp-1725000000 {
-+ opp-hz = /bits/ 64 <1725000000>;
-+ opp-microvolt-speed0-pvs0-v0 = <1262500 1199375 1325625>;
-+ opp-microvolt-speed0-pvs1-v0 = <1225000 1163750 1286250>;
-+ opp-microvolt-speed0-pvs2-v0 = <1200000 1140000 1260000>;
-+ opp-microvolt-speed0-pvs3-v0 = <1175000 1116250 1233750>;
-+ opp-microvolt-speed0-pvs4-v0 = <1150000 1092500 1207500>;
-+ opp-microvolt-speed0-pvs5-v0 = <1100000 1045000 1155000>;
-+ opp-microvolt-speed0-pvs6-v0 = <1050000 997500 1102500>;
-+ opp-supported-hw = <0x1>;
-+ clock-latency-ns = <100000>;
-+ opp-level = <2>;
-+ };
-+};
---- a/arch/arm/boot/dts/qcom-ipq8062.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8062.dtsi
-@@ -6,3 +6,39 @@
- model = "Qualcomm Technologies, Inc. IPQ8062";
- compatible = "qcom,ipq8062", "qcom,ipq8064";
- };
-+
-+&opp_table0 {
-+ /delete-node/opp-1200000000;
-+ /delete-node/opp-1400000000;
-+
-+ /*
-+ * Voltage thresholds are <target min max>
-+ */
-+ opp-384000000 {
-+ opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;
-+ opp-microvolt-speed0-pvs1-v0 = < 925000 878750 971250>;
-+ opp-microvolt-speed0-pvs2-v0 = < 875000 831250 918750>;
-+ opp-microvolt-speed0-pvs3-v0 = < 800000 760000 840000>;
-+ };
-+
-+ opp-600000000 {
-+ opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;
-+ opp-microvolt-speed0-pvs1-v0 = < 975000 926250 1023750>;
-+ opp-microvolt-speed0-pvs2-v0 = < 925000 878750 971250>;
-+ opp-microvolt-speed0-pvs3-v0 = < 850000 807500 892500>;
-+ };
-+
-+ opp-800000000 {
-+ opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;
-+ opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>;
-+ opp-microvolt-speed0-pvs2-v0 = < 995000 945250 1044750>;
-+ opp-microvolt-speed0-pvs3-v0 = < 900000 855000 945000>;
-+ };
-+
-+ opp-1000000000 {
-+ opp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>;
-+ opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;
-+ opp-microvolt-speed0-pvs2-v0 = <1025000 973750 1076250>;
-+ opp-microvolt-speed0-pvs3-v0 = < 950000 902500 997500>;
-+ };
-+};
+++ /dev/null
-From 211fc0c0a63c99b68663a27182e643316c2d8cbe Mon Sep 17 00:00:00 2001
-From: Ansuel Smith <ansuelsmth@gmail.com>
-Date: Tue, 18 Jan 2022 00:07:57 +0100
-Subject: [PATCH v3 15/18] ARM: dts: qcom: add multiple missing binding for cpu
- and l2 for ipq8064
-
-Add multiple binding for cpu node, l2 node and add idle-states
-definition for ipq8064 dtsi.
-
-Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
-Tested-by: Jonathan McDowell <noodles@earth.li>
----
- arch/arm/boot/dts/qcom-ipq8064.dtsi | 36 +++++++++++++++++++++++++++++
- 1 file changed, 36 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -30,6 +30,15 @@
- next-level-cache = <&L2>;
- qcom,acc = <&acc0>;
- qcom,saw = <&saw0>;
-+ clocks = <&kraitcc 0>, <&kraitcc 4>;
-+ clock-names = "cpu", "l2";
-+ clock-latency = <100000>;
-+ operating-points-v2 = <&opp_table0>;
-+ voltage-tolerance = <5>;
-+ cooling-min-state = <0>;
-+ cooling-max-state = <10>;
-+ #cooling-cells = <2>;
-+ cpu-idle-states = <&CPU_SPC>;
- };
-
- cpu1: cpu@1 {
-@@ -40,11 +49,35 @@
- next-level-cache = <&L2>;
- qcom,acc = <&acc1>;
- qcom,saw = <&saw1>;
-+ clocks = <&kraitcc 1>, <&kraitcc 4>;
-+ clock-names = "cpu", "l2";
-+ clock-latency = <100000>;
-+ operating-points-v2 = <&opp_table0>;
-+ voltage-tolerance = <5>;
-+ cooling-min-state = <0>;
-+ cooling-max-state = <10>;
-+ #cooling-cells = <2>;
-+ cpu-idle-states = <&CPU_SPC>;
-+ };
-+
-+ idle-states {
-+ CPU_SPC: spc {
-+ compatible = "qcom,idle-state-spc";
-+ status = "disabled";
-+ entry-latency-us = <400>;
-+ exit-latency-us = <900>;
-+ min-residency-us = <3000>;
-+ };
- };
-
- L2: l2-cache {
- compatible = "cache";
- cache-level = <2>;
-+ qcom,saw = <&saw_l2>;
-+
-+ clocks = <&kraitcc 4>;
-+ clock-names = "l2";
-+ operating-points-v2 = <&opp_table_l2>;
- };
- };
-
---- a/arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi
-@@ -2,6 +2,18 @@
-
- #include "qcom-ipq8064.dtsi"
-
-+&cpu0 {
-+ cpu-supply = <&smb208_s2a>;
-+};
-+
-+&cpu1 {
-+ cpu-supply = <&smb208_s2b>;
-+};
-+
-+&L2 {
-+ l2-supply = <&smb208_s1a>;
-+};
-+
- &rpm {
- smb208_regulators: regulators {
- compatible = "qcom,rpm-smb208-regulators";
---- a/arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi
-@@ -2,6 +2,18 @@
-
- #include "qcom-ipq8064-v2.0.dtsi"
-
-+&cpu0 {
-+ cpu-supply = <&smb208_s2a>;
-+};
-+
-+&cpu1 {
-+ cpu-supply = <&smb208_s2b>;
-+};
-+
-+&L2 {
-+ l2-supply = <&smb208_s1a>;
-+};
-+
- &rpm {
- smb208_regulators: regulators {
- compatible = "qcom,rpm-smb208-regulators";
---- a/arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi
-@@ -2,6 +2,18 @@
-
- #include "qcom-ipq8062.dtsi"
-
-+&cpu0 {
-+ cpu-supply = <&smb208_s2a>;
-+};
-+
-+&cpu1 {
-+ cpu-supply = <&smb208_s2b>;
-+};
-+
-+&L2 {
-+ l2-supply = <&smb208_s1a>;
-+};
-+
- &rpm {
- smb208_regulators: regulators {
- compatible = "qcom,rpm-smb208-regulators";
---- a/arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi
-@@ -2,6 +2,18 @@
-
- #include "qcom-ipq8065.dtsi"
-
-+&cpu0 {
-+ cpu-supply = <&smb208_s2a>;
-+};
-+
-+&cpu1 {
-+ cpu-supply = <&smb208_s2b>;
-+};
-+
-+&L2 {
-+ l2-supply = <&smb208_s1a>;
-+};
-+
- &rpm {
- smb208_regulators: regulators {
- compatible = "qcom,rpm-smb208-regulators";
+++ /dev/null
-From 6c94e0184e56f9e9f1f5d5f54b20758433e498d2 Mon Sep 17 00:00:00 2001
-From: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
-Date: Wed, 15 Jun 2022 16:47:09 +0200
-Subject: [PATCH 1/2] ARM: dts: qcom: fix wrong nad_pins definition for ipq806x
-
-Fix wrong nand_pings definition for bias-disable pins.
-
-Signed-off-by: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
----
- arch/arm/boot/dts/qcom-ipq8064.dtsi | 7 ++-----
- 1 file changed, 2 insertions(+), 5 deletions(-)
-
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -599,12 +599,9 @@
- };
-
- nand_pins: nand_pins {
-- mux {
-+ disable {
- pins = "gpio34", "gpio35", "gpio36",
-- "gpio37", "gpio38", "gpio39",
-- "gpio40", "gpio41", "gpio42",
-- "gpio43", "gpio44", "gpio45",
-- "gpio46", "gpio47";
-+ "gpio37", "gpio38";
- function = "nand";
- drive-strength = <10>;
- bias-disable;
+++ /dev/null
-From 504188183408fac0f61b59f5ed8ea1773fe43669 Mon Sep 17 00:00:00 2001
-From: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
-Date: Wed, 15 Jun 2022 16:59:30 +0200
-Subject: [PATCH 2/2] ARM: dts: qcom: add MDIO dedicated controller node for
- ipq806x
-
-Add MDIO dedicated controller attached to gmac0 and fix rb3011 dts to
-correctly use the new tag.
-
-Signed-off-by: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
----
- arch/arm/boot/dts/qcom-ipq8064-rb3011.dts | 134 +++++++++++-----------
- arch/arm/boot/dts/qcom-ipq8064.dtsi | 14 +++
- 2 files changed, 81 insertions(+), 67 deletions(-)
-
---- a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
-+++ b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
-@@ -25,73 +25,6 @@
- device_type = "memory";
- };
-
-- mdio0: mdio-0 {
-- status = "okay";
-- compatible = "virtual,mdio-gpio";
-- gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>,
-- <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
-- #address-cells = <1>;
-- #size-cells = <0>;
--
-- pinctrl-0 = <&mdio0_pins>;
-- pinctrl-names = "default";
--
-- switch0: switch@10 {
-- compatible = "qca,qca8337";
-- #address-cells = <1>;
-- #size-cells = <0>;
--
-- dsa,member = <0 0>;
--
-- pinctrl-0 = <&sw0_reset_pin>;
-- pinctrl-names = "default";
--
-- reset-gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;
-- reg = <0x10>;
--
-- ports {
-- #address-cells = <1>;
-- #size-cells = <0>;
--
-- switch0cpu: port@0 {
-- reg = <0>;
-- label = "cpu";
-- ethernet = <&gmac0>;
-- phy-mode = "rgmii-id";
-- fixed-link {
-- speed = <1000>;
-- full-duplex;
-- };
-- };
--
-- port@1 {
-- reg = <1>;
-- label = "sw1";
-- };
--
-- port@2 {
-- reg = <2>;
-- label = "sw2";
-- };
--
-- port@3 {
-- reg = <3>;
-- label = "sw3";
-- };
--
-- port@4 {
-- reg = <4>;
-- label = "sw4";
-- };
--
-- port@5 {
-- reg = <5>;
-- label = "sw5";
-- };
-- };
-- };
-- };
--
- mdio1: mdio-1 {
- status = "okay";
- compatible = "virtual,mdio-gpio";
-@@ -222,6 +155,73 @@
- status = "okay";
- };
-
-+&mdio0 {
-+ status = "okay";
-+ compatible = "virtual,mdio-gpio";
-+ gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>,
-+ <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ pinctrl-0 = <&mdio0_pins>;
-+ pinctrl-names = "default";
-+
-+ switch0: switch@10 {
-+ compatible = "qca,qca8337";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ dsa,member = <0 0>;
-+
-+ pinctrl-0 = <&sw0_reset_pin>;
-+ pinctrl-names = "default";
-+
-+ reset-gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;
-+ reg = <0x10>;
-+
-+ ports {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ switch0cpu: port@0 {
-+ reg = <0>;
-+ label = "cpu";
-+ ethernet = <&gmac0>;
-+ phy-mode = "rgmii-id";
-+ fixed-link {
-+ speed = <1000>;
-+ full-duplex;
-+ };
-+ };
-+
-+ port@1 {
-+ reg = <1>;
-+ label = "sw1";
-+ };
-+
-+ port@2 {
-+ reg = <2>;
-+ label = "sw2";
-+ };
-+
-+ port@3 {
-+ reg = <3>;
-+ label = "sw3";
-+ };
-+
-+ port@4 {
-+ reg = <4>;
-+ label = "sw4";
-+ };
-+
-+ port@5 {
-+ reg = <5>;
-+ label = "sw5";
-+ };
-+ };
-+ };
-+};
-+
- &gmac0 {
- status = "okay";
-
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -476,6 +476,20 @@
- snps,blen = <16 0 0 0 0 0 0>;
- };
-
-+ mdio0: mdio@37000000 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ compatible = "qcom,ipq8064-mdio", "syscon";
-+ reg = <0x37000000 0x200000>;
-+ resets = <&gcc GMAC_CORE1_RESET>;
-+ reset-names = "stmmaceth";
-+ clocks = <&gcc GMAC_CORE1_CLK>;
-+ clock-names = "stmmaceth";
-+
-+ status = "disabled";
-+ };
-+
- vsdcc_fixed: vsdcc-regulator {
- compatible = "regulator-fixed";
- regulator-name = "SDCC Power";
+++ /dev/null
-From b044ae89862132a86fb511648e9c52ea3cdf8c30 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Wed, 5 Aug 2020 14:19:23 +0200
-Subject: [PATCH 1/4] devfreq: qcom: Add L2 Krait Cache devfreq scaling driver
-
-Qcom L2 Krait CPUs use the generic cpufreq-dt driver and doesn't actually
-scale the Cache frequency when the CPU frequency is changed. This
-devfreq driver register with the cpu notifier and scale the Cache
-based on the max Freq across all core as the CPU cache is shared across
-all of them. If provided this also scale the voltage of the regulator
-attached to the CPU cache. The scaling logic is based on the CPU freq
-and the 3 scaling interval are set by the device dts.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- drivers/devfreq/Kconfig | 11 ++
- drivers/devfreq/Makefile | 1 +
- drivers/devfreq/krait-cache-devfreq.c | 188 ++++++++++++++++++++++++++
- 3 files changed, 200 insertions(+)
- create mode 100644 drivers/devfreq/krait-cache-devfreq.c
-
---- a/drivers/devfreq/Kconfig
-+++ b/drivers/devfreq/Kconfig
-@@ -151,6 +151,17 @@ config ARM_SUN8I_A33_MBUS_DEVFREQ
- This adds the DEVFREQ driver for the MBUS controller in some
- Allwinner sun8i (A33 through H3) and sun50i (A64 and H5) SoCs.
-
-+config ARM_KRAIT_CACHE_DEVFREQ
-+ tristate "Scaling support for Krait CPU Cache Devfreq"
-+ depends on ARCH_QCOM || COMPILE_TEST
-+ select DEVFREQ_GOV_PASSIVE
-+ help
-+ This adds the DEVFREQ driver for the Krait CPU L2 Cache shared by all cores.
-+
-+ The driver register with the cpufreq notifier and find the right frequency
-+ based on the max frequency across all core and the range set in the device
-+ dts. If provided this scale also the regulator attached to the l2 cache.
-+
- source "drivers/devfreq/event/Kconfig"
-
- endif # PM_DEVFREQ
---- a/drivers/devfreq/Makefile
-+++ b/drivers/devfreq/Makefile
-@@ -15,6 +15,7 @@ obj-$(CONFIG_ARM_MEDIATEK_CCI_DEVFREQ) +
- obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o
- obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ) += sun8i-a33-mbus.o
- obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-devfreq.o
-+obj-$(CONFIG_ARM_KRAIT_CACHE_DEVFREQ) += krait-cache-devfreq.o
-
- # DEVFREQ Event Drivers
- obj-$(CONFIG_PM_DEVFREQ_EVENT) += event/
---- /dev/null
-+++ b/drivers/devfreq/krait-cache-devfreq.c
-@@ -0,0 +1,181 @@
-+// SPDX-License-Identifier: GPL-2.0
-+
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/cpufreq.h>
-+#include <linux/devfreq.h>
-+#include <linux/of.h>
-+#include <linux/platform_device.h>
-+#include <linux/clk.h>
-+#include <linux/slab.h>
-+#include <linux/regulator/consumer.h>
-+#include <linux/pm_opp.h>
-+
-+#include "governor.h"
-+
-+struct krait_cache_data {
-+ struct clk *clk;
-+ unsigned long idle_freq;
-+ int token;
-+};
-+
-+static int krait_cache_config_clk(struct device *dev, struct opp_table *opp_table,
-+ struct dev_pm_opp *old_opp, struct dev_pm_opp *opp,
-+ void *data, bool scaling_down)
-+{
-+ struct krait_cache_data *kdata;
-+ unsigned long old_freq, freq;
-+ unsigned long idle_freq;
-+ struct clk *clk;
-+ int ret;
-+
-+ kdata = dev_get_drvdata(dev);
-+ idle_freq = kdata->idle_freq;
-+ clk = kdata->clk;
-+
-+ old_freq = dev_pm_opp_get_freq(old_opp);
-+ freq = dev_pm_opp_get_freq(opp);
-+
-+ /*
-+ * Set to idle bin if switching from normal to high bin
-+ * or vice versa. It has been notice that a bug is triggered
-+ * in cache scaling when more than one bin is scaled, to fix
-+ * this we first need to transition to the base rate and then
-+ * to target rate
-+ */
-+ if (likely(freq != idle_freq && old_freq != idle_freq)) {
-+ ret = clk_set_rate(clk, idle_freq);
-+ if (ret)
-+ return ret;
-+ }
-+
-+ return clk_set_rate(clk, freq);
-+};
-+
-+static int krait_cache_get_cur_freq(struct device *dev, unsigned long *freq)
-+{
-+ struct krait_cache_data *data = dev_get_drvdata(dev);
-+
-+ *freq = clk_get_rate(data->clk);
-+
-+ return 0;
-+};
-+
-+static int krait_cache_target(struct device *dev, unsigned long *freq,
-+ u32 flags)
-+{
-+ struct dev_pm_opp *opp;
-+
-+ opp = dev_pm_opp_find_freq_ceil(dev, freq);
-+ if (unlikely(IS_ERR(opp)))
-+ return PTR_ERR(opp);
-+
-+ dev_pm_opp_put(opp);
-+
-+ return dev_pm_opp_set_rate(dev, *freq);
-+};
-+
-+static int krait_cache_get_dev_status(struct device *dev,
-+ struct devfreq_dev_status *stat)
-+{
-+ struct krait_cache_data *data = dev_get_drvdata(dev);
-+
-+ stat->busy_time = 0;
-+ stat->total_time = 0;
-+ stat->current_frequency = clk_get_rate(data->clk);
-+
-+ return 0;
-+};
-+
-+static struct devfreq_dev_profile krait_cache_devfreq_profile = {
-+ .target = krait_cache_target,
-+ .get_dev_status = krait_cache_get_dev_status,
-+ .get_cur_freq = krait_cache_get_cur_freq
-+};
-+
-+static struct devfreq_passive_data devfreq_gov_data = {
-+ .parent_type = CPUFREQ_PARENT_DEV,
-+};
-+
-+static int krait_cache_probe(struct platform_device *pdev)
-+{
-+ struct dev_pm_opp_config config = { };
-+ struct device *dev = &pdev->dev;
-+ struct krait_cache_data *data;
-+ struct devfreq *devfreq;
-+ struct dev_pm_opp *opp;
-+ struct clk *clk;
-+ int ret, token;
-+
-+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
-+ if (!data)
-+ return -ENOMEM;
-+
-+ clk = devm_clk_get(dev, "l2");
-+ if (IS_ERR(clk))
-+ return PTR_ERR(clk);
-+
-+ config.regulator_names = (const char *[]){ "l2", NULL };
-+ config.clk_names = (const char *[]){ "l2", NULL };
-+ config.config_clks = krait_cache_config_clk;
-+
-+ token = dev_pm_opp_set_config(dev, &config);
-+ if (token < 0)
-+ return token;
-+
-+ ret = devm_pm_opp_of_add_table(dev);
-+ if (ret)
-+ goto free_opp;
-+
-+ opp = dev_pm_opp_find_freq_ceil(dev, &data->idle_freq);
-+ if (IS_ERR(opp)) {
-+ ret = PTR_ERR(opp);
-+ goto free_opp;
-+ }
-+ dev_pm_opp_put(opp);
-+
-+ data->token = token;
-+ data->clk = clk;
-+ dev_set_drvdata(dev, data);
-+ devfreq = devm_devfreq_add_device(dev, &krait_cache_devfreq_profile,
-+ DEVFREQ_GOV_PASSIVE, &devfreq_gov_data);
-+ if (IS_ERR(devfreq)) {
-+ ret = PTR_ERR(devfreq);
-+ goto free_opp;
-+ }
-+
-+ return 0;
-+
-+free_opp:
-+ dev_pm_opp_clear_config(token);
-+ return ret;
-+};
-+
-+static int krait_cache_remove(struct platform_device *pdev)
-+{
-+ struct krait_cache_data *data = dev_get_drvdata(&pdev->dev);
-+
-+ dev_pm_opp_clear_config(data->token);
-+
-+ return 0;
-+};
-+
-+static const struct of_device_id krait_cache_match_table[] = {
-+ { .compatible = "qcom,krait-cache" },
-+ {}
-+};
-+
-+static struct platform_driver krait_cache_driver = {
-+ .probe = krait_cache_probe,
-+ .remove = krait_cache_remove,
-+ .driver = {
-+ .name = "krait-cache-scaling",
-+ .of_match_table = krait_cache_match_table,
-+ },
-+};
-+module_platform_driver(krait_cache_driver);
-+
-+MODULE_DESCRIPTION("Krait CPU Cache Scaling driver");
-+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
-+MODULE_LICENSE("GPL v2");
+++ /dev/null
-From ef124ad0ff8abfbf4ebe3fe6d7dcef4541dec13a Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Thu, 16 Jun 2022 18:39:21 +0200
-Subject: [PATCH] ARM: dts: qcom: add krait-cache compatible for ipq806x dtsi
-
-Add qcom,krait-cache compatible to enable cache devfreq driver for
-ipq806x SoC and move the L2 node to the soc node to make the devfreq
-driver correctly probe.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- arch/arm/boot/dts/qcom-ipq8064.dtsi | 22 +++++++++++-----------
- 1 file changed, 11 insertions(+), 11 deletions(-)
-
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -69,16 +69,6 @@
- min-residency-us = <3000>;
- };
- };
--
-- L2: l2-cache {
-- compatible = "cache";
-- cache-level = <2>;
-- qcom,saw = <&saw_l2>;
--
-- clocks = <&kraitcc 4>;
-- clock-names = "l2";
-- operating-points-v2 = <&opp_table_l2>;
-- };
- };
-
- opp_table_l2: opp_table_l2 {
-@@ -1409,6 +1399,16 @@
- #reset-cells = <1>;
- };
-
-+ L2: l2-cache {
-+ compatible = "cache", "qcom,krait-cache";
-+ cache-level = <2>;
-+ qcom,saw = <&saw_l2>;
-+
-+ clocks = <&kraitcc 4>;
-+ clock-names = "l2";
-+ operating-points-v2 = <&opp_table_l2>;
-+ };
-+
- lpass@28100000 {
- compatible = "qcom,lpass-cpu";
- status = "disabled";
+++ /dev/null
-From 13f075999935bb696dbab63243923179f06fa05e Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Thu, 16 Jun 2022 19:56:08 +0200
-Subject: [PATCH 3/4] devfreq: add ipq806x fabric scaling driver
-
-Add ipq806x fabric scaling driver using the devfreq passive governor.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- drivers/devfreq/Kconfig | 11 ++
- drivers/devfreq/Makefile | 1 +
- drivers/devfreq/ipq806x-fab-devfreq.c | 155 ++++++++++++++++++++++++++
- 3 files changed, 167 insertions(+)
- create mode 100644 drivers/devfreq/ipq806x-fab-devfreq.c
-
---- a/drivers/devfreq/Kconfig
-+++ b/drivers/devfreq/Kconfig
-@@ -162,6 +162,17 @@ config ARM_KRAIT_CACHE_DEVFREQ
- based on the max frequency across all core and the range set in the device
- dts. If provided this scale also the regulator attached to the l2 cache.
-
-+config ARM_IPQ806X_FAB_DEVFREQ
-+ tristate "Scaling support for ipq806x Soc Fabric"
-+ depends on ARCH_QCOM || COMPILE_TEST
-+ select DEVFREQ_GOV_PASSIVE
-+ help
-+ This adds the DEVFREQ driver for the ipq806x Soc Fabric.
-+
-+ The driver register with the cpufreq notifier and find the right frequency
-+ based on the max frequency across all core and the range set in the device
-+ dts.
-+
- source "drivers/devfreq/event/Kconfig"
-
- endif # PM_DEVFREQ
---- a/drivers/devfreq/Makefile
-+++ b/drivers/devfreq/Makefile
-@@ -16,6 +16,7 @@ obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) +=
- obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ) += sun8i-a33-mbus.o
- obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-devfreq.o
- obj-$(CONFIG_ARM_KRAIT_CACHE_DEVFREQ) += krait-cache-devfreq.o
-+obj-$(CONFIG_ARM_IPQ806X_FAB_DEVFREQ) += ipq806x-fab-devfreq.o
-
- # DEVFREQ Event Drivers
- obj-$(CONFIG_PM_DEVFREQ_EVENT) += event/
---- /dev/null
-+++ b/drivers/devfreq/ipq806x-fab-devfreq.c
-@@ -0,0 +1,155 @@
-+// SPDX-License-Identifier: GPL-2.0
-+
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/cpufreq.h>
-+#include <linux/devfreq.h>
-+#include <linux/of.h>
-+#include <linux/platform_device.h>
-+#include <linux/clk.h>
-+#include <linux/slab.h>
-+#include <linux/pm_opp.h>
-+
-+#include "governor.h"
-+
-+struct ipq806x_fab_data {
-+ struct clk *fab_clk;
-+ struct clk *ddr_clk;
-+};
-+
-+static int ipq806x_fab_get_cur_freq(struct device *dev, unsigned long *freq)
-+{
-+ struct ipq806x_fab_data *data = dev_get_drvdata(dev);
-+
-+ *freq = clk_get_rate(data->fab_clk);
-+
-+ return 0;
-+};
-+
-+static int ipq806x_fab_target(struct device *dev, unsigned long *freq,
-+ u32 flags)
-+{
-+ struct ipq806x_fab_data *data = dev_get_drvdata(dev);
-+ struct dev_pm_opp *opp;
-+ int ret;
-+
-+ opp = dev_pm_opp_find_freq_ceil(dev, freq);
-+ if (unlikely(IS_ERR(opp)))
-+ return PTR_ERR(opp);
-+
-+ dev_pm_opp_put(opp);
-+
-+ ret = clk_set_rate(data->fab_clk, *freq);
-+ if (ret)
-+ return ret;
-+
-+ return clk_set_rate(data->ddr_clk, *freq);
-+};
-+
-+static int ipq806x_fab_get_dev_status(struct device *dev,
-+ struct devfreq_dev_status *stat)
-+{
-+ struct ipq806x_fab_data *data = dev_get_drvdata(dev);
-+
-+ stat->busy_time = 0;
-+ stat->total_time = 0;
-+ stat->current_frequency = clk_get_rate(data->fab_clk);
-+
-+ return 0;
-+};
-+
-+static struct devfreq_dev_profile ipq806x_fab_devfreq_profile = {
-+ .target = ipq806x_fab_target,
-+ .get_dev_status = ipq806x_fab_get_dev_status,
-+ .get_cur_freq = ipq806x_fab_get_cur_freq
-+};
-+
-+static struct devfreq_passive_data devfreq_gov_data = {
-+ .parent_type = CPUFREQ_PARENT_DEV,
-+};
-+
-+static int ipq806x_fab_probe(struct platform_device *pdev)
-+{
-+ struct device *dev = &pdev->dev;
-+ struct ipq806x_fab_data *data;
-+ struct devfreq *devfreq;
-+ struct clk *clk;
-+ int ret;
-+
-+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
-+ if (!data)
-+ return -ENOMEM;
-+
-+ clk = devm_clk_get(dev, "apps-fab-clk");
-+ if (IS_ERR(clk)) {
-+ dev_err_probe(dev, PTR_ERR(clk), "failed to get apps fab clk\n");
-+ return PTR_ERR(clk);
-+ }
-+
-+ clk_prepare_enable(clk);
-+ data->fab_clk = clk;
-+
-+ clk = devm_clk_get(dev, "ddr-fab-clk");
-+ if (IS_ERR(clk)) {
-+ dev_err_probe(dev, PTR_ERR(clk), "failed to get ddr fab clk\n");
-+ goto err_ddr;
-+ }
-+
-+ clk_prepare_enable(clk);
-+ data->ddr_clk = clk;
-+
-+ ret = dev_pm_opp_of_add_table(dev);
-+ if (ret) {
-+ dev_err(dev, "failed to parse fab freq thresholds\n");
-+ return ret;
-+ }
-+
-+ dev_set_drvdata(dev, data);
-+
-+ devfreq = devm_devfreq_add_device(&pdev->dev, &ipq806x_fab_devfreq_profile,
-+ DEVFREQ_GOV_PASSIVE, &devfreq_gov_data);
-+ if (IS_ERR(devfreq))
-+ dev_pm_opp_remove_table(dev);
-+
-+ return PTR_ERR_OR_ZERO(devfreq);
-+
-+err_ddr:
-+ clk_unprepare(data->fab_clk);
-+ clk_put(data->fab_clk);
-+ return PTR_ERR(clk);
-+};
-+
-+static int ipq806x_fab_remove(struct platform_device *pdev)
-+{
-+ struct ipq806x_fab_data *data = dev_get_drvdata(&pdev->dev);
-+
-+ clk_unprepare(data->fab_clk);
-+ clk_put(data->fab_clk);
-+
-+ clk_unprepare(data->ddr_clk);
-+ clk_put(data->ddr_clk);
-+
-+ dev_pm_opp_remove_table(&pdev->dev);
-+
-+ return 0;
-+};
-+
-+static const struct of_device_id ipq806x_fab_match_table[] = {
-+ { .compatible = "qcom,fab-scaling" },
-+ {}
-+};
-+
-+static struct platform_driver ipq806x_fab_driver = {
-+ .probe = ipq806x_fab_probe,
-+ .remove = ipq806x_fab_remove,
-+ .driver = {
-+ .name = "ipq806x-fab-scaling",
-+ .of_match_table = ipq806x_fab_match_table,
-+ },
-+};
-+module_platform_driver(ipq806x_fab_driver);
-+
-+MODULE_DESCRIPTION("ipq806x Fab Scaling driver");
-+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
-+MODULE_LICENSE("GPL v2");
+++ /dev/null
-From c3573f0907dadb0a6e9933aae2a46a489abcbd48 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Thu, 16 Jun 2022 20:03:05 +0200
-Subject: [PATCH 4/4] ARM: dts: qcom: add fab scaling node for ipq806x
-
-Add fabric scaling node for ipq806x to correctly scale apps and ddr
-fabric clk.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- arch/arm/boot/dts/qcom-ipq8064.dtsi | 19 +++++++++++++++++++
- 1 file changed, 19 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -170,6 +170,18 @@
- };
- };
-
-+ opp_table_fab: opp_table_fab {
-+ compatible = "operating-points-v2";
-+
-+ opp-533000000 {
-+ opp-hz = /bits/ 64 <533000000>;
-+ };
-+
-+ opp-400000000 {
-+ opp-hz = /bits/ 64 <400000000>;
-+ };
-+ };
-+
- thermal-zones {
- sensor0-thermal {
- polling-delay-passive = <0>;
-@@ -1409,6 +1421,13 @@
- operating-points-v2 = <&opp_table_l2>;
- };
-
-+ fab-scaling {
-+ compatible = "qcom,fab-scaling";
-+ clocks = <&rpmcc RPM_APPS_FABRIC_A_CLK>, <&rpmcc RPM_EBI1_A_CLK>;
-+ clock-names = "apps-fab-clk", "ddr-fab-clk";
-+ operating-points-v2 = <&opp_table_fab>;
-+ };
-+
- lpass@28100000 {
- compatible = "qcom,lpass-cpu";
- status = "disabled";
+++ /dev/null
-From 666c1b745e93ccddde841d5057c33f97b29a316a Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Thu, 15 Sep 2022 02:19:28 +0200
-Subject: [PATCH 3/9] clk: qcom: krait-cc: handle qsb clock defined in DTS
-
-qsb fixed clk may be defined in DTS and correctly passed in the clocks
-list. Add related code to handle this and modify the logic to
-dynamically read qsb clock frequency.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- drivers/clk/qcom/krait-cc.c | 14 +++++++++++---
- 1 file changed, 11 insertions(+), 3 deletions(-)
-
---- a/drivers/clk/qcom/krait-cc.c
-+++ b/drivers/clk/qcom/krait-cc.c
-@@ -348,7 +348,7 @@ static int krait_cc_probe(struct platfor
- {
- struct device *dev = &pdev->dev;
- const struct of_device_id *id;
-- unsigned long cur_rate, aux_rate;
-+ unsigned long cur_rate, aux_rate, qsb_rate;
- int cpu;
- struct clk_hw *mux, *l2_pri_mux;
- struct clk *clk, **clks;
-@@ -357,11 +357,19 @@ static int krait_cc_probe(struct platfor
- if (!id)
- return -ENODEV;
-
-- /* Rate is 1 because 0 causes problems for __clk_mux_determine_rate */
-- clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1);
-+ /*
-+ * Per Documentation qsb should be provided from DTS.
-+ * To address old implementation, register the fixed clock anyway.
-+ * Rate is 1 because 0 causes problems for __clk_mux_determine_rate
-+ */
-+ clk = clk_get(dev, "qsb");
-+ if (IS_ERR(clk))
-+ clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1);
- if (IS_ERR(clk))
- return PTR_ERR(clk);
-
-+ qsb_rate = clk_get_rate(clk);
-+
- if (!id->data) {
- clk = clk_register_fixed_factor(dev, "acpu_aux",
- "gpll0_vote", 0, 1, 2);
+++ /dev/null
-From fca6f185a9d9ef0892a719bc6da955b22d326ec7 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Thu, 15 Sep 2022 02:24:33 +0200
-Subject: [PATCH 4/9] clk: qcom: krait-cc: register REAL qsb fixed clock
-
-With some tools it was discovered the real frequency of the qsb fixed
-clock. While not 100% correct it's still better than using 1 as a dummy
-frequency.
-Correctly register the qsb fixed clock with the frequency of 225 MHz
-instead of 1.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- drivers/clk/qcom/krait-cc.c | 8 +++++---
- 1 file changed, 5 insertions(+), 3 deletions(-)
-
---- a/drivers/clk/qcom/krait-cc.c
-+++ b/drivers/clk/qcom/krait-cc.c
-@@ -25,6 +25,8 @@ enum {
- clks_max,
- };
-
-+#define QSB_RATE 2250000000
-+
- static unsigned int sec_mux_map[] = {
- 2,
- 0,
-@@ -364,7 +366,7 @@ static int krait_cc_probe(struct platfor
- */
- clk = clk_get(dev, "qsb");
- if (IS_ERR(clk))
-- clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1);
-+ clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, QSB_RATE);
- if (IS_ERR(clk))
- return PTR_ERR(clk);
-
+++ /dev/null
-From 2399d181557d94ae9a2686926cd25768f132e4b4 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Fri, 18 Mar 2022 16:12:14 +0100
-Subject: [PATCH 7/9] clk: qcom: krait-cc: drop pr_info and use dev_info
-
-Replace pr_info() with dev_info() to provide better diagnostics.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- drivers/clk/qcom/krait-cc.c | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
---- a/drivers/clk/qcom/krait-cc.c
-+++ b/drivers/clk/qcom/krait-cc.c
-@@ -423,25 +423,25 @@ static int krait_cc_probe(struct platfor
- cur_rate = clk_get_rate(clks[l2_mux]);
- aux_rate = 384000000;
- if (cur_rate < aux_rate) {
-- pr_info("L2 @ Undefined rate. Forcing new rate.\n");
-+ dev_info(dev, "L2 @ Undefined rate. Forcing new rate.\n");
- cur_rate = aux_rate;
- }
- clk_set_rate(clks[l2_mux], aux_rate);
- clk_set_rate(clks[l2_mux], 2);
- clk_set_rate(clks[l2_mux], cur_rate);
-- pr_info("L2 @ %lu KHz\n", clk_get_rate(clks[l2_mux]) / 1000);
-+ dev_info(dev, "L2 @ %lu KHz\n", clk_get_rate(clks[l2_mux]) / 1000);
- for_each_possible_cpu(cpu) {
- clk = clks[cpu];
- cur_rate = clk_get_rate(clk);
- if (cur_rate < aux_rate) {
-- pr_info("CPU%d @ Undefined rate. Forcing new rate.\n", cpu);
-+ dev_info(dev, "CPU%d @ Undefined rate. Forcing new rate.\n", cpu);
- cur_rate = aux_rate;
- }
-
- clk_set_rate(clk, aux_rate);
- clk_set_rate(clk, 2);
- clk_set_rate(clk, cur_rate);
-- pr_info("CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000);
-+ dev_info(dev, "CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000);
- }
-
- of_clk_add_provider(dev->of_node, krait_of_get, clks);
+++ /dev/null
-From 6a77cf3f5f95ec0058e1b4d1ada018748cb0b83b Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Thu, 15 Sep 2022 03:33:13 +0200
-Subject: [PATCH 9/9] clk: qcom: krait-cc: rework mux reset logic and reset
- hfpll
-
-Rework and clean mux reset logic.
-Compact it to a for loop to handle both CPU and L2 in one place.
-Move hardcoded aux_rate to define and add a new hfpll_rate value to
-reset hfpll settings.
-Change logic to now reset the hfpll to the lowest value of 600 Mhz and
-then restoring the previous frequency. This permits to reset the hfpll if
-the primary mux was set to source out of the secondary mux.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- drivers/clk/qcom/krait-cc.c | 50 +++++++++++++++++--------------------
- 1 file changed, 23 insertions(+), 27 deletions(-)
-
---- a/drivers/clk/qcom/krait-cc.c
-+++ b/drivers/clk/qcom/krait-cc.c
-@@ -25,7 +25,9 @@ enum {
- clks_max,
- };
-
--#define QSB_RATE 2250000000
-+#define QSB_RATE 225000000
-+#define AUX_RATE 384000000
-+#define HFPLL_RATE 600000000
-
- static unsigned int sec_mux_map[] = {
- 2,
-@@ -350,7 +352,7 @@ static int krait_cc_probe(struct platfor
- {
- struct device *dev = &pdev->dev;
- const struct of_device_id *id;
-- unsigned long cur_rate, aux_rate, qsb_rate;
-+ unsigned long cur_rate, qsb_rate;
- int cpu;
- struct clk_hw *mux, *l2_pri_mux;
- struct clk *clk, **clks;
-@@ -420,28 +422,29 @@ static int krait_cc_probe(struct platfor
- * two different rates to force a HFPLL reinit under all
- * circumstances.
- */
-- cur_rate = clk_get_rate(clks[l2_mux]);
-- aux_rate = 384000000;
-- if (cur_rate < aux_rate) {
-- dev_info(dev, "L2 @ Undefined rate. Forcing new rate.\n");
-- cur_rate = aux_rate;
-- }
-- clk_set_rate(clks[l2_mux], aux_rate);
-- clk_set_rate(clks[l2_mux], 2);
-- clk_set_rate(clks[l2_mux], cur_rate);
-- dev_info(dev, "L2 @ %lu KHz\n", clk_get_rate(clks[l2_mux]) / 1000);
-- for_each_possible_cpu(cpu) {
-+ for (cpu = 0; cpu < 5; cpu++) {
-+ const char *l2_s = "L2";
-+ char cpu_s[5];
-+
- clk = clks[cpu];
-+ if (!clk)
-+ continue;
-+
-+ if (cpu < 4)
-+ snprintf(cpu_s, 5, "CPU%d", cpu);
-+
- cur_rate = clk_get_rate(clk);
-- if (cur_rate < aux_rate) {
-- dev_info(dev, "CPU%d @ Undefined rate. Forcing new rate.\n", cpu);
-- cur_rate = aux_rate;
-+ if (cur_rate < AUX_RATE) {
-+ dev_info(dev, "%s @ Undefined rate. Forcing new rate.\n",
-+ cpu < 4 ? cpu_s : l2_s);
-+ cur_rate = AUX_RATE;
- }
-
-- clk_set_rate(clk, aux_rate);
-- clk_set_rate(clk, 2);
-+ clk_set_rate(clk, AUX_RATE);
-+ clk_set_rate(clk, HFPLL_RATE);
- clk_set_rate(clk, cur_rate);
-- dev_info(dev, "CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000);
-+ dev_info(dev, "%s @ %lu KHz\n", cpu < 4 ? cpu_s : l2_s,
-+ clk_get_rate(clk) / 1000);
- }
-
- of_clk_add_provider(dev->of_node, krait_of_get, clks);
+++ /dev/null
-From 908c361b3c3a139eb3e6a798cb620a6da7514d5c Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Fri, 23 Sep 2022 19:05:39 +0200
-Subject: [PATCH 2/4] clk: qcom: clk-krait: generilize div functions
-
-Generilize div functions and remove hardcode to a divisor of 2.
-This is just a cleanup and permit to make it more clear the settings of
-the devisor when used by the krait-cc driver.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- drivers/clk/qcom/clk-krait.c | 57 ++++++++++++++++++++----------------
- drivers/clk/qcom/clk-krait.h | 11 ++++---
- drivers/clk/qcom/krait-cc.c | 7 +++--
- 3 files changed, 42 insertions(+), 33 deletions(-)
-
---- a/drivers/clk/qcom/clk-krait.c
-+++ b/drivers/clk/qcom/clk-krait.c
-@@ -97,53 +97,58 @@ const struct clk_ops krait_mux_clk_ops =
- EXPORT_SYMBOL_GPL(krait_mux_clk_ops);
-
- /* The divider can divide by 2, 4, 6 and 8. But we only really need div-2. */
--static long krait_div2_round_rate(struct clk_hw *hw, unsigned long rate,
-+static long krait_div_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
- {
-- *parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), rate * 2);
-- return DIV_ROUND_UP(*parent_rate, 2);
-+ struct krait_div_clk *d = to_krait_div_clk(hw);
-+
-+ *parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
-+ rate * d->divisor);
-+
-+ return DIV_ROUND_UP(*parent_rate, d->divisor);
- }
-
--static int krait_div2_set_rate(struct clk_hw *hw, unsigned long rate,
-+static int krait_div_set_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long parent_rate)
- {
-- struct krait_div2_clk *d = to_krait_div2_clk(hw);
-+ struct krait_div_clk *d = to_krait_div_clk(hw);
-+ u8 div_val = krait_div_to_val(d->divisor);
- unsigned long flags;
-- u32 val;
-- u32 mask = BIT(d->width) - 1;
--
-- if (d->lpl)
-- mask = mask << (d->shift + LPL_SHIFT) | mask << d->shift;
-- else
-- mask <<= d->shift;
-+ u32 regval;
-
- spin_lock_irqsave(&krait_clock_reg_lock, flags);
-- val = krait_get_l2_indirect_reg(d->offset);
-- val &= ~mask;
-- krait_set_l2_indirect_reg(d->offset, val);
-+ regval = krait_get_l2_indirect_reg(d->offset);
-+
-+ regval &= ~(d->mask << d->shift);
-+ regval |= (div_val & d->mask) << d->shift;
-+
-+ if (d->lpl) {
-+ regval &= ~(d->mask << (d->shift + LPL_SHIFT));
-+ regval |= (div_val & d->mask) << (d->shift + LPL_SHIFT);
-+ }
-+
-+ krait_set_l2_indirect_reg(d->offset, regval);
- spin_unlock_irqrestore(&krait_clock_reg_lock, flags);
-
- return 0;
- }
-
- static unsigned long
--krait_div2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
-+krait_div_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
- {
-- struct krait_div2_clk *d = to_krait_div2_clk(hw);
-- u32 mask = BIT(d->width) - 1;
-+ struct krait_div_clk *d = to_krait_div_clk(hw);
- u32 div;
-
- div = krait_get_l2_indirect_reg(d->offset);
- div >>= d->shift;
-- div &= mask;
-- div = (div + 1) * 2;
-+ div &= d->mask;
-
-- return DIV_ROUND_UP(parent_rate, div);
-+ return DIV_ROUND_UP(parent_rate, krait_val_to_div(div));
- }
-
--const struct clk_ops krait_div2_clk_ops = {
-- .round_rate = krait_div2_round_rate,
-- .set_rate = krait_div2_set_rate,
-- .recalc_rate = krait_div2_recalc_rate,
-+const struct clk_ops krait_div_clk_ops = {
-+ .round_rate = krait_div_round_rate,
-+ .set_rate = krait_div_set_rate,
-+ .recalc_rate = krait_div_recalc_rate,
- };
--EXPORT_SYMBOL_GPL(krait_div2_clk_ops);
-+EXPORT_SYMBOL_GPL(krait_div_clk_ops);
---- a/drivers/clk/qcom/clk-krait.h
-+++ b/drivers/clk/qcom/clk-krait.h
-@@ -25,17 +25,20 @@ struct krait_mux_clk {
-
- extern const struct clk_ops krait_mux_clk_ops;
-
--struct krait_div2_clk {
-+struct krait_div_clk {
- u32 offset;
-- u8 width;
-+ u32 mask;
-+ u8 divisor;
- u32 shift;
- bool lpl;
-
- struct clk_hw hw;
- };
-
--#define to_krait_div2_clk(_hw) container_of(_hw, struct krait_div2_clk, hw)
-+#define to_krait_div_clk(_hw) container_of(_hw, struct krait_div_clk, hw)
-+#define krait_div_to_val(_div) ((_div) / 2) - 1
-+#define krait_val_to_div(_val) ((_val) + 1) * 2
-
--extern const struct clk_ops krait_div2_clk_ops;
-+extern const struct clk_ops krait_div_clk_ops;
-
- #endif
---- a/drivers/clk/qcom/krait-cc.c
-+++ b/drivers/clk/qcom/krait-cc.c
-@@ -86,11 +86,11 @@ static int krait_notifier_register(struc
- static struct clk_hw *
- krait_add_div(struct device *dev, int id, const char *s, unsigned int offset)
- {
-- struct krait_div2_clk *div;
-+ struct krait_div_clk *div;
- static struct clk_parent_data p_data[1];
- struct clk_init_data init = {
- .num_parents = ARRAY_SIZE(p_data),
-- .ops = &krait_div2_clk_ops,
-+ .ops = &krait_div_clk_ops,
- .flags = CLK_SET_RATE_PARENT,
- };
- struct clk_hw *clk;
-@@ -101,7 +101,8 @@ krait_add_div(struct device *dev, int id
- if (!div)
- return ERR_PTR(-ENOMEM);
-
-- div->width = 2;
-+ div->mask = 0x3;
-+ div->divisor = 2;
- div->shift = 6;
- div->lpl = id >= 0;
- div->offset = offset;
+++ /dev/null
-From ac84ac819a2e8fd3d87122b452c502a386c54437 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Tue, 5 Jul 2022 18:30:18 +0200
-Subject: [PATCH v2 4/4] clk: qcom: gcc-ipq806x: remove cc_register_board for
- pxo and cxo
-
-Now that these clock are defined as fixed clk in dts, we can drop the
-register_board_clk for cxo_board and pxo_board in gcc_ipq806x_probe.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- drivers/clk/qcom/gcc-ipq806x.c | 8 --------
- 1 file changed, 8 deletions(-)
-
---- a/drivers/clk/qcom/gcc-ipq806x.c
-+++ b/drivers/clk/qcom/gcc-ipq806x.c
-@@ -3386,14 +3386,6 @@ static int gcc_ipq806x_probe(struct plat
- struct regmap *regmap;
- int ret;
-
-- ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 25000000);
-- if (ret)
-- return ret;
--
-- ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 25000000);
-- if (ret)
-- return ret;
--
- if (of_machine_is_compatible("qcom,ipq8065")) {
- ubi32_core1_src_clk.freq_tbl = clk_tbl_nss_ipq8065;
- ubi32_core2_src_clk.freq_tbl = clk_tbl_nss_ipq8065;
+++ /dev/null
-From: Christian Lamparter <chunkeey@googlemail.com>
-Subject: SoC: add qualcomm syscon
---- a/drivers/soc/qcom/Makefile
-+++ b/drivers/soc/qcom/Makefile
-@@ -23,6 +23,7 @@ obj-$(CONFIG_QCOM_SOCINFO) += socinfo.o
- obj-$(CONFIG_QCOM_SPM) += spm.o
- obj-$(CONFIG_QCOM_STATS) += qcom_stats.o
- obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o
-+obj-$(CONFIG_QCOM_TCSR) += qcom_tcsr.o
- obj-$(CONFIG_QCOM_APR) += apr.o
- obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o
- obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o
---- a/drivers/soc/qcom/Kconfig
-+++ b/drivers/soc/qcom/Kconfig
-@@ -213,6 +213,13 @@ config QCOM_STATS
- various SoC level low power modes statistics and export to debugfs
- interface.
-
-+config QCOM_TCSR
-+ tristate "QCOM Top Control and Status Registers"
-+ depends on ARCH_QCOM
-+ help
-+ Say y here to enable TCSR support. The TCSR provides control
-+ functions for various peripherals.
-+
- config QCOM_WCNSS_CTRL
- tristate "Qualcomm WCNSS control driver"
- depends on ARCH_QCOM || COMPILE_TEST
---- /dev/null
-+++ b/drivers/soc/qcom/qcom_tcsr.c
-@@ -0,0 +1,64 @@
-+/*
-+ * Copyright (c) 2014, The Linux foundation. All rights reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License rev 2 and
-+ * only rev 2 as published by the free Software foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/err.h>
-+#include <linux/io.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/of_platform.h>
-+#include <linux/platform_device.h>
-+
-+#define TCSR_USB_PORT_SEL 0xb0
-+
-+static int tcsr_probe(struct platform_device *pdev)
-+{
-+ struct resource *res;
-+ const struct device_node *node = pdev->dev.of_node;
-+ void __iomem *base;
-+ u32 val;
-+
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ base = devm_ioremap_resource(&pdev->dev, res);
-+ if (IS_ERR(base))
-+ return PTR_ERR(base);
-+
-+ if (!of_property_read_u32(node, "qcom,usb-ctrl-select", &val)) {
-+ dev_err(&pdev->dev, "setting usb port select = %d\n", val);
-+ writel(val, base + TCSR_USB_PORT_SEL);
-+ }
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id tcsr_dt_match[] = {
-+ { .compatible = "qcom,tcsr", },
-+ { },
-+};
-+
-+MODULE_DEVICE_TABLE(of, tcsr_dt_match);
-+
-+static struct platform_driver tcsr_driver = {
-+ .driver = {
-+ .name = "tcsr",
-+ .owner = THIS_MODULE,
-+ .of_match_table = tcsr_dt_match,
-+ },
-+ .probe = tcsr_probe,
-+};
-+
-+module_platform_driver(tcsr_driver);
-+
-+MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
-+MODULE_DESCRIPTION("QCOM TCSR driver");
-+MODULE_LICENSE("GPL v2");
---- /dev/null
-+++ b/include/dt-bindings/soc/qcom,tcsr.h
-@@ -0,0 +1,23 @@
-+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 and
-+ * only version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ */
-+#ifndef __DT_BINDINGS_QCOM_TCSR_H
-+#define __DT_BINDINGS_QCOM_TCSR_H
-+
-+#define TCSR_USB_SELECT_USB3_P0 0x1
-+#define TCSR_USB_SELECT_USB3_P1 0x2
-+#define TCSR_USB_SELECT_USB3_DUAL 0x3
-+
-+/* TCSR A/B REG */
-+#define IPQ806X_TCSR_REG_A_ADM_CRCI_MUX_SEL 0
-+#define IPQ806X_TCSR_REG_B_ADM_CRCI_MUX_SEL 1
-+
-+#endif
+++ /dev/null
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -1589,6 +1589,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
-
- endchoice
-
-+config CMDLINE_OVERRIDE
-+ bool "Use alternative cmdline from device tree"
-+ help
-+ Some bootloaders may have uneditable bootargs. While CMDLINE_FORCE can
-+ be used, this is not a good option for kernels that are shared across
-+ devices. This setting enables using "chosen/cmdline-override" as the
-+ cmdline if it exists in the device tree.
-+
- config CMDLINE
- string "Default kernel command string"
- default ""
---- a/drivers/of/fdt.c
-+++ b/drivers/of/fdt.c
-@@ -1187,6 +1187,17 @@ int __init early_init_dt_scan_chosen(cha
- if (p != NULL && l > 0)
- strlcat(cmdline, p, min_t(int, strlen(cmdline) + (int)l, COMMAND_LINE_SIZE));
-
-+ /* CONFIG_CMDLINE_OVERRIDE is used to fallback to a different
-+ * device tree option of chosen/bootargs-override. This is
-+ * helpful on boards where u-boot sets bootargs, and is unable
-+ * to be modified.
-+ */
-+#ifdef CONFIG_CMDLINE_OVERRIDE
-+ p = of_get_flat_dt_prop(node, "bootargs-override", &l);
-+ if (p != NULL && l > 0)
-+ strlcpy(cmdline, p, min((int)l, COMMAND_LINE_SIZE));
-+#endif
-+
- handle_cmdline:
- /*
- * CONFIG_CMDLINE is meant to be a default in case nothing else
+++ /dev/null
-From 2f86b9b71a11f86e3d850214ab781ebb17d7260e Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Fri, 19 Jan 2024 19:48:30 +0100
-Subject: [PATCH v2 1/2] ARM: decompressor: support memory start validation for
- appended DTB
-
-There is currently a problem with a very specific sets of kernel config
-and AUTO_ZRELADDR.
-
-For the most common case AUTO_ZRELADDR check the PC register and
-calculate the start of the physical memory. Then fdt_check_mem_start is
-called to make sure the detected value makes sense by comparing it with
-what is present in DTB in the memory nodes and if additional fixup are
-required with the use of linux,usable-memory-range in the chosen node to
-hardcode usable memory range in case some reserved space needs to be
-addressed. With the help of this function the right address is
-calculated and the kernel correctly decompress and loads.
-
-Things starts to become problematic when in the mix,
-CONFIG_ARM_APPENDED_DTB is used. This is a particular kernel config is
-used when legacy systems doesn't support passing a DTB directly and a
-DTB is appended at the end of the image.
-
-In such case, fdt_check_mem_start is skipped in AUTO_ZRELADDR iteration
-as the appended DTB can be augumented later with ATAGS passed from the
-bootloader (if CONFIG_ARM_ATAG_DTB_COMPAT is enabled).
-
-The main problem and what this patch address is the fact that
-fdt_check_mem_start is never called later when the appended DTB is
-augumented, hence any fixup and validation is not done making AUTO_ZRELADDR
-detection inconsistent and most of the time wrong.
-
-Add support in head.S for this by checking if AUTO_ZRELADDR is enabled
-and calling fdt_check_mem_start with the appended DTB and the augumented
-values permitting legacy device to provide info in DTB instead of
-disabling AUTO_ZRELADDR and hardcoding the physical address offsets.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
-Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
----
- arch/arm/boot/compressed/head.S | 22 ++++++++++++++++++++++
- 1 file changed, 22 insertions(+)
-
---- a/arch/arm/boot/compressed/head.S
-+++ b/arch/arm/boot/compressed/head.S
-@@ -443,6 +443,28 @@ restart: adr r0, LC1
- add r6, r6, r5
- add r10, r10, r5
- add sp, sp, r5
-+
-+#ifdef CONFIG_AUTO_ZRELADDR
-+ /*
-+ * Validate calculated start of physical memory with appended DTB.
-+ * In the first iteration for physical memory start calculation,
-+ * we skipped validating it as it could have been augumented by
-+ * ATAGS stored at an offset from the same start of physical memory.
-+ *
-+ * We now have parsed them and augumented the appended DTB if asked
-+ * so we can finally validate the start of physical memory.
-+ *
-+ * This is needed to apply additional fixup with
-+ * linux,usable-memory-range or to make sure AUTO_ZRELADDR detected
-+ * the correct value.
-+ */
-+ sub r0, r4, #TEXT_OFFSET @ revert to base address
-+ mov r1, r8 @ use appended DTB
-+ bl fdt_check_mem_start
-+
-+ /* Determine final kernel image address. */
-+ add r4, r0, #TEXT_OFFSET
-+#endif
- dtb_check_done:
- #endif
-
+++ /dev/null
-From 781d7cd4c3364e9d38fa12a342c5ad4c7e33a5ba Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Fri, 19 Jan 2024 20:33:10 +0100
-Subject: [PATCH v2 2/2] ARM: decompressor: add option to ignore MEM ATAGs
-
-Some bootloaders can pass broken MEM ATAGs that provide hardcoded
-information about mounted RAM size and physical location.
-Example booloader provide RAM of size 1.7Gb but actual mounted RAM
-size is 512Mb causing kernel panic.
-
-Add option CONFIG_ARM_ATAG_DTB_COMPAT_IGNORE_MEM to ignore these ATAG
-and not augument appended DTB memory node.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Acked-by: Linus Walleij <linus.walleij@linaro.org>
----
- arch/arm/Kconfig | 12 ++++++++++++
- arch/arm/boot/compressed/atags_to_fdt.c | 4 ++++
- 2 files changed, 16 insertions(+)
-
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -1570,6 +1570,18 @@ config ARM_ATAG_DTB_COMPAT
- bootloaders, this option allows zImage to extract the information
- from the ATAG list and store it at run time into the appended DTB.
-
-+config ARM_ATAG_DTB_COMPAT_IGNORE_MEM
-+ bool "Ignore MEM ATAG information from bootloader"
-+ depends on ARM_ATAG_DTB_COMPAT
-+ help
-+ Some bootloaders can pass broken MEM ATAGs that provide hardcoded
-+ information about mounted RAM size and physical location.
-+ Example booloader provide RAM of size 1.7Gb but actual mounted RAM
-+ size is 512Mb causing kernel panic.
-+
-+ Enable this option if MEM ATAGs should be ignored and the memory
-+ node in the appended DTB should NOT be augumented.
-+
- choice
- prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
- default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
---- a/arch/arm/boot/compressed/atags_to_fdt.c
-+++ b/arch/arm/boot/compressed/atags_to_fdt.c
-@@ -169,6 +169,10 @@ int atags_to_fdt(void *atag_list, void *
- setprop_string(fdt, "/chosen", "bootargs",
- atag->u.cmdline.cmdline);
- } else if (atag->hdr.tag == ATAG_MEM) {
-+ /* Bootloader MEM ATAG are broken and should be ignored */
-+ if (IS_ENABLED(CONFIG_ARM_ATAG_DTB_COMPAT_IGNORE_MEM))
-+ continue;
-+
- if (memcount >= sizeof(mem_reg_property)/4)
- continue;
- if (!atag->u.mem.size)
+++ /dev/null
-From 13bb6d8dd9138927950a520a288401db82871dc9 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Sun, 21 Jan 2024 23:36:57 +0100
-Subject: [PATCH] ARM: decompressor: support for ATAGs rootblock parsing
-
-The command-line arguments provided by the boot loader will be
-appended to a new device tree property: bootloader-args.
-
-If there is a property "append-rootblock" in DT under /chosen
-and a root= option in bootloaders command line it will be parsed
-and added to DT bootargs with the form: <append-rootblock>XX.
-
-This is usefull in dual boot systems, to get the current root partition
-without afecting the rest of the system.
-
-Signed-off-by: Adrian Panella <ianchi74@outlook.com>
-[ reworked to a cleaner patch ]
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- arch/arm/Kconfig | 10 +++
- arch/arm/boot/compressed/atags_to_fdt.c | 102 ++++++++++++++++++++++--
- init/main.c | 12 +++
- 3 files changed, 117 insertions(+), 7 deletions(-)
-
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -1599,6 +1599,16 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
- The command-line arguments provided by the boot loader will be
- appended to the the device tree bootargs property.
-
-+config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
-+ bool "Append rootblock parsing bootloader's kernel arguments"
-+ help
-+ The command-line arguments provided by the boot loader will be
-+ appended to a new device tree property: bootloader-args.
-+
-+ If there is a property "append-rootblock" in DT under /chosen
-+ and a root= option in bootloaders command line it will be parsed
-+ and added to DT bootargs with the form: <append-rootblock>XX.
-+
- endchoice
-
- config CMDLINE_OVERRIDE
---- a/arch/arm/boot/compressed/atags_to_fdt.c
-+++ b/arch/arm/boot/compressed/atags_to_fdt.c
-@@ -3,7 +3,8 @@
- #include <asm/setup.h>
- #include <libfdt.h>
-
--#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND)
-+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND) || \
-+ defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
- #define do_extend_cmdline 1
- #else
- #define do_extend_cmdline 0
-@@ -69,6 +70,83 @@ static uint32_t get_cell_size(const void
- return cell_size;
- }
-
-+/**
-+ * taken from arch/x86/boot/string.c
-+ * local_strstr - Find the first substring in a %NUL terminated string
-+ * @s1: The string to be searched
-+ * @s2: The string to search for
-+ */
-+static char *local_strstr(const char *s1, const char *s2)
-+{
-+ size_t l1, l2;
-+
-+ l2 = strlen(s2);
-+ if (!l2)
-+ return (char *)s1;
-+ l1 = strlen(s1);
-+ while (l1 >= l2) {
-+ l1--;
-+ if (!memcmp(s1, s2, l2))
-+ return (char *)s1;
-+ s1++;
-+ }
-+ return NULL;
-+}
-+
-+static char *append_rootblock(char *dest, const char *str, int len, void *fdt)
-+{
-+ char *ptr, *end, *tmp;
-+ const char *root="root=";
-+ const char *find_rootblock;
-+ int i, l;
-+ const char *rootblock;
-+
-+ find_rootblock = getprop(fdt, "/chosen", "find-rootblock", &l);
-+ if (!find_rootblock)
-+ find_rootblock = root;
-+
-+ /* ARM doesn't have __HAVE_ARCH_STRSTR, so it was copied from x86 */
-+ ptr = local_strstr(str, find_rootblock);
-+ if (!ptr)
-+ return dest;
-+
-+ end = strchr(ptr, ' ');
-+ end = end ? (end - 1) : (strchr(ptr, 0) - 1);
-+
-+ /* Some boards ubi.mtd=XX,ZZZZ, so let's check for '," too. */
-+ tmp = strchr(ptr, ',');
-+ if (tmp)
-+ end = end < tmp ? end : tmp - 1;
-+
-+ /*
-+ * find partition number
-+ * (assumes format root=/dev/mtdXX | /dev/mtdblockXX | yy:XX | ubi.mtd=XX,ZZZZ )
-+ */
-+ for (i = 0; end >= ptr && *end >= '0' && *end <= '9'; end--, i++);
-+
-+ ptr = end + 1;
-+
-+ /* if append-rootblock property is set use it to append to command line */
-+ rootblock = getprop(fdt, "/chosen", "append-rootblock", &l);
-+ if (rootblock != NULL) {
-+ if (*dest != ' ') {
-+ *dest = ' ';
-+ dest++;
-+ len++;
-+ }
-+
-+ if (len + l + i <= COMMAND_LINE_SIZE) {
-+ memcpy(dest, rootblock, l);
-+ dest += l - 1;
-+
-+ memcpy(dest, ptr, i);
-+ dest += i;
-+ }
-+ }
-+
-+ return dest;
-+}
-+
- static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline)
- {
- char cmdline[COMMAND_LINE_SIZE];
-@@ -86,13 +164,23 @@ static void merge_fdt_bootargs(void *fdt
- ptr += len - 1;
- }
-
-- /* and append the ATAG_CMDLINE */
- if (fdt_cmdline) {
-- len = strlen(fdt_cmdline);
-- if (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) {
-- *ptr++ = ' ';
-- memcpy(ptr, fdt_cmdline, len);
-- ptr += len;
-+ if (IS_ENABLED(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)) {
-+ /*
-+ * save original bootloader args
-+ * and append ubi.mtd with root partition number
-+ * to current cmdline
-+ */
-+ setprop_string(fdt, "/chosen", "bootloader-args", fdt_cmdline);
-+ ptr = append_rootblock(ptr, fdt_cmdline, len, fdt);
-+ } else {
-+ /* and append the ATAG_CMDLINE */
-+ len = strlen(fdt_cmdline);
-+ if (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) {
-+ *ptr++ = ' ';
-+ memcpy(ptr, fdt_cmdline, len);
-+ ptr += len;
-+ }
- }
- }
- *ptr = '\0';
---- a/init/main.c
-+++ b/init/main.c
-@@ -28,6 +28,7 @@
- #include <linux/initrd.h>
- #include <linux/memblock.h>
- #include <linux/acpi.h>
-+#include <linux/of.h>
- #include <linux/bootconfig.h>
- #include <linux/console.h>
- #include <linux/nmi.h>
-@@ -996,6 +997,17 @@ asmlinkage __visible void __init __no_sa
- pr_notice("Kernel command line: %s\n", saved_command_line);
- /* parameters may set static keys */
- jump_label_init();
-+
-+ /* Show bootloader's original command line for reference */
-+ if (IS_ENABLED(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) && of_chosen) {
-+ const char *prop = of_get_property(of_chosen, "bootloader-args", NULL);
-+
-+ if(prop)
-+ pr_notice("Bootloader command line (ignored): %s\n", prop);
-+ else
-+ pr_notice("Bootloader command line not present\n");
-+ }
-+
- parse_early_param();
- after_dashes = parse_args("Booting kernel",
- static_command_line, __start___param,
#include <linux/bootconfig.h>
#include <linux/console.h>
#include <linux/nmi.h>
-@@ -930,6 +931,17 @@ void start_kernel(void)
+@@ -932,6 +933,17 @@ void start_kernel(void)
pr_notice("Kernel command line: %s\n", saved_command_line);
/* parameters may set static keys */
jump_label_init();
+++ /dev/null
-From b3f1a164c7f742503dc7159011f7ad6b092b660e Mon Sep 17 00:00:00 2001
-From: Greg Ungerer <gerg@kernel.org>
-Date: Fri, 24 Nov 2023 14:15:28 +1000
-Subject: [PATCH] net: dsa: mv88e6xxx: fix marvell 6350 switch probing
-
-As of commit de5c9bf40c45 ("net: phylink: require supported_interfaces to
-be filled") Marvell 88e6350 switches fail to be probed:
-
- ...
- mv88e6085 d0072004.mdio-mii:11: switch 0x3710 detected: Marvell 88E6350, revision 2
- mv88e6085 d0072004.mdio-mii:11: phylink: error: empty supported_interfaces
- error creating PHYLINK: -22
- mv88e6085: probe of d0072004.mdio-mii:11 failed with error -22
- ...
-
-The problem stems from the use of mv88e6185_phylink_get_caps() to get
-the device capabilities. Create a new dedicated phylink_get_caps for the
-6351 family (which the 6350 is one of) to properly support their set of
-capabilities.
-
-According to chip.h the 6351 switch family includes the 6171, 6175, 6350
-and 6351 switches, so update each of these to use the correct
-phylink_get_caps.
-
-Fixes: de5c9bf40c45 ("net: phylink: require supported_interfaces to be filled")
-Signed-off-by: Greg Ungerer <gerg@kernel.org>
-Reviewed-by: Andrew Lunn <andrew@lunn.ch>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/dsa/mv88e6xxx/chip.c | 20 ++++++++++++++++----
- 1 file changed, 16 insertions(+), 4 deletions(-)
-
---- a/drivers/net/dsa/mv88e6xxx/chip.c
-+++ b/drivers/net/dsa/mv88e6xxx/chip.c
-@@ -652,6 +652,18 @@ static void mv88e6250_phylink_get_caps(s
- config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
- }
-
-+static void mv88e6351_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
-+ struct phylink_config *config)
-+{
-+ unsigned long *supported = config->supported_interfaces;
-+
-+ /* Translate the default cmode */
-+ mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
-+
-+ config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
-+ MAC_1000FD;
-+}
-+
- static int mv88e6352_get_port4_serdes_cmode(struct mv88e6xxx_chip *chip)
- {
- u16 reg, val;
-@@ -4498,7 +4510,7 @@ static const struct mv88e6xxx_ops mv88e6
- .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
- .stu_getnext = mv88e6352_g1_stu_getnext,
- .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
-- .phylink_get_caps = mv88e6185_phylink_get_caps,
-+ .phylink_get_caps = mv88e6351_phylink_get_caps,
- };
-
- static const struct mv88e6xxx_ops mv88e6172_ops = {
-@@ -4599,7 +4611,7 @@ static const struct mv88e6xxx_ops mv88e6
- .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
- .stu_getnext = mv88e6352_g1_stu_getnext,
- .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
-- .phylink_get_caps = mv88e6185_phylink_get_caps,
-+ .phylink_get_caps = mv88e6351_phylink_get_caps,
- };
-
- static const struct mv88e6xxx_ops mv88e6176_ops = {
-@@ -5256,7 +5268,7 @@ static const struct mv88e6xxx_ops mv88e6
- .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
- .stu_getnext = mv88e6352_g1_stu_getnext,
- .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
-- .phylink_get_caps = mv88e6185_phylink_get_caps,
-+ .phylink_get_caps = mv88e6351_phylink_get_caps,
- };
-
- static const struct mv88e6xxx_ops mv88e6351_ops = {
-@@ -5302,7 +5314,7 @@ static const struct mv88e6xxx_ops mv88e6
- .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
- .avb_ops = &mv88e6352_avb_ops,
- .ptp_ops = &mv88e6352_ptp_ops,
-- .phylink_get_caps = mv88e6185_phylink_get_caps,
-+ .phylink_get_caps = mv88e6351_phylink_get_caps,
- };
-
- static const struct mv88e6xxx_ops mv88e6352_ops = {
FEATURES:=cpiogz ext4 ramdisk squashfs targz
KERNEL_PATCHVER:=6.1
+KERNEL_TESTING_PATCHVER:=6.6
include $(INCLUDE_DIR)/target.mk
--- /dev/null
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
+CONFIG_ARCH_MMAP_RND_BITS_MAX=15
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
+CONFIG_ATA=y
+CONFIG_ATA_PIIX=y
+CONFIG_BLK_DEV_BSG=y
+CONFIG_BLK_DEV_BSGLIB=y
+CONFIG_BLK_DEV_BSG_COMMON=y
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BOARD_SCACHE=y
+CONFIG_BOOT_ELF32=y
+CONFIG_BUFFER_HEAD=y
+CONFIG_BUILTIN_DTB=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CEVT_R4K=y
+CONFIG_CLKBLD_I8253=y
+CONFIG_CLKEVT_I8253=y
+CONFIG_CLKSRC_I8253=y
+CONFIG_CLKSRC_MIPS_GIC=y
+CONFIG_CLOCKSOURCE_WATCHDOG=y
+CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=100
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_PREFETCH=y
+# CONFIG_CPU_HAS_SMARTMIPS is not set
+CONFIG_CPU_HAS_SYNC=y
+# CONFIG_CPU_MICROMIPS is not set
+# CONFIG_CPU_MIPS32 is not set
+# CONFIG_CPU_MIPS32_3_5_FEATURES is not set
+# CONFIG_CPU_MIPS32_R1 is not set
+# CONFIG_CPU_MIPS32_R2 is not set
+# CONFIG_CPU_MIPS32_R5 is not set
+# CONFIG_CPU_MIPS32_R5_FEATURES is not set
+# CONFIG_CPU_MIPS32_R6 is not set
+# CONFIG_CPU_MIPS64_R1 is not set
+# CONFIG_CPU_MIPS64_R2 is not set
+# CONFIG_CPU_MIPS64_R6 is not set
+# CONFIG_CPU_MIPSR1 is not set
+# CONFIG_CPU_MIPSR2 is not set
+# CONFIG_CPU_MIPSR2_IRQ_EI is not set
+# CONFIG_CPU_MIPSR2_IRQ_VI is not set
+CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
+# CONFIG_CPU_NEVADA is not set
+CONFIG_CPU_R4K_CACHE_TLB=y
+# CONFIG_CPU_RM7000 is not set
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_CRC32=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CSRC_R4K=y
+CONFIG_DMA_NONCOHERENT=y
+CONFIG_DNOTIFY=y
+CONFIG_DTC=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_EXT4_FS=y
+CONFIG_F2FS_FS=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FUNCTION_ALIGNMENT=0
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC11_NO_ARRAY_BOUNDS=y
+CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_GENERIC_LIB_ASHLDI3=y
+CONFIG_GENERIC_LIB_ASHRDI3=y
+CONFIG_GENERIC_LIB_CMPDI2=y
+CONFIG_GENERIC_LIB_LSHRDI3=y
+CONFIG_GENERIC_LIB_UCMPDI2=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GLOB=y
+CONFIG_GPIO_CDEV=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HW_CONSOLE=y
+CONFIG_I8253=y
+CONFIG_I8253_LOCK=y
+CONFIG_I8259=y
+CONFIG_INPUT=y
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_MIPS_CPU=y
+CONFIG_IRQ_WORK=y
+CONFIG_ISA_DMA_API=y
+CONFIG_JBD2=y
+CONFIG_JFFS2_FS_POSIX_ACL=y
+CONFIG_JFFS2_FS_SECURITY=y
+CONFIG_KALLSYMS=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_XZ is not set
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_MD=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MIPS=y
+CONFIG_MIPS_ASID_BITS=8
+CONFIG_MIPS_ASID_SHIFT=0
+CONFIG_MIPS_BONITO64=y
+CONFIG_MIPS_CLOCK_VSYSCALL=y
+CONFIG_MIPS_CM=y
+CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y
+CONFIG_MIPS_CPC=y
+CONFIG_MIPS_CPU_SCACHE=y
+CONFIG_MIPS_EXTERNAL_TIMER=y
+CONFIG_MIPS_GIC=y
+CONFIG_MIPS_L1_CACHE_SHIFT=6
+CONFIG_MIPS_L1_CACHE_SHIFT_6=y
+CONFIG_MIPS_MALTA=y
+CONFIG_MIPS_MSC=y
+CONFIG_MIPS_MT=y
+CONFIG_MIPS_MT_FPAFF=y
+CONFIG_MIPS_MT_SMP=y
+CONFIG_MIPS_NO_APPENDED_DTB=y
+CONFIG_MIPS_NR_CPU_NR_MAP=2
+CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MTD_CFI_STAA=y
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_SRCU_NMI_SAFE=y
+CONFIG_NET_EGRESS=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_XGRESS=y
+CONFIG_NLS=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+CONFIG_NO_HZ=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=2
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_PADATA=y
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_PATA_LEGACY=y
+CONFIG_PATA_TIMINGS=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DRIVERS_LEGACY=y
+CONFIG_PCI_GT64XXX_PCI0=y
+CONFIG_PCSPKR_PLATFORM=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_PIIX4_POWEROFF=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_QFMT_V2=y
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_QUOTA=y
+CONFIG_QUOTACTL=y
+CONFIG_QUOTA_TREE=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RATIONAL=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_RELAY=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_MC146818_LIB=y
+CONFIG_SATA_HOST=y
+CONFIG_SCSI=y
+CONFIG_SCSI_COMMON=y
+CONFIG_SECCOMP=y
+CONFIG_SECCOMP_FILTER=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SG_POOL=y
+CONFIG_SMP=y
+CONFIG_SMP_UP=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
+CONFIG_SWAP_IO_SPACE=y
+CONFIG_SYNC_R4K=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_SYS_HAS_CPU_MIPS32_R3_5=y
+CONFIG_SYS_HAS_CPU_MIPS32_R5=y
+CONFIG_SYS_HAS_CPU_MIPS32_R6=y
+CONFIG_SYS_HAS_CPU_MIPS64_R1=y
+CONFIG_SYS_HAS_CPU_MIPS64_R2=y
+CONFIG_SYS_HAS_CPU_MIPS64_R6=y
+CONFIG_SYS_HAS_CPU_NEVADA=y
+CONFIG_SYS_HAS_CPU_RM7000=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
+CONFIG_SYS_SUPPORTS_HIGHMEM=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_MICROMIPS=y
+CONFIG_SYS_SUPPORTS_MIPS16=y
+CONFIG_SYS_SUPPORTS_MIPS_CPS=y
+CONFIG_SYS_SUPPORTS_MULTITHREADING=y
+CONFIG_SYS_SUPPORTS_RELOCATABLE=y
+CONFIG_SYS_SUPPORTS_SCHED_SMT=y
+CONFIG_SYS_SUPPORTS_SMARTMIPS=y
+CONFIG_SYS_SUPPORTS_SMP=y
+CONFIG_SYS_SUPPORTS_VPE_LOADER=y
+CONFIG_SYS_SUPPORTS_ZBOOT=y
+CONFIG_TARGET_ISA_REV=1
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_VXFS_FS=y
+CONFIG_WAR_ICACHE_REFILLS=y
+CONFIG_XPS=y
+CONFIG_ZBOOT_LOAD_ADDRESS=0x0
fw_setenv ethaddr "$(cat /sys/class/net/eth0/address)"
;;
bananapi,bpi-r3|\
-bananapi,bpi-r3-mini)
+bananapi,bpi-r3-mini|\
+bananapi,bpi-4)
[ -z "$(fw_printenv -n ethaddr 2>/dev/null)" ] &&
fw_setenv ethaddr "$(cat /sys/class/net/eth0/address)"
[ -z "$(fw_printenv -n eth1addr 2>/dev/null)" ] &&
&mdio {
switch@1f {
compatible = "mediatek,mt7531";
- reg = <0x1f>;
+ reg = <31>;
reset-gpios = <&pio 54 GPIO_ACTIVE_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
- switch: switch@0 {
+ switch: switch@1f {
compatible = "mediatek,mt7531";
- reg = <0>;
+ reg = <31>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&pio>;
#address-cells = <1>;
#size-cells = <0>;
- switch@0 {
+ switch@1f {
compatible = "mediatek,mt7531";
- reg = <0>;
+ reg = <31>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&pio>;
#address-cells = <1>;
#size-cells = <0>;
- switch@0 {
+ switch@1f {
compatible = "mediatek,mt7531";
- reg = <0>;
+ reg = <31>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&pio>;
#address-cells = <1>;
#size-cells = <0>;
- switch@0 {
+ switch@1f {
compatible = "mediatek,mt7531";
- reg = <0>;
+ reg = <31>;
reset-gpios = <&pio 54 GPIO_ACTIVE_HIGH>;
interrupt-controller;
#interrupt-cells = <2>;
#address-cells = <1>;
#size-cells = <0>;
- switch@0 {
+ switch@1f {
compatible = "mediatek,mt7531";
- reg = <0>;
+ reg = <31>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&pio>;
reg = <0>;
};
- switch@2 {
+ switch@1f {
compatible = "mediatek,mt7531";
- reg = <2>;
+ reg = <31>;
reset-gpios = <&pio 28 0>;
interrupt-controller;
#interrupt-cells = <1>;
&mdio_bus {
switch: switch@1f {
compatible = "mediatek,mt7531";
- reg = <0x1f>;
+ reg = <31>;
reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
};
chosen {
+ bootargs-override = "root=/dev/fit0 rootwait";
stdout-path = "serial0:115200n8";
+ rootdisk = <&emmc_rootdisk>;
};
memory@40000000 {
vmmc-supply = <®_3p3v>;
vqmmc-supply = <®_1p8v>;
status = "okay";
+
+ card@0 {
+ compatible = "mmc-card";
+ reg = <0>;
+
+ block {
+ compatible = "block-device";
+ partitions {
+ emmc_rootdisk: block-partition-production {
+ partname = "production";
+ };
+ };
+ };
+ };
};
&pio {
/ {
model = "Bananapi BPI-R4";
compatible = "bananapi,bpi-r4",
- "mediatek,mt7988";
+ "mediatek,mt7988a";
aliases {
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
serial0 = &uart0;
led-boot = &led_green;
led-failsafe = &led_green;
/ {
model = "MediaTek MT7988A Reference Board";
compatible = "mediatek,mt7988a-rfb",
- "mediatek,mt7988";
+ "mediatek,mt7988a";
chosen {
bootargs = "console=ttyS0,115200n1 loglevel=8 \
#define MT7988_TOPRGU_XFI_PLL_GRST 16
/ {
- compatible = "mediatek,mt7988";
+ compatible = "mediatek,mt7988a";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
/ {
model = "Bananapi BPI-R4";
compatible = "bananapi,bpi-r4",
- "mediatek,mt7988";
+ "mediatek,mt7988a";
aliases {
serial0 = &uart0;
/ {
model = "MediaTek MT7988A Reference Board";
compatible = "mediatek,mt7988a-rfb",
- "mediatek,mt7988";
+ "mediatek,mt7988a";
chosen {
bootargs = "console=ttyS0,115200n1 loglevel=8 \
#define MT7988_TOPRGU_XFI_PLL_GRST 16
/ {
- compatible = "mediatek,mt7988";
+ compatible = "mediatek,mt7988a";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
local label_mac=""
case $board in
- bananapi,bpi-r3)
+ bananapi,bpi-r3|\
+ bananapi,bpi-r3-mini|\
+ bananapi,bpi-r4)
wan_mac=$(macaddr_add $(cat /sys/class/net/eth0/address) 1)
;;
cmcc,rax3000m)
[ "$PHYNBR" = "0" ] && macaddr_setbit_la $(macaddr_add $addr 1) > /sys${DEVPATH}/macaddress
[ "$PHYNBR" = "1" ] && echo "$addr" > /sys${DEVPATH}/macaddress
;;
- bananapi,bpi-r3)
+ bananapi,bpi-r3|\
+ bananapi,bpi-r3-mini)
addr=$(cat /sys/class/net/eth0/address)
[ "$PHYNBR" = "0" ] && macaddr_add $addr 2 > /sys${DEVPATH}/macaddress
[ "$PHYNBR" = "1" ] && macaddr_add $addr 3 > /sys${DEVPATH}/macaddress
;;
+ bananapi,bpi-r4)
+ addr=$(cat /sys/class/net/eth0/address)
+ [ "$PHYNBR" = "0" ] && macaddr_add $addr 2 > /sys${DEVPATH}/macaddress
+ [ "$PHYNBR" = "1" ] && macaddr_add $addr 3 > /sys${DEVPATH}/macaddress
+ [ "$PHYNBR" = "2" ] && macaddr_add $addr 4 > /sys${DEVPATH}/macaddress
+ ;;
cetron,ct3003)
addr=$(mtd_get_mac_binary "art" 0)
[ "$PHYNBR" = "0" ] && macaddr_add $addr 1 > /sys${DEVPATH}/macaddress
bananapi,bpi-r3|\
bananapi,bpi-r3-mini|\
bananapi,bpi-r4|\
+ jdcloud,re-cp-03|\
tplink,tl-xdr4288|\
tplink,tl-xdr6086|\
tplink,tl-xdr6088|\
CI_KERNPART="fit"
nand_do_upgrade "$1"
;;
- jdcloud,re-cp-03)
- CI_KERNPART="production"
- emmc_do_upgrade "$1"
- ;;
mercusys,mr90x-v1)
CI_UBIPART="ubi0"
nand_do_upgrade "$1"
-From 4983a1517e7ddbc6f53fc07607e4ebeb51412843 Mon Sep 17 00:00:00 2001
+From patchwork Fri Apr 19 16:59:07 2024
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
+X-Patchwork-Id: 13636668
+Return-Path:
+ <linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org>
+Date: Fri, 19 Apr 2024 17:59:07 +0100
+From: Daniel Golle <daniel@makrotopia.org>
+To: "Rafael J. Wysocki" <rafael@kernel.org>,
+ Viresh Kumar <viresh.kumar@linaro.org>,
+ Matthias Brugger <matthias.bgg@gmail.com>,
+ AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
+ linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org,
+ linux-arm-kernel@lists.infradead.org,
+ linux-mediatek@lists.infradead.org
+Subject: [PATCH] cpufreq: mediatek: Add support for MT7988A
+Message-ID:
+ <acf4fb446aacfbf6ce7b6e94bf3aad303e0ad4d1.1713545923.git.daniel@makrotopia.org>
+Content-Disposition: inline
+List-Id: <linux-mediatek.lists.infradead.org>
+
From: Sam Shih <sam.shih@mediatek.com>
-Date: Tue, 28 Feb 2023 19:59:22 +0800
-Subject: [PATCH 21/21] cpufreq: mediatek: Add support for MT7988
-This add cpufreq support for mediatek MT7988 SoC.
+This add cpufreq support for mediatek MT7988A SoC.
-The platform data of MT7988 is different from previous MediaTek SoCs,
+The platform data of MT7988A is different from previous MediaTek SoCs,
so we add a new compatible and platform data for it.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
{ .compatible = "mediatek,mt2712", .data = &mt2701_platform_data },
{ .compatible = "mediatek,mt7622", .data = &mt7622_platform_data },
{ .compatible = "mediatek,mt7623", .data = &mt7623_platform_data },
-+ { .compatible = "mediatek,mt7988", .data = &mt7988_platform_data },
++ { .compatible = "mediatek,mt7988a", .data = &mt7988_platform_data },
{ .compatible = "mediatek,mt8167", .data = &mt8516_platform_data },
{ .compatible = "mediatek,mt817x", .data = &mt2701_platform_data },
{ .compatible = "mediatek,mt8173", .data = &mt2701_platform_data },
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
-@@ -2900,6 +2900,18 @@ static const struct flash_info *spi_nor_
+@@ -2922,6 +2922,18 @@ static const struct flash_info *spi_nor_
return NULL;
}
static const struct flash_info *spi_nor_get_flash_info(struct spi_nor *nor,
const char *name)
{
-@@ -3003,6 +3015,9 @@ int spi_nor_scan(struct spi_nor *nor, co
+@@ -3025,6 +3037,9 @@ int spi_nor_scan(struct spi_nor *nor, co
if (!nor->bouncebuf)
return -ENOMEM;
--- /dev/null
+From 967da67a745fb73fd0fc7aa61fd197b76fceb273 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Fri, 21 Apr 2023 00:23:21 +0100
+Subject: [PATCH] pwm: mediatek: Add support for MT7981
+
+The PWM unit on MT7981 uses different register offsets than previous
+MediaTek PWM units. Add support for these new offsets and add support
+for PWM on MT7981 which has 3 PWM channels, one of them is typically
+used for a temperature controlled fan.
+While at it, also reorder pwm_mediatek_of_data entries to restore
+alphabetic order.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
+Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
+---
+ drivers/pwm/pwm-mediatek.c | 39 ++++++++++++++++++++++++++++++--------
+ 1 file changed, 31 insertions(+), 8 deletions(-)
+
+--- a/drivers/pwm/pwm-mediatek.c
++++ b/drivers/pwm/pwm-mediatek.c
+@@ -38,6 +38,7 @@ struct pwm_mediatek_of_data {
+ unsigned int num_pwms;
+ bool pwm45_fixup;
+ bool has_ck_26m_sel;
++ const unsigned int *reg_offset;
+ };
+
+ /**
+@@ -59,10 +60,14 @@ struct pwm_mediatek_chip {
+ const struct pwm_mediatek_of_data *soc;
+ };
+
+-static const unsigned int pwm_mediatek_reg_offset[] = {
++static const unsigned int mtk_pwm_reg_offset_v1[] = {
+ 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
+ };
+
++static const unsigned int mtk_pwm_reg_offset_v2[] = {
++ 0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240
++};
++
+ static inline struct pwm_mediatek_chip *
+ to_pwm_mediatek_chip(struct pwm_chip *chip)
+ {
+@@ -111,7 +116,7 @@ static inline void pwm_mediatek_writel(s
+ unsigned int num, unsigned int offset,
+ u32 value)
+ {
+- writel(value, chip->regs + pwm_mediatek_reg_offset[num] + offset);
++ writel(value, chip->regs + chip->soc->reg_offset[num] + offset);
+ }
+
+ static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
+@@ -285,60 +290,77 @@ static const struct pwm_mediatek_of_data
+ .num_pwms = 8,
+ .pwm45_fixup = false,
+ .has_ck_26m_sel = false,
++ .reg_offset = mtk_pwm_reg_offset_v1,
+ };
+
+ static const struct pwm_mediatek_of_data mt6795_pwm_data = {
+ .num_pwms = 7,
+ .pwm45_fixup = false,
+ .has_ck_26m_sel = false,
++ .reg_offset = mtk_pwm_reg_offset_v1,
+ };
+
+ static const struct pwm_mediatek_of_data mt7622_pwm_data = {
+ .num_pwms = 6,
+ .pwm45_fixup = false,
+ .has_ck_26m_sel = true,
++ .reg_offset = mtk_pwm_reg_offset_v1,
+ };
+
+ static const struct pwm_mediatek_of_data mt7623_pwm_data = {
+ .num_pwms = 5,
+ .pwm45_fixup = true,
+ .has_ck_26m_sel = false,
++ .reg_offset = mtk_pwm_reg_offset_v1,
+ };
+
+ static const struct pwm_mediatek_of_data mt7628_pwm_data = {
+ .num_pwms = 4,
+ .pwm45_fixup = true,
+ .has_ck_26m_sel = false,
++ .reg_offset = mtk_pwm_reg_offset_v1,
+ };
+
+ static const struct pwm_mediatek_of_data mt7629_pwm_data = {
+ .num_pwms = 1,
+ .pwm45_fixup = false,
+ .has_ck_26m_sel = false,
++ .reg_offset = mtk_pwm_reg_offset_v1,
+ };
+
+-static const struct pwm_mediatek_of_data mt8183_pwm_data = {
+- .num_pwms = 4,
++static const struct pwm_mediatek_of_data mt7981_pwm_data = {
++ .num_pwms = 3,
+ .pwm45_fixup = false,
+ .has_ck_26m_sel = true,
++ .reg_offset = mtk_pwm_reg_offset_v2,
+ };
+
+-static const struct pwm_mediatek_of_data mt8365_pwm_data = {
+- .num_pwms = 3,
++static const struct pwm_mediatek_of_data mt7986_pwm_data = {
++ .num_pwms = 2,
+ .pwm45_fixup = false,
+ .has_ck_26m_sel = true,
++ .reg_offset = mtk_pwm_reg_offset_v1,
+ };
+
+-static const struct pwm_mediatek_of_data mt7986_pwm_data = {
+- .num_pwms = 2,
++static const struct pwm_mediatek_of_data mt8183_pwm_data = {
++ .num_pwms = 4,
++ .pwm45_fixup = false,
++ .has_ck_26m_sel = true,
++ .reg_offset = mtk_pwm_reg_offset_v1,
++};
++
++static const struct pwm_mediatek_of_data mt8365_pwm_data = {
++ .num_pwms = 3,
+ .pwm45_fixup = false,
+ .has_ck_26m_sel = true,
++ .reg_offset = mtk_pwm_reg_offset_v1,
+ };
+
+ static const struct pwm_mediatek_of_data mt8516_pwm_data = {
+ .num_pwms = 5,
+ .pwm45_fixup = false,
+ .has_ck_26m_sel = true,
++ .reg_offset = mtk_pwm_reg_offset_v1,
+ };
+
+ static const struct of_device_id pwm_mediatek_of_match[] = {
+@@ -348,6 +370,7 @@ static const struct of_device_id pwm_med
+ { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
+ { .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data },
+ { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
++ { .compatible = "mediatek,mt7981-pwm", .data = &mt7981_pwm_data },
+ { .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data },
+ { .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data },
+ { .compatible = "mediatek,mt8365-pwm", .data = &mt8365_pwm_data },
--- /dev/null
+From eb58bf4afd708eb3c64c7b9b2c5fbfacdcdee3e5 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Wed, 14 Feb 2024 15:04:54 +0100
+Subject: [PATCH] pwm: mediatek: add support for MT7988
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+MT7988 uses new registers layout just like MT7981 but it supports 8 PWM
+interfaces.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Reviewed-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Link: https://lore.kernel.org/r/20240214140454.6438-2-zajec5@gmail.com
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/pwm/pwm-mediatek.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/drivers/pwm/pwm-mediatek.c
++++ b/drivers/pwm/pwm-mediatek.c
+@@ -342,6 +342,13 @@ static const struct pwm_mediatek_of_data
+ .reg_offset = mtk_pwm_reg_offset_v1,
+ };
+
++static const struct pwm_mediatek_of_data mt7988_pwm_data = {
++ .num_pwms = 8,
++ .pwm45_fixup = false,
++ .has_ck_26m_sel = false,
++ .reg_offset = mtk_pwm_reg_offset_v2,
++};
++
+ static const struct pwm_mediatek_of_data mt8183_pwm_data = {
+ .num_pwms = 4,
+ .pwm45_fixup = false,
+@@ -372,6 +379,7 @@ static const struct of_device_id pwm_med
+ { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
+ { .compatible = "mediatek,mt7981-pwm", .data = &mt7981_pwm_data },
+ { .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data },
++ { .compatible = "mediatek,mt7988-pwm", .data = &mt7988_pwm_data },
+ { .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data },
+ { .compatible = "mediatek,mt8365-pwm", .data = &mt8365_pwm_data },
+ { .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data },
--- /dev/null
+--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+@@ -145,9 +145,9 @@
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+- switch@0 {
++ switch@1f {
+ compatible = "mediatek,mt7531";
+- reg = <0>;
++ reg = <31>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&pio>;
+--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
++++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+@@ -117,9 +117,9 @@
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+- switch@0 {
++ switch@1f {
+ compatible = "mediatek,mt7531";
+- reg = <0>;
++ reg = <31>;
+ reset-gpios = <&pio 54 0>;
+
+ ports {
-From 4983a1517e7ddbc6f53fc07607e4ebeb51412843 Mon Sep 17 00:00:00 2001
+From patchwork Fri Apr 19 16:59:07 2024
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
+X-Patchwork-Id: 13636668
+Return-Path:
+ <linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org>
+Date: Fri, 19 Apr 2024 17:59:07 +0100
+From: Daniel Golle <daniel@makrotopia.org>
+To: "Rafael J. Wysocki" <rafael@kernel.org>,
+ Viresh Kumar <viresh.kumar@linaro.org>,
+ Matthias Brugger <matthias.bgg@gmail.com>,
+ AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
+ linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org,
+ linux-arm-kernel@lists.infradead.org,
+ linux-mediatek@lists.infradead.org
+Subject: [PATCH] cpufreq: mediatek: Add support for MT7988A
+Message-ID:
+ <acf4fb446aacfbf6ce7b6e94bf3aad303e0ad4d1.1713545923.git.daniel@makrotopia.org>
+Content-Disposition: inline
+List-Id: <linux-mediatek.lists.infradead.org>
+
From: Sam Shih <sam.shih@mediatek.com>
-Date: Tue, 28 Feb 2023 19:59:22 +0800
-Subject: [PATCH 21/21] cpufreq: mediatek: Add support for MT7988
-This add cpufreq support for mediatek MT7988 SoC.
+This add cpufreq support for mediatek MT7988A SoC.
-The platform data of MT7988 is different from previous MediaTek SoCs,
+The platform data of MT7988A is different from previous MediaTek SoCs,
so we add a new compatible and platform data for it.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
{ .compatible = "mediatek,mt2712", .data = &mt2701_platform_data },
{ .compatible = "mediatek,mt7622", .data = &mt7622_platform_data },
{ .compatible = "mediatek,mt7623", .data = &mt7623_platform_data },
-+ { .compatible = "mediatek,mt7988", .data = &mt7988_platform_data },
++ { .compatible = "mediatek,mt7988a", .data = &mt7988_platform_data },
{ .compatible = "mediatek,mt8167", .data = &mt8516_platform_data },
{ .compatible = "mediatek,mt817x", .data = &mt2701_platform_data },
{ .compatible = "mediatek,mt8173", .data = &mt2701_platform_data },
--- /dev/null
+From eb58bf4afd708eb3c64c7b9b2c5fbfacdcdee3e5 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Wed, 14 Feb 2024 15:04:54 +0100
+Subject: [PATCH] pwm: mediatek: add support for MT7988
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+MT7988 uses new registers layout just like MT7981 but it supports 8 PWM
+interfaces.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Reviewed-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Link: https://lore.kernel.org/r/20240214140454.6438-2-zajec5@gmail.com
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+---
+ drivers/pwm/pwm-mediatek.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/drivers/pwm/pwm-mediatek.c
++++ b/drivers/pwm/pwm-mediatek.c
+@@ -341,6 +341,13 @@ static const struct pwm_mediatek_of_data
+ .reg_offset = mtk_pwm_reg_offset_v1,
+ };
+
++static const struct pwm_mediatek_of_data mt7988_pwm_data = {
++ .num_pwms = 8,
++ .pwm45_fixup = false,
++ .has_ck_26m_sel = false,
++ .reg_offset = mtk_pwm_reg_offset_v2,
++};
++
+ static const struct pwm_mediatek_of_data mt8183_pwm_data = {
+ .num_pwms = 4,
+ .pwm45_fixup = false,
+@@ -371,6 +378,7 @@ static const struct of_device_id pwm_med
+ { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
+ { .compatible = "mediatek,mt7981-pwm", .data = &mt7981_pwm_data },
+ { .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data },
++ { .compatible = "mediatek,mt7988-pwm", .data = &mt7988_pwm_data },
+ { .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data },
+ { .compatible = "mediatek,mt8365-pwm", .data = &mt8365_pwm_data },
+ { .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data },
--- a/drivers/net/ethernet/mediatek/mtk_wed.c
+++ b/drivers/net/ethernet/mediatek/mtk_wed.c
-@@ -1321,6 +1321,24 @@ mtk_wed_rro_alloc(struct mtk_wed_device
+@@ -1320,6 +1320,24 @@ mtk_wed_rro_alloc(struct mtk_wed_device
struct device_node *np;
int index;
index = of_property_match_string(dev->hw->node, "memory-region-names",
"wo-dlm");
if (index < 0)
-@@ -1337,6 +1355,7 @@ mtk_wed_rro_alloc(struct mtk_wed_device
+@@ -1336,6 +1354,7 @@ mtk_wed_rro_alloc(struct mtk_wed_device
return -ENODEV;
dev->rro.miod_phys = rmem->base;
+++ /dev/null
-From: Felix Fietkau <nbd@nbd.name>
-Date: Thu, 18 Jan 2024 12:51:32 +0100
-Subject: [PATCH] net: ethernet: mtk_eth_soc: fix WED + wifi reset
-
-The WLAN + WED reset sequence relies on being able to receive interrupts from
-the card, in order to synchronize individual steps with the firmware.
-When WED is stopped, leave interrupts running and rely on the driver turning
-off unwanted ones.
-WED DMA also needs to be disabled before resetting.
-
-Fixes: f78cd9c783e0 ("net: ethernet: mtk_wed: update mtk_wed_stop")
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
-
---- a/drivers/net/ethernet/mediatek/mtk_wed.c
-+++ b/drivers/net/ethernet/mediatek/mtk_wed.c
-@@ -1072,13 +1072,13 @@ mtk_wed_dma_disable(struct mtk_wed_devic
- static void
- mtk_wed_stop(struct mtk_wed_device *dev)
- {
-+ mtk_wed_dma_disable(dev);
- mtk_wed_set_ext_int(dev, false);
-
- wed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER, 0);
- wed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, 0);
- wdma_w32(dev, MTK_WDMA_INT_MASK, 0);
- wdma_w32(dev, MTK_WDMA_INT_GRP2, 0);
-- wed_w32(dev, MTK_WED_WPDMA_INT_MASK, 0);
-
- if (!mtk_wed_get_rx_capa(dev))
- return;
-@@ -1091,7 +1091,6 @@ static void
- mtk_wed_deinit(struct mtk_wed_device *dev)
- {
- mtk_wed_stop(dev);
-- mtk_wed_dma_disable(dev);
-
- wed_clr(dev, MTK_WED_CTRL,
- MTK_WED_CTRL_WDMA_INT_AGENT_EN |
-@@ -2622,9 +2621,6 @@ mtk_wed_irq_get(struct mtk_wed_device *d
- static void
- mtk_wed_irq_set_mask(struct mtk_wed_device *dev, u32 mask)
- {
-- if (!dev->running)
-- return;
--
- mtk_wed_set_ext_int(dev, !!mask);
- wed_w32(dev, MTK_WED_INT_MASK, mask);
- }
compatible = "enterasys,ws-ap3710i";
aliases {
+ ethernet0 = &enet0;
+ ethernet1 = &enet2;
led-boot = &led_power_green;
led-failsafe = &led_power_red;
led-running = &led_power_green;
label-mac-device = &enet0;
};
+ chosen {
+ bootargs-override = "console=ttyS0,115200";
+ stdout-path = &serial0;
+ };
+
memory {
device_type = "memory";
};
#size-cells = <1>;
partition@0 {
- compatible = "denx,fit";
+ compatible = "denx,uimage";
reg = <0x0 0x1d80000>;
label = "firmware";
};
ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
reg = <0 0xffe09000 0 0x1000>;
+
+ /* Filled by U-Boot */
+ bus-range = <0x00 0x01>;
+ dma-ranges = <0x2000000 0x00 0xfff00000 0x00 0xffe00000
+ 0x00 0x100000 0x42000000 0x00 0x00 0x00
+ 0x00 0x00 0x10000000>;
+
pcie@0 {
ranges = <0x2000000 0x0 0xa0000000
0x2000000 0x0 0xa0000000
reg = <0 0xffe0a000 0 0x1000>;
ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
+
+ /* Filled by U-Boot */
+ bus-range = <0x00 0x01>;
+ dma-ranges = <0x2000000 0x00 0xfff00000 0x00
+ 0xffe00000 0x00 0x100000 0x42000000
+ 0x00 0x00 0x00 0x00 0x00 0x10000000>;
+
pcie@0 {
ranges = <0x2000000 0x0 0x80000000
0x2000000 0x0 0x80000000
};
/include/ "fsl/p1020si-post.dtsi"
+/ {
+ cpus {
+ PowerPC,P1020@0 {
+ bus-frequency = <399999996>;
+ timebase-frequency = <50000000>;
+ clock-frequency = <799999992>;
+ d-cache-block-size = <0x20>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <0x80>;
+ i-cache-block-size = <0x20>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <0x80>;
+ cpu-release-addr = <0x0 0x0ffff280>;
+ status = "okay";
+ enable-method = "spin-table";
+ };
+
+ PowerPC,P1020@1 {
+ bus-frequency = <399999996>;
+ timebase-frequency = <50000000>;
+ clock-frequency = <799999992>;
+ d-cache-block-size = <0x20>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <0x80>;
+ i-cache-block-size = <0x20>;
+ i-cache-size = <0x8000>;
+ i-cache-sets = <0x80>;
+ cpu-release-addr = <0x0 0x0ffff2a0>;
+ status = "disabled";
+ enable-method = "spin-table";
+ };
+ };
+
+ memory {
+ reg = <0x0 0x0 0x0 0x10000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ cpu1-bootpage@ff00000 {
+ /* Reserve upper 1 MB for second-core-bootpage */
+ reg = <0x0 0xff00000 0x0 0x100000>;
+ };
+ };
+
+ soc@ffe00000 {
+ bus-frequency = <399999996>;
+
+ serial@4600 {
+ clock-frequency = <399999996>;
+ };
+
+ serial@4500 {
+ clock-frequency = <399999996>;
+ };
+
+ pic@40000 {
+ clock-frequency = <399999996>;
+ };
+ };
+
+ localbus@ffe05000 {
+ bus-frequency = <24999999>;
+ };
+};
+
+&enet0 {
+ rx-stash-idx = <0x00>;
+ rx-stash-len = <0x60>;
+ bd-stash;
+};
+
+&enet2 {
+ rx-stash-idx = <0x00>;
+ rx-stash-len = <0x60>;
+ bd-stash;
+};
+
/*
* For the OpenWrt 22.03 release, since Linux 5.10.138 now uses
* aliases to determine PCI domain numbers, drop aliases so as not to
DEVICE_VENDOR := Enterasys
DEVICE_MODEL := WS-AP3710i
BLOCKSIZE := 128k
- KERNEL = kernel-bin | lzma | fit lzma $(KDIR)/image-$$(DEVICE_DTS).dtb
+ KERNEL_NAME := simpleImage.ws-ap3710i
+ KERNEL_ENTRY := 0x1500000
+ KERNEL_LOADADDR := 0x1500000
+ KERNEL = kernel-bin | uImage none
+ KERNEL_INITRAMFS := kernel-bin | uImage none
IMAGES := sysupgrade.bin
IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata
endef
DEVICE_PACKAGES := kmod-ath10k-ct ath10k-firmware-qca988x-ct
BLOCKSIZE := 128k
KERNEL_NAME := simpleImage.ws-ap3825i
- KERNEL_ENTRY := 0x1000000
- KERNEL_LOADADDR := 0x1000000
+ KERNEL_ENTRY := 0x1500000
+ KERNEL_LOADADDR := 0x1500000
KERNEL = kernel-bin | fit none $(KDIR)/image-$$(DEVICE_DTS).dtb
IMAGES := sysupgrade.bin
IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | append-metadata
BOARDNAME:=P1020
-KERNEL_IMAGES:=simpleImage.ws-ap3825i simpleImage.hiveap-330
+KERNEL_IMAGES:=simpleImage.ws-ap3710i simpleImage.ws-ap3825i simpleImage.hiveap-330
define Target/Description
Build firmware images for Freescale P1020 based boards.
obj-$(CONFIG_CORENET_GENERIC) += corenet_generic.o
obj-$(CONFIG_FB_FSL_DIU) += t1042rdb_diu.o
obj-$(CONFIG_RED_15W_REV1) += red15w_rev1.o
+--- a/arch/powerpc/boot/Makefile
++++ b/arch/powerpc/boot/Makefile
+@@ -181,6 +181,7 @@ src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) +=
+ src-plat-$(CONFIG_MVME7100) += motload-head.S mvme7100.c
+ src-plat-$(CONFIG_HIVEAP_330) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_TL_WDR4900_V1) += simpleboot.c fixed-head.S
++src-plat-$(CONFIG_WS_AP3710I) += simpleboot.c fixed-head.S
+
+ src-plat-$(CONFIG_PPC_MICROWATT) += fixed-head.S microwatt.c
+
+@@ -363,6 +364,7 @@ image-$(CONFIG_TQM8560) += cuImage.tqm
+ image-$(CONFIG_KSI8560) += cuImage.ksi8560
+ image-$(CONFIG_HIVEAP_330) += simpleImage.hiveap-330
+ image-$(CONFIG_TL_WDR4900_V1) += simpleImage.tl-wdr4900-v1
++image-$(CONFIG_WS_AP3710I) += simpleImage.ws-ap3710i
+ # Board ports in arch/powerpc/platform/86xx/Kconfig
+ image-$(CONFIG_MVME7100) += dtbImage.mvme7100
+
+--- a/arch/powerpc/boot/wrapper
++++ b/arch/powerpc/boot/wrapper
+@@ -342,7 +342,8 @@ adder875-redboot)
+ binary=y
+ ;;
+ simpleboot-hiveap-330|\
+-simpleboot-tl-wdr4900-v1)
++simpleboot-tl-wdr4900-v1|\
++simpleboot-ws-ap3710i)
+ platformo="$object/fixed-head.o $object/simpleboot.o"
+ link_address='0x1500000'
+ binary=y
obj-$(CONFIG_RED_15W_REV1) += red15w_rev1.o
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
-@@ -181,6 +181,7 @@ src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) +=
- src-plat-$(CONFIG_MVME7100) += motload-head.S mvme7100.c
+@@ -182,6 +182,7 @@ src-plat-$(CONFIG_MVME7100) += motload-h
src-plat-$(CONFIG_HIVEAP_330) += simpleboot.c fixed-head.S
src-plat-$(CONFIG_TL_WDR4900_V1) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_WS_AP3710I) += simpleboot.c fixed-head.S
+src-plat-$(CONFIG_WS_AP3825I) += simpleboot.c fixed-head.S
src-plat-$(CONFIG_PPC_MICROWATT) += fixed-head.S microwatt.c
-@@ -363,6 +364,7 @@ image-$(CONFIG_TQM8560) += cuImage.tqm
- image-$(CONFIG_KSI8560) += cuImage.ksi8560
+@@ -365,6 +366,7 @@ image-$(CONFIG_KSI8560) += cuImage.ksi
image-$(CONFIG_HIVEAP_330) += simpleImage.hiveap-330
image-$(CONFIG_TL_WDR4900_V1) += simpleImage.tl-wdr4900-v1
+ image-$(CONFIG_WS_AP3710I) += simpleImage.ws-ap3710i
+image-$(CONFIG_WS_AP3825I) += simpleImage.ws-ap3825i
# Board ports in arch/powerpc/platform/86xx/Kconfig
image-$(CONFIG_MVME7100) += dtbImage.mvme7100
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
-@@ -342,6 +342,7 @@ adder875-redboot)
- binary=y
+@@ -343,7 +343,8 @@ adder875-redboot)
;;
simpleboot-hiveap-330|\
-+simpleboot-ws-ap3825i|\
- simpleboot-tl-wdr4900-v1)
+ simpleboot-tl-wdr4900-v1|\
+-simpleboot-ws-ap3710i)
++simpleboot-ws-ap3710i|\
++simpleboot-ws-ap3825i)
platformo="$object/fixed-head.o $object/simpleboot.o"
link_address='0x1500000'
+ binary=y
obj-$(CONFIG_CORENET_GENERIC) += corenet_generic.o
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
-@@ -364,6 +364,7 @@ image-$(CONFIG_TQM8560) += cuImage.tqm
- image-$(CONFIG_KSI8560) += cuImage.ksi8560
+@@ -182,6 +182,7 @@ src-plat-$(CONFIG_MVME7100) += motload-h
+ src-plat-$(CONFIG_HIVEAP_330) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_TL_WDR4900_V1) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_WS_AP3710I) += simpleboot.c fixed-head.S
++src-plat-$(CONFIG_WS_AP3715I) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_WS_AP3825I) += simpleboot.c fixed-head.S
+
+ src-plat-$(CONFIG_PPC_MICROWATT) += fixed-head.S microwatt.c
+@@ -366,6 +367,7 @@ image-$(CONFIG_KSI8560) += cuImage.ksi
image-$(CONFIG_HIVEAP_330) += simpleImage.hiveap-330
image-$(CONFIG_TL_WDR4900_V1) += simpleImage.tl-wdr4900-v1
+ image-$(CONFIG_WS_AP3710I) += simpleImage.ws-ap3710i
+image-$(CONFIG_WS_AP3715I) += simpleImage.ws-ap3715i
image-$(CONFIG_WS_AP3825I) += simpleImage.ws-ap3825i
# Board ports in arch/powerpc/platform/86xx/Kconfig
image-$(CONFIG_MVME7100) += dtbImage.mvme7100
---- a/arch/powerpc/boot/wrapper
-+++ b/arch/powerpc/boot/wrapper
-@@ -342,6 +342,7 @@ adder875-redboot)
- binary=y
- ;;
- simpleboot-hiveap-330|\
-+simpleboot-ws-ap3715i|\
- simpleboot-ws-ap3825i|\
- simpleboot-tl-wdr4900-v1)
- platformo="$object/fixed-head.o $object/simpleboot.o"
+src-plat-$(CONFIG_BR200_WP) += simpleboot.c fixed-head.S
src-plat-$(CONFIG_HIVEAP_330) += simpleboot.c fixed-head.S
src-plat-$(CONFIG_TL_WDR4900_V1) += simpleboot.c fixed-head.S
- src-plat-$(CONFIG_WS_AP3825I) += simpleboot.c fixed-head.S
-@@ -362,6 +363,7 @@ image-$(CONFIG_TQM8548) += cuImage.tqm
+ src-plat-$(CONFIG_WS_AP3710I) += simpleboot.c fixed-head.S
+@@ -364,6 +365,7 @@ image-$(CONFIG_TQM8548) += cuImage.tqm
image-$(CONFIG_TQM8555) += cuImage.tqm8555
image-$(CONFIG_TQM8560) += cuImage.tqm8560
image-$(CONFIG_KSI8560) += cuImage.ksi8560
+image-$(CONFIG_BR200_WP) += simpleImage.br200-wp
image-$(CONFIG_HIVEAP_330) += simpleImage.hiveap-330
image-$(CONFIG_TL_WDR4900_V1) += simpleImage.tl-wdr4900-v1
- image-$(CONFIG_WS_AP3715I) += simpleImage.ws-ap3715i
+ image-$(CONFIG_WS_AP3710I) += simpleImage.ws-ap3710i
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
@@ -341,6 +341,7 @@ adder875-redboot)
;;
+simpleboot-br200-wp|\
simpleboot-hiveap-330|\
- simpleboot-ws-ap3715i|\
- simpleboot-ws-ap3825i|\
+ simpleboot-tl-wdr4900-v1|\
+ simpleboot-ws-ap3710i|\
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
-@@ -291,7 +291,6 @@ image-$(CONFIG_PPC_CHRP) += zImage.chrp
+@@ -293,7 +293,6 @@ image-$(CONFIG_PPC_CHRP) += zImage.chrp
image-$(CONFIG_PPC_EFIKA) += zImage.chrp
image-$(CONFIG_PPC_PMAC) += zImage.pmac
image-$(CONFIG_PPC_HOLLY) += dtbImage.holly
image-$(CONFIG_EPAPR_BOOT) += zImage.epapr
#
-@@ -427,15 +426,6 @@ $(obj)/dtbImage.%: vmlinux $(wrapperbits
+@@ -430,15 +429,6 @@ $(obj)/dtbImage.%: vmlinux $(wrapperbits
$(obj)/vmlinux.strip: vmlinux
$(STRIP) -s -R .comment $< -o $@
obj-$(CONFIG_CORENET_GENERIC) += corenet_generic.o
obj-$(CONFIG_FB_FSL_DIU) += t1042rdb_diu.o
obj-$(CONFIG_RED_15W_REV1) += red15w_rev1.o
+--- a/arch/powerpc/boot/Makefile
++++ b/arch/powerpc/boot/Makefile
+@@ -183,6 +183,7 @@ src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) +=
+ src-plat-$(CONFIG_MVME7100) += motload-head.S mvme7100.c
+ src-plat-$(CONFIG_HIVEAP_330) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_TL_WDR4900_V1) += simpleboot.c fixed-head.S
++src-plat-$(CONFIG_WS_AP3710I) += simpleboot.c fixed-head.S
+
+ src-plat-$(CONFIG_PPC_MICROWATT) += fixed-head.S microwatt.c
+
+@@ -355,6 +356,7 @@ image-$(CONFIG_TQM8560) += cuImage.tqm
+ image-$(CONFIG_KSI8560) += cuImage.ksi8560
+ image-$(CONFIG_HIVEAP_330) += simpleImage.hiveap-330
+ image-$(CONFIG_TL_WDR4900_V1) += simpleImage.tl-wdr4900-v1
++image-$(CONFIG_WS_AP3710I) += simpleImage.ws-ap3710i
+ # Board ports in arch/powerpc/platform/86xx/Kconfig
+ image-$(CONFIG_MVME7100) += dtbImage.mvme7100
+
+--- a/arch/powerpc/boot/wrapper
++++ b/arch/powerpc/boot/wrapper
+@@ -346,7 +346,8 @@ adder875-redboot)
+ binary=y
+ ;;
+ simpleboot-hiveap-330|\
+-simpleboot-tl-wdr4900-v1)
++simpleboot-tl-wdr4900-v1|\
++simpleboot-ws-ap3710i)
+ platformo="$object/fixed-head.o $object/simpleboot.o"
+ link_address='0x1500000'
+ binary=y
obj-$(CONFIG_RED_15W_REV1) += red15w_rev1.o
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
-@@ -183,6 +183,7 @@ src-plat-$(CONFIG_PPC_IBM_CELL_BLADE) +=
- src-plat-$(CONFIG_MVME7100) += motload-head.S mvme7100.c
+@@ -184,6 +184,7 @@ src-plat-$(CONFIG_MVME7100) += motload-h
src-plat-$(CONFIG_HIVEAP_330) += simpleboot.c fixed-head.S
src-plat-$(CONFIG_TL_WDR4900_V1) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_WS_AP3710I) += simpleboot.c fixed-head.S
+src-plat-$(CONFIG_WS_AP3825I) += simpleboot.c fixed-head.S
src-plat-$(CONFIG_PPC_MICROWATT) += fixed-head.S microwatt.c
-@@ -355,6 +356,7 @@ image-$(CONFIG_TQM8560) += cuImage.tqm
- image-$(CONFIG_KSI8560) += cuImage.ksi8560
+@@ -357,6 +358,7 @@ image-$(CONFIG_KSI8560) += cuImage.ksi
image-$(CONFIG_HIVEAP_330) += simpleImage.hiveap-330
image-$(CONFIG_TL_WDR4900_V1) += simpleImage.tl-wdr4900-v1
+ image-$(CONFIG_WS_AP3710I) += simpleImage.ws-ap3710i
+image-$(CONFIG_WS_AP3825I) += simpleImage.ws-ap3825i
# Board ports in arch/powerpc/platform/86xx/Kconfig
image-$(CONFIG_MVME7100) += dtbImage.mvme7100
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
-@@ -346,6 +346,7 @@ adder875-redboot)
- binary=y
+@@ -347,7 +347,8 @@ adder875-redboot)
;;
simpleboot-hiveap-330|\
-+simpleboot-ws-ap3825i|\
- simpleboot-tl-wdr4900-v1)
+ simpleboot-tl-wdr4900-v1|\
+-simpleboot-ws-ap3710i)
++simpleboot-ws-ap3710i|\
++simpleboot-ws-ap3825i)
platformo="$object/fixed-head.o $object/simpleboot.o"
link_address='0x1500000'
+ binary=y
obj-$(CONFIG_CORENET_GENERIC) += corenet_generic.o
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
-@@ -356,6 +356,7 @@ image-$(CONFIG_TQM8560) += cuImage.tqm
- image-$(CONFIG_KSI8560) += cuImage.ksi8560
+@@ -184,6 +184,7 @@ src-plat-$(CONFIG_MVME7100) += motload-h
+ src-plat-$(CONFIG_HIVEAP_330) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_TL_WDR4900_V1) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_WS_AP3710I) += simpleboot.c fixed-head.S
++src-plat-$(CONFIG_WS_AP3715I) += simpleboot.c fixed-head.S
+ src-plat-$(CONFIG_WS_AP3825I) += simpleboot.c fixed-head.S
+
+ src-plat-$(CONFIG_PPC_MICROWATT) += fixed-head.S microwatt.c
+@@ -358,6 +359,7 @@ image-$(CONFIG_KSI8560) += cuImage.ksi
image-$(CONFIG_HIVEAP_330) += simpleImage.hiveap-330
image-$(CONFIG_TL_WDR4900_V1) += simpleImage.tl-wdr4900-v1
+ image-$(CONFIG_WS_AP3710I) += simpleImage.ws-ap3710i
+image-$(CONFIG_WS_AP3715I) += simpleImage.ws-ap3715i
image-$(CONFIG_WS_AP3825I) += simpleImage.ws-ap3825i
# Board ports in arch/powerpc/platform/86xx/Kconfig
image-$(CONFIG_MVME7100) += dtbImage.mvme7100
---- a/arch/powerpc/boot/wrapper
-+++ b/arch/powerpc/boot/wrapper
-@@ -346,6 +346,7 @@ adder875-redboot)
- binary=y
- ;;
- simpleboot-hiveap-330|\
-+simpleboot-ws-ap3715i|\
- simpleboot-ws-ap3825i|\
- simpleboot-tl-wdr4900-v1)
- platformo="$object/fixed-head.o $object/simpleboot.o"
+src-plat-$(CONFIG_BR200_WP) += simpleboot.c fixed-head.S
src-plat-$(CONFIG_HIVEAP_330) += simpleboot.c fixed-head.S
src-plat-$(CONFIG_TL_WDR4900_V1) += simpleboot.c fixed-head.S
- src-plat-$(CONFIG_WS_AP3825I) += simpleboot.c fixed-head.S
-@@ -354,6 +355,7 @@ image-$(CONFIG_TQM8548) += cuImage.tqm
+ src-plat-$(CONFIG_WS_AP3710I) += simpleboot.c fixed-head.S
+@@ -356,6 +357,7 @@ image-$(CONFIG_TQM8548) += cuImage.tqm
image-$(CONFIG_TQM8555) += cuImage.tqm8555
image-$(CONFIG_TQM8560) += cuImage.tqm8560
image-$(CONFIG_KSI8560) += cuImage.ksi8560
+image-$(CONFIG_BR200_WP) += simpleImage.br200-wp
image-$(CONFIG_HIVEAP_330) += simpleImage.hiveap-330
image-$(CONFIG_TL_WDR4900_V1) += simpleImage.tl-wdr4900-v1
- image-$(CONFIG_WS_AP3715I) += simpleImage.ws-ap3715i
+ image-$(CONFIG_WS_AP3710I) += simpleImage.ws-ap3710i
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
@@ -345,6 +345,7 @@ adder875-redboot)
;;
+simpleboot-br200-wp|\
simpleboot-hiveap-330|\
- simpleboot-ws-ap3715i|\
- simpleboot-ws-ap3825i|\
+ simpleboot-tl-wdr4900-v1|\
+ simpleboot-ws-ap3710i|\
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
-@@ -293,7 +293,6 @@ image-$(CONFIG_PPC_CHRP) += zImage.chrp
+@@ -295,7 +295,6 @@ image-$(CONFIG_PPC_CHRP) += zImage.chrp
image-$(CONFIG_PPC_EFIKA) += zImage.chrp
image-$(CONFIG_PPC_PMAC) += zImage.pmac
image-$(CONFIG_PPC_HOLLY) += dtbImage.holly
image-$(CONFIG_EPAPR_BOOT) += zImage.epapr
#
-@@ -418,15 +417,6 @@ $(obj)/dtbImage.%: vmlinux $(wrapperbits
+@@ -421,15 +420,6 @@ $(obj)/dtbImage.%: vmlinux $(wrapperbits
$(obj)/vmlinux.strip: vmlinux
$(STRIP) -s -R .comment $< -o $@
static int kernel_init(void *);
/*
-@@ -928,6 +932,18 @@ void start_kernel(void)
+@@ -930,6 +934,18 @@ void start_kernel(void)
boot_cpu_hotplug_init();
pr_notice("Kernel command line: %s\n", saved_command_line);
CPU_TYPE:=arm926ej-s
SUBTARGETS:=generic
-KERNEL_PATCHVER:=6.1
+KERNEL_PATCHVER:=6.6
KERNELNAME:=zImage dtbs
+++ /dev/null
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_FORCE_MAX_ORDER=11
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_CPU_AUTO=y
-# CONFIG_ARCH_MULTI_V4 is not set
-# CONFIG_ARCH_MULTI_V4T is not set
-CONFIG_ARCH_MULTI_V4_V5=y
-CONFIG_ARCH_MULTI_V5=y
-CONFIG_ARCH_MXS=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ATAG_DTB_COMPAT=y
-CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_ARM_CPU_SUSPEND=y
-CONFIG_ARM_L1_CACHE_SHIFT=5
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ATAGS=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_PM=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="console=ttyAMA0,115200 root=/dev/mmcblk0p2 rw rootwait"
-CONFIG_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_COREDUMP=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV5TJ=y
-CONFIG_CPU_ARM926T=y
-# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_COPY_V4WB=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_PABRT_LEGACY=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_USE_DOMAINS=y
-CONFIG_CRC16=y
-CONFIG_CROSS_MEMORY_ATTACH=y
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_DEV_MXS_DCP=y
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_DEBUG_ALIGN_RODATA=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-CONFIG_DMADEVICES=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_OPS=y
-CONFIG_DTC=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EXT4_FS=y
-CONFIG_EXTCON=y
-CONFIG_FEC=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-# CONFIG_GIANFAR is not set
-CONFIG_GLOB=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_GENERIC_PLATFORM=y
-CONFIG_GPIO_MXS=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HZ_FIXED=0
-CONFIG_HZ_PERIODIC=y
-CONFIG_I2C=y
-CONFIG_I2C_ALGOBIT=y
-CONFIG_I2C_ALGOPCA=y
-CONFIG_I2C_ALGOPCF=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_COMPAT=y
-CONFIG_I2C_MUX=y
-CONFIG_I2C_MUX_PINCTRL=y
-CONFIG_I2C_MXS=y
-CONFIG_IIO=y
-CONFIG_IIO_BUFFER=y
-CONFIG_IIO_KFIFO_BUF=y
-CONFIG_IIO_SYSFS_TRIGGER=y
-CONFIG_IIO_TRIGGER=y
-# CONFIG_IIO_TRIGGERED_BUFFER is not set
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_MXS=y
-CONFIG_IRQ_WORK=y
-# CONFIG_ISDN is not set
-CONFIG_JBD2=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MFD_CORE=y
-CONFIG_MFD_MXS_LRADC=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_MXS=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MXS_DMA=y
-# CONFIG_MXS_LRADC_ADC is not set
-CONFIG_MXS_TIMER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_KUSER_HELPERS=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NLS=y
-CONFIG_NVMEM=y
-CONFIG_NVMEM_MXS_OCOTP=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_IMX23=y
-CONFIG_PINCTRL_IMX28=y
-CONFIG_PINCTRL_MXS=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PPS=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_RATIONAL=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_GPIO=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_STMP=y
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RTC_MC146818_LIB=y
-# CONFIG_SERIAL_8250 is not set
-CONFIG_SERIAL_AMBA_PL011=y
-CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_MXS_AUART=y
-CONFIG_SERIAL_MXS_AUART_CONSOLE=y
-CONFIG_SMSC_PHY=y
-CONFIG_SOC_BUS=y
-CONFIG_SOC_IMX23=y
-CONFIG_SOC_IMX28=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MXS=y
-CONFIG_SPLIT_PTLOCK_CPUS=999999
-CONFIG_SRCU=y
-CONFIG_STMP3XXX_RTC_WATCHDOG=y
-CONFIG_STMP_DEVICE=y
-CONFIG_SWPHY=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TINY_SRCU=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-# CONFIG_UNUSED_BOARD_FILES is not set
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB=y
-CONFIG_USB_CHIPIDEA=y
-CONFIG_USB_CHIPIDEA_HOST=y
-CONFIG_USB_CHIPIDEA_IMX=y
-CONFIG_USB_CHIPIDEA_UDC=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_EHCI_HCD=y
-# CONFIG_USB_EHCI_HCD_PLATFORM is not set
-CONFIG_USB_GADGET=y
-CONFIG_USB_MXS_PHY=y
-CONFIG_USB_OTG=y
-CONFIG_USB_PHY=y
-CONFIG_USB_ROLE_SWITCH=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_ULPI_BUS=y
-CONFIG_USE_OF=y
-# CONFIG_VFP is not set
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
--- /dev/null
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MULTIPLATFORM=y
+CONFIG_ARCH_MULTI_CPU_AUTO=y
+# CONFIG_ARCH_MULTI_V4 is not set
+# CONFIG_ARCH_MULTI_V4T is not set
+CONFIG_ARCH_MULTI_V4_V5=y
+CONFIG_ARCH_MULTI_V5=y
+CONFIG_ARCH_MXS=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARM=y
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
+CONFIG_ARM_CPU_SUSPEND=y
+CONFIG_ARM_HAS_GROUP_RELOCS=y
+CONFIG_ARM_L1_CACHE_SHIFT=5
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_UNWIND=y
+CONFIG_ATAGS=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
+CONFIG_BLK_PM=y
+CONFIG_BUFFER_HEAD=y
+CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="console=ttyAMA0,115200 root=/dev/mmcblk0p2 rw rootwait"
+CONFIG_CMDLINE_FROM_BOOTLOADER=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_COREDUMP=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_ARM926T=y
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_PABRT_LEGACY=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_USE_DOMAINS=y
+CONFIG_CRC16=y
+CONFIG_CROSS_MEMORY_ATTACH=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_DEV_MXS_DCP=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_DEBUG_ALIGN_RODATA=y
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+CONFIG_DMADEVICES=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_OPS=y
+CONFIG_DTC=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_EXT4_FS=y
+CONFIG_EXTCON=y
+CONFIG_FEC=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FUNCTION_ALIGNMENT=0
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC11_NO_ARRAY_BOUNDS=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+# CONFIG_GIANFAR is not set
+CONFIG_GLOB=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_GPIO_MXS=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HID_SUPPORT=y
+CONFIG_HZ_FIXED=0
+CONFIG_HZ_PERIODIC=y
+CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_ALGOPCA=y
+CONFIG_I2C_ALGOPCF=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PINCTRL=y
+CONFIG_I2C_MXS=y
+CONFIG_IIO=y
+CONFIG_IIO_BUFFER=y
+CONFIG_IIO_KFIFO_BUF=y
+CONFIG_IIO_SYSFS_TRIGGER=y
+CONFIG_IIO_TRIGGER=y
+# CONFIG_IIO_TRIGGERED_BUFFER is not set
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INPUT=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQSTACKS=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_MXS=y
+CONFIG_IRQ_WORK=y
+# CONFIG_ISDN is not set
+CONFIG_JBD2=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MEMFD_CREATE=y
+CONFIG_MFD_CORE=y
+CONFIG_MFD_MXS_LRADC=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_MXS=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MXS_DMA=y
+# CONFIG_MXS_LRADC_ADC is not set
+CONFIG_MXS_TIMER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_KUSER_HELPERS=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NET_EGRESS=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_XGRESS=y
+CONFIG_NLS=y
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_NVMEM_MXS_OCOTP=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX23=y
+CONFIG_PINCTRL_IMX28=y
+CONFIG_PINCTRL_MXS=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PPS=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_RATIONAL=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_STMP=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RTC_MC146818_LIB=y
+# CONFIG_SERIAL_8250 is not set
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_MXS_AUART=y
+CONFIG_SERIAL_MXS_AUART_CONSOLE=y
+CONFIG_SMSC_PHY=y
+CONFIG_SOC_BUS=y
+CONFIG_SOC_IMX23=y
+CONFIG_SOC_IMX28=y
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MXS=y
+CONFIG_SPLIT_PTLOCK_CPUS=999999
+CONFIG_STMP3XXX_RTC_WATCHDOG=y
+CONFIG_STMP_DEVICE=y
+CONFIG_SWPHY=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TINY_SRCU=y
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNWINDER_ARM=y
+CONFIG_USB=y
+CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_CHIPIDEA_IMX=y
+CONFIG_USB_CHIPIDEA_UDC=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_HCD_PLATFORM is not set
+CONFIG_USB_GADGET=y
+CONFIG_USB_MXS_PHY=y
+CONFIG_USB_OTG=y
+CONFIG_USB_PHY=y
+CONFIG_USB_ROLE_SWITCH=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ULPI_BUS=y
+CONFIG_USE_OF=y
+# CONFIG_VFP is not set
+CONFIG_WATCHDOG_CORE=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_ZBOOT_ROM_TEXT=0
KERNEL_NAME := zImage
KERNEL := kernel-bin | uImage none
IMAGES := sdcard.img.gz
+ DTS_DIR := $(DTS_DIR)/nxp/mxs
DEVICE_DTS = $$(SOC)-$(lastword $(subst _, ,$(1)))
endef
+++ /dev/null
-include $(TOPDIR)/rules.mk
-
-ARCH:=arm
-BOARD:=oxnas
-BOARDNAME:=PLXTECH/Oxford NAS782x/OX8xx
-SUBTARGETS:=ox810se ox820
-FEATURES:=gpio ramdisk rtc squashfs
-DEVICE_TYPE:=nas
-
-KERNEL_PATCHVER:=5.15
-
-include $(INCLUDE_DIR)/target.mk
-
-DEFAULT_PACKAGES += \
- kmod-button-hotplug kmod-input-gpio-keys-polled \
- kmod-leds-gpio uboot-envtools
-
-KERNELNAME:=zImage dtbs
-
-$(eval $(call BuildTarget))
+++ /dev/null
-
-. /lib/functions/uci-defaults.sh
-. /lib/functions/system.sh
-
-bootloader_cmdline_var() {
- local param
- local pval
- for arg in $(cat /proc/device-tree/chosen/bootloader-args); do
- param="$(echo $arg | cut -d'=' -f 1)"
- pval="$(echo $arg | cut -d'=' -f 2-)"
-
- if [ "$param" = "$1" ]; then
- echo "$pval"
- fi
- done
-}
-
-legacy_boot_mac_adr() {
- local macstr
- local oIFS
- macstr="$(bootloader_cmdline_var mac_adr)"
- oIFS="$IFS"
- IFS=","
- set -- $macstr
- printf "%02x:%02x:%02x:%02x:%02x:%02x" $1 $2 $3 $4 $5 $6
- IFS="$oIFS"
-}
-
-oxnas_setup_interfaces()
-{
- local board="$1"
-
- case $board in
- *)
- ucidef_set_interface_lan "eth0" "dhcp"
- ;;
- esac
-}
-
-oxnas_setup_macs()
-{
- local board="$1"
- local lan_mac=""
-
- case $board in
- shuttle,kd20)
- lan_mac="$(legacy_boot_mac_adr)"
- ;;
- esac
-
- [ -n "$lan_mac" ] && ucidef_set_interface_macaddr "lan" $lan_mac
-}
-
-board_config_update
-board=$(board_name)
-oxnas_setup_interfaces $board
-oxnas_setup_macs $board
-board_config_flush
-
-exit 0
+++ /dev/null
-#!/bin/sh /etc/rc.common
-
-START=99
-
-get_irq() {
- local name="$1"
- grep -m 1 "$name" /proc/interrupts | cut -d: -f1 | sed 's, *,,'
-}
-
-set_irq_affinity() {
- local name="$1"
- local val="$2"
- local irq="$(get_irq "$name")"
- [ -n "$irq" ] || return
- echo "$val" > "/proc/irq/$irq/smp_affinity"
-}
-
-start() {
- set_irq_affinity ehci_hcd 2
- set_irq_affinity xhci_hcd 2
- set_irq_affinity sata 2
-}
+++ /dev/null
-REQUIRE_IMAGE_METADATA=1
-
-platform_check_image() {
- return 0
-}
-
-platform_do_upgrade() {
- nand_do_upgrade $1
-}
+++ /dev/null
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_CPU_AUTO=y
-# CONFIG_ARCH_MULTI_V4 is not set
-# CONFIG_ARCH_MULTI_V4T is not set
-CONFIG_ARCH_MULTI_V4_V5=y
-CONFIG_ARCH_MULTI_V5=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OXNAS=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM=y
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ATAG_DTB_COMPAT=y
-# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set
-CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE=y
-CONFIG_ARM_CPU_SUSPEND=y
-CONFIG_ARM_CRYPTO=y
-CONFIG_ARM_HAS_SG_CHAIN=y
-CONFIG_ARM_L1_CACHE_SHIFT=5
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-# CONFIG_ARM_SMMU is not set
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ATAGS=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_DEBUG_FS=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=65536
-CONFIG_BLK_PM=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMA=y
-CONFIG_CMA_ALIGNMENT=8
-CONFIG_CMA_AREAS=7
-# CONFIG_CMA_DEBUG is not set
-# CONFIG_CMA_DEBUGFS is not set
-CONFIG_CMA_SIZE_MBYTES=64
-# CONFIG_CMA_SIZE_SEL_MAX is not set
-CONFIG_CMA_SIZE_SEL_MBYTES=y
-# CONFIG_CMA_SIZE_SEL_MIN is not set
-# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
-# CONFIG_CMA_SYSFS is not set
-CONFIG_CMDLINE_PARTITION=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_OXNAS=y
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONTIG_ALLOC=y
-CONFIG_COREDUMP=y
-CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV5TJ=y
-CONFIG_CPU_ARM926T=y
-# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_COPY_V4WB=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
-CONFIG_CPU_PABRT_LEGACY=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_USE_DOMAINS=y
-CONFIG_CRASH_CORE=y
-CONFIG_CRC16=y
-# CONFIG_CRC32_SARWATE is not set
-CONFIG_CRC32_SLICEBY8=y
-CONFIG_CROSS_MEMORY_ATTACH=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LZ4=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_DEBUG_ALIGN_RODATA=y
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-CONFIG_DECOMPRESS_BZIP2=y
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_DECOMPRESS_LZ4=y
-CONFIG_DECOMPRESS_LZMA=y
-CONFIG_DECOMPRESS_LZO=y
-CONFIG_DECOMPRESS_XZ=y
-CONFIG_DMA_CMA=y
-CONFIG_DMA_OPS=y
-CONFIG_DMA_REMAP=y
-CONFIG_DNOTIFY=y
-CONFIG_DTC=y
-CONFIG_DWMAC_GENERIC=y
-CONFIG_DWMAC_OXNAS=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_ELF_CORE=y
-CONFIG_FAT_FS=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FREEZER=y
-CONFIG_FWNODE_MDIO=y
-# CONFIG_FW_CACHE is not set
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_GENERIC_PLATFORM=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HID=y
-CONFIG_HID_GENERIC=y
-CONFIG_HWMON=y
-CONFIG_HZ_FIXED=0
-CONFIG_ICPLUS_PHY=y
-CONFIG_INET_DIAG=y
-# CONFIG_INET_DIAG_DESTROY is not set
-# CONFIG_INET_RAW_DIAG is not set
-CONFIG_INET_TCP_DIAG=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-# CONFIG_IOMMU_DEBUGFS is not set
-# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
-# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
-CONFIG_IOMMU_SUPPORT=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-# CONFIG_ISDN is not set
-# CONFIG_JFFS2_FS is not set
-CONFIG_KALLSYMS=y
-CONFIG_KERNEL_GZIP=y
-# CONFIG_KERNEL_XZ is not set
-CONFIG_KEXEC=y
-CONFIG_KEXEC_CORE=y
-# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGER_CPU=y
-CONFIG_LEDS_TRIGGER_GPIO=y
-CONFIG_LEDS_TRIGGER_ONESHOT=y
-CONFIG_LIBFDT=y
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LZ4_COMPRESS=y
-CONFIG_LZ4_DECOMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-# CONFIG_MACH_OX810SE is not set
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MEMORY_ISOLATION=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGRATION=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_KUSER_HELPERS=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NLS=y
-CONFIG_NO_HZ=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_OXNAS_RPS_TIMER=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PAGE_POOL=y
-# CONFIG_PANIC_ON_OOPS is not set
-CONFIG_PANIC_ON_OOPS_VALUE=0
-CONFIG_PANIC_TIMEOUT=0
-CONFIG_PCS_XPCS=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PHY_OXNAS=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_OXNAS=y
-# CONFIG_PINCTRL_SINGLE is not set
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_PM_SLEEP=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_OXNAS=y
-CONFIG_PPS=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-CONFIG_RCU_TRACE=y
-CONFIG_RD_BZIP2=y
-CONFIG_RD_GZIP=y
-CONFIG_RD_LZ4=y
-CONFIG_RD_LZMA=y
-CONFIG_RD_LZO=y
-CONFIG_RD_XZ=y
-CONFIG_REALTEK_PHY=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RESET_OXNAS=y
-CONFIG_SCHED_DEBUG=y
-CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIO=y
-CONFIG_SERIO_LIBPS2=y
-CONFIG_SERIO_SERPORT=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SOCK_DIAG=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPLIT_PTLOCK_CPUS=999999
-CONFIG_SRCU=y
-CONFIG_STACKTRACE=y
-CONFIG_STMMAC_ETH=y
-CONFIG_STMMAC_PLATFORM=y
-# CONFIG_STRIP_ASM_SYMS is not set
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_SWPHY=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_HWMON=y
-CONFIG_THERMAL_OF=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TINY_SRCU=y
-CONFIG_TRACE_CLOCK=y
-CONFIG_UEVENT_HELPER_PATH=""
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-CONFIG_VERSATILE_FPGA_IRQ=y
-CONFIG_VERSATILE_FPGA_IRQ_NR=4
-CONFIG_VFAT_FS=y
-# CONFIG_VFP is not set
-CONFIG_VM_EVENT_COUNTERS=y
-# CONFIG_WATCHDOG is not set
-# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_XZ_DEC_IA64=y
-CONFIG_XZ_DEC_POWERPC=y
-CONFIG_XZ_DEC_SPARC=y
-CONFIG_XZ_DEC_X86=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZLIB_INFLATE=y
+++ /dev/null
-/dts-v1/;
-
-#include "ox820.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/ {
- model = "Akitio MyCloud";
-
- compatible = "akitio,mycloud", "oxsemi,ox820";
-
- chosen {
- bootargs = "earlyprintk console=ttyS0,115200";
- stdout-path = "serial0:115200n8";
- };
-
- memory {
- /* 128Mbytes DDR */
- reg = <0x60000000 0x8000000>;
- };
-
- aliases {
- serial0 = &uart0;
- gpio0 = &gpio0;
- gpio1 = &gpio1;
- led-boot = &led_status;
- led-failsafe = &led_status;
- led-running = &led_status;
- led-upgrade = &led_status;
- };
-
- i2c-gpio {
- compatible = "i2c-gpio";
- gpios = <&gpio1 9 GPIO_ACTIVE_HIGH
- &gpio1 10 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c>;
- i2c-gpio,delay-us = <10>;
- #address-cells = <1>;
- #size-cells = <0>;
- ds1307: rtc@68 {
- compatible = "dallas,ds1307";
- reg = <0x68>;
- };
- };
-
- keys {
- compatible = "gpio-keys-polled";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_buttons>;
- #address-cells = <1>;
- #size-cells = <0>;
- poll-interval = <100>;
- power {
- label = "power";
- gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_POWER>;
- };
- reset {
- label = "reset";
- gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_leds>;
- led_status: status {
- label = "akitio:red:status";
- gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;
- };
- };
-
- gpio-poweroff {
- compatible = "gpio-poweroff";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_poweroff>;
- gpios = <&gpio1 13 GPIO_SINGLE_ENDED>;
- };
-};
-
-&pinctrl {
- pinctrl_i2c: i2c-0 {
- i2c {
- pins = "gpio41", "gpio42"; /* MF_B9, MF_B10 */
- function = "gpio";
- /* ToDo: find a way to set debounce for those pins */
- };
- };
- pinctrl_buttons: buttons-0 {
- buttons {
- pins = "gpio11", "gpio38"; /* MF_A11, MF_B6 GPIO */
- function = "gpio";
- };
- };
- pinctrl_leds: leds-0 {
- leds {
- pins = "gpio29"; /* MF_A29 GPIO */
- function = "gpio";
- };
- };
- pinctrl_poweroff: poweroff-0 {
- poweroff {
- pins = "gpio45"; /* MF_B13 GPIO */
- function = "gpio";
- };
- };
-};
-
-&uart0 {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart0>;
-};
-
-&nandc {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_nand>;
-
- nand@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
- nand-ecc-mode = "soft";
- nand-ecc-algo = "hamming";
-
- partition@0 {
- label = "boot";
- reg = <0x0 0x26c0000>;
- };
-
- partition@26c0000 {
- label = "ubi";
- reg = <0x26c0000 0xd940000>;
- };
- };
-};
-
-ða {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_etha_mdio>;
-};
-
-&ehci {
- status = "okay";
-};
-
-&sata {
- status = "okay";
- nr-ports = <2>;
-};
-
-&pcie_phy {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
-};
+++ /dev/null
-/*
- * cloudengines-pogoplug-series-3.dtsi - Device tree file for Cloud Engines PogoPlug Series 3
- *
- * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
- *
- * Licensed under GPLv2 or later
- */
-
-/dts-v1/;
-#include "ox820.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- model = "Cloud Engines PogoPlug Pro";
-
- compatible = "cloudengines,pogoplugpro", "oxsemi,ox820";
-
- chosen {
- bootargs = "earlyprintk console=ttyS0,115200";
- stdout-path = "serial0:115200n8";
- };
-
- memory {
- /* 128Mbytes DDR */
- reg = <0x60000000 0x8000000>;
- };
-
- aliases {
- serial0 = &uart0;
- gpio0 = &gpio0;
- gpio1 = &gpio1;
- led-boot = &led_status;
- led-failsafe = &led_warn;
- led-running = &led_act;
- led-upgrade = &led_warn;
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_status: blue {
- label = "pogoplug:blue";
- gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
- default-state = "keep";
- };
-
- led_warn: orange {
- label = "pogoplug:orange";
- gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
- default-state = "keep";
- };
-
- led_act: green {
- label = "pogoplug:green";
- gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
- default-state = "keep";
- };
- };
-};
-
-&uart0 {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart0>;
-};
-
-&nandc {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_nand>;
-
- nand@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
- nand-ecc-mode = "soft";
- nand-ecc-algo = "hamming";
-
- partition@0 {
- label = "stage1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
-
- partition@40000 {
- label = "u-boot";
- reg = <0x00040000 0x00380000>;
- read-only;
- };
-
- partition@3c0000 {
- label = "u-boot-env";
- reg = <0x003c0000 0x00080000>;
- };
-
- partition@440000 {
- label = "kernel";
- reg = <0x00440000 0x009c0000>;
- };
-
- partition@e00000 {
- label = "ubi";
- reg = <0x00e00000 0x07200000>;
- };
- };
-};
-
-&ehci {
- status = "okay";
-};
-
-ða {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_etha_mdio>;
-};
-
-&sata {
- status = "okay";
-};
-
-&pcie_phy {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
-};
+++ /dev/null
-/dts-v1/;
-
-#include "ox820.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-
-/ {
- model = "MitraStar Technology Corp. STG-212";
-
- compatible = "mitrastar,stg-212", "oxsemi,ox820";
-
- chosen {
- bootargs = "earlyprintk console=ttyS0,115200";
- stdout-path = "serial0:115200n8";
- };
-
- memory {
- /* 128Mbytes DDR */
- reg = <0x60000000 0x8000000>;
- };
-
- aliases {
- serial0 = &uart0;
- gpio0 = &gpio0;
- gpio1 = &gpio1;
- led-boot = &led_status;
- led-failsafe = &led_warn;
- led-running = &led_status;
- led-upgrade = &led_warn;
- };
-
- keys {
- compatible = "gpio-keys-polled";
- #address-cells = <1>;
- #size-cells = <0>;
- poll-interval = <100>;
-
- reset {
- label = "reset";
- gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- copy {
- label = "copy";
- gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_COPY>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- led_status: status {
- label = "zyxel:blue:status";
- gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
- };
- led_warn: status2 {
- label = "zyxel:red:status";
- gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
- };
- copy {
- label = "zyxel:orange:copy";
- gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
- trigger-sources = <&ehci_port1>, <&ehci_port2>;
- linux,default-trigger = "usbport";
- };
- };
-
- i2c-gpio {
- compatible = "i2c-gpio";
- gpios = <&gpio1 9 GPIO_ACTIVE_HIGH
- &gpio1 10 GPIO_ACTIVE_HIGH>;
- i2c-gpio,delay-us = <10>;
- };
-};
-
-&uart0 {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart0>;
-};
-
-&nandc {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_nand>;
-
- nand@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
- nand-ecc-mode = "soft";
- nand-ecc-algo = "hamming";
-
- partition@0 {
- label = "stage1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
-
- partition@40000 {
- label = "u-boot";
- reg = <0x00040000 0x00380000>;
- read-only;
- };
-
- partition@3c0000 {
- label = "u-boot-env";
- reg = <0x003c0000 0x00080000>;
- };
-
- partition@440000 {
- label = "kernel";
- reg = <0x00440000 0x009c0000>;
- };
-
- partition@e00000 {
- label = "ubi";
- reg = <0x00e00000 0x07200000>;
- };
- };
-};
-
-ða {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_etha_mdio>;
-};
-
-&ehci {
- status = "okay";
-};
-
-&sata {
- status = "okay";
-};
+++ /dev/null
-/dts-v1/;
-
-#include "ox820.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/thermal/thermal.h>
-
-/ {
- model = "Shuttle KD20";
-
- compatible = "shuttle,kd20", "oxsemi,ox820";
-
- chosen {
- bootargs = "earlyprintk console=ttyS0,115200";
- stdout-path = "serial0:115200n8";
- };
-
- memory {
- /* 256Mbytes DDR */
- reg = <0x60000000 0x10000000>;
- };
-
- aliases {
- serial0 = &uart0;
- gpio0 = &gpio0;
- gpio1 = &gpio1;
- led-boot = &led_status;
- led-failsafe = &led_warn;
- led-running = &led_status;
- led-upgrade = &led_warn;
- };
-
- thermal-zones {
- chassis-thermal {
- /* Poll every 20 seconds */
- polling-delay = <20000>;
- /* Poll every 2nd second when cooling */
- polling-delay-passive = <2000>;
-
- thermal-sensors = <&hdd0_temp>, <&hdd1_temp>;
-
- trips {
- chassis_alert0: chassis-alert0 {
- /* At 43 degrees turn on fan */
- temperature = <43000>;
- hysteresis = <3000>;
- type = "active";
- };
-
- chassis_alert1: chassis-alert1 {
- /* At 60 degrees emergency shutdown */
- temperature = <60000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
-
- cooling-maps {
- map0 {
- trip = <&chassis_alert0>;
- cooling-device = <&system_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
- };
- };
-
- i2c-gpio {
- compatible = "i2c-gpio";
- sda-gpios = <&gpio1 9 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
- sck-gpios = <&gpio1 10 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
- i2c-gpio,delay-us = <10>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- rtc0: rtc@51 {
- compatible = "nxp,pcf8563";
- reg = <0x51>;
- };
- };
-
- keys {
- compatible = "gpio-keys-polled";
- #address-cells = <1>;
- #size-cells = <0>;
- poll-interval = <100>;
-
- power {
- label = "power";
- gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_POWER>;
- };
- reset {
- label = "reset";
- gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_RESTART>;
- };
- eject1 {
- label = "eject1";
- gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_EJECTCD>;
- };
- eject2 {
- label = "eject2";
- gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
- linux,code = <162>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
- led_status: status {
- label = "kd20:blue:status";
- gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
- };
- led_warn: status2 {
- label = "kd20:red:status";
- gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
- };
- hdd1blue {
- label = "kd20:blue:hdd1";
- gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "ata1";
- };
- hdd1red {
- label = "kd20:red:hdd1";
- gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
- };
- hdd2blue {
- label = "kd20:blue:hdd2";
- gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "ata2";
- };
- hdd2red {
- label = "kd20:red:hdd2";
- gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
- };
- usb {
- label = "kd20:blue:usb";
- gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
- trigger-sources = <&ehci_port1>, <&ehci_port2>;
- linux,default-trigger = "usbport";
- };
- };
-
- beeper: beeper {
- compatible = "gpio-beeper";
- gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
- };
-
- system_fan: gpio-fan {
- compatible = "gpio-fan";
- gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
- gpio-fan,speed-map = <0 0
- 3000 1>;
- #cooling-cells = <2>;
- };
-
- gpio-poweroff {
- compatible = "gpio-poweroff";
- gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
- };
-};
-
-&uart0 {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart0>;
-};
-
-&nandc {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_nand>;
-
- nand@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
- nand-ecc-mode = "soft";
- nand-ecc-algo = "hamming";
-
- partition@0 {
- label = "stage1";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
-
- partition@40000 {
- label = "u-boot";
- reg = <0x00040000 0x001e0000>;
- read-only;
- };
-
- partition@220000 {
- label = "u-boot-env";
- reg = <0x00220000 0x00020000>;
- };
-
- partition@240000 {
- label = "initrd";
- reg = <0x00240000 0x00600000>;
- };
-
- partition@840000 {
- label = "kernel";
- reg = <0x00840000 0x007C0000>;
- };
-
- partition@e00000 {
- label = "ubi";
- reg = <0x01000000 0x07000000>;
- };
- };
-};
-
-ða {
- status = "okay";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_etha_mdio>;
-};
-
-&ehci {
- status = "okay";
-};
-
-&sata {
- status = "okay";
- nr-ports = <2>;
-
- hdd0_temp: sata-port@0 {
- reg = <0>;
- #thermal-sensor-cells = <0>;
- };
-
- hdd1_temp: sata-port@1 {
- reg = <1>;
- #thermal-sensor-cells = <0>;
- };
-};
-
-&pcie_phy {
- status = "okay";
-};
-
-&pcie0 {
- status = "okay";
-};
+++ /dev/null
-/* linux/include/asm-arm/arch-oxnas/uncompress.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_UNCOMPRESS_H
-#define __ASM_ARCH_UNCOMPRESS_H
-
-#define OXNAS_UART1_BASE 0x44200000
-
-static inline void putc(int c)
-{
- static volatile unsigned char *uart =
- (volatile unsigned char *)OXNAS_UART1_BASE;
-
- while (!(uart[5] & 0x20)) { /* LSR reg THR empty bit */
- barrier();
- }
- uart[0] = c; /* THR register */
-}
-
-static inline void flush(void)
-{
-}
-
-#define arch_decomp_setup()
-
-#define arch_decomp_wdog()
-
-#endif /* __ASM_ARCH_UNCOMPRESS_H */
+++ /dev/null
-/*
- * sata_oxnas
- * A driver to interface the 934 based sata core present in the ox820
- * with libata and scsi
- * based on sata_oxnas driver by Ma Haijun <mahaijuns@gmail.com>
- * based on ox820 sata code by:
- * Copyright (c) 2007 Oxford Semiconductor Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/ata.h>
-#include <linux/libata.h>
-#include <linux/of_platform.h>
-#include <linux/delay.h>
-#include <linux/module.h>
-#include <linux/slab.h>
-#include <linux/spinlock.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/clk.h>
-#include <linux/reset.h>
-
-#include <linux/io.h>
-#include <linux/sizes.h>
-#include <linux/version.h>
-
-static inline void oxnas_register_clear_mask(void __iomem *p, unsigned mask)
-{
- u32 val = readl_relaxed(p);
-
- val &= ~mask;
- writel_relaxed(val, p);
-}
-
-static inline void oxnas_register_set_mask(void __iomem *p, unsigned mask)
-{
- u32 val = readl_relaxed(p);
-
- val |= mask;
- writel_relaxed(val, p);
-}
-
-static inline void oxnas_register_value_mask(void __iomem *p,
- unsigned mask, unsigned new_value)
-{
- /* TODO sanity check mask & new_value = new_value */
- u32 val = readl_relaxed(p);
-
- val &= ~mask;
- val |= new_value;
- writel_relaxed(val, p);
-}
-
-/* sgdma request structure */
-struct sgdma_request {
- volatile u32 qualifier;
- volatile u32 control;
- dma_addr_t src_pa;
- dma_addr_t dst_pa;
-} __packed __aligned(4);
-
-
-/* Controller information */
-enum {
- SATA_OXNAS_MAX_PRD = 63,
- SATA_OXNAS_DMA_SIZE = SATA_OXNAS_MAX_PRD *
- sizeof(struct ata_bmdma_prd) +
- sizeof(struct sgdma_request),
- SATA_OXNAS_MAX_PORTS = 2,
- /** The different Oxsemi SATA core version numbers */
- SATA_OXNAS_CORE_VERSION = 0x1f3,
- SATA_OXNAS_IRQ_FLAG = IRQF_SHARED,
- SATA_OXNAS_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
- ATA_FLAG_NO_ATAPI /*| ATA_FLAG_NCQ*/),
- SATA_OXNAS_QUEUE_DEPTH = 32,
-
- SATA_OXNAS_DMA_BOUNDARY = 0xFFFFFFFF,
-};
-
-
-/*
- * SATA Port Registers
- */
-enum {
- /** sata host port register offsets */
- ORB1 = 0x00,
- ORB2 = 0x04,
- ORB3 = 0x08,
- ORB4 = 0x0C,
- ORB5 = 0x10,
- MASTER_STATUS = 0x10,
- FIS_CTRL = 0x18,
- FIS_DATA = 0x1C,
- INT_STATUS = 0x30,
- INT_CLEAR = 0x30,
- INT_ENABLE = 0x34,
- INT_DISABLE = 0x38,
- VERSION = 0x3C,
- SATA_CONTROL = 0x5C,
- SATA_COMMAND = 0x60,
- HID_FEATURES = 0x64,
- PORT_CONTROL = 0x68,
- DRIVE_CONTROL = 0x6C,
- /** These registers allow access to the link layer registers
- that reside in a different clock domain to the processor bus */
- LINK_DATA = 0x70,
- LINK_RD_ADDR = 0x74,
- LINK_WR_ADDR = 0x78,
- LINK_CONTROL = 0x7C,
- /* window control */
- WIN1LO = 0x80,
- WIN1HI = 0x84,
- WIN2LO = 0x88,
- WIN2HI = 0x8C,
- WIN0_CONTROL = 0x90,
-};
-
-/** sata port register bits */
-enum{
- /**
- * commands to issue in the master status to tell it to move shadow ,
- * registers to the actual device ,
- */
- SATA_OPCODE_MASK = 0x00000007,
- CMD_WRITE_TO_ORB_REGS_NO_COMMAND = 0x4,
- CMD_WRITE_TO_ORB_REGS = 0x2,
- CMD_SYNC_ESCAPE = 0x7,
- CMD_CORE_BUSY = (1 << 7),
- CMD_DRIVE_SELECT_SHIFT = 12,
- CMD_DRIVE_SELECT_MASK = (0xf << CMD_DRIVE_SELECT_SHIFT),
-
- /** interrupt bits */
- INT_END_OF_CMD = 1 << 0,
- INT_LINK_SERROR = 1 << 1,
- INT_ERROR = 1 << 2,
- INT_LINK_IRQ = 1 << 3,
- INT_REG_ACCESS_ERR = 1 << 7,
- INT_BIST_FIS = 1 << 11,
- INT_MASKABLE = INT_END_OF_CMD |
- INT_LINK_SERROR |
- INT_ERROR |
- INT_LINK_IRQ |
- INT_REG_ACCESS_ERR |
- INT_BIST_FIS,
- INT_WANT = INT_END_OF_CMD |
- INT_LINK_SERROR |
- INT_REG_ACCESS_ERR |
- INT_ERROR,
- INT_ERRORS = INT_LINK_SERROR |
- INT_REG_ACCESS_ERR |
- INT_ERROR,
-
- /** raw interrupt bits, unmaskable, but do not generate interrupts */
- RAW_END_OF_CMD = INT_END_OF_CMD << 16,
- RAW_LINK_SERROR = INT_LINK_SERROR << 16,
- RAW_ERROR = INT_ERROR << 16,
- RAW_LINK_IRQ = INT_LINK_IRQ << 16,
- RAW_REG_ACCESS_ERR = INT_REG_ACCESS_ERR << 16,
- RAW_BIST_FIS = INT_BIST_FIS << 16,
- RAW_WANT = INT_WANT << 16,
- RAW_ERRORS = INT_ERRORS << 16,
-
- /**
- * variables to write to the device control register to set the current
- * device, ie. master or slave.
- */
- DR_CON_48 = 2,
- DR_CON_28 = 0,
-
- SATA_CTL_ERR_MASK = 0x00000016,
-
-};
-
-/* ATA SGDMA register offsets */
-enum {
- SGDMA_CONTROL = 0x0,
- SGDMA_STATUS = 0x4,
- SGDMA_REQUESTPTR = 0x8,
- SGDMA_RESETS = 0xC,
- SGDMA_CORESIZE = 0x10,
-};
-
-/* DMA controller register offsets */
-enum {
- DMA_CONTROL = 0x0,
- DMA_CORESIZE = 0x20,
-
- DMA_CONTROL_RESET = (1 << 12),
-};
-
-enum {
- /* see DMA core docs for the values. Out means from memory (bus A) out
- * to disk (bus B) */
- SGDMA_REQCTL0OUT = 0x0497c03d,
- /* burst mode disabled when no micro code used */
- SGDMA_REQCTL0IN = 0x0493a3c1,
- SGDMA_REQCTL1OUT = 0x0497c07d,
- SGDMA_REQCTL1IN = 0x0497a3c5,
- SGDMA_CONTROL_NOGO = 0x3e,
- SGDMA_CONTROL_GO = SGDMA_CONTROL_NOGO | 1,
- SGDMA_ERRORMASK = 0x3f,
- SGDMA_BUSY = 0x80,
-
- SGDMA_RESETS_CTRL = 1 << 0,
- SGDMA_RESETS_ARBT = 1 << 1,
- SGDMA_RESETS_AHB = 1 << 2,
- SGDMA_RESETS_ALL = SGDMA_RESETS_CTRL |
- SGDMA_RESETS_ARBT |
- SGDMA_RESETS_AHB,
-
- /* Final EOTs */
- SGDMA_REQQUAL = 0x00220001,
-
-};
-
-/** SATA core register offsets */
-enum {
- DM_DBG1 = 0x000,
- RAID_SET = 0x004,
- DM_DBG2 = 0x008,
- DATACOUNT_PORT0 = 0x010,
- DATACOUNT_PORT1 = 0x014,
- CORE_INT_STATUS = 0x030,
- CORE_INT_CLEAR = 0x030,
- CORE_INT_ENABLE = 0x034,
- CORE_INT_DISABLE = 0x038,
- CORE_REBUILD_ENABLE = 0x050,
- CORE_FAILED_PORT_R = 0x054,
- DEVICE_CONTROL = 0x068,
- EXCESS = 0x06C,
- RAID_SIZE_LOW = 0x070,
- RAID_SIZE_HIGH = 0x074,
- PORT_ERROR_MASK = 0x078,
- IDLE_STATUS = 0x07C,
- RAID_CONTROL = 0x090,
- DATA_PLANE_CTRL = 0x0AC,
- CORE_DATAPLANE_STAT = 0x0b8,
- PROC_PC = 0x100,
- CONFIG_IN = 0x3d8,
- PROC_START = 0x3f0,
- PROC_RESET = 0x3f4,
- UCODE_STORE = 0x1000,
- RAID_WP_BOT_LOW = 0x1FF0,
- RAID_WP_BOT_HIGH = 0x1FF4,
- RAID_WP_TOP_LOW = 0x1FF8,
- RAID_WP_TOP_HIGH = 0x1FFC,
- DATA_MUX_RAM0 = 0x8000,
- DATA_MUX_RAM1 = 0xA000,
- PORT_SIZE = 0x10000,
-};
-
-enum {
- /* Sata core debug1 register bits */
- CORE_PORT0_DATA_DIR_BIT = 20,
- CORE_PORT1_DATA_DIR_BIT = 21,
- CORE_PORT0_DATA_DIR = 1 << CORE_PORT0_DATA_DIR_BIT,
- CORE_PORT1_DATA_DIR = 1 << CORE_PORT1_DATA_DIR_BIT,
-
- /** sata core control register bits */
- SCTL_CLR_ERR = 0x00003016,
- RAID_CLR_ERR = 0x0000011e,
-
- /* Interrupts direct from the ports */
- NORMAL_INTS_WANTED = 0x00000303,
-
- /* shift these left by port number */
- COREINT_HOST = 0x00000001,
- COREINT_END = 0x00000100,
- CORERAW_HOST = COREINT_HOST << 16,
- CORERAW_END = COREINT_END << 16,
-
- /* Interrupts from the RAID controller only */
- RAID_INTS_WANTED = 0x00008300,
-
- /* The bits in the IDLE_STATUS that, when set indicate an idle core */
- IDLE_CORES = (1 << 18) | (1 << 19),
-
- /* Data plane control error-mask mask and bit, these bit in the data
- * plane control mask out errors from the ports that prevent the SGDMA
- * care from sending an interrupt */
- DPC_ERROR_MASK = 0x00000300,
- DPC_ERROR_MASK_BIT = 0x00000100,
- /* enable jbod micro-code */
- DPC_JBOD_UCODE = 1 << 0,
- DPC_FIS_SWCH = 1 << 1,
-
- /** Device Control register bits */
- DEVICE_CONTROL_DMABT = 1 << 4,
- DEVICE_CONTROL_ABORT = 1 << 2,
- DEVICE_CONTROL_PAD = 1 << 3,
- DEVICE_CONTROL_PADPAT = 1 << 16,
- DEVICE_CONTROL_PRTRST = 1 << 8,
- DEVICE_CONTROL_RAMRST = 1 << 12,
- DEVICE_CONTROL_ATA_ERR_OVERRIDE = 1 << 28,
-
- /** oxsemi HW raid modes */
- OXNASSATA_NOTRAID = 0,
- OXNASSATA_RAID0 = 1,
- OXNASSATA_RAID1 = 2,
- /** OX820 specific HW-RAID register values */
- RAID_TWODISKS = 3,
- UNKNOWN_MODE = ~0,
-
- CONFIG_IN_RESUME = 2,
-};
-
-/* SATA PHY Registers */
-enum {
- PHY_STAT = 0x00,
- PHY_DATA = 0x04,
-};
-
-enum {
- STAT_READ_VALID = (1 << 21),
- STAT_CR_ACK = (1 << 20),
- STAT_CR_READ = (1 << 19),
- STAT_CR_WRITE = (1 << 18),
- STAT_CAP_DATA = (1 << 17),
- STAT_CAP_ADDR = (1 << 16),
-
- STAT_ACK_ANY = STAT_CR_ACK |
- STAT_CR_READ |
- STAT_CR_WRITE |
- STAT_CAP_DATA |
- STAT_CAP_ADDR,
-
- CR_READ_ENABLE = (1 << 16),
- CR_WRITE_ENABLE = (1 << 17),
- CR_CAP_DATA = (1 << 18),
-};
-
-enum {
- /* Link layer registers */
- SERROR_IRQ_MASK = 5,
-};
-
-enum {
- OXNAS_SATA_SOFTRESET = 1,
- OXNAS_SATA_REINIT = 2,
-};
-
-enum {
- OXNAS_SATA_UCODE_RAID0,
- OXNAS_SATA_UCODE_RAID1,
- OXNAS_SATA_UCODE_JBOD,
- OXNAS_SATA_UCODE_NONE,
-};
-
-enum {
- SATA_UNLOCKED,
- SATA_WRITER,
- SATA_READER,
- SATA_REBUILD,
- SATA_HWRAID,
- SATA_SCSI_STACK
-};
-
-typedef irqreturn_t (*oxnas_sata_isr_callback_t)(int, unsigned long, int);
-
-struct sata_oxnas_host_priv {
- void __iomem *port_base;
- void __iomem *dmactl_base;
- void __iomem *sgdma_base;
- void __iomem *core_base;
- void __iomem *phy_base;
- dma_addr_t dma_base;
- void __iomem *dma_base_va;
- size_t dma_size;
- int irq;
- int n_ports;
- int current_ucode;
- u32 port_frozen;
- u32 port_in_eh;
- struct clk *clk;
- struct reset_control *rst_sata;
- struct reset_control *rst_link;
- struct reset_control *rst_phy;
- spinlock_t phy_lock;
- spinlock_t core_lock;
- int core_locked;
- int reentrant_port_no;
- int hw_lock_count;
- int direct_lock_count;
- void *locker_uid;
- int current_locker_type;
- int scsi_nonblocking_attempts;
- oxnas_sata_isr_callback_t isr_callback;
- void *isr_arg;
- wait_queue_head_t fast_wait_queue;
- wait_queue_head_t scsi_wait_queue;
-};
-
-
-struct sata_oxnas_port_priv {
- void __iomem *port_base;
- void __iomem *dmactl_base;
- void __iomem *sgdma_base;
- void __iomem *core_base;
- struct sgdma_request *sgdma_request;
- dma_addr_t sgdma_request_pa;
-};
-
-static u8 sata_oxnas_check_status(struct ata_port *ap);
-static int sata_oxnas_cleanup(struct ata_host *ah);
-static void sata_oxnas_tf_load(struct ata_port *ap,
- const struct ata_taskfile *tf);
-static void sata_oxnas_irq_on(struct ata_port *ap);
-static void sata_oxnas_post_reset_init(struct ata_port *ap);
-
-static int sata_oxnas_acquire_hw(struct ata_port *ap, int may_sleep,
- int timeout_jiffies);
-static void sata_oxnas_release_hw(struct ata_port *ap);
-
-static const void *HW_LOCKER_UID = (void *)0xdeadbeef;
-
-/***************************************************************************
-* ASIC access
-***************************************************************************/
-static void wait_cr_ack(void __iomem *phy_base)
-{
- while ((ioread32(phy_base + PHY_STAT) >> 16) & 0x1f)
- ; /* wait for an ack bit to be set */
-}
-
-static u16 read_cr(void __iomem *phy_base, u16 address)
-{
- iowrite32((u32)address, phy_base + PHY_STAT);
- wait_cr_ack(phy_base);
- iowrite32(CR_READ_ENABLE, phy_base + PHY_DATA);
- wait_cr_ack(phy_base);
- return (u16)ioread32(phy_base + PHY_STAT);
-}
-
-static void write_cr(void __iomem *phy_base, u16 data, u16 address)
-{
- iowrite32((u32)address, phy_base + PHY_STAT);
- wait_cr_ack(phy_base);
- iowrite32((data | CR_CAP_DATA), phy_base + PHY_DATA);
- wait_cr_ack(phy_base);
- iowrite32(CR_WRITE_ENABLE, phy_base + PHY_DATA);
- wait_cr_ack(phy_base);
-}
-
-#define PH_GAIN 2
-#define FR_GAIN 3
-#define PH_GAIN_OFFSET 6
-#define FR_GAIN_OFFSET 8
-#define PH_GAIN_MASK (0x3 << PH_GAIN_OFFSET)
-#define FR_GAIN_MASK (0x3 << FR_GAIN_OFFSET)
-#define USE_INT_SETTING (1<<5)
-
-void workaround5458(struct ata_host *ah)
-{
- struct sata_oxnas_host_priv *hd = ah->private_data;
- void __iomem *phy_base = hd->phy_base;
- u16 rx_control;
- unsigned i;
-
- for (i = 0; i < 2; i++) {
- rx_control = read_cr(phy_base, 0x201d + (i << 8));
- rx_control &= ~(PH_GAIN_MASK | FR_GAIN_MASK);
- rx_control |= PH_GAIN << PH_GAIN_OFFSET;
- rx_control |= (FR_GAIN << FR_GAIN_OFFSET) | USE_INT_SETTING;
- write_cr(phy_base, rx_control, 0x201d+(i<<8));
- }
-}
-
-/**
- * allows access to the link layer registers
- * @param link_reg the link layer register to access (oxsemi indexing ie
- * 00 = static config, 04 = phy ctrl)
- */
-void sata_oxnas_link_write(struct ata_port *ap, unsigned int link_reg, u32 val)
-{
- struct sata_oxnas_port_priv *pd = ap->private_data;
- struct sata_oxnas_host_priv *hd = ap->host->private_data;
- void __iomem *port_base = pd->port_base;
- u32 patience;
- unsigned long flags;
-
- DPRINTK("P%d [0x%02x]->0x%08x\n", ap->port_no, link_reg, val);
-
- spin_lock_irqsave(&hd->phy_lock, flags);
- iowrite32(val, port_base + LINK_DATA);
-
- /* accessed twice as a work around for a bug in the SATA abp bridge
- * hardware (bug 6828) */
- iowrite32(link_reg , port_base + LINK_WR_ADDR);
- ioread32(port_base + LINK_WR_ADDR);
-
- for (patience = 0x100000; patience > 0; --patience) {
- if (ioread32(port_base + LINK_CONTROL) & 0x00000001)
- break;
- }
- spin_unlock_irqrestore(&hd->phy_lock, flags);
-}
-
-static int sata_oxnas_scr_write_port(struct ata_port *ap, unsigned int sc_reg,
- u32 val)
-{
- sata_oxnas_link_write(ap, 0x20 + (sc_reg * 4), val);
- return 0;
-}
-
-static int sata_oxnas_scr_write(struct ata_link *link, unsigned int sc_reg,
- u32 val)
-{
- return sata_oxnas_scr_write_port(link->ap, sc_reg, val);
-}
-
-u32 sata_oxnas_link_read(struct ata_port *ap, unsigned int link_reg)
-{
- struct sata_oxnas_port_priv *pd = ap->private_data;
- struct sata_oxnas_host_priv *hd = ap->host->private_data;
- void __iomem *port_base = pd->port_base;
- u32 result;
- u32 patience;
- unsigned long flags;
-
- spin_lock_irqsave(&hd->phy_lock, flags);
- /* accessed twice as a work around for a bug in the SATA abp bridge
- * hardware (bug 6828) */
- iowrite32(link_reg, port_base + LINK_RD_ADDR);
- ioread32(port_base + LINK_RD_ADDR);
-
- for (patience = 0x100000; patience > 0; --patience) {
- if (ioread32(port_base + LINK_CONTROL) & 0x00000001)
- break;
- }
- if (patience == 0)
- DPRINTK("link read timed out for port %d\n", ap->port_no);
-
- result = ioread32(port_base + LINK_DATA);
- spin_unlock_irqrestore(&hd->phy_lock, flags);
-
- return result;
-}
-
-static int sata_oxnas_scr_read_port(struct ata_port *ap, unsigned int sc_reg,
- u32 *val)
-{
- *val = sata_oxnas_link_read(ap, 0x20 + (sc_reg*4));
- return 0;
-}
-
-static int sata_oxnas_scr_read(struct ata_link *link,
- unsigned int sc_reg, u32 *val)
-{
- return sata_oxnas_scr_read_port(link->ap, sc_reg, val);
-}
-
-/**
- * sata_oxnas_irq_clear is called during probe just before the interrupt handler is
- * registered, to be sure hardware is quiet. It clears and masks interrupt bits
- * in the SATA core.
- *
- * @param ap hardware with the registers in
- */
-static void sata_oxnas_irq_clear(struct ata_port *ap)
-{
- struct sata_oxnas_port_priv *port_priv = ap->private_data;
-
- /* clear pending interrupts */
- iowrite32(~0, port_priv->port_base + INT_CLEAR);
- iowrite32(COREINT_END, port_priv->core_base + CORE_INT_CLEAR);
-}
-
-/**
- * qc_issue is used to make a command active, once the hardware and S/G tables
- * have been prepared. IDE BMDMA drivers use the helper function
- * ata_qc_issue_prot() for taskfile protocol-based dispatch. More advanced
- * drivers roll their own ->qc_issue implementation, using this as the
- * "issue new ATA command to hardware" hook.
- * @param qc the queued command to issue
- */
-static unsigned int sata_oxnas_qc_issue(struct ata_queued_cmd *qc)
-{
- struct sata_oxnas_port_priv *pd = qc->ap->private_data;
- struct sata_oxnas_host_priv *hd = qc->ap->host->private_data;
-
- void __iomem *port_base = pd->port_base;
- void __iomem *core_base = pd->core_base;
- int port_no = qc->ap->port_no;
- int no_microcode = (hd->current_ucode == UNKNOWN_MODE);
- u32 reg;
-
- /* check the core is idle */
- if (ioread32(port_base + SATA_COMMAND) & CMD_CORE_BUSY) {
- int count = 0;
-
- DPRINTK("core busy for a command on port %d\n",
- qc->ap->port_no);
- do {
- mdelay(1);
- if (++count > 100) {
- DPRINTK("core busy for a command on port %d\n",
- qc->ap->port_no);
- /* CrazyDumpDebug(); */
- sata_oxnas_cleanup(qc->ap->host);
- }
- } while (ioread32(port_base + SATA_COMMAND) & CMD_CORE_BUSY);
- }
-
- /* enable passing of error signals to DMA sub-core by clearing the
- * appropriate bit */
- reg = ioread32(core_base + DATA_PLANE_CTRL);
- if (no_microcode)
- reg |= (DPC_ERROR_MASK_BIT | (DPC_ERROR_MASK_BIT << 1));
- reg &= ~(DPC_ERROR_MASK_BIT << port_no);
- iowrite32(reg, core_base + DATA_PLANE_CTRL);
-
- /* Disable all interrupts for ports and RAID controller */
- iowrite32(~0, port_base + INT_DISABLE);
-
- /* Disable all interrupts for core */
- iowrite32(~0, core_base + CORE_INT_DISABLE);
- wmb();
-
- /* Load the command settings into the orb registers */
- sata_oxnas_tf_load(qc->ap, &qc->tf);
-
- /* both pio and dma commands use dma */
- if (ata_is_dma(qc->tf.protocol) || ata_is_pio(qc->tf.protocol)) {
- /* Start the DMA */
- iowrite32(SGDMA_CONTROL_GO, pd->sgdma_base + SGDMA_CONTROL);
- wmb();
- }
-
- /* enable End of command interrupt */
- iowrite32(INT_WANT, port_base + INT_ENABLE);
- iowrite32(COREINT_END, core_base + CORE_INT_ENABLE);
- wmb();
-
- /* Start the command */
- reg = ioread32(port_base + SATA_COMMAND);
- reg &= ~SATA_OPCODE_MASK;
- reg |= CMD_WRITE_TO_ORB_REGS;
- iowrite32(reg , port_base + SATA_COMMAND);
- wmb();
-
- return 0;
-}
-
-/**
- * Will schedule the libATA error handler on the premise that there has
- * been a hotplug event on the port specified
- */
-void sata_oxnas_checkforhotplug(struct ata_port *ap)
-{
- DPRINTK("ENTER\n");
-
- ata_ehi_hotplugged(&ap->link.eh_info);
- ata_port_freeze(ap);
-}
-
-
-/**************************************************************************/
-/* Locking */
-/**************************************************************************/
-/**
- * The underlying function that controls access to the sata core
- *
- * @return non-zero indicates that you have acquired exclusive access to the
- * sata core.
- */
-static int __acquire_sata_core(
- struct ata_host *ah,
- int port_no,
- oxnas_sata_isr_callback_t callback,
- void *arg,
- int may_sleep,
- int timeout_jiffies,
- int hw_access,
- void *uid,
- int locker_type)
-{
- unsigned long end = jiffies + timeout_jiffies;
- int acquired = 0;
- unsigned long flags;
- int timed_out = 0;
- struct sata_oxnas_host_priv *hd;
-
- DEFINE_WAIT(wait);
-
- if (!ah)
- return acquired;
-
- hd = ah->private_data;
-
- spin_lock_irqsave(&hd->core_lock, flags);
-
- DPRINTK("Entered uid %p, port %d, h/w count %d, d count %d, "
- "callback %p, hw_access %d, core_locked %d, "
- "reentrant_port_no %d, isr_callback %p\n",
- uid, port_no, hd->hw_lock_count, hd->direct_lock_count,
- callback, hw_access, hd->core_locked, hd->reentrant_port_no,
- hd->isr_callback);
-
- while (!timed_out) {
- if (hd->core_locked ||
- (!hw_access && hd->scsi_nonblocking_attempts)) {
- /* Can only allow access if from SCSI/SATA stack and if
- * reentrant access is allowed and this access is to the
- * same port for which the lock is current held
- */
- if (hw_access && (port_no == hd->reentrant_port_no)) {
- BUG_ON(!hd->hw_lock_count);
- ++(hd->hw_lock_count);
-
- DPRINTK("Allow SCSI/SATA re-entrant access to "
- "uid %p port %d\n", uid, port_no);
- acquired = 1;
- break;
- } else if (!hw_access) {
- if ((locker_type == SATA_READER) &&
- (hd->current_locker_type == SATA_READER)) {
- WARN(1,
- "Already locked by reader, "
- "uid %p, locker_uid %p, "
- "port %d, h/w count %d, "
- "d count %d, hw_access %d\n",
- uid, hd->locker_uid, port_no,
- hd->hw_lock_count,
- hd->direct_lock_count,
- hw_access);
- goto check_uid;
- }
-
- if ((locker_type != SATA_READER) &&
- (locker_type != SATA_WRITER)) {
- goto wait_for_lock;
- }
-
-check_uid:
- WARN(uid == hd->locker_uid, "Attempt to lock "
- "by locker type %d uid %p, already "
- "locked by locker type %d with "
- "locker_uid %p, port %d, "
- "h/w count %d, d count %d, "
- "hw_access %d\n", locker_type, uid,
- hd->current_locker_type,
- hd->locker_uid, port_no,
- hd->hw_lock_count,
- hd->direct_lock_count, hw_access);
- }
- } else {
- WARN(hd->hw_lock_count || hd->direct_lock_count,
- "Core unlocked but counts non-zero: uid %p, "
- "locker_uid %p, port %d, h/w count %d, "
- "d count %d, hw_access %d\n", uid,
- hd->locker_uid, port_no, hd->hw_lock_count,
- hd->direct_lock_count, hw_access);
-
- BUG_ON(hd->current_locker_type != SATA_UNLOCKED);
-
- WARN(hd->locker_uid, "Attempt to lock uid %p when "
- "locker_uid %p is non-zero, port %d, "
- "h/w count %d, d count %d, hw_access %d\n",
- uid, hd->locker_uid, port_no, hd->hw_lock_count,
- hd->direct_lock_count, hw_access);
-
- if (!hw_access) {
- /* Direct access attempting to acquire
- * non-contented lock
- */
- /* Must have callback for direct access */
- BUG_ON(!callback);
- /* Sanity check lock state */
- BUG_ON(hd->reentrant_port_no != -1);
-
- hd->isr_callback = callback;
- hd->isr_arg = arg;
- ++(hd->direct_lock_count);
-
- hd->current_locker_type = locker_type;
- } else {
- /* SCSI/SATA attempting to acquire
- * non-contented lock
- */
- /* No callbacks for SCSI/SATA access */
- BUG_ON(callback);
- /* No callback args for SCSI/SATA access */
- BUG_ON(arg);
-
- /* Sanity check lock state */
- BUG_ON(hd->isr_callback);
- BUG_ON(hd->isr_arg);
-
- ++(hd->hw_lock_count);
- hd->reentrant_port_no = port_no;
-
- hd->current_locker_type = SATA_SCSI_STACK;
- }
-
- hd->core_locked = 1;
- hd->locker_uid = uid;
- acquired = 1;
- break;
- }
-
-wait_for_lock:
- if (!may_sleep) {
- DPRINTK("Denying for uid %p locker_type %d, "
- "hw_access %d, port %d, current_locker_type %d as "
- "cannot sleep\n", uid, locker_type, hw_access, port_no,
- hd->current_locker_type);
-
- if (hw_access)
- ++(hd->scsi_nonblocking_attempts);
-
- break;
- }
-
- /* Core is locked and we're allowed to sleep, so wait to be
- * awoken when the core is unlocked
- */
- for (;;) {
- prepare_to_wait(hw_access ? &hd->scsi_wait_queue :
- &hd->fast_wait_queue,
- &wait, TASK_UNINTERRUPTIBLE);
- if (!hd->core_locked &&
- !(!hw_access && hd->scsi_nonblocking_attempts)) {
- /* We're going to use variables that will have
- * been changed by the waker prior to clearing
- * core_locked so we need to ensure we see
- * changes to all those variables
- */
- smp_rmb();
- break;
- }
- if (time_after(jiffies, end)) {
- printk(KERN_WARNING "__acquire_sata_core() "
- "uid %p failing for port %d timed out, "
- "locker_uid %p, h/w count %d, "
- "d count %d, callback %p, hw_access %d, "
- "core_locked %d, reentrant_port_no %d, "
- "isr_callback %p, isr_arg %p\n", uid,
- port_no, hd->locker_uid,
- hd->hw_lock_count,
- hd->direct_lock_count, callback,
- hw_access, hd->core_locked,
- hd->reentrant_port_no, hd->isr_callback,
- hd->isr_arg);
- timed_out = 1;
- break;
- }
- spin_unlock_irqrestore(&hd->core_lock, flags);
- if (!schedule_timeout(4*HZ)) {
- printk(KERN_INFO "__acquire_sata_core() uid %p, "
- "locker_uid %p, timed-out of "
- "schedule(), checking overall timeout\n",
- uid, hd->locker_uid);
- }
- spin_lock_irqsave(&hd->core_lock, flags);
- }
- finish_wait(hw_access ? &hd->scsi_wait_queue :
- &hd->fast_wait_queue, &wait);
- }
-
- if (hw_access && acquired) {
- if (hd->scsi_nonblocking_attempts)
- hd->scsi_nonblocking_attempts = 0;
-
- /* Wake any other SCSI/SATA waiters so they can get reentrant
- * access to the same port if appropriate. This is because if
- * the SATA core is locked by fast access, or SCSI/SATA access
- * to other port, then can have >1 SCSI/SATA waiters on the wait
- * list so want to give reentrant accessors a chance to get
- * access ASAP
- */
- if (!list_empty(&hd->scsi_wait_queue.head))
- wake_up(&hd->scsi_wait_queue);
- }
-
- DPRINTK("Leaving uid %p with acquired = %d, port %d, callback %p\n",
- uid, acquired, port_no, callback);
-
- spin_unlock_irqrestore(&hd->core_lock, flags);
-
- return acquired;
-}
-
-int sata_core_has_fast_waiters(struct ata_host *ah)
-{
- int has_waiters;
- unsigned long flags;
- struct sata_oxnas_host_priv *hd = ah->private_data;
-
- spin_lock_irqsave(&hd->core_lock, flags);
- has_waiters = !list_empty(&hd->fast_wait_queue.head);
- spin_unlock_irqrestore(&hd->core_lock, flags);
-
- return has_waiters;
-}
-EXPORT_SYMBOL(sata_core_has_fast_waiters);
-
-int sata_core_has_scsi_waiters(struct ata_host *ah)
-{
- int has_waiters;
- unsigned long flags;
- struct sata_oxnas_host_priv *hd = ah->private_data;
-
- spin_lock_irqsave(&hd->core_lock, flags);
- has_waiters = hd->scsi_nonblocking_attempts ||
- !list_empty(&hd->scsi_wait_queue.head);
- spin_unlock_irqrestore(&hd->core_lock, flags);
-
- return has_waiters;
-}
-EXPORT_SYMBOL(sata_core_has_scsi_waiters);
-
-/*
- * ata_port operation to gain ownership of the SATA hardware prior to issuing
- * a command against a SATA host. Allows any number of users of the port against
- * which the lock was first acquired, thus enforcing that only one SATA core
- * port may be operated on at once.
- */
-static int sata_oxnas_acquire_hw(
- struct ata_port *ap,
- int may_sleep,
- int timeout_jiffies)
-{
- return __acquire_sata_core(ap->host, ap->port_no, NULL, 0, may_sleep,
- timeout_jiffies, 1, (void *)HW_LOCKER_UID,
- SATA_SCSI_STACK);
-}
-
-/*
- * operation to release ownership of the SATA hardware
- */
-static void sata_oxnas_release_hw(struct ata_port *ap)
-{
- unsigned long flags;
- int released = 0;
- struct sata_oxnas_host_priv *hd = ap->host->private_data;
-
- spin_lock_irqsave(&hd->core_lock, flags);
-
- DPRINTK("Entered port_no = %d, h/w count %d, d count %d, "
- "core locked = %d, reentrant_port_no = %d, isr_callback %p\n",
- ap->port_no, hd->hw_lock_count, hd->direct_lock_count,
- hd->core_locked, hd->reentrant_port_no, hd->isr_callback);
-
- if (!hd->core_locked) {
- /* Nobody holds the SATA lock */
- printk(KERN_WARNING "Nobody holds SATA lock, port_no %d\n",
- ap->port_no);
- released = 1;
- } else if (!hd->hw_lock_count) {
- /* SCSI/SATA has released without holding the lock */
- printk(KERN_WARNING "SCSI/SATA does not hold SATA lock, "
- "port_no %d\n", ap->port_no);
- } else {
- /* Trap incorrect usage */
- BUG_ON(hd->reentrant_port_no == -1);
- BUG_ON(ap->port_no != hd->reentrant_port_no);
- BUG_ON(hd->direct_lock_count);
- BUG_ON(hd->current_locker_type != SATA_SCSI_STACK);
-
- WARN(!hd->locker_uid || (hd->locker_uid != HW_LOCKER_UID),
- "Invalid locker uid %p, h/w count %d, d count %d, "
- "reentrant_port_no %d, core_locked %d, "
- "isr_callback %p\n", hd->locker_uid, hd->hw_lock_count,
- hd->direct_lock_count, hd->reentrant_port_no,
- hd->core_locked, hd->isr_callback);
-
- if (--(hd->hw_lock_count)) {
- DPRINTK("Still nested port_no %d\n", ap->port_no);
- } else {
- DPRINTK("Release port_no %d\n", ap->port_no);
- hd->reentrant_port_no = -1;
- hd->isr_callback = NULL;
- hd->current_locker_type = SATA_UNLOCKED;
- hd->locker_uid = 0;
- hd->core_locked = 0;
- released = 1;
- wake_up(!list_empty(&hd->scsi_wait_queue.head) ?
- &hd->scsi_wait_queue :
- &hd->fast_wait_queue);
- }
- }
-
- DPRINTK("Leaving, port_no %d, count %d\n", ap->port_no,
- hd->hw_lock_count);
-
- spin_unlock_irqrestore(&hd->core_lock, flags);
-
- /* CONFIG_SATA_OX820_DIRECT_HWRAID */
- /* if (released)
- ox820hwraid_restart_queue();
- } */
-}
-
-static inline int sata_oxnas_is_host_frozen(struct ata_host *ah)
-{
- struct sata_oxnas_host_priv *hd = ah->private_data;
-
- smp_rmb();
- return hd->port_in_eh || hd->port_frozen;
-}
-
-
-static inline u32 sata_oxnas_hostportbusy(struct ata_port *ap)
-{
- struct sata_oxnas_host_priv *hd = ap->host->private_data;
-
- return (ioread32(hd->port_base + SATA_COMMAND) & CMD_CORE_BUSY) ||
- (hd->n_ports > 1 &&
- (ioread32(hd->port_base + PORT_SIZE + SATA_COMMAND) &
- CMD_CORE_BUSY));
-}
-
-static inline u32 sata_oxnas_hostdmabusy(struct ata_port *ap)
-{
- struct sata_oxnas_port_priv *pd = ap->private_data;
-
- return ioread32(pd->sgdma_base + SGDMA_STATUS) & SGDMA_BUSY;
-}
-
-
-/**
- * Turns on the cores clock and resets it
- */
-static void sata_oxnas_reset_core(struct ata_host *ah)
-{
- struct sata_oxnas_host_priv *host_priv = ah->private_data;
- int n;
-
- DPRINTK("ENTER\n");
- clk_prepare_enable(host_priv->clk);
-
- reset_control_assert(host_priv->rst_sata);
- reset_control_assert(host_priv->rst_link);
- reset_control_assert(host_priv->rst_phy);
-
- udelay(50);
-
- /* un-reset the PHY, then Link and Controller */
- reset_control_deassert(host_priv->rst_phy);
- udelay(50);
-
- reset_control_deassert(host_priv->rst_sata);
- reset_control_deassert(host_priv->rst_link);
- udelay(50);
-
- workaround5458(ah);
- /* tune for sata compatibility */
- sata_oxnas_link_write(ah->ports[0], 0x60, 0x2988);
-
- for (n = 0; n < host_priv->n_ports; n++) {
- /* each port in turn */
- sata_oxnas_link_write(ah->ports[n], 0x70, 0x55629);
- }
- udelay(50);
-}
-
-
-/**
- * Called after an identify device command has worked out what kind of device
- * is on the port
- *
- * @param port The port to configure
- * @param pdev The hardware associated with controlling the port
- */
-static void sata_oxnas_dev_config(struct ata_device *pdev)
-{
- struct sata_oxnas_port_priv *pd = pdev->link->ap->private_data;
- void __iomem *port_base = pd->port_base;
- u32 reg;
-
- DPRINTK("ENTER\n");
- /* Set the bits to put the port into 28 or 48-bit node */
- reg = ioread32(port_base + DRIVE_CONTROL);
- reg &= ~3;
- reg |= (pdev->flags & ATA_DFLAG_LBA48) ? DR_CON_48 : DR_CON_28;
- iowrite32(reg, port_base + DRIVE_CONTROL);
-
- /* if this is an ATA-6 disk, put port into ATA-5 auto translate mode */
- if (pdev->flags & ATA_DFLAG_LBA48) {
- reg = ioread32(port_base + PORT_CONTROL);
- reg |= 2;
- iowrite32(reg, port_base + PORT_CONTROL);
- }
-}
-/**
- * called to write a taskfile into the ORB registers
- * @param ap hardware with the registers in
- * @param tf taskfile to write to the registers
- */
-static void sata_oxnas_tf_load(struct ata_port *ap,
- const struct ata_taskfile *tf)
-{
- u32 count = 0;
- u32 Orb1 = 0;
- u32 Orb2 = 0;
- u32 Orb3 = 0;
- u32 Orb4 = 0;
- u32 Command_Reg;
-
- struct sata_oxnas_port_priv *port_priv = ap->private_data;
- void __iomem *port_base = port_priv->port_base;
- unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
-
- /* wait a maximum of 10ms for the core to be idle */
- do {
- Command_Reg = ioread32(port_base + SATA_COMMAND);
- if (!(Command_Reg & CMD_CORE_BUSY))
- break;
- count++;
- udelay(50);
- } while (count < 200);
-
- /* check if the ctl register has interrupts disabled or enabled and
- * modify the interrupt enable registers on the ata core as required */
- if (tf->ctl & ATA_NIEN) {
- /* interrupts disabled */
- u32 mask = (COREINT_END << ap->port_no);
-
- iowrite32(mask, port_priv->core_base + CORE_INT_DISABLE);
- sata_oxnas_irq_clear(ap);
- } else {
- sata_oxnas_irq_on(ap);
- }
-
- Orb2 |= (tf->command) << 24;
-
- /* write 48 or 28 bit tf parameters */
- if (is_addr) {
- /* set LBA bit as it's an address */
- Orb1 |= (tf->device & ATA_LBA) << 24;
-
- if (tf->flags & ATA_TFLAG_LBA48) {
- Orb1 |= ATA_LBA << 24;
- Orb2 |= (tf->hob_nsect) << 8;
- Orb3 |= (tf->hob_lbal) << 24;
- Orb4 |= (tf->hob_lbam) << 0;
- Orb4 |= (tf->hob_lbah) << 8;
- Orb4 |= (tf->hob_feature) << 16;
- } else {
- Orb3 |= (tf->device & 0xf) << 24;
- }
-
- /* write 28-bit lba */
- Orb2 |= (tf->nsect) << 0;
- Orb2 |= (tf->feature) << 16;
- Orb3 |= (tf->lbal) << 0;
- Orb3 |= (tf->lbam) << 8;
- Orb3 |= (tf->lbah) << 16;
- Orb4 |= (tf->ctl) << 24;
- }
-
- if (tf->flags & ATA_TFLAG_DEVICE)
- Orb1 |= (tf->device) << 24;
-
- ap->last_ctl = tf->ctl;
-
- /* write values to registers */
- iowrite32(Orb1, port_base + ORB1);
- iowrite32(Orb2, port_base + ORB2);
- iowrite32(Orb3, port_base + ORB3);
- iowrite32(Orb4, port_base + ORB4);
-}
-
-
-void sata_oxnas_set_mode(struct ata_host *ah, u32 mode, u32 force)
-{
- struct sata_oxnas_host_priv *host_priv = ah->private_data;
- void __iomem *core_base = host_priv->core_base;
-
- unsigned int *src;
- void __iomem *dst;
- unsigned int progmicrocode = 0;
- unsigned int changeparameters = 0;
-
- u32 previous_mode;
-
- /* these micro-code programs _should_ include the version word */
-
- /* JBOD */
- static const unsigned int jbod[] = {
- 0x07B400AC, 0x0228A280, 0x00200001, 0x00204002, 0x00224001,
- 0x00EE0009, 0x00724901, 0x01A24903, 0x00E40009, 0x00224001,
- 0x00621120, 0x0183C908, 0x00E20005, 0x00718908, 0x0198A206,
- 0x00621124, 0x0183C908, 0x00E20046, 0x00621104, 0x0183C908,
- 0x00E20015, 0x00EE009D, 0x01A3E301, 0x00E2001B, 0x0183C900,
- 0x00E2001B, 0x00210001, 0x00EE0020, 0x01A3E302, 0x00E2009D,
- 0x0183C901, 0x00E2009D, 0x00210002, 0x0235D700, 0x0208A204,
- 0x0071C908, 0x000F8207, 0x000FC207, 0x0071C920, 0x000F8507,
- 0x000FC507, 0x0228A240, 0x02269A40, 0x00094004, 0x00621104,
- 0x0180C908, 0x00E40031, 0x00621112, 0x01A3C801, 0x00E2002B,
- 0x00294000, 0x0228A220, 0x01A69ABF, 0x002F8000, 0x002FC000,
- 0x0198A204, 0x0001C022, 0x01B1A220, 0x0001C106, 0x00088007,
- 0x0183C903, 0x00E2009D, 0x0228A220, 0x0071890C, 0x0208A206,
- 0x0198A206, 0x0001C022, 0x01B1A220, 0x0001C106, 0x00088007,
- 0x00EE009D, 0x00621104, 0x0183C908, 0x00E2004A, 0x00EE009D,
- 0x01A3C901, 0x00E20050, 0x0021E7FF, 0x0183E007, 0x00E2009D,
- 0x00EE0054, 0x0061600B, 0x0021E7FF, 0x0183C507, 0x00E2009D,
- 0x01A3E301, 0x00E2005A, 0x0183C900, 0x00E2005A, 0x00210001,
- 0x00EE005F, 0x01A3E302, 0x00E20005, 0x0183C901, 0x00E20005,
- 0x00210002, 0x0235D700, 0x0208A204, 0x000F8109, 0x000FC109,
- 0x0071C918, 0x000F8407, 0x000FC407, 0x0001C022, 0x01A1A2BF,
- 0x0001C106, 0x00088007, 0x02269A40, 0x00094004, 0x00621112,
- 0x01A3C801, 0x00E4007F, 0x00621104, 0x0180C908, 0x00E4008D,
- 0x00621128, 0x0183C908, 0x00E2006C, 0x01A3C901, 0x00E2007B,
- 0x0021E7FF, 0x0183E007, 0x00E2007F, 0x00EE006C, 0x0061600B,
- 0x0021E7FF, 0x0183C507, 0x00E4006C, 0x00621111, 0x01A3C801,
- 0x00E2007F, 0x00621110, 0x01A3C801, 0x00E20082, 0x0228A220,
- 0x00621119, 0x01A3C801, 0x00E20086, 0x0001C022, 0x01B1A220,
- 0x0001C106, 0x00088007, 0x0198A204, 0x00294000, 0x01A69ABF,
- 0x002F8000, 0x002FC000, 0x0183C903, 0x00E20005, 0x0228A220,
- 0x0071890C, 0x0208A206, 0x0198A206, 0x0001C022, 0x01B1A220,
- 0x0001C106, 0x00088007, 0x00EE009D, 0x00621128, 0x0183C908,
- 0x00E20005, 0x00621104, 0x0183C908, 0x00E200A6, 0x0062111C,
- 0x0183C908, 0x00E20005, 0x0071890C, 0x0208A206, 0x0198A206,
- 0x00718908, 0x0208A206, 0x00EE0005, ~0
- };
-
- /* Bi-Modal RAID-0/1 */
- static const unsigned int raid[] = {
- 0x00F20145, 0x00EE20FA, 0x00EE20A7, 0x0001C009, 0x00EE0004,
- 0x00220000, 0x0001000B, 0x037003FF, 0x00700018, 0x037003FE,
- 0x037043FD, 0x00704118, 0x037043FC, 0x01A3D240, 0x00E20017,
- 0x00B3C235, 0x00E40018, 0x0093C104, 0x00E80014, 0x0093C004,
- 0x00E80017, 0x01020000, 0x00274020, 0x00EE0083, 0x0080C904,
- 0x0093C104, 0x00EA0020, 0x0093C103, 0x00EC001F, 0x00220002,
- 0x00924104, 0x0005C009, 0x00EE0058, 0x0093CF04, 0x00E80026,
- 0x00900F01, 0x00600001, 0x00910400, 0x00EE0058, 0x00601604,
- 0x01A00003, 0x00E2002C, 0x01018000, 0x00274040, 0x00EE0083,
- 0x0093CF03, 0x00EC0031, 0x00220003, 0x00924F04, 0x0005C009,
- 0x00810104, 0x00B3C235, 0x00E20037, 0x0022C000, 0x00218210,
- 0x00EE0039, 0x0022C001, 0x00218200, 0x00600401, 0x00A04901,
- 0x00604101, 0x01A0C401, 0x00E20040, 0x00216202, 0x00EE0041,
- 0x00216101, 0x02018506, 0x00EE2141, 0x00904901, 0x00E20049,
- 0x00A00401, 0x00600001, 0x02E0C301, 0x00EE2141, 0x00216303,
- 0x037003EE, 0x01A3C001, 0x00E40105, 0x00250080, 0x00204000,
- 0x002042F1, 0x0004C001, 0x00230001, 0x00100006, 0x02C18605,
- 0x00100006, 0x01A3D502, 0x00E20055, 0x00EE0053, 0x00004009,
- 0x00000004, 0x00B3C235, 0x00E40062, 0x0022C001, 0x0020C000,
- 0x00EE2141, 0x0020C001, 0x00EE2141, 0x00EE006B, 0x0022C000,
- 0x0060D207, 0x00EE2141, 0x00B3C242, 0x00E20069, 0x01A3D601,
- 0x00E2006E, 0x02E0C301, 0x00EE2141, 0x00230001, 0x00301303,
- 0x00EE007B, 0x00218210, 0x01A3C301, 0x00E20073, 0x00216202,
- 0x00EE0074, 0x00216101, 0x02018506, 0x00214000, 0x037003EE,
- 0x01A3C001, 0x00E40108, 0x00230001, 0x00100006, 0x00250080,
- 0x00204000, 0x002042F1, 0x0004C001, 0x00EE007F, 0x0024C000,
- 0x01A3D1F0, 0x00E20088, 0x00230001, 0x00300000, 0x01A3D202,
- 0x00E20085, 0x00EE00A5, 0x00B3C800, 0x00E20096, 0x00218000,
- 0x00924709, 0x0005C009, 0x00B20802, 0x00E40093, 0x037103FD,
- 0x00710418, 0x037103FC, 0x00EE0006, 0x00220000, 0x0001000F,
- 0x00EE0006, 0x00800B0C, 0x00B00001, 0x00204000, 0x00208550,
- 0x00208440, 0x002083E0, 0x00208200, 0x00208100, 0x01008000,
- 0x037083EE, 0x02008212, 0x02008216, 0x01A3C201, 0x00E400A5,
- 0x0100C000, 0x00EE20FA, 0x02800000, 0x00208000, 0x00B24C00,
- 0x00E400AD, 0x00224001, 0x00724910, 0x0005C009, 0x00B3CDC4,
- 0x00E200D5, 0x00B3CD29, 0x00E200D5, 0x00B3CD20, 0x00E200D5,
- 0x00B3CD24, 0x00E200D5, 0x00B3CDC5, 0x00E200D2, 0x00B3CD39,
- 0x00E200D2, 0x00B3CD30, 0x00E200D2, 0x00B3CD34, 0x00E200D2,
- 0x00B3CDCA, 0x00E200CF, 0x00B3CD35, 0x00E200CF, 0x00B3CDC8,
- 0x00E200CC, 0x00B3CD25, 0x00E200CC, 0x00B3CD40, 0x00E200CB,
- 0x00B3CD42, 0x00E200CB, 0x01018000, 0x00EE0083, 0x0025C000,
- 0x036083EE, 0x0000800D, 0x00EE00D8, 0x036083EE, 0x00208035,
- 0x00EE00DA, 0x036083EE, 0x00208035, 0x00EE00DA, 0x00208007,
- 0x036083EE, 0x00208025, 0x036083EF, 0x02400000, 0x01A3D208,
- 0x00E200D8, 0x0067120A, 0x0021C000, 0x0021C224, 0x00220000,
- 0x00404B1C, 0x00600105, 0x00800007, 0x0020C00E, 0x00214000,
- 0x01004000, 0x01A0411F, 0x00404E01, 0x01A3C101, 0x00E200F1,
- 0x00B20800, 0x00E400D8, 0x00220001, 0x0080490B, 0x00B04101,
- 0x0040411C, 0x00EE00E1, 0x02269A01, 0x01020000, 0x02275D80,
- 0x01A3D202, 0x00E200F4, 0x01B75D80, 0x01030000, 0x01B69A01,
- 0x00EE00D8, 0x01A3D204, 0x00E40104, 0x00224000, 0x0020C00E,
- 0x0020001E, 0x00214000, 0x01004000, 0x0212490E, 0x00214001,
- 0x01004000, 0x02400000, 0x00B3D702, 0x00E80112, 0x00EE010E,
- 0x00B3D702, 0x00E80112, 0x00B3D702, 0x00E4010E, 0x00230001,
- 0x00EE0140, 0x00200005, 0x036003EE, 0x00204001, 0x00EE0116,
- 0x00230001, 0x00100006, 0x02C18605, 0x00100006, 0x01A3D1F0,
- 0x00E40083, 0x037003EE, 0x01A3C002, 0x00E20121, 0x0020A300,
- 0x0183D102, 0x00E20124, 0x037003EE, 0x01A00005, 0x036003EE,
- 0x01A0910F, 0x00B3C20F, 0x00E2012F, 0x01A3D502, 0x00E20116,
- 0x01A3C002, 0x00E20116, 0x00B3D702, 0x00E4012C, 0x00300000,
- 0x00EE011F, 0x02C18605, 0x00100006, 0x00EE0116, 0x01A3D1F0,
- 0x00E40083, 0x037003EE, 0x01A3C004, 0x00E20088, 0x00200003,
- 0x036003EE, 0x01A3D502, 0x00E20136, 0x00230001, 0x00B3C101,
- 0x00E4012C, 0x00100006, 0x02C18605, 0x00100006, 0x00204000,
- 0x00EE0116, 0x00100006, 0x01A3D1F0, 0x00E40083, 0x01000000,
- 0x02400000, ~0
- };
-
- DPRINTK("ENTER: mode:%d, force:%d\n", mode, force);
-
- if (force)
- previous_mode = UNKNOWN_MODE;
- else
- previous_mode = host_priv->current_ucode;
-
- if (mode == previous_mode)
- return;
-
- host_priv->current_ucode = mode;
-
- /* decide what needs to be done using the STD in my logbook */
- switch (previous_mode) {
- case OXNASSATA_RAID1:
- switch (mode) {
- case OXNASSATA_RAID0:
- changeparameters = 1;
- break;
- case OXNASSATA_NOTRAID:
- changeparameters = 1;
- progmicrocode = 1;
- break;
- }
- break;
- case OXNASSATA_RAID0:
- switch (mode) {
- case OXNASSATA_RAID1:
- changeparameters = 1;
- break;
- case OXNASSATA_NOTRAID:
- changeparameters = 1;
- progmicrocode = 1;
- break;
- }
- break;
- case OXNASSATA_NOTRAID:
- switch (mode) {
- case OXNASSATA_RAID0:
- case OXNASSATA_RAID1:
- changeparameters = 1;
- progmicrocode = 1;
- break;
- }
- break;
- case UNKNOWN_MODE:
- changeparameters = 1;
- progmicrocode = 1;
- break;
- }
-
- /* no need to reprogram everything if already in the right mode */
- if (progmicrocode) {
- /* reset micro-code processor */
- iowrite32(1, core_base + PROC_RESET);
- wmb();
-
- /* select micro-code */
- switch (mode) {
- case OXNASSATA_RAID1:
- case OXNASSATA_RAID0:
- VPRINTK("Loading RAID micro-code\n");
- src = (unsigned int *)&raid[1];
- break;
- case OXNASSATA_NOTRAID:
- VPRINTK("Loading JBOD micro-code\n");
- src = (unsigned int *)&jbod[1];
- break;
- default:
- BUG();
- break;
- }
-
- /* load micro code */
- dst = core_base + UCODE_STORE;
- while (*src != ~0) {
- iowrite32(*src, dst);
- src++;
- dst += sizeof(*src);
- }
- wmb();
- }
-
- if (changeparameters) {
- u32 reg;
- /* set other mode dependent flags */
- switch (mode) {
- case OXNASSATA_RAID1:
- /* clear JBOD mode */
- reg = ioread32(core_base + DATA_PLANE_CTRL);
- reg |= DPC_JBOD_UCODE;
- reg &= ~DPC_FIS_SWCH;
- iowrite32(reg, core_base + DATA_PLANE_CTRL);
- wmb();
-
- /* set the hardware up for RAID-1 */
- iowrite32(0, core_base + RAID_WP_BOT_LOW);
- iowrite32(0, core_base + RAID_WP_BOT_HIGH);
- iowrite32(0xffffffff, core_base + RAID_WP_TOP_LOW);
- iowrite32(0x7fffffff, core_base + RAID_WP_TOP_HIGH);
- iowrite32(0, core_base + RAID_SIZE_LOW);
- iowrite32(0, core_base + RAID_SIZE_HIGH);
- wmb();
- break;
- case OXNASSATA_RAID0:
- /* clear JBOD mode */
- reg = ioread32(core_base + DATA_PLANE_CTRL);
- reg |= DPC_JBOD_UCODE;
- reg &= ~DPC_FIS_SWCH;
- iowrite32(reg, core_base + DATA_PLANE_CTRL);
- wmb();
-
- /* set the hardware up for RAID-1 */
- iowrite32(0, core_base + RAID_WP_BOT_LOW);
- iowrite32(0, core_base + RAID_WP_BOT_HIGH);
- iowrite32(0xffffffff, core_base + RAID_WP_TOP_LOW);
- iowrite32(0x7fffffff, core_base + RAID_WP_TOP_HIGH);
- iowrite32(0xffffffff, core_base + RAID_SIZE_LOW);
- iowrite32(0x7fffffff, core_base + RAID_SIZE_HIGH);
- wmb();
- break;
- case OXNASSATA_NOTRAID:
- /* enable jbod mode */
- reg = ioread32(core_base + DATA_PLANE_CTRL);
- reg &= ~DPC_JBOD_UCODE;
- reg &= ~DPC_FIS_SWCH;
- iowrite32(reg, core_base + DATA_PLANE_CTRL);
- wmb();
-
- /* start micro-code processor*/
- iowrite32(1, core_base + PROC_START);
- break;
- default:
- reg = ioread32(core_base + DATA_PLANE_CTRL);
- reg |= DPC_JBOD_UCODE;
- reg &= ~DPC_FIS_SWCH;
- iowrite32(reg, core_base + DATA_PLANE_CTRL);
- wmb();
- break;
- }
- }
-}
-
-/**
- * sends a sync-escape if there is a link present
- */
-static inline void sata_oxnas_send_sync_escape(struct ata_port *ap)
-{
- struct sata_oxnas_port_priv *pd = ap->private_data;
- u32 reg;
-
- /* read the SSTATUS register and only send a sync escape if there is a
- * link active */
- if ((sata_oxnas_link_read(ap, 0x20) & 3) == 3) {
- reg = ioread32(pd->port_base + SATA_COMMAND);
- reg &= ~SATA_OPCODE_MASK;
- reg |= CMD_SYNC_ESCAPE;
- iowrite32(reg, pd->port_base + SATA_COMMAND);
- }
-}
-
-/* clears errors */
-static inline void sata_oxnas_clear_CS_error(struct ata_port *ap)
-{
- struct sata_oxnas_port_priv *pd = ap->private_data;
- u32 *base = pd->port_base;
- u32 reg;
-
- reg = ioread32(base + SATA_CONTROL);
- reg &= SATA_CTL_ERR_MASK;
- iowrite32(reg, base + SATA_CONTROL);
-}
-
-static inline void sata_oxnas_reset_sgdma(struct ata_port *ap)
-{
- struct sata_oxnas_port_priv *pd = ap->private_data;
-
- iowrite32(SGDMA_RESETS_CTRL, pd->sgdma_base + SGDMA_RESETS);
-}
-
-static inline void sata_oxnas_reset_dma(struct ata_port *ap, int assert)
-{
- struct sata_oxnas_port_priv *pd = ap->private_data;
- u32 reg;
-
- reg = ioread32(pd->dmactl_base + DMA_CONTROL);
- if (assert)
- reg |= DMA_CONTROL_RESET;
- else
- reg &= ~DMA_CONTROL_RESET;
-
- iowrite32(reg, pd->dmactl_base + DMA_CONTROL);
-};
-
-/**
- * Clears the error caused by the core's registers being accessed when the
- * core is busy.
- */
-static inline void sata_oxnas_clear_reg_access_error(struct ata_port *ap)
-{
- struct sata_oxnas_port_priv *pd = ap->private_data;
- u32 *base = pd->port_base;
- u32 reg;
-
- reg = ioread32(base + INT_STATUS);
-
- DPRINTK("ENTER\n");
- if (reg & INT_REG_ACCESS_ERR) {
- DPRINTK("clearing register access error on port %d\n",
- ap->port_no);
- iowrite32(INT_REG_ACCESS_ERR, base + INT_STATUS);
- }
- reg = ioread32(base + INT_STATUS);
- if (reg & INT_REG_ACCESS_ERR)
- DPRINTK("register access error didn't clear\n");
-}
-
-static inline void sata_oxnas_clear_sctl_error(struct ata_port *ap)
-{
- struct sata_oxnas_port_priv *pd = ap->private_data;
- u32 *base = pd->port_base;
- u32 reg;
-
- reg = ioread32(base + SATA_CONTROL);
- reg |= SCTL_CLR_ERR;
- iowrite32(reg, base + SATA_CONTROL);
-}
-
-static inline void sata_oxnas_clear_raid_error(struct ata_host *ah)
-{
- return;
-};
-
-/**
- * Clean up all the state machines in the sata core.
- * @return post cleanup action required
- */
-static int sata_oxnas_cleanup(struct ata_host *ah)
-{
- struct sata_oxnas_host_priv *hd = ah->private_data;
- int actions_required = 0;
- int n;
-
- printk(KERN_INFO "sata_oxnas: resetting SATA core\n");
- /* core not recovering, reset it */
- mdelay(5);
- sata_oxnas_reset_core(ah);
- mdelay(5);
- actions_required |= OXNAS_SATA_REINIT;
- /* Perform any SATA core re-initialisation after reset post reset init
- * needs to be called for both ports as there's one reset for both
- * ports */
- for (n = 0; n < hd->n_ports; n++)
- sata_oxnas_post_reset_init(ah->ports[n]);
-
-
- return actions_required;
-}
-
-/**
- * ata_qc_new - Request an available ATA command, for queueing
- * @ap: Port associated with device @dev
- * @return non zero will refuse a new command, zero will may grant on subject
- * to conditions elsewhere.
- *
- */
-static int sata_oxnas_qc_new(struct ata_port *ap)
-{
- struct sata_oxnas_host_priv *hd = ap->host->private_data;
-
- DPRINTK("port %d\n", ap->port_no);
- smp_rmb();
- if (hd->port_frozen || hd->port_in_eh)
- return 1;
- else
- return !sata_oxnas_acquire_hw(ap, 0, 0);
-}
-
-/**
- * releases the lock on the port the command used
- */
-static void sata_oxnas_qc_free(struct ata_queued_cmd *qc)
-{
- DPRINTK("\n");
- sata_oxnas_release_hw(qc->ap);
-}
-
-static void sata_oxnas_freeze(struct ata_port *ap)
-{
- struct sata_oxnas_host_priv *hd = ap->host->private_data;
-
- DPRINTK("\n");
- hd->port_frozen |= BIT(ap->port_no);
- smp_wmb();
-}
-
-static void sata_oxnas_thaw(struct ata_port *ap)
-{
- struct sata_oxnas_host_priv *hd = ap->host->private_data;
-
- DPRINTK("\n");
- hd->port_frozen &= ~BIT(ap->port_no);
- smp_wmb();
-}
-
-void sata_oxnas_freeze_host(struct ata_port *ap)
-{
- struct sata_oxnas_host_priv *hd = ap->host->private_data;
-
- DPRINTK("ENTER\n");
- hd->port_in_eh |= BIT(ap->port_no);
- smp_wmb();
-}
-
-void sata_oxnas_thaw_host(struct ata_port *ap)
-{
- struct sata_oxnas_host_priv *hd = ap->host->private_data;
-
- DPRINTK("ENTER\n");
- hd->port_in_eh &= ~BIT(ap->port_no);
- smp_wmb();
-}
-
-static void sata_oxnas_post_internal_cmd(struct ata_queued_cmd *qc)
-{
- DPRINTK("ENTER\n");
- /* If the core is busy here, make it idle */
- if (qc->flags & ATA_QCFLAG_FAILED)
- sata_oxnas_cleanup(qc->ap->host);
-}
-
-
-/**
- * turn on the interrupts
- *
- * @param ap Hardware with the registers in
- */
-static void sata_oxnas_irq_on(struct ata_port *ap)
-{
- struct sata_oxnas_port_priv *pd = ap->private_data;
- u32 mask = (COREINT_END << ap->port_no);
-
- /* Clear pending interrupts */
- iowrite32(~0, pd->port_base + INT_CLEAR);
- iowrite32(mask, pd->core_base + CORE_INT_STATUS);
- wmb();
-
- /* enable End of command interrupt */
- iowrite32(INT_WANT, pd->port_base + INT_ENABLE);
- iowrite32(mask, pd->core_base + CORE_INT_ENABLE);
-}
-
-
-/** @return true if the port has a cable connected */
-int sata_oxnas_check_link(struct ata_port *ap)
-{
- int reg;
-
- sata_oxnas_scr_read_port(ap, SCR_STATUS, ®);
- /* Check for the cable present indicated by SCR status bit-0 set */
- return reg & 0x1;
-}
-
-/**
- * ata_std_postreset - standard postreset callback
- * @link: the target ata_link
- * @classes: classes of attached devices
- *
- * This function is invoked after a successful reset. Note that
- * the device might have been reset more than once using
- * different reset methods before postreset is invoked.
- *
- * LOCKING:
- * Kernel thread context (may sleep)
- */
-static void sata_oxnas_postreset(struct ata_link *link, unsigned int *classes)
-{
- struct ata_port *ap = link->ap;
- struct sata_oxnas_host_priv *hd = ap->host->private_data;
-
- unsigned int dev;
-
- DPRINTK("ENTER\n");
- ata_std_postreset(link, classes);
-
- /* turn on phy error detection by removing the masks */
- sata_oxnas_link_write(ap->host->ports[0], 0x0c, 0x30003);
- if (hd->n_ports > 1)
- sata_oxnas_link_write(ap->host->ports[1], 0x0c, 0x30003);
-
- /* bail out if no device is present */
- if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
- DPRINTK("EXIT, no device\n");
- return;
- }
-
- /* go through all the devices and configure them */
- for (dev = 0; dev < ATA_MAX_DEVICES; ++dev) {
- if (ap->link.device[dev].class == ATA_DEV_ATA)
- sata_oxnas_dev_config(&(ap->link.device[dev]));
- }
-
- DPRINTK("EXIT\n");
-}
-
-/**
- * Called to read the hardware registers / DMA buffers, to
- * obtain the current set of taskfile register values.
- * @param ap hardware with the registers in
- * @param tf taskfile to read the registers into
- */
-static void sata_oxnas_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
-{
- struct sata_oxnas_port_priv *port_priv = ap->private_data;
- void __iomem *port_base = port_priv->port_base;
- /* read the orb registers */
- u32 Orb1 = ioread32(port_base + ORB1);
- u32 Orb2 = ioread32(port_base + ORB2);
- u32 Orb3 = ioread32(port_base + ORB3);
- u32 Orb4 = ioread32(port_base + ORB4);
-
- /* read common 28/48 bit tf parameters */
- tf->device = (Orb1 >> 24);
- tf->nsect = (Orb2 >> 0);
- tf->feature = (Orb2 >> 16);
- tf->command = sata_oxnas_check_status(ap);
-
- /* read 48 or 28 bit tf parameters */
- if (tf->flags & ATA_TFLAG_LBA48) {
- tf->hob_nsect = (Orb2 >> 8);
- tf->lbal = (Orb3 >> 0);
- tf->lbam = (Orb3 >> 8);
- tf->lbah = (Orb3 >> 16);
- tf->hob_lbal = (Orb3 >> 24);
- tf->hob_lbam = (Orb4 >> 0);
- tf->hob_lbah = (Orb4 >> 8);
- /* feature ext and control are write only */
- } else {
- /* read 28-bit lba */
- tf->lbal = (Orb3 >> 0);
- tf->lbam = (Orb3 >> 8);
- tf->lbah = (Orb3 >> 16);
- }
-}
-
-/**
- * Read a result task-file from the sata core registers.
- */
-static bool sata_oxnas_qc_fill_rtf(struct ata_queued_cmd *qc)
-{
- /* Read the most recently received FIS from the SATA core ORB registers
- and convert to an ATA taskfile */
- sata_oxnas_tf_read(qc->ap, &qc->result_tf);
- return true;
-}
-
-/**
- * Reads the Status ATA shadow register from hardware.
- *
- * @return The status register
- */
-static u8 sata_oxnas_check_status(struct ata_port *ap)
-{
- u32 Reg;
- u8 status;
- struct sata_oxnas_port_priv *port_priv = ap->private_data;
- void __iomem *port_base = port_priv->port_base;
-
- /* read byte 3 of Orb2 register */
- status = ioread32(port_base + ORB2) >> 24;
-
- /* check for the drive going missing indicated by SCR status bits
- * 0-3 = 0 */
- sata_oxnas_scr_read_port(ap, SCR_STATUS, &Reg);
-
- if (!(Reg & 0x1)) {
- status |= ATA_DF;
- status |= ATA_ERR;
- }
-
- return status;
-}
-
-static inline void sata_oxnas_reset_ucode(struct ata_host *ah, int force,
- int no_microcode)
-{
- struct sata_oxnas_host_priv *hd = ah->private_data;
-
- DPRINTK("ENTER\n");
- if (no_microcode) {
- u32 reg;
-
- sata_oxnas_set_mode(ah, UNKNOWN_MODE, force);
- reg = ioread32(hd->core_base + DEVICE_CONTROL);
- reg |= DEVICE_CONTROL_ATA_ERR_OVERRIDE;
- iowrite32(reg, hd->core_base + DEVICE_CONTROL);
- } else {
- /* JBOD uCode */
- sata_oxnas_set_mode(ah, OXNASSATA_NOTRAID, force);
- /* Turn the work around off as it may have been left on by any
- * HW-RAID code that we've been working with */
- iowrite32(0x0, hd->core_base + PORT_ERROR_MASK);
- }
-}
-
-/**
- * Prepare as much as possible for a command without involving anything that is
- * shared between ports.
- */
-static enum ata_completion_errors sata_oxnas_qc_prep(struct ata_queued_cmd *qc)
-{
- struct sata_oxnas_port_priv *pd;
- int port_no = qc->ap->port_no;
-
- /* if the port's not connected, complete now with an error */
- if (!sata_oxnas_check_link(qc->ap)) {
- ata_port_err(qc->ap,
- "port %d not connected completing with error\n",
- port_no);
- qc->err_mask |= AC_ERR_ATA_BUS;
- ata_qc_complete(qc);
- }
-
- sata_oxnas_reset_ucode(qc->ap->host, 0, 0);
-
- /* both pio and dma commands use dma */
- if (ata_is_dma(qc->tf.protocol) || ata_is_pio(qc->tf.protocol)) {
-
- /* program the scatterlist into the prd table */
- ata_bmdma_qc_prep(qc);
-
- /* point the sgdma controller at the dma request structure */
- pd = qc->ap->private_data;
-
- iowrite32(pd->sgdma_request_pa,
- pd->sgdma_base + SGDMA_REQUESTPTR);
-
- /* setup the request table */
- if (port_no == 0) {
- pd->sgdma_request->control =
- (qc->dma_dir == DMA_FROM_DEVICE) ?
- SGDMA_REQCTL0IN : SGDMA_REQCTL0OUT;
- } else {
- pd->sgdma_request->control =
- (qc->dma_dir == DMA_FROM_DEVICE) ?
- SGDMA_REQCTL1IN : SGDMA_REQCTL1OUT;
- }
- pd->sgdma_request->qualifier = SGDMA_REQQUAL;
- pd->sgdma_request->src_pa = qc->ap->bmdma_prd_dma;
- pd->sgdma_request->dst_pa = qc->ap->bmdma_prd_dma;
- smp_wmb();
-
- /* tell it to wait */
- iowrite32(SGDMA_CONTROL_NOGO, pd->sgdma_base + SGDMA_CONTROL);
- }
-
- return AC_ERR_OK;
-}
-
-static int sata_oxnas_port_start(struct ata_port *ap)
-{
- struct sata_oxnas_host_priv *host_priv = ap->host->private_data;
- struct device *dev = ap->host->dev;
- struct sata_oxnas_port_priv *pp;
- void *mem;
- dma_addr_t mem_dma;
-
- DPRINTK("ENTER\n");
-
- pp = kzalloc(sizeof(*pp), GFP_KERNEL);
- if (!pp)
- return -ENOMEM;
-
- pp->port_base = host_priv->port_base +
- (ap->port_no ? PORT_SIZE : 0);
- pp->dmactl_base = host_priv->dmactl_base +
- (ap->port_no ? DMA_CORESIZE : 0);
- pp->sgdma_base = host_priv->sgdma_base +
- (ap->port_no ? SGDMA_CORESIZE : 0);
- pp->core_base = host_priv->core_base;
-
- /* preallocated */
- if (host_priv->dma_size >= SATA_OXNAS_DMA_SIZE * host_priv->n_ports) {
- DPRINTK("using preallocated DMA\n");
- mem_dma = host_priv->dma_base +
- (ap->port_no ? SATA_OXNAS_DMA_SIZE : 0);
- mem = ioremap(mem_dma, SATA_OXNAS_DMA_SIZE);
- } else {
- mem = dma_alloc_coherent(dev, SATA_OXNAS_DMA_SIZE, &mem_dma,
- GFP_KERNEL);
- }
- if (!mem)
- goto err_ret;
-
- pp->sgdma_request_pa = mem_dma;
- pp->sgdma_request = mem;
-
- ap->bmdma_prd_dma = mem_dma + sizeof(struct sgdma_request);
- ap->bmdma_prd = mem + sizeof(struct sgdma_request);
-
- ap->private_data = pp;
-
- sata_oxnas_post_reset_init(ap);
-
- return 0;
-
-err_ret:
- kfree(pp);
- return -ENOMEM;
-
-}
-
-static void sata_oxnas_port_stop(struct ata_port *ap)
-{
- struct device *dev = ap->host->dev;
- struct sata_oxnas_port_priv *pp = ap->private_data;
- struct sata_oxnas_host_priv *host_priv = ap->host->private_data;
-
- DPRINTK("ENTER\n");
- ap->private_data = NULL;
- if (host_priv->dma_size) {
- iounmap(pp->sgdma_request);
- } else {
- dma_free_coherent(dev, SATA_OXNAS_DMA_SIZE,
- pp->sgdma_request, pp->sgdma_request_pa);
- }
-
- kfree(pp);
-}
-
-
-static void sata_oxnas_post_reset_init(struct ata_port *ap)
-{
- uint dev;
-
- /* force to load u-code only once after reset */
- sata_oxnas_reset_ucode(ap->host, !ap->port_no, 0);
-
- /* turn on phy error detection by removing the masks */
- sata_oxnas_link_write(ap, 0x0C, 0x30003);
-
- /* enable hotplug event detection */
- sata_oxnas_scr_write_port(ap, SCR_ERROR, ~0);
- sata_oxnas_scr_write_port(ap, SERROR_IRQ_MASK, 0x03feffff);
- sata_oxnas_scr_write_port(ap, SCR_ACTIVE, ~0 & ~(1 << 26) & ~(1 << 16));
-
- /* enable interrupts for ports */
- sata_oxnas_irq_on(ap);
-
- /* go through all the devices and configure them */
- for (dev = 0; dev < ATA_MAX_DEVICES; ++dev) {
- if (ap->link.device[dev].class == ATA_DEV_ATA) {
- sata_std_hardreset(&ap->link, NULL, jiffies + HZ);
- sata_oxnas_dev_config(&(ap->link.device[dev]));
- }
- }
-
- /* clean up any remaining errors */
- sata_oxnas_scr_write_port(ap, SCR_ERROR, ~0);
- VPRINTK("done\n");
-}
-
-/**
- * host_stop() is called when the rmmod or hot unplug process begins. The
- * hook must stop all hardware interrupts, DMA engines, etc.
- *
- * @param ap hardware with the registers in
- */
-static void sata_oxnas_host_stop(struct ata_host *host_set)
-{
- DPRINTK("\n");
-}
-
-
-#define ERROR_HW_ACQUIRE_TIMEOUT_JIFFIES (10 * HZ)
-static void sata_oxnas_error_handler(struct ata_port *ap)
-{
- DPRINTK("Enter port_no %d\n", ap->port_no);
- sata_oxnas_freeze_host(ap);
-
- /* If the core is busy here, make it idle */
- sata_oxnas_cleanup(ap->host);
-
- ata_std_error_handler(ap);
-
- sata_oxnas_thaw_host(ap);
-}
-
-static int sata_oxnas_softreset(struct ata_link *link, unsigned int *class,
- unsigned long deadline)
-{
- struct ata_port *ap = link->ap;
- struct sata_oxnas_port_priv *pd = ap->private_data;
- void __iomem *port_base = pd->port_base;
- int rc;
-
- struct ata_taskfile tf;
- u32 Command_Reg;
-
- DPRINTK("ENTER\n");
-
- port_base = pd->port_base;
-
- if (ata_link_offline(link)) {
- DPRINTK("PHY reports no device\n");
- *class = ATA_DEV_NONE;
- goto out;
- }
-
- /* write value to register */
- iowrite32(0, port_base + ORB1);
- iowrite32(0, port_base + ORB2);
- iowrite32(0, port_base + ORB3);
- iowrite32((ap->ctl) << 24, port_base + ORB4);
-
- /* command the core to send a control FIS */
- Command_Reg = ioread32(port_base + SATA_COMMAND);
- Command_Reg &= ~SATA_OPCODE_MASK;
- Command_Reg |= CMD_WRITE_TO_ORB_REGS_NO_COMMAND;
- iowrite32(Command_Reg, port_base + SATA_COMMAND);
- udelay(20); /* FIXME: flush */
-
- /* write value to register */
- iowrite32((ap->ctl | ATA_SRST) << 24, port_base + ORB4);
-
- /* command the core to send a control FIS */
- Command_Reg &= ~SATA_OPCODE_MASK;
- Command_Reg |= CMD_WRITE_TO_ORB_REGS_NO_COMMAND;
- iowrite32(Command_Reg, port_base + SATA_COMMAND);
- udelay(20); /* FIXME: flush */
-
- /* write value to register */
- iowrite32((ap->ctl) << 24, port_base + ORB4);
-
- /* command the core to send a control FIS */
- Command_Reg &= ~SATA_OPCODE_MASK;
- Command_Reg |= CMD_WRITE_TO_ORB_REGS_NO_COMMAND;
- iowrite32(Command_Reg, port_base + SATA_COMMAND);
-
- msleep(150);
-
- rc = ata_sff_wait_ready(link, deadline);
-
- /* if link is occupied, -ENODEV too is an error */
- if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
- ata_link_err(link, "SRST failed (errno=%d)\n", rc);
- return rc;
- }
-
- /* determine by signature whether we have ATA or ATAPI devices */
- sata_oxnas_tf_read(ap, &tf);
- *class = ata_dev_classify(&tf);
-
- if (*class == ATA_DEV_UNKNOWN)
- *class = ATA_DEV_NONE;
-
-out:
- DPRINTK("EXIT, class=%u\n", *class);
- return 0;
-}
-
-
-int sata_oxnas_init_controller(struct ata_host *host)
-{
- return 0;
-}
-
-/**
- * Ref bug-6320
- *
- * This code is a work around for a DMA hardware bug that will repeat the
- * penultimate 8-bytes on some reads. This code will check that the amount
- * of data transferred is a multiple of 512 bytes, if not the in it will
- * fetch the correct data from a buffer in the SATA core and copy it into
- * memory.
- *
- * @param port SATA port to check and if necessary, correct.
- */
-static int sata_oxnas_bug_6320_detect(struct ata_port *ap)
-{
- struct sata_oxnas_port_priv *pd = ap->private_data;
- void __iomem *core_base = pd->core_base;
- int is_read;
- int quads_transferred;
- int remainder;
- int sector_quads_remaining;
- int bug_present = 0;
-
- /* Only want to apply fix to reads */
- is_read = !(ioread32(core_base + DM_DBG1) & (ap->port_no ?
- BIT(CORE_PORT1_DATA_DIR_BIT) :
- BIT(CORE_PORT0_DATA_DIR_BIT)));
-
- /* Check for an incomplete transfer, i.e. not a multiple of 512 bytes
- transferred (datacount_port register counts quads transferred) */
- quads_transferred =
- ioread32(core_base + (ap->port_no ?
- DATACOUNT_PORT1 : DATACOUNT_PORT0));
-
- remainder = quads_transferred & 0x7f;
- sector_quads_remaining = remainder ? (0x80 - remainder) : 0;
-
- if (is_read && (sector_quads_remaining == 2)) {
- bug_present = 1;
- } else if (sector_quads_remaining) {
- if (is_read) {
- ata_port_warn(ap, "SATA read fixup cannot deal with "
- "%d quads remaining\n",
- sector_quads_remaining);
- } else {
- ata_port_warn(ap, "SATA write fixup of %d quads "
- "remaining not supported\n",
- sector_quads_remaining);
- }
- }
-
- return bug_present;
-}
-
-/* This port done an interrupt */
-static void sata_oxnas_port_irq(struct ata_port *ap, int force_error)
-{
- struct ata_queued_cmd *qc;
- struct sata_oxnas_port_priv *pd = ap->private_data;
- void __iomem *port_base = pd->port_base;
-
- u32 int_status;
- unsigned long flags = 0;
-
- DPRINTK("ENTER port %d irqstatus %x\n", ap->port_no,
- ioread32(port_base + INT_STATUS));
-
- if (ap->qc_active & (1ULL << ATA_TAG_INTERNAL)) {
- qc = ata_qc_from_tag(ap, ATA_TAG_INTERNAL);
- DPRINTK("completing non-ncq cmd\n");
-
- if (qc)
- ata_qc_complete(qc);
-
- return;
- }
-
- qc = ata_qc_from_tag(ap, ap->link.active_tag);
-
-
- /* record the port's interrupt */
- int_status = ioread32(port_base + INT_STATUS);
-
- /* If there's no command associated with this IRQ, ignore it. We may get
- * spurious interrupts when cleaning-up after a failed command, ignore
- * these too. */
- if (likely(qc)) {
- /* get the status before any error cleanup */
- qc->err_mask = ac_err_mask(sata_oxnas_check_status(ap));
- if (force_error) {
- /* Pretend there has been a link error */
- qc->err_mask |= AC_ERR_ATA_BUS;
- DPRINTK(" ####force error####\n");
- }
- /* tell libata we're done */
- local_irq_save(flags);
- sata_oxnas_irq_clear(ap);
- local_irq_restore(flags);
- ata_qc_complete(qc);
- } else {
- VPRINTK("Ignoring interrupt, can't find the command tag="
- "%d %08x\n", ap->link.active_tag, ap->qc_active);
- }
-
- /* maybe a hotplug event */
- if (unlikely(int_status & INT_LINK_SERROR)) {
- u32 serror;
-
- sata_oxnas_scr_read_port(ap, SCR_ERROR, &serror);
- if (serror & (SERR_DEV_XCHG | SERR_PHYRDY_CHG)) {
- ata_ehi_hotplugged(&ap->link.eh_info);
- ata_port_freeze(ap);
- }
- }
-}
-
-/**
- * irq_handler is the interrupt handling routine registered with the system,
- * by libata.
- */
-static irqreturn_t sata_oxnas_interrupt(int irq, void *dev_instance)
-{
- struct ata_host *ah = dev_instance;
- struct sata_oxnas_host_priv *hd = ah->private_data;
- void __iomem *core_base = hd->core_base;
-
- u32 int_status;
- irqreturn_t ret = IRQ_NONE;
- u32 port_no;
- u32 mask;
- int bug_present;
-
- /* loop until there are no more interrupts */
- while ((int_status = (ioread32(core_base + CORE_INT_STATUS)) &
- (COREINT_END | (COREINT_END << 1)))) {
-
- /* clear any interrupt */
- iowrite32(int_status, core_base + CORE_INT_CLEAR);
-
- /* Only need workaround_bug_6320 for single disk systems as dual
- * disk will use uCode which prevents this read underrun problem
- * from occurring.
- * All single disk systems will use port 0 */
- for (port_no = 0; port_no < hd->n_ports; ++port_no) {
- /* check the raw end of command interrupt to see if the
- * port is done */
- mask = (COREINT_END << port_no);
- if (!(int_status & mask))
- continue;
-
- /* this port had an interrupt, clear it */
- iowrite32(mask, core_base + CORE_INT_CLEAR);
- /* check for bug 6320 only if no microcode was loaded */
- bug_present = (hd->current_ucode == UNKNOWN_MODE) &&
- sata_oxnas_bug_6320_detect(ah->ports[port_no]);
-
- sata_oxnas_port_irq(ah->ports[port_no],
- bug_present);
- ret = IRQ_HANDLED;
- }
- }
-
- return ret;
-}
-
-/*
- * scsi mid-layer and libata interface structures
- */
-static struct scsi_host_template sata_oxnas_sht = {
- ATA_NCQ_SHT("sata_oxnas"),
- .can_queue = SATA_OXNAS_QUEUE_DEPTH,
- .sg_tablesize = SATA_OXNAS_MAX_PRD,
- .dma_boundary = ATA_DMA_BOUNDARY,
-};
-
-
-static struct ata_port_operations sata_oxnas_ops = {
- .inherits = &sata_port_ops,
- .qc_prep = sata_oxnas_qc_prep,
- .qc_issue = sata_oxnas_qc_issue,
- .qc_fill_rtf = sata_oxnas_qc_fill_rtf,
- .qc_new = sata_oxnas_qc_new,
- .qc_free = sata_oxnas_qc_free,
-
- .scr_read = sata_oxnas_scr_read,
- .scr_write = sata_oxnas_scr_write,
-
- .freeze = sata_oxnas_freeze,
- .thaw = sata_oxnas_thaw,
- .softreset = sata_oxnas_softreset,
- /* .hardreset = sata_oxnas_hardreset, */
- .postreset = sata_oxnas_postreset,
- .error_handler = sata_oxnas_error_handler,
- .post_internal_cmd = sata_oxnas_post_internal_cmd,
-
- .port_start = sata_oxnas_port_start,
- .port_stop = sata_oxnas_port_stop,
-
- .host_stop = sata_oxnas_host_stop,
- /* .pmp_attach = sata_oxnas_pmp_attach, */
- /* .pmp_detach = sata_oxnas_pmp_detach, */
- .sff_check_status = sata_oxnas_check_status,
- .acquire_hw = sata_oxnas_acquire_hw,
-};
-
-static const struct ata_port_info sata_oxnas_port_info = {
- .flags = SATA_OXNAS_HOST_FLAGS,
- .pio_mask = ATA_PIO4,
- .udma_mask = ATA_UDMA6,
- .port_ops = &sata_oxnas_ops,
-};
-
-static int sata_oxnas_probe(struct platform_device *ofdev)
-{
- int retval = -ENXIO;
- int n_ports = 0;
- void __iomem *port_base = NULL;
- void __iomem *dmactl_base = NULL;
- void __iomem *sgdma_base = NULL;
- void __iomem *core_base = NULL;
- void __iomem *phy_base = NULL;
- struct reset_control *rstc;
-
- struct resource res = {};
- struct sata_oxnas_host_priv *host_priv = NULL;
- int irq = 0;
- struct ata_host *host = NULL;
- struct clk *clk = NULL;
-
- const struct ata_port_info *ppi[] = { &sata_oxnas_port_info, NULL };
-
- of_property_read_u32(ofdev->dev.of_node, "nr-ports", &n_ports);
- if (n_ports < 1 || n_ports > SATA_OXNAS_MAX_PORTS)
- goto error_exit_with_cleanup;
-
- port_base = of_iomap(ofdev->dev.of_node, 0);
- if (!port_base)
- goto error_exit_with_cleanup;
-
- dmactl_base = of_iomap(ofdev->dev.of_node, 1);
- if (!dmactl_base)
- goto error_exit_with_cleanup;
-
- sgdma_base = of_iomap(ofdev->dev.of_node, 2);
- if (!sgdma_base)
- goto error_exit_with_cleanup;
-
- core_base = of_iomap(ofdev->dev.of_node, 3);
- if (!core_base)
- goto error_exit_with_cleanup;
-
- phy_base = of_iomap(ofdev->dev.of_node, 4);
- if (!phy_base)
- goto error_exit_with_cleanup;
-
- host_priv = devm_kzalloc(&ofdev->dev,
- sizeof(struct sata_oxnas_host_priv),
- GFP_KERNEL);
- if (!host_priv)
- goto error_exit_with_cleanup;
-
- host_priv->port_base = port_base;
- host_priv->dmactl_base = dmactl_base;
- host_priv->sgdma_base = sgdma_base;
- host_priv->core_base = core_base;
- host_priv->phy_base = phy_base;
- host_priv->n_ports = n_ports;
- host_priv->current_ucode = UNKNOWN_MODE;
-
- if (!of_address_to_resource(ofdev->dev.of_node, 5, &res)) {
- host_priv->dma_base = res.start;
- host_priv->dma_size = resource_size(&res);
- }
-
- irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
- if (!irq) {
- dev_err(&ofdev->dev, "invalid irq from platform\n");
- goto error_exit_with_cleanup;
- }
- host_priv->irq = irq;
-
- clk = of_clk_get(ofdev->dev.of_node, 0);
- if (IS_ERR(clk)) {
- retval = PTR_ERR(clk);
- clk = NULL;
- goto error_exit_with_cleanup;
- }
- host_priv->clk = clk;
-
- rstc = devm_reset_control_get(&ofdev->dev, "sata");
- if (IS_ERR(rstc)) {
- retval = PTR_ERR(rstc);
- goto error_exit_with_cleanup;
- }
- host_priv->rst_sata = rstc;
-
- rstc = devm_reset_control_get(&ofdev->dev, "link");
- if (IS_ERR(rstc)) {
- retval = PTR_ERR(rstc);
- goto error_exit_with_cleanup;
- }
- host_priv->rst_link = rstc;
-
- rstc = devm_reset_control_get(&ofdev->dev, "phy");
- if (IS_ERR(rstc)) {
- retval = PTR_ERR(rstc);
- goto error_exit_with_cleanup;
- }
- host_priv->rst_phy = rstc;
-
- /* allocate host structure */
- host = ata_host_alloc_pinfo(&ofdev->dev, ppi, n_ports);
-
- if (!host) {
- retval = -ENOMEM;
- goto error_exit_with_cleanup;
- }
- host->private_data = host_priv;
- host->iomap = port_base;
-
- /* initialize core locking and queues */
- init_waitqueue_head(&host_priv->fast_wait_queue);
- init_waitqueue_head(&host_priv->scsi_wait_queue);
- spin_lock_init(&host_priv->phy_lock);
- spin_lock_init(&host_priv->core_lock);
- host_priv->core_locked = 0;
- host_priv->reentrant_port_no = -1;
- host_priv->hw_lock_count = 0;
- host_priv->direct_lock_count = 0;
- host_priv->locker_uid = 0;
- host_priv->current_locker_type = SATA_UNLOCKED;
- host_priv->isr_arg = NULL;
- host_priv->isr_callback = NULL;
-
- /* initialize host controller */
- retval = sata_oxnas_init_controller(host);
- if (retval)
- goto error_exit_with_cleanup;
-
- /*
- * Now, register with libATA core, this will also initiate the
- * device discovery process, invoking our port_start() handler &
- * error_handler() to execute a dummy softreset EH session
- */
- ata_host_activate(host, irq, sata_oxnas_interrupt, SATA_OXNAS_IRQ_FLAG,
- &sata_oxnas_sht);
-
- return 0;
-
-error_exit_with_cleanup:
- if (irq)
- irq_dispose_mapping(host_priv->irq);
- if (clk)
- clk_put(clk);
- if (host)
- ata_host_detach(host);
- if (port_base)
- iounmap(port_base);
- if (sgdma_base)
- iounmap(sgdma_base);
- if (core_base)
- iounmap(core_base);
- if (phy_base)
- iounmap(phy_base);
- return retval;
-}
-
-
-static int sata_oxnas_remove(struct platform_device *ofdev)
-{
- struct ata_host *host = dev_get_drvdata(&ofdev->dev);
- struct sata_oxnas_host_priv *host_priv = host->private_data;
-
- ata_host_detach(host);
-
- irq_dispose_mapping(host_priv->irq);
- iounmap(host_priv->port_base);
- iounmap(host_priv->sgdma_base);
- iounmap(host_priv->core_base);
-
- /* reset Controller, Link and PHY */
- reset_control_assert(host_priv->rst_sata);
- reset_control_assert(host_priv->rst_link);
- reset_control_assert(host_priv->rst_phy);
-
- /* Disable the clock to the SATA block */
- clk_disable_unprepare(host_priv->clk);
- clk_put(host_priv->clk);
-
- return 0;
-}
-
-#ifdef CONFIG_PM
-static int sata_oxnas_suspend(struct platform_device *op, pm_message_t state)
-{
- struct ata_host *host = dev_get_drvdata(&op->dev);
-
- return ata_host_suspend(host, state);
-}
-
-static int sata_oxnas_resume(struct platform_device *op)
-{
- struct ata_host *host = dev_get_drvdata(&op->dev);
- int ret;
-
- ret = sata_oxnas_init_controller(host);
- if (ret) {
- dev_err(&op->dev, "Error initializing hardware\n");
- return ret;
- }
- ata_host_resume(host);
- return 0;
-}
-#endif
-
-
-
-static struct of_device_id oxnas_sata_match[] = {
- {
- .compatible = "plxtech,nas782x-sata",
- },
- {},
-};
-
-MODULE_DEVICE_TABLE(of, oxnas_sata_match);
-
-static struct platform_driver oxnas_sata_driver = {
- .driver = {
- .name = "oxnas-sata",
- .owner = THIS_MODULE,
- .of_match_table = oxnas_sata_match,
- },
- .probe = sata_oxnas_probe,
- .remove = sata_oxnas_remove,
-#ifdef CONFIG_PM
- .suspend = sata_oxnas_suspend,
- .resume = sata_oxnas_resume,
-#endif
-};
-
-module_platform_driver(oxnas_sata_driver);
-
-MODULE_LICENSE("GPL");
-MODULE_VERSION("1.0");
-MODULE_AUTHOR("Oxford Semiconductor Ltd.");
-MODULE_DESCRIPTION("low-level driver for Oxford 934 SATA core");
+++ /dev/null
-/*
- * PCIe driver for PLX NAS782X SoCs
- *
- * Author: Ma Haijun <mahaijuns@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/clk.h>
-#include <linux/module.h>
-#include <linux/mbus.h>
-#include <linux/mfd/syscon.h>
-#include <linux/slab.h>
-#include <linux/platform_device.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/of_gpio.h>
-#include <linux/of_irq.h>
-#include <linux/of_pci.h>
-#include <linux/of_platform.h>
-#include <linux/gpio.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/phy.h>
-#include <linux/phy/phy.h>
-#include <linux/regmap.h>
-#include <linux/reset.h>
-#include <linux/io.h>
-#include <linux/sizes.h>
-
-#include "../pci.h"
-
-#define SYS_CTRL_HCSL_CTRL_REGOFFSET 0x114
-
-static inline void oxnas_register_clear_mask(void __iomem *p, unsigned mask)
-{
- u32 val = readl_relaxed(p);
-
- val &= ~mask;
- writel_relaxed(val, p);
-}
-
-static inline void oxnas_register_set_mask(void __iomem *p, unsigned mask)
-{
- u32 val = readl_relaxed(p);
-
- val |= mask;
- writel_relaxed(val, p);
-}
-
-static inline void oxnas_register_value_mask(void __iomem *p,
- unsigned mask, unsigned new_value)
-{
- /* TODO sanity check mask & new_value = new_value */
- u32 val = readl_relaxed(p);
-
- val &= ~mask;
- val |= new_value;
- writel_relaxed(val, p);
-}
-
-#define VERSION_ID_MAGIC 0x082510b5
-#define LINK_UP_TIMEOUT_SECONDS 1
-#define NUM_CONTROLLERS 1
-
-enum {
- PCIE_DEVICE_TYPE_MASK = 0x0F,
- PCIE_DEVICE_TYPE_ENDPOINT = 0,
- PCIE_DEVICE_TYPE_LEGACY_ENDPOINT = 1,
- PCIE_DEVICE_TYPE_ROOT = 4,
-
- PCIE_LTSSM = BIT(4),
- PCIE_READY_ENTR_L23 = BIT(9),
- PCIE_LINK_UP = BIT(11),
- PCIE_OBTRANS = BIT(12),
-};
-
-/* core config registers */
-enum {
- PCI_CONFIG_VERSION_DEVICEID = 0,
- PCI_CONFIG_COMMAND_STATUS = 4,
-};
-
-/* inbound config registers */
-enum {
- IB_ADDR_XLATE_ENABLE = 0xFC,
-
- /* bits */
- ENABLE_IN_ADDR_TRANS = BIT(0),
-};
-
-/* outbound config registers, offset relative to PCIE_POM0_MEM_ADDR */
-enum {
- PCIE_POM0_MEM_ADDR = 0,
- PCIE_POM1_MEM_ADDR = 4,
- PCIE_IN0_MEM_ADDR = 8,
- PCIE_IN1_MEM_ADDR = 12,
- PCIE_IN_IO_ADDR = 16,
- PCIE_IN_CFG0_ADDR = 20,
- PCIE_IN_CFG1_ADDR = 24,
- PCIE_IN_MSG_ADDR = 28,
- PCIE_IN0_MEM_LIMIT = 32,
- PCIE_IN1_MEM_LIMIT = 36,
- PCIE_IN_IO_LIMIT = 40,
- PCIE_IN_CFG0_LIMIT = 44,
- PCIE_IN_CFG1_LIMIT = 48,
- PCIE_IN_MSG_LIMIT = 52,
- PCIE_AHB_SLAVE_CTRL = 56,
-
- PCIE_SLAVE_BE_SHIFT = 22,
-};
-
-#define PCIE_SLAVE_BE(val) ((val) << PCIE_SLAVE_BE_SHIFT)
-#define PCIE_SLAVE_BE_MASK PCIE_SLAVE_BE(0xF)
-
-struct oxnas_pcie_shared {
- /* seems all access are serialized, no lock required */
- int refcount;
-};
-
-/* Structure representing one PCIe interfaces */
-struct oxnas_pcie {
- void __iomem *cfgbase;
- void __iomem *base;
- void __iomem *inbound;
- struct regmap *sys_ctrl;
- unsigned int outbound_offset;
- unsigned int pcie_ctrl_offset;
- struct phy *phy;
- int haslink;
- struct platform_device *pdev;
- struct resource io;
- struct resource cfg;
- struct resource pre_mem; /* prefetchable */
- struct resource non_mem; /* non-prefetchable */
- struct resource busn; /* max available bus numbers */
- int card_reset; /* gpio pin, optional */
- unsigned hcsl_en; /* hcsl pci enable bit */
- struct clk *clk;
- struct clk *busclk; /* for pcie bus, actually the PLLB */
- void *private_data[1];
- spinlock_t lock;
-};
-
-static struct oxnas_pcie_shared pcie_shared = {
- .refcount = 0,
-};
-
-static inline struct oxnas_pcie *sys_to_pcie(struct pci_sys_data *sys)
-{
- return sys->private_data;
-}
-
-
-static inline void set_out_lanes(struct oxnas_pcie *pcie, unsigned lanes)
-{
- regmap_update_bits(pcie->sys_ctrl, pcie->outbound_offset + PCIE_AHB_SLAVE_CTRL,
- PCIE_SLAVE_BE_MASK, PCIE_SLAVE_BE(lanes));
- wmb();
-}
-
-static int oxnas_pcie_link_up(struct oxnas_pcie *pcie)
-{
- unsigned long end;
- unsigned int val;
-
- /* Poll for PCIE link up */
- end = jiffies + (LINK_UP_TIMEOUT_SECONDS * HZ);
- while (!time_after(jiffies, end)) {
- regmap_read(pcie->sys_ctrl, pcie->pcie_ctrl_offset, &val);
- if (val & PCIE_LINK_UP)
- return 1;
- }
- return 0;
-}
-
-static void oxnas_pcie_setup_hw(struct oxnas_pcie *pcie)
-{
- /* We won't have any inbound address translation. This allows PCI
- * devices to access anywhere in the AHB address map. Might be regarded
- * as a bit dangerous, but let's get things working before we worry
- * about that
- */
- oxnas_register_clear_mask(pcie->inbound + IB_ADDR_XLATE_ENABLE,
- ENABLE_IN_ADDR_TRANS);
- wmb();
-
- /*
- * Program outbound translation windows
- *
- * Outbound window is what is referred to as "PCI client" region in HRM
- *
- * Could use the larger alternative address space to get >>64M regions
- * for graphics cards etc., but will not bother at this point.
- *
- * IP bug means that AMBA window size must be a power of 2
- *
- * Set mem0 window for first 16MB of outbound window non-prefetchable
- * Set mem1 window for second 16MB of outbound window prefetchable
- * Set io window for next 16MB of outbound window
- * Set cfg0 for final 1MB of outbound window
- *
- * Ignore mem1, cfg1 and msg windows for now as no obvious use cases for
- * 820 that would need them
- *
- * Probably ideally want no offset between mem0 window start as seen by
- * ARM and as seen on PCI bus and get Linux to assign memory regions to
- * PCI devices using the same "PCI client" region start address as seen
- * by ARM
- */
-
- /* Set PCIeA mem0 region to be 1st 16MB of the 64MB PCIeA window */
- regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN0_MEM_ADDR, pcie->non_mem.start);
- regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN0_MEM_LIMIT, pcie->non_mem.end);
- regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_POM0_MEM_ADDR, pcie->non_mem.start);
-
- /* Set PCIeA mem1 region to be 2nd 16MB of the 64MB PCIeA window */
- regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN1_MEM_ADDR, pcie->pre_mem.start);
- regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN1_MEM_LIMIT, pcie->pre_mem.end);
- regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_POM1_MEM_ADDR, pcie->pre_mem.start);
-
- /* Set PCIeA io to be third 16M region of the 64MB PCIeA window*/
- regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN_IO_ADDR, pcie->io.start);
- regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN_IO_LIMIT, pcie->io.end);
-
-
- /* Set PCIeA cgf0 to be last 16M region of the 64MB PCIeA window*/
- regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN_CFG0_ADDR, pcie->cfg.start);
- regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN_CFG0_LIMIT, pcie->cfg.end);
- wmb();
-
- /* Enable outbound address translation */
- regmap_write_bits(pcie->sys_ctrl, pcie->pcie_ctrl_offset, PCIE_OBTRANS, PCIE_OBTRANS);
- wmb();
-
- /*
- * Program PCIe command register for core to:
- * enable memory space
- * enable bus master
- * enable io
- */
- writel_relaxed(7, pcie->base + PCI_CONFIG_COMMAND_STATUS);
- /* which is which */
- wmb();
-}
-
-static unsigned oxnas_pcie_cfg_to_offset(
- struct pci_sys_data *sys,
- unsigned char bus_number,
- unsigned int devfn,
- int where)
-{
- unsigned int function = PCI_FUNC(devfn);
- unsigned int slot = PCI_SLOT(devfn);
- unsigned char bus_number_offset;
-
- bus_number_offset = bus_number - sys->busnr;
-
- /*
- * We'll assume for now that the offset, function, slot, bus encoding
- * should map onto linear, contiguous addresses in PCIe config space,
- * albeit that the majority will be unused as only slot 0 is valid for
- * any PCIe bus and most devices have only function 0
- *
- * Could be that PCIe in fact works by not encoding the slot number into
- * the config space address as it's known that only slot 0 is valid.
- * We'll have to experiment if/when we get a PCIe switch connected to
- * the PCIe host
- */
- return (bus_number_offset << 20) | (slot << 15) | (function << 12) |
- (where & ~3);
-}
-
-/* PCI configuration space write function */
-static int oxnas_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
- int where, int size, u32 val)
-{
- unsigned long flags;
- struct oxnas_pcie *pcie = sys_to_pcie(bus->sysdata);
- unsigned offset;
- u32 value;
- u32 lanes;
-
- /* Only a single device per bus for PCIe point-to-point links */
- if (PCI_SLOT(devfn) > 0)
- return PCIBIOS_DEVICE_NOT_FOUND;
-
- if (!pcie->haslink)
- return PCIBIOS_DEVICE_NOT_FOUND;
-
- offset = oxnas_pcie_cfg_to_offset(bus->sysdata, bus->number, devfn,
- where);
-
- value = val << (8 * (where & 3));
- lanes = (0xf >> (4-size)) << (where & 3);
- /* it race with mem and io write, but the possibility is low, normally
- * all config writes happens at driver initialize stage, wont interleave
- * with others.
- * and many pcie cards use dword (4bytes) access mem/io access only,
- * so not bother to copy that ugly work-around now. */
- spin_lock_irqsave(&pcie->lock, flags);
- set_out_lanes(pcie, lanes);
- writel_relaxed(value, pcie->cfgbase + offset);
- set_out_lanes(pcie, 0xf);
- spin_unlock_irqrestore(&pcie->lock, flags);
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-/* PCI configuration space read function */
-static int oxnas_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
- int size, u32 *val)
-{
- struct oxnas_pcie *pcie = sys_to_pcie(bus->sysdata);
- unsigned offset;
- u32 value;
- u32 left_bytes, right_bytes;
-
- /* Only a single device per bus for PCIe point-to-point links */
- if (PCI_SLOT(devfn) > 0) {
- *val = 0xffffffff;
- return PCIBIOS_DEVICE_NOT_FOUND;
- }
-
- if (!pcie->haslink) {
- *val = 0xffffffff;
- return PCIBIOS_DEVICE_NOT_FOUND;
- }
-
- offset = oxnas_pcie_cfg_to_offset(bus->sysdata, bus->number, devfn,
- where);
- value = readl_relaxed(pcie->cfgbase + offset);
- left_bytes = where & 3;
- right_bytes = 4 - left_bytes - size;
- value <<= right_bytes * 8;
- value >>= (left_bytes + right_bytes) * 8;
- *val = value;
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-static struct pci_ops oxnas_pcie_ops = {
- .read = oxnas_pcie_rd_conf,
- .write = oxnas_pcie_wr_conf,
-};
-
-static int oxnas_pcie_setup(int nr, struct pci_sys_data *sys)
-{
- struct oxnas_pcie *pcie = sys_to_pcie(sys);
-
- pci_add_resource_offset(&sys->resources, &pcie->non_mem, sys->mem_offset);
- pci_add_resource_offset(&sys->resources, &pcie->pre_mem, sys->mem_offset);
- pci_add_resource_offset(&sys->resources, &pcie->io, sys->io_offset);
- pci_add_resource(&sys->resources, &pcie->busn);
- if (sys->busnr == 0) { /* default one */
- sys->busnr = pcie->busn.start;
- }
- /* do not use devm_ioremap_resource, it does not like cfg resource */
- pcie->cfgbase = devm_ioremap(&pcie->pdev->dev, pcie->cfg.start,
- resource_size(&pcie->cfg));
- if (!pcie->cfgbase)
- return -ENOMEM;
-
- oxnas_pcie_setup_hw(pcie);
-
- return 1;
-}
-
-static void oxnas_pcie_enable(struct device *dev, struct oxnas_pcie *pcie)
-{
- struct hw_pci hw;
- int i;
-
- memset(&hw, 0, sizeof(hw));
- for (i = 0; i < NUM_CONTROLLERS; i++)
- pcie->private_data[i] = pcie;
-
- hw.nr_controllers = NUM_CONTROLLERS;
-/* I think use stack pointer is a bad idea though it is valid in this case */
- hw.private_data = pcie->private_data;
- hw.setup = oxnas_pcie_setup;
- hw.map_irq = of_irq_parse_and_map_pci;
- hw.ops = &oxnas_pcie_ops;
-
- /* pass dev to maintain of tree, interrupt mapping rely on this */
- pci_common_init_dev(dev, &hw);
-}
-
-static int oxnas_pcie_shared_init(struct platform_device *pdev, struct oxnas_pcie *pcie)
-{
- if (++pcie_shared.refcount == 1) {
- phy_init(pcie->phy);
- phy_power_on(pcie->phy);
- return 0;
- } else {
- return 0;
- }
-}
-
-#if 0
-/* maybe we will call it when enter low power state */
-static void oxnas_pcie_shared_deinit(struct platform_device *pdev)
-{
- if (--pcie_shared.refcount == 0) {
- /* no cleanup needed */;
- }
-}
-#endif
-
-static int
-oxnas_pcie_map_registers(struct platform_device *pdev,
- struct device_node *np,
- struct oxnas_pcie *pcie)
-{
- struct resource regs;
- int ret = 0;
- u32 outbound_ctrl_offset;
- u32 pcie_ctrl_offset;
-
- ret = of_address_to_resource(np, 0, ®s);
- if (ret) {
- dev_err(&pdev->dev, "failed to parse base register space\n");
- return -EINVAL;
- }
-
- pcie->base = devm_ioremap_resource(&pdev->dev, ®s);
- if (!pcie->base) {
- dev_err(&pdev->dev, "failed to map base register space\n");
- return -ENOMEM;
- }
-
- ret = of_address_to_resource(np, 1, ®s);
- if (ret) {
- dev_err(&pdev->dev, "failed to parse inbound register space\n");
- return -EINVAL;
- }
-
- pcie->inbound = devm_ioremap_resource(&pdev->dev, ®s);
- if (!pcie->inbound) {
- dev_err(&pdev->dev, "failed to map inbound register space\n");
- return -ENOMEM;
- }
-
- pcie->phy = devm_of_phy_get(&pdev->dev, np, NULL);
- if (IS_ERR(pcie->phy)) {
- if (PTR_ERR(pcie->phy) == -EPROBE_DEFER) {
- dev_err(&pdev->dev, "failed to probe phy\n");
- return PTR_ERR(pcie->phy);
- }
- dev_warn(&pdev->dev, "phy not attached\n");
- pcie->phy = NULL;
- }
-
- if (of_property_read_u32(np, "plxtech,pcie-outbound-offset",
- &outbound_ctrl_offset)) {
- dev_err(&pdev->dev, "failed to parse outbound register offset\n");
- return -EINVAL;
- }
- pcie->outbound_offset = outbound_ctrl_offset;
-
- if (of_property_read_u32(np, "plxtech,pcie-ctrl-offset",
- &pcie_ctrl_offset)) {
- dev_err(&pdev->dev, "failed to parse pcie-ctrl register offset\n");
- return -EINVAL;
- }
- pcie->pcie_ctrl_offset = pcie_ctrl_offset;
-
- return 0;
-}
-
-static int oxnas_pcie_init_res(struct platform_device *pdev,
- struct oxnas_pcie *pcie,
- struct device_node *np)
-{
- struct of_pci_range range;
- struct of_pci_range_parser parser;
- int ret;
-
- if (of_pci_range_parser_init(&parser, np))
- return -EINVAL;
-
- /* Get the I/O and memory ranges from DT */
- for_each_of_pci_range(&parser, &range) {
-
- unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
- if (restype == IORESOURCE_IO) {
- of_pci_range_to_resource(&range, np, &pcie->io);
- pcie->io.name = "I/O";
- }
- if (restype == IORESOURCE_MEM) {
- if (range.flags & IORESOURCE_PREFETCH) {
- of_pci_range_to_resource(&range, np, &pcie->pre_mem);
- pcie->pre_mem.name = "PRE MEM";
- } else {
- of_pci_range_to_resource(&range, np, &pcie->non_mem);
- pcie->non_mem.name = "NON MEM";
- }
-
- }
- if (restype == 0)
- of_pci_range_to_resource(&range, np, &pcie->cfg);
- }
-
- /* Get the bus range */
- ret = of_pci_parse_bus_range(np, &pcie->busn);
-
- if (ret) {
- dev_err(&pdev->dev, "failed to parse bus-range property: %d\n",
- ret);
- return ret;
- }
-
- pcie->card_reset = of_get_gpio(np, 0);
- if (pcie->card_reset < 0)
- dev_info(&pdev->dev, "card reset gpio pin not exists\n");
-
- if (of_property_read_u32(np, "plxtech,pcie-hcsl-bit", &pcie->hcsl_en))
- return -EINVAL;
-
- pcie->clk = of_clk_get_by_name(np, "pcie");
- if (IS_ERR(pcie->clk)) {
- return PTR_ERR(pcie->clk);
- }
-
- pcie->busclk = of_clk_get_by_name(np, "busclk");
- if (IS_ERR(pcie->busclk)) {
- clk_put(pcie->clk);
- return PTR_ERR(pcie->busclk);
- }
-
- return 0;
-}
-
-static void oxnas_pcie_init_hw(struct platform_device *pdev,
- struct oxnas_pcie *pcie)
-{
- u32 version_id;
- int ret;
-
- clk_prepare_enable(pcie->busclk);
-
- /* reset PCIe cards use hard-wired gpio pin */
- if (pcie->card_reset >= 0 &&
- !gpio_direction_output(pcie->card_reset, 0)) {
- wmb();
- mdelay(10);
- /* must tri-state the pin to pull it up */
- gpio_direction_input(pcie->card_reset);
- wmb();
- mdelay(100);
- }
-
- /* ToDo: use phy power-on port... */
- regmap_update_bits(pcie->sys_ctrl, SYS_CTRL_HCSL_CTRL_REGOFFSET,
- BIT(pcie->hcsl_en), BIT(pcie->hcsl_en));
-
- /* core */
- ret = device_reset(&pdev->dev);
- if (ret) {
- dev_err(&pdev->dev, "core reset failed %d\n", ret);
- return;
- }
-
- /* Start PCIe core clocks */
- clk_prepare_enable(pcie->clk);
-
- version_id = readl_relaxed(pcie->base + PCI_CONFIG_VERSION_DEVICEID);
- dev_info(&pdev->dev, "PCIe version/deviceID 0x%x\n", version_id);
-
- if (version_id != VERSION_ID_MAGIC) {
- dev_info(&pdev->dev, "PCIe controller not found\n");
- pcie->haslink = 0;
- return;
- }
-
- /* allow entry to L23 state */
- regmap_write_bits(pcie->sys_ctrl, pcie->pcie_ctrl_offset,
- PCIE_READY_ENTR_L23, PCIE_READY_ENTR_L23);
-
- /* Set PCIe core into RootCore mode */
- regmap_write_bits(pcie->sys_ctrl, pcie->pcie_ctrl_offset,
- PCIE_DEVICE_TYPE_MASK, PCIE_DEVICE_TYPE_ROOT);
- wmb();
-
- /* Bring up the PCI core */
- regmap_write_bits(pcie->sys_ctrl, pcie->pcie_ctrl_offset,
- PCIE_LTSSM, PCIE_LTSSM);
- wmb();
-}
-
-static int oxnas_pcie_probe(struct platform_device *pdev)
-{
- struct oxnas_pcie *pcie;
- struct device_node *np = pdev->dev.of_node;
- int ret;
-
- pcie = devm_kzalloc(&pdev->dev, sizeof(struct oxnas_pcie),
- GFP_KERNEL);
- if (!pcie)
- return -ENOMEM;
-
- pcie->pdev = pdev;
- pcie->haslink = 1;
- spin_lock_init(&pcie->lock);
-
- pcie->sys_ctrl = syscon_regmap_lookup_by_compatible("oxsemi,ox820-sys-ctrl");
- if (IS_ERR(pcie->sys_ctrl))
- return PTR_ERR(pcie->sys_ctrl);
-
- ret = oxnas_pcie_init_res(pdev, pcie, np);
- if (ret)
- return ret;
- if (pcie->card_reset >= 0) {
- ret = gpio_request_one(pcie->card_reset, GPIOF_DIR_IN,
- dev_name(&pdev->dev));
- if (ret) {
- dev_err(&pdev->dev, "cannot request gpio pin %d\n",
- pcie->card_reset);
- return ret;
- }
- }
-
- ret = oxnas_pcie_map_registers(pdev, np, pcie);
- if (ret) {
- dev_err(&pdev->dev, "cannot map registers\n");
- goto err_free_gpio;
- }
-
- ret = oxnas_pcie_shared_init(pdev, pcie);
- if (ret)
- goto err_free_gpio;
-
- /* if hw not found, haslink cleared */
- oxnas_pcie_init_hw(pdev, pcie);
-
- if (pcie->haslink && oxnas_pcie_link_up(pcie)) {
- pcie->haslink = 1;
- dev_info(&pdev->dev, "link up\n");
- } else {
- pcie->haslink = 0;
- dev_info(&pdev->dev, "link down\n");
- }
- /* should we register our controller even when pcie->haslink is 0 ? */
- /* register the controller with framework */
- oxnas_pcie_enable(&pdev->dev, pcie);
-
- return 0;
-
-err_free_gpio:
- if (pcie->card_reset)
- gpio_free(pcie->card_reset);
-
- return ret;
-}
-
-static const struct of_device_id oxnas_pcie_of_match_table[] = {
- { .compatible = "plxtech,nas782x-pcie", },
- {},
-};
-
-static struct platform_driver oxnas_pcie_driver = {
- .driver = {
- .name = "oxnas-pcie",
- .suppress_bind_attrs = true,
- .of_match_table = oxnas_pcie_of_match_table,
- },
- .probe = oxnas_pcie_probe,
-};
-
-builtin_platform_driver(oxnas_pcie_driver);
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (c) 2019 Daniel Golle <daniel@makrotopia.org>
- *
- */
-
-#include <dt-bindings/phy/phy.h>
-#include <linux/io.h>
-#include <linux/iopoll.h>
-#include <linux/module.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/mfd/syscon.h>
-#include <linux/phy/phy.h>
-#include <linux/platform_device.h>
-#include <linux/regmap.h>
-#include <linux/reset.h>
-
-#define ADDR_VAL(val) ((val) & 0xFFFF)
-#define DATA_VAL(val) ((val) & 0xFFFF)
-
-#define SYS_CTRL_HCSL_CTRL_REGOFFSET 0x114
-
-enum {
- HCSL_BIAS_ON = BIT(0),
- HCSL_PCIE_EN = BIT(1),
- HCSL_PCIEA_EN = BIT(2),
- HCSL_PCIEB_EN = BIT(3),
-};
-
-enum {
- /* pcie phy reg offset */
- PHY_ADDR = 0,
- PHY_DATA = 4,
- /* phy data reg bits */
- READ_EN = BIT(16),
- WRITE_EN = BIT(17),
- CAP_DATA = BIT(18),
-};
-
-struct oxnas_pcie_phy {
- struct device *dev;
- void __iomem *membase;
- const struct phy_ops *ops;
- struct regmap *sys_ctrl;
- struct reset_control *rstc;
-};
-
-static int oxnas_pcie_phy_init(struct phy *phy)
-{
- struct oxnas_pcie_phy *pciephy = phy_get_drvdata(phy);
- int ret;
-
- /* generate clocks from HCSL buffers, shared parts */
- regmap_write(pciephy->sys_ctrl, SYS_CTRL_HCSL_CTRL_REGOFFSET, HCSL_BIAS_ON|HCSL_PCIE_EN);
-
- /* Ensure PCIe PHY is properly reset */
- ret = reset_control_reset(pciephy->rstc);
-
- if (ret) {
- dev_err(pciephy->dev, "phy reset failed %d\n", ret);
- return ret;
- }
-
- return 0;
-}
-
-static int oxnas_pcie_phy_power_on(struct phy *phy)
-{
- struct oxnas_pcie_phy *pciephy = phy_get_drvdata(phy);
-
- /* Enable PCIe Pre-Emphasis: What these value means? */
- writel(ADDR_VAL(0x0014), pciephy->membase + PHY_ADDR);
- writel(DATA_VAL(0xce10) | CAP_DATA, pciephy->membase + PHY_DATA);
- writel(DATA_VAL(0xce10) | WRITE_EN, pciephy->membase + PHY_DATA);
-
- writel(ADDR_VAL(0x2004), pciephy->membase + PHY_ADDR);
- writel(DATA_VAL(0x82c7) | CAP_DATA, pciephy->membase + PHY_DATA);
- writel(DATA_VAL(0x82c7) | WRITE_EN, pciephy->membase + PHY_DATA);
-
- return 0;
-}
-
-static const struct phy_ops ops = {
- .init = oxnas_pcie_phy_init,
- .power_on = oxnas_pcie_phy_power_on,
- .owner = THIS_MODULE,
-};
-
-static int oxnas_pcie_phy_probe(struct platform_device *pdev)
-{
- struct device *dev = &pdev->dev;
- struct device_node *np = pdev->dev.of_node;
- struct phy *generic_phy;
- struct phy_provider *phy_provider;
- struct oxnas_pcie_phy *pciephy;
- struct regmap *sys_ctrl;
- struct reset_control *rstc;
- void __iomem *membase;
-
- membase = of_iomap(np, 0);
- if (IS_ERR(membase))
- return PTR_ERR(membase);
-
- sys_ctrl = syscon_regmap_lookup_by_compatible("oxsemi,ox820-sys-ctrl");
- if (IS_ERR(sys_ctrl))
- return PTR_ERR(sys_ctrl);
-
- rstc = devm_reset_control_get_shared(dev, "phy");
- if (IS_ERR(rstc))
- return PTR_ERR(rstc);
-
- pciephy = devm_kzalloc(dev, sizeof(*pciephy), GFP_KERNEL);
- if (!pciephy)
- return -ENOMEM;
-
- pciephy->sys_ctrl = sys_ctrl;
- pciephy->rstc = rstc;
- pciephy->membase = membase;
- pciephy->dev = dev;
- pciephy->ops = &ops;
-
- generic_phy = devm_phy_create(dev, dev->of_node, pciephy->ops);
- if (IS_ERR(generic_phy)) {
- dev_err(dev, "failed to create PHY\n");
- return PTR_ERR(generic_phy);
- }
-
- phy_set_drvdata(generic_phy, pciephy);
- phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
-
- return PTR_ERR_OR_ZERO(phy_provider);
-}
-
-static const struct of_device_id oxnas_pcie_phy_id_table[] = {
- { .compatible = "oxsemi,ox820-pcie-phy" },
- { },
-};
-
-static struct platform_driver oxnas_pcie_phy_driver = {
- .probe = oxnas_pcie_phy_probe,
- .driver = {
- .name = "ox820-pcie-phy",
- .of_match_table = oxnas_pcie_phy_id_table,
- },
-};
-
-builtin_platform_driver(oxnas_pcie_phy_driver);
+++ /dev/null
-// SPDX-License-Identifier: (GPL-2.0)
-/*
- * oxnas SoC reset driver
- * based on:
- * Microsemi MIPS SoC reset driver
- * and ox820_assert_system_reset() written by Ma Hajun <mahaijuns@gmail.com>
- *
- * License: GPL
- * Copyright (c) 2013 Ma Hajun <mahaijuns@gmail.com>
- * Copyright (c) 2017 Microsemi Corporation
- * Copyright (c) 2019 Daniel Golle <daniel@makrotopia.org>
- */
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/notifier.h>
-#include <linux/mfd/syscon.h>
-#include <linux/of_address.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include <linux/reboot.h>
-#include <linux/regmap.h>
-
-/* bit numbers of reset control register */
-#define OX820_SYS_CTRL_RST_SCU 0
-#define OX820_SYS_CTRL_RST_COPRO 1
-#define OX820_SYS_CTRL_RST_ARM0 2
-#define OX820_SYS_CTRL_RST_ARM1 3
-#define OX820_SYS_CTRL_RST_USBHS 4
-#define OX820_SYS_CTRL_RST_USBHSPHYA 5
-#define OX820_SYS_CTRL_RST_MACA 6
-#define OX820_SYS_CTRL_RST_MAC OX820_SYS_CTRL_RST_MACA
-#define OX820_SYS_CTRL_RST_PCIEA 7
-#define OX820_SYS_CTRL_RST_SGDMA 8
-#define OX820_SYS_CTRL_RST_CIPHER 9
-#define OX820_SYS_CTRL_RST_DDR 10
-#define OX820_SYS_CTRL_RST_SATA 11
-#define OX820_SYS_CTRL_RST_SATA_LINK 12
-#define OX820_SYS_CTRL_RST_SATA_PHY 13
-#define OX820_SYS_CTRL_RST_PCIEPHY 14
-#define OX820_SYS_CTRL_RST_STATIC 15
-#define OX820_SYS_CTRL_RST_GPIO 16
-#define OX820_SYS_CTRL_RST_UART1 17
-#define OX820_SYS_CTRL_RST_UART2 18
-#define OX820_SYS_CTRL_RST_MISC 19
-#define OX820_SYS_CTRL_RST_I2S 20
-#define OX820_SYS_CTRL_RST_SD 21
-#define OX820_SYS_CTRL_RST_MACB 22
-#define OX820_SYS_CTRL_RST_PCIEB 23
-#define OX820_SYS_CTRL_RST_VIDEO 24
-#define OX820_SYS_CTRL_RST_DDR_PHY 25
-#define OX820_SYS_CTRL_RST_USBHSPHYB 26
-#define OX820_SYS_CTRL_RST_USBDEV 27
-#define OX820_SYS_CTRL_RST_ARMDBG 29
-#define OX820_SYS_CTRL_RST_PLLA 30
-#define OX820_SYS_CTRL_RST_PLLB 31
-
-/* bit numbers of clock control register */
-#define OX820_SYS_CTRL_CLK_COPRO 0
-#define OX820_SYS_CTRL_CLK_DMA 1
-#define OX820_SYS_CTRL_CLK_CIPHER 2
-#define OX820_SYS_CTRL_CLK_SD 3
-#define OX820_SYS_CTRL_CLK_SATA 4
-#define OX820_SYS_CTRL_CLK_I2S 5
-#define OX820_SYS_CTRL_CLK_USBHS 6
-#define OX820_SYS_CTRL_CLK_MACA 7
-#define OX820_SYS_CTRL_CLK_MAC OX820_SYS_CTRL_CLK_MACA
-#define OX820_SYS_CTRL_CLK_PCIEA 8
-#define OX820_SYS_CTRL_CLK_STATIC 9
-#define OX820_SYS_CTRL_CLK_MACB 10
-#define OX820_SYS_CTRL_CLK_PCIEB 11
-#define OX820_SYS_CTRL_CLK_REF600 12
-#define OX820_SYS_CTRL_CLK_USBDEV 13
-#define OX820_SYS_CTRL_CLK_DDR 14
-#define OX820_SYS_CTRL_CLK_DDRPHY 15
-#define OX820_SYS_CTRL_CLK_DDRCK 16
-
-/* Regmap offsets */
-#define OX820_CLK_SET_REGOFFSET 0x2c
-#define OX820_CLK_CLR_REGOFFSET 0x30
-#define OX820_RST_SET_REGOFFSET 0x34
-#define OX820_RST_CLR_REGOFFSET 0x38
-#define OX820_SECONDARY_SEL_REGOFFSET 0x14
-#define OX820_TERTIARY_SEL_REGOFFSET 0x8c
-#define OX820_QUATERNARY_SEL_REGOFFSET 0x94
-#define OX820_DEBUG_SEL_REGOFFSET 0x9c
-#define OX820_ALTERNATIVE_SEL_REGOFFSET 0xa4
-#define OX820_PULLUP_SEL_REGOFFSET 0xac
-#define OX820_SEC_SECONDARY_SEL_REGOFFSET 0x100014
-#define OX820_SEC_TERTIARY_SEL_REGOFFSET 0x10008c
-#define OX820_SEC_QUATERNARY_SEL_REGOFFSET 0x100094
-#define OX820_SEC_DEBUG_SEL_REGOFFSET 0x10009c
-#define OX820_SEC_ALTERNATIVE_SEL_REGOFFSET 0x1000a4
-#define OX820_SEC_PULLUP_SEL_REGOFFSET 0x1000ac
-
-
-struct oxnas_restart_context {
- struct regmap *sys_ctrl;
- struct notifier_block restart_handler;
-};
-
-static int ox820_restart_handle(struct notifier_block *this,
- unsigned long mode, void *cmd)
-{
- struct oxnas_restart_context *ctx = container_of(this, struct
- oxnas_restart_context,
- restart_handler);
- u32 value;
-
- /* Assert reset to cores as per power on defaults
- * Don't touch the DDR interface as things will come to an impromptu stop
- * NB Possibly should be asserting reset for PLLB, but there are timing
- * concerns here according to the docs */
- value = BIT(OX820_SYS_CTRL_RST_COPRO) |
- BIT(OX820_SYS_CTRL_RST_USBHS) |
- BIT(OX820_SYS_CTRL_RST_USBHSPHYA) |
- BIT(OX820_SYS_CTRL_RST_MACA) |
- BIT(OX820_SYS_CTRL_RST_PCIEA) |
- BIT(OX820_SYS_CTRL_RST_SGDMA) |
- BIT(OX820_SYS_CTRL_RST_CIPHER) |
- BIT(OX820_SYS_CTRL_RST_SATA) |
- BIT(OX820_SYS_CTRL_RST_SATA_LINK) |
- BIT(OX820_SYS_CTRL_RST_SATA_PHY) |
- BIT(OX820_SYS_CTRL_RST_PCIEPHY) |
- BIT(OX820_SYS_CTRL_RST_STATIC) |
- BIT(OX820_SYS_CTRL_RST_UART1) |
- BIT(OX820_SYS_CTRL_RST_UART2) |
- BIT(OX820_SYS_CTRL_RST_MISC) |
- BIT(OX820_SYS_CTRL_RST_I2S) |
- BIT(OX820_SYS_CTRL_RST_SD) |
- BIT(OX820_SYS_CTRL_RST_MACB) |
- BIT(OX820_SYS_CTRL_RST_PCIEB) |
- BIT(OX820_SYS_CTRL_RST_VIDEO) |
- BIT(OX820_SYS_CTRL_RST_USBHSPHYB) |
- BIT(OX820_SYS_CTRL_RST_USBDEV);
-
- regmap_write(ctx->sys_ctrl, OX820_RST_SET_REGOFFSET, value);
-
- /* Release reset to cores as per power on defaults */
- regmap_write(ctx->sys_ctrl, OX820_RST_CLR_REGOFFSET, BIT(OX820_SYS_CTRL_RST_GPIO));
-
- /* Disable clocks to cores as per power-on defaults - must leave DDR
- * related clocks enabled otherwise we'll stop rather abruptly. */
- value =
- BIT(OX820_SYS_CTRL_CLK_COPRO) |
- BIT(OX820_SYS_CTRL_CLK_DMA) |
- BIT(OX820_SYS_CTRL_CLK_CIPHER) |
- BIT(OX820_SYS_CTRL_CLK_SD) |
- BIT(OX820_SYS_CTRL_CLK_SATA) |
- BIT(OX820_SYS_CTRL_CLK_I2S) |
- BIT(OX820_SYS_CTRL_CLK_USBHS) |
- BIT(OX820_SYS_CTRL_CLK_MAC) |
- BIT(OX820_SYS_CTRL_CLK_PCIEA) |
- BIT(OX820_SYS_CTRL_CLK_STATIC) |
- BIT(OX820_SYS_CTRL_CLK_MACB) |
- BIT(OX820_SYS_CTRL_CLK_PCIEB) |
- BIT(OX820_SYS_CTRL_CLK_REF600) |
- BIT(OX820_SYS_CTRL_CLK_USBDEV);
-
- regmap_write(ctx->sys_ctrl, OX820_CLK_CLR_REGOFFSET, value);
-
- /* Enable clocks to cores as per power-on defaults */
-
- /* Set sys-control pin mux'ing as per power-on defaults */
- regmap_write(ctx->sys_ctrl, OX820_SECONDARY_SEL_REGOFFSET, 0);
- regmap_write(ctx->sys_ctrl, OX820_TERTIARY_SEL_REGOFFSET, 0);
- regmap_write(ctx->sys_ctrl, OX820_QUATERNARY_SEL_REGOFFSET, 0);
- regmap_write(ctx->sys_ctrl, OX820_DEBUG_SEL_REGOFFSET, 0);
- regmap_write(ctx->sys_ctrl, OX820_ALTERNATIVE_SEL_REGOFFSET, 0);
- regmap_write(ctx->sys_ctrl, OX820_PULLUP_SEL_REGOFFSET, 0);
-
- regmap_write(ctx->sys_ctrl, OX820_SEC_SECONDARY_SEL_REGOFFSET, 0);
- regmap_write(ctx->sys_ctrl, OX820_SEC_TERTIARY_SEL_REGOFFSET, 0);
- regmap_write(ctx->sys_ctrl, OX820_SEC_QUATERNARY_SEL_REGOFFSET, 0);
- regmap_write(ctx->sys_ctrl, OX820_SEC_DEBUG_SEL_REGOFFSET, 0);
- regmap_write(ctx->sys_ctrl, OX820_SEC_ALTERNATIVE_SEL_REGOFFSET, 0);
- regmap_write(ctx->sys_ctrl, OX820_SEC_PULLUP_SEL_REGOFFSET, 0);
-
- /* No need to save any state, as the ROM loader can determine whether
- * reset is due to power cycling or programatic action, just hit the
- * (self-clearing) CPU reset bit of the block reset register */
- value =
- BIT(OX820_SYS_CTRL_RST_SCU) |
- BIT(OX820_SYS_CTRL_RST_ARM0) |
- BIT(OX820_SYS_CTRL_RST_ARM1);
-
- regmap_write(ctx->sys_ctrl, OX820_RST_SET_REGOFFSET, value);
-
- pr_emerg("Unable to restart system\n");
- return NOTIFY_DONE;
-}
-
-static int ox820_restart_probe(struct platform_device *pdev)
-{
- struct oxnas_restart_context *ctx;
- struct regmap *sys_ctrl;
- struct device *dev = &pdev->dev;
- int err = 0;
-
- sys_ctrl = syscon_node_to_regmap(pdev->dev.of_node);
- if (IS_ERR(sys_ctrl))
- return PTR_ERR(sys_ctrl);
-
- ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
- if (!ctx)
- return -ENOMEM;
-
- ctx->sys_ctrl = sys_ctrl;
- ctx->restart_handler.notifier_call = ox820_restart_handle;
- ctx->restart_handler.priority = 192;
- err = register_restart_handler(&ctx->restart_handler);
- if (err)
- dev_err(dev, "can't register restart notifier (err=%d)\n", err);
-
- return err;
-}
-
-static const struct of_device_id ox820_restart_of_match[] = {
- { .compatible = "oxsemi,ox820-sys-ctrl" },
- {}
-};
-
-static struct platform_driver ox820_restart_driver = {
- .probe = ox820_restart_probe,
- .driver = {
- .name = "ox820-chip-reset",
- .of_match_table = ox820_restart_of_match,
- },
-};
-builtin_platform_driver(ox820_restart_driver);
+++ /dev/null
-/*
- * drivers/usb/host/ehci-oxnas.c
- *
- * Tzachi Perelstein <tzachi@marvell.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/mfd/syscon.h>
-#include <linux/usb.h>
-#include <linux/usb/hcd.h>
-#include <linux/dma-mapping.h>
-#include <linux/clk.h>
-#include <linux/regmap.h>
-#include <linux/reset.h>
-
-#define USBHSMPH_CTRL_REGOFFSET 0x40
-#define USBHSMPH_STAT_REGOFFSET 0x44
-#define REF300_DIV_REGOFFSET 0xF8
-#define USBHSPHY_CTRL_REGOFFSET 0x84
-#define USB_CTRL_REGOFFSET 0x90
-#define PLLB_DIV_CTRL_REGOFFSET 0x1000F8
-#define USBHSPHY_SUSPENDM_MANUAL_ENABLE 16
-#define USBHSPHY_SUSPENDM_MANUAL_STATE 15
-#define USBHSPHY_ATE_ESET 14
-#define USBHSPHY_TEST_DIN 6
-#define USBHSPHY_TEST_ADD 2
-#define USBHSPHY_TEST_DOUT_SEL 1
-#define USBHSPHY_TEST_CLK 0
-
-#define USB_CTRL_USBAPHY_CKSEL_SHIFT 5
-#define USB_CLK_XTAL0_XTAL1 (0 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
-#define USB_CLK_XTAL0 (1 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
-#define USB_CLK_INTERNAL (2 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
-
-#define USBAMUX_DEVICE BIT(4)
-
-#define USBPHY_REFCLKDIV_SHIFT 2
-#define USB_PHY_REF_12MHZ (0 << USBPHY_REFCLKDIV_SHIFT)
-#define USB_PHY_REF_24MHZ (1 << USBPHY_REFCLKDIV_SHIFT)
-#define USB_PHY_REF_48MHZ (2 << USBPHY_REFCLKDIV_SHIFT)
-
-#define USB_CTRL_USB_CKO_SEL_BIT 0
-
-#define USB_INT_CLK_XTAL 0
-#define USB_INT_CLK_REF300 2
-#define USB_INT_CLK_PLLB 3
-
-#define REF300_DIV_INT_SHIFT 8
-#define REF300_DIV_FRAC_SHIFT 0
-#define REF300_DIV_INT(val) ((val) << REF300_DIV_INT_SHIFT)
-#define REF300_DIV_FRAC(val) ((val) << REF300_DIV_FRAC_SHIFT)
-
-#define PLLB_BYPASS 1
-#define PLLB_ENSAT 3
-#define PLLB_OUTDIV 4
-#define PLLB_REFDIV 8
-#define PLLB_DIV_INT_SHIFT 8
-#define PLLB_DIV_FRAC_SHIFT 0
-#define PLLB_DIV_INT(val) ((val) << PLLB_DIV_INT_SHIFT)
-#define PLLB_DIV_FRAC(val) ((val) << PLLB_DIV_FRAC_SHIFT)
-
-#include "ehci.h"
-
-struct oxnas_hcd {
- struct clk *clk;
- struct clk *refsrc;
- struct clk *phyref;
- int use_pllb;
- int use_phya;
- struct reset_control *rst_host;
- struct reset_control *rst_phya;
- struct reset_control *rst_phyb;
- struct regmap *syscon;
-};
-
-#define DRIVER_DESC "Oxnas On-Chip EHCI Host Controller"
-
-static struct hc_driver __read_mostly oxnas_hc_driver;
-
-static void start_oxnas_usb_ehci(struct oxnas_hcd *oxnas)
-{
- if (oxnas->use_pllb) {
- /* enable pllb */
- clk_prepare_enable(oxnas->refsrc);
- /* enable ref600 */
- clk_prepare_enable(oxnas->phyref);
- /* 600MHz pllb divider for 12MHz */
- regmap_write_bits(oxnas->syscon, PLLB_DIV_CTRL_REGOFFSET, 0xffff, PLLB_DIV_INT(50) | PLLB_DIV_FRAC(0));
- } else {
- /* ref 300 divider for 12MHz */
- regmap_write_bits(oxnas->syscon, REF300_DIV_REGOFFSET, 0xffff, REF300_DIV_INT(25) | REF300_DIV_FRAC(0));
- }
-
- /* Ensure the USB block is properly reset */
- reset_control_reset(oxnas->rst_host);
- reset_control_reset(oxnas->rst_phya);
- reset_control_reset(oxnas->rst_phyb);
-
- /* Force the high speed clock to be generated all the time, via serial
- programming of the USB HS PHY */
- regmap_write_bits(oxnas->syscon, USBHSPHY_CTRL_REGOFFSET, 0xffff,
- (2UL << USBHSPHY_TEST_ADD) |
- (0xe0UL << USBHSPHY_TEST_DIN));
-
- regmap_write_bits(oxnas->syscon, USBHSPHY_CTRL_REGOFFSET, 0xffff,
- (1UL << USBHSPHY_TEST_CLK) |
- (2UL << USBHSPHY_TEST_ADD) |
- (0xe0UL << USBHSPHY_TEST_DIN));
-
- regmap_write_bits(oxnas->syscon, USBHSPHY_CTRL_REGOFFSET, 0xffff,
- (0xfUL << USBHSPHY_TEST_ADD) |
- (0xaaUL << USBHSPHY_TEST_DIN));
-
- regmap_write_bits(oxnas->syscon, USBHSPHY_CTRL_REGOFFSET, 0xffff,
- (1UL << USBHSPHY_TEST_CLK) |
- (0xfUL << USBHSPHY_TEST_ADD) |
- (0xaaUL << USBHSPHY_TEST_DIN));
-
- if (oxnas->use_pllb) /* use pllb clock */
- regmap_write_bits(oxnas->syscon, USB_CTRL_REGOFFSET, 0xffff,
- USB_CLK_INTERNAL | USB_INT_CLK_PLLB);
- else /* use ref300 derived clock */
- regmap_write_bits(oxnas->syscon, USB_CTRL_REGOFFSET, 0xffff,
- USB_CLK_INTERNAL | USB_INT_CLK_REF300);
-
- if (oxnas->use_phya) {
- /* Configure USB PHYA as a host */
- regmap_update_bits(oxnas->syscon, USB_CTRL_REGOFFSET, USBAMUX_DEVICE, 0);
- }
-
- /* Enable the clock to the USB block */
- clk_prepare_enable(oxnas->clk);
-}
-
-static void stop_oxnas_usb_ehci(struct oxnas_hcd *oxnas)
-{
- reset_control_assert(oxnas->rst_host);
- reset_control_assert(oxnas->rst_phya);
- reset_control_assert(oxnas->rst_phyb);
-
- if (oxnas->use_pllb) {
- clk_disable_unprepare(oxnas->phyref);
- clk_disable_unprepare(oxnas->refsrc);
- }
- clk_disable_unprepare(oxnas->clk);
-}
-
-static int ehci_oxnas_reset(struct usb_hcd *hcd)
-{
- #define txttfill_tuning reserved2[0]
-
- struct ehci_hcd *ehci;
- u32 tmp;
- int retval = ehci_setup(hcd);
- if (retval)
- return retval;
-
- ehci = hcd_to_ehci(hcd);
- tmp = ehci_readl(ehci, &ehci->regs->txfill_tuning);
- tmp &= ~0x00ff0000;
- tmp |= 0x003f0000; /* set burst pre load count to 0x40 (63 * 4 bytes) */
- tmp |= 0x16; /* set sheduler overhead to 22 * 1.267us (HS) or 22 * 6.33us (FS/LS)*/
- ehci_writel(ehci, tmp, &ehci->regs->txfill_tuning);
-
- tmp = ehci_readl(ehci, &ehci->regs->txttfill_tuning);
- tmp |= 0x2; /* set sheduler overhead to 2 * 6.333us */
- ehci_writel(ehci, tmp, &ehci->regs->txttfill_tuning);
-
- return retval;
-}
-
-static int ehci_oxnas_drv_probe(struct platform_device *ofdev)
-{
- struct device_node *np = ofdev->dev.of_node;
- struct usb_hcd *hcd;
- struct ehci_hcd *ehci;
- struct resource res;
- struct oxnas_hcd *oxnas;
- int irq, err;
- struct reset_control *rstc;
-
- if (usb_disabled())
- return -ENODEV;
-
- if (!ofdev->dev.dma_mask)
- ofdev->dev.dma_mask = &ofdev->dev.coherent_dma_mask;
- if (!ofdev->dev.coherent_dma_mask)
- ofdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
-
- hcd = usb_create_hcd(&oxnas_hc_driver, &ofdev->dev,
- dev_name(&ofdev->dev));
- if (!hcd)
- return -ENOMEM;
-
- err = of_address_to_resource(np, 0, &res);
- if (err)
- goto err_res;
-
- hcd->rsrc_start = res.start;
- hcd->rsrc_len = resource_size(&res);
-
- hcd->regs = devm_ioremap_resource(&ofdev->dev, &res);
- if (IS_ERR(hcd->regs)) {
- dev_err(&ofdev->dev, "devm_ioremap_resource failed\n");
- err = PTR_ERR(hcd->regs);
- goto err_ioremap;
- }
-
- oxnas = (struct oxnas_hcd *)hcd_to_ehci(hcd)->priv;
-
- oxnas->use_pllb = of_property_read_bool(np, "oxsemi,ehci_use_pllb");
- oxnas->use_phya = of_property_read_bool(np, "oxsemi,ehci_use_phya");
-
- oxnas->syscon = syscon_regmap_lookup_by_phandle(np, "oxsemi,sys-ctrl");
- if (IS_ERR(oxnas->syscon)) {
- err = PTR_ERR(oxnas->syscon);
- goto err_syscon;
- }
-
- oxnas->clk = of_clk_get_by_name(np, "usb");
- if (IS_ERR(oxnas->clk)) {
- err = PTR_ERR(oxnas->clk);
- goto err_clk;
- }
-
- if (oxnas->use_pllb) {
- oxnas->refsrc = of_clk_get_by_name(np, "refsrc");
- if (IS_ERR(oxnas->refsrc)) {
- err = PTR_ERR(oxnas->refsrc);
- goto err_refsrc;
- }
- oxnas->phyref = of_clk_get_by_name(np, "phyref");
- if (IS_ERR(oxnas->refsrc)) {
- err = PTR_ERR(oxnas->refsrc);
- goto err_phyref;
- }
-
- } else {
- oxnas->refsrc = NULL;
- oxnas->phyref = NULL;
- }
-
- rstc = devm_reset_control_get(&ofdev->dev, "host");
- if (IS_ERR(rstc)) {
- err = PTR_ERR(rstc);
- goto err_rst;
- }
- oxnas->rst_host = rstc;
-
- rstc = devm_reset_control_get(&ofdev->dev, "phya");
- if (IS_ERR(rstc)) {
- err = PTR_ERR(rstc);
- goto err_rst;
- }
- oxnas->rst_phya = rstc;
-
- rstc = devm_reset_control_get(&ofdev->dev, "phyb");
- if (IS_ERR(rstc)) {
- err = PTR_ERR(rstc);
- goto err_rst;
- }
- oxnas->rst_phyb = rstc;
-
- irq = irq_of_parse_and_map(np, 0);
- if (!irq) {
- dev_err(&ofdev->dev, "irq_of_parse_and_map failed\n");
- err = -EBUSY;
- goto err_irq;
- }
-
- hcd->has_tt = 1;
- ehci = hcd_to_ehci(hcd);
- ehci->caps = hcd->regs;
-
- start_oxnas_usb_ehci(oxnas);
-
- err = usb_add_hcd(hcd, irq, IRQF_SHARED);
- if (err)
- goto err_hcd;
-
- return 0;
-
-err_hcd:
- stop_oxnas_usb_ehci(oxnas);
-err_irq:
-err_rst:
- if (oxnas->phyref)
- clk_put(oxnas->phyref);
-err_phyref:
- if (oxnas->refsrc)
- clk_put(oxnas->refsrc);
-err_refsrc:
- clk_put(oxnas->clk);
-err_syscon:
-err_clk:
-err_ioremap:
-err_res:
- usb_put_hcd(hcd);
-
- return err;
-}
-
-static int ehci_oxnas_drv_remove(struct platform_device *pdev)
-{
- struct usb_hcd *hcd = platform_get_drvdata(pdev);
- struct oxnas_hcd *oxnas = (struct oxnas_hcd *)hcd_to_ehci(hcd)->priv;
-
- usb_remove_hcd(hcd);
- if (oxnas->use_pllb) {
- clk_disable_unprepare(oxnas->phyref);
- clk_put(oxnas->phyref);
- clk_disable_unprepare(oxnas->refsrc);
- clk_put(oxnas->refsrc);
- }
- clk_disable_unprepare(oxnas->clk);
- usb_put_hcd(hcd);
-
- return 0;
-}
-
-static const struct of_device_id oxnas_ehci_dt_ids[] = {
- { .compatible = "plxtech,nas782x-ehci" },
- { /* sentinel */ }
-};
-
-MODULE_DEVICE_TABLE(of, oxnas_ehci_dt_ids);
-
-static struct platform_driver ehci_oxnas_driver = {
- .probe = ehci_oxnas_drv_probe,
- .remove = ehci_oxnas_drv_remove,
- .shutdown = usb_hcd_platform_shutdown,
- .driver.name = "oxnas-ehci",
- .driver.of_match_table = oxnas_ehci_dt_ids,
-};
-
-static const struct ehci_driver_overrides oxnas_overrides __initconst = {
- .reset = ehci_oxnas_reset,
- .extra_priv_size = sizeof(struct oxnas_hcd),
-};
-
-static int __init ehci_oxnas_init(void)
-{
- if (usb_disabled())
- return -ENODEV;
-
- ehci_init_driver(&oxnas_hc_driver, &oxnas_overrides);
- return platform_driver_register(&ehci_oxnas_driver);
-}
-module_init(ehci_oxnas_init);
-
-static void __exit ehci_oxnas_cleanup(void)
-{
- platform_driver_unregister(&ehci_oxnas_driver);
-}
-module_exit(ehci_oxnas_cleanup);
-
-MODULE_DESCRIPTION(DRIVER_DESC);
-MODULE_ALIAS("platform:oxnas-ehci");
-MODULE_LICENSE("GPL");
+++ /dev/null
-include $(TOPDIR)/rules.mk
-include $(INCLUDE_DIR)/image.mk
-
-VMLINUX:=$(BIN_DIR)/$(IMG_PREFIX)-vmlinux
-UIMAGE:=$(BIN_DIR)/$(IMG_PREFIX)-uImage
-
-include $(SUBTARGET).mk
-
-$(eval $(call BuildImage))
+++ /dev/null
-KERNEL_LOADADDR := 0x48008000
-
-define Device/Default
- KERNEL_NAME := zImage
- KERNEL_SUFFIX := -uImage
- KERNEL_INSTALL := 1
- FILESYSTEMS := squashfs ext4
- PROFILES := Default
- DEVICE_DTS := ox810se-$(subst _,-,$(1))
- IMAGES := sysupgrade.tar
- IMAGE/sysupgrade.tar := sysupgrade-tar | append-metadata
-endef
-
-define Device/wd_mbwe
- DEVICE_VENDOR := Western Digital
- DEVICE_MODEL := My Book
- DEVICE_VARIANT := World Edition
- KERNEL := kernel-bin | append-dtb | uImage none
-endef
-TARGET_DEVICES += wd_mbwe
+++ /dev/null
-UBIFS_OPTS := -m 2048 -e 126KiB -c 4096
-KERNEL_LOADADDR := 0x60008000
-
-define Device/Default
- KERNEL_NAME := zImage
- KERNEL_SUFFIX := -uImage
- KERNEL_INSTALL := 1
- BLOCKSIZE := 128k
- PAGESIZE := 2048
- SUBPAGESIZE := 512
- FILESYSTEMS := squashfs ubifs
- PROFILES := Default
- DEVICE_DTS := ox820-$(subst _,-,$(1))
- KERNEL := kernel-bin | append-dtb | uImage none
- IMAGES := ubinized.bin sysupgrade.tar
- IMAGE/ubinized.bin := append-ubi
- IMAGE/sysupgrade.tar := sysupgrade-tar | append-metadata
-endef
-
-define Build/omninas-factory
- rm -rf $@.tmp $@.dummy $@.dummy.gz
- mkdir -p $@.tmp
- $(CP) $@ $@.tmp/uImage
- dd if=/dev/zero bs=64k count=4 of=$@.dummy
- gzip $@.dummy
- mkimage -A arm -T ramdisk -C gzip -n "dummy" \
- -d $@.dummy.gz \
- $@.tmp/rdimg.gz
- echo 2.35.20140102 > $@.tmp/version ; echo >> $@.tmp/version
- chmod 0744 $@.tmp/*
- $(TAR) -C $@.tmp -czvf $@ \
- $(if $(SOURCE_DATE_EPOCH),--mtime="@$(SOURCE_DATE_EPOCH)") .
-endef
-
-define Build/encrypt-3des
- openssl enc -des3 -a -k $(1) -in $@ -out $@.new && mv $@.new $@
-endef
-
-define Device/akitio_mycloud
- DEVICE_VENDOR := Akitio
- DEVICE_MODEL := MyCloud Mini
- SUPPORTED_DEVICES += akitio
- DEVICE_PACKAGES := kmod-ata-oxnas-sata kmod-i2c-gpio kmod-rtc-ds1307 \
- kmod-usb2-oxnas kmod-usb-ledtrig-usbport
-endef
-TARGET_DEVICES += akitio_mycloud
-
-define Device/cloudengines_pogoplugpro
- DEVICE_VENDOR := Cloud Engines
- DEVICE_MODEL := PogoPlug Pro (with mPCIe)
- SUPPORTED_DEVICES += pogoplug-pro
- DEVICE_PACKAGES := kmod-usb2-oxnas kmod-usb-ledtrig-usbport \
- kmod-ata-oxnas-sata kmod-rt2800-pci wpad-basic-mbedtls
-endef
-TARGET_DEVICES += cloudengines_pogoplugpro
-
-define Device/cloudengines_pogoplug-series-3
- DEVICE_VENDOR := Cloud Engines
- DEVICE_MODEL := PogoPlug Series V3 (without mPCIe)
- SUPPORTED_DEVICES += cloudengines,pogoplugv3 pogoplug-v3
- DEVICE_PACKAGES := kmod-usb2-oxnas kmod-usb-ledtrig-usbport \
- kmod-ata-oxnas-sata
-endef
-TARGET_DEVICES += cloudengines_pogoplug-series-3
-
-define Device/shuttle_kd20
- DEVICE_VENDOR := Shuttle
- DEVICE_MODEL := KD20
- SUPPORTED_DEVICES += kd20
- DEVICE_PACKAGES := kmod-usb2-oxnas kmod-usb3 kmod-usb-ledtrig-usbport \
- kmod-i2c-gpio kmod-rtc-pcf8563 kmod-gpio-beeper kmod-hwmon-drivetemp \
- kmod-hwmon-gpiofan kmod-ata-oxnas-sata kmod-md-mod kmod-md-raid0 \
- kmod-md-raid1 kmod-fs-ext4 kmod-fs-xfs
-endef
-TARGET_DEVICES += shuttle_kd20
-
-define Device/mitrastar_stg-212
- DEVICE_VENDOR := MitraStar
- DEVICE_MODEL := STG-212
- SUPPORTED_DEVICES += stg212
- DEVICE_PACKAGES := kmod-ata-oxnas-sata kmod-fs-ext4 kmod-fs-xfs \
- kmod-usb2-oxnas kmod-usb-ledtrig-usbport
-endef
-TARGET_DEVICES += mitrastar_stg-212
+++ /dev/null
-define KernelPackage/ata-oxnas-sata
- TITLE:=oxnas Serial ATA support
- KCONFIG:=CONFIG_SATA_OXNAS
- FILES:=$(LINUX_DIR)/drivers/ata/sata_oxnas.ko
- AUTOLOAD:=$(call AutoLoad,41,sata_oxnas,1)
- $(call AddDepends/ata,@TARGET_oxnas)
-endef
-
-define KernelPackage/ata-oxnas-sata/description
- SATA support for OX934 core found in the OX8xx/PLX782x SoCs
-endef
-
-$(eval $(call KernelPackage,ata-oxnas-sata))
-
-
-define KernelPackage/usb2-oxnas
- TITLE:=OX820 EHCI driver
- KCONFIG:=CONFIG_USB_EHCI_OXNAS
- FILES:=$(LINUX_DIR)/drivers/usb/host/ehci-oxnas.ko
- AUTOLOAD:=$(call AutoLoad,55,ehci-oxnas,1)
- $(call AddDepends/usb,@TARGET_oxnas_ox820 +kmod-usb2)
-endef
-
-define KernelPackage/usb2-oxnas/description
- This driver provides USB Device Controller support for the
- EHCI USB host built-in to the OX820 SoC.
-endef
-
-$(eval $(call KernelPackage,usb2-oxnas))
+++ /dev/null
-# CONFIG_CACHE_L2X0 is not set
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
-# CONFIG_DEBUG_UNCOMPRESS is not set
-CONFIG_EXT4_FS=y
-CONFIG_FS_MBCACHE=y
-CONFIG_MACH_OX810SE=y
+++ /dev/null
-define Profile/Default
- NAME:=Default Profile
- PRIORITY:=1
-endef
-
-define Profile/Default/Description
- Default package set compatible with most boards.
-endef
-
-$(eval $(call Profile,Default))
+++ /dev/null
-FEATURES+=source-only
-
-SUBTARGET:=ox810se
-BOARDNAME:=OX810SE
-CPU_TYPE:=arm926ej-s
-
-define Target/Description
- Oxford OX810SE
-endef
+++ /dev/null
-CONFIG_ARCH_HAS_TICK_BROADCAST=y
-# CONFIG_ARCH_MULTI_CPU_AUTO is not set
-CONFIG_ARCH_MULTI_V6=y
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_WANT_LIBATA_LEDS=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_HEAVY_MB=y
-CONFIG_ATA_LEDS=y
-CONFIG_CACHE_L2X0=y
-# CONFIG_CACHE_L2X0_PMU is not set
-CONFIG_CPU_32v6=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_ABRT_EV6=y
-# CONFIG_CPU_BPREDICT_DISABLE is not set
-CONFIG_CPU_CACHE_V6=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_HAS_ASID=y
-# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
-CONFIG_CPU_PABRT_V6=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_TLB_V6=y
-CONFIG_CPU_V6K=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_LL=y
-CONFIG_DEBUG_LL_INCLUDE="debug/8250.S"
-CONFIG_DEBUG_LL_UART_8250=y
-# CONFIG_DEBUG_UART_8250 is not set
-# CONFIG_DEBUG_UART_8250_FLOW_CONTROL is not set
-CONFIG_DEBUG_UART_8250_SHIFT=0
-CONFIG_DEBUG_UART_PHYS=0x44200000
-CONFIG_DEBUG_UART_VIRT=0xf4200000
-CONFIG_DEBUG_UNCOMPRESS=y
-CONFIG_DMA_CACHE_RWFO=y
-CONFIG_FORCE_MAX_ZONEORDER=12
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_HAVE_ARM_SCU=y
-CONFIG_HAVE_ARM_TWD=y
-CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
-CONFIG_HAVE_HW_BREAKPOINT=y
-CONFIG_HAVE_SMP=y
-CONFIG_HOTPLUG_CPU=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_MACH_OX820=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGHT_HAVE_PCI=y
-# CONFIG_MTD_CFI is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_NAND_ECC=y
-# CONFIG_MTD_NAND_ECC_SW_BCH is not set
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
-# CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set
-CONFIG_MTD_NAND_OXNAS=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NR_CPUS=16
-CONFIG_OUTER_CACHE=y
-CONFIG_OUTER_CACHE_SYNC=y
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_OXNAS=y
-CONFIG_PCIE_PME=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-# CONFIG_PL310_ERRATA_588369 is not set
-# CONFIG_PL310_ERRATA_727915 is not set
-# CONFIG_PL310_ERRATA_753970 is not set
-# CONFIG_PL310_ERRATA_769419 is not set
-CONFIG_PM_SLEEP_SMP=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UBIFS_FS=y
-CONFIG_UBIFS_FS_SECURITY=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress-ox820.h"
-CONFIG_XPS=y
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0-only
-#
-# Copyright (C) 2016 OpenWrt.org
-
-define Profile/Default
- NAME:=Default Profile
- PRIORITY:=1
- PACKAGES:=\
- kmod-i2c-gpio kmod-gpio-beeper kmod-hwmon-gpiofan \
- kmod-rtc-pcf8563 kmod-rtc-ds1307 kmod-usb3
-endef
-
-define Profile/Default/Description
- Default package set compatible with most boards.
-endef
-
-$(eval $(call Profile,Default))
+++ /dev/null
-SUBTARGET:=ox820
-BOARDNAME:=OX820/NAS782x
-CPU_TYPE:=mpcore
-FEATURES+=nand pci pcie ubifs usb
-
-define Target/Description
- Oxford/PLXTECH OX820/NAS782x
-endef
\ No newline at end of file
+++ /dev/null
-- add compatible string
-- add console to bootargs
-- add led aliases
-- adjust nand partition table
----
---- a/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts
-+++ b/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts
-@@ -11,10 +11,10 @@
- / {
- model = "Cloud Engines PogoPlug Series 3";
-
-- compatible = "cloudengines,pogoplugv3", "oxsemi,ox820";
-+ compatible = "cloudengines,pogoplug-series-3", "cloudengines,pogoplugv3", "oxsemi,ox820";
-
- chosen {
-- bootargs = "earlyprintk";
-+ bootargs = "earlyprintk console=ttyS0,115200";
- stdout-path = "serial0:115200n8";
- };
-
-@@ -27,24 +27,28 @@
- serial0 = &uart0;
- gpio0 = &gpio0;
- gpio1 = &gpio1;
-+ led-boot = &led_status;
-+ led-failsafe = &led_warn;
-+ led-running = &led_act;
-+ led-upgrade = &led_warn;
- };
-
- leds {
- compatible = "gpio-leds";
-
-- blue {
-+ led_status: blue {
- label = "pogoplug:blue";
- gpios = <&gpio0 2 0>;
- default-state = "keep";
- };
-
-- orange {
-+ led_warn: orange {
- label = "pogoplug:orange";
- gpios = <&gpio1 16 1>;
- default-state = "keep";
- };
-
-- green {
-+ led_act: green {
- label = "pogoplug:green";
- gpios = <&gpio1 17 1>;
- default-state = "keep";
-@@ -73,11 +77,27 @@
- nand-ecc-algo = "hamming";
-
- partition@0 {
-- label = "boot";
-- reg = <0x00000000 0x00e00000>;
-+ label = "stage1";
-+ reg = <0x00000000 0x00040000>;
- read-only;
- };
-
-+ partition@40000 {
-+ label = "u-boot";
-+ reg = <0x00040000 0x00380000>;
-+ read-only;
-+ };
-+
-+ partition@3c0000 {
-+ label = "u-boot-env";
-+ reg = <0x003c0000 0x00080000>;
-+ };
-+
-+ partition@440000 {
-+ label = "kernel";
-+ reg = <0x00440000 0x009c0000>;
-+ };
-+
- partition@e00000 {
- label = "ubi";
- reg = <0x00e00000 0x07200000>;
+++ /dev/null
-From 552ed4955c1fee1109bf5ba137dc35a411a1448c Mon Sep 17 00:00:00 2001
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Fri, 1 Jun 2018 02:41:15 +0200
-Subject: [PATCH] arm: ox820: remove left-overs
-
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/clk/clk-oxnas.c | 2 --
- include/dt-bindings/clock/oxsemi,ox820.h | 32 +++++++++++-------------
- 2 files changed, 14 insertions(+), 20 deletions(-)
-
---- a/drivers/clk/clk-oxnas.c
-+++ b/drivers/clk/clk-oxnas.c
-@@ -29,8 +29,6 @@ struct oxnas_stdclk_data {
- struct clk_hw_onecell_data *onecell_data;
- struct clk_oxnas_gate **gates;
- unsigned int ngates;
-- struct clk_oxnas_pll **plls;
-- unsigned int nplls;
- };
-
- /* Regmap offsets */
---- a/include/dt-bindings/clock/oxsemi,ox820.h
-+++ b/include/dt-bindings/clock/oxsemi,ox820.h
-@@ -6,24 +6,20 @@
- #ifndef DT_CLOCK_OXSEMI_OX820_H
- #define DT_CLOCK_OXSEMI_OX820_H
-
--/* PLLs */
--#define CLK_820_PLLA 0
--#define CLK_820_PLLB 1
--
- /* Gate Clocks */
--#define CLK_820_LEON 2
--#define CLK_820_DMA_SGDMA 3
--#define CLK_820_CIPHER 4
--#define CLK_820_SD 5
--#define CLK_820_SATA 6
--#define CLK_820_AUDIO 7
--#define CLK_820_USBMPH 8
--#define CLK_820_ETHA 9
--#define CLK_820_PCIEA 10
--#define CLK_820_NAND 11
--#define CLK_820_PCIEB 12
--#define CLK_820_ETHB 13
--#define CLK_820_REF600 14
--#define CLK_820_USBDEV 15
-+#define CLK_820_LEON 0
-+#define CLK_820_DMA_SGDMA 1
-+#define CLK_820_CIPHER 2
-+#define CLK_820_SD 3
-+#define CLK_820_SATA 4
-+#define CLK_820_AUDIO 5
-+#define CLK_820_USBMPH 6
-+#define CLK_820_ETHA 7
-+#define CLK_820_PCIEA 8
-+#define CLK_820_NAND 9
-+#define CLK_820_PCIEB 10
-+#define CLK_820_ETHB 11
-+#define CLK_820_REF600 12
-+#define CLK_820_USBDEV 13
-
- #endif /* DT_CLOCK_OXSEMI_OX820_H */
+++ /dev/null
---- a/drivers/clk/clk-oxnas.c
-+++ b/drivers/clk/clk-oxnas.c
-@@ -5,19 +5,42 @@
- * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
- */
-
-+#include <linux/clk.h>
-+#include <linux/clkdev.h>
- #include <linux/clk-provider.h>
- #include <linux/kernel.h>
- #include <linux/init.h>
-+#include <linux/delay.h>
- #include <linux/of.h>
- #include <linux/of_device.h>
- #include <linux/platform_device.h>
- #include <linux/stringify.h>
- #include <linux/regmap.h>
- #include <linux/mfd/syscon.h>
-+#include <linux/reset.h>
-
- #include <dt-bindings/clock/oxsemi,ox810se.h>
- #include <dt-bindings/clock/oxsemi,ox820.h>
-
-+#define REF300_DIV_INT_SHIFT 8
-+#define REF300_DIV_FRAC_SHIFT 0
-+#define REF300_DIV_INT(val) ((val) << REF300_DIV_INT_SHIFT)
-+#define REF300_DIV_FRAC(val) ((val) << REF300_DIV_FRAC_SHIFT)
-+
-+#define PLLB_BYPASS 1
-+#define PLLB_ENSAT 3
-+#define PLLB_OUTDIV 4
-+#define PLLB_REFDIV 8
-+#define PLLB_DIV_INT_SHIFT 8
-+#define PLLB_DIV_FRAC_SHIFT 0
-+#define PLLB_DIV_INT(val) ((val) << PLLB_DIV_INT_SHIFT)
-+#define PLLB_DIV_FRAC(val) ((val) << PLLB_DIV_FRAC_SHIFT)
-+
-+#define PLLA_REFDIV_MASK 0x3F
-+#define PLLA_REFDIV_SHIFT 8
-+#define PLLA_OUTDIV_MASK 0x7
-+#define PLLA_OUTDIV_SHIFT 4
-+
- /* Standard regmap gate clocks */
- struct clk_oxnas_gate {
- struct clk_hw hw;
-@@ -36,6 +59,135 @@ struct oxnas_stdclk_data {
- #define CLK_SET_REGOFFSET 0x2c
- #define CLK_CLR_REGOFFSET 0x30
-
-+#define PLLA_CTRL0_REGOFFSET 0x1f0
-+#define PLLA_CTRL1_REGOFFSET 0x1f4
-+#define PLLB_CTRL0_REGOFFSET 0x1001f0
-+#define MHZ (1000 * 1000)
-+
-+struct clk_oxnas_pll {
-+ struct clk_hw hw;
-+ struct device_node *devnode;
-+ struct reset_control *rstc;
-+ struct regmap *syscon;
-+};
-+
-+#define to_clk_oxnas_pll(_hw) container_of(_hw, struct clk_oxnas_pll, hw)
-+
-+static unsigned long plla_clk_recalc_rate(struct clk_hw *hw,
-+ unsigned long parent_rate)
-+{
-+ struct clk_oxnas_pll *plla = to_clk_oxnas_pll(hw);
-+ unsigned long fin = parent_rate;
-+ unsigned long refdiv, outdiv;
-+ unsigned int pll0, fbdiv;
-+
-+ BUG_ON(regmap_read(plla->syscon, PLLA_CTRL0_REGOFFSET, &pll0));
-+
-+ refdiv = (pll0 >> PLLA_REFDIV_SHIFT) & PLLA_REFDIV_MASK;
-+ refdiv += 1;
-+ outdiv = (pll0 >> PLLA_OUTDIV_SHIFT) & PLLA_OUTDIV_MASK;
-+ outdiv += 1;
-+
-+ BUG_ON(regmap_read(plla->syscon, PLLA_CTRL1_REGOFFSET, &fbdiv));
-+ /* seems we will not be here when pll is bypassed, so ignore this
-+ * case */
-+
-+ return fin / MHZ * fbdiv / (refdiv * outdiv) / 32768 * MHZ;
-+}
-+
-+static const char *pll_clk_parents[] = {
-+ "oscillator",
-+};
-+
-+static struct clk_ops plla_ops = {
-+ .recalc_rate = plla_clk_recalc_rate,
-+};
-+
-+static struct clk_init_data clk_plla_init = {
-+ .name = "plla",
-+ .ops = &plla_ops,
-+ .parent_names = pll_clk_parents,
-+ .num_parents = ARRAY_SIZE(pll_clk_parents),
-+};
-+
-+static int pllb_clk_is_prepared(struct clk_hw *hw)
-+{
-+ struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw);
-+
-+ return !!pllb->rstc;
-+}
-+
-+static int pllb_clk_prepare(struct clk_hw *hw)
-+{
-+ struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw);
-+
-+ pllb->rstc = of_reset_control_get(pllb->devnode, NULL);
-+
-+ return IS_ERR(pllb->rstc) ? PTR_ERR(pllb->rstc) : 0;
-+}
-+
-+static void pllb_clk_unprepare(struct clk_hw *hw)
-+{
-+ struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw);
-+
-+ BUG_ON(IS_ERR(pllb->rstc));
-+
-+ reset_control_put(pllb->rstc);
-+ pllb->rstc = NULL;
-+}
-+
-+static int pllb_clk_enable(struct clk_hw *hw)
-+{
-+ struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw);
-+
-+ BUG_ON(IS_ERR(pllb->rstc));
-+
-+ /* put PLL into bypass */
-+ regmap_update_bits(pllb->syscon, PLLB_CTRL0_REGOFFSET, BIT(PLLB_BYPASS), BIT(PLLB_BYPASS));
-+ wmb();
-+ udelay(10);
-+ reset_control_assert(pllb->rstc);
-+ udelay(10);
-+ /* set PLL B control information */
-+ regmap_write_bits(pllb->syscon, PLLB_CTRL0_REGOFFSET, 0xffff,
-+ (1 << PLLB_ENSAT) | (1 << PLLB_OUTDIV) | (2 << PLLB_REFDIV));
-+ reset_control_deassert(pllb->rstc);
-+ udelay(100);
-+ regmap_update_bits(pllb->syscon, PLLB_CTRL0_REGOFFSET, BIT(PLLB_BYPASS), 0);
-+
-+ return 0;
-+}
-+
-+static void pllb_clk_disable(struct clk_hw *hw)
-+{
-+ struct clk_oxnas_pll *pllb = to_clk_oxnas_pll(hw);
-+
-+ BUG_ON(IS_ERR(pllb->rstc));
-+
-+ /* put PLL into bypass */
-+ regmap_update_bits(pllb->syscon, PLLB_CTRL0_REGOFFSET, BIT(PLLB_BYPASS), BIT(PLLB_BYPASS));
-+
-+ wmb();
-+ udelay(10);
-+
-+ reset_control_assert(pllb->rstc);
-+}
-+
-+static struct clk_ops pllb_ops = {
-+ .prepare = pllb_clk_prepare,
-+ .unprepare = pllb_clk_unprepare,
-+ .is_prepared = pllb_clk_is_prepared,
-+ .enable = pllb_clk_enable,
-+ .disable = pllb_clk_disable,
-+};
-+
-+static struct clk_init_data clk_pllb_init = {
-+ .name = "pllb",
-+ .ops = &pllb_ops,
-+ .parent_names = pll_clk_parents,
-+ .num_parents = ARRAY_SIZE(pll_clk_parents),
-+};
-+
- static inline struct clk_oxnas_gate *to_clk_oxnas_gate(struct clk_hw *hw)
- {
- return container_of(hw, struct clk_oxnas_gate, hw);
-@@ -251,3 +403,42 @@ static struct platform_driver oxnas_stdc
- },
- };
- builtin_platform_driver(oxnas_stdclk_driver);
-+
-+void __init oxnas_init_plla(struct device_node *np)
-+{
-+ struct clk *clk;
-+ struct clk_oxnas_pll *plla;
-+
-+ plla = kmalloc(sizeof(*plla), GFP_KERNEL);
-+ BUG_ON(!plla);
-+
-+ plla->syscon = syscon_node_to_regmap(of_get_parent(np));
-+ plla->hw.init = &clk_plla_init;
-+ plla->devnode = np;
-+ plla->rstc = NULL;
-+ clk = clk_register(NULL, &plla->hw);
-+ BUG_ON(IS_ERR(clk));
-+ /* mark it as enabled */
-+ clk_prepare_enable(clk);
-+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
-+}
-+CLK_OF_DECLARE(oxnas_plla, "plxtech,nas782x-plla", oxnas_init_plla);
-+
-+void __init oxnas_init_pllb(struct device_node *np)
-+{
-+ struct clk *clk;
-+ struct clk_oxnas_pll *pllb;
-+
-+ pllb = kmalloc(sizeof(*pllb), GFP_KERNEL);
-+ BUG_ON(!pllb);
-+
-+ pllb->syscon = syscon_node_to_regmap(of_get_parent(np));
-+ pllb->hw.init = &clk_pllb_init;
-+ pllb->devnode = np;
-+ pllb->rstc = NULL;
-+
-+ clk = clk_register(NULL, &pllb->hw);
-+ BUG_ON(IS_ERR(clk));
-+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
-+}
-+CLK_OF_DECLARE(oxnas_pllb, "plxtech,nas782x-pllb", oxnas_init_pllb);
---- a/arch/arm/boot/dts/ox820.dtsi
-+++ b/arch/arm/boot/dts/ox820.dtsi
-@@ -61,12 +61,6 @@
- clocks = <&osc>;
- };
-
-- plla: plla {
-- compatible = "fixed-clock";
-- #clock-cells = <0>;
-- clock-frequency = <850000000>;
-- };
--
- armclk: armclk {
- compatible = "fixed-factor-clock";
- #clock-cells = <0>;
-@@ -266,6 +260,19 @@
- compatible = "oxsemi,ox820-stdclk", "oxsemi,ox810se-stdclk";
- #clock-cells = <1>;
- };
-+
-+ plla: plla {
-+ compatible = "plxtech,nas782x-plla";
-+ #clock-cells = <0>;
-+ clocks = <&osc>;
-+ };
-+
-+ pllb: pllb {
-+ compatible = "plxtech,nas782x-pllb";
-+ #clock-cells = <0>;
-+ clocks = <&osc>;
-+ resets = <&reset RESET_PLLB>;
-+ };
- };
- };
-
-@@ -287,6 +294,13 @@
- clocks = <&armclk>;
- };
-
-+ watchdog@620 {
-+ compatible = "mpcore_wdt";
-+ reg = <0x620 0x20>;
-+ interrupts = <GIC_PPI 14 (GIC_CPU_MASK_RAW(3)|IRQ_TYPE_LEVEL_HIGH)>;
-+ clocks = <&armclk>;
-+ };
-+
- gic: interrupt-controller@1000 {
- compatible = "arm,arm11mp-gic";
- interrupt-controller;
+++ /dev/null
---- a/drivers/power/reset/Kconfig
-+++ b/drivers/power/reset/Kconfig
-@@ -148,6 +148,12 @@ config POWER_RESET_OXNAS
- help
- Restart support for OXNAS/PLXTECH OX820 SoC.
-
-+config POWER_RESET_OXNAS
-+ bool "OXNAS SoC restart driver"
-+ depends on ARCH_OXNAS
-+ help
-+ Restart support for OXNAS boards.
-+
- config POWER_RESET_PIIX4_POWEROFF
- tristate "Intel PIIX4 power-off driver"
- depends on PCI
---- a/drivers/power/reset/Makefile
-+++ b/drivers/power/reset/Makefile
-@@ -19,6 +19,7 @@ obj-$(CONFIG_POWER_RESET_QCOM_PON) += qc
- obj-$(CONFIG_POWER_RESET_OCELOT_RESET) += ocelot-reset.o
- obj-$(CONFIG_POWER_RESET_PIIX4_POWEROFF) += piix4-poweroff.o
- obj-$(CONFIG_POWER_RESET_LTC2952) += ltc2952-poweroff.o
-+obj-$(CONFIG_POWER_RESET_OXNAS) += oxnas-restart.o
- obj-$(CONFIG_POWER_RESET_QNAP) += qnap-poweroff.o
- obj-$(CONFIG_POWER_RESET_REGULATOR) += regulator-poweroff.o
- obj-$(CONFIG_POWER_RESET_RESTART) += restart-poweroff.o
+++ /dev/null
---- a/arch/arm/boot/dts/ox820.dtsi
-+++ b/arch/arm/boot/dts/ox820.dtsi
-@@ -247,6 +247,15 @@
- };
- };
-
-+ pcie_phy: pcie-phy@a00000 {
-+ compatible = "oxsemi,ox820-pcie-phy";
-+ reg = <0xa00000 0x10>;
-+ #phy-cells = <0>;
-+ resets = <&reset RESET_PCIEPHY>;
-+ reset-names = "phy";
-+ status = "disabled";
-+ };
-+
- sys: sys-ctrl@e00000 {
- compatible = "oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd";
- reg = <0xe00000 0x200000>;
---- a/drivers/phy/Kconfig
-+++ b/drivers/phy/Kconfig
-@@ -35,6 +35,13 @@ config PHY_LPC18XX_USB_OTG
- This driver is need for USB0 support on LPC18xx/43xx and takes
- care of enabling and clock setup.
-
-+config PHY_OXNAS
-+ tristate "Oxford Semi. OX820 PCI-E PHY support"
-+ depends on HAS_IOMEM && OF && (ARM || COMPILE_TEST)
-+ select GENERIC_PHY
-+ help
-+ This option enables support for OXNAS OX820 SoC PCIE PHY.
-+
- config PHY_PISTACHIO_USB
- tristate "IMG Pistachio USB2.0 PHY driver"
- depends on MIPS || COMPILE_TEST
---- a/drivers/phy/Makefile
-+++ b/drivers/phy/Makefile
-@@ -7,6 +7,7 @@ obj-$(CONFIG_GENERIC_PHY) += phy-core.o
- obj-$(CONFIG_GENERIC_PHY_MIPI_DPHY) += phy-core-mipi-dphy.o
- obj-$(CONFIG_PHY_CAN_TRANSCEIVER) += phy-can-transceiver.o
- obj-$(CONFIG_PHY_LPC18XX_USB_OTG) += phy-lpc18xx-usb-otg.o
-+obj-$(CONFIG_PHY_OXNAS) += phy-oxnas-pcie.o
- obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
- obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
- obj-$(CONFIG_USB_LGM_PHY) += phy-lgm-usb.o
+++ /dev/null
---- a/drivers/pci/controller/Kconfig
-+++ b/drivers/pci/controller/Kconfig
-@@ -312,6 +312,11 @@ config PCIE_HISI_ERR
- Say Y here if you want error handling support
- for the PCIe controller's errors on HiSilicon HIP SoCs
-
-+config PCIE_OXNAS
-+ bool "PLX Oxnas PCIe controller"
-+ depends on ARCH_OXNAS
-+ select PCIEPORTBUS
-+
- source "drivers/pci/controller/dwc/Kconfig"
- source "drivers/pci/controller/mobiveil/Kconfig"
- source "drivers/pci/controller/cadence/Kconfig"
---- a/drivers/pci/controller/Makefile
-+++ b/drivers/pci/controller/Makefile
-@@ -33,6 +33,7 @@ obj-$(CONFIG_PCIE_ROCKCHIP_HOST) += pcie
- obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
- obj-$(CONFIG_PCIE_MEDIATEK_GEN3) += pcie-mediatek-gen3.o
- obj-$(CONFIG_PCIE_MICROCHIP_HOST) += pcie-microchip-host.o
-+obj-$(CONFIG_PCIE_OXNAS) += pcie-oxnas.o
- obj-$(CONFIG_VMD) += vmd.o
- obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
- obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o
---- a/arch/arm/boot/dts/ox820.dtsi
-+++ b/arch/arm/boot/dts/ox820.dtsi
-@@ -289,7 +289,7 @@
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
-- ranges = <0 0x47000000 0x1000000>;
-+ ranges = <0 0x47000000 0x2000>;
-
- scu: scu@0 {
- compatible = "arm,arm11mp-scu";
-@@ -318,5 +318,86 @@
- <0x100 0x500>;
- };
- };
-+
-+ pcie0: pcie@47c00000 {
-+ compatible = "plxtech,nas782x-pcie";
-+ device_type = "pci";
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+
-+ /* flag & space bus address host address size */
-+ ranges = < 0x82000000 0 0x48000000 0x48000000 0 0x2000000
-+ 0xC2000000 0 0x4A000000 0x4A000000 0 0x1E00000
-+ 0x81000000 0 0x4BE00000 0x4BE00000 0 0x0100000
-+ 0x80000000 0 0x4BF00000 0x4BF00000 0 0x0100000>;
-+
-+ bus-range = <0x00 0x7f>;
-+
-+ /* cfg inbound translator */
-+ reg = <0x47c00000 0x1000>, <0x47d00000 0x100>;
-+
-+ phys = <&pcie_phy>;
-+ phy-names = "pcie-phy";
-+
-+ #interrupt-cells = <1>;
-+ /* wild card mask, match all bus address & interrupt specifier */
-+ /* format: bus address mask, interrupt specifier mask */
-+ /* each bit 1 means need match, 0 means ignored when match */
-+ interrupt-map-mask = <0 0 0 0>;
-+ /* format: a list of: bus address, interrupt specifier,
-+ * parent interrupt controller & specifier */
-+ interrupt-map = <0 0 0 0 &gic 0 19 0x304>;
-+ gpios = <&gpio1 12 0>;
-+ clocks = <&stdclk CLK_820_PCIEA>, <&pllb>;
-+ clock-names = "pcie", "busclk";
-+ resets = <&reset RESET_PCIEA>;
-+ reset-names = "pcie";
-+
-+ plxtech,pcie-hcsl-bit = <2>;
-+ plxtech,pcie-ctrl-offset = <0x120>;
-+ plxtech,pcie-outbound-offset = <0x138>;
-+ status = "disabled";
-+ };
-+
-+ pcie1: pcie@47e00000 {
-+ compatible = "plxtech,nas782x-pcie";
-+ device_type = "pci";
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+
-+ /* flag & space bus address host address size */
-+ ranges = < 0x82000000 0 0x4C000000 0x4C000000 0 0x2000000
-+ 0xC2000000 0 0x4E000000 0x4E000000 0 0x1E00000
-+ 0x81000000 0 0x4FE00000 0x4FE00000 0 0x0100000
-+ 0x80000000 0 0x4FF00000 0x4FF00000 0 0x0100000>;
-+
-+ bus-range = <0x80 0xff>;
-+
-+ /* cfg inbound translator */
-+ reg = <0x47e00000 0x1000>, <0x47f00000 0x100>;
-+
-+ phys = <&pcie_phy>;
-+ phy-names = "pcie-phy";
-+
-+ #interrupt-cells = <1>;
-+ /* wild card mask, match all bus address & interrupt specifier */
-+ /* format: bus address mask, interrupt specifier mask */
-+ /* each bit 1 means need match, 0 means ignored when match */
-+ interrupt-map-mask = <0 0 0 0>;
-+ /* format: a list of: bus address, interrupt specifier,
-+ * parent interrupt controller & specifier */
-+ interrupt-map = <0 0 0 0 &gic 0 20 0x304>;
-+
-+ /* gpios = <&gpio1 12 0>; */
-+ clocks = <&stdclk CLK_820_PCIEB>, <&pllb>;
-+ clock-names = "pcie", "busclk";
-+ resets = <&reset RESET_PCIEB>;
-+ reset-names = "pcie";
-+
-+ plxtech,pcie-hcsl-bit = <3>;
-+ plxtech,pcie-ctrl-offset = <0x124>;
-+ plxtech,pcie-outbound-offset = <0x174>;
-+ status = "disabled";
-+ };
- };
- };
+++ /dev/null
---- a/drivers/ata/Kconfig
-+++ b/drivers/ata/Kconfig
-@@ -568,6 +568,14 @@ config SATA_VITESSE
-
- If unsure, say N.
-
-+config SATA_OXNAS
-+ tristate "PLXTECH NAS782X SATA support"
-+ select SATA_HOST
-+ help
-+ This option enables support for Nas782x Serial ATA controller.
-+
-+ If unsure, say N.
-+
- comment "PATA SFF controllers with BMDMA"
-
- config PATA_ALI
---- a/drivers/ata/Makefile
-+++ b/drivers/ata/Makefile
-@@ -46,6 +46,7 @@ obj-$(CONFIG_SATA_SVW) += sata_svw.o
- obj-$(CONFIG_SATA_ULI) += sata_uli.o
- obj-$(CONFIG_SATA_VIA) += sata_via.o
- obj-$(CONFIG_SATA_VITESSE) += sata_vsc.o
-+obj-$(CONFIG_SATA_OXNAS) += sata_oxnas.o
-
- # SFF PATA w/ BMDMA
- obj-$(CONFIG_PATA_ALI) += pata_ali.o
---- a/arch/arm/boot/dts/ox820.dtsi
-+++ b/arch/arm/boot/dts/ox820.dtsi
-@@ -399,5 +399,20 @@
- plxtech,pcie-outbound-offset = <0x174>;
- status = "disabled";
- };
-+
-+ sata: sata@45900000 {
-+ compatible = "plxtech,nas782x-sata";
-+ /* ports dmactl sgdma */
-+ reg = <0x45900000 0x20000>, <0x459A0000 0x40>, <0x459B0000 0x20>,
-+ /* core phy descriptors (optional) */
-+ <0x459E0000 0x2000>, <0x44900000 0x0C>, <0x50000000 0x1000>;
-+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&stdclk CLK_820_SATA>;
-+ resets = <&reset RESET_SATA>, <&reset RESET_SATA_LINK>, <&reset RESET_SATA_PHY>;
-+ reset-names = "sata", "link", "phy";
-+ nr-ports = <1>;
-+ status = "disabled";
-+ };
-+
- };
- };
---- a/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts
-+++ b/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts
-@@ -111,3 +111,7 @@
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_etha_mdio>;
- };
-+
-+&sata {
-+ status = "okay";
-+};
+++ /dev/null
---- a/arch/arm/mach-oxnas/Kconfig
-+++ b/arch/arm/mach-oxnas/Kconfig
-@@ -2,6 +2,7 @@
- menuconfig ARCH_OXNAS
- bool "Oxford Semiconductor OXNAS Family SoCs"
- select ARCH_HAS_RESET_CONTROLLER
-+ select ARCH_WANT_LIBATA_LEDS
- select COMMON_CLK_OXNAS
- select GPIOLIB
- select MFD_SYSCON
+++ /dev/null
---- a/drivers/usb/host/Kconfig
-+++ b/drivers/usb/host/Kconfig
-@@ -339,6 +339,13 @@ config USB_OCTEON_EHCI
- USB 2.0 device support. All CN6XXX based chips with USB are
- supported.
-
-+config USB_EHCI_OXNAS
-+ tristate "OXNAS EHCI Module"
-+ depends on USB_EHCI_HCD && ARCH_OXNAS
-+ select USB_EHCI_ROOT_HUB_TT
-+ help
-+ Enable support for the OX820 SOC's on-chip EHCI controller.
-+
- endif # USB_EHCI_HCD
-
- config USB_OXU210HP_HCD
---- a/drivers/usb/host/Makefile
-+++ b/drivers/usb/host/Makefile
-@@ -46,6 +46,7 @@ obj-$(CONFIG_USB_EHCI_HCD_STI) += ehci-s
- obj-$(CONFIG_USB_EHCI_EXYNOS) += ehci-exynos.o
- obj-$(CONFIG_USB_EHCI_HCD_AT91) += ehci-atmel.o
- obj-$(CONFIG_USB_EHCI_BRCMSTB) += ehci-brcm.o
-+obj-$(CONFIG_USB_EHCI_OXNAS) += ehci-oxnas.o
-
- obj-$(CONFIG_USB_OXU210HP_HCD) += oxu210hp-hcd.o
- obj-$(CONFIG_USB_ISP116X_HCD) += isp116x-hcd.o
---- a/arch/arm/boot/dts/ox820.dtsi
-+++ b/arch/arm/boot/dts/ox820.dtsi
-@@ -106,6 +106,31 @@
- status = "disabled";
- };
-
-+ ehci: ehci@40200100 {
-+ compatible = "plxtech,nas782x-ehci";
-+ reg = <0x40200100 0xf00>;
-+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&stdclk CLK_820_USBMPH>, <&pllb>, <&stdclk CLK_820_REF600>;
-+ clock-names = "usb", "refsrc", "phyref";
-+ resets = <&reset RESET_USBHS>, <&reset RESET_USBPHYA>, <&reset RESET_USBPHYB>;
-+ reset-names = "host", "phya", "phyb";
-+ oxsemi,sys-ctrl = <&sys>;
-+ /* Otherwise ref300 is used, which is derived from sata phy
-+ * in that case, usb depends on sata initialization */
-+ /* FIXME: how to make this dependency explicit ? */
-+ oxsemi,ehci_use_pllb;
-+ status = "disabled";
-+
-+ ehci_port1: port@1 {
-+ reg = <1>;
-+ #trigger-source-cells = <0>;
-+ };
-+ ehci_port2: port@2 {
-+ reg = <2>;
-+ #trigger-source-cells = <0>;
-+ };
-+ };
-+
- apb-bridge@44000000 {
- #address-cells = <1>;
- #size-cells = <1>;
---- a/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts
-+++ b/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts
-@@ -105,6 +105,10 @@
- };
- };
-
-+&ehci {
-+ status = "okay";
-+};
-+
- ða {
- status = "okay";
-
+++ /dev/null
-From 71270226b14733a4b1f2cde58ea9265caa50b38d Mon Sep 17 00:00:00 2001
-From: Adrian Panella <ianchi74@outlook.com>
-Date: Thu, 9 Mar 2017 09:37:17 +0100
-Subject: [PATCH 67/69] generic: Mangle bootloader's kernel arguments
-
-The command-line arguments provided by the boot loader will be
-appended to a new device tree property: bootloader-args.
-If there is a property "append-rootblock" in DT under /chosen
-and a root= option in bootloaders command line it will be parsed
-and added to DT bootargs with the form: <append-rootblock>XX.
-Only command line ATAG will be processed, the rest of the ATAGs
-sent by bootloader will be ignored.
-This is usefull in dual boot systems, to get the current root partition
-without afecting the rest of the system.
-
-Signed-off-by: Adrian Panella <ianchi74@outlook.com>
----
- arch/arm/Kconfig | 11 +++++
- arch/arm/boot/compressed/atags_to_fdt.c | 72 ++++++++++++++++++++++++++++++++-
- init/main.c | 16 ++++++++
- 3 files changed, 98 insertions(+), 1 deletion(-)
-
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -1728,6 +1728,17 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
- The command-line arguments provided by the boot loader will be
- appended to the the device tree bootargs property.
-
-+config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
-+ bool "Append rootblock parsing bootloader's kernel arguments"
-+ help
-+ The command-line arguments provided by the boot loader will be
-+ appended to a new device tree property: bootloader-args.
-+ If there is a property "append-rootblock" in DT under /chosen
-+ and a root= option in bootloaders command line it will be parsed
-+ and added to DT bootargs with the form: <append-rootblock>XX.
-+ Only command line ATAG will be processed, the rest of the ATAGs
-+ sent by bootloader will be ignored.
-+
- endchoice
-
- config CMDLINE
---- a/arch/arm/boot/compressed/atags_to_fdt.c
-+++ b/arch/arm/boot/compressed/atags_to_fdt.c
-@@ -5,6 +5,8 @@
-
- #if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND)
- #define do_extend_cmdline 1
-+#elif defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
-+#define do_extend_cmdline 1
- #else
- #define do_extend_cmdline 0
- #endif
-@@ -20,6 +22,7 @@ static int node_offset(void *fdt, const
- return offset;
- }
-
-+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
- static int setprop(void *fdt, const char *node_path, const char *property,
- void *val_array, int size)
- {
-@@ -28,6 +31,7 @@ static int setprop(void *fdt, const char
- return offset;
- return fdt_setprop(fdt, offset, property, val_array, size);
- }
-+#endif
-
- static int setprop_string(void *fdt, const char *node_path,
- const char *property, const char *string)
-@@ -38,6 +42,7 @@ static int setprop_string(void *fdt, con
- return fdt_setprop_string(fdt, offset, property, string);
- }
-
-+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
- static int setprop_cell(void *fdt, const char *node_path,
- const char *property, uint32_t val)
- {
-@@ -46,6 +51,7 @@ static int setprop_cell(void *fdt, const
- return offset;
- return fdt_setprop_cell(fdt, offset, property, val);
- }
-+#endif
-
- static const void *getprop(const void *fdt, const char *node_path,
- const char *property, int *len)
-@@ -58,6 +64,7 @@ static const void *getprop(const void *f
- return fdt_getprop(fdt, offset, property, len);
- }
-
-+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
- static uint32_t get_cell_size(const void *fdt)
- {
- int len;
-@@ -69,6 +76,61 @@ static uint32_t get_cell_size(const void
- return cell_size;
- }
-
-+#endif
-+
-+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
-+
-+static char *append_rootblock(char *dest, const char *str, int len, void *fdt)
-+{
-+ const char *ptr, *end;
-+ const char *root="root=";
-+ int i, l;
-+ const char *rootblock;
-+
-+ //ARM doesn't have __HAVE_ARCH_STRSTR, so search manually
-+ ptr = str - 1;
-+
-+ do {
-+ //first find an 'r' at the begining or after a space
-+ do {
-+ ptr++;
-+ ptr = strchr(ptr, 'r');
-+ if(!ptr) return dest;
-+
-+ } while (ptr != str && *(ptr-1) != ' ');
-+
-+ //then check for the rest
-+ for(i = 1; i <= 4; i++)
-+ if(*(ptr+i) != *(root+i)) break;
-+
-+ } while (i != 5);
-+
-+ end = strchr(ptr, ' ');
-+ end = end ? (end - 1) : (strchr(ptr, 0) - 1);
-+
-+ //find partition number (assumes format root=/dev/mtdXX | /dev/mtdblockXX | yy:XX )
-+ for( i = 0; end >= ptr && *end >= '0' && *end <= '9'; end--, i++);
-+ ptr = end + 1;
-+
-+ /* if append-rootblock property is set use it to append to command line */
-+ rootblock = getprop(fdt, "/chosen", "append-rootblock", &l);
-+ if(rootblock != NULL) {
-+ if(*dest != ' ') {
-+ *dest = ' ';
-+ dest++;
-+ len++;
-+ }
-+ if (len + l + i <= COMMAND_LINE_SIZE) {
-+ memcpy(dest, rootblock, l);
-+ dest += l - 1;
-+ memcpy(dest, ptr, i);
-+ dest += i;
-+ }
-+ }
-+ return dest;
-+}
-+#endif
-+
- static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline)
- {
- char cmdline[COMMAND_LINE_SIZE];
-@@ -88,18 +150,28 @@ static void merge_fdt_bootargs(void *fdt
-
- /* and append the ATAG_CMDLINE */
- if (fdt_cmdline) {
-+
-+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
-+ //save original bootloader args
-+ //and append ubi.mtd with root partition number to current cmdline
-+ setprop_string(fdt, "/chosen", "bootloader-args", fdt_cmdline);
-+ ptr = append_rootblock(ptr, fdt_cmdline, len, fdt);
-+
-+#else
- len = strlen(fdt_cmdline);
- if (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) {
- *ptr++ = ' ';
- memcpy(ptr, fdt_cmdline, len);
- ptr += len;
- }
-+#endif
- }
- *ptr = '\0';
-
- setprop_string(fdt, "/chosen", "bootargs", cmdline);
- }
-
-+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
- static void hex_str(char *out, uint32_t value)
- {
- uint32_t digit;
-@@ -117,6 +189,7 @@ static void hex_str(char *out, uint32_t
- }
- *out = '\0';
- }
-+#endif
-
- /*
- * Convert and fold provided ATAGs into the provided FDT.
-@@ -131,9 +204,11 @@ int atags_to_fdt(void *atag_list, void *
- struct tag *atag = atag_list;
- /* In the case of 64 bits memory size, need to reserve 2 cells for
- * address and size for each bank */
-+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
- __be32 mem_reg_property[2 * 2 * NR_BANKS];
-- int memcount = 0;
-- int ret, memsize;
-+ int memsize, memcount = 0;
-+#endif
-+ int ret;
-
- /* make sure we've got an aligned pointer */
- if ((u32)atag_list & 0x3)
-@@ -168,7 +243,9 @@ int atags_to_fdt(void *atag_list, void *
- else
- setprop_string(fdt, "/chosen", "bootargs",
- atag->u.cmdline.cmdline);
-- } else if (atag->hdr.tag == ATAG_MEM) {
-+ }
-+#ifndef CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
-+ else if (atag->hdr.tag == ATAG_MEM) {
- if (memcount >= sizeof(mem_reg_property)/4)
- continue;
- if (!atag->u.mem.size)
-@@ -212,6 +289,10 @@ int atags_to_fdt(void *atag_list, void *
- setprop(fdt, "/memory", "reg", mem_reg_property,
- 4 * memcount * memsize);
- }
-+#else
-+
-+ }
-+#endif
-
- return fdt_pack(fdt);
- }
---- a/init/main.c
-+++ b/init/main.c
-@@ -113,6 +113,10 @@
-
- #include <kunit/test.h>
-
-+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
-+#include <linux/of.h>
-+#endif
-+
- static int kernel_init(void *);
-
- extern void init_IRQ(void);
-@@ -993,6 +997,18 @@ asmlinkage __visible void __init __no_sa
- page_alloc_init();
-
- pr_notice("Kernel command line: %s\n", saved_command_line);
-+
-+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
-+ //Show bootloader's original command line for reference
-+ if(of_chosen) {
-+ const char *prop = of_get_property(of_chosen, "bootloader-args", NULL);
-+ if(prop)
-+ pr_notice("Bootloader command line (ignored): %s\n", prop);
-+ else
-+ pr_notice("Bootloader command line not present\n");
-+ }
-+#endif
-+
- /* parameters may set static keys */
- jump_label_init();
- parse_early_param();
+++ /dev/null
---- a/drivers/ata/libata-core.c
-+++ b/drivers/ata/libata-core.c
-@@ -1531,6 +1531,14 @@ unsigned ata_exec_internal_sg(struct ata
- return AC_ERR_SYSTEM;
- }
-
-+ if (ap->ops->acquire_hw && !ap->ops->acquire_hw(ap, 0, 0)) {
-+ spin_unlock_irqrestore(ap->lock, flags);
-+ if (!ap->ops->acquire_hw(ap, 1, (2*HZ))) {
-+ return AC_ERR_TIMEOUT;
-+ }
-+ spin_lock_irqsave(ap->lock, flags);
-+ }
-+
- /* initialize internal qc */
- qc = __ata_qc_from_tag(ap, ATA_TAG_INTERNAL);
-
-@@ -4587,6 +4595,9 @@ struct ata_queued_cmd *ata_qc_new_init(s
- if (unlikely(ap->pflags & ATA_PFLAG_FROZEN))
- return NULL;
-
-+ if (ap->ops->qc_new && ap->ops->qc_new(ap))
-+ return NULL;
-+
- /* libsas case */
- if (ap->flags & ATA_FLAG_SAS_HOST) {
- tag = ata_sas_allocate_tag(ap);
-@@ -4632,6 +4643,8 @@ void ata_qc_free(struct ata_queued_cmd *
- qc->tag = ATA_TAG_POISON;
- if (ap->flags & ATA_FLAG_SAS_HOST)
- ata_sas_free_tag(tag, ap);
-+ if (ap->ops->qc_free)
-+ ap->ops->qc_free(qc);
- }
- }
-
---- a/include/linux/libata.h
-+++ b/include/linux/libata.h
-@@ -927,6 +927,8 @@ struct ata_port_operations {
- enum ata_completion_errors (*qc_prep)(struct ata_queued_cmd *qc);
- unsigned int (*qc_issue)(struct ata_queued_cmd *qc);
- bool (*qc_fill_rtf)(struct ata_queued_cmd *qc);
-+ int (*qc_new)(struct ata_port *ap);
-+ void (*qc_free)(struct ata_queued_cmd *qc);
-
- /*
- * Configuration and exception handling
-@@ -1017,6 +1019,9 @@ struct ata_port_operations {
- void (*phy_reset)(struct ata_port *ap);
- void (*eng_timeout)(struct ata_port *ap);
-
-+ int (*acquire_hw)(struct ata_port *ap, int may_sleep,
-+ int timeout_jiffies);
-+
- /*
- * ->inherits must be the last field and all the preceding
- * fields must be pointers.
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
-@@ -2942,12 +2942,20 @@ static void spi_nor_set_mtd_info(struct
+@@ -2964,12 +2964,20 @@ static void spi_nor_set_mtd_info(struct
{
struct mtd_info *mtd = &nor->mtd;
struct device *dev = nor->dev;
};
partition@480000 {
+ compatible = "u-boot,env";
label = "0:appsblenv";
reg = <0x480000 0x10000>;
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/dts-v1/;
+
+#include "ipq8074.dtsi"
+#include "ipq8074-hk-cpu.dtsi"
+#include "ipq8074-ess.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "Spectrum SAX1V1K";
+ compatible = "spectrum,sax1v1k", "qcom,ipq8074";
+
+ aliases {
+ led-boot = &led_system_red;
+ led-failsafe = &led_system_red;
+ led-running = &led_system_blue;
+ led-upgrade = &led_system_red;
+ serial0 = &blsp1_uart5;
+ /* Aliases as required by u-boot to patch MAC addresses */
+ ethernet0 = &dp6_syn;
+ ethernet1 = &dp4;
+ ethernet2 = &dp3;
+ ethernet3 = &dp2;
+ label-mac-device = &dp6_syn;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ gpios = <&tlmm 34 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+
+ wps {
+ label = "wps";
+ gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WPS_BUTTON>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_system_blue: system-blue {
+ gpios = <&tlmm 26 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_STATUS;
+ };
+
+ led_system_red: system-red {
+ gpios = <&tlmm 25 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_STATUS;
+ };
+ };
+};
+
+&tlmm {
+ mdio_pins: mdio-pins {
+ mdc {
+ pins = "gpio68";
+ function = "mdc";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ mdio {
+ pins = "gpio69";
+ function = "mdio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+};
+
+&blsp1_uart5 {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&cryptobam {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
+&qpic_bam {
+ status = "okay";
+};
+
+&mdio {
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ ethernet-phy-package@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "qcom,qca8075-package";
+ reg = <0>;
+
+ qcom,package-mode = "qsgmii";
+
+ qca8075_1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+
+ qca8075_2: ethernet-phy@2 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <2>;
+ };
+
+ qca8075_3: ethernet-phy@3 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <3>;
+ };
+ };
+
+ qca8081: ethernet-phy@28 {
+ compatible = "ethernet-phy-id004d.d101";
+ reg = <28>;
+ reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&sdhc_1 {
+ /* Following same rule as QNAP 301W
+ * the emmc has a problem with the hs400 > hs200 speed switch.
+ * Therefore remove the mmc-hs400-1_8v property
+ */
+ /delete-property/ mmc-hs400-1_8v;
+ mmc-hs200-1_8v;
+ mmc-ddr-1_8v;
+ vqmmc-supply = <&l11>;
+ status = "okay";
+};
+
+&switch {
+ switch_lan_bmp = <(ESS_PORT2 | ESS_PORT3 | ESS_PORT4)>; /* lan port bitmap */
+ switch_wan_bmp = <ESS_PORT6>; /* wan port bitmap */
+ switch_mac_mode = <MAC_MODE_QSGMII>; /* mac mode for uniphy instance0*/
+ switch_mac_mode2 = <MAC_MODE_SGMII_PLUS>; /* mac mode for uniphy instance2*/
+ status = "okay";
+
+ qcom,port_phyinfo {
+ port@2 {
+ port_id = <2>;
+ phy_address = <1>;
+ };
+
+ port@3 {
+ port_id = <3>;
+ phy_address = <2>;
+ };
+
+ port@4 {
+ port_id = <4>;
+ phy_address = <3>;
+ };
+
+ port@6 {
+ port_id = <6>;
+ phy_address = <28>;
+ port_mac_sel = "QGMAC_PORT";
+ };
+ };
+};
+
+&edma {
+ status = "okay";
+};
+
+&dp2 {
+ phy-mode = "qsgmii";
+ phy-handle = <&qca8075_1>;
+ label = "lan3";
+ status = "okay";
+};
+
+&dp3 {
+ phy-mode = "qsgmii";
+ phy-handle = <&qca8075_2>;
+ label = "lan2";
+ status = "okay";
+};
+
+&dp4 {
+ phy-mode = "qsgmii";
+ phy-handle = <&qca8075_3>;
+ label = "lan1";
+ status = "okay";
+};
+
+&dp6_syn {
+ phy-handle = <&qca8081>;
+ label = "wan";
+ status = "okay";
+};
+
+&wifi {
+ qcom,ath11k-calibration-variant = "Spectrum-SAX1V1K";
+ status = "okay";
+};
endef
TARGET_DEVICES += redmi_ax6
+define Device/spectrum_sax1v1k
+ $(call Device/FitImage)
+ $(call Device/EmmcImage)
+ DEVICE_VENDOR := Spectrum
+ DEVICE_MODEL := SAX1V1K
+ DEVICE_DTS_CONFIG := config@rt5010w-d187-rev6
+ SOC := ipq8072
+ IMAGES := sysupgrade.bin
+ DEVICE_PACKAGES := ipq-wifi-spectrum_sax1v1k
+endef
+TARGET_DEVICES += spectrum_sax1v1k
+
define Device/xiaomi_ax3600
$(call Device/FitImage)
$(call Device/UbiFit)
START=99
-. /lib/functions.sh
-
boot() {
case $(board_name) in
- yuncore,fap650)
- fw_setenv owrt_bootcount 0
- ;;
- esac
+ yuncore,fap650)
+ fw_setenv owrt_bootcount 0
+ ;;
+ esac
}
linksys,mx4200v2|\
prpl,haze|\
redmi,ax6|\
+ spectrum,sax1v1k|\
xiaomi,ax3600)
ucidef_set_interfaces_lan_wan "lan1 lan2 lan3" "wan"
;;
local label_mac=""
case "$board" in
- linksys,mx4200v1|\
linksys,mx4200v2)
label_mac=$(mtd_get_mac_ascii devinfo hw_mac_addr)
for i in $(seq 3 5); do
dynalink,dl-wrx36|\
edgecore,eap102|\
edimax,cax1800|\
- linksys,mx4200v1|\
- linksys,mx4200v2|\
linksys,mx5300|\
- netgear,rax120v2|\
netgear,wax218|\
netgear,wax620|\
netgear,wax630|\
xiaomi,ax9000|\
yuncore,ax880|\
zbtlink,zbt-z800ax|\
- zte,mf269|\
- zyxel,nbg7815)
+ zte,mf269)
caldata_extract "0:art" 0x1000 0x20000
;;
- prpl,haze)
+ linksys,mx4200v1)
+ caldata_extract "0:art" 0x1000 0x20000
+ ath11k_remove_regdomain
+ ;;
+ linksys,mx4200v2)
+ caldata_extract "0:art" 0x1000 0x20000
+ label_mac=$(mtd_get_mac_ascii devinfo hw_mac_addr)
+ ath11k_patch_mac $(macaddr_add $label_mac 2) 0
+ ath11k_patch_mac $(macaddr_add $label_mac 1) 1
+ ath11k_patch_mac $(macaddr_add $label_mac 3) 2
+ ath11k_remove_regdomain
+ ath11k_set_macflag
+ ;;
+ netgear,rax120v2)
+ caldata_extract "0:art" 0x1000 0x20000
+ ath11k_patch_mac $(mtd_get_mac_binary boarddata1 0xc) 0
+ ath11k_patch_mac $(mtd_get_mac_binary boarddata1 0x0) 1
+ ath11k_patch_mac $(mtd_get_mac_binary boarddata1 0x6) 2
+ ath11k_set_macflag
+ ;;
+ prpl,haze|\
+ spectrum,sax1v1k)
caldata_extract_mmc "0:ART" 0x1000 0x20000
;;
+ zyxel,nbg7815)
+ caldata_extract "0:art" 0x1000 0x20000
+ label_mac=$(get_mac_label)
+ ath11k_patch_mac $(macaddr_add $label_mac 3) 0
+ ath11k_patch_mac $(macaddr_add $label_mac 2) 1
+ ath11k_patch_mac $(macaddr_add $label_mac 4) 2
+ ath11k_set_macflag
+ ;;
esac
;;
"ath11k/QCN9074/hw1.0/cal-pci-0000:01:00.0.bin"|\
[ "$PHYNBR" = "0" ] && macaddr_add $(get_mac_label) 2 > /sys${DEVPATH}/macaddress
[ "$PHYNBR" = "1" ] && macaddr_add $(get_mac_label) 3 > /sys${DEVPATH}/macaddress
;;
- linksys,mx4200v1|\
- linksys,mx4200v2)
- label_mac=$(mtd_get_mac_ascii devinfo hw_mac_addr)
- [ "$PHYNBR" = "0" ] && macaddr_add $label_mac 2 > /sys${DEVPATH}/macaddress
- [ "$PHYNBR" = "1" ] && macaddr_add $label_mac 1 > /sys${DEVPATH}/macaddress
- [ "$PHYNBR" = "2" ] && macaddr_add $label_mac 3 > /sys${DEVPATH}/macaddress
- ;;
zbtlink,zbt-z800ax)
[ "$PHYNBR" = "0" ] && macaddr_add $(get_mac_label) -1 > /sys${DEVPATH}/macaddress
[ "$PHYNBR" = "1" ] && macaddr_add $(get_mac_label) -2 > /sys${DEVPATH}/macaddress
nand_do_upgrade "$1"
;;
prpl,haze|\
- qnap,301w)
+ qnap,301w|\
+ spectrum,sax1v1k)
kernelname="0:HLOS"
rootfsname="rootfs"
mmc_do_upgrade "$1"
--- a/drivers/tty/serial/serial_core.c
+++ b/drivers/tty/serial/serial_core.c
-@@ -467,6 +467,9 @@ uart_get_baud_rate(struct uart_port *por
+@@ -480,6 +480,9 @@ uart_get_baud_rate(struct uart_port *por
break;
}
KERNELNAME:=Image dtbs
SUBTARGETS:=generic
-KERNEL_PATCHVER:=6.1
+KERNEL_PATCHVER:=6.6
include $(INCLUDE_DIR)/target.mk
+++ /dev/null
-CONFIG_64BIT=y
-CONFIG_ARCH_CLOCKSOURCE_INIT=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_MMAP_RND_BITS=18
-CONFIG_ARCH_MMAP_RND_BITS_MAX=24
-CONFIG_ARCH_MMAP_RND_BITS_MIN=18
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_RV64I=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_STACKWALK=y
-CONFIG_ARCH_WANTS_THP_SWAP=y
-CONFIG_ASN1=y
-CONFIG_ASSOCIATIVE_ARRAY=y
-CONFIG_ATA=y
-CONFIG_ATA_VERBOSE_ERROR=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_CAVIUM_PTP=y
-CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_CC_NO_ARRAY_BOUNDS=y
-CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC=y
-CONFIG_CLK_SIFIVE=y
-CONFIG_CLK_SIFIVE_PRCI=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CLZ_TAB=y
-CONFIG_CMODEL_MEDANY=y
-# CONFIG_CMODEL_MEDLOW is not set
-CONFIG_COMMON_CLK=y
-CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
-# CONFIG_COMPAT_32BIT_TIME is not set
-CONFIG_COMPAT_BRK=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_CONTEXT_TRACKING=y
-CONFIG_CONTEXT_TRACKING_IDLE=y
-CONFIG_COREDUMP=y
-CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
-CONFIG_CPU_ISOLATION=y
-CONFIG_CPU_RMAP=y
-CONFIG_CRC16=y
-# CONFIG_CRC32_SARWATE is not set
-CONFIG_CRC32_SLICEBY8=y
-CONFIG_CRC7=y
-CONFIG_CRC_ITU_T=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_DRBG=y
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_MENU=y
-CONFIG_CRYPTO_ECHAINIV=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_JITTERENTROPY=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1
-CONFIG_CRYPTO_LIB_SHA1=y
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_LIB_UTILS=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_RNG_DEFAULT=y
-CONFIG_CRYPTO_RSA=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_DMA_DIRECT_REMAP=y
-CONFIG_DNOTIFY=y
-CONFIG_DTC=y
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_EDAC=y
-# CONFIG_EDAC_DEBUG is not set
-CONFIG_EDAC_LEGACY_SYSFS=y
-CONFIG_EDAC_SIFIVE=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EFI=y
-CONFIG_EFIVAR_FS=m
-# CONFIG_EFI_BOOTLOADER_CONTROL is not set
-# CONFIG_EFI_CAPSULE_LOADER is not set
-# CONFIG_EFI_COCO_SECRET is not set
-# CONFIG_EFI_DISABLE_PCI_DMA is not set
-# CONFIG_EFI_DISABLE_RUNTIME is not set
-CONFIG_EFI_EARLYCON=y
-CONFIG_EFI_ESRT=y
-CONFIG_EFI_GENERIC_STUB=y
-CONFIG_EFI_PARAMS_FROM_FDT=y
-CONFIG_EFI_RUNTIME_WRAPPERS=y
-CONFIG_EFI_STUB=y
-# CONFIG_EFI_TEST is not set
-# CONFIG_EFI_ZBOOT is not set
-CONFIG_ELF_CORE=y
-CONFIG_ERRATA_SIFIVE=y
-CONFIG_ERRATA_SIFIVE_CIP_1200=y
-CONFIG_ERRATA_SIFIVE_CIP_453=y
-# CONFIG_ERRATA_THEAD is not set
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-CONFIG_EXT4_FS=y
-CONFIG_FAILOVER=y
-CONFIG_FAT_FS=y
-CONFIG_FHANDLE=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FONT_8x16=y
-CONFIG_FONT_AUTOSELECT=y
-CONFIG_FONT_SUPPORT=y
-CONFIG_FPU=y
-CONFIG_FRAME_POINTER=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CSUM=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IOREMAP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_INJECTION=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GLOB=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_CDEV_V1=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_SIFIVE=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HID=y
-CONFIG_HID_GENERIC=y
-CONFIG_HOTPLUG_PCI=y
-# CONFIG_HOTPLUG_PCI_CPCI is not set
-CONFIG_HOTPLUG_PCI_PCIE=y
-CONFIG_HOTPLUG_PCI_SHPC=y
-CONFIG_HVC_DRIVER=y
-CONFIG_HVC_RISCV_SBI=y
-CONFIG_HW_CONSOLE=y
-CONFIG_HZ_PERIODIC=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_COMPAT=y
-CONFIG_I2C_HELPER_AUTO=y
-CONFIG_I2C_OCORES=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-# CONFIG_IOMMU_DEBUGFS is not set
-CONFIG_IOMMU_SUPPORT=y
-CONFIG_IO_URING=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD2=y
-CONFIG_KALLSYMS=y
-CONFIG_KEYS=y
-CONFIG_LEDS_PWM=y
-CONFIG_LEDS_TRIGGER_DISK=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-CONFIG_LIBFDT=y
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_MACB=y
-# CONFIG_MACB_PCI is not set
-CONFIG_MACB_USE_HWSTAMP=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MICROSEMI_PHY=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_CADENCE=y
-# CONFIG_MMC_SDHCI_PCI is not set
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MMC_SPI=y
-CONFIG_MMIOWB=y
-CONFIG_MODULES_USE_ELF_RELA=y
-CONFIG_MODULE_SECTIONS=y
-CONFIG_MPILIB=y
-CONFIG_MQ_IOSCHED_DEADLINE=y
-CONFIG_MQ_IOSCHED_KYBER=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NET_FAILOVER=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NLS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_NONPORTABLE is not set
-CONFIG_NR_CPUS=8
-CONFIG_NVMEM=y
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_DMA_DEFAULT_COHERENT=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OID_REGISTRY=y
-CONFIG_PADATA=y
-CONFIG_PAGE_OFFSET=0xff60000000000000
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_REPORTING=y
-CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEAER_INJECT=m
-CONFIG_PCIEASPM=y
-CONFIG_PCIEASPM_DEFAULT=y
-# CONFIG_PCIEASPM_PERFORMANCE is not set
-# CONFIG_PCIEASPM_POWERSAVE is not set
-# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_DPC=y
-CONFIG_PCIE_DW=y
-CONFIG_PCIE_DW_HOST=y
-CONFIG_PCIE_ECRC=y
-CONFIG_PCIE_FU740=y
-CONFIG_PCIE_PTM=y
-CONFIG_PCIE_XILINX=y
-CONFIG_PCI_DEBUG=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_ECAM=y
-CONFIG_PCI_HOST_COMMON=y
-CONFIG_PCI_HOST_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PCI_SW_SWITCHTEC=y
-CONFIG_PGTABLE_LEVELS=5
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_PORTABLE=y
-CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_GPIO=y
-CONFIG_POWER_RESET_GPIO_RESTART=y
-CONFIG_POWER_RESET_RESTART=y
-CONFIG_POWER_RESET_SYSCON=y
-CONFIG_POWER_RESET_SYSCON_POWEROFF=y
-CONFIG_PPS=y
-CONFIG_PREEMPT_NONE_BUILD=y
-CONFIG_PRINTK_TIME=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
-CONFIG_PWM_SIFIVE=y
-CONFIG_PWM_SYSFS=y
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_RANDSTRUCT_NONE=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-CONFIG_RCU_TRACE=y
-CONFIG_RD_GZIP=y
-CONFIG_REALTEK_PHY=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-# CONFIG_RESET_ATTACK_MITIGATION is not set
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RESET_SIMPLE=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RISCV=y
-CONFIG_RISCV_ALTERNATIVE=y
-# CONFIG_RISCV_BOOT_SPINWAIT is not set
-CONFIG_RISCV_DMA_NONCOHERENT=y
-CONFIG_RISCV_INTC=y
-CONFIG_RISCV_ISA_C=y
-CONFIG_RISCV_ISA_SVPBMT=y
-CONFIG_RISCV_ISA_ZICBOM=y
-CONFIG_RISCV_SBI=y
-CONFIG_RISCV_SBI_V01=y
-CONFIG_RISCV_TIMER=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-# CONFIG_RTC_DRV_EFI is not set
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_SCHED_DEBUG=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
-CONFIG_SERIAL_8250_EXAR=y
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_PCI=y
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIAL_SIFIVE=y
-CONFIG_SERIAL_SIFIVE_CONSOLE=y
-CONFIG_SERIO=y
-CONFIG_SERIO_SERPORT=y
-CONFIG_SG_POOL=y
-CONFIG_SIFIVE_CCACHE=y
-CONFIG_SIFIVE_PLIC=y
-CONFIG_SMP=y
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-# CONFIG_SOC_MICROCHIP_POLARFIRE is not set
-CONFIG_SOC_SIFIVE=y
-# CONFIG_SOC_STARFIVE is not set
-# CONFIG_SOC_VIRT is not set
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_BITBANG=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_SIFIVE=y
-CONFIG_SRCU=y
-CONFIG_STACKTRACE=y
-CONFIG_SWIOTLB=y
-CONFIG_SWPHY=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-# CONFIG_SYSFB_SIMPLEFB is not set
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TOOLCHAIN_HAS_ZICBOM=y
-CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE=y
-CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI=y
-CONFIG_TRACE_CLOCK=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_TUNE_GENERIC=y
-CONFIG_UCS2_STRING=y
-CONFIG_UEVENT_HELPER_PATH=""
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_EHCI_HCD=y
-# CONFIG_USB_EHCI_HCD_PLATFORM is not set
-CONFIG_USB_EHCI_PCI=y
-CONFIG_USB_HID=y
-CONFIG_USB_NET_DRIVERS=y
-CONFIG_USB_PCI=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SUPPORT=y
-# CONFIG_USB_UHCI_HCD is not set
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_PCI=y
-# CONFIG_USB_XHCI_PLATFORM is not set
-CONFIG_VFAT_FS=y
-CONFIG_VGA_ARB=y
-CONFIG_VGA_ARB_MAX_GPUS=16
-CONFIG_VMAP_STACK=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XPS=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZONE_DMA32=y
--- /dev/null
+CONFIG_64BIT=y
+# CONFIG_ACPI is not set
+CONFIG_ARCH_CLOCKSOURCE_INIT=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_ARCH_MMAP_RND_BITS=18
+CONFIG_ARCH_MMAP_RND_BITS_MAX=24
+CONFIG_ARCH_MMAP_RND_BITS_MIN=18
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+CONFIG_ARCH_RV64I=y
+# CONFIG_ARCH_THEAD is not set
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_WANTS_THP_SWAP=y
+CONFIG_ASN1=y
+CONFIG_ASSOCIATIVE_ARRAY=y
+CONFIG_ATA=y
+CONFIG_ATA_VERBOSE_ERROR=y
+# CONFIG_AX45MP_L2_CACHE is not set
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_CAVIUM_PTP=y
+CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC=y
+CONFIG_CLK_SIFIVE=y
+CONFIG_CLK_SIFIVE_PRCI=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CLZ_TAB=y
+CONFIG_CMODEL_MEDANY=y
+# CONFIG_CMODEL_MEDLOW is not set
+CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+# CONFIG_COMPAT_32BIT_TIME is not set
+CONFIG_COMPAT_BRK=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_COREDUMP=y
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+CONFIG_CPU_ISOLATION=y
+CONFIG_CPU_RMAP=y
+CONFIG_CRC16=y
+# CONFIG_CRC32_SARWATE is not set
+CONFIG_CRC32_SLICEBY8=y
+CONFIG_CRC7=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_DRBG_HMAC=y
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_ECHAINIV=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_SHA256=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RNG_DEFAULT=y
+CONFIG_CRYPTO_RSA=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_DMA_DIRECT_REMAP=y
+CONFIG_DNOTIFY=y
+CONFIG_DTC=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_EDAC=y
+# CONFIG_EDAC_DEBUG is not set
+CONFIG_EDAC_LEGACY_SYSFS=y
+CONFIG_EDAC_SIFIVE=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EFI=y
+CONFIG_EFIVAR_FS=m
+# CONFIG_EFI_BOOTLOADER_CONTROL is not set
+# CONFIG_EFI_CAPSULE_LOADER is not set
+# CONFIG_EFI_COCO_SECRET is not set
+# CONFIG_EFI_DISABLE_PCI_DMA is not set
+# CONFIG_EFI_DISABLE_RUNTIME is not set
+CONFIG_EFI_EARLYCON=y
+CONFIG_EFI_ESRT=y
+CONFIG_EFI_GENERIC_STUB=y
+CONFIG_EFI_PARAMS_FROM_FDT=y
+CONFIG_EFI_RUNTIME_WRAPPERS=y
+CONFIG_EFI_STUB=y
+# CONFIG_EFI_TEST is not set
+# CONFIG_EFI_ZBOOT is not set
+CONFIG_ELF_CORE=y
+# CONFIG_ERRATA_ANDES is not set
+CONFIG_ERRATA_SIFIVE=y
+CONFIG_ERRATA_SIFIVE_CIP_1200=y
+CONFIG_ERRATA_SIFIVE_CIP_453=y
+# CONFIG_ERRATA_THEAD is not set
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_EXT4_FS=y
+CONFIG_FAILOVER=y
+CONFIG_FAT_FS=y
+CONFIG_FHANDLE=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FONT_8x16=y
+CONFIG_FONT_AUTOSELECT=y
+CONFIG_FONT_SUPPORT=y
+CONFIG_FPU=y
+CONFIG_FRAME_POINTER=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC11_NO_ARRAY_BOUNDS=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IOREMAP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_INJECTION=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GLOB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_CDEV_V1=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_SIFIVE=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HID=y
+CONFIG_HID_GENERIC=y
+CONFIG_HOTPLUG_PCI=y
+# CONFIG_HOTPLUG_PCI_CPCI is not set
+CONFIG_HOTPLUG_PCI_PCIE=y
+CONFIG_HOTPLUG_PCI_SHPC=y
+CONFIG_HVC_DRIVER=y
+CONFIG_HVC_RISCV_SBI=y
+CONFIG_HW_CONSOLE=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_OCORES=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INPUT=y
+# CONFIG_IOMMU_DEBUGFS is not set
+# CONFIG_IOMMUFD is not set
+CONFIG_IOMMU_SUPPORT=y
+CONFIG_IO_URING=y
+CONFIG_IRQ_STACKS=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+CONFIG_JBD2=y
+CONFIG_KALLSYMS=y
+CONFIG_KEYS=y
+CONFIG_LEDS_PWM=y
+CONFIG_LEDS_TRIGGER_DISK=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+CONFIG_LIBFDT=y
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_MACB=y
+# CONFIG_MACB_PCI is not set
+CONFIG_MACB_USE_HWSTAMP=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MEMFD_CREATE=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MICROSEMI_PHY=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_CADENCE=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SPI=y
+CONFIG_MMIOWB=y
+CONFIG_MODULES_USE_ELF_RELA=y
+CONFIG_MODULE_SECTIONS=y
+CONFIG_MPILIB=y
+CONFIG_MQ_IOSCHED_DEADLINE=y
+CONFIG_MQ_IOSCHED_KYBER=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NET_FAILOVER=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NLS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NONPORTABLE is not set
+CONFIG_NR_CPUS=8
+CONFIG_NVMEM=y
+CONFIG_NVMEM_SYSFS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_DMA_DEFAULT_COHERENT=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OID_REGISTRY=y
+CONFIG_PADATA=y
+CONFIG_PAGE_OFFSET=0xff60000000000000
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_REPORTING=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PCI=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEAER_INJECT=m
+CONFIG_PCIEASPM=y
+CONFIG_PCIEASPM_DEFAULT=y
+# CONFIG_PCIEASPM_PERFORMANCE is not set
+# CONFIG_PCIEASPM_POWERSAVE is not set
+# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_DPC=y
+CONFIG_PCIE_DW=y
+CONFIG_PCIE_DW_HOST=y
+CONFIG_PCIE_ECRC=y
+CONFIG_PCIE_FU740=y
+CONFIG_PCIE_PTM=y
+CONFIG_PCIE_XILINX=y
+CONFIG_PCI_DEBUG=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_ECAM=y
+CONFIG_PCI_HOST_COMMON=y
+CONFIG_PCI_HOST_GENERIC=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_MSI_IRQ_DOMAIN=y
+CONFIG_PCI_SW_SWITCHTEC=y
+CONFIG_PGTABLE_LEVELS=5
+CONFIG_PHYLIB=y
+CONFIG_PHYLINK=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_PORTABLE=y
+CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_GPIO=y
+CONFIG_POWER_RESET_GPIO_RESTART=y
+CONFIG_POWER_RESET_RESTART=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_POWER_RESET_SYSCON_POWEROFF=y
+CONFIG_PPS=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PRINTK_TIME=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_PWM=y
+CONFIG_PWM_SIFIVE=y
+CONFIG_PWM_SYSFS=y
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+CONFIG_RCU_TRACE=y
+CONFIG_RD_GZIP=y
+CONFIG_REALTEK_PHY=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+# CONFIG_RESET_ATTACK_MITIGATION is not set
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RESET_SIMPLE=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RISCV=y
+CONFIG_RISCV_ALTERNATIVE=y
+# CONFIG_RISCV_BOOT_SPINWAIT is not set
+CONFIG_RISCV_DMA_NONCOHERENT=y
+CONFIG_RISCV_INTC=y
+CONFIG_RISCV_ISA_C=y
+CONFIG_RISCV_ISA_FALLBACK=y
+CONFIG_RISCV_ISA_SVNAPOT=y
+CONFIG_RISCV_ISA_SVPBMT=y
+CONFIG_RISCV_ISA_V=y
+CONFIG_RISCV_ISA_V_DEFAULT_ENABLE=y
+CONFIG_RISCV_ISA_ZBB=y
+CONFIG_RISCV_ISA_ZICBOZ=y
+CONFIG_RISCV_ISA_ZICBOM=y
+CONFIG_RISCV_SBI=y
+CONFIG_RISCV_SBI_V01=y
+CONFIG_RISCV_TIMER=y
+CONFIG_RPS=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_DRV_EFI is not set
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_SCHED_DEBUG=y
+CONFIG_SCSI=y
+CONFIG_SCSI_COMMON=y
+CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
+CONFIG_SERIAL_8250_EXAR=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_SIFIVE=y
+CONFIG_SERIAL_SIFIVE_CONSOLE=y
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SG_POOL=y
+CONFIG_SIFIVE_CCACHE=y
+CONFIG_SIFIVE_PLIC=y
+CONFIG_SMP=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+# CONFIG_SOC_MICROCHIP_POLARFIRE is not set
+CONFIG_SOC_SIFIVE=y
+# CONFIG_SOC_STARFIVE is not set
+# CONFIG_SOC_VIRT is not set
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SPI_SIFIVE=y
+CONFIG_SRCU=y
+CONFIG_STACKTRACE=y
+CONFIG_SWIOTLB=y
+CONFIG_SWPHY=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+# CONFIG_SYSFB_SIMPLEFB is not set
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_THREAD_SIZE_ORDER=2
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TOOLCHAIN_HAS_ZICBOM=y
+CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE=y
+CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI=y
+CONFIG_TRACE_CLOCK=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_TUNE_GENERIC=y
+CONFIG_UCS2_STRING=y
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_HCD_PLATFORM is not set
+CONFIG_USB_EHCI_PCI=y
+CONFIG_USB_HID=y
+CONFIG_USB_NET_DRIVERS=y
+CONFIG_USB_PCI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_SUPPORT=y
+# CONFIG_USB_UHCI_HCD is not set
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PCI=y
+# CONFIG_USB_XHCI_PLATFORM is not set
+CONFIG_VFAT_FS=y
+CONFIG_VGA_ARB=y
+CONFIG_VGA_ARB_MAX_GPUS=16
+CONFIG_VMAP_STACK=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_WATCHDOG_CORE=y
+CONFIG_XPS=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZONE_DMA32=y
+++ /dev/null
-From ab5c8f5492cce16ff2104393e2f1fa64a3ff6e88 Mon Sep 17 00:00:00 2001
-From: David Abdurachmanov <david.abdurachmanov@sifive.com>
-Date: Wed, 17 Feb 2021 06:06:14 -0800
-Subject: [PATCH 1/7] riscv: sifive: fu740: cpu{1,2,3,4} set compatible to
- sifive,u74-mc
-
-Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
----
- arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
---- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
-+++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
-@@ -39,7 +39,7 @@
- };
- };
- cpu1: cpu@1 {
-- compatible = "sifive,bullet0", "riscv";
-+ compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
- d-cache-block-size = <64>;
- d-cache-sets = <64>;
- d-cache-size = <32768>;
-@@ -63,7 +63,7 @@
- };
- };
- cpu2: cpu@2 {
-- compatible = "sifive,bullet0", "riscv";
-+ compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
- d-cache-block-size = <64>;
- d-cache-sets = <64>;
- d-cache-size = <32768>;
-@@ -87,7 +87,7 @@
- };
- };
- cpu3: cpu@3 {
-- compatible = "sifive,bullet0", "riscv";
-+ compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
- d-cache-block-size = <64>;
- d-cache-sets = <64>;
- d-cache-size = <32768>;
-@@ -111,7 +111,7 @@
- };
- };
- cpu4: cpu@4 {
-- compatible = "sifive,bullet0", "riscv";
-+ compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
- d-cache-block-size = <64>;
- d-cache-sets = <64>;
- d-cache-size = <32768>;
+++ /dev/null
-From 14ede57943bc4209755d08daf93ac7be967d7fbe Mon Sep 17 00:00:00 2001
-From: David Abdurachmanov <david.abdurachmanov@sifive.com>
-Date: Mon, 13 Sep 2021 02:18:30 -0700
-Subject: [PATCH 4/7] riscv: sifive: unmatched: add gpio-poweroff node
-
-Add gpio-poweroff node to allow powering off the system.
-
-Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
----
- arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 6 ++++++
- 1 file changed, 6 insertions(+)
-
---- a/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
-+++ b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
-@@ -86,6 +86,11 @@
- };
- };
- };
-+
-+ gpio-poweroff {
-+ compatible = "gpio-poweroff";
-+ gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
-+ };
- };
-
- &uart0 {
+++ /dev/null
-From d3cf2859a056273400fbdf9d389b75750ff6ca5e Mon Sep 17 00:00:00 2001
-From: David Abdurachmanov <david.abdurachmanov@sifive.com>
-Date: Fri, 14 May 2021 05:27:51 -0700
-Subject: [PATCH 6/7] riscv: sifive: unleashed: define opp table (cpufreq)
-
-Source: https://github.com/sifive/riscv-linux/commits/dev/paulw/cpufreq-dt-aloe-v5.3-rc4
-
-Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
----
- arch/riscv/Kconfig | 8 +++++
- arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 5 ++++
- .../riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 34 ++++++++++++++++++++++
- 3 files changed, 47 insertions(+)
-
---- a/arch/riscv/Kconfig
-+++ b/arch/riscv/Kconfig
-@@ -711,6 +711,14 @@ config PORTABLE
- select OF
- select MMU
-
-+menu "CPU Power Management"
-+
-+source "drivers/cpuidle/Kconfig"
-+
-+source "drivers/cpufreq/Kconfig"
-+
-+endmenu
-+
- menu "Power management options"
-
- source "kernel/power/Kconfig"
---- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
-+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
-@@ -30,6 +30,7 @@
- i-cache-size = <16384>;
- reg = <0>;
- riscv,isa = "rv64imac";
-+ clocks = <&prci FU540_PRCI_CLK_COREPLL>;
- status = "disabled";
- cpu0_intc: interrupt-controller {
- #interrupt-cells = <1>;
-@@ -54,6 +55,7 @@
- reg = <1>;
- riscv,isa = "rv64imafdc";
- tlb-split;
-+ clocks = <&prci FU540_PRCI_CLK_COREPLL>;
- next-level-cache = <&l2cache>;
- cpu1_intc: interrupt-controller {
- #interrupt-cells = <1>;
-@@ -78,6 +80,7 @@
- reg = <2>;
- riscv,isa = "rv64imafdc";
- tlb-split;
-+ clocks = <&prci FU540_PRCI_CLK_COREPLL>;
- next-level-cache = <&l2cache>;
- cpu2_intc: interrupt-controller {
- #interrupt-cells = <1>;
-@@ -102,6 +105,7 @@
- reg = <3>;
- riscv,isa = "rv64imafdc";
- tlb-split;
-+ clocks = <&prci FU540_PRCI_CLK_COREPLL>;
- next-level-cache = <&l2cache>;
- cpu3_intc: interrupt-controller {
- #interrupt-cells = <1>;
-@@ -126,6 +130,7 @@
- reg = <4>;
- riscv,isa = "rv64imafdc";
- tlb-split;
-+ clocks = <&prci FU540_PRCI_CLK_COREPLL>;
- next-level-cache = <&l2cache>;
- cpu4_intc: interrupt-controller {
- #interrupt-cells = <1>;
---- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
-+++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
-@@ -80,6 +80,40 @@
- label = "d4";
- };
- };
-+
-+ fu540_c000_opp_table: opp-table {
-+ compatible = "operating-points-v2";
-+ opp-shared;
-+
-+ opp-350000000 {
-+ opp-hz = /bits/ 64 <350000000>;
-+ };
-+ opp-700000000 {
-+ opp-hz = /bits/ 64 <700000000>;
-+ };
-+ opp-999999999 {
-+ opp-hz = /bits/ 64 <999999999>;
-+ };
-+ opp-1400000000 {
-+ opp-hz = /bits/ 64 <1400000000>;
-+ };
-+ };
-+};
-+
-+&cpu0 {
-+ operating-points-v2 = <&fu540_c000_opp_table>;
-+};
-+&cpu1 {
-+ operating-points-v2 = <&fu540_c000_opp_table>;
-+};
-+&cpu2 {
-+ operating-points-v2 = <&fu540_c000_opp_table>;
-+};
-+&cpu3 {
-+ operating-points-v2 = <&fu540_c000_opp_table>;
-+};
-+&cpu4 {
-+ operating-points-v2 = <&fu540_c000_opp_table>;
- };
-
- &uart0 {
--- /dev/null
+From ab5c8f5492cce16ff2104393e2f1fa64a3ff6e88 Mon Sep 17 00:00:00 2001
+From: David Abdurachmanov <david.abdurachmanov@sifive.com>
+Date: Wed, 17 Feb 2021 06:06:14 -0800
+Subject: [PATCH 1/7] riscv: sifive: fu740: cpu{1,2,3,4} set compatible to
+ sifive,u74-mc
+
+Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
+---
+ arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+--- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
++++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
+@@ -39,7 +39,7 @@
+ };
+ };
+ cpu1: cpu@1 {
+- compatible = "sifive,bullet0", "riscv";
++ compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+@@ -63,7 +63,7 @@
+ };
+ };
+ cpu2: cpu@2 {
+- compatible = "sifive,bullet0", "riscv";
++ compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+@@ -87,7 +87,7 @@
+ };
+ };
+ cpu3: cpu@3 {
+- compatible = "sifive,bullet0", "riscv";
++ compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+@@ -111,7 +111,7 @@
+ };
+ };
+ cpu4: cpu@4 {
+- compatible = "sifive,bullet0", "riscv";
++ compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
--- /dev/null
+From 14ede57943bc4209755d08daf93ac7be967d7fbe Mon Sep 17 00:00:00 2001
+From: David Abdurachmanov <david.abdurachmanov@sifive.com>
+Date: Mon, 13 Sep 2021 02:18:30 -0700
+Subject: [PATCH 4/7] riscv: sifive: unmatched: add gpio-poweroff node
+
+Add gpio-poweroff node to allow powering off the system.
+
+Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
+---
+ arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
++++ b/arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dts
+@@ -86,6 +86,11 @@
+ };
+ };
+ };
++
++ gpio-poweroff {
++ compatible = "gpio-poweroff";
++ gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
++ };
+ };
+
+ &uart0 {
--- /dev/null
+From d3cf2859a056273400fbdf9d389b75750ff6ca5e Mon Sep 17 00:00:00 2001
+From: David Abdurachmanov <david.abdurachmanov@sifive.com>
+Date: Fri, 14 May 2021 05:27:51 -0700
+Subject: [PATCH 6/7] riscv: sifive: unleashed: define opp table (cpufreq)
+
+Source: https://github.com/sifive/riscv-linux/commits/dev/paulw/cpufreq-dt-aloe-v5.3-rc4
+
+Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
+---
+ arch/riscv/Kconfig | 8 +++++
+ arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 5 ++++
+ .../riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 34 ++++++++++++++++++++++
+ 3 files changed, 47 insertions(+)
+
+--- a/arch/riscv/Kconfig
++++ b/arch/riscv/Kconfig
+@@ -896,6 +896,14 @@ config PORTABLE
+ select MMU
+ select OF
+
++menu "CPU Power Management"
++
++source "drivers/cpuidle/Kconfig"
++
++source "drivers/cpufreq/Kconfig"
++
++endmenu
++
+ menu "Power management options"
+
+ source "kernel/power/Kconfig"
+--- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
++++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
+@@ -30,6 +30,7 @@
+ i-cache-size = <16384>;
+ reg = <0>;
+ riscv,isa = "rv64imac";
++ clocks = <&prci FU540_PRCI_CLK_COREPLL>;
+ status = "disabled";
+ cpu0_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+@@ -54,6 +55,7 @@
+ reg = <1>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
++ clocks = <&prci FU540_PRCI_CLK_COREPLL>;
+ next-level-cache = <&l2cache>;
+ cpu1_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+@@ -78,6 +80,7 @@
+ reg = <2>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
++ clocks = <&prci FU540_PRCI_CLK_COREPLL>;
+ next-level-cache = <&l2cache>;
+ cpu2_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+@@ -102,6 +105,7 @@
+ reg = <3>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
++ clocks = <&prci FU540_PRCI_CLK_COREPLL>;
+ next-level-cache = <&l2cache>;
+ cpu3_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+@@ -126,6 +130,7 @@
+ reg = <4>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
++ clocks = <&prci FU540_PRCI_CLK_COREPLL>;
+ next-level-cache = <&l2cache>;
+ cpu4_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+--- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
++++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
+@@ -80,6 +80,40 @@
+ label = "d4";
+ };
+ };
++
++ fu540_c000_opp_table: opp-table {
++ compatible = "operating-points-v2";
++ opp-shared;
++
++ opp-350000000 {
++ opp-hz = /bits/ 64 <350000000>;
++ };
++ opp-700000000 {
++ opp-hz = /bits/ 64 <700000000>;
++ };
++ opp-999999999 {
++ opp-hz = /bits/ 64 <999999999>;
++ };
++ opp-1400000000 {
++ opp-hz = /bits/ 64 <1400000000>;
++ };
++ };
++};
++
++&cpu0 {
++ operating-points-v2 = <&fu540_c000_opp_table>;
++};
++&cpu1 {
++ operating-points-v2 = <&fu540_c000_opp_table>;
++};
++&cpu2 {
++ operating-points-v2 = <&fu540_c000_opp_table>;
++};
++&cpu3 {
++ operating-points-v2 = <&fu540_c000_opp_table>;
++};
++&cpu4 {
++ operating-points-v2 = <&fu540_c000_opp_table>;
+ };
+
+ &uart0 {
ARCH:=arm
BOARD:=sunxi
BOARDNAME:=Allwinner ARM SoCs
-FEATURES:=fpu usb ext4 display rootfs-part rtc squashfs
+FEATURES:=usb ext4 display rootfs-part rtc squashfs
SUBTARGETS:=cortexa8 cortexa7 cortexa53
KERNEL_PATCHVER:=6.1
+KERNEL_TESTING_PATCHVER:=6.6
KERNELNAME:=zImage dtbs
--- /dev/null
+# CONFIG_AHCI_SUNXI is not set
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_ARCH_FORCE_MAX_ORDER=11
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MULTIPLATFORM=y
+CONFIG_ARCH_MULTI_V6_V7=y
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_ARCH_NR_GPIO=416
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_ARCH_SUNXI_MC_SMP=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARM=y
+CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=y
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
+CONFIG_ARM_CCI=y
+CONFIG_ARM_CCI400_COMMON=y
+CONFIG_ARM_CCI400_PORT_CTRL=y
+CONFIG_ARM_CPU_SUSPEND=y
+CONFIG_ARM_CRYPTO=y
+CONFIG_ARM_ERRATA_643719=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_HAS_SG_CHAIN=y
+CONFIG_ARM_HEAVY_MB=y
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+CONFIG_ARM_LPAE=y
+CONFIG_ARM_PATCH_IDIV=y
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_ARM_PSCI=y
+CONFIG_ARM_PSCI_FW=y
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_UNWIND=y
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_ATA=y
+CONFIG_ATAGS=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_AXP20X_POWER=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_PWM=y
+CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_PM=y
+CONFIG_BOUNCE=y
+CONFIG_CACHE_L2X0=y
+CONFIG_CAN=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLK_SUNXI=y
+CONFIG_CLK_SUNXI_CLOCKS=y
+CONFIG_CLK_SUNXI_PRCM_SUN6I=y
+CONFIG_CLK_SUNXI_PRCM_SUN8I=y
+CONFIG_CLK_SUNXI_PRCM_SUN9I=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_CONNECTOR=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_COREDUMP=y
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPUFREQ_DT_PLATDEV=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_SPECTRE=y
+CONFIG_CPU_THERMAL=y
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_V7=y
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRYPTO_CRC32=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_CRCT10DIF=y
+CONFIG_CRYPTO_CRCT10DIF_ARM_CE=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_DEV_ALLWINNER=y
+CONFIG_CRYPTO_DEV_SUN4I_SS=y
+# CONFIG_CRYPTO_DEV_SUN4I_SS_DEBUG is not set
+CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG=y
+# CONFIG_CRYPTO_DEV_SUN8I_CE is not set
+# CONFIG_CRYPTO_DEV_SUN8I_SS is not set
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_LIB_DES=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_SHA1=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_DMADEVICES=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_OPS=y
+CONFIG_DMA_REMAP=y
+CONFIG_DMA_SUN4I=y
+CONFIG_DMA_SUN6I=y
+CONFIG_DMA_VIRTUAL_CHANNELS=y
+CONFIG_DNOTIFY=y
+CONFIG_DTC=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_DVB_CORE=y
+CONFIG_DWMAC_GENERIC=y
+# CONFIG_DWMAC_SUN8I is not set
+CONFIG_DWMAC_SUNXI=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_ELF_CORE=y
+CONFIG_EXT4_FS=y
+CONFIG_EXTCON=y
+CONFIG_F2FS_FS=y
+CONFIG_FAT_FS=y
+CONFIG_FB=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+CONFIG_FB_CMDLINE=y
+CONFIG_FB_FOREIGN_ENDIAN=y
+CONFIG_FB_LITTLE_ENDIAN=y
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_SIMPLE=y
+CONFIG_FB_TILEBLITTING=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FONT_8x16=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_SUPPORT=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+CONFIG_FRAME_WARN=2048
+CONFIG_FREEZER=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_CACHE=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_VDSO_32=y
+CONFIG_GLOB=y
+CONFIG_GPIO_CDEV=y
+CONFIG_HANDLE_DOMAIN_IRQ=y
+CONFIG_HARDEN_BRANCH_PREDICTOR=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HAVE_SMP=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGHPTE=y
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HWMON=y
+CONFIG_HW_CONSOLE=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_TIMERIOMEM=y
+CONFIG_HZ_FIXED=0
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_MV64XXX=y
+CONFIG_I2C_SUN6I_P2WI=y
+CONFIG_IIO=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INPUT=y
+CONFIG_INPUT_AXP20X_PEK=y
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+CONFIG_JBD2=y
+CONFIG_KALLSYMS=y
+CONFIG_KEYBOARD_SUN4I_LRADC=y
+CONFIG_KMAP_LOCAL=y
+CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
+CONFIG_KSM=y
+CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_LCD_PLATFORM=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_MACH_SUN4I=y
+CONFIG_MACH_SUN5I=y
+CONFIG_MACH_SUN6I=y
+CONFIG_MACH_SUN7I=y
+CONFIG_MACH_SUN8I=y
+CONFIG_MACH_SUN9I=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MDIO_SUN4I=y
+CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
+CONFIG_MEDIA_ATTACH=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
+CONFIG_MEDIA_PLATFORM_SUPPORT=y
+CONFIG_MEDIA_RADIO_SUPPORT=y
+CONFIG_MEDIA_SDR_SUPPORT=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_TEST_SUPPORT=y
+CONFIG_MEDIA_TUNER=y
+CONFIG_MEMFD_CREATE=y
+CONFIG_MFD_AXP20X=y
+CONFIG_MFD_AXP20X_I2C=y
+CONFIG_MFD_AXP20X_RSB=y
+CONFIG_MFD_CORE=y
+CONFIG_MFD_SUN6I_PRCM=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_SUNXI=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPLIT_FIT_FW=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEON=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_VENDOR_ALLWINNER=y
+CONFIG_NLS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NO_HZ=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=8
+CONFIG_NVMEM=y
+CONFIG_NVMEM_SUNXI_SID=y
+CONFIG_NVMEM_SYSFS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_OUTER_CACHE=y
+CONFIG_OUTER_CACHE_SYNC=y
+CONFIG_PADATA=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PAGE_POOL=y
+CONFIG_PCS_XPCS=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=3
+CONFIG_PHYLIB=y
+CONFIG_PHYLINK=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_PHY_SUN4I_USB=y
+# CONFIG_PHY_SUN50I_USB3 is not set
+# CONFIG_PHY_SUN6I_MIPI_DPHY is not set
+CONFIG_PHY_SUN9I_USB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AXP209=y
+# CONFIG_PINCTRL_SUN20I_D1 is not set
+CONFIG_PINCTRL_SUN4I_A10=y
+# CONFIG_PINCTRL_SUN50I_A100 is not set
+# CONFIG_PINCTRL_SUN50I_A100_R is not set
+# CONFIG_PINCTRL_SUN50I_A64 is not set
+# CONFIG_PINCTRL_SUN50I_A64_R is not set
+# CONFIG_PINCTRL_SUN50I_H5 is not set
+# CONFIG_PINCTRL_SUN50I_H6 is not set
+# CONFIG_PINCTRL_SUN50I_H616 is not set
+# CONFIG_PINCTRL_SUN50I_H616_R is not set
+# CONFIG_PINCTRL_SUN50I_H6_R is not set
+CONFIG_PINCTRL_SUN5I=y
+CONFIG_PINCTRL_SUN6I_A31=y
+CONFIG_PINCTRL_SUN6I_A31_R=y
+CONFIG_PINCTRL_SUN8I_A23=y
+CONFIG_PINCTRL_SUN8I_A23_R=y
+CONFIG_PINCTRL_SUN8I_A33=y
+CONFIG_PINCTRL_SUN8I_A83T=y
+CONFIG_PINCTRL_SUN8I_A83T_R=y
+CONFIG_PINCTRL_SUN8I_H3=y
+CONFIG_PINCTRL_SUN8I_H3_R=y
+CONFIG_PINCTRL_SUN8I_V3S=y
+CONFIG_PINCTRL_SUN9I_A80=y
+CONFIG_PINCTRL_SUN9I_A80_R=y
+CONFIG_PINCTRL_SUNXI=y
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_PM_OPP=y
+CONFIG_PM_SLEEP=y
+CONFIG_PM_SLEEP_SMP=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PPS=y
+CONFIG_PRINTK_TIME=y
+CONFIG_PROC_EVENTS=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_PWM=y
+CONFIG_PWM_SUN4I=y
+CONFIG_PWM_SYSFS=y
+CONFIG_RATIONAL=y
+CONFIG_REALTEK_PHY=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_IRQ=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGMAP_SPI=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_AXP20X=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_REGULATOR_SY8106A=y
+CONFIG_RELAY=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RESET_SIMPLE=y
+CONFIG_RESET_SUNXI=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_SATA_HOST=y
+CONFIG_SATA_PMP=y
+CONFIG_SCSI=y
+CONFIG_SCSI_COMMON=y
+CONFIG_SDIO_UART=y
+CONFIG_SECURITYFS=y
+CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_8250_DWLIB=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_NR_UARTS=8
+CONFIG_SERIAL_8250_RUNTIME_UARTS=8
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SG_POOL=y
+CONFIG_SMP=y
+CONFIG_SMP_ON_UP=y
+CONFIG_SND=y
+CONFIG_SND_COMPRESS_OFFLOAD=y
+CONFIG_SND_JACK=y
+CONFIG_SND_JACK_INPUT_DEV=y
+CONFIG_SND_PCM=y
+CONFIG_SND_SIMPLE_CARD=y
+CONFIG_SND_SIMPLE_CARD_UTILS=y
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+# CONFIG_SND_SUN4I_I2S is not set
+# CONFIG_SND_SUN4I_SPDIF is not set
+# CONFIG_SND_SUN50I_DMIC is not set
+# CONFIG_SND_SUN8I_CODEC is not set
+# CONFIG_SND_SUN8I_CODEC_ANALOG is not set
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SPI_SUN4I=y
+CONFIG_SPI_SUN6I=y
+CONFIG_SRCU=y
+CONFIG_STMMAC_ETH=y
+CONFIG_STMMAC_PLATFORM=y
+# CONFIG_SUN20I_GPADC is not set
+# CONFIG_SUN20I_PPU is not set
+CONFIG_SUN4I_A10_CCU=y
+# CONFIG_SUN4I_EMAC is not set
+CONFIG_SUN4I_TIMER=y
+CONFIG_SUN5I_CCU=y
+CONFIG_SUN5I_HSTIMER=y
+CONFIG_SUN6I_A31_CCU=y
+# CONFIG_SUN6I_RTC_CCU is not set
+CONFIG_SUN8I_A23_CCU=y
+CONFIG_SUN8I_A33_CCU=y
+CONFIG_SUN8I_A83T_CCU=y
+CONFIG_SUN8I_DE2_CCU=y
+CONFIG_SUN8I_H3_CCU=y
+CONFIG_SUN8I_R40_CCU=y
+CONFIG_SUN8I_R_CCU=y
+CONFIG_SUN8I_THERMAL=y
+CONFIG_SUN8I_V3S_CCU=y
+CONFIG_SUN9I_A80_CCU=y
+CONFIG_SUNXI_CCU=y
+CONFIG_SUNXI_MBUS=y
+CONFIG_SUNXI_RSB=y
+CONFIG_SUNXI_SRAM=y
+CONFIG_SUNXI_WATCHDOG=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_SWIOTLB=y
+CONFIG_SWPHY=y
+CONFIG_SWP_EMULATE=y
+CONFIG_SYSFS_SYSCALL=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_OF=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_TOUCHSCREEN_SUN4I=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNWINDER_ARM=y
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_DWC2_HOST=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_NET_DRIVERS=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_ROLE_SWITCH=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USERIO=y
+CONFIG_USE_OF=y
+CONFIG_VFAT_FS=y
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_VHOST=y
+CONFIG_VHOST_IOTLB=y
+CONFIG_VHOST_NET=y
+# CONFIG_VIDEO_SUN4I_CSI is not set
+# CONFIG_VIDEO_SUN6I_CSI is not set
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_CONSOLE_SLEEP=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_ZBOOT_ROM_TEXT=0
--- /dev/null
+CONFIG_64BIT=y
+CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
+CONFIG_ARCH_MMAP_RND_BITS=18
+CONFIG_ARCH_MMAP_RND_BITS_MAX=24
+CONFIG_ARCH_MMAP_RND_BITS_MIN=18
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
+CONFIG_ARCH_PROC_KCORE_TEXT=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_WANTS_NO_INSTR=y
+CONFIG_ARM64=y
+CONFIG_ARM64_4K_PAGES=y
+CONFIG_ARM64_CRYPTO=y
+CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
+CONFIG_ARM64_ERRATUM_2051678=y
+CONFIG_ARM64_ERRATUM_2077057=y
+CONFIG_ARM64_ERRATUM_2658417=y
+CONFIG_ARM64_ERRATUM_2054223=y
+CONFIG_ARM64_ERRATUM_2067961=y
+CONFIG_ARM64_PAGE_SHIFT=12
+CONFIG_ARM64_PA_BITS=48
+CONFIG_ARM64_PA_BITS_48=y
+CONFIG_ARM64_TAGGED_ADDR_ABI=y
+CONFIG_ARM64_VA_BITS=39
+CONFIG_ARM64_VA_BITS_39=y
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
+CONFIG_ARM_GIC_V3=y
+CONFIG_ARM_GIC_V3_ITS=y
+CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
+CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CRYPTO_AES_ARM64=y
+CONFIG_CRYPTO_AES_ARM64_CE=y
+CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
+CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
+CONFIG_CRYPTO_BLAKE2S=y
+CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
+CONFIG_CRYPTO_CRYPTD=y
+CONFIG_CRYPTO_GHASH_ARM64_CE=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_SHA1_ARM64_CE=y
+CONFIG_CRYPTO_SIMD=y
+CONFIG_DMA_DIRECT_REMAP=y
+CONFIG_DWMAC_SUN8I=y
+CONFIG_EEPROM_AT24=y
+CONFIG_FRAME_POINTER=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_FIND_FIRST_BIT=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
+CONFIG_MDIO_BUS_MUX=y
+CONFIG_MICREL_PHY=y
+# CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY is not set
+CONFIG_MODULES_USE_ELF_RELA=y
+CONFIG_MOTORCOMM_PHY=y
+CONFIG_MUSB_PIO_ONLY=y
+CONFIG_NEED_SG_DMA_LENGTH=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_NO_IOPORT_MAP=y
+CONFIG_PARTITION_PERCPU=y
+CONFIG_PHY_SUN50I_USB3=y
+CONFIG_PINCTRL_SUN50I_A100=y
+CONFIG_PINCTRL_SUN50I_A100_R=y
+CONFIG_PINCTRL_SUN50I_A64=y
+CONFIG_PINCTRL_SUN50I_A64_R=y
+CONFIG_PINCTRL_SUN50I_H5=y
+CONFIG_PINCTRL_SUN50I_H6=y
+CONFIG_PINCTRL_SUN50I_H6_R=y
+CONFIG_PINCTRL_SUN50I_H616=y
+CONFIG_PINCTRL_SUN50I_H616_R=y
+# CONFIG_PREEMPT_DYNAMIC is not set
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
+# CONFIG_SCHED_CLUSTER is not set
+# CONFIG_SHADOW_CALL_STACK is not set
+# CONFIG_SND_SUN50I_CODEC_ANALOG is not set
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
+CONFIG_SPARSEMEM=y
+CONFIG_SPARSEMEM_EXTREME=y
+CONFIG_SPARSEMEM_VMEMMAP=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SUN50I_A100_CCU=y
+CONFIG_SUN50I_A100_R_CCU=y
+CONFIG_SUN50I_A64_CCU=y
+CONFIG_SUN50I_DE2_BUS=y
+CONFIG_SUN50I_ERRATUM_UNKNOWN1=y
+CONFIG_SUN50I_H616_CCU=y
+CONFIG_SUN50I_H6_CCU=y
+CONFIG_SUN50I_H6_R_CCU=y
+# CONFIG_SUN6I_RTC_CCU is not set
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_UNMAP_KERNEL_AT_EL0=y
+CONFIG_USB_MUSB_DUAL_ROLE=y
+CONFIG_USB_MUSB_HDRC=y
+CONFIG_USB_MUSB_SUNXI=y
+CONFIG_USB_PHY=y
+CONFIG_VMAP_STACK=y
+CONFIG_ZONE_DMA32=y
+CONFIG_SURFACE_PLATFORMS=y
+# CONFIG_CRYPTO_POLYVAL_ARM64_CE is not set
+# CONFIG_CRYPTO_SM4_ARM64_CE_BLK is not set
+# CONFIG_CRYPTO_SM4_ARM64_NEON_BLK is not set
+# CONFIG_PAGE_TABLE_CHECK is not set
+CONFIG_RANDOMIZE_KSTACK_OFFSET=y
+# CONFIG_ARCH_NXP is not set
BOARDNAME:=Allwinner A64/H5/H6/H616
CPU_TYPE:=cortex-a53
KERNELNAME:=Image dtbs
+FEATURES+=fpu
\ No newline at end of file
--- /dev/null
+CONFIG_B53=y
+CONFIG_B53_MDIO_DRIVER=y
+CONFIG_CRYPTO_BLAKE2S_ARM=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_DWMAC_SUN8I=y
+CONFIG_GRO_CELLS=y
+# CONFIG_HARDEN_BRANCH_HISTORY is not set
+# CONFIG_HARDEN_BRANCH_PREDICTOR is not set
+# CONFIG_MACH_SUN4I is not set
+# CONFIG_MACH_SUN5I is not set
+CONFIG_MDIO_BUS_MUX=y
+CONFIG_MICREL_PHY=y
+CONFIG_MUSB_PIO_ONLY=y
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_TAG_BRCM=y
+CONFIG_NET_DSA_TAG_BRCM_COMMON=y
+CONFIG_NET_DSA_TAG_BRCM_LEGACY=y
+CONFIG_NET_DSA_TAG_BRCM_PREPEND=y
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_RTC_DRV_SUN6I=y
+CONFIG_SUN20I_D1_CCU=y
+CONFIG_SUN20I_D1_R_CCU=y
+CONFIG_USB_MUSB_DUAL_ROLE=y
+CONFIG_USB_MUSB_HDRC=y
+CONFIG_USB_MUSB_SUNXI=y
+CONFIG_USB_PHY=y
BOARDNAME:=Allwinner A20/A3x/H3/R40
CPU_TYPE:=cortex-a7
CPU_SUBTYPE:=neon-vfpv4
+FEATURES+=fpu
--- /dev/null
+# CONFIG_ARM_LPAE is not set
+CONFIG_CRYPTO_BLAKE2S_ARM=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+# CONFIG_MACH_SUN6I is not set
+# CONFIG_MACH_SUN7I is not set
+# CONFIG_MACH_SUN8I is not set
+# CONFIG_MACH_SUN9I is not set
+CONFIG_PGTABLE_LEVELS=2
+# CONFIG_PHY_SUN9I_USB is not set
+# CONFIG_SPI_SUN6I is not set
+# CONFIG_SUN8I_A83T_CCU is not set
+# CONFIG_SUN8I_THERMAL is not set
BOARDNAME:=Allwinner A1x
CPU_TYPE:=cortex-a8
CPU_SUBTYPE:=vfpv3
+FEATURES+=fpu
FAT32_BLOCKS=$(shell echo $$(($(CONFIG_SUNXI_SD_BOOT_PARTSIZE)*1024*1024/$(FAT32_BLOCK_SIZE))))
DEVICE_VARS := SUNXI_DTS SUNXI_DTS_DIR
-KERNEL_LOADADDR:=0x40008000
define Build/sunxi-sdcard
rm -f $@.boot
KERNEL := kernel-bin | uImage none
IMAGES := sdcard.img.gz
IMAGE/sdcard.img.gz := sunxi-sdcard | append-metadata | gzip
- SUNXI_DTS_DIR :=
+ifdef CONFIG_LINUX_6_6
+ SUNXI_DTS_DIR :=allwinner/
+endif
SUNXI_DTS = $$(SUNXI_DTS_DIR)$$(SOC)-$(lastword $(subst _, ,$(1)))
endef
# Copyright (C) 2013-2016 OpenWrt.org
# Copyright (C) 2016 Yousong Zhou
+KERNEL_LOADADDR:=0x40008000
+
define Device/sun50i
SUNXI_DTS_DIR := allwinner/
KERNEL_NAME := Image
# Copyright (C) 2013-2019 OpenWrt.org
# Copyright (C) 2016 Yousong Zhou
+KERNEL_LOADADDR:=0x40008000
+
define Device/cubietech_cubieboard2
DEVICE_VENDOR := Cubietech
DEVICE_MODEL := Cubieboard2
# Copyright (C) 2013-2016 OpenWrt.org
# Copyright (C) 2016 Yousong Zhou
+KERNEL_LOADADDR:=0x40008000
+
define Device/cubietech_a10-cubieboard
DEVICE_VENDOR := Cubietech
DEVICE_MODEL := Cubieboard
--- /dev/null
+From 951992797378a2177946400438f4d23c9fceae5b Mon Sep 17 00:00:00 2001
+From: Martin Botka <martin.botka@somainline.org>
+Date: Tue, 12 Sep 2023 14:25:13 +0200
+Subject: [PATCH] arm64: dts: allwinner: h616: Add SID controller node
+
+Add node for the H616 SID controller
+
+Signed-off-by: Martin Botka <martin.botka@somainline.org>
+Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Link: https://lore.kernel.org/r/20230912-sid-h616-v3-2-ee18e1c5bbb5@somainline.org
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+@@ -133,6 +133,13 @@
+ #reset-cells = <1>;
+ };
+
++ sid: efuse@3006000 {
++ compatible = "allwinner,sun50i-h616-sid", "allwinner,sun50i-a64-sid";
++ reg = <0x03006000 0x1000>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ };
++
+ watchdog: watchdog@30090a0 {
+ compatible = "allwinner,sun50i-h616-wdt",
+ "allwinner,sun6i-a31-wdt";
--- /dev/null
+From 898d96c5464b69af44f6407c5de81ebc349d574b Mon Sep 17 00:00:00 2001
+From: Andre Przywara <andre.przywara@arm.com>
+Date: Mon, 19 Feb 2024 15:36:33 +0000
+Subject: [PATCH] soc: sunxi: sram: export register 0 for THS on H616
+
+The Allwinner H616 SoC contains a mysterious bit at register offset 0x0
+in the SRAM control block. If bit 16 is set (the reset value), the
+temperature readings of the THS are way off, leading to reports about
+200C, at normal ambient temperatures. Clearing this bits brings the
+reported values down to the expected values.
+The BSP code clears this bit in firmware (U-Boot), and has an explicit
+comment about this, but offers no real explanation.
+
+Experiments in U-Boot show that register 0x0 has no effect on the SRAM C
+visibility: all tested bit settings still allow full read and write
+access by the CPU to the whole of SRAM C. Only bit 24 of the register at
+offset 0x4 makes all of SRAM C inaccessible by the CPU. So modelling
+the THS switch functionality as an SRAM region would not reflect reality.
+
+Since we should not rely on firmware settings, allow other code (the THS
+driver) to access this register, by exporting it through the already
+existing regmap. This mimics what we already do for the LDO control and
+the EMAC register.
+
+To avoid concurrent accesses to the same register at the same time, by
+the SRAM switch code and the regmap code, use the same lock to protect
+the access. The regmap subsystem allows to use an existing lock, so we
+just need to hook in there.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20240219153639.179814-2-andre.przywara@arm.com
+---
+ drivers/soc/sunxi/sunxi_sram.c | 22 ++++++++++++++++++++++
+ 1 file changed, 22 insertions(+)
+
+--- a/drivers/soc/sunxi/sunxi_sram.c
++++ b/drivers/soc/sunxi/sunxi_sram.c
+@@ -287,6 +287,7 @@ EXPORT_SYMBOL(sunxi_sram_release);
+ struct sunxi_sramc_variant {
+ int num_emac_clocks;
+ bool has_ldo_ctrl;
++ bool has_ths_offset;
+ };
+
+ static const struct sunxi_sramc_variant sun4i_a10_sramc_variant = {
+@@ -308,8 +309,10 @@ static const struct sunxi_sramc_variant
+
+ static const struct sunxi_sramc_variant sun50i_h616_sramc_variant = {
+ .num_emac_clocks = 2,
++ .has_ths_offset = true,
+ };
+
++#define SUNXI_SRAM_THS_OFFSET_REG 0x0
+ #define SUNXI_SRAM_EMAC_CLOCK_REG 0x30
+ #define SUNXI_SYS_LDO_CTRL_REG 0x150
+
+@@ -318,6 +321,8 @@ static bool sunxi_sram_regmap_accessible
+ {
+ const struct sunxi_sramc_variant *variant = dev_get_drvdata(dev);
+
++ if (reg == SUNXI_SRAM_THS_OFFSET_REG && variant->has_ths_offset)
++ return true;
+ if (reg >= SUNXI_SRAM_EMAC_CLOCK_REG &&
+ reg < SUNXI_SRAM_EMAC_CLOCK_REG + variant->num_emac_clocks * 4)
+ return true;
+@@ -327,6 +332,20 @@ static bool sunxi_sram_regmap_accessible
+ return false;
+ }
+
++static void sunxi_sram_lock(void *_lock)
++{
++ spinlock_t *lock = _lock;
++
++ spin_lock(lock);
++}
++
++static void sunxi_sram_unlock(void *_lock)
++{
++ spinlock_t *lock = _lock;
++
++ spin_unlock(lock);
++}
++
+ static struct regmap_config sunxi_sram_regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+@@ -336,6 +355,9 @@ static struct regmap_config sunxi_sram_r
+ /* other devices have no business accessing other registers */
+ .readable_reg = sunxi_sram_regmap_accessible_reg,
+ .writeable_reg = sunxi_sram_regmap_accessible_reg,
++ .lock = sunxi_sram_lock,
++ .unlock = sunxi_sram_unlock,
++ .lock_arg = &sram_lock,
+ };
+
+ static int __init sunxi_sram_probe(struct platform_device *pdev)
--- /dev/null
+From ebbf19e36d021f253425344b4d4b987f3b7d9be5 Mon Sep 17 00:00:00 2001
+From: Maxim Kiselev <bigunclemax@gmail.com>
+Date: Mon, 18 Dec 2023 00:06:23 +0300
+Subject: [PATCH] thermal/drivers/sun8i: Add D1/T113s THS controller support
+
+This patch adds a thermal sensor controller support for the D1/T113s,
+which is similar to the one on H6, but with only one sensor and
+different scale and offset values.
+
+Signed-off-by: Maxim Kiselev <bigunclemax@gmail.com>
+Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Reviewed-by: Andre Przywara <andre.przywara@arm.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20231217210629.131486-3-bigunclemax@gmail.com
+---
+ drivers/thermal/sun8i_thermal.c | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+--- a/drivers/thermal/sun8i_thermal.c
++++ b/drivers/thermal/sun8i_thermal.c
+@@ -606,6 +606,18 @@ static const struct ths_thermal_chip sun
+ .calc_temp = sun8i_ths_calc_temp,
+ };
+
++static const struct ths_thermal_chip sun20i_d1_ths = {
++ .sensor_num = 1,
++ .has_bus_clk_reset = true,
++ .offset = 188552,
++ .scale = 673,
++ .temp_data_base = SUN50I_H6_THS_TEMP_DATA,
++ .calibrate = sun50i_h6_ths_calibrate,
++ .init = sun50i_h6_thermal_init,
++ .irq_ack = sun50i_h6_irq_ack,
++ .calc_temp = sun8i_ths_calc_temp,
++};
++
+ static const struct of_device_id of_ths_match[] = {
+ { .compatible = "allwinner,sun8i-a83t-ths", .data = &sun8i_a83t_ths },
+ { .compatible = "allwinner,sun8i-h3-ths", .data = &sun8i_h3_ths },
+@@ -614,6 +626,7 @@ static const struct of_device_id of_ths_
+ { .compatible = "allwinner,sun50i-a100-ths", .data = &sun50i_a100_ths },
+ { .compatible = "allwinner,sun50i-h5-ths", .data = &sun50i_h5_ths },
+ { .compatible = "allwinner,sun50i-h6-ths", .data = &sun50i_h6_ths },
++ { .compatible = "allwinner,sun20i-d1-ths", .data = &sun20i_d1_ths },
+ { /* sentinel */ },
+ };
+ MODULE_DEVICE_TABLE(of, of_ths_match);
--- /dev/null
+From 14f118aa50fe7c7c7330f56d007ecacca487cea8 Mon Sep 17 00:00:00 2001
+From: Andre Przywara <andre.przywara@arm.com>
+Date: Mon, 19 Feb 2024 15:36:35 +0000
+Subject: [PATCH] thermal/drivers/sun8i: Explain unknown H6 register value
+
+So far we were ORing in some "unknown" value into the THS control
+register on the Allwinner H6. This part of the register is not explained
+in the H6 manual, but the H616 manual details those bits, and on closer
+inspection the THS IP blocks in both SoCs seem very close:
+- The BSP code for both SoCs writes the same values into THS_CTRL.
+- The reset values of at least the first three registers are the same.
+
+Replace the "unknown" value with its proper meaning: "acquire time",
+most probably the sample part of the sample & hold circuit of the ADC,
+according to its explanation in the H616 manual.
+
+No functional change, just a macro rename and adjustment.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Acked-by: Vasily Khoruzhick <anarsoul@gmail.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20240219153639.179814-4-andre.przywara@arm.com
+---
+ drivers/thermal/sun8i_thermal.c | 29 ++++++++++++++++-------------
+ 1 file changed, 16 insertions(+), 13 deletions(-)
+
+--- a/drivers/thermal/sun8i_thermal.c
++++ b/drivers/thermal/sun8i_thermal.c
+@@ -50,7 +50,8 @@
+ #define SUN8I_THS_CTRL2_T_ACQ1(x) ((GENMASK(15, 0) & (x)) << 16)
+ #define SUN8I_THS_DATA_IRQ_STS(x) BIT(x + 8)
+
+-#define SUN50I_THS_CTRL0_T_ACQ(x) ((GENMASK(15, 0) & (x)) << 16)
++#define SUN50I_THS_CTRL0_T_ACQ(x) (GENMASK(15, 0) & ((x) - 1))
++#define SUN50I_THS_CTRL0_T_SAMPLE_PER(x) ((GENMASK(15, 0) & ((x) - 1)) << 16)
+ #define SUN50I_THS_FILTER_EN BIT(2)
+ #define SUN50I_THS_FILTER_TYPE(x) (GENMASK(1, 0) & (x))
+ #define SUN50I_H6_THS_PC_TEMP_PERIOD(x) ((GENMASK(19, 0) & (x)) << 12)
+@@ -410,25 +411,27 @@ static int sun8i_h3_thermal_init(struct
+ return 0;
+ }
+
+-/*
+- * Without this undocumented value, the returned temperatures would
+- * be higher than real ones by about 20C.
+- */
+-#define SUN50I_H6_CTRL0_UNK 0x0000002f
+-
+ static int sun50i_h6_thermal_init(struct ths_device *tmdev)
+ {
+ int val;
+
+ /*
+- * T_acq = 20us
+- * clkin = 24MHz
+- *
+- * x = T_acq * clkin - 1
+- * = 479
++ * The manual recommends an overall sample frequency of 50 KHz (20us,
++ * 480 cycles at 24 MHz), which provides plenty of time for both the
++ * acquisition time (>24 cycles) and the actual conversion time
++ * (>14 cycles).
++ * The lower half of the CTRL register holds the "acquire time", in
++ * clock cycles, which the manual recommends to be 2us:
++ * 24MHz * 2us = 48 cycles.
++ * The high half of THS_CTRL encodes the sample frequency, in clock
++ * cycles: 24MHz * 20us = 480 cycles.
++ * This is explained in the H616 manual, but apparently wrongly
++ * described in the H6 manual, although the BSP code does the same
++ * for both SoCs.
+ */
+ regmap_write(tmdev->regmap, SUN50I_THS_CTRL0,
+- SUN50I_H6_CTRL0_UNK | SUN50I_THS_CTRL0_T_ACQ(479));
++ SUN50I_THS_CTRL0_T_ACQ(48) |
++ SUN50I_THS_CTRL0_T_SAMPLE_PER(480));
+ /* average over 4 samples */
+ regmap_write(tmdev->regmap, SUN50I_H6_THS_MFC,
+ SUN50I_THS_FILTER_EN |
--- /dev/null
+From 6c04a419a4c5fb18edefc44dd676fb95c7f6c55d Mon Sep 17 00:00:00 2001
+From: Maksim Kiselev <bigunclemax@gmail.com>
+Date: Mon, 19 Feb 2024 15:36:36 +0000
+Subject: [PATCH] thermal/drivers/sun8i: Extend H6 calibration to support 4
+ sensors
+
+The H616 SoC resembles the H6 thermal sensor controller, with a few
+changes like four sensors.
+
+Extend sun50i_h6_ths_calibrate() function to support calibration of
+these sensors.
+
+Co-developed-by: Martin Botka <martin.botka@somainline.org>
+Signed-off-by: Martin Botka <martin.botka@somainline.org>
+Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
+Reviewed-by: Andre Przywara <andre.przywara@arm.com>
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Acked-by: Vasily Khoruzhick <anarsoul@gmail.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20240219153639.179814-5-andre.przywara@arm.com
+---
+ drivers/thermal/sun8i_thermal.c | 28 ++++++++++++++++++++--------
+ 1 file changed, 20 insertions(+), 8 deletions(-)
+
+--- a/drivers/thermal/sun8i_thermal.c
++++ b/drivers/thermal/sun8i_thermal.c
+@@ -222,16 +222,21 @@ static int sun50i_h6_ths_calibrate(struc
+ struct device *dev = tmdev->dev;
+ int i, ft_temp;
+
+- if (!caldata[0] || callen < 2 + 2 * tmdev->chip->sensor_num)
++ if (!caldata[0])
+ return -EINVAL;
+
+ /*
+ * efuse layout:
+ *
+- * 0 11 16 32
+- * +-------+-------+-------+
+- * |temp| |sensor0|sensor1|
+- * +-------+-------+-------+
++ * 0 11 16 27 32 43 48 57
++ * +----------+-----------+-----------+-----------+
++ * | temp | |sensor0| |sensor1| |sensor2| |
++ * +----------+-----------+-----------+-----------+
++ * ^ ^ ^
++ * | | |
++ * | | sensor3[11:8]
++ * | sensor3[7:4]
++ * sensor3[3:0]
+ *
+ * The calibration data on the H6 is the ambient temperature and
+ * sensor values that are filled during the factory test stage.
+@@ -244,9 +249,16 @@ static int sun50i_h6_ths_calibrate(struc
+ ft_temp = (caldata[0] & FT_TEMP_MASK) * 100;
+
+ for (i = 0; i < tmdev->chip->sensor_num; i++) {
+- int sensor_reg = caldata[i + 1] & TEMP_CALIB_MASK;
+- int cdata, offset;
+- int sensor_temp = tmdev->chip->calc_temp(tmdev, i, sensor_reg);
++ int sensor_reg, sensor_temp, cdata, offset;
++
++ if (i == 3)
++ sensor_reg = (caldata[1] >> 12)
++ | ((caldata[2] >> 12) << 4)
++ | ((caldata[3] >> 12) << 8);
++ else
++ sensor_reg = caldata[i + 1] & TEMP_CALIB_MASK;
++
++ sensor_temp = tmdev->chip->calc_temp(tmdev, i, sensor_reg);
+
+ /*
+ * Calibration data is CALIBRATE_DEFAULT - (calculated
--- /dev/null
+From f8b54d1120b81ed57bed96cc8e814ba08886d1e5 Mon Sep 17 00:00:00 2001
+From: Andre Przywara <andre.przywara@arm.com>
+Date: Mon, 19 Feb 2024 15:36:37 +0000
+Subject: [PATCH] thermal/drivers/sun8i: Add SRAM register access code
+
+The Allwinner H616 SoC needs to clear a bit in one register in the SRAM
+controller, to report reasonable temperature values. On reset, bit 16 in
+register 0x3000000 is set, which leads to the driver reporting
+temperatures around 200C. Clearing this bit brings the values down to the
+expected range. The BSP code does a one-time write in U-Boot, with a
+comment just mentioning the effect on the THS, but offering no further
+explanation.
+
+To not rely on firmware to set things up for us, add code that queries
+the SRAM controller device via a DT phandle link, then clear just this
+single bit.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+Acked-by: Vasily Khoruzhick <anarsoul@gmail.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20240219153639.179814-6-andre.przywara@arm.com
+---
+ drivers/thermal/sun8i_thermal.c | 51 +++++++++++++++++++++++++++++++++
+ 1 file changed, 51 insertions(+)
+
+--- a/drivers/thermal/sun8i_thermal.c
++++ b/drivers/thermal/sun8i_thermal.c
+@@ -15,6 +15,7 @@
+ #include <linux/module.h>
+ #include <linux/nvmem-consumer.h>
+ #include <linux/of.h>
++#include <linux/of_platform.h>
+ #include <linux/platform_device.h>
+ #include <linux/regmap.h>
+ #include <linux/reset.h>
+@@ -66,6 +67,7 @@ struct tsensor {
+ struct ths_thermal_chip {
+ bool has_mod_clk;
+ bool has_bus_clk_reset;
++ bool needs_sram;
+ int sensor_num;
+ int offset;
+ int scale;
+@@ -83,12 +85,16 @@ struct ths_device {
+ const struct ths_thermal_chip *chip;
+ struct device *dev;
+ struct regmap *regmap;
++ struct regmap_field *sram_regmap_field;
+ struct reset_control *reset;
+ struct clk *bus_clk;
+ struct clk *mod_clk;
+ struct tsensor sensor[MAX_SENSOR_NUM];
+ };
+
++/* The H616 needs to have a bit 16 in the SRAM control register cleared. */
++static const struct reg_field sun8i_ths_sram_reg_field = REG_FIELD(0x0, 16, 16);
++
+ /* Temp Unit: millidegree Celsius */
+ static int sun8i_ths_calc_temp(struct ths_device *tmdev,
+ int id, int reg)
+@@ -337,6 +343,34 @@ static void sun8i_ths_reset_control_asse
+ reset_control_assert(data);
+ }
+
++static struct regmap *sun8i_ths_get_sram_regmap(struct device_node *node)
++{
++ struct device_node *sram_node;
++ struct platform_device *sram_pdev;
++ struct regmap *regmap = NULL;
++
++ sram_node = of_parse_phandle(node, "allwinner,sram", 0);
++ if (!sram_node)
++ return ERR_PTR(-ENODEV);
++
++ sram_pdev = of_find_device_by_node(sram_node);
++ if (!sram_pdev) {
++ /* platform device might not be probed yet */
++ regmap = ERR_PTR(-EPROBE_DEFER);
++ goto out_put_node;
++ }
++
++ /* If no regmap is found then the other device driver is at fault */
++ regmap = dev_get_regmap(&sram_pdev->dev, NULL);
++ if (!regmap)
++ regmap = ERR_PTR(-EINVAL);
++
++ platform_device_put(sram_pdev);
++out_put_node:
++ of_node_put(sram_node);
++ return regmap;
++}
++
+ static int sun8i_ths_resource_init(struct ths_device *tmdev)
+ {
+ struct device *dev = tmdev->dev;
+@@ -381,6 +415,19 @@ static int sun8i_ths_resource_init(struc
+ if (ret)
+ return ret;
+
++ if (tmdev->chip->needs_sram) {
++ struct regmap *regmap;
++
++ regmap = sun8i_ths_get_sram_regmap(dev->of_node);
++ if (IS_ERR(regmap))
++ return PTR_ERR(regmap);
++ tmdev->sram_regmap_field = devm_regmap_field_alloc(dev,
++ regmap,
++ sun8i_ths_sram_reg_field);
++ if (IS_ERR(tmdev->sram_regmap_field))
++ return PTR_ERR(tmdev->sram_regmap_field);
++ }
++
+ ret = sun8i_ths_calibrate(tmdev);
+ if (ret)
+ return ret;
+@@ -427,6 +474,10 @@ static int sun50i_h6_thermal_init(struct
+ {
+ int val;
+
++ /* The H616 needs to have a bit in the SRAM control register cleared. */
++ if (tmdev->sram_regmap_field)
++ regmap_field_write(tmdev->sram_regmap_field, 0);
++
+ /*
+ * The manual recommends an overall sample frequency of 50 KHz (20us,
+ * 480 cycles at 24 MHz), which provides plenty of time for both the
--- /dev/null
+From e7dbfa19572a1440a2e67ef70f94ff204849a0a8 Mon Sep 17 00:00:00 2001
+From: Martin Botka <martin.botka@somainline.org>
+Date: Mon, 19 Feb 2024 15:36:38 +0000
+Subject: [PATCH] thermal/drivers/sun8i: Add support for H616 THS controller
+
+Add support for the thermal sensor found in H616 SoCs, is the same as
+the H6 thermal sensor controller, but with four sensors.
+Also the registers readings are wrong, unless a bit in the first SYS_CFG
+register cleared, so set exercise the SRAM regmap to take care of that.
+
+Signed-off-by: Martin Botka <martin.botka@somainline.org>
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+Acked-by: Vasily Khoruzhick <anarsoul@gmail.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20240219153639.179814-7-andre.przywara@arm.com
+---
+ drivers/thermal/sun8i_thermal.c | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+--- a/drivers/thermal/sun8i_thermal.c
++++ b/drivers/thermal/sun8i_thermal.c
+@@ -684,6 +684,20 @@ static const struct ths_thermal_chip sun
+ .calc_temp = sun8i_ths_calc_temp,
+ };
+
++static const struct ths_thermal_chip sun50i_h616_ths = {
++ .sensor_num = 4,
++ .has_bus_clk_reset = true,
++ .needs_sram = true,
++ .ft_deviation = 8000,
++ .offset = 263655,
++ .scale = 810,
++ .temp_data_base = SUN50I_H6_THS_TEMP_DATA,
++ .calibrate = sun50i_h6_ths_calibrate,
++ .init = sun50i_h6_thermal_init,
++ .irq_ack = sun50i_h6_irq_ack,
++ .calc_temp = sun8i_ths_calc_temp,
++};
++
+ static const struct of_device_id of_ths_match[] = {
+ { .compatible = "allwinner,sun8i-a83t-ths", .data = &sun8i_a83t_ths },
+ { .compatible = "allwinner,sun8i-h3-ths", .data = &sun8i_h3_ths },
+@@ -693,6 +707,7 @@ static const struct of_device_id of_ths_
+ { .compatible = "allwinner,sun50i-h5-ths", .data = &sun50i_h5_ths },
+ { .compatible = "allwinner,sun50i-h6-ths", .data = &sun50i_h6_ths },
+ { .compatible = "allwinner,sun20i-d1-ths", .data = &sun20i_d1_ths },
++ { .compatible = "allwinner,sun50i-h616-ths", .data = &sun50i_h616_ths },
+ { /* sentinel */ },
+ };
+ MODULE_DEVICE_TABLE(of, of_ths_match);
--- /dev/null
+From 9ac53d5532cc4bb595bbee86ccba2172ccc336c3 Mon Sep 17 00:00:00 2001
+From: Mark Brown <broonie@kernel.org>
+Date: Tue, 23 Jan 2024 23:33:07 +0000
+Subject: [PATCH] thermal/drivers/sun8i: Don't fail probe due to zone
+ registration failure
+
+Currently the sun8i thermal driver will fail to probe if any of the
+thermal zones it is registering fails to register with the thermal core.
+Since we currently do not define any trip points for the GPU thermal
+zones on at least A64 or H5 this means that we have no thermal support
+on these platforms:
+
+[ 1.698703] thermal_sys: Failed to find 'trips' node
+[ 1.698707] thermal_sys: Failed to find trip points for thermal-sensor id=1
+
+even though the main CPU thermal zone on both SoCs is fully configured.
+This does not seem ideal, while we may not be able to use all the zones
+it seems better to have those zones which are usable be operational.
+Instead just carry on registering zones if we get any non-deferral
+error, allowing use of those zones which are usable.
+
+This means that we also need to update the interrupt handler to not
+attempt to notify the core for events on zones which we have not
+registered, I didn't see an ability to mask individual interrupts and
+I would expect that interrupts would still be indicated in the ISR even
+if they were masked.
+
+Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
+Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20240123-thermal-sun8i-registration-v3-1-3e5771b1bbdd@kernel.org
+---
+ drivers/thermal/sun8i_thermal.c | 16 ++++++++++++++--
+ 1 file changed, 14 insertions(+), 2 deletions(-)
+
+--- a/drivers/thermal/sun8i_thermal.c
++++ b/drivers/thermal/sun8i_thermal.c
+@@ -195,6 +195,9 @@ static irqreturn_t sun8i_irq_thread(int
+ int i;
+
+ for_each_set_bit(i, &irq_bitmap, tmdev->chip->sensor_num) {
++ /* We allow some zones to not register. */
++ if (IS_ERR(tmdev->sensor[i].tzd))
++ continue;
+ thermal_zone_device_update(tmdev->sensor[i].tzd,
+ THERMAL_EVENT_UNSPECIFIED);
+ }
+@@ -531,8 +534,17 @@ static int sun8i_ths_register(struct ths
+ i,
+ &tmdev->sensor[i],
+ &ths_ops);
+- if (IS_ERR(tmdev->sensor[i].tzd))
+- return PTR_ERR(tmdev->sensor[i].tzd);
++
++ /*
++ * If an individual zone fails to register for reasons
++ * other than probe deferral (eg, a bad DT) then carry
++ * on, other zones might register successfully.
++ */
++ if (IS_ERR(tmdev->sensor[i].tzd)) {
++ if (PTR_ERR(tmdev->sensor[i].tzd) == -EPROBE_DEFER)
++ return PTR_ERR(tmdev->sensor[i].tzd);
++ continue;
++ }
+
+ devm_thermal_add_hwmon_sysfs(tmdev->dev, tmdev->sensor[i].tzd);
+ }
--- /dev/null
+From f4318af40544b8e7ff5a6b667ede60e6cf808262 Mon Sep 17 00:00:00 2001
+From: Martin Botka <martin.botka@somainline.org>
+Date: Mon, 19 Feb 2024 15:36:39 +0000
+Subject: [PATCH] arm64: dts: allwinner: h616: Add thermal sensor and zones
+
+There are four thermal sensors:
+- CPU
+- GPU
+- VE
+- DRAM
+
+Add the thermal sensor configuration and the thermal zones.
+
+Signed-off-by: Martin Botka <martin.botka@somainline.org>
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Link: https://lore.kernel.org/r/20240219153639.179814-8-andre.przywara@arm.com
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 88 +++++++++++++++++++
+ 1 file changed, 88 insertions(+)
+
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+@@ -9,6 +9,7 @@
+ #include <dt-bindings/clock/sun6i-rtc.h>
+ #include <dt-bindings/reset/sun50i-h616-ccu.h>
+ #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
++#include <dt-bindings/thermal/thermal.h>
+
+ / {
+ interrupt-parent = <&gic>;
+@@ -138,6 +139,10 @@
+ reg = <0x03006000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
++
++ ths_calibration: thermal-sensor-calibration@14 {
++ reg = <0x14 0x8>;
++ };
+ };
+
+ watchdog: watchdog@30090a0 {
+@@ -511,6 +516,19 @@
+ };
+ };
+
++ ths: thermal-sensor@5070400 {
++ compatible = "allwinner,sun50i-h616-ths";
++ reg = <0x05070400 0x400>;
++ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&ccu CLK_BUS_THS>;
++ clock-names = "bus";
++ resets = <&ccu RST_BUS_THS>;
++ nvmem-cells = <&ths_calibration>;
++ nvmem-cell-names = "calibration";
++ allwinner,sram = <&syscon>;
++ #thermal-sensor-cells = <1>;
++ };
++
+ usbotg: usb@5100000 {
+ compatible = "allwinner,sun50i-h616-musb",
+ "allwinner,sun8i-h3-musb";
+@@ -755,4 +773,74 @@
+ #size-cells = <0>;
+ };
+ };
++
++ thermal-zones {
++ cpu-thermal {
++ polling-delay-passive = <500>;
++ polling-delay = <1000>;
++ thermal-sensors = <&ths 2>;
++ sustainable-power = <1000>;
++
++ trips {
++ cpu_threshold: cpu-trip-0 {
++ temperature = <60000>;
++ type = "passive";
++ hysteresis = <0>;
++ };
++ cpu_target: cpu-trip-1 {
++ temperature = <70000>;
++ type = "passive";
++ hysteresis = <0>;
++ };
++ cpu_critical: cpu-trip-2 {
++ temperature = <110000>;
++ type = "critical";
++ hysteresis = <0>;
++ };
++ };
++ };
++
++ gpu-thermal {
++ polling-delay-passive = <500>;
++ polling-delay = <1000>;
++ thermal-sensors = <&ths 0>;
++ sustainable-power = <1100>;
++
++ trips {
++ gpu_temp_critical: gpu-trip-0 {
++ temperature = <110000>;
++ type = "critical";
++ hysteresis = <0>;
++ };
++ };
++ };
++
++ ve-thermal {
++ polling-delay-passive = <0>;
++ polling-delay = <0>;
++ thermal-sensors = <&ths 1>;
++
++ trips {
++ ve_temp_critical: ve-trip-0 {
++ temperature = <110000>;
++ type = "critical";
++ hysteresis = <0>;
++ };
++ };
++ };
++
++ ddr-thermal {
++ polling-delay-passive = <0>;
++ polling-delay = <0>;
++ thermal-sensors = <&ths 3>;
++
++ trips {
++ ddr_temp_critical: ddr-trip-0 {
++ temperature = <110000>;
++ type = "critical";
++ hysteresis = <0>;
++ };
++ };
++ };
++ };
+ };
--- /dev/null
+From a896bc1d79e3c00f0aacfe225499d811775616f3 Mon Sep 17 00:00:00 2001
+From: Chukun Pan <amadeus@jmu.edu.cn>
+Date: Sun, 10 Oct 2021 21:50:17 +0800
+Subject: [PATCH] arm64: allwinner: add OF node for USB eth on NanoPi R1S H5
+
+This adds the OF node for the USB3 ethernet adapter on the FriendlyARM
+NanoPi R1S H5. Add the correct value for the RTL8153 LED configuration
+register to match the blink behavior of the other port on the device.
+
+Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts
+@@ -116,6 +116,13 @@
+
+ &ehci1 {
+ status = "okay";
++
++ usb-eth@1 {
++ compatible = "realtek,rtl8153";
++ reg = <1>;
++
++ realtek,led-data = <0x78>;
++ };
+ };
+
+ &ehci2 {
--- /dev/null
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
+@@ -60,7 +60,7 @@
+
+ key-sw4 {
+ label = "sw4";
+- linux,code = <BTN_0>;
++ linux,code = <KEY_POWER>;
+ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+ wakeup-source;
+ };
+@@ -221,7 +221,7 @@
+ };
+
+ &usb_otg {
+- dr_mode = "otg";
++ dr_mode = "host";
+ status = "okay";
+ };
+
--- /dev/null
+From 7d87d3dafc4b1ea5659eb71ee6c5fd5308490d1f Mon Sep 17 00:00:00 2001
+From: Oskari Lemmela <oskari@lemmela.net>
+Date: Mon, 31 Dec 2018 07:44:49 +0200
+Subject: [PATCH] arm64: allwinner: a64-sopine: Add Sopine flash partitions.
+
+First 896kB to u-boot. Enough space for SPL, u-boot and ATF.
+Next 128kB to u-boot environment and rest to firmware.
+
+Firmware partition is compatible FIT image dynamic splitting.
+
+Signed-off-by: Oskari Lemmela <oskari@lemmela.net>
+---
+ .../boot/dts/allwinner/sun50i-a64-sopine.dtsi | 22 +++++++++++++++++++
+ 1 file changed, 22 insertions(+)
+
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi
+@@ -58,6 +58,28 @@
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
++
++ partitions {
++ compatible = "fixed-partitions";
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ partition@0 {
++ label = "u-boot";
++ reg = <0x000000 0x0E0000>;
++ };
++
++ partition@e0000 {
++ label = "u-boot-env";
++ reg = <0x0E0000 0x020000>;
++ };
++
++ partition@100000 {
++ compatible = "denx,fit";
++ label = "firmware";
++ reg = <0x100000 0xF00000>;
++ };
++ };
+ };
+ };
+
--- /dev/null
+--- a/arch/arm/boot/dts/allwinner/Makefile
++++ b/arch/arm/boot/dts/allwinner/Makefile
+@@ -280,6 +280,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
+ sun8i-a83t-cubietruck-plus.dtb \
+ sun8i-a83t-tbs-a711.dtb \
+ sun8i-h2-plus-bananapi-m2-zero.dtb \
++ sun8i-h2-plus-bananapi-p2-zero.dtb \
+ sun8i-h2-plus-libretech-all-h3-cc.dtb \
+ sun8i-h2-plus-orangepi-r1.dtb \
+ sun8i-h2-plus-orangepi-zero.dtb \
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-bananapi-p2-zero.dts
+@@ -0,0 +1,279 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (C) 2023 Zoltan HERPAI <wigyori@uid0.hu>
++ *
++ * Based on sun8i-h2-plus-bananapi-m2-zero.dts, which is:
++ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
++ */
++
++/dts-v1/;
++#include "sun8i-h3.dtsi"
++#include "sunxi-common-regulators.dtsi"
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++
++/ {
++ model = "Banana Pi BPI-P2-Zero";
++ compatible = "sinovoip,bpi-p2-zero", "allwinner,sun8i-h2-plus";
++
++ aliases {
++ serial0 = &uart0;
++ serial1 = &uart1;
++ };
++
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++
++ connector {
++ compatible = "hdmi-connector";
++ type = "c";
++
++ port {
++ hdmi_con_in: endpoint {
++ remote-endpoint = <&hdmi_out_con>;
++ };
++ };
++ };
++
++ leds {
++ compatible = "gpio-leds";
++
++ pwr_led {
++ label = "bananapi-p2-zero:red:pwr";
++ gpios = <&r_pio 0 10 GPIO_ACTIVE_LOW>; /* PL10 */
++ default-state = "on";
++ };
++ };
++
++ gpio_keys {
++ compatible = "gpio-keys";
++
++ sw4 {
++ label = "power";
++ linux,code = <BTN_0>;
++ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
++ };
++ };
++
++ reg_vdd_cpux: vdd-cpux-regulator {
++ compatible = "regulator-gpio";
++ regulator-name = "vdd-cpux";
++ regulator-type = "voltage";
++ regulator-boot-on;
++ regulator-always-on;
++ regulator-min-microvolt = <1100000>;
++ regulator-max-microvolt = <1300000>;
++ regulator-ramp-delay = <50>; /* 4ms */
++
++ gpios = <&r_pio 0 1 GPIO_ACTIVE_HIGH>; /* PL1 */
++ enable-active-high;
++ gpios-states = <0x1>;
++ states = <1100000 0>, <1300000 1>;
++ };
++
++ reg_vcc_dram: vcc-dram {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc-dram";
++ regulator-min-microvolt = <1500000>;
++ regulator-max-microvolt = <1500000>;
++ regulator-always-on;
++ regulator-boot-on;
++ enable-active-high;
++ gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */
++ vin-supply = <®_vcc5v0>;
++ };
++
++ reg_vcc1v2: vcc1v2 {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc1v2";
++ regulator-min-microvolt = <1200000>;
++ regulator-max-microvolt = <1200000>;
++ regulator-always-on;
++ regulator-boot-on;
++ enable-active-high;
++ gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
++ vin-supply = <®_vcc5v0>;
++ };
++
++ poweroff {
++ compatible = "regulator-poweroff";
++ cpu-supply = <®_vcc1v2>;
++ };
++
++ wifi_pwrseq: wifi_pwrseq {
++ compatible = "mmc-pwrseq-simple";
++ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
++ clocks = <&rtc 1>;
++ clock-names = "ext_clock";
++ };
++};
++
++&cpu0 {
++ cpu-supply = <®_vdd_cpux>;
++};
++
++&de {
++ status = "okay";
++};
++
++&ehci0 {
++ status = "okay";
++};
++
++&emac {
++ phy-handle = <&int_mii_phy>;
++ phy-mode = "mii";
++ allwinner,leds-active-low;
++ status = "okay";
++};
++
++&hdmi {
++ status = "okay";
++};
++
++&hdmi_out {
++ hdmi_out_con: endpoint {
++ remote-endpoint = <&hdmi_con_in>;
++ };
++};
++
++&mmc0 {
++ vmmc-supply = <®_vcc3v3>;
++ bus-width = <4>;
++ /*
++ * On the production batch of this board the card detect GPIO is
++ * high active (card inserted), although on the early samples it's
++ * low active.
++ */
++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
++ status = "okay";
++};
++
++&mmc1 {
++ vmmc-supply = <®_vcc3v3>;
++ vqmmc-supply = <®_vcc3v3>;
++ mmc-pwrseq = <&wifi_pwrseq>;
++ bus-width = <4>;
++ non-removable;
++ status = "okay";
++
++ brcmf: wifi@1 {
++ reg = <1>;
++ compatible = "brcm,bcm4329-fmac";
++ interrupt-parent = <&pio>;
++ interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */
++ interrupt-names = "host-wake";
++ };
++};
++
++&ohci0 {
++ status = "okay";
++};
++
++&uart0 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&uart0_pa_pins>;
++ status = "okay";
++};
++
++&uart1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
++ uart-has-rtscts;
++ status = "okay";
++
++ bluetooth {
++ compatible = "brcm,bcm43438-bt";
++ max-speed = <1500000>;
++ clocks = <&rtc 1>;
++ clock-names = "lpo";
++ vbat-supply = <®_vcc3v3>;
++ vddio-supply = <®_vcc3v3>;
++ device-wakeup-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */
++ host-wakeup-gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; /* PG11 */
++ shutdown-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
++ };
++
++};
++
++&pio {
++ gpio-line-names =
++ /* PA */
++ "CON2-P13", "CON2-P11", "CON2-P22", "CON2-P15",
++ "CON3-P03", "CON3-P02", "CON2-P07", "CON2-P29",
++ "CON2-P31", "CON2-P33", "CON2-P35", "CON2-P05",
++ "CON2-P03", "CON2-P08", "CON2-P10", "CON2-P16",
++ "CON2-P12", "CON2-P37", "CON2-P28", "CON2-P27",
++ "CON2-P40", "CON2-P38", "", "",
++ "", "", "", "", "", "", "", "",
++
++ /* PB */
++ "", "", "", "", "", "", "", "",
++ "", "", "", "", "", "", "", "",
++ "", "", "", "", "", "", "", "",
++ "", "", "", "", "", "", "", "",
++
++ /* PC */
++ "CON2-P19", "CON2-P21", "CON2-P23", "CON2-P24",
++ "CON2-P18", "", "", "CON2-P26",
++ "", "", "", "", "", "", "", "",
++ "", "", "", "", "", "", "", "",
++ "", "", "", "", "", "", "", "",
++
++ /* PD */
++ "", "", "", "", "", "", "", "",
++ "", "", "", "", "", "", "CSI-PWR-EN", "",
++ "", "", "", "", "", "", "", "",
++ "", "", "", "", "", "", "", "",
++
++ /* PE */
++ "CN3-P17", "CN3-P13", "CN3-P09", "CN3-P07",
++ "CN3-P19", "CN3-P21", "CN3-P22", "CN3-P20",
++ "CN3-P18", "CN3-P16", "CN3-P14", "CN3-P12",
++ "CN3-P05", "CN3-P03", "CN3-P06", "CN3-P08",
++ "", "", "", "", "", "", "", "",
++ "", "", "", "", "", "", "", "",
++
++ /* PF */
++ "SDC0-D1", "SDC0-D0", "SDC0-CLK", "SDC0-CMD", "SDC0-D3",
++ "SDC0-D2", "SDC0-DET", "",
++ "", "", "", "", "", "", "", "",
++ "", "", "", "", "", "", "", "",
++ "", "", "", "", "", "", "", "",
++
++ /* PG */
++ "WL-SDIO-CLK", "WL-SDIO-CMD", "WL-SDIO-D0", "WL-SDIO-D1",
++ "WL-SDIO-D2", "WL-SDIO-D3", "BT-UART-TX", "BT-UART-RX",
++ "BT-UART-RTS", "BT-UART-CTS", "WL-WAKE-AP", "BT-WAKE-AP",
++ "BT-RST-N", "AP-WAKE-BT", "", "",
++ "", "", "", "", "", "", "", "",
++ "", "", "", "", "", "", "", "";
++};
++
++&r_pio {
++ gpio-line-names =
++ /* PL */
++ "", "CPUX-SET", "CON2-P32", "POWER-KEY", "CON2-P36",
++ "VCC-IO-EN", "USB0-ID", "WL-PWR-EN",
++ "PWR-STB", "PWR-DRAM", "PWR-LED", "IR-RX", "", "", "", "",
++ "", "", "", "", "", "", "", "",
++ "", "", "", "", "", "", "", "";
++};
++
++&usb_otg {
++ dr_mode = "otg";
++ status = "okay";
++};
++
++&usbphy {
++ usb0_id_det-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
++ /*
++ * There're two micro-USB connectors, one is power-only and another is
++ * OTG. The Vbus of these two connectors are connected together, so
++ * the external USB device will be powered just by the power input
++ * from the power-only USB port.
++ */
++ status = "okay";
++};
--- /dev/null
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Petr=20=C5=A0tetiar?= <ynezz@true.cz>
+Date: Thu, 26 Mar 2020 10:09:19 +0100
+Subject: [PATCH] arm64: dts: allwinner: a64: olinuxino: add status LED aliases
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Petr Štetiar <ynezz@true.cz>
+
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
+@@ -15,6 +15,10 @@
+ aliases {
+ ethernet0 = &emac;
+ serial0 = &uart0;
++ led-boot = &led_user;
++ led-failsafe = &led_user;
++ led-running = &led_user;
++ led-upgrade = &led_user;
+ };
+
+ chosen {
+@@ -35,7 +39,7 @@
+ leds {
+ compatible = "gpio-leds";
+
+- led-0 {
++ led_user: led-0 {
+ label = "a64-olinuxino:red:user";
+ gpios = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */
+ };
--- /dev/null
+From 1845163a052efac124f00656eb72f38947630a42 Mon Sep 17 00:00:00 2001
+From: Chukun Pan <amadeus@jmu.edu.cn>
+Date: Sun, 10 Oct 2021 21:50:18 +0800
+Subject: [PATCH] arm64: dts: allwinner: NanoPi R1S H5: add status LED aliases
+
+Use the SYS LED on the casing for showing system status.
+
+Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts
+@@ -23,6 +23,11 @@
+ ethernet0 = &emac;
+ ethernet1 = &rtl8189etv;
+ serial0 = &uart0;
++
++ led-boot = &led_sys;
++ led-failsafe = &led_sys;
++ led-running = &led_sys;
++ led-upgrade = &led_sys;
+ };
+
+ chosen {
+@@ -38,7 +43,7 @@
+ gpios = <&pio 0 9 GPIO_ACTIVE_HIGH>;
+ };
+
+- led-1 {
++ led_sys: led-1 {
+ function = LED_FUNCTION_STATUS;
+ color = <LED_COLOR_ID_RED>;
+ gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>;
--- /dev/null
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts
+@@ -41,3 +41,7 @@
+ reg = <1>;
+ };
+ };
++
++&pwm {
++ status = "okay";
++};
--- /dev/null
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
+@@ -42,6 +42,11 @@
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
++
++ wifi_pwrseq: wifi_pwrseq {
++ compatible = "mmc-pwrseq-simple";
++ reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
++ };
+ };
+
+ &ac_power_supply {
+@@ -102,6 +107,21 @@
+ reg = <1>;
+ };
+ };
++
++&mmc1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&mmc1_pins>;
++ vmmc-supply = <®_dldo4>;
++ vqmmc-supply = <®_eldo1>;
++ mmc-pwrseq = <&wifi_pwrseq>;
++ bus-width = <4>;
++ non-removable;
++ status = "okay";
++
++ rtl8723cs: wifi@1 {
++ reg = <1>;
++ };
++};
+
+ &mmc2 {
+ pinctrl-names = "default";
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+@@ -35,6 +35,11 @@
+ };
+ };
+ };
++
++ wifi_pwrseq: wifi_pwrseq {
++ compatible = "mmc-pwrseq-simple";
++ reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
++ };
+ };
+
+ &codec {
+@@ -124,6 +129,21 @@
+ status = "okay";
+ };
+
++&mmc1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&mmc1_pins>;
++ vmmc-supply = <®_dldo4>;
++ vqmmc-supply = <®_eldo1>;
++ mmc-pwrseq = <&wifi_pwrseq>;
++ bus-width = <4>;
++ non-removable;
++ status = "okay";
++
++ rtl8723cs: wifi@1 {
++ reg = <1>;
++ };
++};
++
+ &ohci0 {
+ status = "okay";
+ };
CONFIG_MICROCODE_LATE_LOADING=y
CONFIG_MIGRATION=y
CONFIG_MITIGATION_RFDS=y
+CONFIG_MITIGATION_SPECTRE_BHI=y
# CONFIG_MK6 is not set
# CONFIG_MK7 is not set
# CONFIG_MK8 is not set
CONFIG_SOFTIRQ_ON_OWN_STACK=y
CONFIG_SPARSEMEM_STATIC=y
CONFIG_SPARSE_IRQ=y
-# CONFIG_SPECTRE_BHI_AUTO is not set
-# CONFIG_SPECTRE_BHI_OFF is not set
-CONFIG_SPECTRE_BHI_ON=y
CONFIG_SPECULATION_MITIGATIONS=y
CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
# CONFIG_STATIC_CALL_SELFTEST is not set
endef
KERNEL_PATCHVER:=5.15
+KERNEL_TESTING_PATCHVER:=6.1
include $(INCLUDE_DIR)/target.mk
--- /dev/null
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_ALTERA_FREEZE_BRIDGE is not set
+# CONFIG_ALTERA_PR_IP_CORE is not set
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MULTIPLATFORM=y
+CONFIG_ARCH_MULTI_V6_V7=y
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_ARCH_NR_GPIO=1024
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_VEXPRESS=y
+CONFIG_ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA=y
+# CONFIG_ARCH_VEXPRESS_SPC is not set
+CONFIG_ARCH_ZYNQ=y
+CONFIG_ARM=y
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_CPU_SUSPEND=y
+CONFIG_ARM_ERRATA_643719=y
+CONFIG_ARM_ERRATA_720789=y
+CONFIG_ARM_ERRATA_754322=y
+CONFIG_ARM_ERRATA_754327=y
+CONFIG_ARM_ERRATA_764369=y
+CONFIG_ARM_ERRATA_775420=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_GLOBAL_TIMER=y
+CONFIG_ARM_GT_INITIAL_PRESCALER_VAL=2
+CONFIG_ARM_HAS_GROUP_RELOCS=y
+CONFIG_ARM_HEAVY_MB=y
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+CONFIG_ARM_PATCH_IDIV=y
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+# CONFIG_ARM_PL172_MPMC is not set
+# CONFIG_ARM_SMMU is not set
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_TIMER_SP804=y
+CONFIG_ARM_UNWIND=y
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_ARM_ZYNQ_CPUIDLE=y
+CONFIG_ATAGS=y
+CONFIG_AUTO_ZRELADDR=y
+# CONFIG_AXI_DMAC is not set
+CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_PM=y
+CONFIG_BOUNCE=y
+CONFIG_CACHE_L2X0=y
+CONFIG_CADENCE_TTC_TIMER=y
+CONFIG_CADENCE_WATCHDOG=y
+CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLKSRC_VERSATILE=y
+CONFIG_CLK_ICST=y
+CONFIG_CLK_SP810=y
+CONFIG_CLK_VEXPRESS_OSC=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMA=y
+CONFIG_CMA_ALIGNMENT=8
+CONFIG_CMA_AREAS=7
+# CONFIG_CMA_DEBUG is not set
+# CONFIG_CMA_DEBUGFS is not set
+CONFIG_CMA_SIZE_MBYTES=16
+# CONFIG_CMA_SIZE_SEL_MAX is not set
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+# CONFIG_CMA_SIZE_SEL_MIN is not set
+# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
+# CONFIG_CMA_SYSFS is not set
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_SI570=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONNECTOR=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CONTIG_ALLOC=y
+CONFIG_COREDUMP=y
+# CONFIG_CPUFREQ_DT is not set
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_FREQ=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_SPECTRE=y
+CONFIG_CPU_THERMAL=y
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_V7=y
+CONFIG_CRC16=y
+# CONFIG_CRC32_SARWATE is not set
+CONFIG_CRC32_SLICEBY8=y
+CONFIG_CROSS_MEMORY_ATTACH=y
+CONFIG_CRYPTO_CRC32=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+CONFIG_DMADEVICES=y
+CONFIG_DMA_CMA=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_OPS=y
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_DRM=y
+CONFIG_DRM_BRIDGE=y
+CONFIG_DRM_NOMODESET=y
+CONFIG_DRM_PANEL=y
+CONFIG_DRM_PANEL_BRIDGE=y
+CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
+CONFIG_DTC=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_E1000E=y
+CONFIG_EDAC=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+# CONFIG_EDAC_DEBUG is not set
+CONFIG_EDAC_LEGACY_SYSFS=y
+CONFIG_EDAC_SUPPORT=y
+# CONFIG_EDAC_SYNOPSYS is not set
+CONFIG_EEPROM_AT24=y
+CONFIG_EEPROM_AT25=y
+CONFIG_ELF_CORE=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_EXT4_FS=y
+CONFIG_EXTCON=y
+CONFIG_F2FS_FS=y
+CONFIG_FB=y
+CONFIG_FB_CMDLINE=y
+# CONFIG_FB_XILINX is not set
+CONFIG_FHANDLE=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FPGA=y
+CONFIG_FPGA_BRIDGE=y
+# CONFIG_FPGA_DFL is not set
+# CONFIG_FPGA_MGR_ALTERA_CVP is not set
+# CONFIG_FPGA_MGR_ALTERA_PS_SPI is not set
+# CONFIG_FPGA_MGR_ICE40_SPI is not set
+# CONFIG_FPGA_MGR_MACHXO2_SPI is not set
+# CONFIG_FPGA_MGR_MICROCHIP_SPI is not set
+# CONFIG_FPGA_MGR_XILINX_SPI is not set
+CONFIG_FPGA_MGR_ZYNQ_FPGA=y
+CONFIG_FPGA_REGION=y
+CONFIG_FREEZER=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_CACHE=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC10_NO_ARRAY_BOUNDS=y
+CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_VDSO_32=y
+CONFIG_GLOB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_GPIO_ZYNQ=y
+CONFIG_HARDEN_BRANCH_PREDICTOR=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAVE_SMP=y
+CONFIG_HDMI=y
+CONFIG_HID=y
+CONFIG_HID_GENERIC=y
+CONFIG_HID_MICROSOFT=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGHPTE=y
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HWMON=y
+CONFIG_HW_CONSOLE=y
+CONFIG_HZ_FIXED=0
+CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CADENCE=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_IIO=y
+CONFIG_IIO_BUFFER=y
+CONFIG_IIO_KFIFO_BUF=y
+CONFIG_IIO_TRIGGER=y
+CONFIG_IIO_TRIGGERED_BUFFER=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INPUT=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_FF_MEMLESS=y
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_INPUT_MOUSE=y
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+CONFIG_INPUT_SPARSEKMAP=y
+CONFIG_INPUT_VIVALDIFMAP=y
+# CONFIG_IOMMU_DEBUGFS is not set
+# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
+# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
+CONFIG_IOMMU_SUPPORT=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQSTACKS=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+# CONFIG_ISDN is not set
+CONFIG_JBD2=y
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+CONFIG_KCMP=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_XZ is not set
+CONFIG_KEYBOARD_ATKBD=y
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_GPIO_POLLED=y
+CONFIG_KMAP_LOCAL=y
+CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+CONFIG_LEDS_TRIGGER_CAMERA=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_TRANSIENT=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_MACB=y
+# CONFIG_MACB_PCI is not set
+CONFIG_MACB_USE_HWSTAMP=y
+CONFIG_MARVELL_PHY=y
+CONFIG_MDIO_BITBANG=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+# CONFIG_MDIO_GPIO is not set
+CONFIG_MEMFD_CREATE=y
+CONFIG_MEMORY=y
+CONFIG_MEMORY_ISOLATION=y
+CONFIG_MFD_CORE=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MFD_VEXPRESS_SYSREG=y
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_CQHCI=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_OF_ARASAN=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MODULE_STRIPPED is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_CYAPA is not set
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_BYD=y
+CONFIG_MOUSE_PS2_CYPRESS=y
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+CONFIG_MOUSE_PS2_FOCALTECH=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SMBUS=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+# CONFIG_MTD_SPLIT_SQUASHFS_ROOT is not set
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEON=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_SELFTESTS=y
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_VIA is not set
+CONFIG_NLS=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_NO_HZ=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NO_IOPORT_MAP=y
+CONFIG_NR_CPUS=4
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_NVMEM_SYSFS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+# CONFIG_OF_FPGA_REGION is not set
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_OUTER_CACHE=y
+CONFIG_OUTER_CACHE_SYNC=y
+CONFIG_PADATA=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_PCI=y
+CONFIG_PCIE_XILINX=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_MSI_IRQ_DOMAIN=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+CONFIG_PHYLINK=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PINCTRL_ZYNQ=y
+CONFIG_PL310_ERRATA_588369=y
+CONFIG_PL310_ERRATA_727915=y
+CONFIG_PL310_ERRATA_753970=y
+CONFIG_PL310_ERRATA_769419=y
+CONFIG_PL330_DMA=y
+# CONFIG_PL353_SMC is not set
+CONFIG_PLAT_VERSATILE=y
+CONFIG_PM=y
+CONFIG_PMBUS=y
+CONFIG_PM_CLK=y
+CONFIG_PM_SLEEP=y
+CONFIG_PM_SLEEP_SMP=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_VEXPRESS=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PPS=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PROC_EVENTS=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_R8169=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+CONFIG_REALTEK_PHY=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+# CONFIG_REGULATOR_VEXPRESS is not set
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RESET_ZYNQ=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_PCF8563=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RTC_MC146818_LIB=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+# CONFIG_SCHED_CORE is not set
+CONFIG_SCHED_MC=y
+CONFIG_SCHED_SMT=y
+CONFIG_SENSORS_PMBUS=y
+CONFIG_SENSORS_UCD9000=y
+CONFIG_SENSORS_UCD9200=y
+# CONFIG_SERIAL_8250 is not set
+CONFIG_SERIAL_XILINX_PS_UART=y
+CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
+CONFIG_SERIO=y
+CONFIG_SERIO_LIBPS2=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SMP=y
+CONFIG_SMP_ON_UP=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SOC_BUS=y
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_CADENCE=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SPI_XILINX=y
+CONFIG_SPI_ZYNQ_QSPI=y
+CONFIG_SRAM=y
+CONFIG_SRAM_EXEC=y
+CONFIG_SRCU=y
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_SWPHY=y
+CONFIG_SWP_EMULATE=y
+CONFIG_SYNC_FILE=y
+CONFIG_SYSFS_SYSCALL=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+# CONFIG_TEXTSEARCH is not set
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_OF=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UIO=y
+# CONFIG_UIO_AEC is not set
+# CONFIG_UIO_CIF is not set
+# CONFIG_UIO_DMEM_GENIRQ is not set
+# CONFIG_UIO_MF624 is not set
+# CONFIG_UIO_NETX is not set
+# CONFIG_UIO_PCI_GENERIC is not set
+CONFIG_UIO_PDRV_GENIRQ=y
+# CONFIG_UIO_PRUSS is not set
+# CONFIG_UIO_SERCOS3 is not set
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNWINDER_ARM=y
+CONFIG_USB=y
+CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_CHIPIDEA_UDC=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_HCD_PLATFORM is not set
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_XILINX=y
+CONFIG_USB_HID=y
+CONFIG_USB_NET_DRIVERS=y
+CONFIG_USB_OTG=y
+CONFIG_USB_OTG_FSM=y
+CONFIG_USB_PHY=y
+CONFIG_USB_ROLE_SWITCH=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_BUS=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USE_OF=y
+CONFIG_VEXPRESS_CONFIG=y
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_VGA_ARB=y
+CONFIG_VGA_ARB_MAX_GPUS=16
+CONFIG_VITESSE_PHY=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_CONSOLE_SLEEP=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_WATCHDOG_CORE=y
+# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
+CONFIG_XILINX_EMACLITE=y
+# CONFIG_XILINX_PR_DECOUPLER is not set
+CONFIG_XILINX_WATCHDOG=y
+CONFIG_XILINX_XADC=y
+CONFIG_XPS=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_XZ_DEC_IA64=y
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_SPARC=y
+CONFIG_XZ_DEC_X86=y
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
choice
prompt "Binutils Version" if TOOLCHAINOPTS
- default BINUTILS_USE_VERSION_2_40
+ default BINUTILS_USE_VERSION_2_42
help
Select the version of binutils you wish to use.
bool
config BINUTILS_VERSION_2_40
- default y if !TOOLCHAINOPTS
bool
config BINUTILS_VERSION_2_41
bool
config BINUTILS_VERSION_2_42
+ default y if !TOOLCHAINOPTS
bool
config BINUTILS_VERSION
include $(TOPDIR)/rules.mk
PKG_NAME:=glibc
-PKG_VERSION:=2.37
+PKG_VERSION:=2.38
PKG_RELEASE:=1
PKG_SOURCE_PROTO:=git
PKG_SOURCE_SUBDIR:=$(PKG_NAME)-$(PKG_VERSION)
-PKG_SOURCE_VERSION:=eee7525d35ec16bbe81435e41079ab72519d825c
-PKG_MIRROR_HASH:=fad5a67d9622b75bce5e3e8c91b07a6df0bf8b21cb001a6d06019a6ce4cff31f
+PKG_SOURCE_VERSION:=cfe121910013a46e2477562282c56ae8062089aa
+PKG_MIRROR_HASH:=99b9beb283d644caacea12fe87dd7f0a0141ff26349ee500a78047aba3f5be5c
PKG_SOURCE_URL:=https://sourceware.org/git/glibc.git
-PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION)-$(PKG_SOURCE_VERSION).tar.xz
+PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION)-$(PKG_SOURCE_VERSION).tar.zst
PKG_CPE_ID:=cpe:/a:gnu:glibc
HOST_BUILD_DIR:=$(BUILD_DIR_TOOLCHAIN)/$(PKG_SOURCE_SUBDIR)
--without-gd \
--without-cvs \
--enable-add-ons \
+ --enable-crypt \
--$(if $(CONFIG_SOFT_FLOAT),without,with)-fp \
$(if $(CONFIG_PKG_CC_STACKPROTECTOR_REGULAR),--enable-stack-protector=yes) \
$(if $(CONFIG_PKG_CC_STACKPROTECTOR_STRONG),--enable-stack-protector=strong) \
$(if $(CONFIG_PKG_CC_STACKPROTECTOR_ALL),--enable-stack-protector=all) \
$(if $(CONFIG_PKG_RELRO_FULL),--enable-bind-now) \
+ $(if $(CONFIG_PKG_FORTIFY_SOURCE_1),--enable-fortify-source=1) \
+ $(if $(CONFIG_PKG_FORTIFY_SOURCE_2),--enable-fortify-source=2) \
--enable-kernel=5.15.0
export libc_cv_ssp=no
int totfails = 0;
int main (int argc, char *argv[]);
-@@ -119,13 +103,3 @@ put8 (char *cp)
+@@ -123,13 +107,3 @@ put8 (char *cp)
printf("%02x", t);
}
}
* Encode Binary Data:: Encoding and Decoding of Binary Data.
* Argz and Envz Vectors:: Null-separated string vectors.
@end menu
-@@ -2423,73 +2423,73 @@ functionality under a different name, su
+@@ -2512,73 +2512,73 @@ functionality under a different name, su
systems it may be in @file{strings.h} instead.
@end deftypefun
range [FROM - N + 1, FROM - 1]. If N is odd the first byte in FROM
--- a/stdlib/stdlib.h
+++ b/stdlib/stdlib.h
-@@ -984,6 +984,12 @@ extern int getsubopt (char **__restrict
+@@ -1103,6 +1103,12 @@ extern int getsubopt (char **__restrict
#endif
--- a/Makeconfig
+++ b/Makeconfig
-@@ -631,6 +631,9 @@ else
+@@ -632,6 +632,9 @@ else
default-rpath = $(libdir)
endif
PKG_SOURCE_URL:=https://www.nasm.us/pub/nasm/releasebuilds/$(PKG_VERSION)/
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
PKG_HASH:=c77745f4802375efeee2ec5c0ad6b7f037ea9c87c92b149a9637ff099f162558
-PKG_CPE_ID:=cpe:/a:nasm:nasm
+PKG_CPE_ID:=cpe:/a:nasm:netwide_assembler
HOST_BUILD_PARALLEL:=1
endef
+define Host/SetToolchainInfo
+ if [ -f $(CONFIG_TOOLCHAIN_ROOT)/info.mk ]; then \
+ $(CP) $(CONFIG_TOOLCHAIN_ROOT)/info.mk $(TOOLCHAIN_DIR)/; \
+ else \
+ $(SED) 's,GCC_VERSION=.*,GCC_VERSION=$(CONFIG_GCC_VERSION),' $(TOOLCHAIN_DIR)/info.mk; \
+ fi
+endef
+
define Host/Prepare
$(call toolchain_test,CONFIG_SOFT_FLOAT,softfloat)
$(call toolchain_test,CONFIG_IPV6,ipv6)
define Host/Install
$(call toolchain_util,--wrap "$(TOOLCHAIN_DIR)/bin")
+ $(call Host/SetToolchainInfo)
endef
define Host/Clean
rm -rf $(TOOLCHAIN_DIR)/bin
+ rm -rf $(TOOLCHAIN_DIR)/info.mk
endef
$(eval $(call HostBuild))
--- /dev/null
+--- a/src/files.c
++++ b/src/files.c
+@@ -560,9 +560,9 @@ pkgdatadir (void)
+ char const *
+ m4path (void)
+ {
+- char const *m4 = getenv ("M4");
++ char const *m4 = getenv ("STAGING_DIR_HOST");
+ if (m4)
+- return m4;
++ return strcat(getenv ("STAGING_DIR_HOST"), "/bin/m4");
+
+ /* We don't use relocate2() to store the temporary buffer and re-use
+ it, because m4path() is only called once. */
+--- a/src/getargs.c
++++ b/src/getargs.c
+@@ -373,11 +373,13 @@ usage (int status)
+ A --long option is required.
+ Otherwise, add exceptions to ../build-aux/cross-options.pl. */
+
+- printf (_("Usage: %s [OPTION]... FILE\n"), program_name);
++ printf (_("Usage: STAGING_DIR_HOST=... %s [OPTION]... FILE\n"), program_name);
+ fputs (_("\
+ Generate a deterministic LR or generalized LR (GLR) parser employing\n\
+ LALR(1), IELR(1), or canonical LR(1) parser tables.\n\
+ \n\
++Environment Variable STAGING_DIR_HOST controls path to m4\n\
++\n\
+ "), stdout);
+
+ fputs (_("\
+@@ -450,6 +452,11 @@ Output Files:\n\
+ -M, --file-prefix-map=OLD=NEW replace prefix OLD with NEW when writing file paths\n\
+ in output files\n\
+ "), stdout);
++
++ fputs (_("\
++Environment Variables:\n\
++ STAGING_DIR_HOST Path to m4 is [STAGING_DIR_HOST]/bin/m4\n\
++"), stdout);
+ putc ('\n', stdout);
+
+ argmatch_report_usage (stdout);
PKG_NAME:=coreutils
PKG_CPE_ID:=cpe:/a:gnu:coreutils
-PKG_VERSION:=9.3
+PKG_VERSION:=9.5
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
PKG_SOURCE_URL:=@GNU/coreutils
-PKG_HASH:=a33d2c0bc49be3c79a4794944dcd87103bf497b53a14bafcd431c8ca53975252
+PKG_HASH:=767ae6a22950ec42f3ba5f7c1de79dd27800ee8e9b8642da5dedb5974a1741e5
HOST_BUILD_PARALLEL := 1
export GNULIB_SRCDIR:=$(HOST_GNULIB_SRCDIR)
+HOST_GNULIB_SKIP := \
+ lib/nstrftime.c \
+ lib/fprintftime.c \
+ lib/locale.in.h
+
HOST_CONFIGURE_ARGS += \
+ --disable-year2038 \
--enable-install-program=$(subst $(space),$(comma),$(strip $(PKG_PROGRAMS)))
HOST_MAKE_FLAGS += \
define Host/Configure
$(if $(QUILT),$(call Host/Bootstrap))
- -$(CP) $(HOST_BUILD_DIR)/lib/time.in.h~ $(HOST_BUILD_DIR)/lib/time.in.h # @GNULIB_TIME@ not defined
+ $(foreach src,$(HOST_GNULIB_SKIP),mv -f $(HOST_BUILD_DIR)/$(src)~ $(HOST_BUILD_DIR)/$(src) || true; )
$(call Host/Configure/Default)
endef
--- a/bootstrap
+++ b/bootstrap
-@@ -278,7 +278,7 @@ check_exists() {
+@@ -244,7 +244,7 @@ check_exists() {
($2 --version </dev/null)
fi
else
fi
test $? -lt 126
-@@ -563,7 +563,7 @@ p
+@@ -309,7 +309,7 @@ p
q'
get_version() {
$app --version >/dev/null 2>&1 || { $app --version; return 1; }
-@@ -620,13 +620,13 @@ check_versions() {
+@@ -366,13 +366,13 @@ check_versions() {
if [ "$req_ver" = "-" ]; then
# Merely require app to exist; not all prereq apps are well-behaved
# so we have to rely on $? rather than get_version.
if [ ! "$inst_ver" ]; then
warn_ "Error: '$app' not found"
ret=1
-@@ -923,7 +923,7 @@ version_controlled_file() {
- # two just-pre-run programs.
+@@ -1157,7 +1157,7 @@ autogen()
+ # two just-pre-run programs.
- # Import from gettext.
--with_gettext=yes
-+with_gettext=no
- grep '^[ ]*AM_GNU_GETTEXT_VERSION(' configure.ac >/dev/null || \
- with_gettext=no
+ # Import from gettext.
+- with_gettext=yes
++ with_gettext=no
+ grep '^[ ]*AM_GNU_GETTEXT_VERSION(' configure.ac >/dev/null || \
+ with_gettext=no
include $(TOPDIR)/rules.mk
PKG_NAME:=elfutils
-PKG_VERSION:=0.189
-PKG_RELEASE:=1
+PKG_VERSION:=0.191
+PKG_RELEASE:=2
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
PKG_SOURCE_URL:=https://sourceware.org/$(PKG_NAME)/ftp/$(PKG_VERSION)
-PKG_HASH:=39bd8f1a338e2b7cd4abc3ff11a0eddc6e690f69578a57478d8179b4148708c8
+PKG_HASH:=df76db71366d1d708365fc7a6c60ca48398f14367eb2b8954efc8897147ad871
PKG_LICENSE:=GPL-3.0-or-later
PKG_LICENSE_FILES:=COPYING COPYING-GPLV2 COPYING-LGPLV3
PKG_FIXUP:=autoreconf
PKG_INSTALL:=1
+PKG_SUBDIRS := \
+ libgnu \
+ config \
+ lib \
+ libelf \
+ libcpu \
+ backends \
+ libebl \
+ libdwelf \
+ libdwfl \
+ libdw
+
+PKG_GNULIB_BASE:=libgnu
+
+PKG_GNULIB_ARGS = \
+ --dir=$(HOST_BUILD_DIR) \
+ --local-dir=$(STAGING_DIR_HOST)/share/gnulib \
+ --source-base=$(PKG_GNULIB_BASE) \
+ --libtool \
+ --avoid=reallocarray \
+ --import
+
+PKG_GNULIB_MODS = \
+ argp \
+ fts \
+ obstack \
+ progname \
+ strchrnul \
+ tsearch
+
include $(INCLUDE_DIR)/host-build.mk
ifeq ($(HOST_OS),Darwin)
Hooks/HostConfigure/Pre := Host/Gnulib $(Hooks/HostConfigure/Pre)
define Host/Gnulib
- cd $(HOST_BUILD_DIR); $(STAGING_DIR_HOST)/bin/gnulib-tool --libtool --source-base=libgnu --import argp obstack fts strchrnul progname tsearch;
+ $(STAGING_DIR_HOST)/bin/gnulib-tool $(PKG_GNULIB_ARGS) $(PKG_GNULIB_MODS);
ln -sf ../lib/eu-config.h $(HOST_BUILD_DIR)/libgnu/;
endef
+define Host/Compile
+ $(call Host/Compile/Default,SUBDIRS='$$$$(wildcard $(PKG_SUBDIRS))')
+endef
+
+define Host/Install
+ $(call Host/Compile/Default,install SUBDIRS='$$$$(wildcard $(PKG_SUBDIRS))')
+endef
+
define Host/Uninstall
-$(call Host/Compile/Default,uninstall)
endef
+++ b/configure.ac
@@ -20,6 +20,7 @@ dnl You should have received a copy of
dnl along with this program. If not, see <http://www.gnu.org/licenses/>.
- AC_INIT([elfutils],[0.189],[https://sourceware.org/bugzilla],[elfutils],[http://elfutils.org/])
+ AC_INIT([elfutils],[0.191],[https://sourceware.org/bugzilla],[elfutils],[http://elfutils.org/])
+AC_CONFIG_MACRO_DIRS([m4])
dnl Workaround for older autoconf < 2.64
-AC_CONFIG_FILES([config/Makefile])
+AC_CONFIG_FILES([config/Makefile libgnu/Makefile])
- AC_COPYRIGHT([Copyright (C) 1996-2023 The elfutils developers.])
+ AC_COPYRIGHT([Copyright (C) 1996-2024 The elfutils developers.])
-AC_PREREQ(2.63) dnl Minimum Autoconf version required.
+AC_PREREQ(2.64) dnl Minimum Autoconf version required.
dnl The directories with content.
dnl Documentation.
---- a/Makefile.am
-+++ b/Makefile.am
-@@ -26,11 +26,11 @@ AM_MAKEFLAGS = --no-print-directory
-
- pkginclude_HEADERS = version.h
-
--SUBDIRS = config lib libelf libcpu backends libebl libdwelf libdwfl libdw \
-- libasm debuginfod src po doc tests
-+SUBDIRS = libgnu config lib libelf libcpu backends libebl libdwelf libdwfl libdw
-
- EXTRA_DIST = elfutils.spec GPG-KEY NOTES CONTRIBUTING \
-- COPYING COPYING-GPLV2 COPYING-LGPLV3
-+ COPYING COPYING-GPLV2 COPYING-LGPLV3 \
-+ m4/gnulib-cache.m4
-
- # Make sure the test install uses lib64 when $LIB will yield lib64.
- # Make sure the test build uses the same compiler, which on e.g. ppc64
--- a/libelf/elf_update.c
+++ b/libelf/elf_update.c
@@ -37,6 +37,33 @@
write_file (Elf *elf, int64_t size, int change_bo, size_t shnum)
--- a/lib/eu-config.h
+++ b/lib/eu-config.h
-@@ -52,14 +52,18 @@
- # define rwlock_unlock(lock) ((void) (lock))
+@@ -59,14 +59,18 @@
+ # define once(once_control, init_routine) init_routine()
#endif /* USE_LOCKS */
-#include <libintl.h>
#ifdef __i386__
# define internal_function __attribute__ ((regparm (3), stdcall))
-@@ -70,12 +74,7 @@
+@@ -77,12 +81,7 @@
#define internal_strong_alias(name, aliasname) \
extern __typeof (name) aliasname __attribute__ ((alias (#name))) internal_function;
#ifdef HAVE_GCC_STRUCT
#define attribute_packed \
-@@ -159,7 +158,7 @@ asm (".section predict_data, \"aw\"; .pr
+@@ -166,7 +165,7 @@ asm (".section predict_data, \"aw\"; .pr
#endif
/* Avoid PLT entries. */
+{
+ return ppc_check_object_attribute(ebl, vendor, tag, value, tag_name, value_name);
+}
---- a/lib/libeu.h
-+++ b/lib/libeu.h
-@@ -45,4 +45,11 @@ extern char *xasprintf(const char *fmt,
- extern uint32_t crc32 (uint32_t crc, unsigned char *buf, size_t len);
- extern int crc32_file (int fd, uint32_t *resp);
-
-+#ifdef __APPLE__
-+static inline void tdestroy(void *root __attribute__ ((unused)),
-+ void (*freekey)(void *) __attribute__ ((unused)))
-+{
-+}
-+#endif
-+
- #endif
--- a/libdwfl/libdwflP.h
+++ b/libdwfl/libdwflP.h
-@@ -31,6 +31,8 @@
+@@ -31,6 +31,7 @@
#include <libdwfl.h>
#include <libebl.h>
+#include <libeu.h>
-+#include <libgen.h>
#include <assert.h>
#include <dirent.h>
#include <errno.h>
+#endif
--- a/libdw/libdwP.h
+++ b/libdw/libdwP.h
-@@ -32,8 +32,10 @@
+@@ -32,10 +32,10 @@
#include <stdbool.h>
#include <pthread.h>
+#include <libeu.h>
#include <libdw.h>
#include <dwarf.h>
-+#include <libgen.h>
-
+-
/* Known location expressions already decoded. */
+ struct loc_s
+ {
--- a/libdw/Makefile.am
+++ b/libdw/Makefile.am
@@ -34,14 +34,12 @@ endif
modules = i386 sh x86_64 ia64 alpha arm aarch64 sparc ppc ppc64 s390 \
m68k bpf riscv csky loongarch arc
-@@ -100,17 +100,13 @@ loongarch_SRCS = loongarch_init.c loonga
+@@ -102,17 +102,13 @@ loongarch_SRCS = loongarch_init.c loonga
arc_SRCS = arc_init.c arc_symbol.c
+++ b/src/Makefile.am
@@ -29,9 +29,9 @@ bin_PROGRAMS = readelf nm size strip elf
elfcmp objdump ranlib strings ar unstrip stack elfcompress \
- elfclassify
+ elfclassify srcfiles
-noinst_LIBRARIES = libar.a
+noinst_LTLIBRARIES = libar.la
EXTRA_DIST = arlib.h debugpred.h
-@@ -39,17 +39,11 @@ bin_SCRIPTS = make-debug-archive
+@@ -39,27 +39,16 @@ bin_SCRIPTS = make-debug-archive
EXTRA_DIST += make-debug-archive.in
CLEANFILES += make-debug-archive
-if BUILD_STATIC
-libasm = ../libasm/libasm.a
-libdw = ../libdw/libdw.a -lz $(zip_LIBS) $(libelf) -ldl -lpthread
--libelf = ../libelf/libelf.a -lz
+-libelf = ../libelf/libelf.a -lz $(zstd_LIBS)
++libasm = ../libasm/libasm.la
++libdw = ../libdw/libdw.la -lz $(zip_LIBS) $(libelf) -ldl -lpthread
++libelf = ../libelf/libelf.la -lz $(zstd_LIBS)
+ if LIBDEBUGINFOD
+-libdebuginfod = ../debuginfod/libdebuginfod.a -lpthread $(libcurl_LIBS)
++libdebuginfod = ../debuginfod/libdebuginfod.la -lpthread $(libcurl_LIBS)
+ else
+ libdebuginfod =
+ endif
-else
-libasm = ../libasm/libasm.so
-libdw = ../libdw/libdw.so
-libelf = ../libelf/libelf.so
+-if LIBDEBUGINFOD
+-libdebuginfod = ../debuginfod/libdebuginfod.so
+-else
+-libdebuginfod =
+-endif
-endif
-libebl = ../libebl/libebl.a ../backends/libebl_backends.a ../libcpu/libcpu.a
-libeu = ../lib/libeu.a
-+libasm = ../libasm/libasm.la
-+libdw = ../libdw/libdw.la -lz $(zip_LIBS) $(libelf) -ldl -lpthread
-+libelf = ../libelf/libelf.la
+libebl = ../libebl/libebl.la ../backends/libebl_backends.la ../libcpu/libcpu.la
+libeu = ../lib/libeu.la
if DEMANGLE
demanglelib = -lstdc++
-@@ -77,9 +71,9 @@ findtextrel_LDADD = $(libdw) $(libelf) $
+@@ -87,9 +76,9 @@ findtextrel_LDADD = $(libdw) $(libelf) $
addr2line_LDADD = $(libdw) $(libelf) $(libeu) $(argp_LDADD) $(demanglelib)
elfcmp_LDADD = $(libebl) $(libdw) $(libelf) $(libeu) $(argp_LDADD)
objdump_LDADD = $(libasm) $(libebl) $(libdw) $(libelf) $(libeu) $(argp_LDADD)
elfcompress_LDADD = $(libebl) $(libelf) $(libdw) $(libeu) $(argp_LDADD)
--- a/tests/Makefile.am
+++ b/tests/Makefile.am
-@@ -662,17 +662,11 @@ installcheck-local:
+@@ -689,17 +689,11 @@ installcheck-local:
TESTS_ENVIRONMENT="$(installed_TESTS_ENVIRONMENT)" \
LOG_COMPILER="$(installed_LOG_COMPILER)" check-TESTS
-if BUILD_STATIC
-libdw = ../libdw/libdw.a -lz $(zip_LIBS) $(libelf) $(libebl) -ldl -lpthread
--libelf = ../libelf/libelf.a -lz
+-libelf = ../libelf/libelf.a -lz $(zstd_LIBS)
-libasm = ../libasm/libasm.a
-else
-libdw = ../libdw/libdw.so
Cflags: -I${includedir}
Requires.private: zlib @LIBZSTD@
+--- a/lib/next_prime.c
++++ b/lib/next_prime.c
+@@ -27,6 +27,7 @@
+ the GNU Lesser General Public License along with this program. If
+ not, see <http://www.gnu.org/licenses/>. */
+
++#include <config.h>
+ #include <stddef.h>
+
+
include $(TOPDIR)/rules.mk
PKG_NAME:=expat
-PKG_CPE_ID:=cpe:/a:libexpat:expat
+PKG_CPE_ID:=cpe:/a:libexpat:libexpat
PKG_VERSION:=2.6.2
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
include $(TOPDIR)/rules.mk
PKG_NAME:=flex
-PKG_CPE_ID:=cpe:/a:flex_project:flex
+PKG_CPE_ID:=cpe:/a:westes:flex
PKG_VERSION:=2.6.4
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
PKG_NAME:=gnulib
PKG_CPE_ID:=cpe:/a:gnu:$(PKG_NAME)
-PKG_VERSION:=f9a4ee73c3e7b544f640d0d04b55983d3a7b894e# # master
+PKG_VERSION:=c99c8d491850dc3a6e0b8604a2729d8bc5c0eff1# # stable-202401
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
PKG_SOURCE_URL:=https://git.savannah.gnu.org/cgit/$(PKG_NAME).git/snapshot
-PKG_HASH:=514716d58987a9c0de0d69fb22d42bcd19edf80eed099882a004ff162060f1a8
+PKG_HASH:=8e6f4a907d9677b55fd452e1340a3e030a6f530b138d420c11975da33f086b1e
include $(INCLUDE_DIR)/host-build.mk
if [ ! "$inst_ver" ]; then
warn_ "Error: '$app' not found"
ret=1
-@@ -1135,7 +1135,7 @@ autogen()
+@@ -1157,7 +1157,7 @@ autogen()
# two just-pre-run programs.
# Import from gettext.
--- /dev/null
+--- a/lib/search.in.h
++++ b/lib/search.in.h
+@@ -112,6 +112,11 @@ _GL_CXXALIASWARN (lsearch);
+ # define twalk rpl_twalk
+ # endif
+ # endif
++# if @REPLACE_TDESTROY@
++# if !(defined __cplusplus && defined GNULIB_NAMESPACE)
++# define tdestroy rpl_tdestroy
++# endif
++# endif
+
+ /* See <https://pubs.opengroup.org/onlinepubs/9699919799/basedefs/search.h.html>
+ <https://pubs.opengroup.org/onlinepubs/9699919799/functions/tsearch.html>
+@@ -137,6 +142,7 @@ extern "C" {
+ # if !GNULIB_defined_search_fn_types
+ typedef int (*_gl_search_compar_fn) (const void *, const void *);
+ typedef void (*_gl_search_action_fn) (const void *, VISIT, int);
++typedef void (*_gl_search_free_fn) (void *);
+ # define GNULIB_defined_search_fn_types 1
+ # endif
+ # ifdef __cplusplus
+@@ -252,9 +258,36 @@ _GL_CXXALIAS_SYS (twalk, void,
+ _GL_CXXALIASWARN (twalk);
+ # endif
+
++/* Removes the whole tree pointed to by root,
++ freeing all resources allocated by the tsearch() function.
++ The FREE_NODE function is called:
++ - For the data in each tree node.
++ - Even when no such work is necessary, to a function doing nothing
++ The arguments passed to FREE_NODE are:
++ 1. The pointer to the data. */
++# if @REPLACE_TDESTROY@
++_GL_FUNCDECL_RPL (tdestroy, void,
++ (void *vroot, _gl_search_free_fn freefct)
++ _GL_ARG_NONNULL ((2)));
++_GL_CXXALIAS_RPL (tdestroy, void,
++ (void *vroot, _gl_search_free_fn freefct));
++# else
++# if !@HAVE_TDESTROY@
++_GL_FUNCDECL_SYS (tdestroy, void,
++ (void *vroot, _gl_search_free_fn freefct)
++ _GL_ARG_NONNULL ((2)));
++# endif
++_GL_CXXALIAS_SYS (tdestroy, void,
++ (void *vroot, _gl_search_free_fn freefct));
++# endif
++# if __GLIBC__ >= 2
++_GL_CXXALIASWARN (tdestroy);
++# endif
++
+ /* Flags used by tsearch.c. */
+ # define GNULIB_defined_tsearch (@REPLACE_TSEARCH@ || !@HAVE_TSEARCH@)
+ # define GNULIB_defined_twalk (@REPLACE_TWALK@ || !@HAVE_TWALK@)
++# define GNULIB_defined_tdestroy (@REPLACE_TDESTROY@ || !@HAVE_TDESTROY@)
+
+ #elif defined GNULIB_POSIXCHECK
+ # undef tsearch
+@@ -277,6 +310,11 @@ _GL_WARN_ON_USE (tdelete, "tdelete is un
+ _GL_WARN_ON_USE (twalk, "twalk is unportable - "
+ "use gnulib module tsearch for portability");
+ # endif
++# undef tdestroy
++# if HAVE_RAW_DECL_TDESTROY
++_GL_WARN_ON_USE (tdestroy, "tdestroy is unportable - "
++ "use gnulib module tsearch for portability");
++# endif
+ #endif
+
+
+--- a/lib/tsearch.c
++++ b/lib/tsearch.c
+@@ -98,12 +98,14 @@
+
+ typedef int (*__compar_fn_t) (const void *, const void *);
+ typedef void (*__action_fn_t) (const void *, VISIT, int);
++typedef void (*__free_fn_t) (void *);
+
+ #ifndef weak_alias
+ # define __tsearch tsearch
+ # define __tfind tfind
+ # define __tdelete tdelete
+ # define __twalk twalk
++# define __tdestroy tdestroy
+ #endif
+
+ #ifndef internal_function
+@@ -656,7 +658,7 @@ weak_alias (__twalk, twalk)
+ #endif /* GNULIB_defined_twalk */
+
+
+-#ifdef _LIBC
++#if defined(_LIBC) || GNULIB_defined_tdestroy
+
+ /* The standardized functions miss an important functionality: the
+ tree cannot be removed easily. We provide a function to do this. */
+@@ -683,6 +685,8 @@ __tdestroy (void *vroot, __free_fn_t fre
+ if (root != NULL)
+ tdestroy_recurse (root, freefct);
+ }
++#ifdef weak_alias
+ weak_alias (__tdestroy, tdestroy)
++#endif
+
+-#endif /* _LIBC */
++#endif /* defined(_LIBC) || GNULIB_defined_tdestroy */
+--- a/m4/search_h.m4
++++ b/m4/search_h.m4
+@@ -39,7 +39,7 @@ AC_DEFUN_ONCE([gl_SEARCH_H],
+ dnl Check for declarations of anything we want to poison if the
+ dnl corresponding gnulib module is not in use.
+ gl_WARN_ON_USE_PREPARE([[#include <search.h>
+- ]], [tdelete tfind tsearch twalk])
++ ]], [tdelete tfind tsearch twalk tdestroy])
+
+ AC_REQUIRE([AC_C_RESTRICT])
+ ])
+@@ -75,8 +75,10 @@ AC_DEFUN([gl_SEARCH_H_DEFAULTS],
+ gl_MODULE_INDICATOR_INIT_VARIABLE([GNULIB_MDA_LFIND], [1])
+ gl_MODULE_INDICATOR_INIT_VARIABLE([GNULIB_MDA_LSEARCH], [1])
+ dnl Assume proper GNU behavior unless another module says otherwise.
+- HAVE_TSEARCH=1; AC_SUBST([HAVE_TSEARCH])
+- HAVE_TWALK=1; AC_SUBST([HAVE_TWALK])
+- REPLACE_TSEARCH=0; AC_SUBST([REPLACE_TSEARCH])
+- REPLACE_TWALK=0; AC_SUBST([REPLACE_TWALK])
++ HAVE_TSEARCH=1; AC_SUBST([HAVE_TSEARCH])
++ HAVE_TWALK=1; AC_SUBST([HAVE_TWALK])
++ HAVE_TDESTROY=1; AC_SUBST([HAVE_TDESTROY])
++ REPLACE_TSEARCH=0; AC_SUBST([REPLACE_TSEARCH])
++ REPLACE_TWALK=0; AC_SUBST([REPLACE_TWALK])
++ REPLACE_TDESTROY=0; AC_SUBST([REPLACE_TDESTROY])
+ ])
+--- a/m4/tsearch.m4
++++ b/m4/tsearch.m4
+@@ -9,6 +9,7 @@ AC_DEFUN([gl_FUNC_TSEARCH],
+ AC_REQUIRE([gl_SEARCH_H_DEFAULTS])
+ gl_CHECK_FUNCS_ANDROID([tsearch], [[#include <search.h>]])
+ gl_CHECK_FUNCS_ANDROID([twalk], [[#include <search.h>]])
++ gl_CHECK_FUNCS_ANDROID([tdestroy], [[#include <search.h>]])
+ if test $ac_cv_func_tsearch = yes; then
+ dnl On OpenBSD 4.0, the return value of tdelete() is incorrect.
+ AC_REQUIRE([AC_PROG_CC])
+@@ -50,6 +51,7 @@ main ()
+ *no)
+ REPLACE_TSEARCH=1
+ REPLACE_TWALK=1
++ REPLACE_TDESTROY=1
+ ;;
+ esac
+ else
+@@ -64,6 +66,12 @@ main ()
+ future*) REPLACE_TWALK=1 ;;
+ esac
+ fi
++ if test $ac_cv_func_tdestroy != yes; then
++ HAVE_TDESTROY=0
++ case "$gl_cv_onwards_func_tdestroy" in
++ future*) REPLACE_TDESTROY=1 ;;
++ esac
++ fi
+ ])
+
+ # Prerequisites of lib/tsearch.c.
+--- a/modules/search
++++ b/modules/search
+@@ -37,8 +37,10 @@ search.h: search.in.h $(top_builddir)/co
+ -e 's/@''GNULIB_MDA_LSEARCH''@/$(GNULIB_MDA_LSEARCH)/g' \
+ -e 's|@''HAVE_TSEARCH''@|$(HAVE_TSEARCH)|g' \
+ -e 's|@''HAVE_TWALK''@|$(HAVE_TWALK)|g' \
++ -e 's|@''HAVE_TDESTROY''@|$(HAVE_TDESTROY)|g' \
+ -e 's|@''REPLACE_TSEARCH''@|$(REPLACE_TSEARCH)|g' \
+ -e 's|@''REPLACE_TWALK''@|$(REPLACE_TWALK)|g' \
++ -e 's|@''REPLACE_TDESTROY''@|$(REPLACE_TDESTROY)|g' \
+ -e '/definitions of _GL_FUNCDECL_RPL/r $(CXXDEFS_H)' \
+ -e '/definition of _GL_ARG_NONNULL/r $(ARG_NONNULL_H)' \
+ -e '/definition of _GL_WARN_ON_USE/r $(WARN_ON_USE_H)' \
+--- a/modules/tsearch
++++ b/modules/tsearch
+@@ -11,7 +11,12 @@ search
+ configure.ac:
+ gl_FUNC_TSEARCH
+ gl_CONDITIONAL([GL_COND_OBJ_TSEARCH],
+- [test $HAVE_TSEARCH = 0 || test $HAVE_TWALK = 0 || test $REPLACE_TSEARCH = 1 || test $REPLACE_TWALK = 1])
++ [test $HAVE_TSEARCH = 0 ||
++ test $HAVE_TWALK = 0 ||
++ test $HAVE_TDESTROY = 0 ||
++ test $REPLACE_TSEARCH = 1 ||
++ test $REPLACE_TWALK = 1 ||
++ test $REPLACE_TDESTROY = 1])
+ AM_COND_IF([GL_COND_OBJ_TSEARCH], [
+ gl_PREREQ_TSEARCH
+ ])
--- /dev/null
+--- a/lib/ialloc.h
++++ b/lib/ialloc.h
+@@ -106,6 +106,8 @@ icalloc (idx_t n, idx_t s)
+ return calloc (n, s);
+ }
+
++#if GNULIB_REALLOCARRAY
++
+ /* ireallocarray (ptr, num, size) is like reallocarray (ptr, num, size).
+ It returns a non-NULL pointer to num * size bytes of memory.
+ Upon failure, it returns NULL with errno set. */
+@@ -131,6 +133,8 @@ ireallocarray (void *p, idx_t n, idx_t s
+ return _gl_alloc_nomem ();
+ }
+
++#endif /* GNULIB_REALLOCARRAY */
++
+ #ifdef __cplusplus
+ }
+ #endif
+--- a/lib/xmalloc.c
++++ b/lib/xmalloc.c
+@@ -51,12 +51,16 @@ ximalloc (idx_t s)
+ return nonnull (imalloc (s));
+ }
+
++#if GNULIB_REALLOCARRAY
++
+ char *
+ xcharalloc (size_t n)
+ {
+ return XNMALLOC (n, char);
+ }
+
++#endif /* GNULIB_REALLOCARRAY */
++
+ /* Change the size of an allocated block of memory P to S bytes,
+ with error checking. */
+
+@@ -75,6 +79,8 @@ xirealloc (void *p, idx_t s)
+ return nonnull (irealloc (p, s));
+ }
+
++#if GNULIB_REALLOCARRAY
++
+ /* Change the size of an allocated block of memory P to an array of N
+ objects each of S bytes, with error checking. */
+
+@@ -205,6 +211,8 @@ x2nrealloc (void *p, size_t *pn, size_t
+ return p;
+ }
+
++#endif /* GNULIB_REALLOCARRAY */
++
+ /* Grow PA, which points to an array of *PN items, and return the
+ location of the reallocated array, updating *PN to reflect its
+ new size. The new array will contain at least N_INCR_MIN more
+--- a/lib/xalloc.h
++++ b/lib/xalloc.h
+@@ -129,6 +129,7 @@ char *xstrdup (char const *str)
+ # define XCALLOC(n, t) \
+ ((t *) (sizeof (t) == 1 ? xzalloc (n) : xcalloc (n, sizeof (t))))
+
++# if GNULIB_REALLOCARRAY
+
+ /* Allocate an array of N objects, each with S bytes of memory,
+ dynamically, with error checking. S must be nonzero. */
+@@ -156,6 +157,8 @@ char *xcharalloc (size_t n)
+ _GL_ATTRIBUTE_MALLOC _GL_ATTRIBUTE_DEALLOC_FREE
+ _GL_ATTRIBUTE_ALLOC_SIZE ((1)) _GL_ATTRIBUTE_RETURNS_NONNULL;
+
++# endif /* GNULIB_REALLOCARRAY */
++
+ #endif /* GNULIB_XALLOC */
+
+
+--- a/lib/safe-alloc.h
++++ b/lib/safe-alloc.h
+@@ -36,6 +36,8 @@ _GL_INLINE_HEADER_BEGIN
+ # define SAFE_ALLOC_INLINE _GL_INLINE
+ #endif
+
++#if GNULIB_REALLOCARRAY
++
+ /* Don't call these directly - use the macros below. */
+ SAFE_ALLOC_INLINE void *
+ safe_alloc_realloc_n (void *ptr, size_t count, size_t size)
+@@ -51,6 +53,9 @@ safe_alloc_realloc_n (void *ptr, size_t
+ #endif
+ return ptr;
+ }
++
++#endif /* GNULIB_REALLOCARRAY */
++
+ _GL_ATTRIBUTE_NODISCARD SAFE_ALLOC_INLINE int
+ safe_alloc_check (void *ptr)
+ {
+@@ -84,6 +89,8 @@ safe_alloc_check (void *ptr)
+ #define ALLOC_N(ptr, count) \
+ safe_alloc_check ((ptr) = calloc (count, sizeof *(ptr)))
+
++#if GNULIB_REALLOCARRAY
++
+ /**
+ * ALLOC_N_UNINITIALIZED:
+ * @ptr: pointer to allocated memory
+@@ -112,6 +119,8 @@ safe_alloc_check (void *ptr)
+ #define REALLOC_N(ptr, count) \
+ safe_alloc_check ((ptr) = safe_alloc_realloc_n (ptr, count, sizeof *(ptr)))
+
++#endif /* GNULIB_REALLOCARRAY */
++
+ /**
+ * FREE:
+ * @ptr: pointer holding address to be freed
include $(TOPDIR)/rules.mk
PKG_NAME:=missing-macros
-PKG_RELEASE:=11
+PKG_RELEASE:=12
include $(INCLUDE_DIR)/host-build.mk
$(INSTALL_DATA) ./src/m4/*.m4 $(STAGING_DIR_HOST)/share/aclocal/
$(INSTALL_DIR) $(STAGING_DIR_HOST)/bin
$(INSTALL_BIN) ./src/bin/* $(STAGING_DIR_HOST)/bin/
+ $(LN) makeinfo $(STAGING_DIR_HOST)/bin/texi2any
+ $(LN) makeinfo $(STAGING_DIR_HOST)/bin/texi2pdf
+ $(LN) makeinfo $(STAGING_DIR_HOST)/bin/texi2dvi
+ $(LN) makeinfo $(STAGING_DIR_HOST)/bin/pdftexi2dvi
+ $(LN) makeinfo $(STAGING_DIR_HOST)/bin/texi2html
endef
$(eval $(call HostBuild))
PKG_LICENSE:=Zlib
PKG_LICENSE_FILES:=README
-PKG_CPE_ID:=cpe:/a:gnu:zlib
+PKG_CPE_ID:=cpe:/a:zlib:zlib
HOST_BUILD_PARALLEL:=1
HOSTCC:= $(HOSTCC_NOCACHE)
+HOST_CFLAGS += $(HOST_FPIC)
+
HOST_MAKE_FLAGS += \
BACKTRACE=0 \
HAVE_THREAD=1 \