target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4018-ex61x0v2.dtsi

   1 /* Copyright (c) 2015, The Linux Foundation. All rights reserved.
   2  * Copyright (c) 2018, David Bauer <mail@david-bauer.net>
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  *
  16  */
  17
  18 #include "qcom-ipq4019.dtsi"
  19 #include <dt-bindings/gpio/gpio.h>
  20 #include <dt-bindings/input/input.h>
  21 #include <dt-bindings/leds/common.h>
  22 #include <dt-bindings/soc/qcom,tcsr.h>
  23
  24 / {
  25         model = "Netgear EX61X0v2";
  26         compatible = "netgear,ex61x0v2";
  27
  28         soc {
  29                 rng@22000 {
  30                         status = "okay";
  31                 };
  32
  33                 mdio@90000 {
  34                         status = "okay";
  35                 };
  36
  37                 tcsr@1949000 {
  38                         compatible = "qcom,tcsr";
  39                         reg = <0x1949000 0x100>;
  40                         qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  41                 };
  42
  43                 ess_tcsr@1953000 {
  44                         compatible = "qcom,tcsr";
  45                         reg = <0x1953000 0x1000>;
  46                         qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  47                 };
  48
  49                 tcsr@1957000 {
  50                         compatible = "qcom,tcsr";
  51                         reg = <0x1957000 0x100>;
  52                         qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  53                 };
  54
  55                 crypto@8e3a000 {
  56                         status = "okay";
  57                 };
  58
  59                 watchdog@b017000 {
  60                         status = "okay";
  61                 };
  62         };
  63
  64         aliases {
  65                 led-boot = &power_amber;
  66                 led-failsafe = &power_amber;
  67                 led-running = &power_green;
  68                 led-upgrade = &power_amber;
  69                 label-mac-device = &gmac;
  70         };
  71
  72         keys {
  73                 compatible = "gpio-keys";
  74
  75                 wps {
  76                         label = "wps";
  77                         gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
  78                         linux,code = <KEY_WPS_BUTTON>;
  79                 };
  80
  81                 reset {
  82                         label = "reset";
  83                         gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
  84                         linux,code = <KEY_RESTART>;
  85                 };
  86         };
  87
  88         led_spi {
  89                 compatible = "spi-gpio";
  90                 #address-cells = <1>;
  91                 #size-cells = <0>;
  92
  93                 sck-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>;
  94                 mosi-gpios = <&tlmm 4 GPIO_ACTIVE_HIGH>;
  95                 num-chipselects = <0>;
  96
  97                 led_gpio: led_gpio@0 {
  98                         compatible = "fairchild,74hc595";
  99                         reg = <0>;
 100                         gpio-controller;
 101                         #gpio-cells = <2>;
 102                         registers-number = <1>;
 103                         spi-max-frequency = <1000000>;
 104                 };
 105         };
 106
 107         leds {
 108                 compatible = "gpio-leds";
 109
 110                 power_amber: power_amber {
 111                         function = LED_FUNCTION_POWER;
 112                         color = <LED_COLOR_ID_AMBER>;
 113                         gpios = <&led_gpio 7 GPIO_ACTIVE_LOW>;
 114                 };
 115
 116                 power_green: power_green {
 117                         function = LED_FUNCTION_POWER;
 118                         color = <LED_COLOR_ID_GREEN>;
 119                         gpios = <&led_gpio 6 GPIO_ACTIVE_LOW>;
 120                 };
 121
 122                 right {
 123                         label = "blue:right";
 124                         gpios = <&led_gpio 5 GPIO_ACTIVE_LOW>;
 125                 };
 126
 127                 left {
 128                         label = "blue:left";
 129                         gpios = <&led_gpio 4 GPIO_ACTIVE_LOW>;
 130                 };
 131
 132                 client_green {
 133                         label = "green:client";
 134                         gpios = <&led_gpio 3 GPIO_ACTIVE_LOW>;
 135                 };
 136
 137                 client_red {
 138                         label = "red:client";
 139                         gpios = <&led_gpio 2 GPIO_ACTIVE_LOW>;
 140                 };
 141
 142                 router_green {
 143                         label = "green:router";
 144                         gpios = <&led_gpio 1 GPIO_ACTIVE_LOW>;
 145                 };
 146
 147                 router_red {
 148                         label = "red:router";
 149                         gpios = <&led_gpio 0 GPIO_ACTIVE_LOW>;
 150                 };
 151
 152                 wps {
 153                         function = LED_FUNCTION_WPS;
 154                         color = <LED_COLOR_ID_GREEN>;
 155                         gpios = <&tlmm 1 GPIO_ACTIVE_LOW>;
 156                 };
 157         };
 158 };
 159
 160 &tlmm {
 161         serial_pins: serial_pinmux {
 162                 mux {
 163                         pins = "gpio60", "gpio61";
 164                         function = "blsp_uart0";
 165                         bias-disable;
 166                 };
 167         };
 168
 169         spi_0_pins: spi_0_pinmux {
 170                 pin {
 171                         function = "blsp_spi0";
 172                         pins = "gpio55", "gpio56", "gpio57";
 173                         drive-strength = <12>;
 174                         bias-disable;
 175                 };
 176                 pin_cs {
 177                         function = "gpio";
 178                         pins = "gpio54";
 179                         drive-strength = <2>;
 180                         bias-disable;
 181                         output-high;
 182                 };
 183         };
 184 };
 185
 186 &blsp1_spi1 {
 187         pinctrl-0 = <&spi_0_pins>;
 188         pinctrl-names = "default";
 189         status = "okay";
 190         cs-gpios = <&tlmm 54 GPIO_ACTIVE_HIGH>;
 191
 192         mx25l12805d@0 {
 193                 compatible = "jedec,spi-nor";
 194                 reg = <0>;
 195                 spi-max-frequency = <45000000>;
 196
 197                 partitions {
 198                         compatible = "fixed-partitions";
 199                         #address-cells = <1>;
 200                         #size-cells = <1>;
 201
 202                         partition0@0 {
 203                                 label = "SBL1";
 204                                 reg = <0x00000000 0x00040000>;
 205                                 read-only;
 206                         };
 207
 208                         partition1@40000 {
 209                                 label = "MIBIB";
 210                                 reg = <0x00040000 0x00020000>;
 211                                 read-only;
 212                         };
 213
 214                         partition2@60000 {
 215                                 label = "QSEE";
 216                                 reg = <0x00060000 0x00060000>;
 217                                 read-only;
 218                         };
 219
 220                         partition3@c0000 {
 221                                 label = "CDT";
 222                                 reg = <0x000c0000 0x00010000>;
 223                                 read-only;
 224                         };
 225
 226                         partition4@d0000 {
 227                                 label = "DDRPARAMS";
 228                                 reg = <0x000d0000 0x00010000>;
 229                                 read-only;
 230                         };
 231
 232                         partition5@E0000 {
 233                                 label = "APPSBLENV";
 234                                 reg = <0x000e0000 0x00010000>;
 235                                 read-only;
 236                         };
 237
 238                         partition6@F0000 {
 239                                 label = "APPSBL";
 240                                 reg = <0x000f0000 0x00080000>;
 241                                 read-only;
 242                         };
 243
 244                         partition7@170000 {
 245                                 label = "ART";
 246                                 reg = <0x00170000 0x00010000>;
 247                                 read-only;
 248
 249                                 nvmem-layout {
 250                                         compatible = "fixed-layout";
 251                                         #address-cells = <1>;
 252                                         #size-cells = <1>;
 253
 254                                         precal_art_1000: precal@1000 {
 255                                                 reg = <0x1000 0x2f20>;
 256                                         };
 257
 258                                         precal_art_5000: precal@5000 {
 259                                                 reg = <0x5000 0x2f20>;
 260                                         };
 261                                 };
 262                         };
 263
 264                         partition8@180000 {
 265                                 label = "config";
 266                                 reg = <0x00180000 0x00010000>;
 267                                 read-only;
 268                         };
 269
 270                         partition9@190000 {
 271                                 label = "pot";
 272                                 reg = <0x00190000 0x00010000>;
 273                                 read-only;
 274                         };
 275
 276                         partition10@1a0000 {
 277                                 label = "dnidata";
 278                                 reg = <0x001a0000 0x00010000>;
 279                                 read-only;
 280
 281                                 nvmem-layout {
 282                                         compatible = "fixed-layout";
 283                                         #address-cells = <1>;
 284                                         #size-cells = <1>;
 285
 286                                         macaddr_dnidata_0: macaddr@0 {
 287                                                 reg = <0x0 0x6>;
 288                                         };
 289
 290                                         macaddr_dnidata_c: macaddr@c {
 291                                                 reg = <0xc 0x6>;
 292                                         };
 293                                 };
 294                         };
 295
 296                         partition11@1b0000 {
 297                                 compatible = "denx,fit";
 298                                 label = "firmware";
 299                                 reg = <0x001b0000 0x00e10000>;
 300                         };
 301
 302                         partition12@fc0000 {
 303                                 label = "language";
 304                                 reg = <0x00fc0000 0x00040000>;
 305                                 read-only;
 306                         };
 307                 };
 308         };
 309 };
 310
 311 &blsp1_uart1 {
 312         pinctrl-0 = <&serial_pins>;
 313         pinctrl-names = "default";
 314         status = "okay";
 315 };
 316
 317 &blsp_dma {
 318         status = "okay";
 319 };
 320
 321 &cryptobam {
 322         status = "okay";
 323 };
 324
 325 &wifi0 {
 326         status = "okay";
 327         nvmem-cell-names = "pre-calibration", "mac-address";
 328         nvmem-cells = <&precal_art_1000>, <&macaddr_dnidata_0>;
 329 };
 330
 331 &wifi1 {
 332         status = "okay";
 333         nvmem-cell-names = "pre-calibration", "mac-address";
 334         nvmem-cells = <&precal_art_5000>, <&macaddr_dnidata_c>;
 335 };
 336
 337 &gmac {
 338         status = "okay";
 339 };
 340
 341 &switch {
 342         status = "okay";
 343 };
 344
 345 &swport4 {
 346         status = "okay";
 347         label = "lan";
 348 };