base-files: reduce IPv6 ULA prefix generation to a single call
[openwrt/staging/stintel.git] / target / linux / ipq40xx / files-6.1 / arch / arm / boot / dts / qcom-ipq4019-mf289f.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 // Copyright (c) 2022, Pawel Dembicki <paweldembicki@gmail.com>.
3 // Copyright (c) 2022, Giammarco Marzano <stich86@gmail.com>.
4
5 #include "qcom-ipq4019.dtsi"
6 #include <dt-bindings/soc/qcom,tcsr.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/leds/common.h>
10
11 / {
12 model = "ZTE MF289F";
13 compatible = "zte,mf289f";
14
15 aliases {
16 led-boot = &led_status;
17 led-failsafe = &led_status;
18 led-running = &led_status;
19 led-upgrade = &led_status;
20 };
21
22 chosen {
23 /*
24 * bootargs forced by u-boot bootipq command:
25 * 'ubi.mtd=rootfs root=mtd:ubi_rootfs rootfstype=squashfs rootwait'
26 */
27 bootargs-append = " root=/dev/ubiblock0_1";
28 };
29
30 /*
31 * This node is used to restart modem module to avoid anomalous
32 * behaviours on initial communication.
33 */
34 gpio-restart {
35 compatible = "gpio-restart";
36 gpios = <&tlmm 8 GPIO_ACTIVE_HIGH>;
37 };
38
39 leds {
40 compatible = "gpio-leds";
41
42 led_status: led-0 {
43 function = LED_FUNCTION_POWER;
44 color = <LED_COLOR_ID_BLUE>;
45 gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
46 };
47
48 led-1 {
49 function = LED_FUNCTION_WLAN;
50 color = <LED_COLOR_ID_BLUE>;
51 gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
52 linux,default-trigger = "phy0tpt";
53 };
54 };
55
56 keys {
57 compatible = "gpio-keys";
58
59 key-reset {
60 label = "reset";
61 linux,code = <KEY_RESTART>;
62 gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
63 };
64
65 key-wps {
66 label = "wps";
67 linux,code = <KEY_WPS_BUTTON>;
68 gpios = <&tlmm 68 GPIO_ACTIVE_LOW>;
69 };
70 };
71
72 soc {
73 tcsr@1949000 {
74 compatible = "qcom,tcsr";
75 reg = <0x1949000 0x100>;
76 qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
77 };
78
79 tcsr@194b000 {
80 /* select hostmode */
81 compatible = "qcom,tcsr";
82 reg = <0x194b000 0x100>;
83 qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
84 status = "okay";
85 };
86
87 ess_tcsr@1953000 {
88 compatible = "qcom,tcsr";
89 reg = <0x1953000 0x1000>;
90 qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
91 };
92
93 tcsr@1957000 {
94 compatible = "qcom,tcsr";
95 reg = <0x1957000 0x100>;
96 qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
97 };
98 };
99 };
100
101 &prng {
102 status = "okay";
103 };
104
105 &mdio {
106 status = "okay";
107 pinctrl-0 = <&mdio_pins>;
108 pinctrl-names = "default";
109 reset-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>;
110 reset-delay-us = <2000>;
111 };
112
113 &watchdog {
114 status = "okay";
115 };
116
117 &blsp_dma {
118 status = "okay";
119 };
120
121 &usb2 {
122 status = "okay";
123 };
124
125 &usb3 {
126 status = "okay";
127 };
128
129 &blsp1_spi1 {
130 pinctrl-0 = <&spi_0_pins>;
131 pinctrl-names = "default";
132 status = "okay";
133 cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>,
134 <&tlmm 54 GPIO_ACTIVE_HIGH>;
135
136 flash@0 {
137 compatible = "jedec,spi-nor";
138 #address-cells = <1>;
139 #size-cells = <1>;
140 reg = <0>;
141 spi-max-frequency = <24000000>;
142
143 partitions {
144 compatible = "fixed-partitions";
145 #address-cells = <1>;
146 #size-cells = <1>;
147
148 partition@0 {
149 label = "0:SBL1";
150 reg = <0x0 0x40000>;
151 read-only;
152 };
153
154 partition@40000 {
155 label = "0:MIBIB";
156 reg = <0x40000 0x20000>;
157 read-only;
158 };
159
160 partition@60000 {
161 label = "0:QSEE";
162 reg = <0x60000 0x60000>;
163 read-only;
164 };
165
166 partition@c0000 {
167 label = "0:CDT";
168 reg = <0xc0000 0x10000>;
169 read-only;
170 };
171
172 partition@d0000 {
173 label = "0:DDRPARAMS";
174 reg = <0xd0000 0x10000>;
175 read-only;
176 };
177
178 partition@e0000 {
179 label = "0:APPSBLENV";
180 reg = <0xe0000 0x10000>;
181 read-only;
182 };
183
184 partition@f0000 {
185 label = "0:APPSBL";
186 reg = <0xf0000 0xc0000>;
187 read-only;
188 };
189
190 partition@1b0000 {
191 label = "0:reserved1";
192 reg = <0x1b0000 0x50000>;
193 read-only;
194 };
195 };
196 };
197
198 spi-nand@1 { /* flash@1 ? */
199 compatible = "spi-nand";
200 reg = <1>;
201 spi-max-frequency = <24000000>;
202
203 partitions {
204 compatible = "fixed-partitions";
205 #address-cells = <1>;
206 #size-cells = <1>;
207
208 partition@0 {
209 label = "fota-flag";
210 reg = <0x0 0xa0000>;
211 read-only;
212 };
213
214 partition@a0000 {
215 label = "ART";
216 reg = <0xa0000 0x80000>;
217 read-only;
218
219 nvmem-layout {
220 compatible = "fixed-layout";
221 #address-cells = <1>;
222 #size-cells = <1>;
223
224 precal_art_1000: precal@1000 {
225 reg = <0x1000 0x2f20>;
226 };
227
228 precal_art_5000: precal@5000 {
229 reg = <0x5000 0x2f20>;
230 };
231 };
232 };
233
234 partition@120000 {
235 label = "mac";
236 reg = <0x120000 0x80000>;
237 read-only;
238
239 nvmem-layout {
240 compatible = "fixed-layout";
241 #address-cells = <1>;
242 #size-cells = <1>;
243
244 macaddr_mac_0: macaddr@0 {
245 compatible = "mac-base";
246 reg = <0x0 0x6>;
247 #nvmem-cell-cells = <1>;
248 };
249 };
250 };
251
252 partition@1a0000 {
253 label = "reserved2";
254 reg = <0x1a0000 0xc0000>;
255 read-only;
256 };
257
258 partition@260000 {
259 label = "cfg-param";
260 reg = <0x260000 0x400000>;
261 read-only;
262 };
263
264 partition@660000 {
265 label = "log";
266 reg = <0x660000 0x400000>;
267 };
268
269 partition@a60000 {
270 label = "oops";
271 reg = <0xa60000 0xa0000>;
272 };
273
274 partition@b00000 {
275 label = "reserved3";
276 reg = <0xb00000 0x500000>;
277 read-only;
278 };
279
280 partition@1000000 {
281 label = "web";
282 reg = <0x1000000 0x800000>;
283 };
284
285 partition@1800000 {
286 label = "rootfs";
287 reg = <0x1800000 0x1d00000>;
288 };
289
290 partition@3500000 {
291 label = "data";
292 reg = <0x3500000 0x1900000>;
293 };
294
295 partition@4e00000 {
296 label = "fota";
297 reg = <0x4e00000 0x3200000>;
298 };
299 };
300 };
301 };
302
303 &blsp1_uart1 {
304 pinctrl-0 = <&serial_pins>;
305 pinctrl-names = "default";
306 status = "okay";
307 };
308
309 &crypto {
310 status = "okay";
311 };
312
313 &cryptobam {
314 status = "okay";
315 };
316
317 &gmac {
318 status = "okay";
319 nvmem-cell-names = "mac-address";
320 nvmem-cells = <&macaddr_mac_0 0>;
321 };
322
323 &switch {
324 status = "okay";
325 };
326
327 &swport2 {
328 status = "okay";
329
330 label = "wan";
331
332 nvmem-cell-names = "mac-address";
333 nvmem-cells = <&macaddr_mac_0 1>;
334 };
335
336 &swport5 {
337 status = "okay";
338
339 label = "lan";
340 };
341
342 &qpic_bam {
343 status = "okay";
344 };
345
346 &tlmm {
347 i2c_0_pins: i2c_0_pinmux {
348 mux {
349 pins = "gpio20", "gpio21";
350 function = "blsp_i2c0";
351 bias-disable;
352 };
353 };
354
355 mdio_pins: mdio_pinmux {
356 mux_1 {
357 pins = "gpio6";
358 function = "mdio";
359 bias-pull-up;
360 };
361
362 mux_2 {
363 pins = "gpio7";
364 function = "mdc";
365 bias-pull-up;
366 };
367 };
368
369 serial_pins: serial_pinmux {
370 mux {
371 pins = "gpio16", "gpio17";
372 function = "blsp_uart0";
373 bias-disable;
374 };
375 };
376
377 spi_0_pins: spi_0_pinmux {
378 pinmux {
379 function = "blsp_spi0";
380 pins = "gpio13", "gpio14", "gpio15";
381 drive-strength = <12>;
382 bias-disable;
383 };
384
385 pinmux_cs {
386 function = "gpio";
387 pins = "gpio12", "gpio54";
388 drive-strength = <2>;
389 bias-disable;
390 output-high;
391 };
392 };
393 };
394
395 &usb2_hs_phy {
396 status = "okay";
397 };
398
399 &usb3_ss_phy {
400 status = "okay";
401 };
402
403 &usb3_hs_phy {
404 status = "okay";
405 };
406
407 &wifi0 {
408 status = "okay";
409 nvmem-cell-names = "pre-calibration", "mac-address";
410 nvmem-cells = <&precal_art_1000>, <&macaddr_mac_0 2>;
411 qcom,ath10k-calibration-variant = "zte,mf289f";
412 };
413
414 /* This node is used only on AT2 version for 5Ghz on IPQ4019 with board-id=21 */
415 &wifi1 {
416 status = "okay";
417 nvmem-cell-names = "pre-calibration", "mac-address";
418 nvmem-cells = <&precal_art_5000>, <&macaddr_mac_0 3>;
419 qcom,ath10k-calibration-variant = "zte,mf289f";
420 };
421
422 /* This node is used only on AT1 version for 5Ghz on QCA9984 */
423 &pcie0 {
424 status = "okay";
425 perst-gpio = <&tlmm 38 GPIO_ACTIVE_LOW>;
426 wake-gpio = <&tlmm 40 GPIO_ACTIVE_LOW>;
427 clkreq-gpio = <&tlmm 39 GPIO_ACTIVE_LOW>;
428
429 bridge@0,0 {
430 reg = <0x00000000 0 0 0 0>;
431 #address-cells = <3>;
432 #size-cells = <2>;
433 ranges;
434
435 wifi2: wifi@1,0 {
436 nvmem-cell-names = "mac-address";
437 nvmem-cells = <&macaddr_mac_0 4>;
438 compatible = "qcom,ath10k";
439 reg = <0x00010000 0 0 0 0>;
440 qcom,ath10k-calibration-variant = "zte,mf289f";
441 };
442 };
443 };