FEATURES:=squashfs gpio
KERNEL_PATCHVER:=5.15
+KERNEL_TESTING_PATCHVER:=6.1
define Target/Description
Build firmware images for Ralink RT288x/RT3xxx based boards.
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_BLK_MQ_PCI=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
CONFIG_CEVT_R4K=y
CONFIG_CEVT_SYSTICK_QUIRK=y
CONFIG_CLKEVT_RT3352=y
CONFIG_CMDLINE_BOOL=y
# CONFIG_CMDLINE_OVERRIDE is not set
CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_CPU_GENERIC_DUMP_TLB=y
CONFIG_CPU_HAS_DIEI=y
CONFIG_CPU_SUPPORTS_MSA=y
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CSRC_R4K=y
+CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_PINCTRL=y
CONFIG_DMA_NONCOHERENT=y
# CONFIG_DTB_MT7620A_EVAL is not set
CONFIG_DTC=y
CONFIG_EARLY_PRINTK=y
CONFIG_ETHERNET_PACKET_MANGLE=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
CONFIG_FIXED_PHY=y
CONFIG_FWNODE_MDIO=y
CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC11_NO_ARRAY_BOUNDS=y
CONFIG_GENERIC_ATOMIC64=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_FIND_FIRST_BIT=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_IOMAP=y
CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_LIB_ASHLDI3=y
CONFIG_GENERIC_LIB_ASHRDI3=y
CONFIG_GPIO_RALINK=y
CONFIG_GPIO_WATCHDOG=y
# CONFIG_GPIO_WATCHDOG_ARCH_INITCALL is not set
-CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_HARDWARE_WATCHPOINTS=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
CONFIG_MIPS_CMDLINE_FROM_DTB=y
-CONFIG_MIPS_EBPF_JIT=y
CONFIG_MIPS_L1_CACHE_SHIFT=5
CONFIG_MIPS_LD_CAN_LINK_VDSO=y
# CONFIG_MIPS_NO_APPENDED_DTB is not set
CONFIG_NET_VENDOR_RALINK=y
CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_MDIO=y
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DRIVERS_LEGACY=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PGTABLE_LEVELS=2
CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
# CONFIG_PHY_MT7621_PCI is not set
CONFIG_PHY_RALINK_USB=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MT7620=y
CONFIG_PINCTRL_RALINK=y
# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PREEMPT_NONE_BUILD=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
CONFIG_RALINK=y
CONFIG_RALINK_WDT=y
+CONFIG_RANDSTRUCT_NONE=y
CONFIG_RATIONAL=y
CONFIG_REGMAP=y
CONFIG_REGMAP_MMIO=y
CONFIG_USB_SUPPORT=y
CONFIG_USE_OF=y
CONFIG_WATCHDOG_CORE=y
+CONFIG_ZBOOT_LOAD_ADDRESS=0x0
CONFIG_AT803X_PHY=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BOARD_SCACHE=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
CONFIG_CEVT_R4K=y
CONFIG_CLKSRC_MIPS_GIC=y
CONFIG_CLK_MT7621=y
CONFIG_CLOCKSOURCE_WATCHDOG=y
+CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=100
CONFIG_CLONE_BACKWARDS=y
CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
CONFIG_CMDLINE_BOOL=y
# CONFIG_CMDLINE_OVERRIDE is not set
CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
CONFIG_CPU_GENERIC_DUMP_TLB=y
CONFIG_CPU_HAS_DIEI=y
CONFIG_CPU_HAS_PREFETCH=y
CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_ZSTD=y
CONFIG_CSRC_R4K=y
+CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_PINCTRL=y
CONFIG_DIMLIB=y
CONFIG_DMA_NONCOHERENT=y
-# CONFIG_DTB_GNUBEE1 is not set
-# CONFIG_DTB_GNUBEE2 is not set
-CONFIG_DTB_RT_NONE=y
CONFIG_DTC=y
CONFIG_EARLY_PRINTK=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
CONFIG_FIXED_PHY=y
CONFIG_FWNODE_MDIO=y
CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC11_NO_ARRAY_BOUNDS=y
CONFIG_GENERIC_ATOMIC64=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_FIND_FIRST_BIT=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_IOMAP=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_GPIO_WATCHDOG=y
# CONFIG_GPIO_WATCHDOG_ARCH_INITCALL is not set
CONFIG_GRO_CELLS=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_HARDWARE_WATCHPOINTS=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_MIPS_CPS=y
# CONFIG_MIPS_CPS_NS16550_BOOL is not set
CONFIG_MIPS_CPU_SCACHE=y
-CONFIG_MIPS_EBPF_JIT=y
CONFIG_MIPS_GIC=y
CONFIG_MIPS_L1_CACHE_SHIFT=5
CONFIG_MIPS_LD_CAN_LINK_VDSO=y
CONFIG_MTD_UBI_BLOCK=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MTD_VIRT_CONCAT=y
-# CONFIG_MTK_HSDMA is not set
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NET_DEVLINK=y
CONFIG_NET_DSA=y
CONFIG_NO_HZ_IDLE=y
CONFIG_NR_CPUS=4
CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_PADATA=y
CONFIG_PAGE_POOL=y
CONFIG_PAGE_POOL_STATS=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
CONFIG_PCI=y
CONFIG_PCIE_MT7621=y
CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PGTABLE_LEVELS=2
CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
CONFIG_PHYLINK=y
CONFIG_PHY_MT7621_PCI=y
# CONFIG_PHY_RALINK_USB is not set
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_GPIO=y
CONFIG_POWER_SUPPLY=y
+CONFIG_PREEMPT_NONE_BUILD=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_QCOM_NET_PHYLIB=y
CONFIG_QUEUED_RWLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
CONFIG_RALINK=y
# CONFIG_RALINK_WDT is not set
+CONFIG_RANDSTRUCT_NONE=y
CONFIG_RATIONAL=y
CONFIG_REGMAP=y
CONFIG_REGMAP_I2C=y
CONFIG_WEAK_ORDERING=y
CONFIG_XPS=y
CONFIG_XXHASH=y
+CONFIG_ZBOOT_LOAD_ADDRESS=0x0
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y
+CONFIG_ZSTD_COMMON=y
CONFIG_ZSTD_COMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_AT803X_PHY=y
CONFIG_BLK_MQ_PCI=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
CONFIG_CEVT_R4K=y
CONFIG_CEVT_SYSTICK_QUIRK=y
CONFIG_CLKEVT_RT3352=y
CONFIG_CMDLINE_BOOL=y
# CONFIG_CMDLINE_OVERRIDE is not set
CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_CPU_GENERIC_DUMP_TLB=y
CONFIG_CPU_HAS_DIEI=y
CONFIG_CPU_SUPPORTS_MSA=y
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CSRC_R4K=y
+CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_PINCTRL=y
CONFIG_DMA_NONCOHERENT=y
# CONFIG_DTB_MT7620A_EVAL is not set
# CONFIG_DTB_VOCORE2 is not set
CONFIG_DTC=y
CONFIG_EARLY_PRINTK=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
CONFIG_FIXED_PHY=y
CONFIG_FWNODE_MDIO=y
CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC11_NO_ARRAY_BOUNDS=y
CONFIG_GENERIC_ATOMIC64=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_FIND_FIRST_BIT=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_IOMAP=y
CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_LIB_ASHLDI3=y
CONFIG_GENERIC_LIB_ASHRDI3=y
CONFIG_GPIO_GENERIC=y
CONFIG_GPIO_MT7621=y
# CONFIG_GPIO_RALINK is not set
-CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_HARDWARE_WATCHPOINTS=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
CONFIG_MIPS_CMDLINE_FROM_DTB=y
-CONFIG_MIPS_EBPF_JIT=y
CONFIG_MIPS_L1_CACHE_SHIFT=5
CONFIG_MIPS_LD_CAN_LINK_VDSO=y
# CONFIG_MIPS_NO_APPENDED_DTB is not set
CONFIG_NET_VENDOR_RALINK=y
CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_MDIO=y
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DRIVERS_LEGACY=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PGTABLE_LEVELS=2
CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
# CONFIG_PHY_MT7621_PCI is not set
CONFIG_PHY_RALINK_USB=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MT7620=y
CONFIG_PINCTRL_RALINK=y
# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PREEMPT_NONE_BUILD=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_QCOM_NET_PHYLIB=y
CONFIG_RALINK=y
# CONFIG_RALINK_WDT is not set
+CONFIG_RANDSTRUCT_NONE=y
CONFIG_RATIONAL=y
CONFIG_REGMAP=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_RESET_CONTROLLER=y
CONFIG_RTC_CLASS=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RTC_MC146818_LIB=y
CONFIG_SERIAL_8250_NR_UARTS=3
CONFIG_SERIAL_8250_RUNTIME_UARTS=3
CONFIG_SERIAL_MCTRL_GPIO=y
CONFIG_USB_SUPPORT=y
CONFIG_USE_OF=y
CONFIG_WATCHDOG_CORE=y
+CONFIG_ZBOOT_LOAD_ADDRESS=0x0
+++ /dev/null
-From f383b0770612838e78986231710c0a3afee4db42 Mon Sep 17 00:00:00 2001
-From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Date: Mon, 10 Jan 2022 12:49:27 +0100
-Subject: [PATCH 1/2] dt-bindings: reset: add dt binding header for Mediatek MT7621 resets
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Add dt binding header for resets lines in Mediatek MT7621 SoCs.
-
-Acked-by: Rob Herring <robh@kernel.org>
-Tested-by: Arınç ÜNAL <arinc.unal@arinc9.com>
-Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Link: https://lore.kernel.org/r/20220110114930.1406665-2-sergio.paracuellos@gmail.com
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- include/dt-bindings/reset/mt7621-reset.h | 37 ++++++++++++++++++++++++++++++++
- 1 file changed, 37 insertions(+)
- create mode 100644 include/dt-bindings/reset/mt7621-reset.h
-
---- /dev/null
-+++ b/include/dt-bindings/reset/mt7621-reset.h
-@@ -0,0 +1,37 @@
-+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
-+/*
-+ * Copyright (c) 2021 Sergio Paracuellos
-+ * Author: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-+ */
-+
-+#ifndef DT_BINDING_MT7621_RESET_H
-+#define DT_BINDING_MT7621_RESET_H
-+
-+#define MT7621_RST_SYS 0
-+#define MT7621_RST_MCM 2
-+#define MT7621_RST_HSDMA 5
-+#define MT7621_RST_FE 6
-+#define MT7621_RST_SPDIFTX 7
-+#define MT7621_RST_TIMER 8
-+#define MT7621_RST_INT 9
-+#define MT7621_RST_MC 10
-+#define MT7621_RST_PCM 11
-+#define MT7621_RST_PIO 13
-+#define MT7621_RST_GDMA 14
-+#define MT7621_RST_NFI 15
-+#define MT7621_RST_I2C 16
-+#define MT7621_RST_I2S 17
-+#define MT7621_RST_SPI 18
-+#define MT7621_RST_UART1 19
-+#define MT7621_RST_UART2 20
-+#define MT7621_RST_UART3 21
-+#define MT7621_RST_ETH 23
-+#define MT7621_RST_PCIE0 24
-+#define MT7621_RST_PCIE1 25
-+#define MT7621_RST_PCIE2 26
-+#define MT7621_RST_AUX_STCK 28
-+#define MT7621_RST_CRYPTO 29
-+#define MT7621_RST_SDXC 30
-+#define MT7621_RST_PPE 31
-+
-+#endif /* DT_BINDING_MT7621_RESET_H */
+++ /dev/null
-From 64b2d6ffff862c0e7278198b4229e42e1abb3bb1 Mon Sep 17 00:00:00 2001
-From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Date: Mon, 10 Jan 2022 12:49:30 +0100
-Subject: [PATCH 2/2] staging: mt7621-dts: align resets with binding documentation
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Binding documentation for compatible 'mediatek,mt7621-sysc' has been updated
-to be used as a reset provider. Align reset related bits and system controller
-node with binding documentation along the dtsi file.
-
-Tested-by: Arınç ÜNAL <arinc.unal@arinc9.com>
-Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
-Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Link: https://lore.kernel.org/r/20220110114930.1406665-5-sergio.paracuellos@gmail.com
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- drivers/staging/mt7621-dts/mt7621.dtsi | 21 +++++++++------------
- 1 file changed, 9 insertions(+), 12 deletions(-)
-
---- a/drivers/staging/mt7621-dts/mt7621.dtsi
-+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
-@@ -1,6 +1,7 @@
- #include <dt-bindings/interrupt-controller/mips-gic.h>
- #include <dt-bindings/gpio/gpio.h>
- #include <dt-bindings/clock/mt7621-clk.h>
-+#include <dt-bindings/reset/mt7621-reset.h>
-
- / {
- #address-cells = <1>;
-@@ -59,6 +60,7 @@
- compatible = "mediatek,mt7621-sysc", "syscon";
- reg = <0x0 0x100>;
- #clock-cells = <1>;
-+ #reset-cells = <1>;
- ralink,memctl = <&memc>;
- clock-output-names = "xtal", "cpu", "bus",
- "50m", "125m", "150m",
-@@ -88,7 +90,7 @@
-
- clocks = <&sysc MT7621_CLK_I2C>;
- clock-names = "i2c";
-- resets = <&rstctrl 16>;
-+ resets = <&sysc MT7621_RST_I2C>;
- reset-names = "i2c";
-
- #address-cells = <1>;
-@@ -161,7 +163,7 @@
- clocks = <&sysc MT7621_CLK_SPI>;
- clock-names = "spi";
-
-- resets = <&rstctrl 18>;
-+ resets = <&sysc MT7621_RST_SPI>;
- reset-names = "spi";
-
- #address-cells = <1>;
-@@ -296,11 +298,6 @@
- };
- };
-
-- rstctrl: rstctrl {
-- compatible = "ralink,rt2880-reset";
-- #reset-cells = <1>;
-- };
--
- sdhci: sdhci@1e130000 {
- status = "disabled";
-
-@@ -383,7 +380,7 @@
- #address-cells = <1>;
- #size-cells = <0>;
-
-- resets = <&rstctrl 6 &rstctrl 23>;
-+ resets = <&sysc MT7621_RST_FE &sysc MT7621_RST_ETH>;
- reset-names = "fe", "eth";
-
- interrupt-parent = <&gic>;
-@@ -423,7 +420,7 @@
- #size-cells = <0>;
- reg = <0>;
- mediatek,mcm;
-- resets = <&rstctrl 2>;
-+ resets = <&sysc MT7621_RST_MCM>;
- reset-names = "mcm";
- interrupt-controller;
- #interrupt-cells = <1>;
-@@ -516,7 +513,7 @@
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
-- resets = <&rstctrl 24>;
-+ resets = <&sysc MT7621_RST_PCIE0>;
- clocks = <&sysc MT7621_CLK_PCIE0>;
- phys = <&pcie0_phy 1>;
- phy-names = "pcie-phy0";
-@@ -531,7 +528,7 @@
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
-- resets = <&rstctrl 25>;
-+ resets = <&sysc MT7621_RST_PCIE1>;
- clocks = <&sysc MT7621_CLK_PCIE1>;
- phys = <&pcie0_phy 1>;
- phy-names = "pcie-phy1";
-@@ -546,7 +543,7 @@
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
-- resets = <&rstctrl 26>;
-+ resets = <&sysc MT7621_RST_PCIE2>;
- clocks = <&sysc MT7621_CLK_PCIE2>;
- phys = <&pcie2_phy 0>;
- phy-names = "pcie-phy2";
+++ /dev/null
-From 478b09fa2c00cbc40d25bc061befdf11f04a27ad Mon Sep 17 00:00:00 2001
-From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Date: Thu, 10 Feb 2022 10:48:58 +0100
-Subject: [PATCH 1/2] dt-bindings: clock: mediatek,mt7621-sysc: add '#reset-cells' property
-
-Make system controller a reset provider for all the peripherals in the
-MT7621 SoC adding '#reset-cells' property.
-
-Acked-by: Rob Herring <robh@kernel.org>
-Acked-by: Stephen Boyd <sboyd@kernel.org>
-Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Link: https://lore.kernel.org/r/20220210094859.927868-2-sergio.paracuellos@gmail.com
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- .../devicetree/bindings/clock/mediatek,mt7621-sysc.yaml | 12 ++++++++++++
- 1 file changed, 12 insertions(+)
-
---- a/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml
-+++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml
-@@ -22,6 +22,11 @@ description: |
-
- The clocks are provided inside a system controller node.
-
-+ This node is also a reset provider for all the peripherals.
-+
-+ Reset related bits are defined in:
-+ [2]: <include/dt-bindings/reset/mt7621-reset.h>.
-+
- properties:
- compatible:
- items:
-@@ -37,6 +42,12 @@ properties:
- clocks.
- const: 1
-
-+ "#reset-cells":
-+ description:
-+ The first cell indicates the reset bit within the register, see
-+ [2] for available resets.
-+ const: 1
-+
- ralink,memctl:
- $ref: /schemas/types.yaml#/definitions/phandle
- description:
-@@ -61,6 +72,7 @@ examples:
- compatible = "mediatek,mt7621-sysc", "syscon";
- reg = <0x0 0x100>;
- #clock-cells = <1>;
-+ #reset-cells = <1>;
- ralink,memctl = <&memc>;
- clock-output-names = "xtal", "cpu", "bus",
- "50m", "125m", "150m",
+++ /dev/null
-From 38a8553b0a22ed54f014d8402fedd268b529175c Mon Sep 17 00:00:00 2001
-From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Date: Thu, 10 Feb 2022 10:48:59 +0100
-Subject: [PATCH 2/2] clk: ralink: make system controller node a reset provider
-
-MT7621 system controller node is already providing the clocks for the whole
-system but must also serve as a reset provider. Hence, add reset controller
-related code to the clock driver itself. To get resets properly ready for
-the rest of the world we need to move platform driver initialization process
-to 'arch_initcall'.
-
-CC: Philipp Zabel <p.zabel@pengutronix.de>
-Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
-Acked-by: Stephen Boyd <sboyd@kernel.org>
-Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Link: https://lore.kernel.org/r/20220210094859.927868-3-sergio.paracuellos@gmail.com
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- drivers/clk/ralink/clk-mt7621.c | 92 ++++++++++++++++++++++++++++++++++++++++-
- 1 file changed, 91 insertions(+), 1 deletion(-)
-
---- a/drivers/clk/ralink/clk-mt7621.c
-+++ b/drivers/clk/ralink/clk-mt7621.c
-@@ -11,14 +11,17 @@
- #include <linux/mfd/syscon.h>
- #include <linux/platform_device.h>
- #include <linux/regmap.h>
-+#include <linux/reset-controller.h>
- #include <linux/slab.h>
- #include <dt-bindings/clock/mt7621-clk.h>
-+#include <dt-bindings/reset/mt7621-reset.h>
-
- /* Configuration registers */
- #define SYSC_REG_SYSTEM_CONFIG0 0x10
- #define SYSC_REG_SYSTEM_CONFIG1 0x14
- #define SYSC_REG_CLKCFG0 0x2c
- #define SYSC_REG_CLKCFG1 0x30
-+#define SYSC_REG_RESET_CTRL 0x34
- #define SYSC_REG_CUR_CLK_STS 0x44
- #define MEMC_REG_CPU_PLL 0x648
-
-@@ -398,6 +401,82 @@ free_clk_priv:
- }
- CLK_OF_DECLARE_DRIVER(mt7621_clk, "mediatek,mt7621-sysc", mt7621_clk_init);
-
-+struct mt7621_rst {
-+ struct reset_controller_dev rcdev;
-+ struct regmap *sysc;
-+};
-+
-+static struct mt7621_rst *to_mt7621_rst(struct reset_controller_dev *dev)
-+{
-+ return container_of(dev, struct mt7621_rst, rcdev);
-+}
-+
-+static int mt7621_assert_device(struct reset_controller_dev *rcdev,
-+ unsigned long id)
-+{
-+ struct mt7621_rst *data = to_mt7621_rst(rcdev);
-+ struct regmap *sysc = data->sysc;
-+
-+ return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), BIT(id));
-+}
-+
-+static int mt7621_deassert_device(struct reset_controller_dev *rcdev,
-+ unsigned long id)
-+{
-+ struct mt7621_rst *data = to_mt7621_rst(rcdev);
-+ struct regmap *sysc = data->sysc;
-+
-+ return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), 0);
-+}
-+
-+static int mt7621_reset_device(struct reset_controller_dev *rcdev,
-+ unsigned long id)
-+{
-+ int ret;
-+
-+ ret = mt7621_assert_device(rcdev, id);
-+ if (ret < 0)
-+ return ret;
-+
-+ return mt7621_deassert_device(rcdev, id);
-+}
-+
-+static int mt7621_rst_xlate(struct reset_controller_dev *rcdev,
-+ const struct of_phandle_args *reset_spec)
-+{
-+ unsigned long id = reset_spec->args[0];
-+
-+ if (id == MT7621_RST_SYS || id >= rcdev->nr_resets)
-+ return -EINVAL;
-+
-+ return id;
-+}
-+
-+static const struct reset_control_ops reset_ops = {
-+ .reset = mt7621_reset_device,
-+ .assert = mt7621_assert_device,
-+ .deassert = mt7621_deassert_device
-+};
-+
-+static int mt7621_reset_init(struct device *dev, struct regmap *sysc)
-+{
-+ struct mt7621_rst *rst_data;
-+
-+ rst_data = devm_kzalloc(dev, sizeof(*rst_data), GFP_KERNEL);
-+ if (!rst_data)
-+ return -ENOMEM;
-+
-+ rst_data->sysc = sysc;
-+ rst_data->rcdev.ops = &reset_ops;
-+ rst_data->rcdev.owner = THIS_MODULE;
-+ rst_data->rcdev.nr_resets = 32;
-+ rst_data->rcdev.of_reset_n_cells = 1;
-+ rst_data->rcdev.of_xlate = mt7621_rst_xlate;
-+ rst_data->rcdev.of_node = dev_of_node(dev);
-+
-+ return devm_reset_controller_register(dev, &rst_data->rcdev);
-+}
-+
- static int mt7621_clk_probe(struct platform_device *pdev)
- {
- struct device_node *np = pdev->dev.of_node;
-@@ -424,6 +503,12 @@ static int mt7621_clk_probe(struct platf
- return ret;
- }
-
-+ ret = mt7621_reset_init(dev, priv->sysc);
-+ if (ret) {
-+ dev_err(dev, "Could not init reset controller\n");
-+ return ret;
-+ }
-+
- count = ARRAY_SIZE(mt7621_clks_base) +
- ARRAY_SIZE(mt7621_fixed_clks) + ARRAY_SIZE(mt7621_gates);
- clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, count),
-@@ -485,4 +570,9 @@ static struct platform_driver mt7621_clk
- .of_match_table = mt7621_clk_of_match,
- },
- };
--builtin_platform_driver(mt7621_clk_driver);
-+
-+static int __init mt7621_clk_reset_init(void)
-+{
-+ return platform_driver_register(&mt7621_clk_driver);
-+}
-+arch_initcall(mt7621_clk_reset_init);
+++ /dev/null
-From bb3ababe7f986900672e0048153c31aa4a21f96b Mon Sep 17 00:00:00 2001
-From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Date: Sat, 17 Dec 2022 08:48:06 +0100
-Subject: [PATCH] MIPS: ralink: mt7621: avoid to init common ralink reset controller
-
-[ Upstream commit 76ce51798cb16738a4a28a6662e7344aaf7ef769 ]
-
-Commit 38a8553b0a22 ("clk: ralink: make system controller node a reset provider")
-make system controller a reset provider for mt7621 ralink SoCs. Ralink init code
-also tries to start previous common reset controller which at the end tries to
-find device tree node 'ralink,rt2880-reset'. mt7621 device tree file is not
-using at all this node anymore. Hence avoid to init this common reset controller
-for mt7621 ralink SoCs to avoid 'Failed to find reset controller node' boot
-error trace error.
-
-Fixes: 64b2d6ffff86 ("staging: mt7621-dts: align resets with binding documentation")
-Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
-Signed-off-by: Sasha Levin <sashal@kernel.org>
----
- arch/mips/ralink/of.c | 4 +++-
- 1 file changed, 3 insertions(+), 1 deletion(-)
-
---- a/arch/mips/ralink/of.c
-+++ b/arch/mips/ralink/of.c
-@@ -21,6 +21,7 @@
- #include <asm/bootinfo.h>
- #include <asm/addrspace.h>
- #include <asm/prom.h>
-+#include <asm/mach-ralink/ralink_regs.h>
-
- #include "common.h"
-
-@@ -95,7 +96,8 @@ static int __init plat_of_setup(void)
- __dt_register_buses(soc_info.compatible, "palmbus");
-
- /* make sure that the reset controller is setup early */
-- ralink_rst_init();
-+ if (ralink_soc != MT762X_SOC_MT7621AT)
-+ ralink_rst_init();
-
- return 0;
- }
__iomem void *plat_of_remap_node(const char *node);
--- a/arch/mips/ralink/of.c
+++ b/arch/mips/ralink/of.c
-@@ -95,10 +95,6 @@ static int __init plat_of_setup(void)
+@@ -81,10 +81,6 @@ static int __init plat_of_setup(void)
{
__dt_register_buses(soc_info.compatible, "palmbus");
--- a/MAINTAINERS
+++ b/MAINTAINERS
-@@ -11859,6 +11859,12 @@ S: Maintained
+@@ -13012,6 +13012,12 @@ S: Maintained
F: Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml
F: drivers/clk/ralink/clk-mt7621.c
{
--- a/arch/mips/ralink/mt7621.c
+++ b/arch/mips/ralink/mt7621.c
-@@ -58,15 +58,6 @@ static void __init mt7621_memory_detect(
+@@ -89,15 +89,6 @@ static void __init mt7621_memory_detect(
memblock_add(MT7621_HIGHMEM_BASE, MT7621_HIGHMEM_SIZE);
}
return __raw_readl(MT7621_SYSC_BASE + SYSC_REG_CHIP_NAME0);
--- a/arch/mips/ralink/of.c
+++ b/arch/mips/ralink/of.c
-@@ -29,26 +29,56 @@ __iomem void *rt_sysc_membase;
+@@ -29,28 +29,56 @@ __iomem void *rt_sysc_membase;
__iomem void *rt_memc_membase;
EXPORT_SYMBOL_GPL(rt_sysc_membase);
if (of_address_to_resource(np, 0, &res))
- panic("Failed to get resource for %s", node);
+-
+- of_node_put(np);
+ panic("Failed to get resource for %s node", np->name);
if (!request_mem_region(res.start,
+ panic("Failed to remap core resources");
+}
+
- void __init device_tree_init(void)
+ void __init plat_mem_setup(void)
{
- unflatten_and_copy_device_tree();
+ void *dtb;
--- a/arch/mips/ralink/rt288x.c
+++ b/arch/mips/ralink/rt288x.c
@@ -17,15 +17,6 @@
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
-@@ -1799,7 +1799,9 @@ config RALINK_WDT
+@@ -1865,7 +1865,9 @@ config GXP_WATCHDOG
config MT7621_WDT
tristate "Mediatek SoC watchdog"
select WATCHDOG_CORE
+++ /dev/null
-From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Date: Wed, 22 Sep 2021 07:00:34 +0200
-Subject: [PATCH] PCI: mt7621: Add MediaTek MT7621 PCIe host controller driver
-
-Add driver for the PCIe controller of the MT7621 SoC.
-
-[bhelgaas: rename from pci-mt7621.c to pcie-mt7621.c; also rename Kconfig
-symbol from PCI_MT7621 to PCIE_MT7621]
-Link: https://lore.kernel.org/r/20210922050035.18162-3-sergio.paracuellos@gmail.com
-Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
-Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- rename drivers/{staging/mt7621-pci/pci-mt7621.c => pci/controller/pcie-mt7621.c} (95%)
- delete mode 100644 drivers/staging/mt7621-pci/Kconfig
- delete mode 100644 drivers/staging/mt7621-pci/Makefile
- delete mode 100644 drivers/staging/mt7621-pci/TODO
- delete mode 100644 drivers/staging/mt7621-pci/mediatek,mt7621-pci.txt
-
---- a/arch/mips/ralink/Kconfig
-+++ b/arch/mips/ralink/Kconfig
-@@ -51,7 +51,8 @@ choice
- select SYS_SUPPORTS_HIGHMEM
- select MIPS_GIC
- select CLKSRC_MIPS_GIC
-- select HAVE_PCI if PCI_MT7621
-+ select HAVE_PCI
-+ select PCI_DRIVERS_GENERIC
- select SOC_BUS
- endchoice
-
---- a/drivers/pci/controller/Kconfig
-+++ b/drivers/pci/controller/Kconfig
-@@ -312,6 +312,14 @@ config PCIE_HISI_ERR
- Say Y here if you want error handling support
- for the PCIe controller's errors on HiSilicon HIP SoCs
-
-+config PCIE_MT7621
-+ tristate "MediaTek MT7621 PCIe Controller"
-+ depends on (RALINK && SOC_MT7621) || (MIPS && COMPILE_TEST)
-+ select PHY_MT7621_PCI
-+ default SOC_MT7621
-+ help
-+ This selects a driver for the MediaTek MT7621 PCIe Controller.
-+
- source "drivers/pci/controller/dwc/Kconfig"
- source "drivers/pci/controller/mobiveil/Kconfig"
- source "drivers/pci/controller/cadence/Kconfig"
---- a/drivers/pci/controller/Makefile
-+++ b/drivers/pci/controller/Makefile
-@@ -37,6 +37,8 @@ obj-$(CONFIG_VMD) += vmd.o
- obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
- obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o
- obj-$(CONFIG_PCIE_HISI_ERR) += pcie-hisi-error.o
-+obj-$(CONFIG_PCIE_MT7621) += pcie-mt7621.o
-+
- # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
- obj-y += dwc/
- obj-y += mobiveil/
---- a/drivers/staging/Kconfig
-+++ b/drivers/staging/Kconfig
-@@ -86,8 +86,6 @@ source "drivers/staging/vc04_services/Kc
-
- source "drivers/staging/pi433/Kconfig"
-
--source "drivers/staging/mt7621-pci/Kconfig"
--
- source "drivers/staging/mt7621-dma/Kconfig"
-
- source "drivers/staging/ralink-gdma/Kconfig"
---- a/drivers/staging/Makefile
-+++ b/drivers/staging/Makefile
-@@ -33,7 +33,6 @@ obj-$(CONFIG_KS7010) += ks7010/
- obj-$(CONFIG_GREYBUS) += greybus/
- obj-$(CONFIG_BCM2835_VCHIQ) += vc04_services/
- obj-$(CONFIG_PI433) += pi433/
--obj-$(CONFIG_PCI_MT7621) += mt7621-pci/
- obj-$(CONFIG_SOC_MT7621) += mt7621-dma/
- obj-$(CONFIG_DMA_RALINK) += ralink-gdma/
- obj-$(CONFIG_SOC_MT7621) += mt7621-dts/
---- a/drivers/staging/mt7621-pci/Kconfig
-+++ /dev/null
-@@ -1,8 +0,0 @@
--# SPDX-License-Identifier: GPL-2.0
--config PCI_MT7621
-- tristate "MediaTek MT7621 PCI Controller"
-- depends on RALINK
-- select PCI_DRIVERS_GENERIC
-- help
-- This selects a driver for the MediaTek MT7621 PCI Controller.
--
---- a/drivers/staging/mt7621-pci/Makefile
-+++ /dev/null
-@@ -1,2 +0,0 @@
--# SPDX-License-Identifier: GPL-2.0
--obj-$(CONFIG_PCI_MT7621) += pci-mt7621.o
---- a/drivers/staging/mt7621-pci/TODO
-+++ /dev/null
-@@ -1,4 +0,0 @@
--
--- general code review and cleanup
--
--Cc: NeilBrown <neil@brown.name>
---- a/drivers/staging/mt7621-pci/mediatek,mt7621-pci.txt
-+++ /dev/null
-@@ -1,104 +0,0 @@
--MediaTek MT7621 PCIe controller
--
--Required properties:
--- compatible: "mediatek,mt7621-pci"
--- device_type: Must be "pci"
--- reg: Base addresses and lengths of the PCIe subsys and root ports.
--- bus-range: Range of bus numbers associated with this controller.
--- #address-cells: Address representation for root ports (must be 3)
--- pinctrl-names : The pin control state names.
--- pinctrl-0: The "default" pinctrl state.
--- #size-cells: Size representation for root ports (must be 2)
--- ranges: Ranges for the PCI memory and I/O regions.
--- #interrupt-cells: Must be 1
--- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties.
-- Please refer to the standard PCI bus binding document for a more detailed
-- explanation.
--- status: either "disabled" or "okay".
--- resets: Must contain an entry for each entry in reset-names.
-- See ../reset/reset.txt for details.
--- reset-names: Must be "pcie0", "pcie1", "pcieN"... based on the number of
-- root ports.
--- clocks: Must contain an entry for each entry in clock-names.
-- See ../clocks/clock-bindings.txt for details.
--- clock-names: Must be "pcie0", "pcie1", "pcieN"... based on the number of
-- root ports.
--- reset-gpios: GPIO specs for the reset pins.
--
--In addition, the device tree node must have sub-nodes describing each PCIe port
--interface, having the following mandatory properties:
--
--Required properties:
--- reg: Only the first four bytes are used to refer to the correct bus number
-- and device number.
--- #address-cells: Must be 3
--- #size-cells: Must be 2
--- ranges: Sub-ranges distributed from the PCIe controller node. An empty
-- property is sufficient.
--- bus-range: Range of bus numbers associated with this port.
--
--Example for MT7621:
--
-- pcie: pcie@1e140000 {
-- compatible = "mediatek,mt7621-pci";
-- reg = <0x1e140000 0x100 /* host-pci bridge registers */
-- 0x1e142000 0x100 /* pcie port 0 RC control registers */
-- 0x1e143000 0x100 /* pcie port 1 RC control registers */
-- 0x1e144000 0x100>; /* pcie port 2 RC control registers */
--
-- #address-cells = <3>;
-- #size-cells = <2>;
--
-- pinctrl-names = "default";
-- pinctrl-0 = <&pcie_pins>;
--
-- device_type = "pci";
--
-- bus-range = <0 255>;
-- ranges = <
-- 0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
-- 0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
-- >;
--
-- #interrupt-cells = <1>;
-- interrupt-map-mask = <0xF0000 0 0 1>;
-- interrupt-map = <0x10000 0 0 1 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
-- <0x20000 0 0 1 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
-- <0x30000 0 0 1 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
--
-- status = "disabled";
--
-- resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
-- reset-names = "pcie0", "pcie1", "pcie2";
-- clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
-- clock-names = "pcie0", "pcie1", "pcie2";
--
-- reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>,
-- <&gpio 8 GPIO_ACTIVE_LOW>,
-- <&gpio 7 GPIO_ACTIVE_LOW>;
--
-- pcie@0,0 {
-- reg = <0x0000 0 0 0 0>;
-- #address-cells = <3>;
-- #size-cells = <2>;
-- ranges;
-- bus-range = <0x00 0xff>;
-- };
--
-- pcie@1,0 {
-- reg = <0x0800 0 0 0 0>;
-- #address-cells = <3>;
-- #size-cells = <2>;
-- ranges;
-- bus-range = <0x00 0xff>;
-- };
--
-- pcie@2,0 {
-- reg = <0x1000 0 0 0 0>;
-- #address-cells = <3>;
-- #size-cells = <2>;
-- ranges;
-- bus-range = <0x00 0xff>;
-- };
-- };
--
---- a/drivers/staging/mt7621-pci/pci-mt7621.c
-+++ /dev/null
-@@ -1,601 +0,0 @@
--// SPDX-License-Identifier: GPL-2.0+
--/*
-- * BRIEF MODULE DESCRIPTION
-- * PCI init for Ralink RT2880 solution
-- *
-- * Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
-- *
-- * May 2007 Bruce Chang
-- * Initial Release
-- *
-- * May 2009 Bruce Chang
-- * support RT2880/RT3883 PCIe
-- *
-- * May 2011 Bruce Chang
-- * support RT6855/MT7620 PCIe
-- */
--
--#include <linux/bitops.h>
--#include <linux/clk.h>
--#include <linux/delay.h>
--#include <linux/gpio/consumer.h>
--#include <linux/module.h>
--#include <linux/of.h>
--#include <linux/of_address.h>
--#include <linux/of_pci.h>
--#include <linux/of_platform.h>
--#include <linux/pci.h>
--#include <linux/phy/phy.h>
--#include <linux/platform_device.h>
--#include <linux/reset.h>
--#include <linux/sys_soc.h>
--
--/* MediaTek specific configuration registers */
--#define PCIE_FTS_NUM 0x70c
--#define PCIE_FTS_NUM_MASK GENMASK(15, 8)
--#define PCIE_FTS_NUM_L0(x) (((x) & 0xff) << 8)
--
--/* Host-PCI bridge registers */
--#define RALINK_PCI_PCICFG_ADDR 0x0000
--#define RALINK_PCI_PCIMSK_ADDR 0x000C
--#define RALINK_PCI_CONFIG_ADDR 0x0020
--#define RALINK_PCI_CONFIG_DATA 0x0024
--#define RALINK_PCI_MEMBASE 0x0028
--#define RALINK_PCI_IOBASE 0x002C
--
--/* PCIe RC control registers */
--#define RALINK_PCI_ID 0x0030
--#define RALINK_PCI_CLASS 0x0034
--#define RALINK_PCI_SUBID 0x0038
--#define RALINK_PCI_STATUS 0x0050
--
--/* Some definition values */
--#define PCIE_REVISION_ID BIT(0)
--#define PCIE_CLASS_CODE (0x60400 << 8)
--#define PCIE_BAR_MAP_MAX GENMASK(30, 16)
--#define PCIE_BAR_ENABLE BIT(0)
--#define PCIE_PORT_INT_EN(x) BIT(20 + (x))
--#define PCIE_PORT_LINKUP BIT(0)
--#define PCIE_PORT_CNT 3
--
--#define PERST_DELAY_MS 100
--
--/**
-- * struct mt7621_pcie_port - PCIe port information
-- * @base: I/O mapped register base
-- * @list: port list
-- * @pcie: pointer to PCIe host info
-- * @clk: pointer to the port clock gate
-- * @phy: pointer to PHY control block
-- * @pcie_rst: pointer to port reset control
-- * @gpio_rst: gpio reset
-- * @slot: port slot
-- * @enabled: indicates if port is enabled
-- */
--struct mt7621_pcie_port {
-- void __iomem *base;
-- struct list_head list;
-- struct mt7621_pcie *pcie;
-- struct clk *clk;
-- struct phy *phy;
-- struct reset_control *pcie_rst;
-- struct gpio_desc *gpio_rst;
-- u32 slot;
-- bool enabled;
--};
--
--/**
-- * struct mt7621_pcie - PCIe host information
-- * @base: IO Mapped Register Base
-- * @dev: Pointer to PCIe device
-- * @ports: pointer to PCIe port information
-- * @resets_inverted: depends on chip revision
-- * reset lines are inverted.
-- */
--struct mt7621_pcie {
-- struct device *dev;
-- void __iomem *base;
-- struct list_head ports;
-- bool resets_inverted;
--};
--
--static inline u32 pcie_read(struct mt7621_pcie *pcie, u32 reg)
--{
-- return readl_relaxed(pcie->base + reg);
--}
--
--static inline void pcie_write(struct mt7621_pcie *pcie, u32 val, u32 reg)
--{
-- writel_relaxed(val, pcie->base + reg);
--}
--
--static inline void pcie_rmw(struct mt7621_pcie *pcie, u32 reg, u32 clr, u32 set)
--{
-- u32 val = readl_relaxed(pcie->base + reg);
--
-- val &= ~clr;
-- val |= set;
-- writel_relaxed(val, pcie->base + reg);
--}
--
--static inline u32 pcie_port_read(struct mt7621_pcie_port *port, u32 reg)
--{
-- return readl_relaxed(port->base + reg);
--}
--
--static inline void pcie_port_write(struct mt7621_pcie_port *port,
-- u32 val, u32 reg)
--{
-- writel_relaxed(val, port->base + reg);
--}
--
--static inline u32 mt7621_pcie_get_cfgaddr(unsigned int bus, unsigned int slot,
-- unsigned int func, unsigned int where)
--{
-- return (((where & 0xF00) >> 8) << 24) | (bus << 16) | (slot << 11) |
-- (func << 8) | (where & 0xfc) | 0x80000000;
--}
--
--static void __iomem *mt7621_pcie_map_bus(struct pci_bus *bus,
-- unsigned int devfn, int where)
--{
-- struct mt7621_pcie *pcie = bus->sysdata;
-- u32 address = mt7621_pcie_get_cfgaddr(bus->number, PCI_SLOT(devfn),
-- PCI_FUNC(devfn), where);
--
-- writel_relaxed(address, pcie->base + RALINK_PCI_CONFIG_ADDR);
--
-- return pcie->base + RALINK_PCI_CONFIG_DATA + (where & 3);
--}
--
--struct pci_ops mt7621_pcie_ops = {
-- .map_bus = mt7621_pcie_map_bus,
-- .read = pci_generic_config_read,
-- .write = pci_generic_config_write,
--};
--
--static u32 read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg)
--{
-- u32 address = mt7621_pcie_get_cfgaddr(0, dev, 0, reg);
--
-- pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
-- return pcie_read(pcie, RALINK_PCI_CONFIG_DATA);
--}
--
--static void write_config(struct mt7621_pcie *pcie, unsigned int dev,
-- u32 reg, u32 val)
--{
-- u32 address = mt7621_pcie_get_cfgaddr(0, dev, 0, reg);
--
-- pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
-- pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA);
--}
--
--static inline void mt7621_rst_gpio_pcie_assert(struct mt7621_pcie_port *port)
--{
-- if (port->gpio_rst)
-- gpiod_set_value(port->gpio_rst, 1);
--}
--
--static inline void mt7621_rst_gpio_pcie_deassert(struct mt7621_pcie_port *port)
--{
-- if (port->gpio_rst)
-- gpiod_set_value(port->gpio_rst, 0);
--}
--
--static inline bool mt7621_pcie_port_is_linkup(struct mt7621_pcie_port *port)
--{
-- return (pcie_port_read(port, RALINK_PCI_STATUS) & PCIE_PORT_LINKUP) != 0;
--}
--
--static inline void mt7621_control_assert(struct mt7621_pcie_port *port)
--{
-- struct mt7621_pcie *pcie = port->pcie;
--
-- if (pcie->resets_inverted)
-- reset_control_assert(port->pcie_rst);
-- else
-- reset_control_deassert(port->pcie_rst);
--}
--
--static inline void mt7621_control_deassert(struct mt7621_pcie_port *port)
--{
-- struct mt7621_pcie *pcie = port->pcie;
--
-- if (pcie->resets_inverted)
-- reset_control_deassert(port->pcie_rst);
-- else
-- reset_control_assert(port->pcie_rst);
--}
--
--static int setup_cm_memory_region(struct pci_host_bridge *host)
--{
-- struct mt7621_pcie *pcie = pci_host_bridge_priv(host);
-- struct device *dev = pcie->dev;
-- struct resource_entry *entry;
-- resource_size_t mask;
--
-- entry = resource_list_first_type(&host->windows, IORESOURCE_MEM);
-- if (!entry) {
-- dev_err(dev, "Cannot get memory resource\n");
-- return -EINVAL;
-- }
--
-- if (mips_cps_numiocu(0)) {
-- /*
-- * FIXME: hardware doesn't accept mask values with 1s after
-- * 0s (e.g. 0xffef), so it would be great to warn if that's
-- * about to happen
-- */
-- mask = ~(entry->res->end - entry->res->start);
--
-- write_gcr_reg1_base(entry->res->start);
-- write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
-- dev_info(dev, "PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n",
-- (unsigned long long)read_gcr_reg1_base(),
-- (unsigned long long)read_gcr_reg1_mask());
-- }
--
-- return 0;
--}
--
--static int mt7621_pcie_parse_port(struct mt7621_pcie *pcie,
-- struct device_node *node,
-- int slot)
--{
-- struct mt7621_pcie_port *port;
-- struct device *dev = pcie->dev;
-- struct platform_device *pdev = to_platform_device(dev);
-- char name[10];
-- int err;
--
-- port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
-- if (!port)
-- return -ENOMEM;
--
-- port->base = devm_platform_ioremap_resource(pdev, slot + 1);
-- if (IS_ERR(port->base))
-- return PTR_ERR(port->base);
--
-- port->clk = devm_get_clk_from_child(dev, node, NULL);
-- if (IS_ERR(port->clk)) {
-- dev_err(dev, "failed to get pcie%d clock\n", slot);
-- return PTR_ERR(port->clk);
-- }
--
-- port->pcie_rst = of_reset_control_get_exclusive(node, NULL);
-- if (PTR_ERR(port->pcie_rst) == -EPROBE_DEFER) {
-- dev_err(dev, "failed to get pcie%d reset control\n", slot);
-- return PTR_ERR(port->pcie_rst);
-- }
--
-- snprintf(name, sizeof(name), "pcie-phy%d", slot);
-- port->phy = devm_of_phy_get(dev, node, name);
-- if (IS_ERR(port->phy)) {
-- dev_err(dev, "failed to get pcie-phy%d\n", slot);
-- err = PTR_ERR(port->phy);
-- goto remove_reset;
-- }
--
-- port->gpio_rst = devm_gpiod_get_index_optional(dev, "reset", slot,
-- GPIOD_OUT_LOW);
-- if (IS_ERR(port->gpio_rst)) {
-- dev_err(dev, "Failed to get GPIO for PCIe%d\n", slot);
-- err = PTR_ERR(port->gpio_rst);
-- goto remove_reset;
-- }
--
-- port->slot = slot;
-- port->pcie = pcie;
--
-- INIT_LIST_HEAD(&port->list);
-- list_add_tail(&port->list, &pcie->ports);
--
-- return 0;
--
--remove_reset:
-- reset_control_put(port->pcie_rst);
-- return err;
--}
--
--static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)
--{
-- struct device *dev = pcie->dev;
-- struct platform_device *pdev = to_platform_device(dev);
-- struct device_node *node = dev->of_node, *child;
-- int err;
--
-- pcie->base = devm_platform_ioremap_resource(pdev, 0);
-- if (IS_ERR(pcie->base))
-- return PTR_ERR(pcie->base);
--
-- for_each_available_child_of_node(node, child) {
-- int slot;
--
-- err = of_pci_get_devfn(child);
-- if (err < 0) {
-- of_node_put(child);
-- dev_err(dev, "failed to parse devfn: %d\n", err);
-- return err;
-- }
--
-- slot = PCI_SLOT(err);
--
-- err = mt7621_pcie_parse_port(pcie, child, slot);
-- if (err) {
-- of_node_put(child);
-- return err;
-- }
-- }
--
-- return 0;
--}
--
--static int mt7621_pcie_init_port(struct mt7621_pcie_port *port)
--{
-- struct mt7621_pcie *pcie = port->pcie;
-- struct device *dev = pcie->dev;
-- u32 slot = port->slot;
-- int err;
--
-- err = phy_init(port->phy);
-- if (err) {
-- dev_err(dev, "failed to initialize port%d phy\n", slot);
-- return err;
-- }
--
-- err = phy_power_on(port->phy);
-- if (err) {
-- dev_err(dev, "failed to power on port%d phy\n", slot);
-- phy_exit(port->phy);
-- return err;
-- }
--
-- port->enabled = true;
--
-- return 0;
--}
--
--static void mt7621_pcie_reset_assert(struct mt7621_pcie *pcie)
--{
-- struct mt7621_pcie_port *port;
--
-- list_for_each_entry(port, &pcie->ports, list) {
-- /* PCIe RC reset assert */
-- mt7621_control_assert(port);
--
-- /* PCIe EP reset assert */
-- mt7621_rst_gpio_pcie_assert(port);
-- }
--
-- msleep(PERST_DELAY_MS);
--}
--
--static void mt7621_pcie_reset_rc_deassert(struct mt7621_pcie *pcie)
--{
-- struct mt7621_pcie_port *port;
--
-- list_for_each_entry(port, &pcie->ports, list)
-- mt7621_control_deassert(port);
--}
--
--static void mt7621_pcie_reset_ep_deassert(struct mt7621_pcie *pcie)
--{
-- struct mt7621_pcie_port *port;
--
-- list_for_each_entry(port, &pcie->ports, list)
-- mt7621_rst_gpio_pcie_deassert(port);
--
-- msleep(PERST_DELAY_MS);
--}
--
--static int mt7621_pcie_init_ports(struct mt7621_pcie *pcie)
--{
-- struct device *dev = pcie->dev;
-- struct mt7621_pcie_port *port, *tmp;
-- u8 num_disabled = 0;
-- int err;
--
-- mt7621_pcie_reset_assert(pcie);
-- mt7621_pcie_reset_rc_deassert(pcie);
--
-- list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
-- u32 slot = port->slot;
--
-- if (slot == 1) {
-- port->enabled = true;
-- continue;
-- }
--
-- err = mt7621_pcie_init_port(port);
-- if (err) {
-- dev_err(dev, "Initiating port %d failed\n", slot);
-- list_del(&port->list);
-- }
-- }
--
-- mt7621_pcie_reset_ep_deassert(pcie);
--
-- tmp = NULL;
-- list_for_each_entry(port, &pcie->ports, list) {
-- u32 slot = port->slot;
--
-- if (!mt7621_pcie_port_is_linkup(port)) {
-- dev_err(dev, "pcie%d no card, disable it (RST & CLK)\n",
-- slot);
-- mt7621_control_assert(port);
-- port->enabled = false;
-- num_disabled++;
--
-- if (slot == 0) {
-- tmp = port;
-- continue;
-- }
--
-- if (slot == 1 && tmp && !tmp->enabled)
-- phy_power_off(tmp->phy);
-- }
-- }
--
-- return (num_disabled != PCIE_PORT_CNT) ? 0 : -ENODEV;
--}
--
--static void mt7621_pcie_enable_port(struct mt7621_pcie_port *port)
--{
-- struct mt7621_pcie *pcie = port->pcie;
-- u32 slot = port->slot;
-- u32 val;
--
-- /* enable pcie interrupt */
-- val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
-- val |= PCIE_PORT_INT_EN(slot);
-- pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
--
-- /* map 2G DDR region */
-- pcie_port_write(port, PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
-- PCI_BASE_ADDRESS_0);
--
-- /* configure class code and revision ID */
-- pcie_port_write(port, PCIE_CLASS_CODE | PCIE_REVISION_ID,
-- RALINK_PCI_CLASS);
--
-- /* configure RC FTS number to 250 when it leaves L0s */
-- val = read_config(pcie, slot, PCIE_FTS_NUM);
-- val &= ~PCIE_FTS_NUM_MASK;
-- val |= PCIE_FTS_NUM_L0(0x50);
-- write_config(pcie, slot, PCIE_FTS_NUM, val);
--}
--
--static int mt7621_pcie_enable_ports(struct pci_host_bridge *host)
--{
-- struct mt7621_pcie *pcie = pci_host_bridge_priv(host);
-- struct device *dev = pcie->dev;
-- struct mt7621_pcie_port *port;
-- struct resource_entry *entry;
-- int err;
--
-- entry = resource_list_first_type(&host->windows, IORESOURCE_IO);
-- if (!entry) {
-- dev_err(dev, "Cannot get io resource\n");
-- return -EINVAL;
-- }
--
-- /* Setup MEMWIN and IOWIN */
-- pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE);
-- pcie_write(pcie, entry->res->start, RALINK_PCI_IOBASE);
--
-- list_for_each_entry(port, &pcie->ports, list) {
-- if (port->enabled) {
-- err = clk_prepare_enable(port->clk);
-- if (err) {
-- dev_err(dev, "enabling clk pcie%d\n",
-- port->slot);
-- return err;
-- }
--
-- mt7621_pcie_enable_port(port);
-- dev_info(dev, "PCIE%d enabled\n", port->slot);
-- }
-- }
--
-- return 0;
--}
--
--static int mt7621_pcie_register_host(struct pci_host_bridge *host)
--{
-- struct mt7621_pcie *pcie = pci_host_bridge_priv(host);
--
-- host->ops = &mt7621_pcie_ops;
-- host->sysdata = pcie;
-- return pci_host_probe(host);
--}
--
--static const struct soc_device_attribute mt7621_pcie_quirks_match[] = {
-- { .soc_id = "mt7621", .revision = "E2" },
-- { /* sentinel */ }
--};
--
--static int mt7621_pcie_probe(struct platform_device *pdev)
--{
-- struct device *dev = &pdev->dev;
-- const struct soc_device_attribute *attr;
-- struct mt7621_pcie_port *port;
-- struct mt7621_pcie *pcie;
-- struct pci_host_bridge *bridge;
-- int err;
--
-- if (!dev->of_node)
-- return -ENODEV;
--
-- bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
-- if (!bridge)
-- return -ENOMEM;
--
-- pcie = pci_host_bridge_priv(bridge);
-- pcie->dev = dev;
-- platform_set_drvdata(pdev, pcie);
-- INIT_LIST_HEAD(&pcie->ports);
--
-- attr = soc_device_match(mt7621_pcie_quirks_match);
-- if (attr)
-- pcie->resets_inverted = true;
--
-- err = mt7621_pcie_parse_dt(pcie);
-- if (err) {
-- dev_err(dev, "Parsing DT failed\n");
-- return err;
-- }
--
-- err = mt7621_pcie_init_ports(pcie);
-- if (err) {
-- dev_err(dev, "Nothing connected in virtual bridges\n");
-- return 0;
-- }
--
-- err = mt7621_pcie_enable_ports(bridge);
-- if (err) {
-- dev_err(dev, "Error enabling pcie ports\n");
-- goto remove_resets;
-- }
--
-- err = setup_cm_memory_region(bridge);
-- if (err) {
-- dev_err(dev, "Error setting up iocu mem regions\n");
-- goto remove_resets;
-- }
--
-- return mt7621_pcie_register_host(bridge);
--
--remove_resets:
-- list_for_each_entry(port, &pcie->ports, list)
-- reset_control_put(port->pcie_rst);
--
-- return err;
--}
--
--static int mt7621_pcie_remove(struct platform_device *pdev)
--{
-- struct mt7621_pcie *pcie = platform_get_drvdata(pdev);
-- struct mt7621_pcie_port *port;
--
-- list_for_each_entry(port, &pcie->ports, list)
-- reset_control_put(port->pcie_rst);
--
-- return 0;
--}
--
--static const struct of_device_id mt7621_pcie_ids[] = {
-- { .compatible = "mediatek,mt7621-pci" },
-- {},
--};
--MODULE_DEVICE_TABLE(of, mt7621_pcie_ids);
--
--static struct platform_driver mt7621_pcie_driver = {
-- .probe = mt7621_pcie_probe,
-- .remove = mt7621_pcie_remove,
-- .driver = {
-- .name = "mt7621-pci",
-- .of_match_table = of_match_ptr(mt7621_pcie_ids),
-- },
--};
--builtin_platform_driver(mt7621_pcie_driver);
---- /dev/null
-+++ b/drivers/pci/controller/pcie-mt7621.c
-@@ -0,0 +1,600 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+/*
-+ * BRIEF MODULE DESCRIPTION
-+ * PCI init for Ralink RT2880 solution
-+ *
-+ * Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
-+ *
-+ * May 2007 Bruce Chang
-+ * Initial Release
-+ *
-+ * May 2009 Bruce Chang
-+ * support RT2880/RT3883 PCIe
-+ *
-+ * May 2011 Bruce Chang
-+ * support RT6855/MT7620 PCIe
-+ */
-+
-+#include <linux/bitops.h>
-+#include <linux/clk.h>
-+#include <linux/delay.h>
-+#include <linux/gpio/consumer.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/of_address.h>
-+#include <linux/of_pci.h>
-+#include <linux/of_platform.h>
-+#include <linux/pci.h>
-+#include <linux/phy/phy.h>
-+#include <linux/platform_device.h>
-+#include <linux/reset.h>
-+#include <linux/sys_soc.h>
-+
-+/* MediaTek-specific configuration registers */
-+#define PCIE_FTS_NUM 0x70c
-+#define PCIE_FTS_NUM_MASK GENMASK(15, 8)
-+#define PCIE_FTS_NUM_L0(x) (((x) & 0xff) << 8)
-+
-+/* Host-PCI bridge registers */
-+#define RALINK_PCI_PCICFG_ADDR 0x0000
-+#define RALINK_PCI_PCIMSK_ADDR 0x000c
-+#define RALINK_PCI_CONFIG_ADDR 0x0020
-+#define RALINK_PCI_CONFIG_DATA 0x0024
-+#define RALINK_PCI_MEMBASE 0x0028
-+#define RALINK_PCI_IOBASE 0x002c
-+
-+/* PCIe RC control registers */
-+#define RALINK_PCI_ID 0x0030
-+#define RALINK_PCI_CLASS 0x0034
-+#define RALINK_PCI_SUBID 0x0038
-+#define RALINK_PCI_STATUS 0x0050
-+
-+/* Some definition values */
-+#define PCIE_REVISION_ID BIT(0)
-+#define PCIE_CLASS_CODE (0x60400 << 8)
-+#define PCIE_BAR_MAP_MAX GENMASK(30, 16)
-+#define PCIE_BAR_ENABLE BIT(0)
-+#define PCIE_PORT_INT_EN(x) BIT(20 + (x))
-+#define PCIE_PORT_LINKUP BIT(0)
-+#define PCIE_PORT_CNT 3
-+
-+#define PERST_DELAY_MS 100
-+
-+/**
-+ * struct mt7621_pcie_port - PCIe port information
-+ * @base: I/O mapped register base
-+ * @list: port list
-+ * @pcie: pointer to PCIe host info
-+ * @clk: pointer to the port clock gate
-+ * @phy: pointer to PHY control block
-+ * @pcie_rst: pointer to port reset control
-+ * @gpio_rst: gpio reset
-+ * @slot: port slot
-+ * @enabled: indicates if port is enabled
-+ */
-+struct mt7621_pcie_port {
-+ void __iomem *base;
-+ struct list_head list;
-+ struct mt7621_pcie *pcie;
-+ struct clk *clk;
-+ struct phy *phy;
-+ struct reset_control *pcie_rst;
-+ struct gpio_desc *gpio_rst;
-+ u32 slot;
-+ bool enabled;
-+};
-+
-+/**
-+ * struct mt7621_pcie - PCIe host information
-+ * @base: IO Mapped Register Base
-+ * @dev: Pointer to PCIe device
-+ * @ports: pointer to PCIe port information
-+ * @resets_inverted: depends on chip revision
-+ * reset lines are inverted.
-+ */
-+struct mt7621_pcie {
-+ void __iomem *base;
-+ struct device *dev;
-+ struct list_head ports;
-+ bool resets_inverted;
-+};
-+
-+static inline u32 pcie_read(struct mt7621_pcie *pcie, u32 reg)
-+{
-+ return readl_relaxed(pcie->base + reg);
-+}
-+
-+static inline void pcie_write(struct mt7621_pcie *pcie, u32 val, u32 reg)
-+{
-+ writel_relaxed(val, pcie->base + reg);
-+}
-+
-+static inline void pcie_rmw(struct mt7621_pcie *pcie, u32 reg, u32 clr, u32 set)
-+{
-+ u32 val = readl_relaxed(pcie->base + reg);
-+
-+ val &= ~clr;
-+ val |= set;
-+ writel_relaxed(val, pcie->base + reg);
-+}
-+
-+static inline u32 pcie_port_read(struct mt7621_pcie_port *port, u32 reg)
-+{
-+ return readl_relaxed(port->base + reg);
-+}
-+
-+static inline void pcie_port_write(struct mt7621_pcie_port *port,
-+ u32 val, u32 reg)
-+{
-+ writel_relaxed(val, port->base + reg);
-+}
-+
-+static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
-+ unsigned int func, unsigned int where)
-+{
-+ return (((where & 0xf00) >> 8) << 24) | (bus << 16) | (slot << 11) |
-+ (func << 8) | (where & 0xfc) | 0x80000000;
-+}
-+
-+static void __iomem *mt7621_pcie_map_bus(struct pci_bus *bus,
-+ unsigned int devfn, int where)
-+{
-+ struct mt7621_pcie *pcie = bus->sysdata;
-+ u32 address = mt7621_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
-+ PCI_FUNC(devfn), where);
-+
-+ writel_relaxed(address, pcie->base + RALINK_PCI_CONFIG_ADDR);
-+
-+ return pcie->base + RALINK_PCI_CONFIG_DATA + (where & 3);
-+}
-+
-+struct pci_ops mt7621_pci_ops = {
-+ .map_bus = mt7621_pcie_map_bus,
-+ .read = pci_generic_config_read,
-+ .write = pci_generic_config_write,
-+};
-+
-+static u32 read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg)
-+{
-+ u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
-+
-+ pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
-+ return pcie_read(pcie, RALINK_PCI_CONFIG_DATA);
-+}
-+
-+static void write_config(struct mt7621_pcie *pcie, unsigned int dev,
-+ u32 reg, u32 val)
-+{
-+ u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
-+
-+ pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
-+ pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA);
-+}
-+
-+static inline void mt7621_rst_gpio_pcie_assert(struct mt7621_pcie_port *port)
-+{
-+ if (port->gpio_rst)
-+ gpiod_set_value(port->gpio_rst, 1);
-+}
-+
-+static inline void mt7621_rst_gpio_pcie_deassert(struct mt7621_pcie_port *port)
-+{
-+ if (port->gpio_rst)
-+ gpiod_set_value(port->gpio_rst, 0);
-+}
-+
-+static inline bool mt7621_pcie_port_is_linkup(struct mt7621_pcie_port *port)
-+{
-+ return (pcie_port_read(port, RALINK_PCI_STATUS) & PCIE_PORT_LINKUP) != 0;
-+}
-+
-+static inline void mt7621_control_assert(struct mt7621_pcie_port *port)
-+{
-+ struct mt7621_pcie *pcie = port->pcie;
-+
-+ if (pcie->resets_inverted)
-+ reset_control_assert(port->pcie_rst);
-+ else
-+ reset_control_deassert(port->pcie_rst);
-+}
-+
-+static inline void mt7621_control_deassert(struct mt7621_pcie_port *port)
-+{
-+ struct mt7621_pcie *pcie = port->pcie;
-+
-+ if (pcie->resets_inverted)
-+ reset_control_deassert(port->pcie_rst);
-+ else
-+ reset_control_assert(port->pcie_rst);
-+}
-+
-+static int setup_cm_memory_region(struct pci_host_bridge *host)
-+{
-+ struct mt7621_pcie *pcie = pci_host_bridge_priv(host);
-+ struct device *dev = pcie->dev;
-+ struct resource_entry *entry;
-+ resource_size_t mask;
-+
-+ entry = resource_list_first_type(&host->windows, IORESOURCE_MEM);
-+ if (!entry) {
-+ dev_err(dev, "cannot get memory resource\n");
-+ return -EINVAL;
-+ }
-+
-+ if (mips_cps_numiocu(0)) {
-+ /*
-+ * FIXME: hardware doesn't accept mask values with 1s after
-+ * 0s (e.g. 0xffef), so it would be great to warn if that's
-+ * about to happen
-+ */
-+ mask = ~(entry->res->end - entry->res->start);
-+
-+ write_gcr_reg1_base(entry->res->start);
-+ write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
-+ dev_info(dev, "PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n",
-+ (unsigned long long)read_gcr_reg1_base(),
-+ (unsigned long long)read_gcr_reg1_mask());
-+ }
-+
-+ return 0;
-+}
-+
-+static int mt7621_pcie_parse_port(struct mt7621_pcie *pcie,
-+ struct device_node *node,
-+ int slot)
-+{
-+ struct mt7621_pcie_port *port;
-+ struct device *dev = pcie->dev;
-+ struct platform_device *pdev = to_platform_device(dev);
-+ char name[10];
-+ int err;
-+
-+ port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
-+ if (!port)
-+ return -ENOMEM;
-+
-+ port->base = devm_platform_ioremap_resource(pdev, slot + 1);
-+ if (IS_ERR(port->base))
-+ return PTR_ERR(port->base);
-+
-+ port->clk = devm_get_clk_from_child(dev, node, NULL);
-+ if (IS_ERR(port->clk)) {
-+ dev_err(dev, "failed to get pcie%d clock\n", slot);
-+ return PTR_ERR(port->clk);
-+ }
-+
-+ port->pcie_rst = of_reset_control_get_exclusive(node, NULL);
-+ if (PTR_ERR(port->pcie_rst) == -EPROBE_DEFER) {
-+ dev_err(dev, "failed to get pcie%d reset control\n", slot);
-+ return PTR_ERR(port->pcie_rst);
-+ }
-+
-+ snprintf(name, sizeof(name), "pcie-phy%d", slot);
-+ port->phy = devm_of_phy_get(dev, node, name);
-+ if (IS_ERR(port->phy)) {
-+ dev_err(dev, "failed to get pcie-phy%d\n", slot);
-+ err = PTR_ERR(port->phy);
-+ goto remove_reset;
-+ }
-+
-+ port->gpio_rst = devm_gpiod_get_index_optional(dev, "reset", slot,
-+ GPIOD_OUT_LOW);
-+ if (IS_ERR(port->gpio_rst)) {
-+ dev_err(dev, "failed to get GPIO for PCIe%d\n", slot);
-+ err = PTR_ERR(port->gpio_rst);
-+ goto remove_reset;
-+ }
-+
-+ port->slot = slot;
-+ port->pcie = pcie;
-+
-+ INIT_LIST_HEAD(&port->list);
-+ list_add_tail(&port->list, &pcie->ports);
-+
-+ return 0;
-+
-+remove_reset:
-+ reset_control_put(port->pcie_rst);
-+ return err;
-+}
-+
-+static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)
-+{
-+ struct device *dev = pcie->dev;
-+ struct platform_device *pdev = to_platform_device(dev);
-+ struct device_node *node = dev->of_node, *child;
-+ int err;
-+
-+ pcie->base = devm_platform_ioremap_resource(pdev, 0);
-+ if (IS_ERR(pcie->base))
-+ return PTR_ERR(pcie->base);
-+
-+ for_each_available_child_of_node(node, child) {
-+ int slot;
-+
-+ err = of_pci_get_devfn(child);
-+ if (err < 0) {
-+ of_node_put(child);
-+ dev_err(dev, "failed to parse devfn: %d\n", err);
-+ return err;
-+ }
-+
-+ slot = PCI_SLOT(err);
-+
-+ err = mt7621_pcie_parse_port(pcie, child, slot);
-+ if (err) {
-+ of_node_put(child);
-+ return err;
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static int mt7621_pcie_init_port(struct mt7621_pcie_port *port)
-+{
-+ struct mt7621_pcie *pcie = port->pcie;
-+ struct device *dev = pcie->dev;
-+ u32 slot = port->slot;
-+ int err;
-+
-+ err = phy_init(port->phy);
-+ if (err) {
-+ dev_err(dev, "failed to initialize port%d phy\n", slot);
-+ return err;
-+ }
-+
-+ err = phy_power_on(port->phy);
-+ if (err) {
-+ dev_err(dev, "failed to power on port%d phy\n", slot);
-+ phy_exit(port->phy);
-+ return err;
-+ }
-+
-+ port->enabled = true;
-+
-+ return 0;
-+}
-+
-+static void mt7621_pcie_reset_assert(struct mt7621_pcie *pcie)
-+{
-+ struct mt7621_pcie_port *port;
-+
-+ list_for_each_entry(port, &pcie->ports, list) {
-+ /* PCIe RC reset assert */
-+ mt7621_control_assert(port);
-+
-+ /* PCIe EP reset assert */
-+ mt7621_rst_gpio_pcie_assert(port);
-+ }
-+
-+ msleep(PERST_DELAY_MS);
-+}
-+
-+static void mt7621_pcie_reset_rc_deassert(struct mt7621_pcie *pcie)
-+{
-+ struct mt7621_pcie_port *port;
-+
-+ list_for_each_entry(port, &pcie->ports, list)
-+ mt7621_control_deassert(port);
-+}
-+
-+static void mt7621_pcie_reset_ep_deassert(struct mt7621_pcie *pcie)
-+{
-+ struct mt7621_pcie_port *port;
-+
-+ list_for_each_entry(port, &pcie->ports, list)
-+ mt7621_rst_gpio_pcie_deassert(port);
-+
-+ msleep(PERST_DELAY_MS);
-+}
-+
-+static int mt7621_pcie_init_ports(struct mt7621_pcie *pcie)
-+{
-+ struct device *dev = pcie->dev;
-+ struct mt7621_pcie_port *port, *tmp;
-+ u8 num_disabled = 0;
-+ int err;
-+
-+ mt7621_pcie_reset_assert(pcie);
-+ mt7621_pcie_reset_rc_deassert(pcie);
-+
-+ list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
-+ u32 slot = port->slot;
-+
-+ if (slot == 1) {
-+ port->enabled = true;
-+ continue;
-+ }
-+
-+ err = mt7621_pcie_init_port(port);
-+ if (err) {
-+ dev_err(dev, "initializing port %d failed\n", slot);
-+ list_del(&port->list);
-+ }
-+ }
-+
-+ mt7621_pcie_reset_ep_deassert(pcie);
-+
-+ tmp = NULL;
-+ list_for_each_entry(port, &pcie->ports, list) {
-+ u32 slot = port->slot;
-+
-+ if (!mt7621_pcie_port_is_linkup(port)) {
-+ dev_err(dev, "pcie%d no card, disable it (RST & CLK)\n",
-+ slot);
-+ mt7621_control_assert(port);
-+ port->enabled = false;
-+ num_disabled++;
-+
-+ if (slot == 0) {
-+ tmp = port;
-+ continue;
-+ }
-+
-+ if (slot == 1 && tmp && !tmp->enabled)
-+ phy_power_off(tmp->phy);
-+ }
-+ }
-+
-+ return (num_disabled != PCIE_PORT_CNT) ? 0 : -ENODEV;
-+}
-+
-+static void mt7621_pcie_enable_port(struct mt7621_pcie_port *port)
-+{
-+ struct mt7621_pcie *pcie = port->pcie;
-+ u32 slot = port->slot;
-+ u32 val;
-+
-+ /* enable pcie interrupt */
-+ val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
-+ val |= PCIE_PORT_INT_EN(slot);
-+ pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
-+
-+ /* map 2G DDR region */
-+ pcie_port_write(port, PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
-+ PCI_BASE_ADDRESS_0);
-+
-+ /* configure class code and revision ID */
-+ pcie_port_write(port, PCIE_CLASS_CODE | PCIE_REVISION_ID,
-+ RALINK_PCI_CLASS);
-+
-+ /* configure RC FTS number to 250 when it leaves L0s */
-+ val = read_config(pcie, slot, PCIE_FTS_NUM);
-+ val &= ~PCIE_FTS_NUM_MASK;
-+ val |= PCIE_FTS_NUM_L0(0x50);
-+ write_config(pcie, slot, PCIE_FTS_NUM, val);
-+}
-+
-+static int mt7621_pcie_enable_ports(struct pci_host_bridge *host)
-+{
-+ struct mt7621_pcie *pcie = pci_host_bridge_priv(host);
-+ struct device *dev = pcie->dev;
-+ struct mt7621_pcie_port *port;
-+ struct resource_entry *entry;
-+ int err;
-+
-+ entry = resource_list_first_type(&host->windows, IORESOURCE_IO);
-+ if (!entry) {
-+ dev_err(dev, "cannot get io resource\n");
-+ return -EINVAL;
-+ }
-+
-+ /* Setup MEMWIN and IOWIN */
-+ pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE);
-+ pcie_write(pcie, entry->res->start, RALINK_PCI_IOBASE);
-+
-+ list_for_each_entry(port, &pcie->ports, list) {
-+ if (port->enabled) {
-+ err = clk_prepare_enable(port->clk);
-+ if (err) {
-+ dev_err(dev, "enabling clk pcie%d\n",
-+ port->slot);
-+ return err;
-+ }
-+
-+ mt7621_pcie_enable_port(port);
-+ dev_info(dev, "PCIE%d enabled\n", port->slot);
-+ }
-+ }
-+
-+ return 0;
-+}
-+
-+static int mt7621_pcie_register_host(struct pci_host_bridge *host)
-+{
-+ struct mt7621_pcie *pcie = pci_host_bridge_priv(host);
-+
-+ host->ops = &mt7621_pci_ops;
-+ host->sysdata = pcie;
-+ return pci_host_probe(host);
-+}
-+
-+static const struct soc_device_attribute mt7621_pci_quirks_match[] = {
-+ { .soc_id = "mt7621", .revision = "E2" }
-+};
-+
-+static int mt7621_pci_probe(struct platform_device *pdev)
-+{
-+ struct device *dev = &pdev->dev;
-+ const struct soc_device_attribute *attr;
-+ struct mt7621_pcie_port *port;
-+ struct mt7621_pcie *pcie;
-+ struct pci_host_bridge *bridge;
-+ int err;
-+
-+ if (!dev->of_node)
-+ return -ENODEV;
-+
-+ bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
-+ if (!bridge)
-+ return -ENOMEM;
-+
-+ pcie = pci_host_bridge_priv(bridge);
-+ pcie->dev = dev;
-+ platform_set_drvdata(pdev, pcie);
-+ INIT_LIST_HEAD(&pcie->ports);
-+
-+ attr = soc_device_match(mt7621_pci_quirks_match);
-+ if (attr)
-+ pcie->resets_inverted = true;
-+
-+ err = mt7621_pcie_parse_dt(pcie);
-+ if (err) {
-+ dev_err(dev, "parsing DT failed\n");
-+ return err;
-+ }
-+
-+ err = mt7621_pcie_init_ports(pcie);
-+ if (err) {
-+ dev_err(dev, "nothing connected in virtual bridges\n");
-+ return 0;
-+ }
-+
-+ err = mt7621_pcie_enable_ports(bridge);
-+ if (err) {
-+ dev_err(dev, "error enabling pcie ports\n");
-+ goto remove_resets;
-+ }
-+
-+ err = setup_cm_memory_region(bridge);
-+ if (err) {
-+ dev_err(dev, "error setting up iocu mem regions\n");
-+ goto remove_resets;
-+ }
-+
-+ return mt7621_pcie_register_host(bridge);
-+
-+remove_resets:
-+ list_for_each_entry(port, &pcie->ports, list)
-+ reset_control_put(port->pcie_rst);
-+
-+ return err;
-+}
-+
-+static int mt7621_pci_remove(struct platform_device *pdev)
-+{
-+ struct mt7621_pcie *pcie = platform_get_drvdata(pdev);
-+ struct mt7621_pcie_port *port;
-+
-+ list_for_each_entry(port, &pcie->ports, list)
-+ reset_control_put(port->pcie_rst);
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id mt7621_pci_ids[] = {
-+ { .compatible = "mediatek,mt7621-pci" },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, mt7621_pci_ids);
-+
-+static struct platform_driver mt7621_pci_driver = {
-+ .probe = mt7621_pci_probe,
-+ .remove = mt7621_pci_remove,
-+ .driver = {
-+ .name = "mt7621-pci",
-+ .of_match_table = of_match_ptr(mt7621_pci_ids),
-+ },
-+};
-+builtin_platform_driver(mt7621_pci_driver);
+++ /dev/null
-From: Bjorn Helgaas <bhelgaas@google.com>
-Date: Wed, 22 Dec 2021 19:10:48 -0600
-Subject: [PATCH] PCI: mt7621: Rename mt7621_pci_ to mt7621_pcie_
-
-Rename mt7621_pci_* structs and functions to mt7621_pcie_* for consistency
-with the rest of the file.
-
-Link: https://lore.kernel.org/r/20211223011054.1227810-18-helgaas@kernel.org
-Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-Reviewed-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Cc: Matthias Brugger <matthias.bgg@gmail.com>
----
-
---- a/drivers/pci/controller/pcie-mt7621.c
-+++ b/drivers/pci/controller/pcie-mt7621.c
-@@ -93,8 +93,8 @@ struct mt7621_pcie_port {
- * reset lines are inverted.
- */
- struct mt7621_pcie {
-- void __iomem *base;
- struct device *dev;
-+ void __iomem *base;
- struct list_head ports;
- bool resets_inverted;
- };
-@@ -129,7 +129,7 @@ static inline void pcie_port_write(struc
- writel_relaxed(val, port->base + reg);
- }
-
--static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
-+static inline u32 mt7621_pcie_get_cfgaddr(unsigned int bus, unsigned int slot,
- unsigned int func, unsigned int where)
- {
- return (((where & 0xf00) >> 8) << 24) | (bus << 16) | (slot << 11) |
-@@ -140,7 +140,7 @@ static void __iomem *mt7621_pcie_map_bus
- unsigned int devfn, int where)
- {
- struct mt7621_pcie *pcie = bus->sysdata;
-- u32 address = mt7621_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
-+ u32 address = mt7621_pcie_get_cfgaddr(bus->number, PCI_SLOT(devfn),
- PCI_FUNC(devfn), where);
-
- writel_relaxed(address, pcie->base + RALINK_PCI_CONFIG_ADDR);
-@@ -148,7 +148,7 @@ static void __iomem *mt7621_pcie_map_bus
- return pcie->base + RALINK_PCI_CONFIG_DATA + (where & 3);
- }
-
--struct pci_ops mt7621_pci_ops = {
-+struct pci_ops mt7621_pcie_ops = {
- .map_bus = mt7621_pcie_map_bus,
- .read = pci_generic_config_read,
- .write = pci_generic_config_write,
-@@ -156,7 +156,7 @@ struct pci_ops mt7621_pci_ops = {
-
- static u32 read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg)
- {
-- u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
-+ u32 address = mt7621_pcie_get_cfgaddr(0, dev, 0, reg);
-
- pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
- return pcie_read(pcie, RALINK_PCI_CONFIG_DATA);
-@@ -165,7 +165,7 @@ static u32 read_config(struct mt7621_pci
- static void write_config(struct mt7621_pcie *pcie, unsigned int dev,
- u32 reg, u32 val)
- {
-- u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
-+ u32 address = mt7621_pcie_get_cfgaddr(0, dev, 0, reg);
-
- pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
- pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA);
-@@ -505,16 +505,16 @@ static int mt7621_pcie_register_host(str
- {
- struct mt7621_pcie *pcie = pci_host_bridge_priv(host);
-
-- host->ops = &mt7621_pci_ops;
-+ host->ops = &mt7621_pcie_ops;
- host->sysdata = pcie;
- return pci_host_probe(host);
- }
-
--static const struct soc_device_attribute mt7621_pci_quirks_match[] = {
-+static const struct soc_device_attribute mt7621_pcie_quirks_match[] = {
- { .soc_id = "mt7621", .revision = "E2" }
- };
-
--static int mt7621_pci_probe(struct platform_device *pdev)
-+static int mt7621_pcie_probe(struct platform_device *pdev)
- {
- struct device *dev = &pdev->dev;
- const struct soc_device_attribute *attr;
-@@ -535,7 +535,7 @@ static int mt7621_pci_probe(struct platf
- platform_set_drvdata(pdev, pcie);
- INIT_LIST_HEAD(&pcie->ports);
-
-- attr = soc_device_match(mt7621_pci_quirks_match);
-+ attr = soc_device_match(mt7621_pcie_quirks_match);
- if (attr)
- pcie->resets_inverted = true;
-
-@@ -572,7 +572,7 @@ remove_resets:
- return err;
- }
-
--static int mt7621_pci_remove(struct platform_device *pdev)
-+static int mt7621_pcie_remove(struct platform_device *pdev)
- {
- struct mt7621_pcie *pcie = platform_get_drvdata(pdev);
- struct mt7621_pcie_port *port;
-@@ -583,18 +583,18 @@ static int mt7621_pci_remove(struct plat
- return 0;
- }
-
--static const struct of_device_id mt7621_pci_ids[] = {
-+static const struct of_device_id mt7621_pcie_ids[] = {
- { .compatible = "mediatek,mt7621-pci" },
- {},
- };
--MODULE_DEVICE_TABLE(of, mt7621_pci_ids);
-+MODULE_DEVICE_TABLE(of, mt7621_pcie_ids);
-
--static struct platform_driver mt7621_pci_driver = {
-- .probe = mt7621_pci_probe,
-- .remove = mt7621_pci_remove,
-+static struct platform_driver mt7621_pcie_driver = {
-+ .probe = mt7621_pcie_probe,
-+ .remove = mt7621_pcie_remove,
- .driver = {
- .name = "mt7621-pci",
-- .of_match_table = of_match_ptr(mt7621_pci_ids),
-+ .of_match_table = of_match_ptr(mt7621_pcie_ids),
- },
- };
--builtin_platform_driver(mt7621_pci_driver);
-+builtin_platform_driver(mt7621_pcie_driver);
+++ /dev/null
-From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Date: Wed, 17 Nov 2021 16:29:52 +0100
-Subject: [PATCH] PCI: mt7621: Declare mt7621_pci_ops static
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Sparse complains about mt7621_pci_ops symbol is not declared and asks if
-it should be declared as static instead. Sparse is right. Hence declare
-symbol as static.
-
-Link: https://lore.kernel.org/r/20211117152952.12271-1-sergio.paracuellos@gmail.com
-Reported-by: kernel test robot <lkp@intel.com>
-Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
-Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-Reviewed-by: Krzysztof Wilczyński <kw@linux.com>
----
-
---- a/drivers/pci/controller/pcie-mt7621.c
-+++ b/drivers/pci/controller/pcie-mt7621.c
-@@ -148,7 +148,7 @@ static void __iomem *mt7621_pcie_map_bus
- return pcie->base + RALINK_PCI_CONFIG_DATA + (where & 3);
- }
-
--struct pci_ops mt7621_pcie_ops = {
-+static struct pci_ops mt7621_pcie_ops = {
- .map_bus = mt7621_pcie_map_bus,
- .read = pci_generic_config_read,
- .write = pci_generic_config_write,
+++ /dev/null
-From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Date: Tue, 7 Dec 2021 11:49:21 +0100
-Subject: [PATCH] PCI: mt7621: Move MIPS setup to pcibios_root_bridge_prepare()
-
-On the MIPS ralink mt7621 platform, we need to set up I/O coherency units
-based on the host bridge apertures.
-
-To remove this arch dependency from the driver itself, move the coherency
-setup from the driver to pcibios_root_bridge_prepare().
-
-[bhelgaas: squash add/remove into one patch, commit log]
-Link: https://lore.kernel.org/r/20211207104924.21327-3-sergio.paracuellos@gmail.com
-Link: https://lore.kernel.org/r/20211207104924.21327-4-sergio.paracuellos@gmail.com
-Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-Reviewed-by: Guenter Roeck <linux@roeck-us.net> # arch/mips
-Acked-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> # arch/mips
----
-
---- a/arch/mips/ralink/mt7621.c
-+++ b/arch/mips/ralink/mt7621.c
-@@ -10,6 +10,8 @@
- #include <linux/slab.h>
- #include <linux/sys_soc.h>
- #include <linux/memblock.h>
-+#include <linux/pci.h>
-+#include <linux/bug.h>
-
- #include <asm/bootinfo.h>
- #include <asm/mipsregs.h>
-@@ -25,6 +27,35 @@
- static u32 detect_magic __initdata;
- static struct ralink_soc_info *soc_info_ptr;
-
-+int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
-+{
-+ struct resource_entry *entry;
-+ resource_size_t mask;
-+
-+ entry = resource_list_first_type(&bridge->windows, IORESOURCE_MEM);
-+ if (!entry) {
-+ pr_err("Cannot get memory resource\n");
-+ return -EINVAL;
-+ }
-+
-+ if (mips_cps_numiocu(0)) {
-+ /*
-+ * Hardware doesn't accept mask values with 1s after
-+ * 0s (e.g. 0xffef), so warn if that's happen
-+ */
-+ mask = ~(entry->res->end - entry->res->start) & CM_GCR_REGn_MASK_ADDRMASK;
-+ WARN_ON(mask && BIT(ffz(~mask)) - 1 != ~mask);
-+
-+ write_gcr_reg1_base(entry->res->start);
-+ write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
-+ pr_info("PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n",
-+ (unsigned long long)read_gcr_reg1_base(),
-+ (unsigned long long)read_gcr_reg1_mask());
-+ }
-+
-+ return 0;
-+}
-+
- phys_addr_t mips_cpc_default_phys_base(void)
- {
- panic("Cannot detect cpc address");
---- a/drivers/pci/controller/pcie-mt7621.c
-+++ b/drivers/pci/controller/pcie-mt7621.c
-@@ -208,37 +208,6 @@ static inline void mt7621_control_deasse
- reset_control_assert(port->pcie_rst);
- }
-
--static int setup_cm_memory_region(struct pci_host_bridge *host)
--{
-- struct mt7621_pcie *pcie = pci_host_bridge_priv(host);
-- struct device *dev = pcie->dev;
-- struct resource_entry *entry;
-- resource_size_t mask;
--
-- entry = resource_list_first_type(&host->windows, IORESOURCE_MEM);
-- if (!entry) {
-- dev_err(dev, "cannot get memory resource\n");
-- return -EINVAL;
-- }
--
-- if (mips_cps_numiocu(0)) {
-- /*
-- * FIXME: hardware doesn't accept mask values with 1s after
-- * 0s (e.g. 0xffef), so it would be great to warn if that's
-- * about to happen
-- */
-- mask = ~(entry->res->end - entry->res->start);
--
-- write_gcr_reg1_base(entry->res->start);
-- write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
-- dev_info(dev, "PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n",
-- (unsigned long long)read_gcr_reg1_base(),
-- (unsigned long long)read_gcr_reg1_mask());
-- }
--
-- return 0;
--}
--
- static int mt7621_pcie_parse_port(struct mt7621_pcie *pcie,
- struct device_node *node,
- int slot)
-@@ -557,12 +526,6 @@ static int mt7621_pcie_probe(struct plat
- goto remove_resets;
- }
-
-- err = setup_cm_memory_region(bridge);
-- if (err) {
-- dev_err(dev, "error setting up iocu mem regions\n");
-- goto remove_resets;
-- }
--
- return mt7621_pcie_register_host(bridge);
-
- remove_resets:
+++ /dev/null
-From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Date: Mon, 24 Jan 2022 12:30:02 +0100
-Subject: [PATCH] PCI: mt7621: Drop of_match_ptr() to avoid unused variable
-
-We have stubs for most OF interfaces even when CONFIG_OF is not set, so we
-allow building of pcie-mt7621.c in that case for compile testing.
-
-When CONFIG_OF is not set, "of_match_ptr(mt7621_pcie_ids)" compiles to
-NULL, which leaves mt7621_pcie_ids unused:
-
- $ make W=1
- drivers/pci/controller/pcie-mt7621.c:549:34: warning: unused variable 'mt7621_pcie_ids' [-Wunused-const-variable]
-
-Drop of_match_ptr() to avoid the unused variable warning.
-
-[bhelgaas: commit log]
-Fixes: 2bdd5238e756 ("PCI: mt7621: Add MediaTek MT7621 PCIe host controller driver")
-Link: https://lore.kernel.org/r/20220124113003.406224-2-sergio.paracuellos@gmail.com
-Link: https://lore.kernel.org/r/202201241754.igtHzgHv-lkp@intel.com
-Reported-by: kernel test robot <lkp@intel.com>
-Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
----
-
---- a/drivers/pci/controller/pcie-mt7621.c
-+++ b/drivers/pci/controller/pcie-mt7621.c
-@@ -557,7 +557,7 @@ static struct platform_driver mt7621_pci
- .remove = mt7621_pcie_remove,
- .driver = {
- .name = "mt7621-pci",
-- .of_match_table = of_match_ptr(mt7621_pcie_ids),
-+ .of_match_table = mt7621_pcie_ids,
- },
- };
- builtin_platform_driver(mt7621_pcie_driver);
+++ /dev/null
-From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Date: Mon, 24 Jan 2022 12:30:03 +0100
-Subject: [PATCH] PCI: mt7621: Remove unused function pcie_rmw()
-
-Function pcie_rmw() is not being used at all and can be deleted. Hence get
-rid of it, which fixes this warning:
-
- drivers/pci/controller/pcie-mt7621.c:112:20: warning: unused function 'pcie_rmw' [-Wunused-function]
-
-Fixes: 2bdd5238e756 ("PCI: mt7621: Add MediaTek MT7621 PCIe host controller driver")
-Link: https://lore.kernel.org/r/20220124113003.406224-3-sergio.paracuellos@gmail.com
-Link: https://lore.kernel.org/all/202201241754.igtHzgHv-lkp@intel.com/
-Reported-by: kernel test robot <lkp@intel.com>
-Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
----
-
---- a/drivers/pci/controller/pcie-mt7621.c
-+++ b/drivers/pci/controller/pcie-mt7621.c
-@@ -109,15 +109,6 @@ static inline void pcie_write(struct mt7
- writel_relaxed(val, pcie->base + reg);
- }
-
--static inline void pcie_rmw(struct mt7621_pcie *pcie, u32 reg, u32 clr, u32 set)
--{
-- u32 val = readl_relaxed(pcie->base + reg);
--
-- val &= ~clr;
-- val |= set;
-- writel_relaxed(val, pcie->base + reg);
--}
--
- static inline u32 pcie_port_read(struct mt7621_pcie_port *port, u32 reg)
- {
- return readl_relaxed(port->base + reg);
+++ /dev/null
-From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Date: Tue, 7 Dec 2021 11:49:20 +0100
-Subject: [PATCH] PCI: Let pcibios_root_bridge_prepare() access bridge->windows
-
-When pci_register_host_bridge() is called, bridge->windows are already
-available. However these windows are being moved temporarily from there.
-
-To let pcibios_root_bridge_prepare() have access to these windows, move the
-windows movement after calling this function. This is useful for the MIPS
-ralink mt7621 platform so it can set up I/O coherence units and avoid
-custom MIPS code in the mt7621 PCIe controller driver.
-
-Link: https://lore.kernel.org/r/20211207104924.21327-2-sergio.paracuellos@gmail.com
-Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-Acked-by: Arnd Bergmann <arnd@arndb.de>
----
-
---- a/drivers/pci/probe.c
-+++ b/drivers/pci/probe.c
-@@ -898,8 +898,6 @@ static int pci_register_host_bridge(stru
-
- bridge->bus = bus;
-
-- /* Temporarily move resources off the list */
-- list_splice_init(&bridge->windows, &resources);
- bus->sysdata = bridge->sysdata;
- bus->ops = bridge->ops;
- bus->number = bus->busn_res.start = bridge->busnr;
-@@ -925,6 +923,8 @@ static int pci_register_host_bridge(stru
- if (err)
- goto free;
-
-+ /* Temporarily move resources off the list */
-+ list_splice_init(&bridge->windows, &resources);
- err = device_add(&bridge->dev);
- if (err) {
- put_device(&bridge->dev);
+++ /dev/null
-From 19098934f910b4d47cb30251dd39ffa57bef9523 Mon Sep 17 00:00:00 2001
-From: John Thomson <git@johnthomson.fastmail.com.au>
-Date: Tue, 6 Dec 2022 06:46:45 +1000
-Subject: [PATCH] PCI: mt7621: Add sentinel to quirks table
-
-Current driver is missing a sentinel in the struct soc_device_attribute
-array, which causes an oops when assessed by the
-soc_device_match(mt7621_pcie_quirks_match) call.
-
-This was only exposed once the CONFIG_SOC_MT7621 mt7621 soc_dev_attr
-was fixed to register the SOC as a device, in:
-
-commit 7c18b64bba3b ("mips: ralink: mt7621: do not use kzalloc too early")
-
-Fix it by adding the required sentinel.
-
-Link: https://lore.kernel.org/lkml/26ebbed1-0fe9-4af9-8466-65f841d0b382@app.fastmail.com
-Link: https://lore.kernel.org/r/20221205204645.301301-1-git@johnthomson.fastmail.com.au
-Fixes: b483b4e4d3f6 ("staging: mt7621-pci: add quirks for 'E2' revision using 'soc_device_attribute'")
-Signed-off-by: John Thomson <git@johnthomson.fastmail.com.au>
-Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
-Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
----
- drivers/pci/controller/pcie-mt7621.c | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
---- a/drivers/pci/controller/pcie-mt7621.c
-+++ b/drivers/pci/controller/pcie-mt7621.c
-@@ -471,7 +471,8 @@ static int mt7621_pcie_register_host(str
- }
-
- static const struct soc_device_attribute mt7621_pcie_quirks_match[] = {
-- { .soc_id = "mt7621", .revision = "E2" }
-+ { .soc_id = "mt7621", .revision = "E2" },
-+ { /* sentinel */ }
- };
-
- static int mt7621_pcie_probe(struct platform_device *pdev)
+++ /dev/null
-From 0cb2a8f3456ff1cc51d571e287a48e8fddc98ec2 Mon Sep 17 00:00:00 2001
-From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Date: Sat, 31 Dec 2022 08:40:41 +0100
-Subject: PCI: mt7621: Delay phy ports initialization
-
-Some devices like ZBT WE1326 and ZBT WF3526-P and some Netgear models need
-to delay phy port initialization after calling the mt7621_pcie_init_port()
-driver function to get into reliable boots for both warm and hard resets.
-
-The delay required to detect the ports seems to be in the range [75-100]
-milliseconds.
-
-If the ports are not detected the controller is not functional.
-
-There is no datasheet or something similar to really understand why this
-extra delay is needed only for these devices and it is not for most of
-the boards that are built on mt7621 SoC.
-
-This issue has been reported by openWRT community and the complete
-discussion is in [0]. The 100 milliseconds delay has been tested in all
-devices to validate it.
-
-Add the extra 100 milliseconds delay to fix the issue.
-
-[0]: https://github.com/openwrt/openwrt/pull/11220
-
-Link: https://lore.kernel.org/r/20221231074041.264738-1-sergio.paracuellos@gmail.com
-Fixes: 2bdd5238e756 ("PCI: mt7621: Add MediaTek MT7621 PCIe host controller driver")
-Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
-Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
----
- drivers/pci/controller/pcie-mt7621.c | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/drivers/pci/controller/pcie-mt7621.c
-+++ b/drivers/pci/controller/pcie-mt7621.c
-@@ -58,6 +58,7 @@
- #define PCIE_PORT_LINKUP BIT(0)
- #define PCIE_PORT_CNT 3
-
-+#define INIT_PORTS_DELAY_MS 100
- #define PERST_DELAY_MS 100
-
- /**
-@@ -374,6 +375,7 @@ static int mt7621_pcie_init_ports(struct
- }
- }
-
-+ msleep(INIT_PORTS_DELAY_MS);
- mt7621_pcie_reset_ep_deassert(pcie);
-
- tmp = NULL;
--- a/drivers/pci/controller/pcie-mt7621.c
+++ b/drivers/pci/controller/pcie-mt7621.c
-@@ -383,8 +383,8 @@ static int mt7621_pcie_init_ports(struct
+@@ -378,8 +378,8 @@ static int mt7621_pcie_init_ports(struct
u32 slot = port->slot;
if (!mt7621_pcie_port_is_linkup(port)) {
--- a/drivers/net/ethernet/Kconfig
+++ b/drivers/net/ethernet/Kconfig
-@@ -162,6 +162,7 @@ source "drivers/net/ethernet/pensando/Kc
+@@ -167,6 +167,7 @@ source "drivers/net/ethernet/pensando/Kc
source "drivers/net/ethernet/qlogic/Kconfig"
source "drivers/net/ethernet/brocade/Kconfig"
source "drivers/net/ethernet/qualcomm/Kconfig"
source "drivers/net/ethernet/renesas/Kconfig"
--- a/drivers/net/ethernet/Makefile
+++ b/drivers/net/ethernet/Makefile
-@@ -73,6 +73,7 @@ obj-$(CONFIG_NET_VENDOR_PACKET_ENGINES)
+@@ -77,6 +77,7 @@ obj-$(CONFIG_NET_VENDOR_PACKET_ENGINES)
obj-$(CONFIG_NET_VENDOR_PASEMI) += pasemi/
obj-$(CONFIG_NET_VENDOR_QLOGIC) += qlogic/
obj-$(CONFIG_NET_VENDOR_QUALCOMM) += qualcomm/
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
-@@ -547,8 +547,28 @@ static int __init bootcmdline_scan_chose
+@@ -557,8 +557,28 @@ static int __init bootcmdline_scan_chose
#endif /* CONFIG_OF_EARLY_FLATTREE */
bool dt_bootargs = false;
/*
-@@ -562,6 +582,14 @@ static void __init bootcmdline_init(void
+@@ -572,6 +592,14 @@ static void __init bootcmdline_init(void
}
/*
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
-@@ -689,7 +689,6 @@ static void __init arch_mem_init(char **
+@@ -699,7 +699,6 @@ static void __init arch_mem_init(char **
mips_reserve_vmcore();
mips_parse_crashkernel();
/*
* In order to reduce the possibility of kernel panic when failed to
-@@ -806,6 +805,7 @@ void __init setup_arch(char **cmdline_p)
+@@ -834,6 +833,7 @@ void __init setup_arch(char **cmdline_p)
cpu_cache_init();
paging_init();
+ device_tree_init();
memblock_dump_all();
- }
+
--- a/arch/mips/include/asm/mips-cps.h
+++ b/arch/mips/include/asm/mips-cps.h
-@@ -10,6 +10,8 @@
+@@ -11,6 +11,8 @@
#include <linux/io.h>
#include <linux/types.h>
extern unsigned long __cps_access_bad_size(void)
__compiletime_error("Bad size for CPS accessor");
-@@ -165,11 +167,30 @@ static inline uint64_t mips_cps_cluster_
+@@ -162,12 +164,31 @@ static inline uint64_t mips_cps_cluster_
*/
static inline unsigned int mips_cps_numcores(unsigned int cluster)
{
return 0;
/* Add one before masking to handle 0xff indicating no cores */
-- return (mips_cps_cluster_config(cluster) + 1) & CM_GCR_CONFIG_PCORES;
-+ ncores = (mips_cps_cluster_config(cluster) + 1) & CM_GCR_CONFIG_PCORES;
+- return FIELD_GET(CM_GCR_CONFIG_PCORES,
++ ncores = FIELD_GET(CM_GCR_CONFIG_PCORES,
+ mips_cps_cluster_config(cluster) + 1);
+
+ if (IS_ENABLED(CONFIG_SOC_MT7621)) {
+ struct cpulaunch *launch;
+
+static const struct flash_info bohong_parts[] = {
+ /* BoHong Microelectronics */
-+ { "bh25q128as", INFO(0x684018, 0, 64 * 1024, 256,
-+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
++ { "bh25q128as", INFO(0x684018, 0, 64 * 1024, 256)
++ NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+};
+
+const struct spi_nor_manufacturer spi_nor_bohong = {
+};
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
-@@ -1844,6 +1844,7 @@ int spi_nor_sr2_bit7_quad_enable(struct
+@@ -1620,6 +1620,7 @@ int spi_nor_sr2_bit7_quad_enable(struct
static const struct spi_nor_manufacturer *manufacturers[] = {
&spi_nor_atmel,
&spi_nor_esmt,
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
-@@ -473,6 +473,7 @@ struct sfdp {
+@@ -617,6 +617,7 @@ struct sfdp {
/* Manufacturer drivers. */
extern const struct spi_nor_manufacturer spi_nor_atmel;
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
-@@ -358,6 +358,14 @@ config MTD_NAND_QCOM
+@@ -352,6 +352,14 @@ config MTD_NAND_QCOM
Enables support for NAND flash chips on SoCs containing the EBI2 NAND
controller. This controller is found on IPQ806x SoC.
+
config MTD_NAND_MTK
tristate "MTK NAND controller"
- depends on ARCH_MEDIATEK || COMPILE_TEST
+ depends on MTD_NAND_ECC_MEDIATEK
--- a/drivers/mtd/nand/raw/Makefile
+++ b/drivers/mtd/nand/raw/Makefile
@@ -48,6 +48,7 @@ obj-$(CONFIG_MTD_NAND_SUNXI) += sunxi_n
obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/
obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o
+obj-$(CONFIG_MTD_NAND_MT7621) += mt7621_nand.o
- obj-$(CONFIG_MTD_NAND_MTK) += mtk_ecc.o mtk_nand.o
+ obj-$(CONFIG_MTD_NAND_MTK) += mtk_nand.o
obj-$(CONFIG_MTD_NAND_MXIC) += mxic_nand.o
obj-$(CONFIG_MTD_NAND_TEGRA) += tegra_nand.o
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -4558,6 +4558,7 @@ static const struct net_device_ops mtk_n
+@@ -4612,6 +4612,7 @@ static const struct net_device_ops mtk_n
static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
{
const __be32 *_id = of_get_property(np, "reg", NULL);
phy_interface_t phy_mode;
struct phylink *phylink;
-@@ -4729,6 +4730,9 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4783,6 +4784,9 @@ static int mtk_add_mac(struct mtk_eth *e
register_netdevice_notifier(&mac->device_notifier);
}
phy_led_trigger_change_speed(phydev);
}
-@@ -591,7 +591,7 @@ int phy_start_cable_test(struct phy_devi
+@@ -595,7 +595,7 @@ int phy_start_cable_test(struct phy_devi
goto out;
/* Mark the carrier down until the test is complete */
netif_testing_on(dev);
err = phydev->drv->cable_test_start(phydev);
-@@ -662,7 +662,7 @@ int phy_start_cable_test_tdr(struct phy_
+@@ -666,7 +666,7 @@ int phy_start_cable_test_tdr(struct phy_
goto out;
/* Mark the carrier down until the test is complete */
netif_testing_on(dev);
err = phydev->drv->cable_test_tdr_start(phydev, config);
-@@ -734,7 +734,7 @@ static int phy_check_link_status(struct
+@@ -738,7 +738,7 @@ static int phy_check_link_status(struct
phy_link_up(phydev);
} else if (!phydev->link && phydev->state != PHY_NOLINK) {
phydev->state = PHY_NOLINK;
}
return 0;
-@@ -1220,7 +1220,7 @@ void phy_state_machine(struct work_struc
+@@ -1224,7 +1224,7 @@ void phy_state_machine(struct work_struc
case PHY_HALTED:
if (phydev->link) {
phydev->link = 0;
break;
--- a/drivers/net/phy/phy_device.c
+++ b/drivers/net/phy/phy_device.c
-@@ -1035,14 +1035,16 @@ struct phy_device *phy_find_first(struct
+@@ -1039,14 +1039,16 @@ struct phy_device *phy_find_first(struct
}
EXPORT_SYMBOL(phy_find_first);
phydev->mii_ts->link_state(phydev->mii_ts, phydev);
--- a/drivers/net/phy/phylink.c
+++ b/drivers/net/phy/phylink.c
-@@ -1373,7 +1373,8 @@ void phylink_destroy(struct phylink *pl)
+@@ -1602,7 +1602,8 @@ bool phylink_expects_phy(struct phylink
}
- EXPORT_SYMBOL_GPL(phylink_destroy);
+ EXPORT_SYMBOL_GPL(phylink_expects_phy);
-static void phylink_phy_change(struct phy_device *phydev, bool up)
+static void phylink_phy_change(struct phy_device *phydev, bool up,
bool tx_pause, rx_pause;
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
-@@ -716,7 +716,7 @@ struct phy_device {
- u8 mdix;
- u8 mdix_ctrl;
+@@ -736,7 +736,7 @@ struct phy_device {
+
+ int pma_extable;
- void (*phy_link_change)(struct phy_device *phydev, bool up);
+ void (*phy_link_change)(struct phy_device *, bool up, bool do_carrier);
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
-@@ -734,7 +734,10 @@ static int phy_check_link_status(struct
+@@ -738,7 +738,10 @@ static int phy_check_link_status(struct
phy_link_up(phydev);
} else if (!phydev->link && phydev->state != PHY_NOLINK) {
phydev->state = PHY_NOLINK;
}
return 0;
-@@ -1220,7 +1223,10 @@ void phy_state_machine(struct work_struc
+@@ -1224,7 +1227,10 @@ void phy_state_machine(struct work_struc
case PHY_HALTED:
if (phydev->link) {
phydev->link = 0;
break;
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
-@@ -630,6 +630,7 @@ struct phy_device {
+@@ -644,6 +644,7 @@ struct phy_device {
unsigned downshifted_rate:1;
unsigned is_on_sfp_module:1;
unsigned mac_managed_pm:1;
drivers/dma/mediatek/Makefile | 1 +
2 files changed, 7 insertions(+)
-diff --git a/drivers/dma/mediatek/Kconfig b/drivers/dma/mediatek/Kconfig
-index 7a46a5455957..1a24d73ce87f 100644
--- a/drivers/dma/mediatek/Kconfig
+++ b/drivers/dma/mediatek/Kconfig
@@ -36,3 +36,9 @@ config MTK_UART_APDMA
+ depends on RALINK && SOC_MT7621
+ select DMA_ENGINE
+ select DMA_VIRTUAL_CHANNELS
-diff --git a/drivers/dma/mediatek/Makefile b/drivers/dma/mediatek/Makefile
-index 5ba39a5edc13..784af039b7c0 100644
--- a/drivers/dma/mediatek/Makefile
+++ b/drivers/dma/mediatek/Makefile
@@ -2,3 +2,4 @@
obj-$(CONFIG_MTK_HSDMA) += mtk-hsdma.o
obj-$(CONFIG_MTK_CQDMA) += mtk-cqdma.o
+obj-$(CONFIG_MTK_HSDMA) += hsdma-mt7621.o
---
-2.40.1
-
+#endif /* __ASM_MACH_RALINK_GPIO_H */
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
-@@ -569,6 +569,12 @@ config GPIO_SNPS_CREG
+@@ -585,6 +585,12 @@ config GPIO_SNPS_CREG
where only several fields in register belong to GPIO lines and
each GPIO line owns a field with different length and on/off value.
depends on PLAT_SPEAR
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
-@@ -121,6 +121,7 @@ obj-$(CONFIG_GPIO_PISOSR) += gpio-pisos
+@@ -122,6 +122,7 @@ obj-$(CONFIG_GPIO_PISOSR) += gpio-pisos
obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o
obj-$(CONFIG_GPIO_PMIC_EIC_SPRD) += gpio-pmic-eic-sprd.o
obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
-@@ -111,6 +111,24 @@ config PINCTRL_AMD
- Requires ACPI/FDT device enumeration code to set up a platform
- device.
+@@ -113,6 +113,24 @@ config PINCTRL_AT91PIO4
+ Say Y here to enable the at91 pinctrl/gpio driver for Atmel PIO4
+ controller available on sama5d2 SoC.
+config PINCTRL_AW9523
+ bool "Awinic AW9523/AW9523B I2C GPIO expander pinctrl driver"
+
+ Say yes to enable pinctrl and GPIO support for the AW9523(B).
+
- config PINCTRL_BM1880
- bool "Bitmain BM1880 Pinctrl driver"
- depends on OF && (ARCH_BITMAIN || COMPILE_TEST)
+ config PINCTRL_AXP209
+ tristate "X-Powers AXP209 PMIC pinctrl and GPIO Support"
+ depends on MFD_AXP20X
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
-@@ -14,6 +14,7 @@ obj-$(CONFIG_PINCTRL_AXP209) += pinctrl-
+@@ -15,6 +15,7 @@ obj-$(CONFIG_PINCTRL_ARTPEC6) += pinctrl
+ obj-$(CONFIG_PINCTRL_AS3722) += pinctrl-as3722.o
obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
obj-$(CONFIG_PINCTRL_AT91PIO4) += pinctrl-at91-pio4.o
- obj-$(CONFIG_PINCTRL_AMD) += pinctrl-amd.o
+obj-$(CONFIG_PINCTRL_AW9523) += pinctrl-aw9523.o
+ obj-$(CONFIG_PINCTRL_AXP209) += pinctrl-axp209.o
obj-$(CONFIG_PINCTRL_BM1880) += pinctrl-bm1880.o
- obj-$(CONFIG_PINCTRL_DA850_PUPD) += pinctrl-da850-pupd.o
- obj-$(CONFIG_PINCTRL_DA9062) += pinctrl-da9062.o
+ obj-$(CONFIG_PINCTRL_CY8C95X0) += pinctrl-cy8c95x0.o
--- a/drivers/media/usb/uvc/uvc_driver.c
+++ b/drivers/media/usb/uvc/uvc_driver.c
-@@ -3158,6 +3158,18 @@ static const struct usb_device_id uvc_id
+@@ -2981,6 +2981,18 @@ static const struct usb_device_id uvc_id
.bInterfaceSubClass = 1,
.bInterfaceProtocol = 0,
.driver_info = UVC_INFO_META(V4L2_META_FMT_D4XX) },
{ USB_INTERFACE_INFO(USB_CLASS_VIDEO, 1, UVC_PC_PROTOCOL_15) },
--- a/drivers/media/usb/uvc/uvc_status.c
+++ b/drivers/media/usb/uvc/uvc_status.c
-@@ -224,6 +224,7 @@ static void uvc_status_complete(struct u
+@@ -223,6 +223,7 @@ static void uvc_status_complete(struct u
if (uvc_event_control(urb, status, len))
/* The URB will be resubmitted in work context. */
return;
break;
}
-@@ -272,6 +273,7 @@ int uvc_status_init(struct uvc_device *d
+@@ -271,6 +272,7 @@ int uvc_status_init(struct uvc_device *d
}
pipe = usb_rcvintpipe(dev->udev, ep->desc.bEndpointAddress);
+ dev->motion = 0;
- /* For high-speed interrupt endpoints, the bInterval value is used as
- * an exponent of two. Some developers forgot about it.
+ /*
+ * For high-speed interrupt endpoints, the bInterval value is used as
--- a/drivers/media/usb/uvc/uvc_video.c
+++ b/drivers/media/usb/uvc/uvc_video.c
@@ -19,6 +19,11 @@
#include <media/v4l2-common.h>
-@@ -1214,9 +1219,149 @@ static void uvc_video_decode_data(struct
+@@ -1231,9 +1236,149 @@ static void uvc_video_decode_data(struct
uvc_urb->async_operations++;
}
/* Mark the buffer as done if the EOF marker is set. */
if (data[1] & UVC_STREAM_EOF && buf->bytesused != 0) {
uvc_dbg(stream->dev, FRAME, "Frame complete (EOF found)\n");
-@@ -1801,6 +1946,8 @@ static int uvc_init_video_isoc(struct uv
+@@ -1815,6 +1960,8 @@ static int uvc_init_video_isoc(struct uv
if (npackets == 0)
return -ENOMEM;
for_each_uvc_urb(uvc_urb, stream) {
--- a/drivers/media/usb/uvc/uvcvideo.h
+++ b/drivers/media/usb/uvc/uvcvideo.h
-@@ -210,6 +210,8 @@
+@@ -75,6 +75,8 @@
#define UVC_QUIRK_FORCE_Y8 0x00000800
#define UVC_QUIRK_FORCE_BPP 0x00001000
#define UVC_QUIRK_WAKE_AUTOSUSPEND 0x00002000
/* Format flags */
#define UVC_FMT_FLAG_COMPRESSED 0x00000001
-@@ -701,6 +703,7 @@ struct uvc_device {
+@@ -562,6 +564,7 @@ struct uvc_device {
u8 *status;
struct input_dev *input;
char input_phys[64];
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
-@@ -718,6 +718,12 @@ config SPI_QCOM_GENI
+@@ -823,6 +823,12 @@ config SPI_QCOM_GENI
This driver can also be built as a module. If so, the module
will be called spi-geni-qcom.
depends on ARCH_S3C24XX
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
-@@ -100,6 +100,7 @@ obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o
+@@ -110,6 +110,7 @@ obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o
obj-$(CONFIG_MACH_REALTEK_RTL) += spi-realtek-rtl.o
obj-$(CONFIG_SPI_RPCIF) += spi-rpc-if.o
obj-$(CONFIG_SPI_RSPI) += spi-rspi.o
+};
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
-@@ -949,6 +949,11 @@ config I2C_RK3X
+@@ -998,6 +998,11 @@ config I2C_RK3X
This driver can also be built as a module. If so, the module will
be called i2c-rk3x.
+ depends on RALINK && !SOC_MT7621
+ select OF_I2C
+
- config HAVE_S3C2410_I2C
- bool
- help
+ config I2C_RZV2M
+ tristate "Renesas RZ/V2M adapter"
+ depends on ARCH_RENESAS || COMPILE_TEST
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
-@@ -89,6 +89,7 @@ obj-$(CONFIG_I2C_PCA_PLATFORM) += i2c-pc
+@@ -97,6 +97,7 @@ obj-$(CONFIG_I2C_PCA_PLATFORM) += i2c-pc
obj-$(CONFIG_I2C_PNX) += i2c-pnx.o
obj-$(CONFIG_I2C_PXA) += i2c-pxa.o
obj-$(CONFIG_I2C_PXA_PCI) += i2c-pxa-pci.o
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
-@@ -1095,3 +1095,5 @@ config MMC_OWL
-
+@@ -1102,6 +1102,8 @@ config MMC_OWL
config MMC_SDHCI_EXTERNAL_DMA
bool
-+
+
+source "drivers/mmc/host/mtk-mmc/Kconfig"
++
+ config MMC_LITEX
+ tristate "LiteX MMC Host Controller support"
+ depends on ((PPC_MICROWATT || LITEX) && OF && HAVE_CLK) || COMPILE_TEST
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -3,6 +3,7 @@
--- a/sound/soc/Kconfig
+++ b/sound/soc/Kconfig
-@@ -78,6 +78,7 @@ source "sound/soc/mxs/Kconfig"
+@@ -86,6 +86,7 @@ source "sound/soc/mxs/Kconfig"
source "sound/soc/pxa/Kconfig"
source "sound/soc/qcom/Kconfig"
source "sound/soc/rockchip/Kconfig"
source "sound/soc/sof/Kconfig"
--- a/sound/soc/Makefile
+++ b/sound/soc/Makefile
-@@ -48,6 +48,7 @@ obj-$(CONFIG_SND_SOC) += kirkwood/
+@@ -54,6 +54,7 @@ obj-$(CONFIG_SND_SOC) += kirkwood/
obj-$(CONFIG_SND_SOC) += pxa/
obj-$(CONFIG_SND_SOC) += qcom/
obj-$(CONFIG_SND_SOC) += rockchip/
--- a/drivers/tty/serial/serial_core.c
+++ b/drivers/tty/serial/serial_core.c
-@@ -393,6 +393,9 @@ uart_get_baud_rate(struct uart_port *por
+@@ -445,6 +445,9 @@ uart_get_baud_rate(struct uart_port *por
break;
}
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
-@@ -383,6 +383,15 @@ config PWM_MEDIATEK
+@@ -393,6 +393,15 @@ config PWM_MEDIATEK
To compile this driver as a module, choose M here: the module
will be called pwm-mediatek.
depends on ARCH_MXS || COMPILE_TEST
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
-@@ -33,6 +33,7 @@ obj-$(CONFIG_PWM_LPSS_PCI) += pwm-lpss-p
+@@ -34,6 +34,7 @@ obj-$(CONFIG_PWM_LPSS_PCI) += pwm-lpss-p
obj-$(CONFIG_PWM_LPSS_PLATFORM) += pwm-lpss-platform.o
obj-$(CONFIG_PWM_MESON) += pwm-meson.o
obj-$(CONFIG_PWM_MEDIATEK) += pwm-mediatek.o
--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
-@@ -508,6 +508,12 @@ static int dwc2_driver_probe(struct plat
+@@ -462,6 +462,12 @@ static int dwc2_driver_probe(struct plat
if (retval)
return retval;
+#endif
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
-@@ -918,4 +918,6 @@ config CRYPTO_DEV_SA2UL
-
+@@ -824,4 +824,6 @@ config CRYPTO_DEV_SA2UL
source "drivers/crypto/keembay/Kconfig"
+ source "drivers/crypto/aspeed/Kconfig"
+source "drivers/crypto/mtk-eip93/Kconfig"
+
endif # CRYPTO_HW
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
-@@ -51,3 +51,4 @@ obj-$(CONFIG_CRYPTO_DEV_ZYNQMP_AES) += x
+@@ -53,3 +53,4 @@ obj-y += xilinx/
obj-y += hisilicon/
obj-$(CONFIG_CRYPTO_DEV_AMLOGIC_GXL) += amlogic/
obj-y += keembay/
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_BLK_MQ_PCI=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
CONFIG_CEVT_R4K=y
CONFIG_CLK_MTMIPS=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_CMDLINE_BOOL=y
# CONFIG_CMDLINE_OVERRIDE is not set
CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_CPU_GENERIC_DUMP_TLB=y
CONFIG_CPU_HAS_DIEI=y
CONFIG_CPU_SUPPORTS_MSA=y
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CSRC_R4K=y
+CONFIG_DEBUG_INFO=y
CONFIG_DMA_NONCOHERENT=y
# CONFIG_DTB_RT2880_EVAL is not set
CONFIG_DTB_RT_NONE=y
CONFIG_DTC=y
CONFIG_EARLY_PRINTK=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
CONFIG_FIXED_PHY=y
CONFIG_FWNODE_MDIO=y
CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC11_NO_ARRAY_BOUNDS=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_GENERIC_ATOMIC64=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_FIND_FIRST_BIT=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_IOMAP=y
CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_LIB_ASHLDI3=y
CONFIG_GENERIC_LIB_ASHRDI3=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GPIO_CDEV=y
CONFIG_GPIO_RALINK=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_HARDWARE_WATCHPOINTS=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
CONFIG_MIPS_CMDLINE_FROM_DTB=y
-CONFIG_MIPS_EBPF_JIT=y
CONFIG_MIPS_L1_CACHE_SHIFT=4
CONFIG_MIPS_L1_CACHE_SHIFT_4=y
CONFIG_MIPS_LD_CAN_LINK_VDSO=y
CONFIG_NLS=m
CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_MDIO=y
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DRIVERS_LEGACY=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PGTABLE_LEVELS=2
CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
# CONFIG_PHY_MT7621_PCI is not set
# CONFIG_PHY_RALINK_USB is not set
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_AW9523 is not set
CONFIG_PINCTRL_RALINK=y
-CONFIG_PINCTRL_RT288X=y
+CONFIG_PINCTRL_RT2880=y
# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PREEMPT_NONE_BUILD=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
CONFIG_RALINK=y
CONFIG_RALINK_WDT=y
+CONFIG_RANDSTRUCT_NONE=y
CONFIG_RATIONAL=y
CONFIG_REGMAP=y
CONFIG_REGMAP_MMIO=y
CONFIG_USB_SUPPORT=y
CONFIG_USE_OF=y
CONFIG_WATCHDOG_CORE=y
+CONFIG_ZBOOT_LOAD_ADDRESS=0x0
CONFIG_ARCH_MMAP_RND_BITS_MAX=15
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
CONFIG_CEVT_R4K=y
CONFIG_CEVT_SYSTICK_QUIRK=y
CONFIG_CLKEVT_RT3352=y
CONFIG_CMDLINE_BOOL=y
# CONFIG_CMDLINE_OVERRIDE is not set
CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_CPU_GENERIC_DUMP_TLB=y
CONFIG_CPU_HAS_DIEI=y
CONFIG_CPU_SUPPORTS_MSA=y
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CSRC_R4K=y
+CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_PINCTRL=y
CONFIG_DMA_NONCOHERENT=y
# CONFIG_DTB_RT305X_EVAL is not set
CONFIG_DTB_RT_NONE=y
CONFIG_DTC=y
CONFIG_EARLY_PRINTK=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
CONFIG_FIXED_PHY=y
CONFIG_FWNODE_MDIO=y
CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC11_NO_ARRAY_BOUNDS=y
CONFIG_GENERIC_ATOMIC64=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_FIND_FIRST_BIT=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_IOMAP=y
CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_LIB_ASHLDI3=y
CONFIG_GENERIC_LIB_ASHRDI3=y
CONFIG_GPIO_RALINK=y
CONFIG_GPIO_WATCHDOG=y
# CONFIG_GPIO_WATCHDOG_ARCH_INITCALL is not set
-CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_HARDWARE_WATCHPOINTS=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
CONFIG_MIPS_CMDLINE_FROM_DTB=y
-CONFIG_MIPS_EBPF_JIT=y
CONFIG_MIPS_L1_CACHE_SHIFT=5
CONFIG_MIPS_LD_CAN_LINK_VDSO=y
# CONFIG_MIPS_NO_APPENDED_DTB is not set
CONFIG_NET_VENDOR_RALINK=y
CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_MDIO=y
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
CONFIG_PCI_DRIVERS_LEGACY=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PGTABLE_LEVELS=2
CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
# CONFIG_PHY_MT7621_PCI is not set
CONFIG_PHY_RALINK_USB=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_RALINK=y
CONFIG_PINCTRL_RT305X=y
# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PREEMPT_NONE_BUILD=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
CONFIG_RALINK=y
# CONFIG_RALINK_ILL_ACC is not set
CONFIG_RALINK_WDT=y
+CONFIG_RANDSTRUCT_NONE=y
CONFIG_RATIONAL=y
CONFIG_REGMAP=y
CONFIG_REGMAP_MMIO=y
CONFIG_USB_SUPPORT=y
CONFIG_USE_OF=y
CONFIG_WATCHDOG_CORE=y
+CONFIG_ZBOOT_LOAD_ADDRESS=0x0
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_BLK_MQ_PCI=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
CONFIG_CEVT_R4K=y
CONFIG_CLK_MTMIPS=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_CMDLINE_BOOL=y
# CONFIG_CMDLINE_OVERRIDE is not set
CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_CPU_GENERIC_DUMP_TLB=y
CONFIG_CPU_HAS_DIEI=y
CONFIG_CPU_SUPPORTS_MSA=y
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CSRC_R4K=y
+CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_PINCTRL=y
CONFIG_DMA_NONCOHERENT=y
# CONFIG_DTB_RT3883_EVAL is not set
CONFIG_DTC=y
CONFIG_EARLY_PRINTK=y
CONFIG_ETHERNET_PACKET_MANGLE=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
CONFIG_FIXED_PHY=y
CONFIG_FWNODE_MDIO=y
CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC11_NO_ARRAY_BOUNDS=y
CONFIG_GENERIC_ATOMIC64=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_FIND_FIRST_BIT=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_IOMAP=y
CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_LIB_ASHLDI3=y
CONFIG_GENERIC_LIB_ASHRDI3=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GPIO_CDEV=y
CONFIG_GPIO_RALINK=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_HARDWARE_WATCHPOINTS=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
CONFIG_MIPS_CMDLINE_FROM_DTB=y
-CONFIG_MIPS_EBPF_JIT=y
CONFIG_MIPS_L1_CACHE_SHIFT=5
CONFIG_MIPS_LD_CAN_LINK_VDSO=y
# CONFIG_MIPS_NO_APPENDED_DTB is not set
CONFIG_NET_VENDOR_RALINK=y
CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_MDIO=y
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DRIVERS_LEGACY=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PGTABLE_LEVELS=2
CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
# CONFIG_PHY_MT7621_PCI is not set
CONFIG_PHY_RALINK_USB=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_RALINK=y
CONFIG_PINCTRL_RT3883=y
# CONFIG_PINCTRL_SINGLE is not set
+CONFIG_PREEMPT_NONE_BUILD=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
CONFIG_RALINK=y
CONFIG_RALINK_WDT=y
+CONFIG_RANDSTRUCT_NONE=y
CONFIG_RATIONAL=y
CONFIG_REGMAP=y
CONFIG_REGMAP_MMIO=y
CONFIG_USB_SUPPORT=y
CONFIG_USE_OF=y
CONFIG_WATCHDOG_CORE=y
+CONFIG_ZBOOT_LOAD_ADDRESS=0x0
projects / openwrt / staging / jow.git / commitdiff