bdd9fcfd336a25a34721d718c1cf900298c0d5e4
[openwrt/staging/jow.git] / target / linux / ramips / patches-6.1 / 005-v6.5-07-mips-ralink-remove-reset-related-code.patch
1 From 201ddc05777cd8e084b508bcdda22214bfe2895e Mon Sep 17 00:00:00 2001
2 From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
3 Date: Mon, 19 Jun 2023 06:09:39 +0200
4 Subject: [PATCH 7/9] mips: ralink: remove reset related code
5
6 A proper clock driver for ralink SoCs has been added. This driver is also
7 a reset provider for the SoC. Hence there is no need to have reset related
8 code in 'arch/mips/ralink' folder anymore. The only code that remains is
9 the one related with mips_reboot_setup where a PCI reset is performed.
10 We maintain this because I cannot test old ralink board with PCI to be
11 sure all works if we remove also this code.
12
13 Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
14 Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
15 ---
16 arch/mips/ralink/common.h | 2 --
17 arch/mips/ralink/of.c | 4 ----
18 arch/mips/ralink/reset.c | 61 -----------------------------------------------
19 3 files changed, 67 deletions(-)
20
21 --- a/arch/mips/ralink/common.h
22 +++ b/arch/mips/ralink/common.h
23 @@ -23,8 +23,6 @@ extern struct ralink_soc_info soc_info;
24
25 extern void ralink_of_remap(void);
26
27 -extern void ralink_rst_init(void);
28 -
29 extern void __init prom_soc_init(struct ralink_soc_info *soc_info);
30
31 __iomem void *plat_of_remap_node(const char *node);
32 --- a/arch/mips/ralink/of.c
33 +++ b/arch/mips/ralink/of.c
34 @@ -95,10 +95,6 @@ static int __init plat_of_setup(void)
35 {
36 __dt_register_buses(soc_info.compatible, "palmbus");
37
38 - /* make sure that the reset controller is setup early */
39 - if (ralink_soc != MT762X_SOC_MT7621AT)
40 - ralink_rst_init();
41 -
42 return 0;
43 }
44
45 --- a/arch/mips/ralink/reset.c
46 +++ b/arch/mips/ralink/reset.c
47 @@ -10,7 +10,6 @@
48 #include <linux/io.h>
49 #include <linux/of.h>
50 #include <linux/delay.h>
51 -#include <linux/reset-controller.h>
52
53 #include <asm/reboot.h>
54
55 @@ -22,66 +21,6 @@
56 #define RSTCTL_RESET_PCI BIT(26)
57 #define RSTCTL_RESET_SYSTEM BIT(0)
58
59 -static int ralink_assert_device(struct reset_controller_dev *rcdev,
60 - unsigned long id)
61 -{
62 - u32 val;
63 -
64 - if (id == 0)
65 - return -1;
66 -
67 - val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
68 - val |= BIT(id);
69 - rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
70 -
71 - return 0;
72 -}
73 -
74 -static int ralink_deassert_device(struct reset_controller_dev *rcdev,
75 - unsigned long id)
76 -{
77 - u32 val;
78 -
79 - if (id == 0)
80 - return -1;
81 -
82 - val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
83 - val &= ~BIT(id);
84 - rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
85 -
86 - return 0;
87 -}
88 -
89 -static int ralink_reset_device(struct reset_controller_dev *rcdev,
90 - unsigned long id)
91 -{
92 - ralink_assert_device(rcdev, id);
93 - return ralink_deassert_device(rcdev, id);
94 -}
95 -
96 -static const struct reset_control_ops reset_ops = {
97 - .reset = ralink_reset_device,
98 - .assert = ralink_assert_device,
99 - .deassert = ralink_deassert_device,
100 -};
101 -
102 -static struct reset_controller_dev reset_dev = {
103 - .ops = &reset_ops,
104 - .owner = THIS_MODULE,
105 - .nr_resets = 32,
106 - .of_reset_n_cells = 1,
107 -};
108 -
109 -void ralink_rst_init(void)
110 -{
111 - reset_dev.of_node = of_find_compatible_node(NULL, NULL,
112 - "ralink,rt2880-reset");
113 - if (!reset_dev.of_node)
114 - pr_err("Failed to find reset controller node");
115 - else
116 - reset_controller_register(&reset_dev);
117 -}
118 -
119 static void ralink_restart(char *command)
120 {
121 if (IS_ENABLED(CONFIG_PCI)) {