target/linux/ramips/patches-6.1/103-v5.17-PCI-mt7621-Move-MIPS-setup-to-pcibios_root_bridge_pr.patch

   1 From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
   2 Date: Tue, 7 Dec 2021 11:49:21 +0100
   3 Subject: [PATCH] PCI: mt7621: Move MIPS setup to pcibios_root_bridge_prepare()
   4
   5 On the MIPS ralink mt7621 platform, we need to set up I/O coherency units
   6 based on the host bridge apertures.
   7
   8 To remove this arch dependency from the driver itself, move the coherency
   9 setup from the driver to pcibios_root_bridge_prepare().
  10
  11 [bhelgaas: squash add/remove into one patch, commit log]
  12 Link: https://lore.kernel.org/r/20211207104924.21327-3-sergio.paracuellos@gmail.com
  13 Link: https://lore.kernel.org/r/20211207104924.21327-4-sergio.paracuellos@gmail.com
  14 Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
  15 Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  16 Reviewed-by: Guenter Roeck <linux@roeck-us.net>             # arch/mips
  17 Acked-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>   # arch/mips
  18 ---
  19
  20 --- a/arch/mips/ralink/mt7621.c
  21 +++ b/arch/mips/ralink/mt7621.c
  22 @@ -10,6 +10,8 @@
  23  #include <linux/slab.h>
  24  #include <linux/sys_soc.h>
  25  #include <linux/memblock.h>
  26 +#include <linux/pci.h>
  27 +#include <linux/bug.h>
  28
  29  #include <asm/bootinfo.h>
  30  #include <asm/mipsregs.h>
  31 @@ -25,6 +27,35 @@
  32  static u32 detect_magic __initdata;
  33  static struct ralink_soc_info *soc_info_ptr;
  34
  35 +int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
  36 +{
  37 +       struct resource_entry *entry;
  38 +       resource_size_t mask;
  39 +
  40 +       entry = resource_list_first_type(&bridge->windows, IORESOURCE_MEM);
  41 +       if (!entry) {
  42 +               pr_err("Cannot get memory resource\n");
  43 +               return -EINVAL;
  44 +       }
  45 +
  46 +       if (mips_cps_numiocu(0)) {
  47 +               /*
  48 +                * Hardware doesn't accept mask values with 1s after
  49 +                * 0s (e.g. 0xffef), so warn if that's happen
  50 +                */
  51 +               mask = ~(entry->res->end - entry->res->start) & CM_GCR_REGn_MASK_ADDRMASK;
  52 +               WARN_ON(mask && BIT(ffz(~mask)) - 1 != ~mask);
  53 +
  54 +               write_gcr_reg1_base(entry->res->start);
  55 +               write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
  56 +               pr_info("PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n",
  57 +                       (unsigned long long)read_gcr_reg1_base(),
  58 +                       (unsigned long long)read_gcr_reg1_mask());
  59 +       }
  60 +
  61 +       return 0;
  62 +}
  63 +
  64  phys_addr_t mips_cpc_default_phys_base(void)
  65  {
  66         panic("Cannot detect cpc address");
  67 --- a/drivers/pci/controller/pcie-mt7621.c
  68 +++ b/drivers/pci/controller/pcie-mt7621.c
  69 @@ -208,37 +208,6 @@ static inline void mt7621_control_deasse
  70                 reset_control_assert(port->pcie_rst);
  71  }
  72
  73 -static int setup_cm_memory_region(struct pci_host_bridge *host)
  74 -{
  75 -       struct mt7621_pcie *pcie = pci_host_bridge_priv(host);
  76 -       struct device *dev = pcie->dev;
  77 -       struct resource_entry *entry;
  78 -       resource_size_t mask;
  79 -
  80 -       entry = resource_list_first_type(&host->windows, IORESOURCE_MEM);
  81 -       if (!entry) {
  82 -               dev_err(dev, "cannot get memory resource\n");
  83 -               return -EINVAL;
  84 -       }
  85 -
  86 -       if (mips_cps_numiocu(0)) {
  87 -               /*
  88 -                * FIXME: hardware doesn't accept mask values with 1s after
  89 -                * 0s (e.g. 0xffef), so it would be great to warn if that's
  90 -                * about to happen
  91 -                */
  92 -               mask = ~(entry->res->end - entry->res->start);
  93 -
  94 -               write_gcr_reg1_base(entry->res->start);
  95 -               write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
  96 -               dev_info(dev, "PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n",
  97 -                        (unsigned long long)read_gcr_reg1_base(),
  98 -                        (unsigned long long)read_gcr_reg1_mask());
  99 -       }
 100 -
 101 -       return 0;
 102 -}
 103 -
 104  static int mt7621_pcie_parse_port(struct mt7621_pcie *pcie,
 105                                   struct device_node *node,
 106                                   int slot)
 107 @@ -557,12 +526,6 @@ static int mt7621_pcie_probe(struct plat
 108                 goto remove_resets;
 109         }
 110
 111 -       err = setup_cm_memory_region(bridge);
 112 -       if (err) {
 113 -               dev_err(dev, "error setting up iocu mem regions\n");
 114 -               goto remove_resets;
 115 -       }
 116 -
 117         return mt7621_pcie_register_host(bridge);
 118
 119  remove_resets: