+...
--- a/MAINTAINERS
+++ b/MAINTAINERS
-@@ -19281,6 +19281,14 @@ T: git git://linuxtv.org/media_tree.git
+@@ -19283,6 +19283,14 @@ T: git git://linuxtv.org/media_tree.git
F: Documentation/devicetree/bindings/media/i2c/sony,imx412.yaml
F: drivers/media/i2c/imx412.c
+...
--- a/MAINTAINERS
+++ b/MAINTAINERS
-@@ -19289,6 +19289,14 @@ T: git git://linuxtv.org/media_tree.git
+@@ -19291,6 +19291,14 @@ T: git git://linuxtv.org/media_tree.git
F: Documentation/devicetree/bindings/media/i2c/imx477.yaml
F: drivers/media/i2c/imx477.c
+...
--- a/MAINTAINERS
+++ b/MAINTAINERS
-@@ -19286,6 +19286,7 @@ M: Raspberry Pi Kernel Maintenance <kern
+@@ -19288,6 +19288,7 @@ M: Raspberry Pi Kernel Maintenance <kern
L: linux-media@vger.kernel.org
S: Maintained
T: git git://linuxtv.org/media_tree.git
+...
--- a/MAINTAINERS
+++ b/MAINTAINERS
-@@ -19330,6 +19330,14 @@ T: git git://linuxtv.org/media_tree.git
+@@ -19332,6 +19332,14 @@ T: git git://linuxtv.org/media_tree.git
F: Documentation/devicetree/bindings/media/i2c/imx519.yaml
F: drivers/media/i2c/imx519.c
+...
--- a/MAINTAINERS
+++ b/MAINTAINERS
-@@ -19272,6 +19272,14 @@ T: git git://linuxtv.org/media_tree.git
+@@ -19274,6 +19274,14 @@ T: git git://linuxtv.org/media_tree.git
F: Documentation/devicetree/bindings/media/i2c/imx290.txt
F: drivers/media/i2c/imx290.c
--- a/MAINTAINERS
+++ b/MAINTAINERS
-@@ -19279,6 +19279,7 @@ L: linux-media@vger.kernel.org
+@@ -19281,6 +19281,7 @@ L: linux-media@vger.kernel.org
S: Maintained
T: git git://linuxtv.org/media_tree.git
F: Documentation/devicetree/bindings/media/i2c/sony,imx296.yaml
+...
--- a/MAINTAINERS
+++ b/MAINTAINERS
-@@ -19269,7 +19269,7 @@ M: Manivannan Sadhasivam <manivannan.sad
+@@ -19271,7 +19271,7 @@ M: Manivannan Sadhasivam <manivannan.sad
L: linux-media@vger.kernel.org
S: Maintained
T: git git://linuxtv.org/media_tree.git
+...
--- a/MAINTAINERS
+++ b/MAINTAINERS
-@@ -19344,7 +19344,7 @@ M: Raspberry Pi Kernel Maintenance <kern
+@@ -19346,7 +19346,7 @@ M: Raspberry Pi Kernel Maintenance <kern
L: linux-media@vger.kernel.org
S: Maintained
T: git git://linuxtv.org/media_tree.git
+...
--- a/MAINTAINERS
+++ b/MAINTAINERS
-@@ -17895,6 +17895,13 @@ S: Maintained
+@@ -17897,6 +17897,13 @@ S: Maintained
F: Documentation/devicetree/bindings/iio/light/bh1750.yaml
F: drivers/iio/light/bh1750.c
--- a/MAINTAINERS
+++ b/MAINTAINERS
-@@ -15321,6 +15321,14 @@ S: Maintained
+@@ -15323,6 +15323,14 @@ S: Maintained
T: git git://linuxtv.org/media_tree.git
F: drivers/media/i2c/ov5695.c
# CONFIG_PCNET32 is not set
# CONFIG_PCPU_DEV_REFCNT is not set
# CONFIG_PCSPKR_PLATFORM is not set
+# CONFIG_PCS_MTK_USXGMII is not set
# CONFIG_PCS_XPCS is not set
# CONFIG_PD6729 is not set
# CONFIG_PDA_POWER is not set
# CONFIG_PHY_MIXEL_MIPI_DPHY is not set
# CONFIG_PHY_MTK_HDMI is not set
# CONFIG_PHY_MTK_MIPI_DSI is not set
+# CONFIG_PHY_MTK_XFI_TPHY is not set
# CONFIG_PHY_MVEBU_CP110_UTMI is not set
# CONFIG_PHY_OCELOT_SERDES is not set
# CONFIG_PHY_PISTACHIO_USB is not set
--- a/drivers/net/pcs/pcs-mtk-lynxi.c
+++ b/drivers/net/pcs/pcs-mtk-lynxi.c
-@@ -92,14 +92,23 @@ static void mtk_pcs_lynxi_get_state(stru
+@@ -114,14 +114,23 @@ static void mtk_pcs_lynxi_get_state(stru
struct phylink_link_state *state)
{
struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs);
+ phylink_mii_c22_pcs_decode_state(state, bmsr, FIELD_GET(SGMII_LPA, adv));
}
- static int mtk_pcs_lynxi_config(struct phylink_pcs *pcs, unsigned int neg_mode,
-@@ -130,7 +139,8 @@ static int mtk_pcs_lynxi_config(struct p
+ static void mtk_sgmii_reset(struct mtk_pcs_lynxi *mpcs)
+@@ -163,7 +172,8 @@ static int mtk_pcs_lynxi_config(struct p
if (neg_mode & PHYLINK_PCS_NEG_INBAND)
sgm_mode |= SGMII_REMOTE_FAULT_DIS;
-From 1e25ca1147579bda8b941be1b9851f5911d44eb0 Mon Sep 17 00:00:00 2001
+From 91bda2f441f9e37273922028ffc48ce8e91bf5bd Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org>
-Date: Tue, 22 Aug 2023 19:04:42 +0100
-Subject: [PATCH 098/125] net: ethernet: mtk_eth_soc: add paths and SerDes
- modes for MT7988
+Date: Tue, 12 Dec 2023 03:51:14 +0000
+Subject: [PATCH] net: ethernet: mtk_eth_soc: add paths and SerDes modes for
+ MT7988
MT7988 comes with a built-in 2.5G PHY as well as SerDes lanes to
connect external PHYs or transceivers in USXGMII, 10GBase-R, 5GBase-R,
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
- drivers/net/ethernet/mediatek/Kconfig | 16 +
- drivers/net/ethernet/mediatek/Makefile | 1 +
- drivers/net/ethernet/mediatek/mtk_eth_path.c | 123 +++-
- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 182 ++++-
- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 232 ++++++-
- drivers/net/ethernet/mediatek/mtk_usxgmii.c | 692 +++++++++++++++++++
- 6 files changed, 1215 insertions(+), 31 deletions(-)
- create mode 100644 drivers/net/ethernet/mediatek/mtk_usxgmii.c
+ drivers/net/ethernet/mediatek/mtk_eth_path.c | 122 +++++++-
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c | 291 +++++++++++++++++--
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h | 107 ++++++-
+ 3 files changed, 469 insertions(+), 51 deletions(-)
---- a/drivers/net/ethernet/mediatek/Kconfig
-+++ b/drivers/net/ethernet/mediatek/Kconfig
-@@ -25,6 +25,22 @@ config NET_MEDIATEK_SOC
- This driver supports the gigabit ethernet MACs in the
- MediaTek SoC family.
-
-+config NET_MEDIATEK_SOC_USXGMII
-+ bool "Support USXGMII SerDes on MT7988"
-+ depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
-+ def_bool NET_MEDIATEK_SOC != n
-+ help
-+ Include support for 10GE SerDes which can be found on MT7988.
-+ If this kernel should run on SoCs with 10 GBit/s Ethernet you
-+ will need to select this option to use GMAC2 and GMAC3 with
-+ external PHYs, SFP(+) cages in 10GBase-R, 5GBase-R or USXGMII
-+ interface modes.
-+
-+ Note that as the 2500Base-X/1000Base-X/Cisco SGMII SerDes PCS
-+ unit (MediaTek LynxI) in MT7988 is connected via the new 10GE
-+ SerDes, you will also need to select this option in case you
-+ want to use any of those SerDes modes.
-+
- config NET_MEDIATEK_STAR_EMAC
- tristate "MediaTek STAR Ethernet MAC support"
- select PHYLIB
---- a/drivers/net/ethernet/mediatek/Makefile
-+++ b/drivers/net/ethernet/mediatek/Makefile
-@@ -5,6 +5,7 @@
-
- obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o
- mtk_eth-y := mtk_eth_soc.o mtk_eth_path.o mtk_ppe.o mtk_ppe_debugfs.o mtk_ppe_offload.o
-+mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_USXGMII) += mtk_usxgmii.o
- mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed.o mtk_wed_mcu.o mtk_wed_wo.o
- ifdef CONFIG_DEBUG_FS
- mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed_debugfs.o
--- a/drivers/net/ethernet/mediatek/mtk_eth_path.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c
@@ -31,10 +31,20 @@ static const char *mtk_eth_path_name(u64
/* Setup proper MUXes along the path */
return mtk_eth_mux_setup(eth, path);
-@@ -284,4 +398,3 @@ int mtk_gmac_rgmii_path_setup(struct mtk
- /* Setup proper MUXes along the path */
- return mtk_eth_mux_setup(eth, path);
- }
--
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -475,6 +475,30 @@ static void mtk_setup_bridge_switch(stru
+@@ -21,6 +21,8 @@
+ #include <linux/pinctrl/devinfo.h>
+ #include <linux/phylink.h>
+ #include <linux/pcs/pcs-mtk-lynxi.h>
++#include <linux/pcs/pcs-mtk-usxgmii.h>
++#include <linux/phy/phy.h>
+ #include <linux/jhash.h>
+ #include <linux/bitfield.h>
+ #include <net/dsa.h>
+@@ -258,12 +260,8 @@ static const char * const mtk_clks_sourc
+ "ethwarp_wocpu2",
+ "ethwarp_wocpu1",
+ "ethwarp_wocpu0",
+- "top_usxgmii0_sel",
+- "top_usxgmii1_sel",
+ "top_sgm0_sel",
+ "top_sgm1_sel",
+- "top_xfi_phy0_xtal_sel",
+- "top_xfi_phy1_xtal_sel",
+ "top_eth_gmii_sel",
+ "top_eth_refck_50m_sel",
+ "top_eth_sys_200m_sel",
+@@ -475,6 +473,30 @@ static void mtk_setup_bridge_switch(stru
MTK_GSW_CFG);
}
static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config,
phy_interface_t interface)
{
-@@ -483,12 +507,20 @@ static struct phylink_pcs *mtk_mac_selec
+@@ -483,6 +505,21 @@ static struct phylink_pcs *mtk_mac_selec
struct mtk_eth *eth = mac->hw;
unsigned int sid;
-- if (interface == PHY_INTERFACE_MODE_SGMII ||
-- phy_interface_mode_is_8023z(interface)) {
-- sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ?
-- 0 : mac->id;
--
-- return eth->sgmii_pcs[sid];
-+ if ((interface == PHY_INTERFACE_MODE_SGMII ||
-+ phy_interface_mode_is_8023z(interface)) &&
-+ MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
-+ sid = mtk_mac2xgmii_id(eth, mac->id);
-+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_USXGMII))
-+ return mtk_sgmii_wrapper_select_pcs(eth, mac->id);
-+ else
-+ return eth->sgmii_pcs[sid];
-+ } else if ((interface == PHY_INTERFACE_MODE_USXGMII ||
-+ interface == PHY_INTERFACE_MODE_10GBASER ||
-+ interface == PHY_INTERFACE_MODE_5GBASER) &&
-+ MTK_HAS_CAPS(eth->soc->caps, MTK_USXGMII) &&
-+ mac->id != MTK_GMAC1_ID) {
-+ return mtk_usxgmii_select_pcs(eth, mac->id);
- }
-
- return NULL;
-@@ -544,7 +576,22 @@ static void mtk_mac_config(struct phylin
++ if (mtk_is_netsys_v3_or_greater(eth)) {
++ switch (interface) {
++ case PHY_INTERFACE_MODE_1000BASEX:
++ case PHY_INTERFACE_MODE_2500BASEX:
++ case PHY_INTERFACE_MODE_SGMII:
++ return mac->sgmii_pcs;
++ case PHY_INTERFACE_MODE_5GBASER:
++ case PHY_INTERFACE_MODE_10GBASER:
++ case PHY_INTERFACE_MODE_USXGMII:
++ return mac->usxgmii_pcs;
++ default:
++ return NULL;
++ }
++ }
++
+ if (interface == PHY_INTERFACE_MODE_SGMII ||
+ phy_interface_mode_is_8023z(interface)) {
+ sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ?
+@@ -544,7 +581,22 @@ static void mtk_mac_config(struct phylin
goto init_err;
}
break;
break;
default:
goto err_phy;
-@@ -599,8 +646,6 @@ static void mtk_mac_config(struct phylin
+@@ -599,8 +651,6 @@ static void mtk_mac_config(struct phylin
val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
val |= SYSCFG0_GE_MODE(ge_mode, mac->id);
regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
}
/* SGMII */
-@@ -617,21 +662,40 @@ static void mtk_mac_config(struct phylin
+@@ -617,21 +667,40 @@ static void mtk_mac_config(struct phylin
/* Save the syscfg0 value for mac_finish */
mac->syscfg0 = val;
return;
err_phy:
-@@ -677,10 +741,13 @@ static void mtk_mac_link_down(struct phy
+@@ -644,6 +713,18 @@ init_err:
+ mac->id, phy_modes(state->interface), err);
+ }
+
++static int mtk_mac_prepare(struct phylink_config *config, unsigned int mode,
++ phy_interface_t interface)
++{
++ struct mtk_mac *mac = container_of(config, struct mtk_mac,
++ phylink_config);
++
++ if (mac->pextp && mac->interface != interface)
++ phy_reset(mac->pextp);
++
++ return 0;
++}
++
+ static int mtk_mac_finish(struct phylink_config *config, unsigned int mode,
+ phy_interface_t interface)
+ {
+@@ -652,6 +733,10 @@ static int mtk_mac_finish(struct phylink
+ struct mtk_eth *eth = mac->hw;
+ u32 mcr_cur, mcr_new;
+
++ /* Setup PMA/PMD */
++ if (mac->pextp)
++ phy_set_mode_ext(mac->pextp, PHY_MODE_ETHERNET, interface);
++
+ /* Enable SGMII */
+ if (interface == PHY_INTERFACE_MODE_SGMII ||
+ phy_interface_mode_is_8023z(interface))
+@@ -677,10 +762,13 @@ static void mtk_mac_link_down(struct phy
{
struct mtk_mac *mac = container_of(config, struct mtk_mac,
phylink_config);
}
static void mtk_set_queue_speed(struct mtk_eth *eth, unsigned int idx,
-@@ -752,13 +819,11 @@ static void mtk_set_queue_speed(struct m
+@@ -752,13 +840,11 @@ static void mtk_set_queue_speed(struct m
mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs);
}
u32 mcr;
mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
-@@ -792,6 +857,55 @@ static void mtk_mac_link_up(struct phyli
+@@ -792,9 +878,63 @@ static void mtk_mac_link_up(struct phyli
mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
}
+ else
+ mtk_gdm_mac_link_up(mac, phy, mode, interface, speed, duplex,
+ tx_pause, rx_pause);
++
++ /* Repeat pextp setup to tune link */
++ if (mac->pextp)
++ phy_set_mode_ext(mac->pextp, PHY_MODE_ETHERNET, interface);
+}
+
static const struct phylink_mac_ops mtk_phylink_ops = {
.mac_select_pcs = mtk_mac_select_pcs,
.mac_config = mtk_mac_config,
-@@ -4616,8 +4730,21 @@ static int mtk_add_mac(struct mtk_eth *e
++ .mac_prepare = mtk_mac_prepare,
+ .mac_finish = mtk_mac_finish,
+ .mac_link_down = mtk_mac_link_down,
+ .mac_link_up = mtk_mac_link_up,
+@@ -3373,6 +3513,9 @@ static int mtk_open(struct net_device *d
+ struct mtk_eth *eth = mac->hw;
+ int i, err;
+
++ if (mac->pextp)
++ phy_power_on(mac->pextp);
++
+ err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0);
+ if (err) {
+ netdev_err(dev, "%s: could not attach PHY: %d\n", __func__,
+@@ -3501,6 +3644,9 @@ static int mtk_stop(struct net_device *d
+ for (i = 0; i < ARRAY_SIZE(eth->ppe); i++)
+ mtk_ppe_stop(eth->ppe[i]);
+
++ if (mac->pextp)
++ phy_power_off(mac->pextp);
++
+ return 0;
+ }
+
+@@ -4498,6 +4644,7 @@ static const struct net_device_ops mtk_n
+ static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
+ {
+ const __be32 *_id = of_get_property(np, "reg", NULL);
++ struct device_node *pcs_np;
+ phy_interface_t phy_mode;
+ struct phylink *phylink;
+ struct mtk_mac *mac;
+@@ -4533,16 +4680,41 @@ static int mtk_add_mac(struct mtk_eth *e
+ mac->id = id;
+ mac->hw = eth;
+ mac->of_node = np;
++ pcs_np = of_parse_phandle(mac->of_node, "pcs-handle", 0);
++ if (pcs_np) {
++ mac->sgmii_pcs = mtk_pcs_lynxi_get(eth->dev, pcs_np);
++ if (IS_ERR(mac->sgmii_pcs)) {
++ if (PTR_ERR(mac->sgmii_pcs) == -EPROBE_DEFER)
++ return -EPROBE_DEFER;
+
+- err = of_get_ethdev_address(mac->of_node, eth->netdev[id]);
+- if (err == -EPROBE_DEFER)
+- return err;
++ dev_err(eth->dev, "cannot select SGMII PCS, error %ld\n",
++ PTR_ERR(mac->sgmii_pcs));
++ return PTR_ERR(mac->sgmii_pcs);
++ }
++ }
+
+- if (err) {
+- /* If the mac address is invalid, use random mac address */
+- eth_hw_addr_random(eth->netdev[id]);
+- dev_err(eth->dev, "generated random MAC address %pM\n",
+- eth->netdev[id]->dev_addr);
++ pcs_np = of_parse_phandle(mac->of_node, "pcs-handle", 1);
++ if (pcs_np) {
++ mac->usxgmii_pcs = mtk_usxgmii_pcs_get(eth->dev, pcs_np);
++ if (IS_ERR(mac->usxgmii_pcs)) {
++ if (PTR_ERR(mac->usxgmii_pcs) == -EPROBE_DEFER)
++ return -EPROBE_DEFER;
++
++ dev_err(eth->dev, "cannot select USXGMII PCS, error %ld\n",
++ PTR_ERR(mac->usxgmii_pcs));
++ return PTR_ERR(mac->usxgmii_pcs);
++ }
++ }
++
++ if (mtk_is_netsys_v3_or_greater(eth) && (mac->sgmii_pcs || mac->usxgmii_pcs)) {
++ mac->pextp = devm_of_phy_get(eth->dev, mac->of_node, NULL);
++ if (IS_ERR(mac->pextp)) {
++ if (PTR_ERR(mac->pextp) != -EPROBE_DEFER)
++ dev_err(eth->dev, "cannot get PHY, error %ld\n",
++ PTR_ERR(mac->pextp));
++
++ return PTR_ERR(mac->pextp);
++ }
+ }
+
+ memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip));
+@@ -4616,8 +4788,21 @@ static int mtk_add_mac(struct mtk_eth *e
phy_interface_zero(mac->phylink_config.supported_interfaces);
__set_bit(PHY_INTERFACE_MODE_INTERNAL,
mac->phylink_config.supported_interfaces);
phylink = phylink_create(&mac->phylink_config,
of_fwnode_handle(mac->of_node),
phy_mode, &mtk_phylink_ops);
-@@ -4810,6 +4937,13 @@ static int mtk_probe(struct platform_dev
+@@ -4662,6 +4847,26 @@ free_netdev:
+ return err;
+ }
+
++static int mtk_mac_assign_address(struct mtk_eth *eth, int i, bool test_defer_only)
++{
++ int err = of_get_ethdev_address(eth->mac[i]->of_node, eth->netdev[i]);
++
++ if (err == -EPROBE_DEFER)
++ return err;
++
++ if (test_defer_only)
++ return 0;
++
++ if (err) {
++ /* If the mac address is invalid, use random mac address */
++ eth_hw_addr_random(eth->netdev[i]);
++ dev_err(eth->dev, "generated random MAC address %pM\n",
++ eth->netdev[i]);
++ }
++
++ return 0;
++}
++
+ void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev)
+ {
+ struct net_device *dev, *tmp;
+@@ -4805,7 +5010,8 @@ static int mtk_probe(struct platform_dev
+ regmap_write(cci, 0, 3);
+ }
+
+- if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
++ if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII) &&
++ !mtk_is_netsys_v3_or_greater(eth)) {
+ err = mtk_sgmii_init(eth);
if (err)
- return err;
+@@ -4916,6 +5122,24 @@ static int mtk_probe(struct platform_dev
+ }
+ }
+
++ for (i = 0; i < MTK_MAX_DEVS; i++) {
++ if (!eth->netdev[i])
++ continue;
++
++ err = mtk_mac_assign_address(eth, i, true);
++ if (err)
++ goto err_deinit_hw;
+ }
+
-+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_USXGMII)) {
-+ err = mtk_usxgmii_init(eth);
++ for (i = 0; i < MTK_MAX_DEVS; i++) {
++ if (!eth->netdev[i])
++ continue;
+
++ err = mtk_mac_assign_address(eth, i, false);
+ if (err)
-+ return err;
++ goto err_deinit_hw;
++ }
++
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) {
+ err = devm_request_irq(eth->dev, eth->irq[0],
+ mtk_handle_irq, 0,
+@@ -5018,6 +5242,11 @@ static int mtk_remove(struct platform_de
+ mtk_stop(eth->netdev[i]);
+ mac = netdev_priv(eth->netdev[i]);
+ phylink_disconnect_phy(mac->phylink);
++ if (mac->sgmii_pcs)
++ mtk_pcs_lynxi_put(mac->sgmii_pcs);
++
++ if (mac->usxgmii_pcs)
++ mtk_usxgmii_pcs_put(mac->usxgmii_pcs);
}
- if (eth->soc->required_pctl) {
+ mtk_wed_exit();
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -502,6 +502,21 @@
+@@ -15,6 +15,7 @@
+ #include <linux/u64_stats_sync.h>
+ #include <linux/refcount.h>
+ #include <linux/phylink.h>
++#include <linux/reset.h>
+ #include <linux/rhashtable.h>
+ #include <linux/dim.h>
+ #include <linux/bitfield.h>
+@@ -502,6 +503,21 @@
#define INTF_MODE_RGMII_1000 (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED)
#define INTF_MODE_RGMII_10_100 0
/* GPIO port control registers for GMAC 2*/
#define GPIO_OD33_CTRL8 0x4c0
#define GPIO_BIAS_CTRL 0xed0
-@@ -527,6 +542,7 @@
+@@ -527,6 +543,7 @@
#define SYSCFG0_SGMII_GMAC2 ((3 << 8) & SYSCFG0_SGMII_MASK)
#define SYSCFG0_SGMII_GMAC1_V2 BIT(9)
#define SYSCFG0_SGMII_GMAC2_V2 BIT(8)
/* ethernet subsystem clock register */
-@@ -559,12 +575,74 @@
- #define ETHSYS_DMA_AG_MAP_QDMA BIT(1)
- #define ETHSYS_DMA_AG_MAP_PPE BIT(2)
-
-+/* USXGMII subsystem config registers */
-+/* Register to control speed */
-+#define RG_PHY_TOP_SPEED_CTRL1 0x80C
-+#define USXGMII_RATE_UPDATE_MODE BIT(31)
-+#define USXGMII_MAC_CK_GATED BIT(29)
-+#define USXGMII_IF_FORCE_EN BIT(28)
-+#define USXGMII_RATE_ADAPT_MODE GENMASK(10, 8)
-+#define USXGMII_RATE_ADAPT_MODE_X1 0
-+#define USXGMII_RATE_ADAPT_MODE_X2 1
-+#define USXGMII_RATE_ADAPT_MODE_X4 2
-+#define USXGMII_RATE_ADAPT_MODE_X10 3
-+#define USXGMII_RATE_ADAPT_MODE_X100 4
-+#define USXGMII_RATE_ADAPT_MODE_X5 5
-+#define USXGMII_RATE_ADAPT_MODE_X50 6
-+#define USXGMII_XFI_RX_MODE GENMASK(6, 4)
-+#define USXGMII_XFI_RX_MODE_10G 0
-+#define USXGMII_XFI_RX_MODE_5G 1
-+#define USXGMII_XFI_TX_MODE GENMASK(2, 0)
-+#define USXGMII_XFI_TX_MODE_10G 0
-+#define USXGMII_XFI_TX_MODE_5G 1
-+
-+/* Register to control PCS AN */
-+#define RG_PCS_AN_CTRL0 0x810
-+#define USXGMII_AN_RESTART BIT(31)
-+#define USXGMII_AN_SYNC_CNT GENMASK(30, 11)
-+#define USXGMII_AN_ENABLE BIT(0)
-+
-+#define RG_PCS_AN_CTRL2 0x818
-+#define USXGMII_LINK_TIMER_IDLE_DETECT GENMASK(29, 20)
-+#define USXGMII_LINK_TIMER_COMP_ACK_DETECT GENMASK(19, 10)
-+#define USXGMII_LINK_TIMER_AN_RESTART GENMASK(9, 0)
-+
-+/* Register to read PCS AN status */
-+#define RG_PCS_AN_STS0 0x81c
-+#define USXGMII_PCS_AN_WORD GENMASK(15, 0)
-+#define USXGMII_LPA_LATCH BIT(31)
-+
-+/* Register to control USXGMII XFI PLL digital */
-+#define XFI_PLL_DIG_GLB8 0x08
-+#define RG_XFI_PLL_EN BIT(31)
-+
-+/* Register to control USXGMII XFI PLL analog */
-+#define XFI_PLL_ANA_GLB8 0x108
-+#define RG_XFI_PLL_ANA_SWWA 0x02283248
-+
- /* Infrasys subsystem config registers */
- #define INFRA_MISC2 0x70c
- #define CO_QPHY_SEL BIT(0)
+@@ -565,6 +582,11 @@
#define GEPHY_MAC_SEL BIT(1)
-+/* Toprgu subsystem config registers */
-+#define TOPRGU_SWSYSRST 0x18
-+#define SWSYSRST_UNLOCK_KEY GENMASK(31, 24)
-+#define SWSYSRST_XFI_PLL_GRST BIT(16)
-+#define SWSYSRST_XFI_PEXPT1_GRST BIT(15)
-+#define SWSYSRST_XFI_PEXPT0_GRST BIT(14)
-+#define SWSYSRST_XFI1_GRST BIT(13)
-+#define SWSYSRST_XFI0_GRST BIT(12)
-+#define SWSYSRST_SGMII1_GRST BIT(2)
-+#define SWSYSRST_SGMII0_GRST BIT(1)
-+#define TOPRGU_SWSYSRST_EN 0xFC
-+
/* Top misc registers */
+#define TOP_MISC_NETSYS_PCS_MUX 0x84
+#define NETSYS_PCS_MUX_MASK GENMASK(1, 0)
#define USB_PHY_SWITCH_REG 0x218
#define QPHY_SEL_MASK GENMASK(1, 0)
#define SGMII_QPHY_SEL 0x2
-@@ -589,6 +667,8 @@
+@@ -589,6 +611,8 @@
#define MT7628_SDM_RBCNT (MT7628_SDM_OFFSET + 0x10c)
#define MT7628_SDM_CS_ERR (MT7628_SDM_OFFSET + 0x110)
#define MTK_FE_CDM1_FSM 0x220
#define MTK_FE_CDM2_FSM 0x224
#define MTK_FE_CDM3_FSM 0x238
-@@ -597,6 +677,11 @@
+@@ -597,6 +621,11 @@
#define MTK_FE_CDM6_FSM 0x328
#define MTK_FE_GDM1_FSM 0x228
#define MTK_FE_GDM2_FSM 0x22C
#define MTK_MAC_FSM(x) (0x1010C + ((x) * 0x100))
-@@ -943,6 +1028,8 @@ enum mkt_eth_capabilities {
+@@ -721,12 +750,8 @@ enum mtk_clks_map {
+ MTK_CLK_ETHWARP_WOCPU2,
+ MTK_CLK_ETHWARP_WOCPU1,
+ MTK_CLK_ETHWARP_WOCPU0,
+- MTK_CLK_TOP_USXGMII_SBUS_0_SEL,
+- MTK_CLK_TOP_USXGMII_SBUS_1_SEL,
+ MTK_CLK_TOP_SGM_0_SEL,
+ MTK_CLK_TOP_SGM_1_SEL,
+- MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL,
+- MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL,
+ MTK_CLK_TOP_ETH_GMII_SEL,
+ MTK_CLK_TOP_ETH_REFCK_50M_SEL,
+ MTK_CLK_TOP_ETH_SYS_200M_SEL,
+@@ -797,19 +822,9 @@ enum mtk_clks_map {
+ BIT_ULL(MTK_CLK_GP3) | BIT_ULL(MTK_CLK_XGP1) | \
+ BIT_ULL(MTK_CLK_XGP2) | BIT_ULL(MTK_CLK_XGP3) | \
+ BIT_ULL(MTK_CLK_CRYPTO) | \
+- BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
+- BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
+- BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
+- BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
+ BIT_ULL(MTK_CLK_ETHWARP_WOCPU2) | \
+ BIT_ULL(MTK_CLK_ETHWARP_WOCPU1) | \
+ BIT_ULL(MTK_CLK_ETHWARP_WOCPU0) | \
+- BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_0_SEL) | \
+- BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_1_SEL) | \
+- BIT_ULL(MTK_CLK_TOP_SGM_0_SEL) | \
+- BIT_ULL(MTK_CLK_TOP_SGM_1_SEL) | \
+- BIT_ULL(MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL) | \
+- BIT_ULL(MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL) | \
+ BIT_ULL(MTK_CLK_TOP_ETH_GMII_SEL) | \
+ BIT_ULL(MTK_CLK_TOP_ETH_REFCK_50M_SEL) | \
+ BIT_ULL(MTK_CLK_TOP_ETH_SYS_200M_SEL) | \
+@@ -943,6 +958,8 @@ enum mkt_eth_capabilities {
MTK_RGMII_BIT = 0,
MTK_TRGMII_BIT,
MTK_SGMII_BIT,
MTK_ESW_BIT,
MTK_GEPHY_BIT,
MTK_MUX_BIT,
-@@ -963,8 +1050,11 @@ enum mkt_eth_capabilities {
+@@ -963,8 +980,11 @@ enum mkt_eth_capabilities {
MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT,
MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT,
MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT,
/* PATH BITS */
MTK_ETH_PATH_GMAC1_RGMII_BIT,
-@@ -972,14 +1062,21 @@ enum mkt_eth_capabilities {
+@@ -972,14 +992,21 @@ enum mkt_eth_capabilities {
MTK_ETH_PATH_GMAC1_SGMII_BIT,
MTK_ETH_PATH_GMAC2_RGMII_BIT,
MTK_ETH_PATH_GMAC2_SGMII_BIT,
#define MTK_ESW BIT_ULL(MTK_ESW_BIT)
#define MTK_GEPHY BIT_ULL(MTK_GEPHY_BIT)
#define MTK_MUX BIT_ULL(MTK_MUX_BIT)
-@@ -1002,10 +1099,16 @@ enum mkt_eth_capabilities {
+@@ -1002,10 +1029,16 @@ enum mkt_eth_capabilities {
BIT_ULL(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT)
#define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \
BIT_ULL(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT)
/* Supported path present on SoCs */
#define MTK_ETH_PATH_GMAC1_RGMII BIT_ULL(MTK_ETH_PATH_GMAC1_RGMII_BIT)
-@@ -1013,8 +1116,13 @@ enum mkt_eth_capabilities {
+@@ -1013,8 +1046,13 @@ enum mkt_eth_capabilities {
#define MTK_ETH_PATH_GMAC1_SGMII BIT_ULL(MTK_ETH_PATH_GMAC1_SGMII_BIT)
#define MTK_ETH_PATH_GMAC2_RGMII BIT_ULL(MTK_ETH_PATH_GMAC2_RGMII_BIT)
#define MTK_ETH_PATH_GMAC2_SGMII BIT_ULL(MTK_ETH_PATH_GMAC2_SGMII_BIT)
#define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII)
#define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
-@@ -1022,7 +1130,12 @@ enum mkt_eth_capabilities {
+@@ -1022,7 +1060,12 @@ enum mkt_eth_capabilities {
#define MTK_GMAC2_RGMII (MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII)
#define MTK_GMAC2_SGMII (MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII)
#define MTK_GMAC2_GEPHY (MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY)
/* MUXes present on SoCs */
/* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */
-@@ -1041,10 +1154,20 @@ enum mkt_eth_capabilities {
+@@ -1041,10 +1084,20 @@ enum mkt_eth_capabilities {
(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \
MTK_SHARED_SGMII)
#define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x))
#define MT7621_CAPS (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \
-@@ -1076,8 +1199,12 @@ enum mkt_eth_capabilities {
+@@ -1076,8 +1129,12 @@ enum mkt_eth_capabilities {
MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
MTK_RSTCTRL_PPE1 | MTK_SRAM)
struct mtk_tx_dma_desc_info {
dma_addr_t addr;
-@@ -1187,6 +1314,24 @@ struct mtk_soc_data {
- /* currently no SoC has more than 3 macs */
- #define MTK_MAX_DEVS 3
-
-+/* struct mtk_usxgmii_pcs - This structure holds each usxgmii regmap and
-+ * associated data
-+ * @regmap: The register map pointing at the range used to setup
-+ * USXGMII modes
-+ * @interface: Currently selected interface mode
-+ * @id: The element is used to record the index of PCS
-+ * @pcs: Phylink PCS structure
-+ */
-+struct mtk_usxgmii_pcs {
-+ struct mtk_eth *eth;
-+ struct regmap *regmap;
-+ struct phylink_pcs *wrapped_sgmii_pcs;
-+ phy_interface_t interface;
-+ u8 id;
-+ unsigned int mode;
-+ struct phylink_pcs pcs;
-+};
-+
- /* struct mtk_eth - This is the main datasructure for holding the state
- * of the driver
- * @dev: The device pointer
-@@ -1207,6 +1352,12 @@ struct mtk_soc_data {
- * @infra: The register map pointing at the range used to setup
- * SGMII and GePHY path
- * @sgmii_pcs: Pointers to mtk-pcs-lynxi phylink_pcs instances
-+ * @sgmii_wrapped_pcs: Pointers to NETSYSv3 wrapper PCS instances
-+ * @usxgmii_pll: The register map pointing at the range used to control
-+ * the USXGMII SerDes PLL
-+ * @regmap_pextp: The register map pointing at the range used to setup
-+ * PHYA
-+ * @usxgmii_pcs: Pointer to array of pointers to struct for USXGMII PCS
- * @pctl: The register map pointing at the range used to setup
- * GMAC port drive/slew values
- * @dma_refcnt: track how many netdevs are using the DMA engine
-@@ -1250,6 +1401,10 @@ struct mtk_eth {
- struct regmap *ethsys;
- struct regmap *infra;
- struct phylink_pcs *sgmii_pcs[MTK_MAX_DEVS];
-+ struct regmap *toprgu;
-+ struct regmap *usxgmii_pll;
-+ struct regmap *regmap_pextp[MTK_MAX_DEVS];
-+ struct mtk_usxgmii_pcs *usxgmii_pcs[MTK_MAX_DEVS];
- struct regmap *pctl;
- bool hwlro;
- refcount_t dma_refcnt;
-@@ -1437,6 +1592,19 @@ static inline u32 mtk_get_ib2_multicast_
+@@ -1314,6 +1371,9 @@ struct mtk_mac {
+ struct device_node *of_node;
+ struct phylink *phylink;
+ struct phylink_config phylink_config;
++ struct phylink_pcs *sgmii_pcs;
++ struct phylink_pcs *usxgmii_pcs;
++ struct phy *pextp;
+ struct mtk_eth *hw;
+ struct mtk_hw_stats *hw_stats;
+ __be32 hwlro_ip[MTK_MAX_LRO_IP_CNT];
+@@ -1437,6 +1497,19 @@ static inline u32 mtk_get_ib2_multicast_
return MTK_FOE_IB2_MULTICAST;
}
/* read the hardware status register */
void mtk_stats_update_mac(struct mtk_mac *mac);
-@@ -1445,8 +1613,10 @@ u32 mtk_r32(struct mtk_eth *eth, unsigne
+@@ -1445,8 +1518,10 @@ u32 mtk_r32(struct mtk_eth *eth, unsigne
u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg);
int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id);
int mtk_eth_offload_init(struct mtk_eth *eth);
int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type,
-@@ -1456,5 +1626,63 @@ int mtk_flow_offload_cmd(struct mtk_eth
- void mtk_flow_offload_cleanup(struct mtk_eth *eth, struct list_head *list);
- void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev);
-
-+static inline int mtk_mac2xgmii_id(struct mtk_eth *eth, int mac_id)
-+{
-+ int xgmii_id = mac_id;
-+
-+ if (mtk_is_netsys_v3_or_greater(eth)) {
-+ switch (mac_id) {
-+ case MTK_GMAC1_ID:
-+ case MTK_GMAC2_ID:
-+ xgmii_id = 1;
-+ break;
-+ case MTK_GMAC3_ID:
-+ xgmii_id = 0;
-+ break;
-+ default:
-+ xgmii_id = -1;
-+ }
-+ }
-+
-+ return MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII) ? 0 : xgmii_id;
-+}
-+
-+static inline int mtk_xgmii2mac_id(struct mtk_eth *eth, int xgmii_id)
-+{
-+ int mac_id = xgmii_id;
-+
-+ if (mtk_is_netsys_v3_or_greater(eth)) {
-+ switch (xgmii_id) {
-+ case 0:
-+ mac_id = 2;
-+ break;
-+ case 1:
-+ mac_id = 1;
-+ break;
-+ default:
-+ mac_id = -1;
-+ }
-+ }
-+
-+ return mac_id;
-+}
-+
-+#ifdef CONFIG_NET_MEDIATEK_SOC_USXGMII
-+struct phylink_pcs *mtk_sgmii_wrapper_select_pcs(struct mtk_eth *eth, int id);
-+struct phylink_pcs *mtk_usxgmii_select_pcs(struct mtk_eth *eth, int id);
-+int mtk_usxgmii_init(struct mtk_eth *eth);
-+#else
-+static inline struct phylink_pcs *mtk_sgmii_wrapper_select_pcs(struct mtk_eth *eth, int id)
-+{
-+ return NULL;
-+}
-+
-+static inline struct phylink_pcs *mtk_usxgmii_select_pcs(struct mtk_eth *eth, int id)
-+{
-+ return NULL;
-+}
-+
-+static inline int mtk_usxgmii_init(struct mtk_eth *eth) { return 0; }
-+#endif /* NET_MEDIATEK_SOC_USXGMII */
-
- #endif /* MTK_ETH_H */
---- /dev/null
-+++ b/drivers/net/ethernet/mediatek/mtk_usxgmii.c
-@@ -0,0 +1,690 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2023 MediaTek Inc.
-+ * Author: Henry Yen <henry.yen@mediatek.com>
-+ * Daniel Golle <daniel@makrotopia.org>
-+ */
-+
-+#include <linux/mfd/syscon.h>
-+#include <linux/of.h>
-+#include <linux/regmap.h>
-+#include "mtk_eth_soc.h"
-+
-+static struct mtk_usxgmii_pcs *pcs_to_mtk_usxgmii_pcs(struct phylink_pcs *pcs)
-+{
-+ return container_of(pcs, struct mtk_usxgmii_pcs, pcs);
-+}
-+
-+static int mtk_xfi_pextp_init(struct mtk_eth *eth)
-+{
-+ struct device *dev = eth->dev;
-+ struct device_node *r = dev->of_node;
-+ struct device_node *np;
-+ int i;
-+
-+ for (i = 0; i < MTK_MAX_DEVS; i++) {
-+ np = of_parse_phandle(r, "mediatek,xfi-pextp", i);
-+ if (!np)
-+ break;
-+
-+ eth->regmap_pextp[i] = syscon_node_to_regmap(np);
-+ if (IS_ERR(eth->regmap_pextp[i]))
-+ return PTR_ERR(eth->regmap_pextp[i]);
-+ }
-+
-+ return 0;
-+}
-+
-+static int mtk_xfi_pll_init(struct mtk_eth *eth)
-+{
-+ struct device_node *r = eth->dev->of_node;
-+ struct device_node *np;
-+
-+ np = of_parse_phandle(r, "mediatek,xfi-pll", 0);
-+ if (!np)
-+ return -1;
-+
-+ eth->usxgmii_pll = syscon_node_to_regmap(np);
-+ if (IS_ERR(eth->usxgmii_pll))
-+ return PTR_ERR(eth->usxgmii_pll);
-+
-+ return 0;
-+}
-+
-+static int mtk_toprgu_init(struct mtk_eth *eth)
-+{
-+ struct device_node *r = eth->dev->of_node;
-+ struct device_node *np;
-+
-+ np = of_parse_phandle(r, "mediatek,toprgu", 0);
-+ if (!np)
-+ return -1;
-+
-+ eth->toprgu = syscon_node_to_regmap(np);
-+ if (IS_ERR(eth->toprgu))
-+ return PTR_ERR(eth->toprgu);
-+
-+ return 0;
-+}
-+
-+static int mtk_xfi_pll_enable(struct mtk_eth *eth)
-+{
-+ u32 val = 0;
-+
-+ if (!eth->usxgmii_pll)
-+ return -EINVAL;
-+
-+ /* Add software workaround for USXGMII PLL TCL issue */
-+ regmap_write(eth->usxgmii_pll, XFI_PLL_ANA_GLB8, RG_XFI_PLL_ANA_SWWA);
-+
-+ regmap_read(eth->usxgmii_pll, XFI_PLL_DIG_GLB8, &val);
-+ val |= RG_XFI_PLL_EN;
-+ regmap_write(eth->usxgmii_pll, XFI_PLL_DIG_GLB8, val);
-+
-+ return 0;
-+}
-+
-+static void mtk_usxgmii_setup_phya(struct regmap *pextp, phy_interface_t interface, int id)
-+{
-+ bool is_10g = (interface == PHY_INTERFACE_MODE_10GBASER ||
-+ interface == PHY_INTERFACE_MODE_USXGMII);
-+ bool is_2p5g = (interface == PHY_INTERFACE_MODE_2500BASEX);
-+ bool is_5g = (interface == PHY_INTERFACE_MODE_5GBASER);
-+
-+ /* Setup operation mode */
-+ if (is_10g)
-+ regmap_write(pextp, 0x9024, 0x00C9071C);
-+ else
-+ regmap_write(pextp, 0x9024, 0x00D9071C);
-+
-+ if (is_5g)
-+ regmap_write(pextp, 0x2020, 0xAAA5A5AA);
-+ else
-+ regmap_write(pextp, 0x2020, 0xAA8585AA);
-+
-+ if (is_2p5g || is_5g || is_10g) {
-+ regmap_write(pextp, 0x2030, 0x0C020707);
-+ regmap_write(pextp, 0x2034, 0x0E050F0F);
-+ regmap_write(pextp, 0x2040, 0x00140032);
-+ } else {
-+ regmap_write(pextp, 0x2030, 0x0C020207);
-+ regmap_write(pextp, 0x2034, 0x0E05050F);
-+ regmap_write(pextp, 0x2040, 0x00200032);
-+ }
-+
-+ if (is_2p5g || is_10g)
-+ regmap_write(pextp, 0x50F0, 0x00C014AA);
-+ else if (is_5g)
-+ regmap_write(pextp, 0x50F0, 0x00C018AA);
-+ else
-+ regmap_write(pextp, 0x50F0, 0x00C014BA);
-+
-+ if (is_5g) {
-+ regmap_write(pextp, 0x50E0, 0x3777812B);
-+ regmap_write(pextp, 0x506C, 0x005C9CFF);
-+ regmap_write(pextp, 0x5070, 0x9DFAFAFA);
-+ regmap_write(pextp, 0x5074, 0x273F3F3F);
-+ regmap_write(pextp, 0x5078, 0xA8883868);
-+ regmap_write(pextp, 0x507C, 0x14661466);
-+ } else {
-+ regmap_write(pextp, 0x50E0, 0x3777C12B);
-+ regmap_write(pextp, 0x506C, 0x005F9CFF);
-+ regmap_write(pextp, 0x5070, 0x9D9DFAFA);
-+ regmap_write(pextp, 0x5074, 0x27273F3F);
-+ regmap_write(pextp, 0x5078, 0xA7883C68);
-+ regmap_write(pextp, 0x507C, 0x11661166);
-+ }
-+
-+ if (is_2p5g || is_10g) {
-+ regmap_write(pextp, 0x5080, 0x0E000AAF);
-+ regmap_write(pextp, 0x5084, 0x08080D0D);
-+ regmap_write(pextp, 0x5088, 0x02030909);
-+ } else if (is_5g) {
-+ regmap_write(pextp, 0x5080, 0x0E001ABF);
-+ regmap_write(pextp, 0x5084, 0x080B0D0D);
-+ regmap_write(pextp, 0x5088, 0x02050909);
-+ } else {
-+ regmap_write(pextp, 0x5080, 0x0E000EAF);
-+ regmap_write(pextp, 0x5084, 0x08080E0D);
-+ regmap_write(pextp, 0x5088, 0x02030B09);
-+ }
-+
-+ if (is_5g) {
-+ regmap_write(pextp, 0x50E4, 0x0C000000);
-+ regmap_write(pextp, 0x50E8, 0x04000000);
-+ } else {
-+ regmap_write(pextp, 0x50E4, 0x0C0C0000);
-+ regmap_write(pextp, 0x50E8, 0x04040000);
-+ }
-+
-+ if (is_2p5g || mtk_interface_mode_is_xgmii(interface))
-+ regmap_write(pextp, 0x50EC, 0x0F0F0C06);
-+ else
-+ regmap_write(pextp, 0x50EC, 0x0F0F0606);
-+
-+ if (is_5g) {
-+ regmap_write(pextp, 0x50A8, 0x50808C8C);
-+ regmap_write(pextp, 0x6004, 0x18000000);
-+ } else {
-+ regmap_write(pextp, 0x50A8, 0x506E8C8C);
-+ regmap_write(pextp, 0x6004, 0x18190000);
-+ }
-+
-+ if (is_10g)
-+ regmap_write(pextp, 0x00F8, 0x01423342);
-+ else if (is_5g)
-+ regmap_write(pextp, 0x00F8, 0x00A132A1);
-+ else if (is_2p5g)
-+ regmap_write(pextp, 0x00F8, 0x009C329C);
-+ else
-+ regmap_write(pextp, 0x00F8, 0x00FA32FA);
-+
-+ /* Force SGDT_OUT off and select PCS */
-+ if (mtk_interface_mode_is_xgmii(interface))
-+ regmap_write(pextp, 0x00F4, 0x80201F20);
-+ else
-+ regmap_write(pextp, 0x00F4, 0x80201F21);
-+
-+ /* Force GLB_CKDET_OUT */
-+ regmap_write(pextp, 0x0030, 0x00050C00);
-+
-+ /* Force AEQ on */
-+ regmap_write(pextp, 0x0070, 0x02002800);
-+ ndelay(1020);
-+
-+ /* Setup DA default value */
-+ regmap_write(pextp, 0x30B0, 0x00000020);
-+ regmap_write(pextp, 0x3028, 0x00008A01);
-+ regmap_write(pextp, 0x302C, 0x0000A884);
-+ regmap_write(pextp, 0x3024, 0x00083002);
-+ if (mtk_interface_mode_is_xgmii(interface)) {
-+ regmap_write(pextp, 0x3010, 0x00022220);
-+ regmap_write(pextp, 0x5064, 0x0F020A01);
-+ regmap_write(pextp, 0x50B4, 0x06100600);
-+ if (interface == PHY_INTERFACE_MODE_USXGMII)
-+ regmap_write(pextp, 0x3048, 0x40704000);
-+ else
-+ regmap_write(pextp, 0x3048, 0x47684100);
-+ } else {
-+ regmap_write(pextp, 0x3010, 0x00011110);
-+ regmap_write(pextp, 0x3048, 0x40704000);
-+ }
-+
-+ if (!mtk_interface_mode_is_xgmii(interface) && !is_2p5g)
-+ regmap_write(pextp, 0x3064, 0x0000C000);
-+
-+ if (interface == PHY_INTERFACE_MODE_USXGMII) {
-+ regmap_write(pextp, 0x3050, 0xA8000000);
-+ regmap_write(pextp, 0x3054, 0x000000AA);
-+ } else if (mtk_interface_mode_is_xgmii(interface)) {
-+ regmap_write(pextp, 0x3050, 0x00000000);
-+ regmap_write(pextp, 0x3054, 0x00000000);
-+ } else {
-+ regmap_write(pextp, 0x3050, 0xA8000000);
-+ regmap_write(pextp, 0x3054, 0x000000AA);
-+ }
-+
-+ if (mtk_interface_mode_is_xgmii(interface))
-+ regmap_write(pextp, 0x306C, 0x00000F00);
-+ else if (is_2p5g)
-+ regmap_write(pextp, 0x306C, 0x22000F00);
-+ else
-+ regmap_write(pextp, 0x306C, 0x20200F00);
-+
-+ if (interface == PHY_INTERFACE_MODE_10GBASER && id == 0)
-+ regmap_write(pextp, 0xA008, 0x0007B400);
-+
-+ if (mtk_interface_mode_is_xgmii(interface))
-+ regmap_write(pextp, 0xA060, 0x00040000);
-+ else
-+ regmap_write(pextp, 0xA060, 0x00050000);
-+
-+ if (is_10g)
-+ regmap_write(pextp, 0x90D0, 0x00000001);
-+ else if (is_5g)
-+ regmap_write(pextp, 0x90D0, 0x00000003);
-+ else if (is_2p5g)
-+ regmap_write(pextp, 0x90D0, 0x00000005);
-+ else
-+ regmap_write(pextp, 0x90D0, 0x00000007);
-+
-+ /* Release reset */
-+ regmap_write(pextp, 0x0070, 0x0200E800);
-+ usleep_range(150, 500);
-+
-+ /* Switch to P0 */
-+ regmap_write(pextp, 0x0070, 0x0200C111);
-+ ndelay(1020);
-+ regmap_write(pextp, 0x0070, 0x0200C101);
-+ usleep_range(15, 50);
-+
-+ if (mtk_interface_mode_is_xgmii(interface)) {
-+ /* Switch to Gen3 */
-+ regmap_write(pextp, 0x0070, 0x0202C111);
-+ } else {
-+ /* Switch to Gen2 */
-+ regmap_write(pextp, 0x0070, 0x0201C111);
-+ }
-+ ndelay(1020);
-+ if (mtk_interface_mode_is_xgmii(interface))
-+ regmap_write(pextp, 0x0070, 0x0202C101);
-+ else
-+ regmap_write(pextp, 0x0070, 0x0201C101);
-+ usleep_range(100, 500);
-+ regmap_write(pextp, 0x30B0, 0x00000030);
-+ if (mtk_interface_mode_is_xgmii(interface))
-+ regmap_write(pextp, 0x00F4, 0x80201F00);
-+ else
-+ regmap_write(pextp, 0x00F4, 0x80201F01);
-+
-+ regmap_write(pextp, 0x3040, 0x30000000);
-+ usleep_range(400, 1000);
-+}
-+
-+static void mtk_usxgmii_reset(struct mtk_eth *eth, int id)
-+{
-+ u32 toggle, val;
-+
-+ if (id >= MTK_MAX_DEVS || !eth->toprgu)
-+ return;
-+
-+ switch (id) {
-+ case 0:
-+ toggle = SWSYSRST_XFI_PEXPT0_GRST | SWSYSRST_XFI0_GRST |
-+ SWSYSRST_SGMII0_GRST;
-+ break;
-+ case 1:
-+ toggle = SWSYSRST_XFI_PEXPT1_GRST | SWSYSRST_XFI1_GRST |
-+ SWSYSRST_SGMII1_GRST;
-+ break;
-+ default:
-+ return;
-+ }
-+
-+ /* Enable software reset */
-+ regmap_set_bits(eth->toprgu, TOPRGU_SWSYSRST_EN, toggle);
-+
-+ /* Assert USXGMII reset */
-+ regmap_set_bits(eth->toprgu, TOPRGU_SWSYSRST,
-+ FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88) | toggle);
-+
-+ usleep_range(100, 500);
-+
-+ /* De-assert USXGMII reset */
-+ regmap_read(eth->toprgu, TOPRGU_SWSYSRST, &val);
-+ val |= FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88);
-+ val &= ~toggle;
-+ regmap_write(eth->toprgu, TOPRGU_SWSYSRST, val);
-+
-+ /* Disable software reset */
-+ regmap_clear_bits(eth->toprgu, TOPRGU_SWSYSRST_EN, toggle);
-+
-+ mdelay(10);
-+}
-+
-+/* As the USXGMII PHYA is shared with the 1000Base-X/2500Base-X/Cisco SGMII unit
-+ * the psc-mtk-lynxi instance needs to be wrapped, so that calls to .pcs_config
-+ * also trigger an initial reset and subsequent configuration of the PHYA.
-+ */
-+struct mtk_sgmii_wrapper_pcs {
-+ struct mtk_eth *eth;
-+ struct phylink_pcs *wrapped_pcs;
-+ u8 id;
-+ struct phylink_pcs pcs;
-+};
-+
-+static int mtk_sgmii_wrapped_pcs_config(struct phylink_pcs *pcs,
-+ unsigned int mode,
-+ phy_interface_t interface,
-+ const unsigned long *advertising,
-+ bool permit_pause_to_mac)
-+{
-+ struct mtk_sgmii_wrapper_pcs *wp = container_of(pcs, struct mtk_sgmii_wrapper_pcs, pcs);
-+ bool full_reconf;
-+ int ret;
-+
-+ full_reconf = interface != wp->eth->usxgmii_pcs[wp->id]->interface;
-+ if (full_reconf) {
-+ mtk_xfi_pll_enable(wp->eth);
-+ mtk_usxgmii_reset(wp->eth, wp->id);
-+ }
-+
-+ ret = wp->wrapped_pcs->ops->pcs_config(wp->wrapped_pcs, mode, interface,
-+ advertising, permit_pause_to_mac);
-+
-+ if (full_reconf)
-+ mtk_usxgmii_setup_phya(wp->eth->regmap_pextp[wp->id], interface, wp->id);
-+
-+ wp->eth->usxgmii_pcs[wp->id]->interface = interface;
-+
-+ return ret;
-+}
-+
-+static void mtk_sgmii_wrapped_pcs_get_state(struct phylink_pcs *pcs,
-+ struct phylink_link_state *state)
-+{
-+ struct mtk_sgmii_wrapper_pcs *wp = container_of(pcs, struct mtk_sgmii_wrapper_pcs, pcs);
-+
-+ return wp->wrapped_pcs->ops->pcs_get_state(wp->wrapped_pcs, state);
-+}
-+
-+static void mtk_sgmii_wrapped_pcs_an_restart(struct phylink_pcs *pcs)
-+{
-+ struct mtk_sgmii_wrapper_pcs *wp = container_of(pcs, struct mtk_sgmii_wrapper_pcs, pcs);
-+
-+ wp->wrapped_pcs->ops->pcs_an_restart(wp->wrapped_pcs);
-+}
-+
-+static void mtk_sgmii_wrapped_pcs_link_up(struct phylink_pcs *pcs,
-+ unsigned int mode,
-+ phy_interface_t interface, int speed,
-+ int duplex)
-+{
-+ struct mtk_sgmii_wrapper_pcs *wp = container_of(pcs, struct mtk_sgmii_wrapper_pcs, pcs);
-+
-+ wp->wrapped_pcs->ops->pcs_link_up(wp->wrapped_pcs, mode, interface, speed, duplex);
-+}
-+
-+static void mtk_sgmii_wrapped_pcs_disable(struct phylink_pcs *pcs)
-+{
-+ struct mtk_sgmii_wrapper_pcs *wp = container_of(pcs, struct mtk_sgmii_wrapper_pcs, pcs);
-+
-+ wp->wrapped_pcs->ops->pcs_disable(wp->wrapped_pcs);
-+
-+ wp->eth->usxgmii_pcs[wp->id]->interface = PHY_INTERFACE_MODE_NA;
-+}
-+
-+static const struct phylink_pcs_ops mtk_sgmii_wrapped_pcs_ops = {
-+ .pcs_get_state = mtk_sgmii_wrapped_pcs_get_state,
-+ .pcs_config = mtk_sgmii_wrapped_pcs_config,
-+ .pcs_an_restart = mtk_sgmii_wrapped_pcs_an_restart,
-+ .pcs_link_up = mtk_sgmii_wrapped_pcs_link_up,
-+ .pcs_disable = mtk_sgmii_wrapped_pcs_disable,
-+};
-+
-+static int mtk_sgmii_wrapper_init(struct mtk_eth *eth)
-+{
-+ struct mtk_sgmii_wrapper_pcs *wp;
-+ int i;
-+
-+ for (i = 0; i < MTK_MAX_DEVS; i++) {
-+ if (!eth->sgmii_pcs[i])
-+ continue;
-+
-+ if (!eth->usxgmii_pcs[i])
-+ continue;
-+
-+ /* Make sure all PCS ops are supported by wrapped PCS */
-+ if (!eth->sgmii_pcs[i]->ops->pcs_get_state ||
-+ !eth->sgmii_pcs[i]->ops->pcs_config ||
-+ !eth->sgmii_pcs[i]->ops->pcs_an_restart ||
-+ !eth->sgmii_pcs[i]->ops->pcs_link_up ||
-+ !eth->sgmii_pcs[i]->ops->pcs_disable)
-+ return -EOPNOTSUPP;
-+
-+ wp = devm_kzalloc(eth->dev, sizeof(*wp), GFP_KERNEL);
-+ if (!wp)
-+ return -ENOMEM;
-+
-+ wp->wrapped_pcs = eth->sgmii_pcs[i];
-+ wp->id = i;
-+ wp->pcs.poll = true;
-+ wp->pcs.ops = &mtk_sgmii_wrapped_pcs_ops;
-+ wp->eth = eth;
-+
-+ eth->usxgmii_pcs[i]->wrapped_sgmii_pcs = &wp->pcs;
-+ }
-+
-+ return 0;
-+}
-+
-+struct phylink_pcs *mtk_sgmii_wrapper_select_pcs(struct mtk_eth *eth, int mac_id)
-+{
-+ u32 xgmii_id = mtk_mac2xgmii_id(eth, mac_id);
-+
-+ if (!eth->usxgmii_pcs[xgmii_id])
-+ return NULL;
-+
-+ return eth->usxgmii_pcs[xgmii_id]->wrapped_sgmii_pcs;
-+}
-+
-+static int mtk_usxgmii_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
-+ phy_interface_t interface,
-+ const unsigned long *advertising,
-+ bool permit_pause_to_mac)
-+{
-+ struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
-+ struct mtk_eth *eth = mpcs->eth;
-+ struct regmap *pextp = eth->regmap_pextp[mpcs->id];
-+ unsigned int an_ctrl = 0, link_timer = 0, xfi_mode = 0, adapt_mode = 0;
-+ bool mode_changed = false;
-+
-+ if (!pextp)
-+ return -ENODEV;
-+
-+ if (interface == PHY_INTERFACE_MODE_USXGMII) {
-+ an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0x1FF) | USXGMII_AN_ENABLE;
-+ link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x7B) |
-+ FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x7B) |
-+ FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x7B);
-+ xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_RX_MODE_10G) |
-+ FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_TX_MODE_10G);
-+ } else if (interface == PHY_INTERFACE_MODE_10GBASER) {
-+ an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0x1FF);
-+ link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x7B) |
-+ FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x7B) |
-+ FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x7B);
-+ xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_RX_MODE_10G) |
-+ FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_TX_MODE_10G);
-+ adapt_mode = USXGMII_RATE_UPDATE_MODE;
-+ } else if (interface == PHY_INTERFACE_MODE_5GBASER) {
-+ an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0xFF);
-+ link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x3D) |
-+ FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x3D) |
-+ FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x3D);
-+ xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_RX_MODE_5G) |
-+ FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_TX_MODE_5G);
-+ adapt_mode = USXGMII_RATE_UPDATE_MODE;
-+ } else {
-+ return -EINVAL;
-+ }
-+
-+ adapt_mode |= FIELD_PREP(USXGMII_RATE_ADAPT_MODE, USXGMII_RATE_ADAPT_MODE_X1);
-+
-+ if (mpcs->interface != interface) {
-+ mpcs->interface = interface;
-+ mode_changed = true;
-+ }
-+
-+ mtk_xfi_pll_enable(eth);
-+ mtk_usxgmii_reset(eth, mpcs->id);
-+
-+ /* Setup USXGMII AN ctrl */
-+ regmap_update_bits(mpcs->regmap, RG_PCS_AN_CTRL0,
-+ USXGMII_AN_SYNC_CNT | USXGMII_AN_ENABLE,
-+ an_ctrl);
-+
-+ regmap_update_bits(mpcs->regmap, RG_PCS_AN_CTRL2,
-+ USXGMII_LINK_TIMER_IDLE_DETECT |
-+ USXGMII_LINK_TIMER_COMP_ACK_DETECT |
-+ USXGMII_LINK_TIMER_AN_RESTART,
-+ link_timer);
-+
-+ mpcs->mode = mode;
-+
-+ /* Gated MAC CK */
-+ regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1,
-+ USXGMII_MAC_CK_GATED, USXGMII_MAC_CK_GATED);
-+
-+ /* Enable interface force mode */
-+ regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1,
-+ USXGMII_IF_FORCE_EN, USXGMII_IF_FORCE_EN);
-+
-+ /* Setup USXGMII adapt mode */
-+ regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1,
-+ USXGMII_RATE_UPDATE_MODE | USXGMII_RATE_ADAPT_MODE,
-+ adapt_mode);
-+
-+ /* Setup USXGMII speed */
-+ regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1,
-+ USXGMII_XFI_RX_MODE | USXGMII_XFI_TX_MODE,
-+ xfi_mode);
-+
-+ usleep_range(1, 10);
-+
-+ /* Un-gated MAC CK */
-+ regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1,
-+ USXGMII_MAC_CK_GATED, 0);
-+
-+ usleep_range(1, 10);
-+
-+ /* Disable interface force mode for the AN mode */
-+ if (an_ctrl & USXGMII_AN_ENABLE)
-+ regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1,
-+ USXGMII_IF_FORCE_EN, 0);
-+
-+ /* Setup USXGMIISYS with the determined property */
-+ mtk_usxgmii_setup_phya(pextp, interface, mpcs->id);
-+
-+ return mode_changed;
-+}
-+
-+static void mtk_usxgmii_pcs_get_state(struct phylink_pcs *pcs,
-+ struct phylink_link_state *state)
-+{
-+ struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
-+ struct mtk_eth *eth = mpcs->eth;
-+ struct mtk_mac *mac = eth->mac[mtk_xgmii2mac_id(eth, mpcs->id)];
-+ u32 val = 0;
-+
-+ regmap_read(mpcs->regmap, RG_PCS_AN_CTRL0, &val);
-+ if (FIELD_GET(USXGMII_AN_ENABLE, val)) {
-+ /* Refresh LPA by inverting LPA_LATCH */
-+ regmap_read(mpcs->regmap, RG_PCS_AN_STS0, &val);
-+ regmap_update_bits(mpcs->regmap, RG_PCS_AN_STS0,
-+ USXGMII_LPA_LATCH,
-+ !(val & USXGMII_LPA_LATCH));
-+
-+ regmap_read(mpcs->regmap, RG_PCS_AN_STS0, &val);
-+
-+ phylink_decode_usxgmii_word(state, FIELD_GET(USXGMII_PCS_AN_WORD,
-+ val));
-+
-+ state->interface = mpcs->interface;
-+ } else {
-+ val = mtk_r32(mac->hw, MTK_XGMAC_STS(mac->id));
-+
-+ if (mac->id == MTK_GMAC2_ID)
-+ val >>= 16;
-+
-+ switch (FIELD_GET(MTK_USXGMII_PCS_MODE, val)) {
-+ case 0:
-+ state->speed = SPEED_10000;
-+ break;
-+ case 1:
-+ state->speed = SPEED_5000;
-+ break;
-+ case 2:
-+ state->speed = SPEED_2500;
-+ break;
-+ case 3:
-+ state->speed = SPEED_1000;
-+ break;
-+ }
-+
-+ state->interface = mpcs->interface;
-+ state->link = FIELD_GET(MTK_USXGMII_PCS_LINK, val);
-+ state->duplex = DUPLEX_FULL;
-+ }
-+
-+ /* Continuously repeat re-configuration sequence until link comes up */
-+ if (state->link == 0)
-+ mtk_usxgmii_pcs_config(pcs, mpcs->mode,
-+ state->interface, NULL, false);
-+}
-+
-+static void mtk_usxgmii_pcs_restart_an(struct phylink_pcs *pcs)
-+{
-+ struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
-+ unsigned int val = 0;
-+
-+ if (!mpcs->regmap)
-+ return;
-+
-+ regmap_read(mpcs->regmap, RG_PCS_AN_CTRL0, &val);
-+ val |= USXGMII_AN_RESTART;
-+ regmap_write(mpcs->regmap, RG_PCS_AN_CTRL0, val);
-+}
-+
-+static void mtk_usxgmii_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
-+ phy_interface_t interface,
-+ int speed, int duplex)
-+{
-+ /* Reconfiguring USXGMII to ensure the quality of the RX signal
-+ * after the line side link up.
-+ */
-+ mtk_usxgmii_pcs_config(pcs, mode,
-+ interface, NULL, false);
-+}
-+
-+static const struct phylink_pcs_ops mtk_usxgmii_pcs_ops = {
-+ .pcs_config = mtk_usxgmii_pcs_config,
-+ .pcs_get_state = mtk_usxgmii_pcs_get_state,
-+ .pcs_an_restart = mtk_usxgmii_pcs_restart_an,
-+ .pcs_link_up = mtk_usxgmii_pcs_link_up,
-+};
-+
-+int mtk_usxgmii_init(struct mtk_eth *eth)
-+{
-+ struct device_node *r = eth->dev->of_node;
-+ struct device *dev = eth->dev;
-+ struct device_node *np;
-+ int i, ret;
-+
-+ for (i = 0; i < MTK_MAX_DEVS; i++) {
-+ np = of_parse_phandle(r, "mediatek,usxgmiisys", i);
-+ if (!np)
-+ break;
-+
-+ eth->usxgmii_pcs[i] = devm_kzalloc(dev, sizeof(*eth->usxgmii_pcs[i]), GFP_KERNEL);
-+ if (!eth->usxgmii_pcs[i])
-+ return -ENOMEM;
-+
-+ eth->usxgmii_pcs[i]->id = i;
-+ eth->usxgmii_pcs[i]->eth = eth;
-+ eth->usxgmii_pcs[i]->regmap = syscon_node_to_regmap(np);
-+ if (IS_ERR(eth->usxgmii_pcs[i]->regmap))
-+ return PTR_ERR(eth->usxgmii_pcs[i]->regmap);
-+
-+ eth->usxgmii_pcs[i]->pcs.ops = &mtk_usxgmii_pcs_ops;
-+ eth->usxgmii_pcs[i]->pcs.poll = true;
-+ eth->usxgmii_pcs[i]->interface = PHY_INTERFACE_MODE_NA;
-+ eth->usxgmii_pcs[i]->mode = -1;
-+
-+ of_node_put(np);
-+ }
-+
-+ ret = mtk_xfi_pextp_init(eth);
-+ if (ret)
-+ return ret;
-+
-+ ret = mtk_xfi_pll_init(eth);
-+ if (ret)
-+ return ret;
-+
-+ ret = mtk_toprgu_init(eth);
-+ if (ret)
-+ return ret;
-+
-+ return mtk_sgmii_wrapper_init(eth);
-+}
-+
-+struct phylink_pcs *mtk_usxgmii_select_pcs(struct mtk_eth *eth, int mac_id)
-+{
-+ u32 xgmii_id = mtk_mac2xgmii_id(eth, mac_id);
-+
-+ if (!eth->usxgmii_pcs[xgmii_id]->regmap)
-+ return NULL;
-+
-+ return ð->usxgmii_pcs[xgmii_id]->pcs;
-+}
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -4885,7 +4885,10 @@ static int mtk_probe(struct platform_dev
+@@ -4963,7 +4963,10 @@ static int mtk_probe(struct platform_dev
}
if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) {
--- /dev/null
+From patchwork Thu Feb 1 21:52:20 2024
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
+X-Patchwork-Id: 13541842
+Date: Thu, 1 Feb 2024 21:52:20 +0000
+From: Daniel Golle <daniel@makrotopia.org>
+To: Bc-bocun Chen <bc-bocun.chen@mediatek.com>,
+ Steven Liu <steven.liu@mediatek.com>,
+ John Crispin <john@phrozen.org>,
+ Chunfeng Yun <chunfeng.yun@mediatek.com>,
+ Vinod Koul <vkoul@kernel.org>,
+ Kishon Vijay Abraham I <kishon@kernel.org>,
+ Rob Herring <robh@kernel.org>,
+ Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
+ Conor Dooley <conor+dt@kernel.org>,
+ Daniel Golle <daniel@makrotopia.org>,
+ Qingfang Deng <dqfext@gmail.com>,
+ SkyLake Huang <SkyLake.Huang@mediatek.com>,
+ Matthias Brugger <matthias.bgg@gmail.com>,
+ AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
+ Philipp Zabel <p.zabel@pengutronix.de>,
+ linux-arm-kernel@lists.infradead.org,
+ linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org,
+ devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
+ netdev@vger.kernel.org
+Subject: [PATCH 1/2] dt-bindings: phy: mediatek,xfi-tphy: add new bindings
+Message-ID:
+ <702afb0c1246d95c90b22e57105304028bdd3083.1706823233.git.daniel@makrotopia.org>
+MIME-Version: 1.0
+Content-Disposition: inline
+List-Id: Linux Phy Mailing list <linux-phy.lists.infradead.org>
+
+Add bindings for the MediaTek XFI T-PHY Ethernet SerDes PHY found in the
+MediaTek MT7988 SoC which can operate at various interfaces modes:
+
+via USXGMII PCS:
+ * USXGMII
+ * 10GBase-R
+ * 5GBase-R
+
+via LynxI SGMII PCS:
+ * 2500Base-X
+ * 1000Base-X
+ * Cisco SGMII (MAC side)
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ .../bindings/phy/mediatek,xfi-tphy.yaml | 80 +++++++++++++++++++
+ 1 file changed, 80 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/phy/mediatek,xfi-tphy.yaml
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/phy/mediatek,xfi-tphy.yaml
+@@ -0,0 +1,80 @@
++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/phy/mediatek,xfi-tphy.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: MediaTek XFI T-PHY
++
++maintainers:
++ - Daniel Golle <daniel@makrotopia.org>
++
++description:
++ The MediaTek XFI SerDes T-PHY provides the physical SerDes lanes
++ used by the (10G/5G) USXGMII PCS and (1G/2.5G) LynxI PCS found in
++ MediaTek's 10G-capabale SoCs.
++
++properties:
++ $nodename:
++ pattern: "^phy@[0-9a-f]+$"
++
++ compatible:
++ const: mediatek,mt7988-xfi-tphy
++
++ reg:
++ maxItems: 1
++
++ clocks:
++ items:
++ - description: XFI PHY clock
++ - description: XFI register clock
++
++ clock-names:
++ items:
++ - const: xfipll
++ - const: topxtal
++
++ resets:
++ items:
++ - description: PEXTP reset
++
++ mediatek,usxgmii-performance-errata:
++ $ref: /schemas/types.yaml#/definitions/flag
++ description:
++ One instance of the T-PHY on MT7988 suffers from a performance
++ problem in 10GBase-R mode which needs a work-around in the driver.
++ The work-around is enabled using this flag.
++
++ "#phy-cells":
++ const: 0
++
++required:
++ - compatible
++ - reg
++ - clocks
++ - clock-names
++ - resets
++ - "#phy-cells"
++
++additionalProperties: false
++
++examples:
++ - |
++ #include <dt-bindings/clock/mediatek,mt7988-clk.h>
++ soc {
++ #address-cells = <2>;
++ #size-cells = <2>;
++
++ phy@11f20000 {
++ compatible = "mediatek,mt7988-xfi-tphy";
++ reg = <0 0x11f20000 0 0x10000>;
++ clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>,
++ <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>;
++ clock-names = "xfipll", "topxtal";
++ resets = <&watchdog 14>;
++ mediatek,usxgmii-performance-errata;
++ #phy-cells = <0>;
++ };
++ };
++
++...
--- /dev/null
+From patchwork Thu Feb 1 21:53:06 2024
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
+X-Patchwork-Id: 13541843
+Date: Thu, 1 Feb 2024 21:53:06 +0000
+From: Daniel Golle <daniel@makrotopia.org>
+To: Bc-bocun Chen <bc-bocun.chen@mediatek.com>,
+ Chunfeng Yun <chunfeng.yun@mediatek.com>,
+ Vinod Koul <vkoul@kernel.org>,
+ Kishon Vijay Abraham I <kishon@kernel.org>,
+ Rob Herring <robh@kernel.org>,
+ Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
+ Conor Dooley <conor+dt@kernel.org>,
+ Daniel Golle <daniel@makrotopia.org>,
+ Qingfang Deng <dqfext@gmail.com>,
+ SkyLake Huang <SkyLake.Huang@mediatek.com>,
+ Matthias Brugger <matthias.bgg@gmail.com>,
+ AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
+ Philipp Zabel <p.zabel@pengutronix.de>,
+ linux-arm-kernel@lists.infradead.org,
+ linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org,
+ devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
+ netdev@vger.kernel.org
+Subject: [PATCH 2/2] phy: add driver for MediaTek XFI T-PHY
+Message-ID:
+ <dd6b40ea1f7f8459a9a2cfe7fa60c1108332ade6.1706823233.git.daniel@makrotopia.org>
+References:
+ <702afb0c1246d95c90b22e57105304028bdd3083.1706823233.git.daniel@makrotopia.org>
+MIME-Version: 1.0
+Content-Disposition: inline
+In-Reply-To:
+ <702afb0c1246d95c90b22e57105304028bdd3083.1706823233.git.daniel@makrotopia.org>
+List-Id: Linux Phy Mailing list <linux-phy.lists.infradead.org>
+
+Add driver for MediaTek's XFI T-PHY, 10 Gigabit/s Ethernet SerDes PHY
+which can be found in the MT7988 SoC.
+
+The PHY can operates only in PHY_MODE_ETHERNET, the submode is one of
+PHY_INTERFACE_MODE_* corresponding to the supported modes:
+
+ * USXGMII \
+ * 10GBase-R }- USXGMII PCS - XGDM \
+ * 5GBase-R / \
+ }- Ethernet MAC
+ * 2500Base-X \ /
+ * 1000Base-X }- LynxI PCS - GDM /
+ * Cisco SGMII (MAC side) /
+
+In order to work-around a performance issue present on the first of
+two XFI T-PHYs present in MT7988, special tuning is applied which can be
+selected by adding the 'mediatek,usxgmii-performance-errata' property to
+the device tree node.
+
+There is no documentation for most registers used for the
+analog/tuning part, however, most of the registers have been partially
+reverse-engineered from MediaTek's SDK implementation (an opaque
+sequence of 32-bit register writes) and descriptions for all relevant
+digital registers and bits such as resets and muxes have been supplied
+by MediaTek.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ MAINTAINERS | 1 +
+ drivers/phy/mediatek/Kconfig | 12 +
+ drivers/phy/mediatek/Makefile | 1 +
+ drivers/phy/mediatek/phy-mtk-xfi-tphy.c | 392 ++++++++++++++++++++++++
+ 4 files changed, 406 insertions(+)
+ create mode 100644 drivers/phy/mediatek/phy-mtk-xfi-tphy.c
+
+--- a/drivers/phy/mediatek/Kconfig
++++ b/drivers/phy/mediatek/Kconfig
+@@ -13,6 +13,18 @@ config PHY_MTK_PCIE
+ callback for PCIe GEN3 port, it supports software efuse
+ initialization.
+
++config PHY_MTK_XFI_TPHY
++ tristate "MediaTek XFI T-PHY Driver"
++ depends on ARCH_MEDIATEK || COMPILE_TEST
++ depends on OF && OF_ADDRESS
++ depends on HAS_IOMEM
++ select GENERIC_PHY
++ help
++ Say 'Y' here to add support for MediaTek XFI T-PHY driver.
++ The driver provides access to the Ethernet SerDes T-PHY supporting
++ 1GE and 2.5GE modes via the LynxI PCS, and 5GE and 10GE modes
++ via the USXGMII PCS found in MediaTek SoCs with 10G Ethernet.
++
+ config PHY_MTK_TPHY
+ tristate "MediaTek T-PHY Driver"
+ depends on ARCH_MEDIATEK || COMPILE_TEST
+--- a/drivers/phy/mediatek/Makefile
++++ b/drivers/phy/mediatek/Makefile
+@@ -8,6 +8,7 @@ obj-$(CONFIG_PHY_MTK_PCIE) += phy-mtk-p
+ obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
+ obj-$(CONFIG_PHY_MTK_UFS) += phy-mtk-ufs.o
+ obj-$(CONFIG_PHY_MTK_XSPHY) += phy-mtk-xsphy.o
++obj-$(CONFIG_PHY_MTK_XFI_TPHY) += phy-mtk-xfi-tphy.o
+
+ phy-mtk-hdmi-drv-y := phy-mtk-hdmi.o
+ phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt2701.o
+--- /dev/null
++++ b/drivers/phy/mediatek/phy-mtk-xfi-tphy.c
+@@ -0,0 +1,392 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++/* MediaTek 10GE SerDes PHY driver
++ *
++ * Copyright (c) 2024 Daniel Golle <daniel@makrotopia.org>
++ * Bc-bocun Chen <bc-bocun.chen@mediatek.com>
++ * based on mtk_usxgmii.c found in MediaTek's SDK released under GPL-2.0
++ * Copyright (c) 2022 MediaTek Inc.
++ * Author: Henry Yen <henry.yen@mediatek.com>
++ */
++
++#include <linux/module.h>
++#include <linux/device.h>
++#include <linux/platform_device.h>
++#include <linux/of.h>
++#include <linux/io.h>
++#include <linux/clk.h>
++#include <linux/reset.h>
++#include <linux/phy.h>
++#include <linux/phy/phy.h>
++
++#define MTK_XFI_TPHY_NUM_CLOCKS 2
++
++#define REG_DIG_GLB_70 0x0070
++#define XTP_PCS_RX_EQ_IN_PROGRESS(x) FIELD_PREP(GENMASK(25, 24), (x))
++#define XTP_PCS_MODE_MASK GENMASK(17, 16)
++#define XTP_PCS_MODE(x) FIELD_PREP(GENMASK(17, 16), (x))
++#define XTP_PCS_RST_B BIT(15)
++#define XTP_FRC_PCS_RST_B BIT(14)
++#define XTP_PCS_PWD_SYNC_MASK GENMASK(13, 12)
++#define XTP_PCS_PWD_SYNC(x) FIELD_PREP(XTP_PCS_PWD_SYNC_MASK, (x))
++#define XTP_PCS_PWD_ASYNC_MASK GENMASK(11, 10)
++#define XTP_PCS_PWD_ASYNC(x) FIELD_PREP(XTP_PCS_PWD_ASYNC_MASK, (x))
++#define XTP_FRC_PCS_PWD_ASYNC BIT(8)
++#define XTP_PCS_UPDT BIT(4)
++#define XTP_PCS_IN_FR_RG BIT(0)
++
++#define REG_DIG_GLB_F4 0x00f4
++#define XFI_DPHY_PCS_SEL BIT(0)
++#define XFI_DPHY_PCS_SEL_SGMII FIELD_PREP(XFI_DPHY_PCS_SEL, 1)
++#define XFI_DPHY_PCS_SEL_USXGMII FIELD_PREP(XFI_DPHY_PCS_SEL, 0)
++#define XFI_DPHY_AD_SGDT_FRC_EN BIT(5)
++
++#define REG_DIG_LN_TRX_40 0x3040
++#define XTP_LN_FRC_TX_DATA_EN BIT(29)
++#define XTP_LN_TX_DATA_EN BIT(28)
++
++#define REG_DIG_LN_TRX_B0 0x30b0
++#define XTP_LN_FRC_TX_MACCK_EN BIT(5)
++#define XTP_LN_TX_MACCK_EN BIT(4)
++
++#define REG_ANA_GLB_D0 0x90d0
++#define XTP_GLB_USXGMII_SEL_MASK GENMASK(3, 1)
++#define XTP_GLB_USXGMII_SEL(x) FIELD_PREP(GENMASK(3, 1), (x))
++#define XTP_GLB_USXGMII_EN BIT(0)
++
++struct mtk_xfi_tphy {
++ void __iomem *base;
++ struct device *dev;
++ struct reset_control *reset;
++ struct clk_bulk_data clocks[MTK_XFI_TPHY_NUM_CLOCKS];
++ bool da_war;
++};
++
++static void mtk_xfi_tphy_write(struct mtk_xfi_tphy *xfi_tphy, u16 reg,
++ u32 value)
++{
++ iowrite32(value, xfi_tphy->base + reg);
++}
++
++static void mtk_xfi_tphy_rmw(struct mtk_xfi_tphy *xfi_tphy, u16 reg,
++ u32 clr, u32 set)
++{
++ u32 val;
++
++ val = ioread32(xfi_tphy->base + reg);
++ val &= ~clr;
++ val |= set;
++ iowrite32(val, xfi_tphy->base + reg);
++}
++
++static void mtk_xfi_tphy_set(struct mtk_xfi_tphy *xfi_tphy, u16 reg,
++ u32 set)
++{
++ mtk_xfi_tphy_rmw(xfi_tphy, reg, 0, set);
++}
++
++static void mtk_xfi_tphy_clear(struct mtk_xfi_tphy *xfi_tphy, u16 reg,
++ u32 clr)
++{
++ mtk_xfi_tphy_rmw(xfi_tphy, reg, clr, 0);
++}
++
++static void mtk_xfi_tphy_setup(struct mtk_xfi_tphy *xfi_tphy,
++ phy_interface_t interface)
++{
++ bool is_2p5g = (interface == PHY_INTERFACE_MODE_2500BASEX);
++ bool is_1g = (interface == PHY_INTERFACE_MODE_1000BASEX ||
++ interface == PHY_INTERFACE_MODE_SGMII);
++ bool is_10g = (interface == PHY_INTERFACE_MODE_10GBASER ||
++ interface == PHY_INTERFACE_MODE_USXGMII);
++ bool is_5g = (interface == PHY_INTERFACE_MODE_5GBASER);
++ bool is_xgmii = (is_10g || is_5g);
++
++ dev_dbg(xfi_tphy->dev, "setting up for mode %s\n", phy_modes(interface));
++
++ /* Setup PLL setting */
++ mtk_xfi_tphy_rmw(xfi_tphy, 0x9024, 0x100000, is_10g ? 0x0 : 0x100000);
++ mtk_xfi_tphy_rmw(xfi_tphy, 0x2020, 0x202000, is_5g ? 0x202000 : 0x0);
++ mtk_xfi_tphy_rmw(xfi_tphy, 0x2030, 0x500, is_1g ? 0x0 : 0x500);
++ mtk_xfi_tphy_rmw(xfi_tphy, 0x2034, 0xa00, is_1g ? 0x0 : 0xa00);
++ mtk_xfi_tphy_rmw(xfi_tphy, 0x2040, 0x340000, is_1g ? 0x200000 :
++ 0x140000);
++
++ /* Setup RXFE BW setting */
++ mtk_xfi_tphy_rmw(xfi_tphy, 0x50f0, 0xc10, is_1g ? 0x410 :
++ is_5g ? 0x800 : 0x400);
++ mtk_xfi_tphy_rmw(xfi_tphy, 0x50e0, 0x4000, is_5g ? 0x0 : 0x4000);
++
++ /* Setup RX CDR setting */
++ mtk_xfi_tphy_rmw(xfi_tphy, 0x506c, 0x30000, is_5g ? 0x0 : 0x30000);
++ mtk_xfi_tphy_rmw(xfi_tphy, 0x5070, 0x670000, is_5g ? 0x620000 : 0x50000);
++ mtk_xfi_tphy_rmw(xfi_tphy, 0x5074, 0x180000, is_5g ? 0x180000 : 0x0);
++ mtk_xfi_tphy_rmw(xfi_tphy, 0x5078, 0xf000400, is_5g ? 0x8000000 :
++ 0x7000400);
++ mtk_xfi_tphy_rmw(xfi_tphy, 0x507c, 0x5000500, is_5g ? 0x4000400 :
++ 0x1000100);
++ mtk_xfi_tphy_rmw(xfi_tphy, 0x5080, 0x1410, is_1g ? 0x400 :
++ is_5g ? 0x1010 : 0x0);
++ mtk_xfi_tphy_rmw(xfi_tphy, 0x5084, 0x30300, is_1g ? 0x30300 :
++ is_5g ? 0x30100 :
++ 0x100);
++ mtk_xfi_tphy_rmw(xfi_tphy, 0x5088, 0x60200, is_1g ? 0x20200 :
++ is_5g ? 0x40000 :
++ 0x20000);
++
++ /* Setting RXFE adaptation range setting */
++ mtk_xfi_tphy_rmw(xfi_tphy, 0x50e4, 0xc0000, is_5g ? 0x0 : 0xc0000);
++ mtk_xfi_tphy_rmw(xfi_tphy, 0x50e8, 0x40000, is_5g ? 0x0 : 0x40000);
++ mtk_xfi_tphy_rmw(xfi_tphy, 0x50ec, 0xa00, is_1g ? 0x200 : 0x800);
++ mtk_xfi_tphy_rmw(xfi_tphy, 0x50a8, 0xee0000, is_5g ? 0x800000 :
++ 0x6e0000);
++ mtk_xfi_tphy_rmw(xfi_tphy, 0x6004, 0x190000, is_5g ? 0x0 : 0x190000);
++ if (is_10g)
++ mtk_xfi_tphy_write(xfi_tphy, 0x00f8, 0x01423342);
++ else if (is_5g)
++ mtk_xfi_tphy_write(xfi_tphy, 0x00f8, 0x00a132a1);
++ else if (is_2p5g)
++ mtk_xfi_tphy_write(xfi_tphy, 0x00f8, 0x009c329c);
++ else
++ mtk_xfi_tphy_write(xfi_tphy, 0x00f8, 0x00fa32fa);
++
++ /* Force SGDT_OUT off and select PCS */
++ mtk_xfi_tphy_rmw(xfi_tphy, REG_DIG_GLB_F4,
++ XFI_DPHY_AD_SGDT_FRC_EN | XFI_DPHY_PCS_SEL,
++ XFI_DPHY_AD_SGDT_FRC_EN |
++ (is_xgmii ? XFI_DPHY_PCS_SEL_USXGMII :
++ XFI_DPHY_PCS_SEL_SGMII));
++
++
++ /* Force GLB_CKDET_OUT */
++ mtk_xfi_tphy_set(xfi_tphy, 0x0030, 0xc00);
++
++ /* Force AEQ on */
++ mtk_xfi_tphy_write(xfi_tphy, REG_DIG_GLB_70,
++ XTP_PCS_RX_EQ_IN_PROGRESS(2) |
++ XTP_PCS_PWD_SYNC(2) |
++ XTP_PCS_PWD_ASYNC(2));
++
++ usleep_range(1, 5);
++
++ /* Setup TX DA default value */
++ mtk_xfi_tphy_rmw(xfi_tphy, 0x30b0, 0x30, 0x20);
++ mtk_xfi_tphy_write(xfi_tphy, 0x3028, 0x00008a01);
++ mtk_xfi_tphy_write(xfi_tphy, 0x302c, 0x0000a884);
++ mtk_xfi_tphy_write(xfi_tphy, 0x3024, 0x00083002);
++
++ /* Setup RG default value */
++ if (is_xgmii) {
++ mtk_xfi_tphy_write(xfi_tphy, 0x3010, 0x00022220);
++ mtk_xfi_tphy_write(xfi_tphy, 0x5064, 0x0f020a01);
++ mtk_xfi_tphy_write(xfi_tphy, 0x50b4, 0x06100600);
++ if (interface == PHY_INTERFACE_MODE_USXGMII)
++ mtk_xfi_tphy_write(xfi_tphy, 0x3048, 0x40704000);
++ else
++ mtk_xfi_tphy_write(xfi_tphy, 0x3048, 0x47684100);
++ } else {
++ mtk_xfi_tphy_write(xfi_tphy, 0x3010, 0x00011110);
++ mtk_xfi_tphy_write(xfi_tphy, 0x3048, 0x40704000);
++ }
++
++ if (is_1g)
++ mtk_xfi_tphy_write(xfi_tphy, 0x3064, 0x0000c000);
++
++ /* Setup RX EQ initial value */
++ mtk_xfi_tphy_rmw(xfi_tphy, 0x3050, 0xa8000000,
++ (interface != PHY_INTERFACE_MODE_10GBASER) ?
++ 0xa8000000 : 0x0);
++ mtk_xfi_tphy_rmw(xfi_tphy, 0x3054, 0xaa,
++ (interface != PHY_INTERFACE_MODE_10GBASER) ?
++ 0xaa : 0x0);
++
++ if (is_xgmii)
++ mtk_xfi_tphy_write(xfi_tphy, 0x306c, 0x00000f00);
++ else if (is_2p5g)
++ mtk_xfi_tphy_write(xfi_tphy, 0x306c, 0x22000f00);
++ else
++ mtk_xfi_tphy_write(xfi_tphy, 0x306c, 0x20200f00);
++
++ if (interface == PHY_INTERFACE_MODE_10GBASER && xfi_tphy->da_war)
++ mtk_xfi_tphy_rmw(xfi_tphy, 0xa008, 0x10000, 0x10000);
++
++ mtk_xfi_tphy_rmw(xfi_tphy, 0xa060, 0x50000, is_xgmii ? 0x40000 :
++ 0x50000);
++
++ /* Setup PHYA speed */
++ mtk_xfi_tphy_rmw(xfi_tphy, REG_ANA_GLB_D0,
++ XTP_GLB_USXGMII_SEL_MASK | XTP_GLB_USXGMII_EN,
++ is_10g ? XTP_GLB_USXGMII_SEL(0) :
++ is_5g ? XTP_GLB_USXGMII_SEL(1) :
++ is_2p5g ? XTP_GLB_USXGMII_SEL(2) :
++ XTP_GLB_USXGMII_SEL(3));
++ mtk_xfi_tphy_set(xfi_tphy, REG_ANA_GLB_D0, XTP_GLB_USXGMII_EN);
++
++ /* Release reset */
++ mtk_xfi_tphy_set(xfi_tphy, REG_DIG_GLB_70,
++ XTP_PCS_RST_B | XTP_FRC_PCS_RST_B);
++ usleep_range(150, 500);
++
++ /* Switch to P0 */
++ mtk_xfi_tphy_rmw(xfi_tphy, REG_DIG_GLB_70,
++ XTP_PCS_PWD_SYNC_MASK |
++ XTP_PCS_PWD_ASYNC_MASK,
++ XTP_FRC_PCS_PWD_ASYNC |
++ XTP_PCS_UPDT | XTP_PCS_IN_FR_RG);
++ usleep_range(1, 5);
++
++ mtk_xfi_tphy_clear(xfi_tphy, REG_DIG_GLB_70, XTP_PCS_UPDT);
++ usleep_range(15, 50);
++
++ if (is_xgmii) {
++ /* Switch to Gen3 */
++ mtk_xfi_tphy_rmw(xfi_tphy, REG_DIG_GLB_70,
++ XTP_PCS_MODE_MASK | XTP_PCS_UPDT,
++ XTP_PCS_MODE(2) | XTP_PCS_UPDT);
++ } else {
++ /* Switch to Gen2 */
++ mtk_xfi_tphy_rmw(xfi_tphy, REG_DIG_GLB_70,
++ XTP_PCS_MODE_MASK | XTP_PCS_UPDT,
++ XTP_PCS_MODE(1) | XTP_PCS_UPDT);
++ }
++ usleep_range(1, 5);
++
++ mtk_xfi_tphy_clear(xfi_tphy, REG_DIG_GLB_70, XTP_PCS_UPDT);
++
++ usleep_range(100, 500);
++
++ /* Enable MAC CK */
++ mtk_xfi_tphy_set(xfi_tphy, REG_DIG_LN_TRX_B0, XTP_LN_TX_MACCK_EN);
++ mtk_xfi_tphy_clear(xfi_tphy, REG_DIG_GLB_F4, XFI_DPHY_AD_SGDT_FRC_EN);
++
++ /* Enable TX data */
++ mtk_xfi_tphy_set(xfi_tphy, REG_DIG_LN_TRX_40,
++ XTP_LN_FRC_TX_DATA_EN | XTP_LN_TX_DATA_EN);
++ usleep_range(400, 1000);
++}
++
++static int mtk_xfi_tphy_set_mode(struct phy *phy, enum phy_mode mode, int
++ submode)
++{
++ struct mtk_xfi_tphy *xfi_tphy = phy_get_drvdata(phy);
++
++ if (mode != PHY_MODE_ETHERNET)
++ return -EINVAL;
++
++ switch (submode) {
++ case PHY_INTERFACE_MODE_1000BASEX:
++ case PHY_INTERFACE_MODE_2500BASEX:
++ case PHY_INTERFACE_MODE_SGMII:
++ case PHY_INTERFACE_MODE_5GBASER:
++ case PHY_INTERFACE_MODE_10GBASER:
++ case PHY_INTERFACE_MODE_USXGMII:
++ mtk_xfi_tphy_setup(xfi_tphy, submode);
++ return 0;
++ default:
++ return -EINVAL;
++ }
++}
++
++static int mtk_xfi_tphy_reset(struct phy *phy)
++{
++ struct mtk_xfi_tphy *xfi_tphy = phy_get_drvdata(phy);
++
++ reset_control_assert(xfi_tphy->reset);
++ usleep_range(100, 500);
++ reset_control_deassert(xfi_tphy->reset);
++ usleep_range(1, 10);
++
++ return 0;
++}
++
++static int mtk_xfi_tphy_power_on(struct phy *phy)
++{
++ struct mtk_xfi_tphy *xfi_tphy = phy_get_drvdata(phy);
++
++ return clk_bulk_prepare_enable(MTK_XFI_TPHY_NUM_CLOCKS, xfi_tphy->clocks);
++}
++
++static int mtk_xfi_tphy_power_off(struct phy *phy)
++{
++ struct mtk_xfi_tphy *xfi_tphy = phy_get_drvdata(phy);
++
++ clk_bulk_disable_unprepare(MTK_XFI_TPHY_NUM_CLOCKS, xfi_tphy->clocks);
++
++ return 0;
++}
++
++static const struct phy_ops mtk_xfi_tphy_ops = {
++ .power_on = mtk_xfi_tphy_power_on,
++ .power_off = mtk_xfi_tphy_power_off,
++ .set_mode = mtk_xfi_tphy_set_mode,
++ .reset = mtk_xfi_tphy_reset,
++ .owner = THIS_MODULE,
++};
++
++static int mtk_xfi_tphy_probe(struct platform_device *pdev)
++{
++ struct device_node *np = pdev->dev.of_node;
++ struct phy_provider *phy_provider;
++ struct mtk_xfi_tphy *xfi_tphy;
++ struct phy *phy;
++
++ if (!np)
++ return -ENODEV;
++
++ xfi_tphy = devm_kzalloc(&pdev->dev, sizeof(*xfi_tphy), GFP_KERNEL);
++ if (!xfi_tphy)
++ return -ENOMEM;
++
++ xfi_tphy->base = devm_of_iomap(&pdev->dev, np, 0, NULL);
++ if (!xfi_tphy->base)
++ return -EIO;
++
++ xfi_tphy->dev = &pdev->dev;
++
++ xfi_tphy->clocks[0].id = "topxtal";
++ xfi_tphy->clocks[0].clk = devm_clk_get(&pdev->dev, xfi_tphy->clocks[0].id);
++ if (IS_ERR(xfi_tphy->clocks[0].clk))
++ return PTR_ERR(xfi_tphy->clocks[0].clk);
++
++ xfi_tphy->clocks[1].id = "xfipll";
++ xfi_tphy->clocks[1].clk = devm_clk_get(&pdev->dev, xfi_tphy->clocks[1].id);
++ if (IS_ERR(xfi_tphy->clocks[1].clk))
++ return PTR_ERR(xfi_tphy->clocks[1].clk);
++
++ xfi_tphy->reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);
++ if (IS_ERR(xfi_tphy->reset))
++ return PTR_ERR(xfi_tphy->reset);
++
++ xfi_tphy->da_war = of_property_read_bool(np,
++ "mediatek,usxgmii-performance-errata");
++
++ phy = devm_phy_create(&pdev->dev, NULL, &mtk_xfi_tphy_ops);
++ if (IS_ERR(phy))
++ return PTR_ERR(phy);
++
++ phy_set_drvdata(phy, xfi_tphy);
++
++ phy_provider = devm_of_phy_provider_register(&pdev->dev,
++ of_phy_simple_xlate);
++
++ return PTR_ERR_OR_ZERO(phy_provider);
++}
++
++static const struct of_device_id mtk_xfi_tphy_match[] = {
++ { .compatible = "mediatek,mt7988-xfi-tphy", },
++ { }
++};
++MODULE_DEVICE_TABLE(of, mtk_xfi_tphy_match);
++
++static struct platform_driver mtk_xfi_tphy_driver = {
++ .probe = mtk_xfi_tphy_probe,
++ .driver = {
++ .name = "mtk-xfi-tphy",
++ .of_match_table = mtk_xfi_tphy_match,
++ },
++};
++module_platform_driver(mtk_xfi_tphy_driver);
++
++MODULE_DESCRIPTION("MediaTek XFI T-PHY driver");
++MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
++MODULE_AUTHOR("Bc-bocun Chen <bc-bocun.chen@mediatek.com>");
++MODULE_LICENSE("GPL");
--- /dev/null
+From 4b1a2716299c0e96a698044aebf3f80513509ae7 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Tue, 12 Dec 2023 03:47:18 +0000
+Subject: [PATCH 3/5] net: pcs: pcs-mtk-lynxi: add platform driver for MT7988
+
+Introduce a proper platform MFD driver for the LynxI (H)SGMII PCS which
+is going to initially be used for the MT7988 SoC.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/net/pcs/pcs-mtk-lynxi.c | 227 ++++++++++++++++++++++++++++--
+ include/linux/pcs/pcs-mtk-lynxi.h | 11 ++
+ 2 files changed, 227 insertions(+), 11 deletions(-)
+
+--- a/drivers/net/pcs/pcs-mtk-lynxi.c
++++ b/drivers/net/pcs/pcs-mtk-lynxi.c
+@@ -1,6 +1,6 @@
+ // SPDX-License-Identifier: GPL-2.0
+ // Copyright (c) 2018-2019 MediaTek Inc.
+-/* A library for MediaTek SGMII circuit
++/* A library and platform driver for the MediaTek LynxI SGMII circuit
+ *
+ * Author: Sean Wang <sean.wang@mediatek.com>
+ * Author: Alexander Couzens <lynxis@fe80.eu>
+@@ -8,11 +8,17 @@
+ *
+ */
+
++#include <linux/clk.h>
+ #include <linux/mdio.h>
++#include <linux/mfd/syscon.h>
++#include <linux/mutex.h>
+ #include <linux/of.h>
++#include <linux/of_platform.h>
+ #include <linux/pcs/pcs-mtk-lynxi.h>
+ #include <linux/phylink.h>
++#include <linux/platform_device.h>
+ #include <linux/regmap.h>
++#include <linux/reset.h>
+
+ /* SGMII subsystem config registers */
+ /* BMCR (low 16) BMSR (high 16) */
+@@ -65,6 +71,8 @@
+ #define SGMII_PN_SWAP_MASK GENMASK(1, 0)
+ #define SGMII_PN_SWAP_TX_RX (BIT(0) | BIT(1))
+
++#define MTK_NETSYS_V3_AMA_RGC3 0x128
++
+ /* struct mtk_pcs_lynxi - This structure holds each sgmii regmap andassociated
+ * data
+ * @regmap: The register map pointing at the range used to setup
+@@ -74,15 +82,29 @@
+ * @interface: Currently configured interface mode
+ * @pcs: Phylink PCS structure
+ * @flags: Flags indicating hardware properties
++ * @rstc: Reset controller
++ * @sgmii_sel: SGMII Register Clock
++ * @sgmii_rx: SGMII RX Clock
++ * @sgmii_tx: SGMII TX Clock
++ * @node: List node
+ */
+ struct mtk_pcs_lynxi {
+ struct regmap *regmap;
++ struct device *dev;
+ u32 ana_rgc3;
+ phy_interface_t interface;
+ struct phylink_pcs pcs;
+ u32 flags;
++ struct reset_control *rstc;
++ struct clk *sgmii_sel;
++ struct clk *sgmii_rx;
++ struct clk *sgmii_tx;
++ struct list_head node;
+ };
+
++static LIST_HEAD(mtk_pcs_lynxi_instances);
++static DEFINE_MUTEX(instance_mutex);
++
+ static struct mtk_pcs_lynxi *pcs_to_mtk_pcs_lynxi(struct phylink_pcs *pcs)
+ {
+ return container_of(pcs, struct mtk_pcs_lynxi, pcs);
+@@ -102,6 +124,17 @@ static void mtk_pcs_lynxi_get_state(stru
+ FIELD_GET(SGMII_LPA, adv));
+ }
+
++static void mtk_sgmii_reset(struct mtk_pcs_lynxi *mpcs)
++{
++ if (!mpcs->rstc)
++ return;
++
++ reset_control_assert(mpcs->rstc);
++ udelay(100);
++ reset_control_deassert(mpcs->rstc);
++ mdelay(1);
++}
++
+ static int mtk_pcs_lynxi_config(struct phylink_pcs *pcs, unsigned int neg_mode,
+ phy_interface_t interface,
+ const unsigned long *advertising,
+@@ -148,6 +181,7 @@ static int mtk_pcs_lynxi_config(struct p
+ SGMII_PHYA_PWD);
+
+ /* Reset SGMII PCS state */
++ mtk_sgmii_reset(mpcs);
+ regmap_set_bits(mpcs->regmap, SGMSYS_RESERVED_0,
+ SGMII_SW_RESET);
+
+@@ -234,10 +268,29 @@ static void mtk_pcs_lynxi_link_up(struct
+ }
+ }
+
++static int mtk_pcs_lynxi_enable(struct phylink_pcs *pcs)
++{
++ struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs);
++
++ if (mpcs->sgmii_tx && mpcs->sgmii_rx) {
++ clk_prepare_enable(mpcs->sgmii_rx);
++ clk_prepare_enable(mpcs->sgmii_tx);
++ }
++
++ return 0;
++}
++
+ static void mtk_pcs_lynxi_disable(struct phylink_pcs *pcs)
+ {
+ struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs);
+
++ regmap_set_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD);
++
++ if (mpcs->sgmii_tx && mpcs->sgmii_rx) {
++ clk_disable_unprepare(mpcs->sgmii_tx);
++ clk_disable_unprepare(mpcs->sgmii_rx);
++ }
++
+ mpcs->interface = PHY_INTERFACE_MODE_NA;
+ }
+
+@@ -247,11 +300,12 @@ static const struct phylink_pcs_ops mtk_
+ .pcs_an_restart = mtk_pcs_lynxi_restart_an,
+ .pcs_link_up = mtk_pcs_lynxi_link_up,
+ .pcs_disable = mtk_pcs_lynxi_disable,
++ .pcs_enable = mtk_pcs_lynxi_enable,
+ };
+
+-struct phylink_pcs *mtk_pcs_lynxi_create(struct device *dev,
+- struct regmap *regmap, u32 ana_rgc3,
+- u32 flags)
++static struct phylink_pcs *mtk_pcs_lynxi_init(struct device *dev, struct regmap *regmap,
++ u32 ana_rgc3, u32 flags,
++ struct mtk_pcs_lynxi *prealloc)
+ {
+ struct mtk_pcs_lynxi *mpcs;
+ u32 id, ver;
+@@ -259,29 +313,33 @@ struct phylink_pcs *mtk_pcs_lynxi_create
+
+ ret = regmap_read(regmap, SGMSYS_PCS_DEVICE_ID, &id);
+ if (ret < 0)
+- return NULL;
++ return ERR_PTR(ret);
+
+ if (id != SGMII_LYNXI_DEV_ID) {
+ dev_err(dev, "unknown PCS device id %08x\n", id);
+- return NULL;
++ return ERR_PTR(-ENODEV);
+ }
+
+ ret = regmap_read(regmap, SGMSYS_PCS_SCRATCH, &ver);
+ if (ret < 0)
+- return NULL;
++ return ERR_PTR(ret);
+
+ ver = FIELD_GET(SGMII_DEV_VERSION, ver);
+ if (ver != 0x1) {
+ dev_err(dev, "unknown PCS device version %04x\n", ver);
+- return NULL;
++ return ERR_PTR(-ENODEV);
+ }
+
+ dev_dbg(dev, "MediaTek LynxI SGMII PCS (id 0x%08x, ver 0x%04x)\n", id,
+ ver);
+
+- mpcs = kzalloc(sizeof(*mpcs), GFP_KERNEL);
+- if (!mpcs)
+- return NULL;
++ if (prealloc) {
++ mpcs = prealloc;
++ } else {
++ mpcs = kzalloc(sizeof(*mpcs), GFP_KERNEL);
++ if (!mpcs)
++ return ERR_PTR(-ENOMEM);
++ };
+
+ mpcs->ana_rgc3 = ana_rgc3;
+ mpcs->regmap = regmap;
+@@ -292,6 +350,13 @@ struct phylink_pcs *mtk_pcs_lynxi_create
+ mpcs->interface = PHY_INTERFACE_MODE_NA;
+
+ return &mpcs->pcs;
++};
++
++struct phylink_pcs *mtk_pcs_lynxi_create(struct device *dev,
++ struct regmap *regmap, u32 ana_rgc3,
++ u32 flags)
++{
++ return mtk_pcs_lynxi_init(dev, regmap, ana_rgc3, flags, NULL);
+ }
+ EXPORT_SYMBOL(mtk_pcs_lynxi_create);
+
+@@ -304,4 +369,144 @@ void mtk_pcs_lynxi_destroy(struct phylin
+ }
+ EXPORT_SYMBOL(mtk_pcs_lynxi_destroy);
+
++static int mtk_pcs_lynxi_probe(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ struct device_node *np = dev->of_node;
++ struct mtk_pcs_lynxi *mpcs;
++ struct phylink_pcs *pcs;
++ struct regmap *regmap;
++ u32 flags = 0;
++
++ mpcs = devm_kzalloc(dev, sizeof(*mpcs), GFP_KERNEL);
++ if (!mpcs)
++ return -ENOMEM;
++
++ mpcs->dev = dev;
++ regmap = syscon_node_to_regmap(np->parent);
++ if (IS_ERR(regmap))
++ return PTR_ERR(regmap);
++
++ if (of_property_read_bool(np->parent, "mediatek,pnswap"))
++ flags |= MTK_SGMII_FLAG_PN_SWAP;
++
++ mpcs->rstc = of_reset_control_get_shared(np->parent, NULL);
++ if (IS_ERR(mpcs->rstc))
++ return PTR_ERR(mpcs->rstc);
++
++ reset_control_deassert(mpcs->rstc);
++ mpcs->sgmii_sel = devm_clk_get_enabled(dev, "sgmii_sel");
++ if (IS_ERR(mpcs->sgmii_sel))
++ return PTR_ERR(mpcs->sgmii_sel);
++
++ mpcs->sgmii_rx = devm_clk_get(dev, "sgmii_rx");
++ if (IS_ERR(mpcs->sgmii_rx))
++ return PTR_ERR(mpcs->sgmii_rx);
++
++ mpcs->sgmii_tx = devm_clk_get(dev, "sgmii_tx");
++ if (IS_ERR(mpcs->sgmii_tx))
++ return PTR_ERR(mpcs->sgmii_tx);
++
++ pcs = mtk_pcs_lynxi_init(dev, regmap, (uintptr_t)of_device_get_match_data(dev),
++ flags, mpcs);
++ if (IS_ERR(pcs))
++ return PTR_ERR(pcs);
++
++ regmap_set_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD);
++
++ platform_set_drvdata(pdev, mpcs);
++
++ mutex_lock(&instance_mutex);
++ list_add_tail(&mpcs->node, &mtk_pcs_lynxi_instances);
++ mutex_unlock(&instance_mutex);
++
++ return 0;
++}
++
++static int mtk_pcs_lynxi_remove(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ struct mtk_pcs_lynxi *cur, *tmp;
++
++ mutex_lock(&instance_mutex);
++ list_for_each_entry_safe(cur, tmp, &mtk_pcs_lynxi_instances, node)
++ if (cur->dev == dev) {
++ list_del(&cur->node);
++ kfree(cur);
++ break;
++ }
++ mutex_unlock(&instance_mutex);
++
++ return 0;
++}
++
++static const struct of_device_id mtk_pcs_lynxi_of_match[] = {
++ { .compatible = "mediatek,mt7988-sgmii", .data = (void *)MTK_NETSYS_V3_AMA_RGC3 },
++ { /* sentinel */ },
++};
++MODULE_DEVICE_TABLE(of, mtk_pcs_lynxi_of_match);
++
++struct phylink_pcs *mtk_pcs_lynxi_get(struct device *dev, struct device_node *np)
++{
++ struct platform_device *pdev;
++ struct mtk_pcs_lynxi *mpcs;
++
++ if (!np)
++ return NULL;
++
++ if (!of_device_is_available(np))
++ return ERR_PTR(-ENODEV);
++
++ if (!of_match_node(mtk_pcs_lynxi_of_match, np))
++ return ERR_PTR(-EINVAL);
++
++ pdev = of_find_device_by_node(np);
++ if (!pdev || !platform_get_drvdata(pdev)) {
++ if (pdev)
++ put_device(&pdev->dev);
++ return ERR_PTR(-EPROBE_DEFER);
++ }
++
++ mpcs = platform_get_drvdata(pdev);
++ device_link_add(dev, mpcs->dev, DL_FLAG_AUTOREMOVE_CONSUMER);
++
++ return &mpcs->pcs;
++}
++EXPORT_SYMBOL(mtk_pcs_lynxi_get);
++
++void mtk_pcs_lynxi_put(struct phylink_pcs *pcs)
++{
++ struct mtk_pcs_lynxi *cur, *mpcs = NULL;
++
++ if (!pcs)
++ return;
++
++ mutex_lock(&instance_mutex);
++ list_for_each_entry(cur, &mtk_pcs_lynxi_instances, node)
++ if (pcs == &cur->pcs) {
++ mpcs = cur;
++ break;
++ }
++ mutex_unlock(&instance_mutex);
++
++ if (WARN_ON(!mpcs))
++ return;
++
++ put_device(mpcs->dev);
++}
++EXPORT_SYMBOL(mtk_pcs_lynxi_put);
++
++static struct platform_driver mtk_pcs_lynxi_driver = {
++ .driver = {
++ .name = "mtk-pcs-lynxi",
++ .suppress_bind_attrs = true,
++ .of_match_table = mtk_pcs_lynxi_of_match,
++ },
++ .probe = mtk_pcs_lynxi_probe,
++ .remove = mtk_pcs_lynxi_remove,
++};
++module_platform_driver(mtk_pcs_lynxi_driver);
++
++MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
++MODULE_DESCRIPTION("MediaTek LynxI HSGMII PCS");
+ MODULE_LICENSE("GPL");
+--- a/include/linux/pcs/pcs-mtk-lynxi.h
++++ b/include/linux/pcs/pcs-mtk-lynxi.h
+@@ -10,4 +10,15 @@ struct phylink_pcs *mtk_pcs_lynxi_create
+ struct regmap *regmap,
+ u32 ana_rgc3, u32 flags);
+ void mtk_pcs_lynxi_destroy(struct phylink_pcs *pcs);
++
++#if IS_ENABLED(CONFIG_PCS_MTK_LYNXI)
++struct phylink_pcs *mtk_pcs_lynxi_get(struct device *dev, struct device_node *np);
++void mtk_pcs_lynxi_put(struct phylink_pcs *pcs);
++#else
++static inline struct phylink_pcs *mtk_pcs_lynxi_get(struct device *dev, struct device_node *np)
++{
++ return NULL;
++}
++static inline void mtk_pcs_lynxi_put(struct phylink_pcs *pcs) { }
++#endif /* IS_ENABLED(CONFIG_PCS_MTK_LYNXI) */
+ #endif
--- /dev/null
+From 7d88d79c0f65b27a92754d7547f7af098b3de67b Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Tue, 12 Dec 2023 03:47:31 +0000
+Subject: [PATCH 4/5] dt-bindings: net: pcs: add bindings for MediaTek USXGMII
+ PCS
+
+MediaTek's USXGMII can be found in the MT7988 SoC. We need to access
+it in order to configure and monitor the Ethernet SerDes link in
+USXGMII, 10GBase-R and 5GBase-R mode. By including a wrapped
+legacy 1000Base-X/2500Base-X/Cisco SGMII LynxI PCS as well, those
+interface modes are also available.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ .../bindings/net/pcs/mediatek,usxgmii.yaml | 60 +++++++++++++++++++
+ 1 file changed, 60 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml
+@@ -0,0 +1,60 @@
++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/net/pcs/mediatek,usxgmii.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: MediaTek USXGMII PCS
++
++maintainers:
++ - Daniel Golle <daniel@makrotopia.org>
++
++description:
++ The MediaTek USXGMII PCS provides physical link control and status
++ for USXGMII, 10GBase-R and 5GBase-R links on the SerDes interfaces
++ provided by the PEXTP PHY.
++ In order to also support legacy 2500Base-X, 1000Base-X and Cisco
++ SGMII an existing mediatek,*-sgmiisys LynxI PCS is wrapped to
++ provide those interfaces modes on the same SerDes interfaces shared
++ with the USXGMII PCS.
++
++properties:
++ $nodename:
++ pattern: "^pcs@[0-9a-f]+$"
++
++ compatible:
++ const: mediatek,mt7988-usxgmiisys
++
++ reg:
++ maxItems: 1
++
++ clocks:
++ items:
++ - description: USXGMII top-level clock
++
++ resets:
++ items:
++ - description: XFI reset
++
++required:
++ - compatible
++ - reg
++ - clocks
++ - resets
++
++additionalProperties: false
++
++examples:
++ - |
++ #include <dt-bindings/clock/mediatek,mt7988-clk.h>
++ #define MT7988_TOPRGU_XFI0_GRST 12
++ soc {
++ #address-cells = <2>;
++ #size-cells = <2>;
++ usxgmiisys0: pcs@10080000 {
++ compatible = "mediatek,mt7988-usxgmiisys";
++ reg = <0 0x10080000 0 0x1000>;
++ clocks = <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>;
++ resets = <&watchdog MT7988_TOPRGU_XFI0_GRST>;
++ };
++ };
--- /dev/null
+From dde0e95fff92e9f5009f3bea75278e0e34a48822 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Tue, 12 Dec 2023 03:47:47 +0000
+Subject: [PATCH 5/5] net: pcs: add driver for MediaTek USXGMII PCS
+
+Add driver for USXGMII PCS found in the MediaTek MT7988 SoC and supporting
+USXGMII, 10GBase-R and 5GBase-R interface modes.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ MAINTAINERS | 2 +
+ drivers/net/pcs/Kconfig | 11 +
+ drivers/net/pcs/Makefile | 1 +
+ drivers/net/pcs/pcs-mtk-usxgmii.c | 456 ++++++++++++++++++++++++++++
+ include/linux/pcs/pcs-mtk-usxgmii.h | 27 ++
+ 5 files changed, 497 insertions(+)
+ create mode 100644 drivers/net/pcs/pcs-mtk-usxgmii.c
+ create mode 100644 include/linux/pcs/pcs-mtk-usxgmii.h
+
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -12934,7 +12934,9 @@ M: Daniel Golle <daniel@makrotopia.org>
+ L: netdev@vger.kernel.org
+ S: Maintained
+ F: drivers/net/pcs/pcs-mtk-lynxi.c
++F: drivers/net/pcs/pcs-mtk-usxgmii.c
+ F: include/linux/pcs/pcs-mtk-lynxi.h
++F: include/linux/pcs/pcs-mtk-usxgmii.h
+
+ MEDIATEK I2C CONTROLLER DRIVER
+ M: Qii Wang <qii.wang@mediatek.com>
+--- a/drivers/net/pcs/Kconfig
++++ b/drivers/net/pcs/Kconfig
+@@ -18,6 +18,17 @@ config PCS_LYNX
+ This module provides helpers to phylink for managing the Lynx PCS
+ which is part of the Layerscape and QorIQ Ethernet SERDES.
+
++config PCS_MTK_USXGMII
++ tristate "MediaTek USXGMII PCS"
++ select PCS_MTK_LYNXI
++ select PHY_MTK_PEXTP
++ select PHYLINK
++ help
++ This module provides a driver for MediaTek's USXGMII PCS supporting
++ 10GBase-R, 5GBase-R and USXGMII interface modes.
++ 1000Base-X, 2500Base-X and Cisco SGMII are supported on the same
++ differential pairs via an embedded LynxI PHY.
++
+ config PCS_RZN1_MIIC
+ tristate "Renesas RZ/N1 MII converter"
+ depends on OF && (ARCH_RZN1 || COMPILE_TEST)
+--- a/drivers/net/pcs/Makefile
++++ b/drivers/net/pcs/Makefile
+@@ -8,3 +8,4 @@ obj-$(CONFIG_PCS_LYNX) += pcs-lynx.o
+ obj-$(CONFIG_PCS_RZN1_MIIC) += pcs-rzn1-miic.o
+ obj-$(CONFIG_PCS_ALTERA_TSE) += pcs-altera-tse.o
+ obj-$(CONFIG_PCS_MTK_LYNXI) += pcs-mtk-lynxi.o
++obj-$(CONFIG_PCS_MTK_USXGMII) += pcs-mtk-usxgmii.o
+--- /dev/null
++++ b/drivers/net/pcs/pcs-mtk-usxgmii.c
+@@ -0,0 +1,456 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2023 MediaTek Inc.
++ * Author: Henry Yen <henry.yen@mediatek.com>
++ * Daniel Golle <daniel@makrotopia.org>
++ */
++
++#include <linux/clk.h>
++#include <linux/io.h>
++#include <linux/mfd/syscon.h>
++#include <linux/mdio.h>
++#include <linux/mutex.h>
++#include <linux/of.h>
++#include <linux/of_platform.h>
++#include <linux/reset.h>
++#include <linux/pcs/pcs-mtk-usxgmii.h>
++#include <linux/platform_device.h>
++
++/* USXGMII subsystem config registers */
++/* Register to control speed */
++#define RG_PHY_TOP_SPEED_CTRL1 0x80c
++#define USXGMII_RATE_UPDATE_MODE BIT(31)
++#define USXGMII_MAC_CK_GATED BIT(29)
++#define USXGMII_IF_FORCE_EN BIT(28)
++#define USXGMII_RATE_ADAPT_MODE GENMASK(10, 8)
++#define USXGMII_RATE_ADAPT_MODE_X1 0
++#define USXGMII_RATE_ADAPT_MODE_X2 1
++#define USXGMII_RATE_ADAPT_MODE_X4 2
++#define USXGMII_RATE_ADAPT_MODE_X10 3
++#define USXGMII_RATE_ADAPT_MODE_X100 4
++#define USXGMII_RATE_ADAPT_MODE_X5 5
++#define USXGMII_RATE_ADAPT_MODE_X50 6
++#define USXGMII_XFI_RX_MODE GENMASK(6, 4)
++#define USXGMII_XFI_TX_MODE GENMASK(2, 0)
++#define USXGMII_XFI_MODE_10G 0
++#define USXGMII_XFI_MODE_5G 1
++#define USXGMII_XFI_MODE_2P5G 3
++
++/* Register to control PCS AN */
++#define RG_PCS_AN_CTRL0 0x810
++#define USXGMII_AN_RESTART BIT(31)
++#define USXGMII_AN_SYNC_CNT GENMASK(30, 11)
++#define USXGMII_AN_ENABLE BIT(0)
++
++#define RG_PCS_AN_CTRL2 0x818
++#define USXGMII_LINK_TIMER_IDLE_DETECT GENMASK(29, 20)
++#define USXGMII_LINK_TIMER_COMP_ACK_DETECT GENMASK(19, 10)
++#define USXGMII_LINK_TIMER_AN_RESTART GENMASK(9, 0)
++
++/* Register to read PCS AN status */
++#define RG_PCS_AN_STS0 0x81c
++#define USXGMII_LPA GENMASK(15, 0)
++#define USXGMII_LPA_LATCH BIT(31)
++
++/* Register to read PCS link status */
++#define RG_PCS_RX_STATUS0 0x904
++#define RG_PCS_RX_STATUS_UPDATE BIT(16)
++#define RG_PCS_RX_LINK_STATUS BIT(2)
++
++/* struct mtk_usxgmii_pcs - This structure holds each usxgmii PCS
++ * @pcs: Phylink PCS structure
++ * @dev: Pointer to device structure
++ * @base: IO memory to access PCS hardware
++ * @clk: Pointer to USXGMII clk
++ * @reset: Pointer to USXGMII reset control
++ * @interface: Currently selected interface mode
++ * @neg_mode: Currently used phylink neg_mode
++ * @node: List node
++ */
++struct mtk_usxgmii_pcs {
++ struct phylink_pcs pcs;
++ struct device *dev;
++ void __iomem *base;
++ struct clk *clk;
++ struct reset_control *reset;
++ phy_interface_t interface;
++ unsigned int neg_mode;
++ struct list_head node;
++};
++
++static LIST_HEAD(mtk_usxgmii_pcs_instances);
++static DEFINE_MUTEX(instance_mutex);
++
++static u32 mtk_r32(struct mtk_usxgmii_pcs *mpcs, unsigned int reg)
++{
++ return ioread32(mpcs->base + reg);
++}
++
++static void mtk_m32(struct mtk_usxgmii_pcs *mpcs, unsigned int reg, u32 mask, u32 set)
++{
++ u32 val;
++
++ val = ioread32(mpcs->base + reg);
++ val &= ~mask;
++ val |= set;
++ iowrite32(val, mpcs->base + reg);
++}
++
++static struct mtk_usxgmii_pcs *pcs_to_mtk_usxgmii_pcs(struct phylink_pcs *pcs)
++{
++ return container_of(pcs, struct mtk_usxgmii_pcs, pcs);
++}
++
++static void mtk_usxgmii_reset(struct mtk_usxgmii_pcs *mpcs)
++{
++ reset_control_assert(mpcs->reset);
++ udelay(100);
++ reset_control_deassert(mpcs->reset);
++
++ mdelay(10);
++}
++
++static int mtk_usxgmii_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
++ phy_interface_t interface,
++ const unsigned long *advertising,
++ bool permit_pause_to_mac)
++{
++ struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
++ unsigned int an_ctrl = 0, link_timer = 0, xfi_mode = 0, adapt_mode = 0;
++ bool mode_changed = false;
++
++ if (interface == PHY_INTERFACE_MODE_USXGMII) {
++ an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0x1FF) | USXGMII_AN_ENABLE;
++ link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x7B) |
++ FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x7B) |
++ FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x7B);
++ xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_MODE_10G) |
++ FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_MODE_10G);
++ } else if (interface == PHY_INTERFACE_MODE_10GBASER) {
++ an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0x1FF);
++ link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x7B) |
++ FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x7B) |
++ FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x7B);
++ xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_MODE_10G) |
++ FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_MODE_10G);
++ adapt_mode = USXGMII_RATE_UPDATE_MODE;
++ } else if (interface == PHY_INTERFACE_MODE_5GBASER) {
++ an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0xFF);
++ link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x3D) |
++ FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x3D) |
++ FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x3D);
++ xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_MODE_5G) |
++ FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_MODE_5G);
++ adapt_mode = USXGMII_RATE_UPDATE_MODE;
++ } else {
++ return -EINVAL;
++ }
++
++ adapt_mode |= FIELD_PREP(USXGMII_RATE_ADAPT_MODE, USXGMII_RATE_ADAPT_MODE_X1);
++
++ if (mpcs->interface != interface) {
++ mpcs->interface = interface;
++ mode_changed = true;
++ }
++
++ mtk_usxgmii_reset(mpcs);
++
++ /* Setup USXGMII AN ctrl */
++ mtk_m32(mpcs, RG_PCS_AN_CTRL0,
++ USXGMII_AN_SYNC_CNT | USXGMII_AN_ENABLE,
++ an_ctrl);
++
++ mtk_m32(mpcs, RG_PCS_AN_CTRL2,
++ USXGMII_LINK_TIMER_IDLE_DETECT |
++ USXGMII_LINK_TIMER_COMP_ACK_DETECT |
++ USXGMII_LINK_TIMER_AN_RESTART,
++ link_timer);
++
++ mpcs->neg_mode = neg_mode;
++
++ /* Gated MAC CK */
++ mtk_m32(mpcs, RG_PHY_TOP_SPEED_CTRL1,
++ USXGMII_MAC_CK_GATED, USXGMII_MAC_CK_GATED);
++
++ /* Enable interface force mode */
++ mtk_m32(mpcs, RG_PHY_TOP_SPEED_CTRL1,
++ USXGMII_IF_FORCE_EN, USXGMII_IF_FORCE_EN);
++
++ /* Setup USXGMII adapt mode */
++ mtk_m32(mpcs, RG_PHY_TOP_SPEED_CTRL1,
++ USXGMII_RATE_UPDATE_MODE | USXGMII_RATE_ADAPT_MODE,
++ adapt_mode);
++
++ /* Setup USXGMII speed */
++ mtk_m32(mpcs, RG_PHY_TOP_SPEED_CTRL1,
++ USXGMII_XFI_RX_MODE | USXGMII_XFI_TX_MODE,
++ xfi_mode);
++
++ usleep_range(1, 10);
++
++ /* Un-gated MAC CK */
++ mtk_m32(mpcs, RG_PHY_TOP_SPEED_CTRL1, USXGMII_MAC_CK_GATED, 0);
++
++ usleep_range(1, 10);
++
++ /* Disable interface force mode for the AN mode */
++ if (an_ctrl & USXGMII_AN_ENABLE)
++ mtk_m32(mpcs, RG_PHY_TOP_SPEED_CTRL1, USXGMII_IF_FORCE_EN, 0);
++
++ return mode_changed;
++}
++
++static void mtk_usxgmii_pcs_get_fixed_speed(struct mtk_usxgmii_pcs *mpcs,
++ struct phylink_link_state *state)
++{
++ u32 val = mtk_r32(mpcs, RG_PHY_TOP_SPEED_CTRL1);
++ int speed;
++
++ /* Calculate speed from interface speed and rate adapt mode */
++ switch (FIELD_GET(USXGMII_XFI_RX_MODE, val)) {
++ case USXGMII_XFI_MODE_10G:
++ speed = 10000;
++ break;
++ case USXGMII_XFI_MODE_5G:
++ speed = 5000;
++ break;
++ case USXGMII_XFI_MODE_2P5G:
++ speed = 2500;
++ break;
++ default:
++ state->speed = SPEED_UNKNOWN;
++ return;
++ }
++
++ switch (FIELD_GET(USXGMII_RATE_ADAPT_MODE, val)) {
++ case USXGMII_RATE_ADAPT_MODE_X100:
++ speed /= 100;
++ break;
++ case USXGMII_RATE_ADAPT_MODE_X50:
++ speed /= 50;
++ break;
++ case USXGMII_RATE_ADAPT_MODE_X10:
++ speed /= 10;
++ break;
++ case USXGMII_RATE_ADAPT_MODE_X5:
++ speed /= 5;
++ break;
++ case USXGMII_RATE_ADAPT_MODE_X4:
++ speed /= 4;
++ break;
++ case USXGMII_RATE_ADAPT_MODE_X2:
++ speed /= 2;
++ break;
++ case USXGMII_RATE_ADAPT_MODE_X1:
++ break;
++ default:
++ state->speed = SPEED_UNKNOWN;
++ return;
++ }
++
++ state->speed = speed;
++ state->duplex = DUPLEX_FULL;
++}
++
++static void mtk_usxgmii_pcs_get_an_state(struct mtk_usxgmii_pcs *mpcs,
++ struct phylink_link_state *state)
++{
++ u16 lpa;
++
++ /* Refresh LPA by toggling LPA_LATCH */
++ mtk_m32(mpcs, RG_PCS_AN_STS0, USXGMII_LPA_LATCH, USXGMII_LPA_LATCH);
++ ndelay(1020);
++ mtk_m32(mpcs, RG_PCS_AN_STS0, USXGMII_LPA_LATCH, 0);
++ ndelay(1020);
++ lpa = FIELD_GET(USXGMII_LPA, mtk_r32(mpcs, RG_PCS_AN_STS0));
++
++ phylink_decode_usxgmii_word(state, lpa);
++}
++
++static void mtk_usxgmii_pcs_get_state(struct phylink_pcs *pcs,
++ struct phylink_link_state *state)
++{
++ struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
++
++ /* Refresh USXGMII link status by toggling RG_PCS_AN_STATUS_UPDATE */
++ mtk_m32(mpcs, RG_PCS_RX_STATUS0, RG_PCS_RX_STATUS_UPDATE,
++ RG_PCS_RX_STATUS_UPDATE);
++ ndelay(1020);
++ mtk_m32(mpcs, RG_PCS_RX_STATUS0, RG_PCS_RX_STATUS_UPDATE, 0);
++ ndelay(1020);
++
++ /* Read USXGMII link status */
++ state->link = FIELD_GET(RG_PCS_RX_LINK_STATUS,
++ mtk_r32(mpcs, RG_PCS_RX_STATUS0));
++
++ /* Continuously repeat re-configuration sequence until link comes up */
++ if (!state->link) {
++ mtk_usxgmii_pcs_config(pcs, mpcs->neg_mode,
++ state->interface, NULL, false);
++ return;
++ }
++
++ if (FIELD_GET(USXGMII_AN_ENABLE, mtk_r32(mpcs, RG_PCS_AN_CTRL0)))
++ mtk_usxgmii_pcs_get_an_state(mpcs, state);
++ else
++ mtk_usxgmii_pcs_get_fixed_speed(mpcs, state);
++}
++
++static void mtk_usxgmii_pcs_restart_an(struct phylink_pcs *pcs)
++{
++ struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
++
++ mtk_m32(mpcs, RG_PCS_AN_CTRL0, USXGMII_AN_RESTART, USXGMII_AN_RESTART);
++}
++
++static void mtk_usxgmii_pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
++ phy_interface_t interface,
++ int speed, int duplex)
++{
++ /* Reconfiguring USXGMII to ensure the quality of the RX signal
++ * after the line side link up.
++ */
++ mtk_usxgmii_pcs_config(pcs, neg_mode, interface, NULL, false);
++}
++
++static void mtk_usxgmii_pcs_disable(struct phylink_pcs *pcs)
++{
++ struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
++
++ mpcs->interface = PHY_INTERFACE_MODE_NA;
++ mpcs->neg_mode = -1;
++}
++
++static const struct phylink_pcs_ops mtk_usxgmii_pcs_ops = {
++ .pcs_config = mtk_usxgmii_pcs_config,
++ .pcs_get_state = mtk_usxgmii_pcs_get_state,
++ .pcs_an_restart = mtk_usxgmii_pcs_restart_an,
++ .pcs_link_up = mtk_usxgmii_pcs_link_up,
++ .pcs_disable = mtk_usxgmii_pcs_disable,
++};
++
++static int mtk_usxgmii_probe(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ struct mtk_usxgmii_pcs *mpcs;
++
++ mpcs = devm_kzalloc(dev, sizeof(*mpcs), GFP_KERNEL);
++ if (!mpcs)
++ return -ENOMEM;
++
++ mpcs->base = devm_platform_ioremap_resource(pdev, 0);
++ if (IS_ERR(mpcs->base))
++ return PTR_ERR(mpcs->base);
++
++ mpcs->dev = dev;
++ mpcs->pcs.ops = &mtk_usxgmii_pcs_ops;
++ mpcs->pcs.poll = true;
++ mpcs->pcs.neg_mode = true;
++ mpcs->interface = PHY_INTERFACE_MODE_NA;
++ mpcs->neg_mode = -1;
++
++ mpcs->clk = devm_clk_get_enabled(mpcs->dev, NULL);
++ if (IS_ERR(mpcs->clk))
++ return PTR_ERR(mpcs->clk);
++
++ mpcs->reset = devm_reset_control_get_shared(dev, NULL);
++ if (IS_ERR(mpcs->reset))
++ return PTR_ERR(mpcs->reset);
++
++ reset_control_deassert(mpcs->reset);
++
++ platform_set_drvdata(pdev, mpcs);
++
++ mutex_lock(&instance_mutex);
++ list_add_tail(&mpcs->node, &mtk_usxgmii_pcs_instances);
++ mutex_unlock(&instance_mutex);
++
++ return 0;
++}
++
++static int mtk_usxgmii_remove(struct platform_device *pdev)
++{
++ struct device *dev = &pdev->dev;
++ struct mtk_usxgmii_pcs *cur, *tmp;
++
++ mutex_lock(&instance_mutex);
++ list_for_each_entry_safe(cur, tmp, &mtk_usxgmii_pcs_instances, node)
++ if (cur->dev == dev) {
++ list_del(&cur->node);
++ break;
++ }
++ mutex_unlock(&instance_mutex);
++
++ return 0;
++}
++
++static const struct of_device_id mtk_usxgmii_of_mtable[] = {
++ { .compatible = "mediatek,mt7988-usxgmiisys" },
++ { /* sentinel */ },
++};
++MODULE_DEVICE_TABLE(of, mtk_usxgmii_of_mtable);
++
++struct phylink_pcs *mtk_usxgmii_pcs_get(struct device *dev, struct device_node *np)
++{
++ struct platform_device *pdev;
++ struct mtk_usxgmii_pcs *mpcs;
++
++ if (!np)
++ return NULL;
++
++ if (!of_device_is_available(np))
++ return ERR_PTR(-ENODEV);
++
++ if (!of_match_node(mtk_usxgmii_of_mtable, np))
++ return ERR_PTR(-EINVAL);
++
++ pdev = of_find_device_by_node(np);
++ if (!pdev || !platform_get_drvdata(pdev)) {
++ if (pdev)
++ put_device(&pdev->dev);
++ return ERR_PTR(-EPROBE_DEFER);
++ }
++
++ mpcs = platform_get_drvdata(pdev);
++ device_link_add(dev, mpcs->dev, DL_FLAG_AUTOREMOVE_CONSUMER);
++
++ return &mpcs->pcs;
++}
++EXPORT_SYMBOL(mtk_usxgmii_pcs_get);
++
++void mtk_usxgmii_pcs_put(struct phylink_pcs *pcs)
++{
++ struct mtk_usxgmii_pcs *cur, *mpcs = NULL;
++
++ if (!pcs)
++ return;
++
++ mutex_lock(&instance_mutex);
++ list_for_each_entry(cur, &mtk_usxgmii_pcs_instances, node)
++ if (pcs == &cur->pcs) {
++ mpcs = cur;
++ break;
++ }
++ mutex_unlock(&instance_mutex);
++
++ if (WARN_ON(!mpcs))
++ return;
++
++ put_device(mpcs->dev);
++}
++EXPORT_SYMBOL(mtk_usxgmii_pcs_put);
++
++static struct platform_driver mtk_usxgmii_driver = {
++ .driver = {
++ .name = "mtk_usxgmii",
++ .suppress_bind_attrs = true,
++ .of_match_table = mtk_usxgmii_of_mtable,
++ },
++ .probe = mtk_usxgmii_probe,
++ .remove = mtk_usxgmii_remove,
++};
++module_platform_driver(mtk_usxgmii_driver);
++
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("MediaTek USXGMII PCS driver");
++MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
+--- /dev/null
++++ b/include/linux/pcs/pcs-mtk-usxgmii.h
+@@ -0,0 +1,27 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++#ifndef __LINUX_PCS_MTK_USXGMII_H
++#define __LINUX_PCS_MTK_USXGMII_H
++
++#include <linux/phylink.h>
++
++/**
++ * mtk_usxgmii_select_pcs() - Get MediaTek PCS instance
++ * @np: Pointer to device node indentifying a MediaTek USXGMII PCS
++ * @mode: Ethernet PHY interface mode
++ *
++ * Return PCS identified by a device node and the PHY interface mode in use
++ *
++ * Return: Pointer to phylink PCS instance of NULL
++ */
++#if IS_ENABLED(CONFIG_PCS_MTK_USXGMII)
++struct phylink_pcs *mtk_usxgmii_pcs_get(struct device *dev, struct device_node *np);
++void mtk_usxgmii_pcs_put(struct phylink_pcs *pcs);
++#else
++static inline struct phylink_pcs *mtk_usxgmii_pcs_get(struct device *dev, struct device_node *np)
++{
++ return NULL;
++}
++static inline void mtk_usxgmii_pcs_put(struct phylink_pcs *pcs) { }
++#endif /* IS_ENABLED(CONFIG_PCS_MTK_USXGMII) */
++
++#endif /* __LINUX_PCS_MTK_USXGMII_H */
--- a/MAINTAINERS
+++ b/MAINTAINERS
-@@ -17066,6 +17066,13 @@ L: netdev@vger.kernel.org
+@@ -17068,6 +17068,13 @@ L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/ethernet/qualcomm/emac/
--- a/MAINTAINERS
+++ b/MAINTAINERS
-@@ -17072,6 +17072,7 @@ L: netdev@vger.kernel.org
+@@ -17074,6 +17074,7 @@ L: netdev@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/net/qcom,ipq4019-ess-edma.yaml
F: drivers/net/ethernet/qualcomm/ipqess/
#include <dt-bindings/leds/common.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/pinctrl/mt65xx.h>
-#include <dt-bindings/reset/ti-syscon.h>
+#include <dt-bindings/reset/mediatek,mt7988-resets.h>
#include <dt-bindings/thermal/thermal.h>
+/* TOPRGU resets */
+#define MT7988_TOPRGU_SGMII0_GRST 1
+#define MT7988_TOPRGU_SGMII1_GRST 2
+#define MT7988_TOPRGU_XFI0_GRST 12
+#define MT7988_TOPRGU_XFI1_GRST 13
+#define MT7988_TOPRGU_XFI_PEXTP0_GRST 14
+#define MT7988_TOPRGU_XFI_PEXTP1_GRST 15
+#define MT7988_TOPRGU_XFI_PLL_GRST 16
+
/ {
compatible = "mediatek,mt7988";
interrupt-parent = <&gic>;
compatible = "mediatek,mt7988-infracfg", "syscon";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
topckgen: topckgen@1001b000 {
sgmiisys0: syscon@10060000 {
compatible = "mediatek,mt7988-sgmiisys",
- "mediatek,mt7988-sgmiisys_0",
- "syscon";
+ "mediatek,mt7988-sgmiisys0",
+ "syscon",
+ "simple-mfd";
reg = <0 0x10060000 0 0x1000>;
+ resets = <&watchdog MT7988_TOPRGU_SGMII0_GRST>;
#clock-cells = <1>;
+
+ sgmiipcs0: pcs {
+ compatible = "mediatek,mt7988-sgmii";
+ clocks = <&topckgen CLK_TOP_SGM_0_SEL>,
+ <&sgmiisys0 CLK_SGM0_TX_EN>,
+ <&sgmiisys0 CLK_SGM0_RX_EN>;
+ clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx";
+ };
};
sgmiisys1: syscon@10070000 {
compatible = "mediatek,mt7988-sgmiisys",
- "mediatek,mt7988-sgmiisys_1",
- "syscon";
+ "mediatek,mt7988-sgmiisys1",
+ "syscon",
+ "simple-mfd";
reg = <0 0x10070000 0 0x1000>;
+ resets = <&watchdog MT7988_TOPRGU_SGMII1_GRST>;
#clock-cells = <1>;
+
+ sgmiipcs1: pcs {
+ compatible = "mediatek,mt7988-sgmii";
+ clocks = <&topckgen CLK_TOP_SGM_1_SEL>,
+ <&sgmiisys1 CLK_SGM1_TX_EN>,
+ <&sgmiisys1 CLK_SGM1_RX_EN>;
+ clock-names = "sgmii_sel", "sgmii_tx", "sgmii_rx";
+ };
};
- usxgmiisys0: usxgmiisys@10080000 {
- compatible = "mediatek,mt7988-usxgmiisys",
- "mediatek,mt7988-usxgmiisys_0",
- "syscon";
+ usxgmiisys0: pcs@10080000 {
+ compatible = "mediatek,mt7988-usxgmiisys";
reg = <0 0x10080000 0 0x1000>;
- #clock-cells = <1>;
+ resets = <&watchdog MT7988_TOPRGU_XFI0_GRST>;
+ clocks = <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>;
};
- usxgmiisys1: usxgmiisys@10081000 {
- compatible = "mediatek,mt7988-usxgmiisys",
- "mediatek,mt7988-usxgmiisys_1",
- "syscon";
+ usxgmiisys1: pcs@10081000 {
+ compatible = "mediatek,mt7988-usxgmiisys";
reg = <0 0x10081000 0 0x1000>;
- #clock-cells = <1>;
+ resets = <&watchdog MT7988_TOPRGU_XFI1_GRST>;
+ clocks = <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>;
};
mcusys: mcusys@100e0000 {
};
};
- xfi_pextp0: xfi-pextp@11f20000 {
- compatible = "mediatek,mt7988-xfi-pextp",
- "mediatek,mt7988-xfi-pextp_0",
- "syscon";
+ xfi_tphy0: phy@11f20000 {
+ compatible = "mediatek,mt7988-xfi-tphy";
reg = <0 0x11f20000 0 0x10000>;
- #clock-cells = <1>;
+ resets = <&watchdog MT7988_TOPRGU_XFI_PEXTP0_GRST>;
+ clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>;
+ clock-names = "xfipll", "topxtal";
+ mediatek,usxgmii-performance-errata;
+ #phy-cells = <0>;
};
- xfi_pextp1: xfi-pextp@11f30000 {
- compatible = "mediatek,mt7988-xfi-pextp",
- "mediatek,mt7988-xfi-pextp_1",
- "syscon";
+ xfi_tphy1: phy@11f30000 {
+ compatible = "mediatek,mt7988-xfi-tphy";
reg = <0 0x11f30000 0 0x10000>;
- #clock-cells = <1>;
+ resets = <&watchdog MT7988_TOPRGU_XFI_PEXTP1_GRST>;
+ clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>;
+ clock-names = "xfipll", "topxtal";
+ #phy-cells = <0>;
};
- xfi_pll: xfi-pll@11f40000 {
- compatible = "mediatek,mt7988-xfi-pll", "syscon";
+ xfi_pll: clock-controller@11f40000 {
+ compatible = "mediatek,mt7988-xfi-pll";
reg = <0 0x11f40000 0 0x1000>;
+ resets = <&watchdog MT7988_TOPRGU_XFI_PLL_GRST>;
#clock-cells = <1>;
};
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
- resets = <ðrst 0>;
+ resets = <ðwarp MT7988_ETHWARP_RST_SWITCH>;
#address-cells = <1>;
#size-cells = <1>;
};
};
- ethwarp: syscon@15031000 {
- compatible = "mediatek,mt7988-ethwarp", "syscon", "simple-mfd";
+ ethwarp: clock-controller@15031000 {
+ compatible = "mediatek,mt7988-ethwarp";
reg = <0 0x15031000 0 0x1000>;
#clock-cells = <1>;
-
- ethrst: reset-controller {
- compatible = "ti,syscon-reset";
- #reset-cells = <1>;
- ti,reset-bits = <
- 0x8 9 0x8 9 0 0 (ASSERT_SET | DEASSERT_CLEAR | STATUS_NONE)
- >;
- };
+ #reset-cells = <1>;
};
eth: ethernet@15100000 {
<ðsys CLK_ETHDMA_GP3_EN>,
<ðsys CLK_ETHDMA_ESW_EN>,
<ðsys CLK_ETHDMA_CRYPT0_EN>,
- <&sgmiisys0 CLK_SGM0_TX_EN>,
- <&sgmiisys0 CLK_SGM0_RX_EN>,
- <&sgmiisys1 CLK_SGM1_TX_EN>,
- <&sgmiisys1 CLK_SGM1_RX_EN>,
<ðwarp CLK_ETHWARP_WOCPU2_EN>,
<ðwarp CLK_ETHWARP_WOCPU1_EN>,
<ðwarp CLK_ETHWARP_WOCPU0_EN>,
- <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
- <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
- <&topckgen CLK_TOP_SGM_0_SEL>,
- <&topckgen CLK_TOP_SGM_1_SEL>,
- <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>,
- <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>,
<&topckgen CLK_TOP_ETH_GMII_SEL>,
<&topckgen CLK_TOP_ETH_REFCK_50M_SEL>,
<&topckgen CLK_TOP_ETH_SYS_200M_SEL>,
<&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>,
<&topckgen CLK_TOP_NETSYS_WARP_SEL>;
clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1",
- "gp3", "esw", "crypto", "sgmii_tx250m",
- "sgmii_rx250m", "sgmii2_tx250m", "sgmii2_rx250m",
+ "gp3", "esw", "crypto",
"ethwarp_wocpu2", "ethwarp_wocpu1",
- "ethwarp_wocpu0", "top_usxgmii0_sel",
- "top_usxgmii1_sel", "top_sgm0_sel",
- "top_sgm1_sel", "top_xfi_phy0_xtal_sel",
- "top_xfi_phy1_xtal_sel", "top_eth_gmii_sel",
+ "ethwarp_wocpu0", "top_eth_gmii_sel",
"top_eth_refck_50m_sel", "top_eth_sys_200m_sel",
"top_eth_sys_sel", "top_eth_xgmii_sel",
"top_eth_mii_sel", "top_netsys_sel",
<&apmixedsys CLK_APMIXED_SGMPLL>,
<&apmixedsys CLK_APMIXED_SGMPLL>;
mediatek,ethsys = <ðsys>;
- mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
- mediatek,usxgmiisys = <&usxgmiisys0>, <&usxgmiisys1>;
- mediatek,xfi-pextp = <&xfi_pextp0>, <&xfi_pextp1>;
- mediatek,xfi-pll = <&xfi_pll>;
mediatek,infracfg = <&topmisc>;
- mediatek,toprgu = <&watchdog>;
- #reset-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "mediatek,eth-mac";
reg = <1>;
status = "disabled";
+ pcs-handle = <&sgmiipcs1>, <&usxgmiisys1>;
+ phys = <&xfi_tphy1>;
};
gmac2: mac@2 {
compatible = "mediatek,eth-mac";
reg = <2>;
status = "disabled";
+ pcs-handle = <&sgmiipcs0>, <&usxgmiisys0>;
+ phys = <&xfi_tphy0>;
};
mdio_bus: mdio-bus {
CONFIG_NET_DSA_TAG_MTK=y
CONFIG_NET_FLOW_LIMIT=y
CONFIG_NET_MEDIATEK_SOC=y
-CONFIG_NET_MEDIATEK_SOC_USXGMII=y
CONFIG_NET_MEDIATEK_SOC_WED=y
CONFIG_NET_SELFTESTS=y
CONFIG_NET_SWITCHDEV=y
CONFIG_PCI_MSI=y
CONFIG_PCI_MSI_IRQ_DOMAIN=y
CONFIG_PCS_MTK_LYNXI=y
+CONFIG_PCS_MTK_USXGMII=y
CONFIG_PERF_EVENTS=y
CONFIG_PGTABLE_LEVELS=3
CONFIG_PHYLIB=y
# CONFIG_PHY_MTK_PCIE is not set
CONFIG_PHY_MTK_TPHY=y
# CONFIG_PHY_MTK_UFS is not set
+CONFIG_PHY_MTK_XFI_TPHY=y
CONFIG_PHY_MTK_XSPHY=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_MT2712 is not set
--- a/MAINTAINERS
+++ b/MAINTAINERS
-@@ -12936,6 +12936,15 @@ S: Maintained
- F: drivers/net/pcs/pcs-mtk-lynxi.c
+@@ -12938,6 +12938,15 @@ F: drivers/net/pcs/pcs-mtk-usxgmii.c
F: include/linux/pcs/pcs-mtk-lynxi.h
+ F: include/linux/pcs/pcs-mtk-usxgmii.h
+MEDIATEK ETHERNET PHY DRIVERS
+M: Daniel Golle <daniel@makrotopia.org>
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1238,7 +1238,7 @@ static int mtk_init_fq_dma(struct mtk_et
+@@ -1264,7 +1264,7 @@ static int mtk_init_fq_dma(struct mtk_et
eth->scratch_ring = eth->sram_base;
else
eth->scratch_ring = dma_alloc_coherent(eth->dma_dev,
ð->phy_scratch_ring,
GFP_KERNEL);
if (unlikely(!eth->scratch_ring))
-@@ -1254,16 +1254,16 @@ static int mtk_init_fq_dma(struct mtk_et
+@@ -1280,16 +1280,16 @@ static int mtk_init_fq_dma(struct mtk_et
if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr)))
return -ENOMEM;
txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE);
txd->txd4 = 0;
-@@ -1512,7 +1512,7 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -1538,7 +1538,7 @@ static int mtk_tx_map(struct sk_buff *sk
if (itxd == ring->last_free)
return -ENOMEM;
memset(itx_buf, 0, sizeof(*itx_buf));
txd_info.addr = dma_map_single(eth->dma_dev, skb->data, txd_info.size,
-@@ -1553,7 +1553,7 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -1579,7 +1579,7 @@ static int mtk_tx_map(struct sk_buff *sk
memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info));
txd_info.size = min_t(unsigned int, frag_size,
txd_info.qid = queue;
txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 &&
!(frag_size - txd_info.size);
-@@ -1566,7 +1566,7 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -1592,7 +1592,7 @@ static int mtk_tx_map(struct sk_buff *sk
mtk_tx_set_dma_desc(dev, txd, &txd_info);
tx_buf = mtk_desc_to_tx_buf(ring, txd,
if (new_desc)
memset(tx_buf, 0, sizeof(*tx_buf));
tx_buf->data = (void *)MTK_DMA_DUMMY_DESC;
-@@ -1609,7 +1609,7 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -1635,7 +1635,7 @@ static int mtk_tx_map(struct sk_buff *sk
} else {
int next_idx;
ring->dma_size);
mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0);
}
-@@ -1618,7 +1618,7 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -1644,7 +1644,7 @@ static int mtk_tx_map(struct sk_buff *sk
err_dma:
do {
/* unmap dma */
mtk_tx_unmap(eth, tx_buf, NULL, false);
-@@ -1643,7 +1643,7 @@ static int mtk_cal_txd_req(struct mtk_et
+@@ -1669,7 +1669,7 @@ static int mtk_cal_txd_req(struct mtk_et
for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
frag = &skb_shinfo(skb)->frags[i];
nfrags += DIV_ROUND_UP(skb_frag_size(frag),
}
} else {
nfrags += skb_shinfo(skb)->nr_frags;
-@@ -1784,7 +1784,7 @@ static struct mtk_rx_ring *mtk_get_rx_ri
+@@ -1810,7 +1810,7 @@ static struct mtk_rx_ring *mtk_get_rx_ri
ring = ð->rx_ring[i];
idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
if (rxd->rxd2 & RX_DMA_DONE) {
ring->calc_idx_update = true;
return ring;
-@@ -1952,7 +1952,7 @@ static int mtk_xdp_submit_frame(struct m
+@@ -1978,7 +1978,7 @@ static int mtk_xdp_submit_frame(struct m
}
htxd = txd;
memset(tx_buf, 0, sizeof(*tx_buf));
htx_buf = tx_buf;
-@@ -1971,7 +1971,7 @@ static int mtk_xdp_submit_frame(struct m
+@@ -1997,7 +1997,7 @@ static int mtk_xdp_submit_frame(struct m
goto unmap;
tx_buf = mtk_desc_to_tx_buf(ring, txd,
memset(tx_buf, 0, sizeof(*tx_buf));
n_desc++;
}
-@@ -2009,7 +2009,7 @@ static int mtk_xdp_submit_frame(struct m
+@@ -2035,7 +2035,7 @@ static int mtk_xdp_submit_frame(struct m
} else {
int idx;
mtk_w32(eth, NEXT_DESP_IDX(idx, ring->dma_size),
MT7628_TX_CTX_IDX0);
}
-@@ -2020,7 +2020,7 @@ static int mtk_xdp_submit_frame(struct m
+@@ -2046,7 +2046,7 @@ static int mtk_xdp_submit_frame(struct m
unmap:
while (htxd != txd) {
mtk_tx_unmap(eth, tx_buf, NULL, false);
htxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
-@@ -2151,7 +2151,7 @@ static int mtk_poll_rx(struct napi_struc
+@@ -2177,7 +2177,7 @@ static int mtk_poll_rx(struct napi_struc
goto rx_done;
idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
data = ring->data[idx];
if (!mtk_rx_get_desc(eth, &trxd, rxd))
-@@ -2286,7 +2286,7 @@ static int mtk_poll_rx(struct napi_struc
+@@ -2312,7 +2312,7 @@ static int mtk_poll_rx(struct napi_struc
rxdcsum = &trxd.rxd4;
}
skb->ip_summed = CHECKSUM_UNNECESSARY;
else
skb_checksum_none_assert(skb);
-@@ -2410,7 +2410,7 @@ static int mtk_poll_tx_qdma(struct mtk_e
+@@ -2436,7 +2436,7 @@ static int mtk_poll_tx_qdma(struct mtk_e
break;
tx_buf = mtk_desc_to_tx_buf(ring, desc,
if (!tx_buf->data)
break;
-@@ -2461,7 +2461,7 @@ static int mtk_poll_tx_pdma(struct mtk_e
+@@ -2487,7 +2487,7 @@ static int mtk_poll_tx_pdma(struct mtk_e
}
mtk_tx_unmap(eth, tx_buf, &bq, true);
ring->last_free = desc;
atomic_inc(&ring->free_count);
-@@ -2551,7 +2551,7 @@ static int mtk_napi_rx(struct napi_struc
+@@ -2577,7 +2577,7 @@ static int mtk_napi_rx(struct napi_struc
do {
int rx_done;
reg_map->pdma.irq_status);
rx_done = mtk_poll_rx(napi, budget - rx_done_total, eth);
rx_done_total += rx_done;
-@@ -2567,10 +2567,10 @@ static int mtk_napi_rx(struct napi_struc
+@@ -2593,10 +2593,10 @@ static int mtk_napi_rx(struct napi_struc
return budget;
} while (mtk_r32(eth, reg_map->pdma.irq_status) &
return rx_done_total;
}
-@@ -2579,7 +2579,7 @@ static int mtk_tx_alloc(struct mtk_eth *
+@@ -2605,7 +2605,7 @@ static int mtk_tx_alloc(struct mtk_eth *
{
const struct mtk_soc_data *soc = eth->soc;
struct mtk_tx_ring *ring = ð->tx_ring;
struct mtk_tx_dma_v2 *txd;
int ring_size;
u32 ofs, val;
-@@ -2702,14 +2702,14 @@ static void mtk_tx_clean(struct mtk_eth
+@@ -2728,14 +2728,14 @@ static void mtk_tx_clean(struct mtk_eth
}
if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && ring->dma) {
dma_free_coherent(eth->dma_dev,
ring->dma_pdma, ring->phys_pdma);
ring->dma_pdma = NULL;
}
-@@ -2764,15 +2764,15 @@ static int mtk_rx_alloc(struct mtk_eth *
+@@ -2790,15 +2790,15 @@ static int mtk_rx_alloc(struct mtk_eth *
if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM) ||
rx_flag != MTK_RX_FLAGS_NORMAL) {
ring->dma = dma_alloc_coherent(eth->dma_dev,
}
if (!ring->dma)
-@@ -2783,7 +2783,7 @@ static int mtk_rx_alloc(struct mtk_eth *
+@@ -2809,7 +2809,7 @@ static int mtk_rx_alloc(struct mtk_eth *
dma_addr_t dma_addr;
void *data;
if (ring->page_pool) {
data = mtk_page_pool_get_buff(ring->page_pool,
&dma_addr, GFP_KERNEL);
-@@ -2874,7 +2874,7 @@ static void mtk_rx_clean(struct mtk_eth
+@@ -2900,7 +2900,7 @@ static void mtk_rx_clean(struct mtk_eth
if (!ring->data[i])
continue;
if (!rxd->rxd1)
continue;
-@@ -2891,7 +2891,7 @@ static void mtk_rx_clean(struct mtk_eth
+@@ -2917,7 +2917,7 @@ static void mtk_rx_clean(struct mtk_eth
if (!in_sram && ring->dma) {
dma_free_coherent(eth->dma_dev,
ring->dma, ring->phys);
ring->dma = NULL;
}
-@@ -3254,7 +3254,7 @@ static void mtk_dma_free(struct mtk_eth
+@@ -3280,7 +3280,7 @@ static void mtk_dma_free(struct mtk_eth
netdev_reset_queue(eth->netdev[i]);
if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && eth->scratch_ring) {
dma_free_coherent(eth->dma_dev,
eth->scratch_ring, eth->phy_scratch_ring);
eth->scratch_ring = NULL;
eth->phy_scratch_ring = 0;
-@@ -3304,7 +3304,7 @@ static irqreturn_t mtk_handle_irq_rx(int
+@@ -3330,7 +3330,7 @@ static irqreturn_t mtk_handle_irq_rx(int
eth->rx_events++;
if (likely(napi_schedule_prep(ð->rx_napi))) {
__napi_schedule(ð->rx_napi);
}
-@@ -3330,9 +3330,9 @@ static irqreturn_t mtk_handle_irq(int ir
+@@ -3356,9 +3356,9 @@ static irqreturn_t mtk_handle_irq(int ir
const struct mtk_reg_map *reg_map = eth->soc->reg_map;
if (mtk_r32(eth, reg_map->pdma.irq_mask) &
mtk_handle_irq_rx(irq, _eth);
}
if (mtk_r32(eth, reg_map->tx_irq_mask) & MTK_TX_DONE_INT) {
-@@ -3350,10 +3350,10 @@ static void mtk_poll_controller(struct n
+@@ -3376,10 +3376,10 @@ static void mtk_poll_controller(struct n
struct mtk_eth *eth = mac->hw;
mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
}
#endif
-@@ -3516,7 +3516,7 @@ static int mtk_open(struct net_device *d
+@@ -3545,7 +3545,7 @@ static int mtk_open(struct net_device *d
napi_enable(ð->tx_napi);
napi_enable(ð->rx_napi);
mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
refcount_set(ð->dma_refcnt, 1);
}
else
-@@ -3599,7 +3599,7 @@ static int mtk_stop(struct net_device *d
+@@ -3628,7 +3628,7 @@ static int mtk_stop(struct net_device *d
mtk_gdm_config(eth, MTK_GDMA_DROP_ALL);
mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
napi_disable(ð->tx_napi);
napi_disable(ð->rx_napi);
-@@ -4075,9 +4075,9 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -4107,9 +4107,9 @@ static int mtk_hw_init(struct mtk_eth *e
/* FE int grouping */
mtk_w32(eth, MTK_TX_DONE_INT, reg_map->pdma.int_grp);
mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
if (mtk_is_netsys_v3_or_greater(eth)) {
-@@ -5175,11 +5175,15 @@ static const struct mtk_soc_data mt2701_
+@@ -5270,11 +5270,15 @@ static const struct mtk_soc_data mt2701_
.required_clks = MT7623_CLKS_BITMAP,
.required_pctl = true,
.version = 1,
.dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16,
},
-@@ -5195,11 +5199,15 @@ static const struct mtk_soc_data mt7621_
+@@ -5290,11 +5294,15 @@ static const struct mtk_soc_data mt7621_
.offload_version = 1,
.hash_offset = 2,
.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
.dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16,
},
-@@ -5217,11 +5225,15 @@ static const struct mtk_soc_data mt7622_
+@@ -5312,11 +5320,15 @@ static const struct mtk_soc_data mt7622_
.hash_offset = 2,
.has_accounting = true,
.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
.dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16,
},
-@@ -5238,11 +5250,15 @@ static const struct mtk_soc_data mt7623_
+@@ -5333,11 +5345,15 @@ static const struct mtk_soc_data mt7623_
.hash_offset = 2,
.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
.disable_pll_modes = true,
.dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16,
},
-@@ -5257,11 +5273,15 @@ static const struct mtk_soc_data mt7629_
+@@ -5352,11 +5368,15 @@ static const struct mtk_soc_data mt7629_
.required_pctl = false,
.has_accounting = true,
.version = 1,
.dma_max_len = MTK_TX_DMA_BUF_LEN,
.dma_len_offset = 16,
},
-@@ -5279,11 +5299,15 @@ static const struct mtk_soc_data mt7981_
+@@ -5374,11 +5394,15 @@ static const struct mtk_soc_data mt7981_
.hash_offset = 4,
.has_accounting = true,
.foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
.dma_len_offset = 8,
},
-@@ -5301,11 +5325,15 @@ static const struct mtk_soc_data mt7986_
+@@ -5396,11 +5420,15 @@ static const struct mtk_soc_data mt7986_
.hash_offset = 4,
.has_accounting = true,
.foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
.dma_len_offset = 8,
},
-@@ -5323,11 +5351,15 @@ static const struct mtk_soc_data mt7988_
+@@ -5418,11 +5446,15 @@ static const struct mtk_soc_data mt7988_
.hash_offset = 4,
.has_accounting = true,
.foe_entry_size = MTK_FOE_ENTRY_V3_SIZE,
.dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
.dma_len_offset = 8,
},
-@@ -5340,11 +5372,15 @@ static const struct mtk_soc_data rt5350_
+@@ -5435,11 +5467,15 @@ static const struct mtk_soc_data rt5350_
.required_clks = MT7628_CLKS_BITMAP,
.required_pctl = false,
.version = 1,
},
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -326,8 +326,8 @@
+@@ -327,8 +327,8 @@
/* QDMA descriptor txd3 */
#define TX_DMA_OWNER_CPU BIT(31)
#define TX_DMA_LS0 BIT(30)
#define TX_DMA_SWC BIT(14)
#define TX_DMA_PQID GENMASK(3, 0)
#define TX_DMA_ADDR64_MASK GENMASK(3, 0)
-@@ -347,8 +347,8 @@
+@@ -348,8 +348,8 @@
/* QDMA descriptor rxd2 */
#define RX_DMA_DONE BIT(31)
#define RX_DMA_LSO BIT(30)
#define RX_DMA_VTAG BIT(15)
#define RX_DMA_ADDR64_MASK GENMASK(3, 0)
#if IS_ENABLED(CONFIG_64BIT)
-@@ -1279,10 +1279,9 @@ struct mtk_reg_map {
+@@ -1209,10 +1209,9 @@ struct mtk_reg_map {
* @foe_entry_size Foe table entry size.
* @has_accounting Bool indicating support for accounting of
* offloaded flows.
* @dma_max_len Max DMA tx/rx buffer length.
* @dma_len_offset Tx/Rx DMA length field offset.
*/
-@@ -1300,13 +1299,17 @@ struct mtk_soc_data {
+@@ -1230,13 +1229,17 @@ struct mtk_soc_data {
bool has_accounting;
bool disable_pll_modes;
struct {
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -108,16 +108,16 @@ static const struct mtk_reg_map mt7986_r
+@@ -110,16 +110,16 @@ static const struct mtk_reg_map mt7986_r
.tx_irq_mask = 0x461c,
.tx_irq_status = 0x4618,
.pdma = {
},
.qdma = {
.qtx_cfg = 0x4400,
-@@ -1206,7 +1206,7 @@ static bool mtk_rx_get_desc(struct mtk_e
+@@ -1232,7 +1232,7 @@ static bool mtk_rx_get_desc(struct mtk_e
rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
rxd->rxd5 = READ_ONCE(dma_rxd->rxd5);
rxd->rxd6 = READ_ONCE(dma_rxd->rxd6);
}
-@@ -2158,7 +2158,7 @@ static int mtk_poll_rx(struct napi_struc
+@@ -2184,7 +2184,7 @@ static int mtk_poll_rx(struct napi_struc
break;
/* find out which mac the packet come from. values start at 1 */
u32 val = RX_DMA_GET_SPORT_V2(trxd.rxd5);
switch (val) {
-@@ -2270,7 +2270,7 @@ static int mtk_poll_rx(struct napi_struc
+@@ -2296,7 +2296,7 @@ static int mtk_poll_rx(struct napi_struc
skb->dev = netdev;
bytes += skb->len;
reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5);
hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY;
if (hash != MTK_RXD5_FOE_ENTRY)
-@@ -2820,7 +2820,7 @@ static int mtk_rx_alloc(struct mtk_eth *
+@@ -2846,7 +2846,7 @@ static int mtk_rx_alloc(struct mtk_eth *
rxd->rxd3 = 0;
rxd->rxd4 = 0;
rxd->rxd5 = 0;
rxd->rxd6 = 0;
rxd->rxd7 = 0;
-@@ -4021,7 +4021,7 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -4053,7 +4053,7 @@ static int mtk_hw_init(struct mtk_eth *e
else
mtk_hw_reset(eth);
/* Set FE to PDMAv2 if necessary */
val = mtk_r32(eth, MTK_FE_GLO_MISC);
mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC);
-@@ -5305,11 +5305,11 @@ static const struct mtk_soc_data mt7981_
+@@ -5400,11 +5400,11 @@ static const struct mtk_soc_data mt7981_
.dma_len_offset = 8,
},
.rx = {
},
};
-@@ -5331,11 +5331,11 @@ static const struct mtk_soc_data mt7986_
+@@ -5426,11 +5426,11 @@ static const struct mtk_soc_data mt7986_
.dma_len_offset = 8,
},
.rx = {
--- a/MAINTAINERS
+++ b/MAINTAINERS
-@@ -13012,6 +13012,12 @@ S: Maintained
+@@ -13014,6 +13014,12 @@ S: Maintained
F: Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml
F: drivers/clk/ralink/clk-mt7621.c
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -4612,6 +4612,7 @@ static const struct net_device_ops mtk_n
+@@ -4643,6 +4643,7 @@ static const struct net_device_ops mtk_n
static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
{
+ const char *name = of_get_property(np, "label", NULL);
const __be32 *_id = of_get_property(np, "reg", NULL);
+ struct device_node *pcs_np;
phy_interface_t phy_mode;
- struct phylink *phylink;
-@@ -4783,6 +4784,9 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4840,6 +4841,9 @@ static int mtk_add_mac(struct mtk_eth *e
register_netdevice_notifier(&mac->device_notifier);
}
projects / openwrt / staging / jow.git / commitdiff