1 From 87e3fcaad3017bdc91a7a79d2d1c874422ef87b0 Mon Sep 17 00:00:00 2001
2 From: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
3 Date: Thu, 20 Jul 2023 11:44:40 +0200
4 Subject: [PATCH] media: i2c: Add driver for OmniVision OV64A40
6 Add a driver for the OmniVision OV64A40 image sensor.
8 Signed-off-by: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
11 drivers/media/i2c/Kconfig | 14 +
12 drivers/media/i2c/Makefile | 1 +
13 drivers/media/i2c/ov64a40.c | 3694 +++++++++++++++++++++++++++++++++++
14 4 files changed, 3717 insertions(+)
15 create mode 100644 drivers/media/i2c/ov64a40.c
19 @@ -15321,6 +15321,14 @@ S: Maintained
20 T: git git://linuxtv.org/media_tree.git
21 F: drivers/media/i2c/ov5695.c
23 +OMNIVISION OV64A40 SENSOR DRIVER
24 +M: Jacopo Mondi <jacopo.mondi@ideasonboard.com>
25 +L: linux-media@vger.kernel.org
27 +T: git git://linuxtv.org/media_tree.git
28 +F: Documentation/devicetree/bindings/media/i2c/ovti,ov64a40.yaml
29 +F: drivers/media/i2c/ov64a40.c
31 OMNIVISION OV7670 SENSOR DRIVER
32 L: linux-media@vger.kernel.org
34 --- a/drivers/media/i2c/Kconfig
35 +++ b/drivers/media/i2c/Kconfig
36 @@ -631,6 +631,20 @@ config VIDEO_OV5695
37 To compile this driver as a module, choose M here: the
38 module will be called ov5695.
41 + tristate "OmniVision OV64A40 sensor support"
42 + depends on I2C && VIDEO_DEV
43 + select MEDIA_CONTROLLER
44 + select VIDEO_V4L2_SUBDEV_API
48 + This is a Video4Linux2 sensor driver for the OmniVision
51 + To compile this driver as a module, choose M here: the
52 + module will be called ov64a40.
55 tristate "OmniVision OV6650 sensor support"
56 depends on I2C && VIDEO_DEV
57 --- a/drivers/media/i2c/Makefile
58 +++ b/drivers/media/i2c/Makefile
59 @@ -96,6 +96,7 @@ obj-$(CONFIG_VIDEO_OV5670) += ov5670.o
60 obj-$(CONFIG_VIDEO_OV5675) += ov5675.o
61 obj-$(CONFIG_VIDEO_OV5693) += ov5693.o
62 obj-$(CONFIG_VIDEO_OV5695) += ov5695.o
63 +obj-$(CONFIG_VIDEO_OV64A40) += ov64a40.o
64 obj-$(CONFIG_VIDEO_OV6650) += ov6650.o
65 obj-$(CONFIG_VIDEO_OV7251) += ov7251.o
66 obj-$(CONFIG_VIDEO_OV7640) += ov7640.o
68 +++ b/drivers/media/i2c/ov64a40.c
70 +// SPDX-License-Identifier: GPL-2.0
72 + * V4L2 sensor driver for OmniVision OV64A40
74 + * Copyright (C) 2023 Ideas On Board Oy
75 + * Copyright (C) 2023 Arducam
78 +#include <linux/clk.h>
79 +#include <linux/delay.h>
80 +#include <linux/gpio/consumer.h>
81 +#include <linux/i2c.h>
82 +#include <linux/mod_devicetable.h>
83 +#include <linux/module.h>
84 +#include <linux/pm_runtime.h>
85 +#include <linux/regulator/consumer.h>
87 +#include <media/v4l2-cci.h>
88 +#include <media/v4l2-ctrls.h>
89 +#include <media/v4l2-device.h>
90 +#include <media/v4l2-event.h>
91 +#include <media/v4l2-fwnode.h>
92 +#include <media/v4l2-mediabus.h>
93 +#include <media/v4l2-subdev.h>
95 +#define OV64A40_XCLK_FREQ 24000000
97 +#define OV64A40_NATIVE_WIDTH 9286
98 +#define OV64A40_NATIVE_HEIGHT 6976
99 +#define OV64A40_PIXEL_ARRAY_TOP 0
100 +#define OV64A40_PIXEL_ARRAY_LEFT 0
101 +#define OV64A40_PIXEL_ARRAY_WIDTH 9248
102 +#define OV64A40_PIXEL_ARRAY_HEIGHT 6944
104 +#define OV64A40_PIXEL_RATE 300000000
106 +#define OV64A40_LINK_FREQ_360M 360000000
107 +#define OV64A40_LINK_FREQ_456M 456000000
109 +#define OV64A40_PLL1_PRE_DIV0 CCI_REG8(0x0301)
110 +#define OV64A40_PLL1_PRE_DIV CCI_REG8(0x0303)
111 +#define OV64A40_PLL1_MULTIPLIER CCI_REG16(0x0304)
112 +#define OV64A40_PLL1_M_DIV CCI_REG8(0x0307)
113 +#define OV64A40_PLL2_SEL_BAK_SA1 CCI_REG8(0x0320)
114 +#define OV64A40_PLL2_PRE_DIV CCI_REG8(0x0323)
115 +#define OV64A40_PLL2_MULTIPLIER CCI_REG16(0x0324)
116 +#define OV64A40_PLL2_PRE_DIV0 CCI_REG8(0x0326)
117 +#define OV64A40_PLL2_DIVDAC CCI_REG8(0x0329)
118 +#define OV64A40_PLL2_DIVSP CCI_REG8(0x032d)
119 +#define OV64A40_PLL2_DACPREDIV CCI_REG8(0x032e)
121 +/* TODO: validate vblank_min, it's not characterized in the datasheet. */
122 +#define OV64A40_VBLANK_MIN 128
123 +#define OV64A40_VTS_MAX 0xffffff
125 +#define OV64A40_REG_MEC_LONG_EXPO CCI_REG24(0x3500)
126 +#define OV64A40_EXPOSURE_MIN 16
127 +#define OV64A40_EXPOSURE_MARGIN 32
129 +#define OV64A40_REG_MEC_LONG_GAIN CCI_REG16(0x3508)
130 +#define OV64A40_ANA_GAIN_MIN 0x80
131 +#define OV64A40_ANA_GAIN_MAX 0x7ff
132 +#define OV64A40_ANA_GAIN_DEFAULT 0x80
134 +#define OV64A40_REG_TIMING_CTRL0 CCI_REG16(0x3800)
135 +#define OV64A40_REG_TIMING_CTRL2 CCI_REG16(0x3802)
136 +#define OV64A40_REG_TIMING_CTRL4 CCI_REG16(0x3804)
137 +#define OV64A40_REG_TIMING_CTRL6 CCI_REG16(0x3806)
138 +#define OV64A40_REG_TIMING_CTRL8 CCI_REG16(0x3808)
139 +#define OV64A40_REG_TIMING_CTRLA CCI_REG16(0x380a)
140 +#define OV64A40_REG_TIMING_CTRLC CCI_REG16(0x380c)
141 +#define OV64A40_REG_TIMING_CTRLE CCI_REG16(0x380e)
142 +#define OV64A40_REG_TIMING_CTRL10 CCI_REG16(0x3810)
143 +#define OV64A40_REG_TIMING_CTRL12 CCI_REG16(0x3812)
146 + * Careful: a typo in the datasheet calls this register
147 + * OV64A40_REG_TIMING_CTRL20.
149 +#define OV64A40_REG_TIMING_CTRL14 CCI_REG8(0x3814)
150 +#define OV64A40_REG_TIMING_CTRL15 CCI_REG8(0x3815)
151 +#define OV64A40_ODD_INC_SHIFT 4
152 +#define OV64A40_SKIPPING_CONFIG(_odd, _even) \
153 + (((_odd) << OV64A40_ODD_INC_SHIFT) | (_even))
155 +#define OV64A40_REG_TIMING_CTRL_20 CCI_REG8(0x3820)
156 +#define OV64A40_TIMING_CTRL_20_VFLIP BIT(2)
157 +#define OV64A40_TIMING_CTRL_20_VBIN BIT(1)
159 +#define OV64A40_REG_TIMING_CTRL_21 CCI_REG8(0x3821)
160 +#define OV64A40_TIMING_CTRL_21_HBIN BIT(4)
161 +#define OV64A40_TIMING_CTRL_21_HFLIP BIT(2)
162 +#define OV64A40_TIMING_CTRL_21_DSPEED BIT(0)
163 +#define OV64A40_TIMING_CTRL_21_HBIN_CONF \
164 + (OV64A40_TIMING_CTRL_21_HBIN | \
165 + OV64A40_TIMING_CTRL_21_DSPEED)
167 +#define OV64A40_REG_TIMINGS_VTS_HIGH CCI_REG8(0x3840)
168 +#define OV64A40_REG_TIMINGS_VTS_MID CCI_REG8(0x380e)
169 +#define OV64A40_REG_TIMINGS_VTS_LOW CCI_REG8(0x380f)
171 +/* The test pattern control is weirdly named PRE_ISP_2325_D2V2_TOP_1 in TRM. */
172 +#define OV64A40_REG_TEST_PATTERN CCI_REG8(0x50c1)
173 +#define OV64A40_TEST_PATTERN_DISABLED 0x00
174 +#define OV64A40_TEST_PATTERN_TYPE1 BIT(0)
175 +#define OV64A40_TEST_PATTERN_TYPE2 (BIT(4) | BIT(0))
176 +#define OV64A40_TEST_PATTERN_TYPE3 (BIT(5) | BIT(0))
177 +#define OV64A40_TEST_PATTERN_TYPE4 (BIT(5) | BIT(4) | BIT(0))
179 +#define OV64A40_REG_CHIP_ID CCI_REG24(0x300a)
180 +#define OV64A40_CHIP_ID 0x566441
182 +#define OV64A40_REG_SMIA CCI_REG8(0x0100)
183 +#define OV64A40_REG_SMIA_STREAMING BIT(0)
185 +enum ov64a40_link_freq_ids {
186 + OV64A40_LINK_FREQ_456M_ID,
187 + OV64A40_LINK_FREQ_360M_ID,
188 + OV64A40_NUM_LINK_FREQ,
191 +static const char * const ov64a40_supply_names[] = {
192 + /* Supplies can be enabled in any order */
193 + "avdd", /* Analog (2.8V) supply */
194 + "dovdd", /* Digital Core (1.8V) supply */
195 + "dvdd", /* IF (1.1V) supply */
198 +static const char * const ov64a40_test_pattern_menu[] = {
206 +static const int ov64a40_test_pattern_val[] = {
207 + OV64A40_TEST_PATTERN_DISABLED,
208 + OV64A40_TEST_PATTERN_TYPE1,
209 + OV64A40_TEST_PATTERN_TYPE2,
210 + OV64A40_TEST_PATTERN_TYPE3,
211 + OV64A40_TEST_PATTERN_TYPE4,
214 +static const unsigned int ov64a40_mbus_codes[] = {
215 + MEDIA_BUS_FMT_SBGGR10_1X10,
216 + MEDIA_BUS_FMT_SGRBG10_1X10,
217 + MEDIA_BUS_FMT_SGBRG10_1X10,
218 + MEDIA_BUS_FMT_SRGGB10_1X10,
221 +static const struct cci_reg_sequence ov64a40_init[] = {
222 + { CCI_REG8(0x0103), 0x01 }, { CCI_REG8(0x0301), 0x88 },
223 + { CCI_REG8(0x0304), 0x00 }, { CCI_REG8(0x0305), 0x96 },
224 + { CCI_REG8(0x0306), 0x03 }, { CCI_REG8(0x0307), 0x00 },
225 + { CCI_REG8(0x0345), 0x2c }, { CCI_REG8(0x034a), 0x02 },
226 + { CCI_REG8(0x034b), 0x02 }, { CCI_REG8(0x0350), 0xc0 },
227 + { CCI_REG8(0x0360), 0x09 }, { CCI_REG8(0x3012), 0x31 },
228 + { CCI_REG8(0x3015), 0xf0 }, { CCI_REG8(0x3017), 0xf0 },
229 + { CCI_REG8(0x301d), 0xf6 }, { CCI_REG8(0x301e), 0xf1 },
230 + { CCI_REG8(0x3022), 0xf0 }, { CCI_REG8(0x3400), 0x08 },
231 + { CCI_REG8(0x3608), 0x41 }, { CCI_REG8(0x3421), 0x02 },
232 + { CCI_REG8(0x3500), 0x00 }, { CCI_REG8(0x3501), 0x00 },
233 + { CCI_REG8(0x3502), 0x18 }, { CCI_REG8(0x3504), 0x0c },
234 + { CCI_REG8(0x3508), 0x01 }, { CCI_REG8(0x3509), 0x00 },
235 + { CCI_REG8(0x350a), 0x01 }, { CCI_REG8(0x350b), 0x00 },
236 + { CCI_REG8(0x350b), 0x00 }, { CCI_REG8(0x3540), 0x00 },
237 + { CCI_REG8(0x3541), 0x00 }, { CCI_REG8(0x3542), 0x08 },
238 + { CCI_REG8(0x3548), 0x01 }, { CCI_REG8(0x3549), 0xa0 },
239 + { CCI_REG8(0x3549), 0x00 }, { CCI_REG8(0x3549), 0x00 },
240 + { CCI_REG8(0x3549), 0x00 }, { CCI_REG8(0x3580), 0x00 },
241 + { CCI_REG8(0x3581), 0x00 }, { CCI_REG8(0x3582), 0x04 },
242 + { CCI_REG8(0x3588), 0x01 }, { CCI_REG8(0x3589), 0xf0 },
243 + { CCI_REG8(0x3589), 0x00 }, { CCI_REG8(0x3589), 0x00 },
244 + { CCI_REG8(0x3589), 0x00 }, { CCI_REG8(0x360d), 0x83 },
245 + { CCI_REG8(0x3616), 0xa0 }, { CCI_REG8(0x3617), 0x31 },
246 + { CCI_REG8(0x3623), 0x10 }, { CCI_REG8(0x3633), 0x03 },
247 + { CCI_REG8(0x3634), 0x03 }, { CCI_REG8(0x3635), 0x77 },
248 + { CCI_REG8(0x3640), 0x19 }, { CCI_REG8(0x3641), 0x80 },
249 + { CCI_REG8(0x364d), 0x0f }, { CCI_REG8(0x3680), 0x80 },
250 + { CCI_REG8(0x3682), 0x00 }, { CCI_REG8(0x3683), 0x00 },
251 + { CCI_REG8(0x3684), 0x07 }, { CCI_REG8(0x3688), 0x01 },
252 + { CCI_REG8(0x3689), 0x08 }, { CCI_REG8(0x368a), 0x26 },
253 + { CCI_REG8(0x368b), 0xc8 }, { CCI_REG8(0x368e), 0x70 },
254 + { CCI_REG8(0x368f), 0x00 }, { CCI_REG8(0x3692), 0x04 },
255 + { CCI_REG8(0x3693), 0x00 }, { CCI_REG8(0x3696), 0xd1 },
256 + { CCI_REG8(0x3697), 0xe0 }, { CCI_REG8(0x3698), 0x80 },
257 + { CCI_REG8(0x3699), 0x2b }, { CCI_REG8(0x369a), 0x00 },
258 + { CCI_REG8(0x369d), 0x00 }, { CCI_REG8(0x369e), 0x14 },
259 + { CCI_REG8(0x369f), 0x20 }, { CCI_REG8(0x36a5), 0x80 },
260 + { CCI_REG8(0x36a6), 0x00 }, { CCI_REG8(0x36a7), 0x00 },
261 + { CCI_REG8(0x36a8), 0x00 }, { CCI_REG8(0x36b5), 0x17 },
262 + { CCI_REG8(0x3701), 0x30 }, { CCI_REG8(0x3706), 0x2b },
263 + { CCI_REG8(0x3709), 0x8d }, { CCI_REG8(0x370b), 0x4f },
264 + { CCI_REG8(0x3711), 0x00 }, { CCI_REG8(0x3712), 0x01 },
265 + { CCI_REG8(0x3713), 0x00 }, { CCI_REG8(0x3720), 0x08 },
266 + { CCI_REG8(0x3727), 0x22 }, { CCI_REG8(0x3728), 0x01 },
267 + { CCI_REG8(0x375e), 0x00 }, { CCI_REG8(0x3760), 0x08 },
268 + { CCI_REG8(0x3761), 0x10 }, { CCI_REG8(0x3762), 0x08 },
269 + { CCI_REG8(0x3765), 0x10 }, { CCI_REG8(0x3766), 0x18 },
270 + { CCI_REG8(0x376a), 0x08 }, { CCI_REG8(0x376b), 0x00 },
271 + { CCI_REG8(0x376d), 0x1b }, { CCI_REG8(0x3791), 0x2b },
272 + { CCI_REG8(0x3793), 0x2b }, { CCI_REG8(0x3795), 0x2b },
273 + { CCI_REG8(0x3797), 0x4f }, { CCI_REG8(0x3799), 0x4f },
274 + { CCI_REG8(0x379b), 0x4f }, { CCI_REG8(0x37a0), 0x22 },
275 + { CCI_REG8(0x37da), 0x04 }, { CCI_REG8(0x37f9), 0x02 },
276 + { CCI_REG8(0x37fa), 0x02 }, { CCI_REG8(0x37fb), 0x02 },
277 + { CCI_REG8(0x3814), 0x11 }, { CCI_REG8(0x3815), 0x11 },
278 + { CCI_REG8(0x3820), 0x40 }, { CCI_REG8(0x3821), 0x04 },
279 + { CCI_REG8(0x3822), 0x00 }, { CCI_REG8(0x3823), 0x04 },
280 + { CCI_REG8(0x3827), 0x08 }, { CCI_REG8(0x3828), 0x00 },
281 + { CCI_REG8(0x382a), 0x81 }, { CCI_REG8(0x382e), 0x70 },
282 + { CCI_REG8(0x3837), 0x10 }, { CCI_REG8(0x3839), 0x00 },
283 + { CCI_REG8(0x383b), 0x00 }, { CCI_REG8(0x383c), 0x00 },
284 + { CCI_REG8(0x383d), 0x10 }, { CCI_REG8(0x383f), 0x00 },
285 + { CCI_REG8(0x384c), 0x02 }, { CCI_REG8(0x384d), 0x8c },
286 + { CCI_REG8(0x3852), 0x00 }, { CCI_REG8(0x3856), 0x10 },
287 + { CCI_REG8(0x3857), 0x10 }, { CCI_REG8(0x3858), 0x20 },
288 + { CCI_REG8(0x3859), 0x20 }, { CCI_REG8(0x3894), 0x00 },
289 + { CCI_REG8(0x3895), 0x00 }, { CCI_REG8(0x3896), 0x00 },
290 + { CCI_REG8(0x3897), 0x00 }, { CCI_REG8(0x3900), 0x40 },
291 + { CCI_REG8(0x3aed), 0x6e }, { CCI_REG8(0x3af1), 0x73 },
292 + { CCI_REG8(0x3d86), 0x12 }, { CCI_REG8(0x3d87), 0x30 },
293 + { CCI_REG8(0x3d8c), 0xab }, { CCI_REG8(0x3d8d), 0xb0 },
294 + { CCI_REG8(0x3f00), 0x12 }, { CCI_REG8(0x3f00), 0x12 },
295 + { CCI_REG8(0x3f00), 0x12 }, { CCI_REG8(0x3f01), 0x03 },
296 + { CCI_REG8(0x4009), 0x01 }, { CCI_REG8(0x400e), 0xc6 },
297 + { CCI_REG8(0x400f), 0x00 }, { CCI_REG8(0x4010), 0x28 },
298 + { CCI_REG8(0x4011), 0x01 }, { CCI_REG8(0x4012), 0x0c },
299 + { CCI_REG8(0x4015), 0x00 }, { CCI_REG8(0x4016), 0x1f },
300 + { CCI_REG8(0x4017), 0x00 }, { CCI_REG8(0x4018), 0x07 },
301 + { CCI_REG8(0x401a), 0x40 }, { CCI_REG8(0x4028), 0x01 },
302 + { CCI_REG8(0x4504), 0x00 }, { CCI_REG8(0x4506), 0x01 },
303 + { CCI_REG8(0x4508), 0x00 }, { CCI_REG8(0x4509), 0x35 },
304 + { CCI_REG8(0x450a), 0x08 }, { CCI_REG8(0x450c), 0x00 },
305 + { CCI_REG8(0x450d), 0x20 }, { CCI_REG8(0x450e), 0x00 },
306 + { CCI_REG8(0x450f), 0x20 }, { CCI_REG8(0x451e), 0x00 },
307 + { CCI_REG8(0x451f), 0x00 }, { CCI_REG8(0x4523), 0x00 },
308 + { CCI_REG8(0x4526), 0x00 }, { CCI_REG8(0x4527), 0x18 },
309 + { CCI_REG8(0x4580), 0x01 }, { CCI_REG8(0x4583), 0x00 },
310 + { CCI_REG8(0x4584), 0x00 }, { CCI_REG8(0x45c0), 0xa1 },
311 + { CCI_REG8(0x4602), 0x08 }, { CCI_REG8(0x4603), 0x05 },
312 + { CCI_REG8(0x4606), 0x12 }, { CCI_REG8(0x4607), 0x30 },
313 + { CCI_REG8(0x460b), 0x00 }, { CCI_REG8(0x460d), 0x00 },
314 + { CCI_REG8(0x4640), 0x00 }, { CCI_REG8(0x4641), 0x24 },
315 + { CCI_REG8(0x4643), 0x08 }, { CCI_REG8(0x4645), 0x14 },
316 + { CCI_REG8(0x4648), 0x0a }, { CCI_REG8(0x4649), 0x06 },
317 + { CCI_REG8(0x464a), 0x00 }, { CCI_REG8(0x464b), 0x30 },
318 + { CCI_REG8(0x4800), 0x04 }, { CCI_REG8(0x4802), 0x02 },
319 + { CCI_REG8(0x480b), 0x10 }, { CCI_REG8(0x480c), 0x80 },
320 + { CCI_REG8(0x480e), 0x04 }, { CCI_REG8(0x480f), 0x32 },
321 + { CCI_REG8(0x481b), 0x12 }, { CCI_REG8(0x4833), 0x30 },
322 + { CCI_REG8(0x4837), 0x08 }, { CCI_REG8(0x484b), 0x27 },
323 + { CCI_REG8(0x4850), 0x42 }, { CCI_REG8(0x4851), 0xaa },
324 + { CCI_REG8(0x4860), 0x01 }, { CCI_REG8(0x4861), 0xec },
325 + { CCI_REG8(0x4862), 0x25 }, { CCI_REG8(0x4888), 0x00 },
326 + { CCI_REG8(0x4889), 0x03 }, { CCI_REG8(0x488c), 0x60 },
327 + { CCI_REG8(0x4910), 0x28 }, { CCI_REG8(0x4911), 0x01 },
328 + { CCI_REG8(0x4912), 0x0c }, { CCI_REG8(0x491a), 0x40 },
329 + { CCI_REG8(0x4915), 0x00 }, { CCI_REG8(0x4916), 0x0f },
330 + { CCI_REG8(0x4917), 0x00 }, { CCI_REG8(0x4918), 0x07 },
331 + { CCI_REG8(0x4a10), 0x28 }, { CCI_REG8(0x4a11), 0x01 },
332 + { CCI_REG8(0x4a12), 0x0c }, { CCI_REG8(0x4a1a), 0x40 },
333 + { CCI_REG8(0x4a15), 0x00 }, { CCI_REG8(0x4a16), 0x0f },
334 + { CCI_REG8(0x4a17), 0x00 }, { CCI_REG8(0x4a18), 0x07 },
335 + { CCI_REG8(0x4d00), 0x04 }, { CCI_REG8(0x4d01), 0x5a },
336 + { CCI_REG8(0x4d02), 0xbb }, { CCI_REG8(0x4d03), 0x84 },
337 + { CCI_REG8(0x4d04), 0xd1 }, { CCI_REG8(0x4d05), 0x68 },
338 + { CCI_REG8(0xc4fa), 0x10 }, { CCI_REG8(0x3b56), 0x0a },
339 + { CCI_REG8(0x3b57), 0x0a }, { CCI_REG8(0x3b58), 0x0c },
340 + { CCI_REG8(0x3b59), 0x10 }, { CCI_REG8(0x3a1d), 0x30 },
341 + { CCI_REG8(0x3a1e), 0x30 }, { CCI_REG8(0x3a21), 0x30 },
342 + { CCI_REG8(0x3a22), 0x30 }, { CCI_REG8(0x3992), 0x02 },
343 + { CCI_REG8(0x399e), 0x02 }, { CCI_REG8(0x39fb), 0x30 },
344 + { CCI_REG8(0x39fc), 0x30 }, { CCI_REG8(0x39fd), 0x30 },
345 + { CCI_REG8(0x39fe), 0x30 }, { CCI_REG8(0x3a6d), 0x83 },
346 + { CCI_REG8(0x3a5e), 0x83 }, { CCI_REG8(0xc500), 0x12 },
347 + { CCI_REG8(0xc501), 0x12 }, { CCI_REG8(0xc502), 0x12 },
348 + { CCI_REG8(0xc503), 0x12 }, { CCI_REG8(0xc505), 0x12 },
349 + { CCI_REG8(0xc506), 0x12 }, { CCI_REG8(0xc507), 0x12 },
350 + { CCI_REG8(0xc508), 0x12 }, { CCI_REG8(0x3a77), 0x12 },
351 + { CCI_REG8(0x3a73), 0x12 }, { CCI_REG8(0x3a7b), 0x12 },
352 + { CCI_REG8(0x3a7f), 0x12 }, { CCI_REG8(0x3b2e), 0x13 },
353 + { CCI_REG8(0x3b29), 0x13 }, { CCI_REG8(0xc439), 0x13 },
354 + { CCI_REG8(0xc469), 0x13 }, { CCI_REG8(0xc41c), 0x89 },
355 + { CCI_REG8(0x3618), 0x80 }, { CCI_REG8(0xc514), 0x51 },
356 + { CCI_REG8(0xc515), 0x2c }, { CCI_REG8(0xc516), 0x16 },
357 + { CCI_REG8(0xc517), 0x0d }, { CCI_REG8(0x3615), 0x7f },
358 + { CCI_REG8(0x3632), 0x99 }, { CCI_REG8(0x3642), 0x00 },
359 + { CCI_REG8(0x3645), 0x80 }, { CCI_REG8(0x3702), 0x2a },
360 + { CCI_REG8(0x3703), 0x2a }, { CCI_REG8(0x3708), 0x2f },
361 + { CCI_REG8(0x3721), 0x15 }, { CCI_REG8(0x3744), 0x28 },
362 + { CCI_REG8(0x3991), 0x0c }, { CCI_REG8(0x371d), 0x24 },
363 + { CCI_REG8(0x371f), 0x0c }, { CCI_REG8(0x374b), 0x03 },
364 + { CCI_REG8(0x37d0), 0x00 }, { CCI_REG8(0x391d), 0x55 },
365 + { CCI_REG8(0x391e), 0x52 }, { CCI_REG8(0x399d), 0x0c },
366 + { CCI_REG8(0x3a2f), 0x01 }, { CCI_REG8(0x3a30), 0x01 },
367 + { CCI_REG8(0x3a31), 0x01 }, { CCI_REG8(0x3a32), 0x01 },
368 + { CCI_REG8(0x3a34), 0x01 }, { CCI_REG8(0x3a35), 0x01 },
369 + { CCI_REG8(0x3a36), 0x01 }, { CCI_REG8(0x3a37), 0x01 },
370 + { CCI_REG8(0x3a43), 0x01 }, { CCI_REG8(0x3a44), 0x01 },
371 + { CCI_REG8(0x3a45), 0x01 }, { CCI_REG8(0x3a46), 0x01 },
372 + { CCI_REG8(0x3a48), 0x01 }, { CCI_REG8(0x3a49), 0x01 },
373 + { CCI_REG8(0x3a4a), 0x01 }, { CCI_REG8(0x3a4b), 0x01 },
374 + { CCI_REG8(0x3a50), 0x14 }, { CCI_REG8(0x3a54), 0x14 },
375 + { CCI_REG8(0x3a60), 0x20 }, { CCI_REG8(0x3a6f), 0x20 },
376 + { CCI_REG8(0x3ac5), 0x01 }, { CCI_REG8(0x3ac6), 0x01 },
377 + { CCI_REG8(0x3ac7), 0x01 }, { CCI_REG8(0x3ac8), 0x01 },
378 + { CCI_REG8(0x3ac9), 0x01 }, { CCI_REG8(0x3aca), 0x01 },
379 + { CCI_REG8(0x3acb), 0x01 }, { CCI_REG8(0x3acc), 0x01 },
380 + { CCI_REG8(0x3acd), 0x01 }, { CCI_REG8(0x3ace), 0x01 },
381 + { CCI_REG8(0x3acf), 0x01 }, { CCI_REG8(0x3ad0), 0x01 },
382 + { CCI_REG8(0x3ad1), 0x01 }, { CCI_REG8(0x3ad2), 0x01 },
383 + { CCI_REG8(0x3ad3), 0x01 }, { CCI_REG8(0x3ad4), 0x01 },
384 + { CCI_REG8(0x3add), 0x1f }, { CCI_REG8(0x3adf), 0x24 },
385 + { CCI_REG8(0x3aef), 0x1f }, { CCI_REG8(0x3af0), 0x24 },
386 + { CCI_REG8(0x3b92), 0x08 }, { CCI_REG8(0x3b93), 0x08 },
387 + { CCI_REG8(0x3b94), 0x08 }, { CCI_REG8(0x3b95), 0x08 },
388 + { CCI_REG8(0x3be7), 0x1e }, { CCI_REG8(0x3be8), 0x26 },
389 + { CCI_REG8(0xc44a), 0x20 }, { CCI_REG8(0xc44c), 0x20 },
390 + { CCI_REG8(0xc483), 0x00 }, { CCI_REG8(0xc484), 0x00 },
391 + { CCI_REG8(0xc485), 0x00 }, { CCI_REG8(0xc486), 0x00 },
392 + { CCI_REG8(0xc487), 0x01 }, { CCI_REG8(0xc488), 0x01 },
393 + { CCI_REG8(0xc489), 0x01 }, { CCI_REG8(0xc48a), 0x01 },
394 + { CCI_REG8(0xc4c1), 0x00 }, { CCI_REG8(0xc4c2), 0x00 },
395 + { CCI_REG8(0xc4c3), 0x00 }, { CCI_REG8(0xc4c4), 0x00 },
396 + { CCI_REG8(0xc4c6), 0x10 }, { CCI_REG8(0xc4c7), 0x10 },
397 + { CCI_REG8(0xc4c8), 0x10 }, { CCI_REG8(0xc4c9), 0x10 },
398 + { CCI_REG8(0xc4ca), 0x10 }, { CCI_REG8(0xc4cb), 0x10 },
399 + { CCI_REG8(0xc4cc), 0x10 }, { CCI_REG8(0xc4cd), 0x10 },
400 + { CCI_REG8(0xc4ea), 0x07 }, { CCI_REG8(0xc4eb), 0x07 },
401 + { CCI_REG8(0xc4ec), 0x07 }, { CCI_REG8(0xc4ed), 0x07 },
402 + { CCI_REG8(0xc4ee), 0x07 }, { CCI_REG8(0xc4f6), 0x10 },
403 + { CCI_REG8(0xc4f7), 0x10 }, { CCI_REG8(0xc4f8), 0x10 },
404 + { CCI_REG8(0xc4f9), 0x10 }, { CCI_REG8(0xc518), 0x0e },
405 + { CCI_REG8(0xc519), 0x0e }, { CCI_REG8(0xc51a), 0x0e },
406 + { CCI_REG8(0xc51b), 0x0e }, { CCI_REG8(0xc51c), 0x0e },
407 + { CCI_REG8(0xc51d), 0x0e }, { CCI_REG8(0xc51e), 0x0e },
408 + { CCI_REG8(0xc51f), 0x0e }, { CCI_REG8(0xc520), 0x0e },
409 + { CCI_REG8(0xc521), 0x0e }, { CCI_REG8(0xc522), 0x0e },
410 + { CCI_REG8(0xc523), 0x0e }, { CCI_REG8(0xc524), 0x0e },
411 + { CCI_REG8(0xc525), 0x0e }, { CCI_REG8(0xc526), 0x0e },
412 + { CCI_REG8(0xc527), 0x0e }, { CCI_REG8(0xc528), 0x0e },
413 + { CCI_REG8(0xc529), 0x0e }, { CCI_REG8(0xc52a), 0x0e },
414 + { CCI_REG8(0xc52b), 0x0e }, { CCI_REG8(0xc52c), 0x0e },
415 + { CCI_REG8(0xc52d), 0x0e }, { CCI_REG8(0xc52e), 0x0e },
416 + { CCI_REG8(0xc52f), 0x0e }, { CCI_REG8(0xc530), 0x0e },
417 + { CCI_REG8(0xc531), 0x0e }, { CCI_REG8(0xc532), 0x0e },
418 + { CCI_REG8(0xc533), 0x0e }, { CCI_REG8(0xc534), 0x0e },
419 + { CCI_REG8(0xc535), 0x0e }, { CCI_REG8(0xc536), 0x0e },
420 + { CCI_REG8(0xc537), 0x0e }, { CCI_REG8(0xc538), 0x0e },
421 + { CCI_REG8(0xc539), 0x0e }, { CCI_REG8(0xc53a), 0x0e },
422 + { CCI_REG8(0xc53b), 0x0e }, { CCI_REG8(0xc53c), 0x0e },
423 + { CCI_REG8(0xc53d), 0x0e }, { CCI_REG8(0xc53e), 0x0e },
424 + { CCI_REG8(0xc53f), 0x0e }, { CCI_REG8(0xc540), 0x0e },
425 + { CCI_REG8(0xc541), 0x0e }, { CCI_REG8(0xc542), 0x0e },
426 + { CCI_REG8(0xc543), 0x0e }, { CCI_REG8(0xc544), 0x0e },
427 + { CCI_REG8(0xc545), 0x0e }, { CCI_REG8(0xc546), 0x0e },
428 + { CCI_REG8(0xc547), 0x0e }, { CCI_REG8(0xc548), 0x0e },
429 + { CCI_REG8(0xc549), 0x0e }, { CCI_REG8(0xc57f), 0x22 },
430 + { CCI_REG8(0xc580), 0x22 }, { CCI_REG8(0xc581), 0x22 },
431 + { CCI_REG8(0xc582), 0x22 }, { CCI_REG8(0xc583), 0x22 },
432 + { CCI_REG8(0xc584), 0x22 }, { CCI_REG8(0xc585), 0x22 },
433 + { CCI_REG8(0xc586), 0x22 }, { CCI_REG8(0xc587), 0x22 },
434 + { CCI_REG8(0xc588), 0x22 }, { CCI_REG8(0xc589), 0x22 },
435 + { CCI_REG8(0xc58a), 0x22 }, { CCI_REG8(0xc58b), 0x22 },
436 + { CCI_REG8(0xc58c), 0x22 }, { CCI_REG8(0xc58d), 0x22 },
437 + { CCI_REG8(0xc58e), 0x22 }, { CCI_REG8(0xc58f), 0x22 },
438 + { CCI_REG8(0xc590), 0x22 }, { CCI_REG8(0xc591), 0x22 },
439 + { CCI_REG8(0xc592), 0x22 }, { CCI_REG8(0xc598), 0x22 },
440 + { CCI_REG8(0xc599), 0x22 }, { CCI_REG8(0xc59a), 0x22 },
441 + { CCI_REG8(0xc59b), 0x22 }, { CCI_REG8(0xc59c), 0x22 },
442 + { CCI_REG8(0xc59d), 0x22 }, { CCI_REG8(0xc59e), 0x22 },
443 + { CCI_REG8(0xc59f), 0x22 }, { CCI_REG8(0xc5a0), 0x22 },
444 + { CCI_REG8(0xc5a1), 0x22 }, { CCI_REG8(0xc5a2), 0x22 },
445 + { CCI_REG8(0xc5a3), 0x22 }, { CCI_REG8(0xc5a4), 0x22 },
446 + { CCI_REG8(0xc5a5), 0x22 }, { CCI_REG8(0xc5a6), 0x22 },
447 + { CCI_REG8(0xc5a7), 0x22 }, { CCI_REG8(0xc5a8), 0x22 },
448 + { CCI_REG8(0xc5a9), 0x22 }, { CCI_REG8(0xc5aa), 0x22 },
449 + { CCI_REG8(0xc5ab), 0x22 }, { CCI_REG8(0xc5b1), 0x2a },
450 + { CCI_REG8(0xc5b2), 0x2a }, { CCI_REG8(0xc5b3), 0x2a },
451 + { CCI_REG8(0xc5b4), 0x2a }, { CCI_REG8(0xc5b5), 0x2a },
452 + { CCI_REG8(0xc5b6), 0x2a }, { CCI_REG8(0xc5b7), 0x2a },
453 + { CCI_REG8(0xc5b8), 0x2a }, { CCI_REG8(0xc5b9), 0x2a },
454 + { CCI_REG8(0xc5ba), 0x2a }, { CCI_REG8(0xc5bb), 0x2a },
455 + { CCI_REG8(0xc5bc), 0x2a }, { CCI_REG8(0xc5bd), 0x2a },
456 + { CCI_REG8(0xc5be), 0x2a }, { CCI_REG8(0xc5bf), 0x2a },
457 + { CCI_REG8(0xc5c0), 0x2a }, { CCI_REG8(0xc5c1), 0x2a },
458 + { CCI_REG8(0xc5c2), 0x2a }, { CCI_REG8(0xc5c3), 0x2a },
459 + { CCI_REG8(0xc5c4), 0x2a }, { CCI_REG8(0xc5ca), 0x2a },
460 + { CCI_REG8(0xc5cb), 0x2a }, { CCI_REG8(0xc5cc), 0x2a },
461 + { CCI_REG8(0xc5cd), 0x2a }, { CCI_REG8(0xc5ce), 0x2a },
462 + { CCI_REG8(0xc5cf), 0x2a }, { CCI_REG8(0xc5d0), 0x2a },
463 + { CCI_REG8(0xc5d1), 0x2a }, { CCI_REG8(0xc5d2), 0x2a },
464 + { CCI_REG8(0xc5d3), 0x2a }, { CCI_REG8(0xc5d4), 0x2a },
465 + { CCI_REG8(0xc5d5), 0x2a }, { CCI_REG8(0xc5d6), 0x2a },
466 + { CCI_REG8(0xc5d7), 0x2a }, { CCI_REG8(0xc5d8), 0x2a },
467 + { CCI_REG8(0xc5d9), 0x2a }, { CCI_REG8(0xc5da), 0x2a },
468 + { CCI_REG8(0xc5db), 0x2a }, { CCI_REG8(0xc5dc), 0x2a },
469 + { CCI_REG8(0xc5dd), 0x2a }, { CCI_REG8(0xc5e8), 0x22 },
470 + { CCI_REG8(0xc5ea), 0x22 }, { CCI_REG8(0x4540), 0x12 },
471 + { CCI_REG8(0x4541), 0x30 }, { CCI_REG8(0x3d86), 0x12 },
472 + { CCI_REG8(0x3d87), 0x30 }, { CCI_REG8(0x4606), 0x12 },
473 + { CCI_REG8(0x4607), 0x30 }, { CCI_REG8(0x4648), 0x0a },
474 + { CCI_REG8(0x4649), 0x06 }, { CCI_REG8(0x3220), 0x12 },
475 + { CCI_REG8(0x3221), 0x30 }, { CCI_REG8(0x40c2), 0x12 },
476 + { CCI_REG8(0x49c2), 0x12 }, { CCI_REG8(0x4ac2), 0x12 },
477 + { CCI_REG8(0x40c3), 0x30 }, { CCI_REG8(0x49c3), 0x30 },
478 + { CCI_REG8(0x4ac3), 0x30 }, { CCI_REG8(0x36b0), 0x12 },
479 + { CCI_REG8(0x36b1), 0x30 }, { CCI_REG8(0x45cb), 0x12 },
480 + { CCI_REG8(0x45cc), 0x30 }, { CCI_REG8(0x4585), 0x12 },
481 + { CCI_REG8(0x4586), 0x30 }, { CCI_REG8(0x36b2), 0x12 },
482 + { CCI_REG8(0x36b3), 0x30 }, { CCI_REG8(0x5a40), 0x75 },
483 + { CCI_REG8(0x5a41), 0x75 }, { CCI_REG8(0x5a42), 0x75 },
484 + { CCI_REG8(0x5a43), 0x75 }, { CCI_REG8(0x5a44), 0x75 },
485 + { CCI_REG8(0x5a45), 0x75 }, { CCI_REG8(0x5a46), 0x75 },
486 + { CCI_REG8(0x5a47), 0x75 }, { CCI_REG8(0x5a48), 0x75 },
487 + { CCI_REG8(0x5a49), 0x75 }, { CCI_REG8(0x5a4a), 0x75 },
488 + { CCI_REG8(0x5a4b), 0x75 }, { CCI_REG8(0x5a4c), 0x75 },
489 + { CCI_REG8(0x5a4d), 0x75 }, { CCI_REG8(0x5a4e), 0x75 },
490 + { CCI_REG8(0x5a4f), 0x75 }, { CCI_REG8(0x5a50), 0x75 },
491 + { CCI_REG8(0x5a51), 0x75 }, { CCI_REG8(0x5a52), 0x75 },
492 + { CCI_REG8(0x5a53), 0x75 }, { CCI_REG8(0x5a54), 0x75 },
493 + { CCI_REG8(0x5a55), 0x75 }, { CCI_REG8(0x5a56), 0x75 },
494 + { CCI_REG8(0x5a57), 0x75 }, { CCI_REG8(0x5a58), 0x75 },
495 + { CCI_REG8(0x5a59), 0x75 }, { CCI_REG8(0x5a5a), 0x75 },
496 + { CCI_REG8(0x5a5b), 0x75 }, { CCI_REG8(0x5a5c), 0x75 },
497 + { CCI_REG8(0x5a5d), 0x75 }, { CCI_REG8(0x5a5e), 0x75 },
498 + { CCI_REG8(0x5a5f), 0x75 }, { CCI_REG8(0x5a60), 0x75 },
499 + { CCI_REG8(0x5a61), 0x75 }, { CCI_REG8(0x5a62), 0x75 },
500 + { CCI_REG8(0x5a63), 0x75 }, { CCI_REG8(0x5a64), 0x75 },
501 + { CCI_REG8(0x5a65), 0x75 }, { CCI_REG8(0x5a66), 0x75 },
502 + { CCI_REG8(0x5a67), 0x75 }, { CCI_REG8(0x5a68), 0x75 },
503 + { CCI_REG8(0x5a69), 0x75 }, { CCI_REG8(0x5a6a), 0x75 },
504 + { CCI_REG8(0x5a6b), 0x75 }, { CCI_REG8(0x5a6c), 0x75 },
505 + { CCI_REG8(0x5a6d), 0x75 }, { CCI_REG8(0x5a6e), 0x75 },
506 + { CCI_REG8(0x5a6f), 0x75 }, { CCI_REG8(0x5a70), 0x75 },
507 + { CCI_REG8(0x5a71), 0x75 }, { CCI_REG8(0x5a72), 0x75 },
508 + { CCI_REG8(0x5a73), 0x75 }, { CCI_REG8(0x5a74), 0x75 },
509 + { CCI_REG8(0x5a75), 0x75 }, { CCI_REG8(0x5a76), 0x75 },
510 + { CCI_REG8(0x5a77), 0x75 }, { CCI_REG8(0x5a78), 0x75 },
511 + { CCI_REG8(0x5a79), 0x75 }, { CCI_REG8(0x5a7a), 0x75 },
512 + { CCI_REG8(0x5a7b), 0x75 }, { CCI_REG8(0x5a7c), 0x75 },
513 + { CCI_REG8(0x5a7d), 0x75 }, { CCI_REG8(0x5a7e), 0x75 },
514 + { CCI_REG8(0x5a7f), 0x75 }, { CCI_REG8(0x5a80), 0x75 },
515 + { CCI_REG8(0x5a81), 0x75 }, { CCI_REG8(0x5a82), 0x75 },
516 + { CCI_REG8(0x5a83), 0x75 }, { CCI_REG8(0x5a84), 0x75 },
517 + { CCI_REG8(0x5a85), 0x75 }, { CCI_REG8(0x5a86), 0x75 },
518 + { CCI_REG8(0x5a87), 0x75 }, { CCI_REG8(0x5a88), 0x75 },
519 + { CCI_REG8(0x5a89), 0x75 }, { CCI_REG8(0x5a8a), 0x75 },
520 + { CCI_REG8(0x5a8b), 0x75 }, { CCI_REG8(0x5a8c), 0x75 },
521 + { CCI_REG8(0x5a8d), 0x75 }, { CCI_REG8(0x5a8e), 0x75 },
522 + { CCI_REG8(0x5a8f), 0x75 }, { CCI_REG8(0x5a90), 0x75 },
523 + { CCI_REG8(0x5a91), 0x75 }, { CCI_REG8(0x5a92), 0x75 },
524 + { CCI_REG8(0x5a93), 0x75 }, { CCI_REG8(0x5a94), 0x75 },
525 + { CCI_REG8(0x5a95), 0x75 }, { CCI_REG8(0x5a96), 0x75 },
526 + { CCI_REG8(0x5a97), 0x75 }, { CCI_REG8(0x5a98), 0x75 },
527 + { CCI_REG8(0x5a99), 0x75 }, { CCI_REG8(0x5a9a), 0x75 },
528 + { CCI_REG8(0x5a9b), 0x75 }, { CCI_REG8(0x5a9c), 0x75 },
529 + { CCI_REG8(0x5a9d), 0x75 }, { CCI_REG8(0x5a9e), 0x75 },
530 + { CCI_REG8(0x5a9f), 0x75 }, { CCI_REG8(0x5aa0), 0x75 },
531 + { CCI_REG8(0x5aa1), 0x75 }, { CCI_REG8(0x5aa2), 0x75 },
532 + { CCI_REG8(0x5aa3), 0x75 }, { CCI_REG8(0x5aa4), 0x75 },
533 + { CCI_REG8(0x5aa5), 0x75 }, { CCI_REG8(0x5aa6), 0x75 },
534 + { CCI_REG8(0x5aa7), 0x75 }, { CCI_REG8(0x5aa8), 0x75 },
535 + { CCI_REG8(0x5aa9), 0x75 }, { CCI_REG8(0x5aaa), 0x75 },
536 + { CCI_REG8(0x5aab), 0x75 }, { CCI_REG8(0x5aac), 0x75 },
537 + { CCI_REG8(0x5aad), 0x75 }, { CCI_REG8(0x5aae), 0x75 },
538 + { CCI_REG8(0x5aaf), 0x75 }, { CCI_REG8(0x5ab0), 0x75 },
539 + { CCI_REG8(0x5ab1), 0x75 }, { CCI_REG8(0x5ab2), 0x75 },
540 + { CCI_REG8(0x5ab3), 0x75 }, { CCI_REG8(0x5ab4), 0x75 },
541 + { CCI_REG8(0x5ab5), 0x75 }, { CCI_REG8(0x5ab6), 0x75 },
542 + { CCI_REG8(0x5ab7), 0x75 }, { CCI_REG8(0x5ab8), 0x75 },
543 + { CCI_REG8(0x5ab9), 0x75 }, { CCI_REG8(0x5aba), 0x75 },
544 + { CCI_REG8(0x5abb), 0x75 }, { CCI_REG8(0x5abc), 0x75 },
545 + { CCI_REG8(0x5abd), 0x75 }, { CCI_REG8(0x5abe), 0x75 },
546 + { CCI_REG8(0x5abf), 0x75 }, { CCI_REG8(0x5ac0), 0x75 },
547 + { CCI_REG8(0x5ac1), 0x75 }, { CCI_REG8(0x5ac2), 0x75 },
548 + { CCI_REG8(0x5ac3), 0x75 }, { CCI_REG8(0x5ac4), 0x75 },
549 + { CCI_REG8(0x5ac5), 0x75 }, { CCI_REG8(0x5ac6), 0x75 },
550 + { CCI_REG8(0x5ac7), 0x75 }, { CCI_REG8(0x5ac8), 0x75 },
551 + { CCI_REG8(0x5ac9), 0x75 }, { CCI_REG8(0x5aca), 0x75 },
552 + { CCI_REG8(0x5acb), 0x75 }, { CCI_REG8(0x5acc), 0x75 },
553 + { CCI_REG8(0x5acd), 0x75 }, { CCI_REG8(0x5ace), 0x75 },
554 + { CCI_REG8(0x5acf), 0x75 }, { CCI_REG8(0x5ad0), 0x75 },
555 + { CCI_REG8(0x5ad1), 0x75 }, { CCI_REG8(0x5ad2), 0x75 },
556 + { CCI_REG8(0x5ad3), 0x75 }, { CCI_REG8(0x5ad4), 0x75 },
557 + { CCI_REG8(0x5ad5), 0x75 }, { CCI_REG8(0x5ad6), 0x75 },
558 + { CCI_REG8(0x5ad7), 0x75 }, { CCI_REG8(0x5ad8), 0x75 },
559 + { CCI_REG8(0x5ad9), 0x75 }, { CCI_REG8(0x5ada), 0x75 },
560 + { CCI_REG8(0x5adb), 0x75 }, { CCI_REG8(0x5adc), 0x75 },
561 + { CCI_REG8(0x5add), 0x75 }, { CCI_REG8(0x5ade), 0x75 },
562 + { CCI_REG8(0x5adf), 0x75 }, { CCI_REG8(0x5ae0), 0x75 },
563 + { CCI_REG8(0x5ae1), 0x75 }, { CCI_REG8(0x5ae2), 0x75 },
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951 + { CCI_REG8(0x5e09), 0x75 }, { CCI_REG8(0x5e0a), 0x75 },
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959 + { CCI_REG8(0x5e19), 0x75 }, { CCI_REG8(0x5e1a), 0x75 },
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967 + { CCI_REG8(0x5e29), 0x75 }, { CCI_REG8(0x5e2a), 0x75 },
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969 + { CCI_REG8(0x5e2d), 0x75 }, { CCI_REG8(0x5e2e), 0x75 },
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1411 + { CCI_REG8(0x7693), 0x00 }, { CCI_REG8(0x7694), 0x00 },
1412 + { CCI_REG8(0x7695), 0x00 }, { CCI_REG8(0x7696), 0x10 },
1413 + { CCI_REG8(0x7697), 0x00 }, { CCI_REG8(0x7698), 0x00 },
1414 + { CCI_REG8(0x7699), 0x00 }, { CCI_REG8(0x769a), 0x10 },
1415 + { CCI_REG8(0x769b), 0x00 }, { CCI_REG8(0x769c), 0x00 },
1416 + { CCI_REG8(0x769d), 0x00 }, { CCI_REG8(0x769e), 0x10 },
1417 + { CCI_REG8(0x769f), 0x00 }, { CCI_REG8(0x76a0), 0x00 },
1418 + { CCI_REG8(0x76a1), 0x00 }, { CCI_REG8(0x76a2), 0x10 },
1419 + { CCI_REG8(0x76a3), 0x00 }, { CCI_REG8(0x76a4), 0x00 },
1420 + { CCI_REG8(0x76a5), 0x00 }, { CCI_REG8(0x76a6), 0x10 },
1421 + { CCI_REG8(0x76a7), 0x00 }, { CCI_REG8(0x76a8), 0x00 },
1422 + { CCI_REG8(0x76a9), 0x00 }, { CCI_REG8(0x76aa), 0x10 },
1423 + { CCI_REG8(0x76ab), 0x00 }, { CCI_REG8(0x76ac), 0x00 },
1424 + { CCI_REG8(0x76ad), 0x00 }, { CCI_REG8(0x76ae), 0x10 },
1425 + { CCI_REG8(0x76af), 0x00 }, { CCI_REG8(0x76b0), 0x00 },
1426 + { CCI_REG8(0x76b1), 0x00 }, { CCI_REG8(0x76b2), 0x10 },
1427 + { CCI_REG8(0x76b3), 0x00 }, { CCI_REG8(0x76b4), 0x00 },
1428 + { CCI_REG8(0x76b5), 0x00 }, { CCI_REG8(0x76b6), 0x10 },
1429 + { CCI_REG8(0x76b7), 0x00 }, { CCI_REG8(0x76b8), 0x00 },
1430 + { CCI_REG8(0x76b9), 0x00 }, { CCI_REG8(0x76ba), 0x10 },
1431 + { CCI_REG8(0x76bb), 0x00 }, { CCI_REG8(0x76bc), 0x00 },
1432 + { CCI_REG8(0x76bd), 0x00 }, { CCI_REG8(0x76be), 0x10 },
1433 + { CCI_REG8(0x76bf), 0x00 }, { CCI_REG8(0x76c0), 0x00 },
1434 + { CCI_REG8(0x76c1), 0x00 }, { CCI_REG8(0x76c2), 0x10 },
1435 + { CCI_REG8(0x76c3), 0x00 }, { CCI_REG8(0x76c4), 0x00 },
1436 + { CCI_REG8(0x76c5), 0x00 }, { CCI_REG8(0x76c6), 0x10 },
1437 + { CCI_REG8(0x76c7), 0x00 }, { CCI_REG8(0x76c8), 0x00 },
1438 + { CCI_REG8(0x76c9), 0x00 }, { CCI_REG8(0x76ca), 0x10 },
1439 + { CCI_REG8(0x76cb), 0x00 }, { CCI_REG8(0x76cc), 0x00 },
1440 + { CCI_REG8(0x76cd), 0x00 }, { CCI_REG8(0x76ce), 0x10 },
1441 + { CCI_REG8(0x76cf), 0x00 }, { CCI_REG8(0x76d0), 0x00 },
1442 + { CCI_REG8(0x76d1), 0x00 }, { CCI_REG8(0x76d2), 0x10 },
1443 + { CCI_REG8(0x76d3), 0x00 }, { CCI_REG8(0x76d4), 0x00 },
1444 + { CCI_REG8(0x76d5), 0x00 }, { CCI_REG8(0x76d6), 0x10 },
1445 + { CCI_REG8(0x76d7), 0x00 }, { CCI_REG8(0x76d8), 0x00 },
1446 + { CCI_REG8(0x76d9), 0x00 }, { CCI_REG8(0x76da), 0x10 },
1447 + { CCI_REG8(0x76db), 0x00 }, { CCI_REG8(0x76dc), 0x00 },
1448 + { CCI_REG8(0x76dd), 0x00 }, { CCI_REG8(0x76de), 0x10 },
1449 + { CCI_REG8(0x76df), 0x00 }, { CCI_REG8(0x76e0), 0x00 },
1450 + { CCI_REG8(0x76e1), 0x00 }, { CCI_REG8(0x76e2), 0x10 },
1451 + { CCI_REG8(0x76e3), 0x00 }, { CCI_REG8(0x76e4), 0x00 },
1452 + { CCI_REG8(0x76e5), 0x00 }, { CCI_REG8(0x76e6), 0x10 },
1453 + { CCI_REG8(0x76e7), 0x00 }, { CCI_REG8(0x76e8), 0x00 },
1454 + { CCI_REG8(0x76e9), 0x00 }, { CCI_REG8(0x76ea), 0x10 },
1455 + { CCI_REG8(0x76eb), 0x00 }, { CCI_REG8(0x76ec), 0x00 },
1456 + { CCI_REG8(0x76ed), 0x00 }, { CCI_REG8(0x76ee), 0x10 },
1457 + { CCI_REG8(0x76ef), 0x00 }, { CCI_REG8(0x76f0), 0x00 },
1458 + { CCI_REG8(0x76f1), 0x00 }, { CCI_REG8(0x76f2), 0x10 },
1459 + { CCI_REG8(0x76f3), 0x00 }, { CCI_REG8(0x76f4), 0x00 },
1460 + { CCI_REG8(0x76f5), 0x00 }, { CCI_REG8(0x76f6), 0x10 },
1461 + { CCI_REG8(0x76f7), 0x00 }, { CCI_REG8(0x76f8), 0x00 },
1462 + { CCI_REG8(0x76f9), 0x00 }, { CCI_REG8(0x76fa), 0x10 },
1463 + { CCI_REG8(0x76fb), 0x00 }, { CCI_REG8(0x76fc), 0x00 },
1464 + { CCI_REG8(0x76fd), 0x00 }, { CCI_REG8(0x76fe), 0x10 },
1465 + { CCI_REG8(0x76ff), 0x00 }, { CCI_REG8(0x7700), 0x00 },
1466 + { CCI_REG8(0x7701), 0x00 }, { CCI_REG8(0x7702), 0x10 },
1467 + { CCI_REG8(0x7703), 0x00 }, { CCI_REG8(0x7704), 0x00 },
1468 + { CCI_REG8(0x7705), 0x00 }, { CCI_REG8(0x7706), 0x10 },
1469 + { CCI_REG8(0x7707), 0x00 }, { CCI_REG8(0x7708), 0x00 },
1470 + { CCI_REG8(0x7709), 0x00 }, { CCI_REG8(0x770a), 0x10 },
1471 + { CCI_REG8(0x770b), 0x00 }, { CCI_REG8(0x770c), 0x00 },
1472 + { CCI_REG8(0x770d), 0x00 }, { CCI_REG8(0x770e), 0x10 },
1473 + { CCI_REG8(0x770f), 0x00 }, { CCI_REG8(0x7710), 0x00 },
1474 + { CCI_REG8(0x7711), 0x00 }, { CCI_REG8(0x7712), 0x10 },
1475 + { CCI_REG8(0x7713), 0x00 }, { CCI_REG8(0x7714), 0x00 },
1476 + { CCI_REG8(0x7715), 0x00 }, { CCI_REG8(0x7716), 0x10 },
1477 + { CCI_REG8(0x7717), 0x00 }, { CCI_REG8(0x7718), 0x00 },
1478 + { CCI_REG8(0x7719), 0x00 }, { CCI_REG8(0x771a), 0x10 },
1479 + { CCI_REG8(0x771b), 0x00 }, { CCI_REG8(0x771c), 0x00 },
1480 + { CCI_REG8(0x771d), 0x00 }, { CCI_REG8(0x771e), 0x10 },
1481 + { CCI_REG8(0x771f), 0x00 }, { CCI_REG8(0x7720), 0x00 },
1482 + { CCI_REG8(0x7721), 0x00 }, { CCI_REG8(0x7722), 0x10 },
1483 + { CCI_REG8(0x7723), 0x00 }, { CCI_REG8(0x7724), 0x00 },
1484 + { CCI_REG8(0x7725), 0x00 }, { CCI_REG8(0x7726), 0x10 },
1485 + { CCI_REG8(0x7727), 0x00 }, { CCI_REG8(0x7728), 0x00 },
1486 + { CCI_REG8(0x7729), 0x00 }, { CCI_REG8(0x772a), 0x10 },
1487 + { CCI_REG8(0x772b), 0x00 }, { CCI_REG8(0x772c), 0x00 },
1488 + { CCI_REG8(0x772d), 0x00 }, { CCI_REG8(0x772e), 0x10 },
1489 + { CCI_REG8(0x772f), 0x00 }, { CCI_REG8(0x7730), 0x00 },
1490 + { CCI_REG8(0x7731), 0x00 }, { CCI_REG8(0x7732), 0x10 },
1491 + { CCI_REG8(0x7733), 0x00 }, { CCI_REG8(0x7734), 0x00 },
1492 + { CCI_REG8(0x7735), 0x00 }, { CCI_REG8(0x7736), 0x10 },
1493 + { CCI_REG8(0x7737), 0x00 }, { CCI_REG8(0x7738), 0x00 },
1494 + { CCI_REG8(0x7739), 0x00 }, { CCI_REG8(0x773a), 0x10 },
1495 + { CCI_REG8(0x773b), 0x00 }, { CCI_REG8(0x773c), 0x00 },
1496 + { CCI_REG8(0x773d), 0x00 }, { CCI_REG8(0x773e), 0x10 },
1497 + { CCI_REG8(0x773f), 0x00 }, { CCI_REG8(0x7740), 0x00 },
1498 + { CCI_REG8(0x7741), 0x00 }, { CCI_REG8(0x7742), 0x10 },
1499 + { CCI_REG8(0x7743), 0x00 }, { CCI_REG8(0x3421), 0x02 },
1500 + { CCI_REG8(0x37d0), 0x00 }, { CCI_REG8(0x3632), 0x99 },
1501 + { CCI_REG8(0xc518), 0x1f }, { CCI_REG8(0xc519), 0x1f },
1502 + { CCI_REG8(0xc51a), 0x1f }, { CCI_REG8(0xc51b), 0x1f },
1503 + { CCI_REG8(0xc51c), 0x1f }, { CCI_REG8(0xc51d), 0x1f },
1504 + { CCI_REG8(0xc51e), 0x1f }, { CCI_REG8(0xc51f), 0x1f },
1505 + { CCI_REG8(0xc520), 0x1f }, { CCI_REG8(0xc521), 0x1f },
1506 + { CCI_REG8(0x3616), 0xa0 }, { CCI_REG8(0x3615), 0xc5 },
1507 + { CCI_REG8(0xc4c1), 0x02 }, { CCI_REG8(0xc4c2), 0x02 },
1508 + { CCI_REG8(0xc4c3), 0x03 }, { CCI_REG8(0xc4c4), 0x03 },
1509 + { CCI_REG8(0xc4f6), 0x0a }, { CCI_REG8(0xc4f7), 0x0a },
1510 + { CCI_REG8(0xc4f8), 0x0a }, { CCI_REG8(0xc4f9), 0x0a },
1511 + { CCI_REG8(0xc4fa), 0x0a }, { CCI_REG8(0xc4c6), 0x0a },
1512 + { CCI_REG8(0xc4c7), 0x0a }, { CCI_REG8(0xc4c8), 0x0a },
1513 + { CCI_REG8(0xc4c9), 0x0a }, { CCI_REG8(0xc4ca), 0x14 },
1514 + { CCI_REG8(0xc4cb), 0x14 }, { CCI_REG8(0xc4cc), 0x14 },
1515 + { CCI_REG8(0xc4cd), 0x14 }, { CCI_REG8(0x3b92), 0x05 },
1516 + { CCI_REG8(0x3b93), 0x05 }, { CCI_REG8(0x3b94), 0x05 },
1517 + { CCI_REG8(0x3b95), 0x05 }, { CCI_REG8(0x3623), 0x10 },
1518 + { CCI_REG8(0xc522), 0x18 }, { CCI_REG8(0xc523), 0x12 },
1519 + { CCI_REG8(0xc524), 0x0e }, { CCI_REG8(0xc525), 0x0b },
1520 + { CCI_REG8(0xc526), 0x18 }, { CCI_REG8(0xc527), 0x12 },
1521 + { CCI_REG8(0xc528), 0x0c }, { CCI_REG8(0xc529), 0x08 },
1522 + { CCI_REG8(0xc52a), 0x18 }, { CCI_REG8(0xc52b), 0x12 },
1523 + { CCI_REG8(0xc52c), 0x0e }, { CCI_REG8(0xc52d), 0x0b },
1524 + { CCI_REG8(0xc52e), 0x18 }, { CCI_REG8(0xc52f), 0x12 },
1525 + { CCI_REG8(0xc530), 0x0e }, { CCI_REG8(0xc531), 0x0b },
1526 + { CCI_REG8(0xc532), 0x18 }, { CCI_REG8(0xc533), 0x12 },
1527 + { CCI_REG8(0xc534), 0x0e }, { CCI_REG8(0xc535), 0x0b },
1528 + { CCI_REG8(0xc536), 0x18 }, { CCI_REG8(0xc537), 0x12 },
1529 + { CCI_REG8(0xc538), 0x0e }, { CCI_REG8(0xc539), 0x0b },
1530 + { CCI_REG8(0xc53a), 0x18 }, { CCI_REG8(0xc53b), 0x12 },
1531 + { CCI_REG8(0xc53c), 0x0c }, { CCI_REG8(0xc53d), 0x08 },
1532 + { CCI_REG8(0xc53e), 0x18 }, { CCI_REG8(0xc53f), 0x12 },
1533 + { CCI_REG8(0xc540), 0x0e }, { CCI_REG8(0xc541), 0x0b },
1534 + { CCI_REG8(0xc542), 0x18 }, { CCI_REG8(0xc543), 0x12 },
1535 + { CCI_REG8(0xc544), 0x0e }, { CCI_REG8(0xc545), 0x0b },
1536 + { CCI_REG8(0xc546), 0x18 }, { CCI_REG8(0xc547), 0x12 },
1537 + { CCI_REG8(0xc548), 0x0e }, { CCI_REG8(0xc549), 0x0b },
1538 + { CCI_REG8(0x3701), 0x18 }, { CCI_REG8(0x3702), 0x38 },
1539 + { CCI_REG8(0x3703), 0x72 }, { CCI_REG8(0x3708), 0x26 },
1540 + { CCI_REG8(0x3709), 0xe6 }, { CCI_REG8(0x3a1d), 0x18 },
1541 + { CCI_REG8(0x3a1e), 0x18 }, { CCI_REG8(0x3a21), 0x18 },
1542 + { CCI_REG8(0x3a22), 0x18 }, { CCI_REG8(0x39fb), 0x18 },
1543 + { CCI_REG8(0x39fc), 0x18 }, { CCI_REG8(0x39fd), 0x18 },
1544 + { CCI_REG8(0x39fe), 0x18 }, { CCI_REG8(0xc44a), 0x08 },
1545 + { CCI_REG8(0xc44c), 0x08 }, { CCI_REG8(0xc5e8), 0x0a },
1546 + { CCI_REG8(0xc5ea), 0x0a }, { CCI_REG8(0x391d), 0x54 },
1547 + { CCI_REG8(0x391e), 0xca }, { CCI_REG8(0x3991), 0x0c },
1548 + { CCI_REG8(0x399d), 0x0c }, { CCI_REG8(0x3744), 0x24 },
1549 + { CCI_REG8(0x374b), 0x0c }, { CCI_REG8(0x3be7), 0x1e },
1550 + { CCI_REG8(0x3be8), 0x26 }, { CCI_REG8(0x3a50), 0x14 },
1551 + { CCI_REG8(0x3a54), 0x14 }, { CCI_REG8(0x3add), 0x1f },
1552 + { CCI_REG8(0x3adf), 0x24 }, { CCI_REG8(0x3aef), 0x1f },
1553 + { CCI_REG8(0x3af0), 0x24 }, { CCI_REG8(0xc57f), 0x30 },
1554 + { CCI_REG8(0xc580), 0x30 }, { CCI_REG8(0xc581), 0x30 },
1555 + { CCI_REG8(0xc582), 0x30 }, { CCI_REG8(0xc583), 0x30 },
1556 + { CCI_REG8(0xc584), 0x30 }, { CCI_REG8(0xc585), 0x30 },
1557 + { CCI_REG8(0xc586), 0x30 }, { CCI_REG8(0xc587), 0x30 },
1558 + { CCI_REG8(0xc588), 0x30 }, { CCI_REG8(0xc589), 0x30 },
1559 + { CCI_REG8(0xc58a), 0x30 }, { CCI_REG8(0xc58b), 0x30 },
1560 + { CCI_REG8(0xc58c), 0x30 }, { CCI_REG8(0xc58d), 0x30 },
1561 + { CCI_REG8(0xc58e), 0x30 }, { CCI_REG8(0xc58f), 0x30 },
1562 + { CCI_REG8(0xc590), 0x30 }, { CCI_REG8(0xc591), 0x30 },
1563 + { CCI_REG8(0xc592), 0x30 }, { CCI_REG8(0xc598), 0x30 },
1564 + { CCI_REG8(0xc599), 0x30 }, { CCI_REG8(0xc59a), 0x30 },
1565 + { CCI_REG8(0xc59b), 0x30 }, { CCI_REG8(0xc59c), 0x30 },
1566 + { CCI_REG8(0xc59d), 0x30 }, { CCI_REG8(0xc59e), 0x30 },
1567 + { CCI_REG8(0xc59f), 0x30 }, { CCI_REG8(0xc5a0), 0x30 },
1568 + { CCI_REG8(0xc5a1), 0x30 }, { CCI_REG8(0xc5a2), 0x30 },
1569 + { CCI_REG8(0xc5a3), 0x30 }, { CCI_REG8(0xc5a4), 0x30 },
1570 + { CCI_REG8(0xc5a5), 0x30 }, { CCI_REG8(0xc5a6), 0x30 },
1571 + { CCI_REG8(0xc5a7), 0x30 }, { CCI_REG8(0xc5a8), 0x30 },
1572 + { CCI_REG8(0xc5a9), 0x30 }, { CCI_REG8(0xc5aa), 0x30 },
1573 + { CCI_REG8(0xc5ab), 0x30 }, { CCI_REG8(0xc5b1), 0x38 },
1574 + { CCI_REG8(0xc5b2), 0x38 }, { CCI_REG8(0xc5b3), 0x38 },
1575 + { CCI_REG8(0xc5b4), 0x38 }, { CCI_REG8(0xc5b5), 0x38 },
1576 + { CCI_REG8(0xc5b6), 0x38 }, { CCI_REG8(0xc5b7), 0x38 },
1577 + { CCI_REG8(0xc5b8), 0x38 }, { CCI_REG8(0xc5b9), 0x38 },
1578 + { CCI_REG8(0xc5ba), 0x38 }, { CCI_REG8(0xc5bb), 0x38 },
1579 + { CCI_REG8(0xc5bc), 0x38 }, { CCI_REG8(0xc5bd), 0x38 },
1580 + { CCI_REG8(0xc5be), 0x38 }, { CCI_REG8(0xc5bf), 0x38 },
1581 + { CCI_REG8(0xc5c0), 0x38 }, { CCI_REG8(0xc5c1), 0x38 },
1582 + { CCI_REG8(0xc5c2), 0x38 }, { CCI_REG8(0xc5c3), 0x38 },
1583 + { CCI_REG8(0xc5c4), 0x38 }, { CCI_REG8(0xc5ca), 0x38 },
1584 + { CCI_REG8(0xc5cb), 0x38 }, { CCI_REG8(0xc5cc), 0x38 },
1585 + { CCI_REG8(0xc5cd), 0x38 }, { CCI_REG8(0xc5ce), 0x38 },
1586 + { CCI_REG8(0xc5cf), 0x38 }, { CCI_REG8(0xc5d0), 0x38 },
1587 + { CCI_REG8(0xc5d1), 0x38 }, { CCI_REG8(0xc5d2), 0x38 },
1588 + { CCI_REG8(0xc5d3), 0x38 }, { CCI_REG8(0xc5d4), 0x38 },
1589 + { CCI_REG8(0xc5d5), 0x38 }, { CCI_REG8(0xc5d6), 0x38 },
1590 + { CCI_REG8(0xc5d7), 0x38 }, { CCI_REG8(0xc5d8), 0x38 },
1591 + { CCI_REG8(0xc5d9), 0x38 }, { CCI_REG8(0xc5da), 0x38 },
1592 + { CCI_REG8(0xc5db), 0x38 }, { CCI_REG8(0xc5dc), 0x38 },
1593 + { CCI_REG8(0xc5dd), 0x38 }, { CCI_REG8(0x3a60), 0x68 },
1594 + { CCI_REG8(0x3a6f), 0x68 }, { CCI_REG8(0x3a5e), 0xdc },
1595 + { CCI_REG8(0x3a6d), 0xdc }, { CCI_REG8(0x3aed), 0x6e },
1596 + { CCI_REG8(0x3af1), 0x73 }, { CCI_REG8(0x3992), 0x02 },
1597 + { CCI_REG8(0x399e), 0x02 }, { CCI_REG8(0x371d), 0x17 },
1598 + { CCI_REG8(0x371f), 0x08 }, { CCI_REG8(0x3721), 0xc9 },
1599 + { CCI_REG8(0x401e), 0x00 }, { CCI_REG8(0x401f), 0xf8 },
1600 + { CCI_REG8(0x3642), 0x00 }, { CCI_REG8(0x3641), 0x7f },
1601 + { CCI_REG8(0x3ac5), 0x0c }, { CCI_REG8(0x3ac6), 0x09 },
1602 + { CCI_REG8(0x3ac7), 0x06 }, { CCI_REG8(0x3ac8), 0x02 },
1603 + { CCI_REG8(0x3ac9), 0x0c }, { CCI_REG8(0x3aca), 0x09 },
1604 + { CCI_REG8(0x3acb), 0x06 }, { CCI_REG8(0x3acc), 0x02 },
1605 + { CCI_REG8(0x3acd), 0x0c }, { CCI_REG8(0x3ace), 0x09 },
1606 + { CCI_REG8(0x3acf), 0x07 }, { CCI_REG8(0x3ad0), 0x04 },
1607 + { CCI_REG8(0x3ad1), 0x0c }, { CCI_REG8(0x3ad2), 0x09 },
1608 + { CCI_REG8(0x3ad3), 0x07 }, { CCI_REG8(0x3ad4), 0x04 },
1609 + { CCI_REG8(0xc483), 0x0c }, { CCI_REG8(0xc484), 0x0c },
1610 + { CCI_REG8(0xc485), 0x0c }, { CCI_REG8(0xc486), 0x0c },
1611 + { CCI_REG8(0x3a2f), 0x0c }, { CCI_REG8(0x3a30), 0x09 },
1612 + { CCI_REG8(0x3a31), 0x06 }, { CCI_REG8(0x3a32), 0x02 },
1613 + { CCI_REG8(0x3a34), 0x0c }, { CCI_REG8(0x3a35), 0x09 },
1614 + { CCI_REG8(0x3a36), 0x07 }, { CCI_REG8(0x3a37), 0x04 },
1615 + { CCI_REG8(0x3a43), 0x0c }, { CCI_REG8(0x3a44), 0x09 },
1616 + { CCI_REG8(0x3a45), 0x06 }, { CCI_REG8(0x3a46), 0x02 },
1617 + { CCI_REG8(0x3a48), 0x0c }, { CCI_REG8(0x3a49), 0x09 },
1618 + { CCI_REG8(0x3a4a), 0x07 }, { CCI_REG8(0x3a4b), 0x04 },
1619 + { CCI_REG8(0xc487), 0x0c }, { CCI_REG8(0xc488), 0x0c },
1620 + { CCI_REG8(0xc489), 0x0c }, { CCI_REG8(0xc48a), 0x0c },
1621 + { CCI_REG8(0x3645), 0xbd }, { CCI_REG8(0x373f), 0x00 },
1622 + { CCI_REG8(0x374f), 0x10 }, { CCI_REG8(0x3743), 0xc6 },
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1839 + { CCI_REG8(0x3a45), 0xcd }, { CCI_REG8(0x3a46), 0xcd },
1840 + { CCI_REG8(0x3a47), 0xcd }, { CCI_REG8(0x3a48), 0xcd },
1841 + { CCI_REG8(0x3a49), 0xcd }, { CCI_REG8(0x3a4a), 0xcd },
1842 + { CCI_REG8(0x3a4b), 0xcd }, { CCI_REG8(0x3a4c), 0xcd },
1843 + { CCI_REG8(0x3a4d), 0xcd }, { CCI_REG8(0x3a4e), 0xcd },
1844 + { CCI_REG8(0x3a4f), 0xcd }, { CCI_REG8(0x3a50), 0xcd },
1845 + { CCI_REG8(0x3a51), 0xcd }, { CCI_REG8(0x3a52), 0xcd },
1846 + { CCI_REG8(0x3a53), 0xcd }, { CCI_REG8(0x3a54), 0xcd },
1847 + { CCI_REG8(0x3a55), 0xcd }, { CCI_REG8(0x3a56), 0xcd },
1848 + { CCI_REG8(0x3a57), 0xcd }, { CCI_REG8(0x3a58), 0xcd },
1849 + { CCI_REG8(0x3a59), 0xcd }, { CCI_REG8(0x3a5a), 0xcd },
1850 + { CCI_REG8(0x3a5b), 0xcd }, { CCI_REG8(0x3a5c), 0xcd },
1851 + { CCI_REG8(0x3a5d), 0xcd }, { CCI_REG8(0x3a5e), 0xcd },
1852 + { CCI_REG8(0x3a5f), 0xcd }, { CCI_REG8(0x3a60), 0xcd },
1853 + { CCI_REG8(0x3a61), 0xcd }, { CCI_REG8(0x3a62), 0xcd },
1854 + { CCI_REG8(0x3a63), 0xcd }, { CCI_REG8(0x3a64), 0xcd },
1855 + { CCI_REG8(0x3a65), 0xcd }, { CCI_REG8(0x3a66), 0xcd },
1856 + { CCI_REG8(0x3a67), 0xcd }, { CCI_REG8(0x3a68), 0xcd },
1857 + { CCI_REG8(0x3a69), 0xcd }, { CCI_REG8(0x3a6a), 0xcd },
1858 + { CCI_REG8(0x3a6b), 0xcd }, { CCI_REG8(0x3a6c), 0xcd },
1859 + { CCI_REG8(0x3a6d), 0xcd }, { CCI_REG8(0x3a6e), 0xcd },
1860 + { CCI_REG8(0x3a6f), 0xcd }, { CCI_REG8(0x3a70), 0xcd },
1861 + { CCI_REG8(0x3a71), 0xcd }, { CCI_REG8(0x3a72), 0xcd },
1862 + { CCI_REG8(0x3a73), 0xcd }, { CCI_REG8(0x3a74), 0xcd },
1863 + { CCI_REG8(0x3a75), 0xcd }, { CCI_REG8(0x3a76), 0xcd },
1864 + { CCI_REG8(0x3a77), 0xcd }, { CCI_REG8(0x3a78), 0xcd },
1865 + { CCI_REG8(0x3a79), 0xcd }, { CCI_REG8(0x3a7a), 0xcd },
1866 + { CCI_REG8(0x3a7b), 0xcd }, { CCI_REG8(0x3a7c), 0xcd },
1867 + { CCI_REG8(0x3a7d), 0xcd }, { CCI_REG8(0x3a7e), 0xcd },
1868 + { CCI_REG8(0x3a7f), 0xcd }, { CCI_REG8(0x3a80), 0xcd },
1869 + { CCI_REG8(0x3a81), 0xcd }, { CCI_REG8(0x3a82), 0xcd },
1870 + { CCI_REG8(0x3a83), 0xcd }, { CCI_REG8(0x3a84), 0xcd },
1871 + { CCI_REG8(0x3a85), 0xcd }, { CCI_REG8(0x3a86), 0xcd },
1872 + { CCI_REG8(0x3a87), 0xcd }, { CCI_REG8(0x3a88), 0xcd },
1873 + { CCI_REG8(0x3a89), 0xcd }, { CCI_REG8(0x3a8a), 0xcd },
1874 + { CCI_REG8(0x3a8b), 0xcd }, { CCI_REG8(0x3a8c), 0xcd },
1875 + { CCI_REG8(0x3a8d), 0xcd }, { CCI_REG8(0x3a8e), 0xcd },
1876 + { CCI_REG8(0x3a8f), 0xcd }, { CCI_REG8(0x3a90), 0xcd },
1877 + { CCI_REG8(0x3a91), 0xcd }, { CCI_REG8(0x3a92), 0xcd },
1878 + { CCI_REG8(0x3a93), 0xcd }, { CCI_REG8(0x3a94), 0xcd },
1879 + { CCI_REG8(0x3a95), 0x40 }, { CCI_REG8(0x3a96), 0x40 },
1880 + { CCI_REG8(0x3a97), 0x40 }, { CCI_REG8(0x3a98), 0x40 },
1881 + { CCI_REG8(0x3a99), 0x40 }, { CCI_REG8(0x3a9a), 0x40 },
1882 + { CCI_REG8(0x3a9b), 0x40 }, { CCI_REG8(0x3a9c), 0x40 },
1883 + { CCI_REG8(0x3a9d), 0x40 }, { CCI_REG8(0x3a9e), 0x40 },
1884 + { CCI_REG8(0x3a9f), 0x40 }, { CCI_REG8(0x3aa0), 0x40 },
1885 + { CCI_REG8(0x3aa1), 0x40 }, { CCI_REG8(0x3aa2), 0x40 },
1886 + { CCI_REG8(0x3aa3), 0x40 }, { CCI_REG8(0x3aa4), 0x40 },
1887 + { CCI_REG8(0x3aa5), 0x40 }, { CCI_REG8(0x3aa6), 0x40 },
1888 + { CCI_REG8(0x3aa7), 0x40 }, { CCI_REG8(0x3aa8), 0x40 },
1889 + { CCI_REG8(0x3aa9), 0x40 }, { CCI_REG8(0x3aaa), 0x40 },
1890 + { CCI_REG8(0x3aab), 0x40 }, { CCI_REG8(0x3aac), 0x40 },
1891 + { CCI_REG8(0x3aad), 0x40 }, { CCI_REG8(0x3aae), 0x40 },
1892 + { CCI_REG8(0x3aaf), 0x40 }, { CCI_REG8(0x3ab0), 0x40 },
1893 + { CCI_REG8(0x3ab1), 0x40 }, { CCI_REG8(0x3ab2), 0x40 },
1894 + { CCI_REG8(0x3ab3), 0x40 }, { CCI_REG8(0x3ab4), 0x40 },
1895 + { CCI_REG8(0x3ab5), 0x40 }, { CCI_REG8(0x3ab6), 0x40 },
1896 + { CCI_REG8(0x3ab7), 0x40 }, { CCI_REG8(0x3ab8), 0x40 },
1897 + { CCI_REG8(0x3ab9), 0x40 }, { CCI_REG8(0x3aba), 0x40 },
1898 + { CCI_REG8(0x3abb), 0x40 }, { CCI_REG8(0x3abc), 0x40 },
1899 + { CCI_REG8(0x3abd), 0x40 }, { CCI_REG8(0x3abe), 0x40 },
1900 + { CCI_REG8(0x3abf), 0x40 }, { CCI_REG8(0x3ac0), 0x40 },
1901 + { CCI_REG8(0x3ac1), 0x40 }, { CCI_REG8(0x3ac2), 0x40 },
1902 + { CCI_REG8(0x3ac3), 0x40 }, { CCI_REG8(0x3ac4), 0x40 },
1903 + { CCI_REG8(0x3ac5), 0x40 }, { CCI_REG8(0x3ac6), 0x40 },
1904 + { CCI_REG8(0x3ac7), 0x40 }, { CCI_REG8(0x3ac8), 0x40 },
1905 + { CCI_REG8(0x3ac9), 0x40 }, { CCI_REG8(0x3aca), 0x40 },
1906 + { CCI_REG8(0x3acb), 0x40 }, { CCI_REG8(0x3acc), 0x40 },
1907 + { CCI_REG8(0x3acd), 0x40 }, { CCI_REG8(0x3ace), 0x40 },
1908 + { CCI_REG8(0x3acf), 0x40 }, { CCI_REG8(0x3ad0), 0x40 },
1909 + { CCI_REG8(0x3ad1), 0x40 }, { CCI_REG8(0x3ad2), 0x40 },
1910 + { CCI_REG8(0x3ad3), 0x40 }, { CCI_REG8(0x3ad4), 0x40 },
1911 + { CCI_REG8(0x3ad5), 0x40 }, { CCI_REG8(0x3ad6), 0x40 },
1912 + { CCI_REG8(0x3ad7), 0x40 }, { CCI_REG8(0x3ad8), 0x40 },
1913 + { CCI_REG8(0x3ad9), 0x40 }, { CCI_REG8(0x3ada), 0x40 },
1914 + { CCI_REG8(0x3adb), 0x40 }, { CCI_REG8(0x3adc), 0x40 },
1915 + { CCI_REG8(0x3add), 0x40 }, { CCI_REG8(0x3ade), 0x40 },
1916 + { CCI_REG8(0x3adf), 0x40 }, { CCI_REG8(0x3ae0), 0x40 },
1917 + { CCI_REG8(0x3ae1), 0x40 }, { CCI_REG8(0x3ae2), 0x40 },
1918 + { CCI_REG8(0x3ae3), 0x40 }, { CCI_REG8(0x3ae4), 0x40 },
1919 + { CCI_REG8(0x3ae5), 0x40 }, { CCI_REG8(0x3ae6), 0x40 },
1920 + { CCI_REG8(0x3ae7), 0x40 }, { CCI_REG8(0x3ae8), 0x40 },
1921 + { CCI_REG8(0x3ae9), 0x40 }, { CCI_REG8(0x3aea), 0x40 },
1922 + { CCI_REG8(0x3aeb), 0x40 }, { CCI_REG8(0x3aec), 0x40 },
1923 + { CCI_REG8(0x3aed), 0x40 }, { CCI_REG8(0x3aee), 0x40 },
1924 + { CCI_REG8(0x3aef), 0xcd }, { CCI_REG8(0x3af0), 0xcd },
1925 + { CCI_REG8(0x3af1), 0xcd }, { CCI_REG8(0x3af2), 0xcd },
1926 + { CCI_REG8(0x3af3), 0xcd }, { CCI_REG8(0x3af4), 0xcd },
1927 + { CCI_REG8(0x3af5), 0xcd }, { CCI_REG8(0x3af6), 0xcd },
1928 + { CCI_REG8(0x3af7), 0xcd }, { CCI_REG8(0x3af8), 0xcd },
1929 + { CCI_REG8(0x3af9), 0xcd }, { CCI_REG8(0x3afa), 0xcd },
1930 + { CCI_REG8(0x3afb), 0xcd }, { CCI_REG8(0x3afc), 0xcd },
1931 + { CCI_REG8(0x3afd), 0xcd }, { CCI_REG8(0x3afe), 0xcd },
1932 + { CCI_REG8(0x3aff), 0xcd }, { CCI_REG8(0x3b00), 0xcd },
1933 + { CCI_REG8(0x3b01), 0xcd }, { CCI_REG8(0x3b02), 0xcd },
1934 + { CCI_REG8(0x3b03), 0xcd }, { CCI_REG8(0x3b04), 0xcd },
1935 + { CCI_REG8(0x3b05), 0xcd }, { CCI_REG8(0x3b06), 0xcd },
1936 + { CCI_REG8(0x3b07), 0xcd }, { CCI_REG8(0x3b08), 0xcd },
1937 + { CCI_REG8(0x3b09), 0xcd }, { CCI_REG8(0x3b0a), 0xcd },
1938 + { CCI_REG8(0x3b0b), 0xcd }, { CCI_REG8(0x3b0c), 0xcd },
1939 + { CCI_REG8(0x3b0d), 0xcd }, { CCI_REG8(0x3b0e), 0xcd },
1940 + { CCI_REG8(0x3b0f), 0xcd }, { CCI_REG8(0x3b10), 0xcd },
1941 + { CCI_REG8(0x3b11), 0xcd }, { CCI_REG8(0x3b12), 0xcd },
1942 + { CCI_REG8(0x3b13), 0xcd }, { CCI_REG8(0x3b14), 0xcd },
1943 + { CCI_REG8(0x3b15), 0xcd }, { CCI_REG8(0x3b16), 0xcd },
1944 + { CCI_REG8(0x3b17), 0xcd }, { CCI_REG8(0x3b18), 0xcd },
1945 + { CCI_REG8(0x3b19), 0xcd }, { CCI_REG8(0x3b1a), 0xcd },
1946 + { CCI_REG8(0x3b1b), 0xcd }, { CCI_REG8(0x3b1c), 0xcd },
1947 + { CCI_REG8(0x3b1d), 0xcd }, { CCI_REG8(0x3b1e), 0xcd },
1948 + { CCI_REG8(0x3b1f), 0xcd }, { CCI_REG8(0x3b20), 0xcd },
1949 + { CCI_REG8(0x3b21), 0xcd }, { CCI_REG8(0x3b22), 0xcd },
1950 + { CCI_REG8(0x3b23), 0xcd }, { CCI_REG8(0x3b24), 0xcd },
1951 + { CCI_REG8(0x3b25), 0xcd }, { CCI_REG8(0x3b26), 0xcd },
1952 + { CCI_REG8(0x3b27), 0xcd }, { CCI_REG8(0x3b28), 0xcd },
1953 + { CCI_REG8(0x3b29), 0xcd }, { CCI_REG8(0x3b2a), 0xcd },
1954 + { CCI_REG8(0x3b2b), 0xcd }, { CCI_REG8(0x3b2c), 0xcd },
1955 + { CCI_REG8(0x3b2d), 0xcd }, { CCI_REG8(0x3b2e), 0xcd },
1956 + { CCI_REG8(0x3b2f), 0xcd }, { CCI_REG8(0x3b30), 0xcd },
1957 + { CCI_REG8(0x3b31), 0xcd }, { CCI_REG8(0x3b32), 0xcd },
1958 + { CCI_REG8(0x3b33), 0xcd }, { CCI_REG8(0x3b34), 0xcd },
1959 + { CCI_REG8(0x3b35), 0xcd }, { CCI_REG8(0x3b36), 0xcd },
1960 + { CCI_REG8(0x3b37), 0xcd }, { CCI_REG8(0x3b38), 0xcd },
1961 + { CCI_REG8(0x3b39), 0xcd }, { CCI_REG8(0x3b3a), 0xcd },
1962 + { CCI_REG8(0x3b3b), 0xcd }, { CCI_REG8(0x3b3c), 0xcd },
1963 + { CCI_REG8(0x3b3d), 0xcd }, { CCI_REG8(0x3b3e), 0xcd },
1964 + { CCI_REG8(0x3b3f), 0xcd }, { CCI_REG8(0x3b40), 0xcd },
1965 + { CCI_REG8(0x3b41), 0xcd }, { CCI_REG8(0x3b42), 0xcd },
1966 + { CCI_REG8(0x3b43), 0xcd }, { CCI_REG8(0x3b44), 0xcd },
1967 + { CCI_REG8(0x3b45), 0xcd }, { CCI_REG8(0x3b46), 0xcd },
1968 + { CCI_REG8(0x3b47), 0xcd }, { CCI_REG8(0x3b48), 0xcd },
1969 + { CCI_REG8(0x3b49), 0xcd }, { CCI_REG8(0x3b4a), 0xcd },
1970 + { CCI_REG8(0x3b4b), 0xcd }, { CCI_REG8(0x3b4c), 0xcd },
1971 + { CCI_REG8(0x3b4d), 0xcd }, { CCI_REG8(0x3b4e), 0xcd },
1972 + { CCI_REG8(0x3b4f), 0xcd }, { CCI_REG8(0x3b50), 0xcd },
1973 + { CCI_REG8(0x3b51), 0xcd }, { CCI_REG8(0x3b52), 0xcd },
1974 + { CCI_REG8(0x3b53), 0xcd }, { CCI_REG8(0x3b54), 0xcd },
1975 + { CCI_REG8(0x3b55), 0xcd }, { CCI_REG8(0x3b56), 0xcd },
1976 + { CCI_REG8(0x3b57), 0xcd }, { CCI_REG8(0x3b58), 0xcd },
1977 + { CCI_REG8(0x3b59), 0xcd }, { CCI_REG8(0x3b5a), 0xcd },
1978 + { CCI_REG8(0x3b5b), 0xcd }, { CCI_REG8(0x3b5c), 0xcd },
1979 + { CCI_REG8(0x3b5d), 0xcd }, { CCI_REG8(0x3b5e), 0xcd },
1980 + { CCI_REG8(0x3b5f), 0xcd }, { CCI_REG8(0x3b60), 0xcd },
1981 + { CCI_REG8(0x3b61), 0xcd }, { CCI_REG8(0x3b62), 0xcd },
1982 + { CCI_REG8(0x3b63), 0xcd }, { CCI_REG8(0x3b64), 0xcd },
1983 + { CCI_REG8(0x3b65), 0xcd }, { CCI_REG8(0x3b66), 0xcd },
1984 + { CCI_REG8(0x3b67), 0xcd }, { CCI_REG8(0x3b68), 0xcd },
1985 + { CCI_REG8(0x3b69), 0xcd }, { CCI_REG8(0x3b6a), 0xcd },
1986 + { CCI_REG8(0x3b6b), 0xcd }, { CCI_REG8(0x3b6c), 0xcd },
1987 + { CCI_REG8(0x3b6d), 0xcd }, { CCI_REG8(0x3b6e), 0xcd },
1988 + { CCI_REG8(0x3b6f), 0xcd }, { CCI_REG8(0x3b70), 0xcd },
1989 + { CCI_REG8(0x3b71), 0xcd }, { CCI_REG8(0x3b72), 0xcd },
1990 + { CCI_REG8(0x3b73), 0xcd }, { CCI_REG8(0x3b74), 0xcd },
1991 + { CCI_REG8(0x3b75), 0xcd }, { CCI_REG8(0x3b76), 0xcd },
1992 + { CCI_REG8(0x3b77), 0xcd }, { CCI_REG8(0x3b78), 0xcd },
1993 + { CCI_REG8(0x3b79), 0xcd }, { CCI_REG8(0x3b7a), 0xcd },
1994 + { CCI_REG8(0x3b7b), 0xcd }, { CCI_REG8(0x3b7c), 0xcd },
1995 + { CCI_REG8(0x3b7d), 0xcd }, { CCI_REG8(0x3b7e), 0xcd },
1996 + { CCI_REG8(0x3b7f), 0xcd }, { CCI_REG8(0x3b80), 0xcd },
1997 + { CCI_REG8(0x3b81), 0xcd }, { CCI_REG8(0x3b82), 0xcd },
1998 + { CCI_REG8(0x3b83), 0xcd }, { CCI_REG8(0x3b84), 0xcd },
1999 + { CCI_REG8(0x3b85), 0xcd }, { CCI_REG8(0x3b86), 0xcd },
2000 + { CCI_REG8(0x3b87), 0xcd }, { CCI_REG8(0x3b88), 0xcd },
2001 + { CCI_REG8(0x3b89), 0xcd }, { CCI_REG8(0x3b8a), 0xcd },
2002 + { CCI_REG8(0x3b8b), 0xcd }, { CCI_REG8(0x3b8c), 0xcd },
2003 + { CCI_REG8(0x3b8d), 0xcd }, { CCI_REG8(0x3b8e), 0xcd },
2004 + { CCI_REG8(0x3b8f), 0xcd }, { CCI_REG8(0x3b90), 0xcd },
2005 + { CCI_REG8(0x3b91), 0xcd }, { CCI_REG8(0x3b92), 0xcd },
2006 + { CCI_REG8(0x3b93), 0xcd }, { CCI_REG8(0x3b94), 0xcd },
2007 + { CCI_REG8(0x3b95), 0xcd }, { CCI_REG8(0x3b96), 0xcd },
2008 + { CCI_REG8(0x3b97), 0xcd }, { CCI_REG8(0x3b98), 0xcd },
2009 + { CCI_REG8(0x3b99), 0xcd }, { CCI_REG8(0x3b9a), 0xcd },
2010 + { CCI_REG8(0x3b9b), 0xcd }, { CCI_REG8(0x3b9c), 0xcd },
2011 + { CCI_REG8(0x3b9d), 0xcd }, { CCI_REG8(0x3b9e), 0xcd },
2012 + { CCI_REG8(0x3b9f), 0xcd }, { CCI_REG8(0x3ba0), 0xcd },
2013 + { CCI_REG8(0x3ba1), 0xcd }, { CCI_REG8(0x3ba2), 0xcd },
2014 + { CCI_REG8(0x3ba3), 0xcd }, { CCI_REG8(0x3ba4), 0xcd },
2015 + { CCI_REG8(0x3ba5), 0xcd }, { CCI_REG8(0x3ba6), 0xcd },
2016 + { CCI_REG8(0x3ba7), 0xcd }, { CCI_REG8(0x3ba8), 0xcd },
2017 + { CCI_REG8(0x3ba9), 0xcd }, { CCI_REG8(0x3baa), 0xcd },
2018 + { CCI_REG8(0x3bab), 0xcd }, { CCI_REG8(0x3bac), 0xcd },
2019 + { CCI_REG8(0x3bad), 0xcd }, { CCI_REG8(0x3bae), 0xcd },
2020 + { CCI_REG8(0x3baf), 0xcd }, { CCI_REG8(0x3bb0), 0xcd },
2021 + { CCI_REG8(0x3bb1), 0xcd }, { CCI_REG8(0x3bb2), 0xcd },
2022 + { CCI_REG8(0x3bb3), 0xcd }, { CCI_REG8(0x3bb4), 0xcd },
2023 + { CCI_REG8(0x3bb5), 0xcd }, { CCI_REG8(0x3bb6), 0xcd },
2024 + { CCI_REG8(0x3bb7), 0xcd }, { CCI_REG8(0x3bb8), 0xcd },
2025 + { CCI_REG8(0x3bb9), 0xcd }, { CCI_REG8(0x3bba), 0xcd },
2026 + { CCI_REG8(0x3bbb), 0xcd }, { CCI_REG8(0x3bbc), 0xcd },
2027 + { CCI_REG8(0x3bbd), 0xcd }, { CCI_REG8(0x3bbe), 0xcd },
2028 + { CCI_REG8(0x3bbf), 0xcd }, { CCI_REG8(0x3bc0), 0xcd },
2029 + { CCI_REG8(0x3bc1), 0xcd }, { CCI_REG8(0x3bc2), 0xcd },
2030 + { CCI_REG8(0x3bc3), 0xcd }, { CCI_REG8(0x3bc4), 0xcd },
2031 + { CCI_REG8(0x3bc5), 0xcd }, { CCI_REG8(0x3bc6), 0xcd },
2032 + { CCI_REG8(0x3bc7), 0xcd }, { CCI_REG8(0x3bc8), 0xcd },
2033 + { CCI_REG8(0x3bc9), 0xcd }, { CCI_REG8(0x3bca), 0xcd },
2034 + { CCI_REG8(0x3bcb), 0xcd }, { CCI_REG8(0x3bcc), 0xcd },
2035 + { CCI_REG8(0x3bcd), 0xcd }, { CCI_REG8(0x3bce), 0xcd },
2036 + { CCI_REG8(0x3bcf), 0xcd }, { CCI_REG8(0x3bd0), 0xcd },
2037 + { CCI_REG8(0x3bd1), 0xcd }, { CCI_REG8(0x3bd2), 0xcd },
2038 + { CCI_REG8(0x3bd3), 0xcd }, { CCI_REG8(0x3bd4), 0xcd },
2039 + { CCI_REG8(0x3bd5), 0xcd }, { CCI_REG8(0x3bd6), 0xcd },
2040 + { CCI_REG8(0x3bd7), 0xcd }, { CCI_REG8(0x3bd8), 0xcd },
2041 + { CCI_REG8(0x3bd9), 0xcd }, { CCI_REG8(0x3bda), 0xcd },
2042 + { CCI_REG8(0x3bdb), 0xcd }, { CCI_REG8(0x3bdc), 0xcd },
2043 + { CCI_REG8(0x3bdd), 0xcd }, { CCI_REG8(0x3bde), 0xcd },
2044 + { CCI_REG8(0x3bdf), 0xcd }, { CCI_REG8(0x3be0), 0xcd },
2045 + { CCI_REG8(0x3be1), 0xcd }, { CCI_REG8(0x3be2), 0xcd },
2046 + { CCI_REG8(0x3be3), 0xcd }, { CCI_REG8(0x3be4), 0xcd },
2047 + { CCI_REG8(0x3be5), 0xcd }, { CCI_REG8(0x3be6), 0xcd },
2048 + { CCI_REG8(0x3be7), 0xcd }, { CCI_REG8(0x3be8), 0xcd },
2049 + { CCI_REG8(0x3be9), 0xcd }, { CCI_REG8(0x3bea), 0xcd },
2050 + { CCI_REG8(0x3beb), 0xcd }, { CCI_REG8(0x3bec), 0xcd },
2051 + { CCI_REG8(0x3bed), 0xcd }, { CCI_REG8(0x3bee), 0xcd },
2052 + { CCI_REG8(0x3bef), 0xcd }, { CCI_REG8(0x3bf0), 0xcd },
2053 + { CCI_REG8(0x3bf1), 0xcd }, { CCI_REG8(0x3bf2), 0xcd },
2054 + { CCI_REG8(0x3bf3), 0xcd }, { CCI_REG8(0x3bf4), 0xcd },
2055 + { CCI_REG8(0x3bf5), 0xcd }, { CCI_REG8(0x3bf6), 0xcd },
2056 + { CCI_REG8(0x3bf7), 0xcd }, { CCI_REG8(0x3bf8), 0xcd },
2057 + { CCI_REG8(0x3bf9), 0xcd }, { CCI_REG8(0x3bfa), 0xcd },
2058 + { CCI_REG8(0x3bfb), 0xcd }, { CCI_REG8(0x3bfc), 0xcd },
2059 + { CCI_REG8(0x3bfd), 0xcd }, { CCI_REG8(0x3bfe), 0xcd },
2060 + { CCI_REG8(0x3bff), 0xcd }, { CCI_REG8(0x3c00), 0xcd },
2061 + { CCI_REG8(0x3c01), 0xcd }, { CCI_REG8(0x3c02), 0xcd },
2062 + { CCI_REG8(0x3c03), 0xcd }, { CCI_REG8(0x3c04), 0xcd },
2063 + { CCI_REG8(0x3c05), 0xcd }, { CCI_REG8(0x3c06), 0xcd },
2064 + { CCI_REG8(0x3c07), 0xcd }, { CCI_REG8(0x3c08), 0xcd },
2065 + { CCI_REG8(0x3c09), 0xcd }, { CCI_REG8(0x3c0a), 0xcd },
2066 + { CCI_REG8(0x3c0b), 0xcd }, { CCI_REG8(0x3c0c), 0xcd },
2067 + { CCI_REG8(0x3c0d), 0xcd }, { CCI_REG8(0x3c0e), 0xcd },
2068 + { CCI_REG8(0x3c0f), 0xcd }, { CCI_REG8(0x3c10), 0xcd },
2069 + { CCI_REG8(0x3c11), 0xcd }, { CCI_REG8(0x3c12), 0xcd },
2070 + { CCI_REG8(0x3c13), 0xcd }, { CCI_REG8(0x3c14), 0xcd },
2071 + { CCI_REG8(0x3c15), 0xcd }, { CCI_REG8(0x3c16), 0xcd },
2072 + { CCI_REG8(0x3c17), 0xcd }, { CCI_REG8(0x3c18), 0xcd },
2073 + { CCI_REG8(0x3c19), 0xcd }, { CCI_REG8(0x3c1a), 0xcd },
2074 + { CCI_REG8(0x3c1b), 0xcd }, { CCI_REG8(0x3c1c), 0xcd },
2075 + { CCI_REG8(0x3c1d), 0xcd }, { CCI_REG8(0x3c1e), 0xcd },
2076 + { CCI_REG8(0x3c1f), 0xcd }, { CCI_REG8(0x3c20), 0xcd },
2077 + { CCI_REG8(0x3c21), 0xcd }, { CCI_REG8(0x3c22), 0xcd },
2078 + { CCI_REG8(0x3c23), 0xcd }, { CCI_REG8(0x3c24), 0xcd },
2079 + { CCI_REG8(0x3c25), 0xcd }, { CCI_REG8(0x3c26), 0xcd },
2080 + { CCI_REG8(0x3c27), 0xcd }, { CCI_REG8(0x3c28), 0xcd },
2081 + { CCI_REG8(0x3c29), 0xcd }, { CCI_REG8(0x3c2a), 0xcd },
2082 + { CCI_REG8(0x3c2b), 0xcd }, { CCI_REG8(0x3c2c), 0xcd },
2083 + { CCI_REG8(0x3c2d), 0xcd }, { CCI_REG8(0x3c2e), 0xcd },
2084 + { CCI_REG8(0x3c2f), 0xcd }, { CCI_REG8(0x3c30), 0xcd },
2085 + { CCI_REG8(0x3c31), 0xcd }, { CCI_REG8(0x3c32), 0xcd },
2086 + { CCI_REG8(0x3c33), 0xcd }, { CCI_REG8(0x3c34), 0xcd },
2087 + { CCI_REG8(0x3c35), 0xcd }, { CCI_REG8(0x3c36), 0xcd },
2088 + { CCI_REG8(0x3c37), 0xcd }, { CCI_REG8(0x3c38), 0xcd },
2089 + { CCI_REG8(0x3c39), 0xcd }, { CCI_REG8(0x3c3a), 0xcd },
2090 + { CCI_REG8(0x3c3b), 0xcd }, { CCI_REG8(0x3c3c), 0xcd },
2091 + { CCI_REG8(0x3c3d), 0xcd }, { CCI_REG8(0x3c3e), 0xcd },
2092 + { CCI_REG8(0x3c3f), 0xcd }, { CCI_REG8(0x3c40), 0xcd },
2093 + { CCI_REG8(0x3c41), 0xcd }, { CCI_REG8(0x3c42), 0xcd },
2094 + { CCI_REG8(0x3c43), 0xcd }, { CCI_REG8(0x3c44), 0xcd },
2095 + { CCI_REG8(0x3c45), 0xcd }, { CCI_REG8(0x3c46), 0xcd },
2096 + { CCI_REG8(0x3c47), 0xcd }, { CCI_REG8(0x3c48), 0xcd },
2097 + { CCI_REG8(0x3c49), 0xcd }, { CCI_REG8(0x3c4a), 0xcd },
2098 + { CCI_REG8(0x3c4b), 0xcd }, { CCI_REG8(0x3c4c), 0xcd },
2099 + { CCI_REG8(0x3c4d), 0xcd }, { CCI_REG8(0x3c4e), 0xcd },
2100 + { CCI_REG8(0x3c4f), 0xcd }, { CCI_REG8(0x3c50), 0xcd },
2101 + { CCI_REG8(0x3c51), 0xcd }, { CCI_REG8(0x3c52), 0xcd },
2102 + { CCI_REG8(0x3c53), 0xcd }, { CCI_REG8(0x3c54), 0xcd },
2103 + { CCI_REG8(0x3c55), 0xcd }, { CCI_REG8(0x3c56), 0xcd },
2104 + { CCI_REG8(0x3c57), 0xcd }, { CCI_REG8(0x3c58), 0xcd },
2105 + { CCI_REG8(0x3c59), 0xcd }, { CCI_REG8(0x3c5a), 0xcd },
2106 + { CCI_REG8(0x3c5b), 0xcd }, { CCI_REG8(0x3c5c), 0xcd },
2107 + { CCI_REG8(0x3c5d), 0xcd }, { CCI_REG8(0x3c5e), 0xcd },
2108 + { CCI_REG8(0x3c5f), 0xcd }, { CCI_REG8(0x3c60), 0xcd },
2109 + { CCI_REG8(0x3c61), 0xcd }, { CCI_REG8(0x3c62), 0xcd },
2110 + { CCI_REG8(0x3c63), 0xcd }, { CCI_REG8(0x3c64), 0xcd },
2111 + { CCI_REG8(0x3c65), 0xcd }, { CCI_REG8(0x3c66), 0xcd },
2112 + { CCI_REG8(0x3c67), 0xcd }, { CCI_REG8(0x3c68), 0xcd },
2113 + { CCI_REG8(0x3c69), 0xcd }, { CCI_REG8(0x3c6a), 0xcd },
2114 + { CCI_REG8(0x3c6b), 0xcd }, { CCI_REG8(0x3c6c), 0xcd },
2115 + { CCI_REG8(0x3c6d), 0xcd }, { CCI_REG8(0x3c6e), 0xcd },
2116 + { CCI_REG8(0x3c6f), 0xcd }, { CCI_REG8(0x3c70), 0xcd },
2117 + { CCI_REG8(0x3c71), 0xcd }, { CCI_REG8(0x3c72), 0xcd },
2118 + { CCI_REG8(0x3c73), 0xcd }, { CCI_REG8(0x3c74), 0xcd },
2119 + { CCI_REG8(0x3c75), 0xcd }, { CCI_REG8(0x3c76), 0xcd },
2120 + { CCI_REG8(0x3c77), 0xcd }, { CCI_REG8(0x3c78), 0xcd },
2121 + { CCI_REG8(0x3c79), 0xcd }, { CCI_REG8(0x3c7a), 0xcd },
2122 + { CCI_REG8(0x3c7b), 0xcd }, { CCI_REG8(0x3c7c), 0xcd },
2123 + { CCI_REG8(0x3c7d), 0xcd }, { CCI_REG8(0x3c7e), 0xcd },
2124 + { CCI_REG8(0x3c7f), 0xcd }, { CCI_REG8(0x3c80), 0xcd },
2125 + { CCI_REG8(0x3c81), 0xcd }, { CCI_REG8(0x3c82), 0xcd },
2126 + { CCI_REG8(0x3c83), 0xcd }, { CCI_REG8(0x3c84), 0xcd },
2127 + { CCI_REG8(0x3c85), 0xcd }, { CCI_REG8(0x3c86), 0xcd },
2128 + { CCI_REG8(0x3c87), 0xcd }, { CCI_REG8(0x3c88), 0xcd },
2129 + { CCI_REG8(0x3c89), 0xcd }, { CCI_REG8(0x3c8a), 0xcd },
2130 + { CCI_REG8(0x3c8b), 0xcd }, { CCI_REG8(0x3c8c), 0xcd },
2131 + { CCI_REG8(0x3c8d), 0xcd }, { CCI_REG8(0x3c8e), 0xcd },
2132 + { CCI_REG8(0x3c8f), 0xcd }, { CCI_REG8(0x3c90), 0xcd },
2133 + { CCI_REG8(0x3c91), 0xcd }, { CCI_REG8(0x3c92), 0xcd },
2134 + { CCI_REG8(0x3c93), 0xcd }, { CCI_REG8(0x3c94), 0xcd },
2135 + { CCI_REG8(0x3c95), 0xcd }, { CCI_REG8(0x3c96), 0xcd },
2136 + { CCI_REG8(0x3c97), 0xcd }, { CCI_REG8(0x3c98), 0xcd },
2137 + { CCI_REG8(0x3c99), 0xcd }, { CCI_REG8(0x3c9a), 0xcd },
2138 + { CCI_REG8(0x3c9b), 0xcd }, { CCI_REG8(0x3c9c), 0xcd },
2139 + { CCI_REG8(0x3c9d), 0xcd }, { CCI_REG8(0x3c9e), 0xcd },
2140 + { CCI_REG8(0x3c9f), 0xcd }, { CCI_REG8(0x3ca0), 0xcd },
2141 + { CCI_REG8(0x3ca1), 0xcd }, { CCI_REG8(0x3ca2), 0xcd },
2142 + { CCI_REG8(0x3ca3), 0xcd }, { CCI_REG8(0x3ca4), 0xcd },
2143 + { CCI_REG8(0x3ca5), 0xcd }, { CCI_REG8(0x3ca6), 0xcd },
2144 + { CCI_REG8(0x3ca7), 0xcd }, { CCI_REG8(0x3ca8), 0xcd },
2145 + { CCI_REG8(0x3ca9), 0xcd }, { CCI_REG8(0x3caa), 0xcd },
2146 + { CCI_REG8(0x3cab), 0xcd }, { CCI_REG8(0x3cac), 0xcd },
2147 + { CCI_REG8(0x3cad), 0xcd }, { CCI_REG8(0x3cae), 0xcd },
2148 + { CCI_REG8(0x3caf), 0xcd }, { CCI_REG8(0x3cb0), 0xcd },
2149 + { CCI_REG8(0x3cb1), 0x40 }, { CCI_REG8(0x3cb2), 0x40 },
2150 + { CCI_REG8(0x3cb3), 0x40 }, { CCI_REG8(0x3cb4), 0x40 },
2151 + { CCI_REG8(0x3cb5), 0x40 }, { CCI_REG8(0x3cb6), 0x40 },
2152 + { CCI_REG8(0x3cb7), 0x40 }, { CCI_REG8(0x3cb8), 0x40 },
2153 + { CCI_REG8(0x3cb9), 0x40 }, { CCI_REG8(0x3cba), 0x40 },
2154 + { CCI_REG8(0x3cbb), 0x40 }, { CCI_REG8(0x3cbc), 0x40 },
2155 + { CCI_REG8(0x3cbd), 0x40 }, { CCI_REG8(0x3cbe), 0x40 },
2156 + { CCI_REG8(0x3cbf), 0x40 }, { CCI_REG8(0x3cc0), 0x40 },
2157 + { CCI_REG8(0x3cc1), 0x40 }, { CCI_REG8(0x3cc2), 0x40 },
2158 + { CCI_REG8(0x3cc3), 0x40 }, { CCI_REG8(0x3cc4), 0x40 },
2159 + { CCI_REG8(0x3cc5), 0x40 }, { CCI_REG8(0x3cc6), 0x40 },
2160 + { CCI_REG8(0x3cc7), 0x40 }, { CCI_REG8(0x3cc8), 0x40 },
2161 + { CCI_REG8(0x3cc9), 0x40 }, { CCI_REG8(0x3cca), 0x40 },
2162 + { CCI_REG8(0x3ccb), 0x40 }, { CCI_REG8(0x3ccc), 0x40 },
2163 + { CCI_REG8(0x3ccd), 0x40 }, { CCI_REG8(0x3cce), 0x40 },
2164 + { CCI_REG8(0x3ccf), 0x40 }, { CCI_REG8(0x3cd0), 0x40 },
2165 + { CCI_REG8(0x3cd1), 0x40 }, { CCI_REG8(0x3cd2), 0x40 },
2166 + { CCI_REG8(0x3cd3), 0x40 }, { CCI_REG8(0x3cd4), 0x40 },
2167 + { CCI_REG8(0x3cd5), 0x40 }, { CCI_REG8(0x3cd6), 0x40 },
2168 + { CCI_REG8(0x3cd7), 0x40 }, { CCI_REG8(0x3cd8), 0x40 },
2169 + { CCI_REG8(0x3cd9), 0x40 }, { CCI_REG8(0x3cda), 0x40 },
2170 + { CCI_REG8(0x3cdb), 0x40 }, { CCI_REG8(0x3cdc), 0x40 },
2171 + { CCI_REG8(0x3cdd), 0x40 }, { CCI_REG8(0x3cde), 0x40 },
2172 + { CCI_REG8(0x3cdf), 0x40 }, { CCI_REG8(0x3ce0), 0x40 },
2173 + { CCI_REG8(0x3ce1), 0x40 }, { CCI_REG8(0x3ce2), 0x40 },
2174 + { CCI_REG8(0x3ce3), 0x40 }, { CCI_REG8(0x3ce4), 0x40 },
2175 + { CCI_REG8(0x3ce5), 0x40 }, { CCI_REG8(0x3ce6), 0x40 },
2176 + { CCI_REG8(0x3ce7), 0x40 }, { CCI_REG8(0x3ce8), 0x40 },
2177 + { CCI_REG8(0x3ce9), 0x40 }, { CCI_REG8(0x3cea), 0x40 },
2178 + { CCI_REG8(0x3ceb), 0x40 }, { CCI_REG8(0x3cec), 0x40 },
2179 + { CCI_REG8(0x3ced), 0x40 }, { CCI_REG8(0x3cee), 0x40 },
2180 + { CCI_REG8(0x3cef), 0x40 }, { CCI_REG8(0x3cf0), 0x40 },
2181 + { CCI_REG8(0x3cf1), 0x40 }, { CCI_REG8(0x3cf2), 0x40 },
2182 + { CCI_REG8(0x3cf3), 0x40 }, { CCI_REG8(0x3cf4), 0x40 },
2183 + { CCI_REG8(0x3cf5), 0x40 }, { CCI_REG8(0x3cf6), 0x40 },
2184 + { CCI_REG8(0x3cf7), 0x40 }, { CCI_REG8(0x3cf8), 0x40 },
2185 + { CCI_REG8(0x3cf9), 0x40 }, { CCI_REG8(0x3cfa), 0x40 },
2186 + { CCI_REG8(0x3cfb), 0x40 }, { CCI_REG8(0x3cfc), 0x40 },
2187 + { CCI_REG8(0x3cfd), 0x40 }, { CCI_REG8(0x3cfe), 0x40 },
2188 + { CCI_REG8(0x3cff), 0x40 }, { CCI_REG8(0x3d00), 0x40 },
2189 + { CCI_REG8(0x3d01), 0x40 }, { CCI_REG8(0x3d02), 0x40 },
2190 + { CCI_REG8(0x3d03), 0x40 }, { CCI_REG8(0x3d04), 0x40 },
2191 + { CCI_REG8(0x3d05), 0x40 }, { CCI_REG8(0x3d06), 0x40 },
2192 + { CCI_REG8(0x3d07), 0x40 }, { CCI_REG8(0x3d08), 0x40 },
2193 + { CCI_REG8(0x3d09), 0x40 }, { CCI_REG8(0x3d0a), 0x40 },
2194 + { CCI_REG8(0x3d0b), 0xcd }, { CCI_REG8(0x3d0c), 0xcd },
2195 + { CCI_REG8(0x3d0d), 0xcd }, { CCI_REG8(0x3d0e), 0xcd },
2196 + { CCI_REG8(0x3d0f), 0xcd }, { CCI_REG8(0x3d10), 0xcd },
2197 + { CCI_REG8(0x3d11), 0xcd }, { CCI_REG8(0x3d12), 0xcd },
2198 + { CCI_REG8(0x3d13), 0xcd }, { CCI_REG8(0x3d14), 0xcd },
2199 + { CCI_REG8(0x3d15), 0xcd }, { CCI_REG8(0x3d16), 0xcd },
2200 + { CCI_REG8(0x3d17), 0xcd }, { CCI_REG8(0x3d18), 0xcd },
2201 + { CCI_REG8(0x3d19), 0xcd }, { CCI_REG8(0x3d1a), 0xcd },
2202 + { CCI_REG8(0x3d1b), 0xcd }, { CCI_REG8(0x3d1c), 0xcd },
2203 + { CCI_REG8(0x3d1d), 0xcd }, { CCI_REG8(0x3d1e), 0xcd },
2204 + { CCI_REG8(0x3d1f), 0xcd }, { CCI_REG8(0x3d20), 0xcd },
2205 + { CCI_REG8(0x3d21), 0xcd }, { CCI_REG8(0x3d22), 0xcd },
2206 + { CCI_REG8(0x3d23), 0xcd }, { CCI_REG8(0x3d24), 0xcd },
2207 + { CCI_REG8(0x3d25), 0xcd }, { CCI_REG8(0x3d26), 0xcd },
2208 + { CCI_REG8(0x3d27), 0xcd }, { CCI_REG8(0x3d28), 0xcd },
2209 + { CCI_REG8(0x3d29), 0xcd }, { CCI_REG8(0x3d2a), 0xcd },
2210 + { CCI_REG8(0x3d2b), 0xcd }, { CCI_REG8(0x3d2c), 0xcd },
2211 + { CCI_REG8(0x3d2d), 0xcd }, { CCI_REG8(0x3d2e), 0xcd },
2212 + { CCI_REG8(0x3d2f), 0xcd }, { CCI_REG8(0x3d30), 0xcd },
2213 + { CCI_REG8(0x3d31), 0xcd }, { CCI_REG8(0x3d32), 0xcd },
2214 + { CCI_REG8(0x3d33), 0xcd }, { CCI_REG8(0x3d34), 0xcd },
2215 + { CCI_REG8(0x3d35), 0xcd }, { CCI_REG8(0x3d36), 0xcd },
2216 + { CCI_REG8(0x3d37), 0xcd }, { CCI_REG8(0x3d38), 0xcd },
2217 + { CCI_REG8(0x3d39), 0xcd }, { CCI_REG8(0x3d3a), 0xcd },
2218 + { CCI_REG8(0x3d3b), 0xcd }, { CCI_REG8(0x3d3c), 0xcd },
2219 + { CCI_REG8(0x3d3d), 0xcd }, { CCI_REG8(0x3d3e), 0xcd },
2220 + { CCI_REG8(0x3d3f), 0xcd }, { CCI_REG8(0x3d40), 0xcd },
2221 + { CCI_REG8(0x3d41), 0xcd }, { CCI_REG8(0x3d42), 0xcd },
2222 + { CCI_REG8(0x3d43), 0xcd }, { CCI_REG8(0x3d44), 0xcd },
2223 + { CCI_REG8(0x3d45), 0xcd }, { CCI_REG8(0x3d46), 0xcd },
2224 + { CCI_REG8(0x3d47), 0xcd }, { CCI_REG8(0x3d48), 0xcd },
2225 + { CCI_REG8(0x3d49), 0xcd }, { CCI_REG8(0x3d4a), 0xcd },
2226 + { CCI_REG8(0x3d4b), 0xcd }, { CCI_REG8(0x3d4c), 0xcd },
2227 + { CCI_REG8(0x3d4d), 0xcd }, { CCI_REG8(0x3d4e), 0xcd },
2228 + { CCI_REG8(0x3d4f), 0xcd }, { CCI_REG8(0x3d50), 0xcd },
2229 + { CCI_REG8(0x3d51), 0xcd }, { CCI_REG8(0x3d52), 0xcd },
2230 + { CCI_REG8(0x3d53), 0xcd }, { CCI_REG8(0x3d54), 0xcd },
2231 + { CCI_REG8(0x3d55), 0xcd }, { CCI_REG8(0x3d56), 0xcd },
2232 + { CCI_REG8(0x3d57), 0xcd }, { CCI_REG8(0x3d58), 0xcd },
2233 + { CCI_REG8(0x3d59), 0xcd }, { CCI_REG8(0x3d5a), 0xcd },
2234 + { CCI_REG8(0x3d5b), 0xcd }, { CCI_REG8(0x3d5c), 0xcd },
2235 + { CCI_REG8(0x3d5d), 0xcd }, { CCI_REG8(0x3d5e), 0xcd },
2236 + { CCI_REG8(0x3d5f), 0xcd }, { CCI_REG8(0x3d60), 0xcd },
2237 + { CCI_REG8(0x3d61), 0xcd }, { CCI_REG8(0x3d62), 0xcd },
2238 + { CCI_REG8(0x3d63), 0xcd }, { CCI_REG8(0x3d64), 0xcd },
2239 + { CCI_REG8(0x3d65), 0x40 }, { CCI_REG8(0x3d66), 0x40 },
2240 + { CCI_REG8(0x3d67), 0x40 }, { CCI_REG8(0x3d68), 0x40 },
2241 + { CCI_REG8(0x3d69), 0x40 }, { CCI_REG8(0x3d6a), 0x40 },
2242 + { CCI_REG8(0x3d6b), 0x40 }, { CCI_REG8(0x3d6c), 0x40 },
2243 + { CCI_REG8(0x3d6d), 0x40 }, { CCI_REG8(0x3d6e), 0x40 },
2244 + { CCI_REG8(0x3d6f), 0x40 }, { CCI_REG8(0x3d70), 0x40 },
2245 + { CCI_REG8(0x3d71), 0x40 }, { CCI_REG8(0x3d72), 0x40 },
2246 + { CCI_REG8(0x3d73), 0x40 }, { CCI_REG8(0x3d74), 0x40 },
2247 + { CCI_REG8(0x3d75), 0x40 }, { CCI_REG8(0x3d76), 0x40 },
2248 + { CCI_REG8(0x3d77), 0x40 }, { CCI_REG8(0x3d78), 0x40 },
2249 + { CCI_REG8(0x3d79), 0x40 }, { CCI_REG8(0x3d7a), 0x40 },
2250 + { CCI_REG8(0x3d7b), 0x40 }, { CCI_REG8(0x3d7c), 0x40 },
2251 + { CCI_REG8(0x3d7d), 0x40 }, { CCI_REG8(0x3d7e), 0x40 },
2252 + { CCI_REG8(0x3d7f), 0x40 }, { CCI_REG8(0x3d80), 0x40 },
2253 + { CCI_REG8(0x3d81), 0x40 }, { CCI_REG8(0x3d82), 0x40 },
2254 + { CCI_REG8(0x3d83), 0x40 }, { CCI_REG8(0x3d84), 0x40 },
2255 + { CCI_REG8(0x3d85), 0x40 }, { CCI_REG8(0x3d86), 0x40 },
2256 + { CCI_REG8(0x3d87), 0x40 }, { CCI_REG8(0x3d88), 0x40 },
2257 + { CCI_REG8(0x3d89), 0x40 }, { CCI_REG8(0x3d8a), 0x40 },
2258 + { CCI_REG8(0x3d8b), 0x40 }, { CCI_REG8(0x3d8c), 0x40 },
2259 + { CCI_REG8(0x3d8d), 0x40 }, { CCI_REG8(0x3d8e), 0x40 },
2260 + { CCI_REG8(0x3d8f), 0x40 }, { CCI_REG8(0x3d90), 0x40 },
2261 + { CCI_REG8(0x3d91), 0x40 }, { CCI_REG8(0x3d92), 0x40 },
2262 + { CCI_REG8(0x3d93), 0x40 }, { CCI_REG8(0x3d94), 0x40 },
2263 + { CCI_REG8(0x3d95), 0x40 }, { CCI_REG8(0x3d96), 0x40 },
2264 + { CCI_REG8(0x3d97), 0x40 }, { CCI_REG8(0x3d98), 0x40 },
2265 + { CCI_REG8(0x3d99), 0x40 }, { CCI_REG8(0x3d9a), 0x40 },
2266 + { CCI_REG8(0x3d9b), 0x40 }, { CCI_REG8(0x3d9c), 0x40 },
2267 + { CCI_REG8(0x3d9d), 0x40 }, { CCI_REG8(0x3d9e), 0x40 },
2268 + { CCI_REG8(0x3d9f), 0x40 }, { CCI_REG8(0x3da0), 0x40 },
2269 + { CCI_REG8(0x3da1), 0x40 }, { CCI_REG8(0x3da2), 0x40 },
2270 + { CCI_REG8(0x3da3), 0x40 }, { CCI_REG8(0x3da4), 0x40 },
2271 + { CCI_REG8(0x3da5), 0x40 }, { CCI_REG8(0x3da6), 0x40 },
2272 + { CCI_REG8(0x3da7), 0x40 }, { CCI_REG8(0x3da8), 0x40 },
2273 + { CCI_REG8(0x3da9), 0x40 }, { CCI_REG8(0x3daa), 0x40 },
2274 + { CCI_REG8(0x3dab), 0x40 }, { CCI_REG8(0x3dac), 0x40 },
2275 + { CCI_REG8(0x3dad), 0x40 }, { CCI_REG8(0x3dae), 0x40 },
2276 + { CCI_REG8(0x3daf), 0x40 }, { CCI_REG8(0x3db0), 0x40 },
2277 + { CCI_REG8(0x3db1), 0x40 }, { CCI_REG8(0x3db2), 0x40 },
2278 + { CCI_REG8(0x3db3), 0x40 }, { CCI_REG8(0x3db4), 0x40 },
2279 + { CCI_REG8(0x3db5), 0x40 }, { CCI_REG8(0x3db6), 0x40 },
2280 + { CCI_REG8(0x3db7), 0x40 }, { CCI_REG8(0x3db8), 0x40 },
2281 + { CCI_REG8(0x3db9), 0x40 }, { CCI_REG8(0x3dba), 0x40 },
2282 + { CCI_REG8(0x3dbb), 0x40 }, { CCI_REG8(0x3dbc), 0x40 },
2283 + { CCI_REG8(0x3dbd), 0x40 }, { CCI_REG8(0x3dbe), 0x40 },
2284 + { CCI_REG8(0x3dbf), 0xcd }, { CCI_REG8(0x3dc0), 0xcd },
2285 + { CCI_REG8(0x3dc1), 0xcd }, { CCI_REG8(0x3dc2), 0xcd },
2286 + { CCI_REG8(0x3dc3), 0xcd }, { CCI_REG8(0x3dc4), 0xcd },
2287 + { CCI_REG8(0x3dc5), 0xcd }, { CCI_REG8(0x3dc6), 0xcd },
2288 + { CCI_REG8(0x3dc7), 0xcd }, { CCI_REG8(0x3dc8), 0xcd },
2289 + { CCI_REG8(0x3dc9), 0xcd }, { CCI_REG8(0x3dca), 0xcd },
2290 + { CCI_REG8(0x3dcb), 0xcd }, { CCI_REG8(0x3dcc), 0xcd },
2291 + { CCI_REG8(0x3dcd), 0xcd }, { CCI_REG8(0x3dce), 0xcd },
2292 + { CCI_REG8(0x3dcf), 0xcd }, { CCI_REG8(0x3dd0), 0xcd },
2293 + { CCI_REG8(0x3dd1), 0xcd }, { CCI_REG8(0x3dd2), 0xcd },
2294 + { CCI_REG8(0x3dd3), 0xcd }, { CCI_REG8(0x3dd4), 0xcd },
2295 + { CCI_REG8(0x3dd5), 0xcd }, { CCI_REG8(0x3dd6), 0xcd },
2296 + { CCI_REG8(0x3dd7), 0xcd }, { CCI_REG8(0x3dd8), 0xcd },
2297 + { CCI_REG8(0x3dd9), 0xcd }, { CCI_REG8(0x3dda), 0xcd },
2298 + { CCI_REG8(0x3ddb), 0xcd }, { CCI_REG8(0x3ddc), 0xcd },
2299 + { CCI_REG8(0x3ddd), 0xcd }, { CCI_REG8(0x3dde), 0xcd },
2300 + { CCI_REG8(0x3ddf), 0xcd }, { CCI_REG8(0x3de0), 0xcd },
2301 + { CCI_REG8(0x3de1), 0xcd }, { CCI_REG8(0x3de2), 0xcd },
2302 + { CCI_REG8(0x3de3), 0xcd }, { CCI_REG8(0x3de4), 0xcd },
2303 + { CCI_REG8(0x3de5), 0xcd }, { CCI_REG8(0x3de6), 0xcd },
2304 + { CCI_REG8(0x3de7), 0xcd }, { CCI_REG8(0x3de8), 0xcd },
2305 + { CCI_REG8(0x3de9), 0xcd }, { CCI_REG8(0x3dea), 0xcd },
2306 + { CCI_REG8(0x3deb), 0xcd }, { CCI_REG8(0x3dec), 0xcd },
2307 + { CCI_REG8(0x3ded), 0xcd }, { CCI_REG8(0x3dee), 0xcd },
2308 + { CCI_REG8(0x3def), 0xcd }, { CCI_REG8(0x3df0), 0xcd },
2309 + { CCI_REG8(0x3df1), 0xcd }, { CCI_REG8(0x3df2), 0xcd },
2310 + { CCI_REG8(0x3df3), 0xcd }, { CCI_REG8(0x3df4), 0xcd },
2311 + { CCI_REG8(0x3df5), 0xcd }, { CCI_REG8(0x3df6), 0xcd },
2312 + { CCI_REG8(0x3df7), 0xcd }, { CCI_REG8(0x3df8), 0xcd },
2313 + { CCI_REG8(0x3df9), 0xcd }, { CCI_REG8(0x3dfa), 0xcd },
2314 + { CCI_REG8(0x3dfb), 0xcd }, { CCI_REG8(0x3dfc), 0xcd },
2315 + { CCI_REG8(0x3dfd), 0xcd }, { CCI_REG8(0x3dfe), 0xcd },
2316 + { CCI_REG8(0x3dff), 0xcd }, { CCI_REG8(0x3e00), 0xcd },
2317 + { CCI_REG8(0x3e01), 0xcd }, { CCI_REG8(0x3e02), 0xcd },
2318 + { CCI_REG8(0x3e03), 0xcd }, { CCI_REG8(0x3e04), 0xcd },
2319 + { CCI_REG8(0x3e05), 0xcd }, { CCI_REG8(0x3e06), 0xcd },
2320 + { CCI_REG8(0x3e07), 0xcd }, { CCI_REG8(0x3e08), 0xcd },
2321 + { CCI_REG8(0x3e09), 0xcd }, { CCI_REG8(0x3e0a), 0xcd },
2322 + { CCI_REG8(0x3e0b), 0xcd }, { CCI_REG8(0x3e0c), 0xcd },
2323 + { CCI_REG8(0x3e0d), 0xcd }, { CCI_REG8(0x3e0e), 0xcd },
2324 + { CCI_REG8(0x3e0f), 0xcd }, { CCI_REG8(0x3e10), 0xcd },
2325 + { CCI_REG8(0x3e11), 0xcd }, { CCI_REG8(0x3e12), 0xcd },
2326 + { CCI_REG8(0x3e13), 0xcd }, { CCI_REG8(0x3e14), 0xcd },
2327 + { CCI_REG8(0x3e15), 0xcd }, { CCI_REG8(0x3e16), 0xcd },
2328 + { CCI_REG8(0x3e17), 0xcd }, { CCI_REG8(0x3e18), 0xcd },
2329 + { CCI_REG8(0x3e19), 0xcd }, { CCI_REG8(0x3e1a), 0xcd },
2330 + { CCI_REG8(0x3e1b), 0xcd }, { CCI_REG8(0x3e1c), 0xcd },
2331 + { CCI_REG8(0x3e1d), 0xcd }, { CCI_REG8(0x3e1e), 0xcd },
2332 + { CCI_REG8(0x3e1f), 0xcd }, { CCI_REG8(0x3e20), 0xcd },
2333 + { CCI_REG8(0x3e21), 0xcd }, { CCI_REG8(0x3e22), 0xcd },
2334 + { CCI_REG8(0x3e23), 0xcd }, { CCI_REG8(0x3e24), 0xcd },
2335 + { CCI_REG8(0x3e25), 0xcd }, { CCI_REG8(0x3e26), 0xcd },
2336 + { CCI_REG8(0x3e27), 0xcd }, { CCI_REG8(0x3e28), 0xcd },
2337 + { CCI_REG8(0x3e29), 0xcd }, { CCI_REG8(0x3e2a), 0xcd },
2338 + { CCI_REG8(0x3e2b), 0xcd }, { CCI_REG8(0x3e2c), 0xcd },
2339 + { CCI_REG8(0x3e2d), 0xcd }, { CCI_REG8(0x3e2e), 0xcd },
2340 + { CCI_REG8(0x3e2f), 0xcd }, { CCI_REG8(0x3e30), 0xcd },
2341 + { CCI_REG8(0x3e31), 0xcd }, { CCI_REG8(0x3e32), 0xcd },
2342 + { CCI_REG8(0x3e33), 0xcd }, { CCI_REG8(0x3e34), 0xcd },
2343 + { CCI_REG8(0x3e35), 0xcd }, { CCI_REG8(0x3e36), 0xcd },
2344 + { CCI_REG8(0x3e37), 0xcd }, { CCI_REG8(0x3e38), 0xcd },
2345 + { CCI_REG8(0x3e39), 0xcd }, { CCI_REG8(0x3e3a), 0xcd },
2346 + { CCI_REG8(0x3e3b), 0xcd }, { CCI_REG8(0x3e3c), 0xcd },
2347 + { CCI_REG8(0x3e3d), 0xcd }, { CCI_REG8(0x3e3e), 0xcd },
2348 + { CCI_REG8(0x3e3f), 0xcd }, { CCI_REG8(0x3e40), 0xcd },
2349 + { CCI_REG8(0x3e41), 0xcd }, { CCI_REG8(0x3e42), 0xcd },
2350 + { CCI_REG8(0x3e43), 0xcd }, { CCI_REG8(0x3e44), 0xcd },
2351 + { CCI_REG8(0x3e45), 0xcd }, { CCI_REG8(0x3e46), 0xcd },
2352 + { CCI_REG8(0x3e47), 0xcd }, { CCI_REG8(0x3e48), 0xcd },
2353 + { CCI_REG8(0x3e49), 0xcd }, { CCI_REG8(0x3e4a), 0xcd },
2354 + { CCI_REG8(0x3e4b), 0xcd }, { CCI_REG8(0x3e4c), 0xcd },
2355 + { CCI_REG8(0x3e4d), 0xcd }, { CCI_REG8(0x3e4e), 0xcd },
2356 + { CCI_REG8(0x3e4f), 0xcd }, { CCI_REG8(0x3e50), 0xcd },
2357 + { CCI_REG8(0x3e51), 0xcd }, { CCI_REG8(0x3e52), 0xcd },
2358 + { CCI_REG8(0x3e53), 0xcd }, { CCI_REG8(0x3e54), 0xcd },
2359 + { CCI_REG8(0x3e55), 0xcd }, { CCI_REG8(0x3e56), 0xcd },
2360 + { CCI_REG8(0x3e57), 0xcd }, { CCI_REG8(0x3e58), 0xcd },
2361 + { CCI_REG8(0x3e59), 0xcd }, { CCI_REG8(0x3e5a), 0xcd },
2362 + { CCI_REG8(0x3e5b), 0xcd }, { CCI_REG8(0x3e5c), 0xcd },
2363 + { CCI_REG8(0x3e5d), 0xcd }, { CCI_REG8(0x3e5e), 0xcd },
2364 + { CCI_REG8(0x3e5f), 0xcd }, { CCI_REG8(0x3e60), 0xcd },
2365 + { CCI_REG8(0x3e61), 0xcd }, { CCI_REG8(0x3e62), 0xcd },
2366 + { CCI_REG8(0x3e63), 0xcd }, { CCI_REG8(0x3e64), 0xcd },
2367 + { CCI_REG8(0x3e65), 0xcd }, { CCI_REG8(0x3e66), 0xcd },
2368 + { CCI_REG8(0x3e67), 0xcd }, { CCI_REG8(0x3e68), 0xcd },
2369 + { CCI_REG8(0x3e69), 0xcd }, { CCI_REG8(0x3e6a), 0xcd },
2370 + { CCI_REG8(0x3e6b), 0xcd }, { CCI_REG8(0x3e6c), 0xcd },
2371 + { CCI_REG8(0x3e6d), 0xcd }, { CCI_REG8(0x3e6e), 0xcd },
2372 + { CCI_REG8(0x3e6f), 0xcd }, { CCI_REG8(0x3e70), 0xcd },
2373 + { CCI_REG8(0x3e71), 0xcd }, { CCI_REG8(0x3e72), 0xcd },
2374 + { CCI_REG8(0x3e73), 0xcd }, { CCI_REG8(0x3e74), 0xcd },
2375 + { CCI_REG8(0x3e75), 0xcd }, { CCI_REG8(0x3e76), 0xcd },
2376 + { CCI_REG8(0x3e77), 0xcd }, { CCI_REG8(0x3e78), 0xcd },
2377 + { CCI_REG8(0x3e79), 0xcd }, { CCI_REG8(0x3e7a), 0xcd },
2378 + { CCI_REG8(0x3e7b), 0xcd }, { CCI_REG8(0x3e7c), 0xcd },
2379 + { CCI_REG8(0x3e7d), 0xcd }, { CCI_REG8(0x3e7e), 0xcd },
2380 + { CCI_REG8(0x3e7f), 0xcd }, { CCI_REG8(0x3e80), 0xcd },
2381 + { CCI_REG8(0x3e81), 0xcd }, { CCI_REG8(0x3e82), 0xcd },
2382 + { CCI_REG8(0x3e83), 0xcd }, { CCI_REG8(0x3e84), 0xcd },
2383 + { CCI_REG8(0x3e85), 0xcd }, { CCI_REG8(0x3e86), 0xcd },
2384 + { CCI_REG8(0x3e87), 0xcd }, { CCI_REG8(0x3e88), 0xcd },
2385 + { CCI_REG8(0x3e89), 0xcd }, { CCI_REG8(0x3e8a), 0xcd },
2386 + { CCI_REG8(0x3e8b), 0xcd }, { CCI_REG8(0x3e8c), 0xcd },
2387 + { CCI_REG8(0x3e8d), 0xcd }, { CCI_REG8(0x3e8e), 0xcd },
2388 + { CCI_REG8(0x3e8f), 0xcd }, { CCI_REG8(0x3e90), 0xcd },
2389 + { CCI_REG8(0x3e91), 0xcd }, { CCI_REG8(0x3e92), 0xcd },
2390 + { CCI_REG8(0x3e93), 0xcd }, { CCI_REG8(0x3e94), 0xcd },
2391 + { CCI_REG8(0x3e95), 0xcd }, { CCI_REG8(0x3e96), 0xcd },
2392 + { CCI_REG8(0x3e97), 0xcd }, { CCI_REG8(0x3e98), 0xcd },
2393 + { CCI_REG8(0x3e99), 0xcd }, { CCI_REG8(0x3e9a), 0xcd },
2394 + { CCI_REG8(0x3e9b), 0xcd }, { CCI_REG8(0x3e9c), 0xcd },
2395 + { CCI_REG8(0x3e9d), 0xcd }, { CCI_REG8(0x3e9e), 0xcd },
2396 + { CCI_REG8(0x3e9f), 0xcd }, { CCI_REG8(0xfff9), 0x06 },
2397 + { CCI_REG8(0xc03f), 0x01 }, { CCI_REG8(0xc03e), 0x08 },
2398 + { CCI_REG8(0xc02c), 0xff }, { CCI_REG8(0xc005), 0x06 },
2399 + { CCI_REG8(0xc006), 0x30 }, { CCI_REG8(0xc007), 0xc0 },
2400 + { CCI_REG8(0xc027), 0x01 }, { CCI_REG8(0x30c0), 0x05 },
2401 + { CCI_REG8(0x30c1), 0x9f }, { CCI_REG8(0x30c2), 0x06 },
2402 + { CCI_REG8(0x30c3), 0x5f }, { CCI_REG8(0x30c4), 0x80 },
2403 + { CCI_REG8(0x30c5), 0x08 }, { CCI_REG8(0x30c6), 0x39 },
2404 + { CCI_REG8(0x30c7), 0x00 }, { CCI_REG8(0xc046), 0x20 },
2405 + { CCI_REG8(0xc043), 0x01 }, { CCI_REG8(0xc04b), 0x01 },
2406 + { CCI_REG8(0x0102), 0x01 }, { CCI_REG8(0x0100), 0x00 },
2407 + { CCI_REG8(0x0102), 0x00 }, { CCI_REG8(0x3015), 0xf0 },
2408 + { CCI_REG8(0x3018), 0xf0 }, { CCI_REG8(0x301c), 0xf0 },
2409 + { CCI_REG8(0x301d), 0xf6 }, { CCI_REG8(0x301e), 0xf1 }
2412 +static const struct cci_reg_sequence ov64a40_9248x6944[] = {
2413 + { CCI_REG8(0x0305), 0x98 }, { CCI_REG8(0x0306), 0x04 },
2414 + { CCI_REG8(0x0307), 0x01 }, { CCI_REG8(0x4837), 0x1a },
2415 + { CCI_REG8(0x4888), 0x10 }, { CCI_REG8(0x4860), 0x00 },
2416 + { CCI_REG8(0x4850), 0x43 }, { CCI_REG8(0x480C), 0x92 },
2417 + { CCI_REG8(0x5001), 0x21 }
2420 +static const struct cci_reg_sequence ov64a40_8000x6000[] = {
2421 + { CCI_REG8(0x0305), 0x98 }, { CCI_REG8(0x0306), 0x04 },
2422 + { CCI_REG8(0x0307), 0x01 }, { CCI_REG8(0x4837), 0x1a },
2423 + { CCI_REG8(0x4888), 0x10 }, { CCI_REG8(0x4860), 0x00 },
2424 + { CCI_REG8(0x4850), 0x43 }, { CCI_REG8(0x480C), 0x92 },
2425 + { CCI_REG8(0x5001), 0x21 }
2428 +static const struct cci_reg_sequence ov64a40_4624_3472[] = {
2429 + { CCI_REG8(0x034b), 0x02 }, { CCI_REG8(0x3504), 0x08 },
2430 + { CCI_REG8(0x360d), 0x82 }, { CCI_REG8(0x368a), 0x2e },
2431 + { CCI_REG8(0x3712), 0x50 }, { CCI_REG8(0x3822), 0x00 },
2432 + { CCI_REG8(0x3827), 0x40 }, { CCI_REG8(0x383d), 0x08 },
2433 + { CCI_REG8(0x383f), 0x00 }, { CCI_REG8(0x384c), 0x02 },
2434 + { CCI_REG8(0x384d), 0xba }, { CCI_REG8(0x3852), 0x00 },
2435 + { CCI_REG8(0x3856), 0x08 }, { CCI_REG8(0x3857), 0x08 },
2436 + { CCI_REG8(0x3858), 0x10 }, { CCI_REG8(0x3859), 0x10 },
2437 + { CCI_REG8(0x4016), 0x0f }, { CCI_REG8(0x4018), 0x03 },
2438 + { CCI_REG8(0x4504), 0x1e }, { CCI_REG8(0x4523), 0x41 },
2439 + { CCI_REG8(0x45c0), 0x01 }, { CCI_REG8(0x4641), 0x12 },
2440 + { CCI_REG8(0x4643), 0x0c }, { CCI_REG8(0x4915), 0x02 },
2441 + { CCI_REG8(0x4916), 0x1d }, { CCI_REG8(0x4a15), 0x02 },
2442 + { CCI_REG8(0x4a16), 0x1d }, { CCI_REG8(0x3703), 0x72 },
2443 + { CCI_REG8(0x3709), 0xe6 }, { CCI_REG8(0x3a60), 0x68 },
2444 + { CCI_REG8(0x3a6f), 0x68 }, { CCI_REG8(0x3a5e), 0xdc },
2445 + { CCI_REG8(0x3a6d), 0xdc }, { CCI_REG8(0x3721), 0xc9 },
2446 + { CCI_REG8(0x5250), 0x06 }, { CCI_REG8(0x527a), 0x00 },
2447 + { CCI_REG8(0x527b), 0x65 }, { CCI_REG8(0x527c), 0x00 },
2448 + { CCI_REG8(0x527d), 0x82 }, { CCI_REG8(0x5280), 0x24 },
2449 + { CCI_REG8(0x5281), 0x40 }, { CCI_REG8(0x5282), 0x1b },
2450 + { CCI_REG8(0x5283), 0x40 }, { CCI_REG8(0x5284), 0x24 },
2451 + { CCI_REG8(0x5285), 0x40 }, { CCI_REG8(0x5286), 0x1b },
2452 + { CCI_REG8(0x5287), 0x40 }, { CCI_REG8(0x5200), 0x24 },
2453 + { CCI_REG8(0x5201), 0x40 }, { CCI_REG8(0x5202), 0x1b },
2454 + { CCI_REG8(0x5203), 0x40 }, { CCI_REG8(0x481b), 0x35 },
2455 + { CCI_REG8(0x4862), 0x25 }, { CCI_REG8(0x3400), 0x00 },
2456 + { CCI_REG8(0x3421), 0x23 }, { CCI_REG8(0x3422), 0xfc },
2457 + { CCI_REG8(0x3423), 0x07 }, { CCI_REG8(0x3424), 0x01 },
2458 + { CCI_REG8(0x3425), 0x04 }, { CCI_REG8(0x3426), 0x50 },
2459 + { CCI_REG8(0x3427), 0x55 }, { CCI_REG8(0x3428), 0x15 },
2460 + { CCI_REG8(0x3429), 0x00 }, { CCI_REG8(0x3025), 0x03 },
2461 + { CCI_REG8(0x5250), 0x06 }, { CCI_REG8(0x0305), 0x98 },
2462 + { CCI_REG8(0x0306), 0x04 }, { CCI_REG8(0x0307), 0x01 },
2463 + { CCI_REG8(0x4837), 0x1a }, { CCI_REG8(0x4888), 0x10 },
2464 + { CCI_REG8(0x4860), 0x00 }, { CCI_REG8(0x4850), 0x43 },
2465 + { CCI_REG8(0x480C), 0x92 }, { CCI_REG8(0x5001), 0x21 }
2468 +static const struct cci_reg_sequence ov64a40_3840x2160[] = {
2469 + { CCI_REG8(0x034a), 0x05 }, { CCI_REG8(0x034b), 0x05 },
2470 + { CCI_REG8(0x3504), 0x08 }, { CCI_REG8(0x360d), 0x82 },
2471 + { CCI_REG8(0x368a), 0x2e }, { CCI_REG8(0x3712), 0x50 },
2472 + { CCI_REG8(0x3822), 0x00 }, { CCI_REG8(0x3827), 0x40 },
2473 + { CCI_REG8(0x383d), 0x08 }, { CCI_REG8(0x383f), 0x00 },
2474 + { CCI_REG8(0x384c), 0x02 }, { CCI_REG8(0x384d), 0xba },
2475 + { CCI_REG8(0x3852), 0x00 }, { CCI_REG8(0x3856), 0x08 },
2476 + { CCI_REG8(0x3857), 0x08 }, { CCI_REG8(0x3858), 0x10 },
2477 + { CCI_REG8(0x3859), 0x10 }, { CCI_REG8(0x4016), 0x0f },
2478 + { CCI_REG8(0x4018), 0x03 }, { CCI_REG8(0x4504), 0x1e },
2479 + { CCI_REG8(0x4523), 0x41 }, { CCI_REG8(0x45c0), 0x01 },
2480 + { CCI_REG8(0x4641), 0x12 }, { CCI_REG8(0x4643), 0x0c },
2481 + { CCI_REG8(0x4915), 0x02 }, { CCI_REG8(0x4916), 0x1d },
2482 + { CCI_REG8(0x4a15), 0x02 }, { CCI_REG8(0x4a16), 0x1d },
2483 + { CCI_REG8(0x3703), 0x72 }, { CCI_REG8(0x3709), 0xe6 },
2484 + { CCI_REG8(0x3a60), 0x68 }, { CCI_REG8(0x3a6f), 0x68 },
2485 + { CCI_REG8(0x3a5e), 0xdc }, { CCI_REG8(0x3a6d), 0xdc },
2486 + { CCI_REG8(0x3721), 0xc9 }, { CCI_REG8(0x5250), 0x06 },
2487 + { CCI_REG8(0x527a), 0x00 }, { CCI_REG8(0x527b), 0x65 },
2488 + { CCI_REG8(0x527c), 0x00 }, { CCI_REG8(0x527d), 0x82 },
2489 + { CCI_REG8(0x5280), 0x24 }, { CCI_REG8(0x5281), 0x40 },
2490 + { CCI_REG8(0x5282), 0x1b }, { CCI_REG8(0x5283), 0x40 },
2491 + { CCI_REG8(0x5284), 0x24 }, { CCI_REG8(0x5285), 0x40 },
2492 + { CCI_REG8(0x5286), 0x1b }, { CCI_REG8(0x5287), 0x40 },
2493 + { CCI_REG8(0x5200), 0x24 }, { CCI_REG8(0x5201), 0x40 },
2494 + { CCI_REG8(0x5202), 0x1b }, { CCI_REG8(0x5203), 0x40 },
2495 + { CCI_REG8(0x481b), 0x35 }, { CCI_REG8(0x4862), 0x25 },
2496 + { CCI_REG8(0x3400), 0x00 }, { CCI_REG8(0x3421), 0x23 },
2497 + { CCI_REG8(0x3422), 0xfc }, { CCI_REG8(0x3423), 0x07 },
2498 + { CCI_REG8(0x3424), 0x01 }, { CCI_REG8(0x3425), 0x04 },
2499 + { CCI_REG8(0x3426), 0x50 }, { CCI_REG8(0x3427), 0x55 },
2500 + { CCI_REG8(0x3428), 0x15 }, { CCI_REG8(0x3429), 0x00 },
2501 + { CCI_REG8(0x3025), 0x03 }, { CCI_REG8(0x5250), 0x06 },
2502 + { CCI_REG8(0x0305), 0x98 }, { CCI_REG8(0x0306), 0x04 },
2503 + { CCI_REG8(0x0345), 0x90 }, { CCI_REG8(0x0307), 0x01 },
2504 + { CCI_REG8(0x4837), 0x1a }, { CCI_REG8(0x4888), 0x10 },
2505 + { CCI_REG8(0x4860), 0x00 }, { CCI_REG8(0x4850), 0x43 },
2506 + { CCI_REG8(0x480C), 0x92 }, { CCI_REG8(0x5001), 0x21 },
2507 + { CCI_REG8(0x5000), 0x01 }
2510 +static const struct cci_reg_sequence ov64a40_2312_1736[] = {
2511 + { CCI_REG8(0x034b), 0x02 }, { CCI_REG8(0x3504), 0x08 },
2512 + { CCI_REG8(0x360d), 0x82 }, { CCI_REG8(0x368a), 0x2e },
2513 + { CCI_REG8(0x3712), 0x00 }, { CCI_REG8(0x3822), 0x08 },
2514 + { CCI_REG8(0x3827), 0x40 }, { CCI_REG8(0x383d), 0x04 },
2515 + { CCI_REG8(0x383f), 0x00 }, { CCI_REG8(0x384c), 0x01 },
2516 + { CCI_REG8(0x384d), 0x12 }, { CCI_REG8(0x3852), 0x00 },
2517 + { CCI_REG8(0x3856), 0x04 }, { CCI_REG8(0x3857), 0x04 },
2518 + { CCI_REG8(0x3858), 0x08 }, { CCI_REG8(0x3859), 0x08 },
2519 + { CCI_REG8(0x4016), 0x07 }, { CCI_REG8(0x4018), 0x01 },
2520 + { CCI_REG8(0x4504), 0x00 }, { CCI_REG8(0x4523), 0x00 },
2521 + { CCI_REG8(0x45c0), 0x01 }, { CCI_REG8(0x4641), 0x24 },
2522 + { CCI_REG8(0x4643), 0x0c }, { CCI_REG8(0x4837), 0x0b },
2523 + { CCI_REG8(0x4915), 0x02 }, { CCI_REG8(0x4916), 0x1d },
2524 + { CCI_REG8(0x4a15), 0x02 }, { CCI_REG8(0x4a16), 0x1d },
2525 + { CCI_REG8(0x5000), 0x55 }, { CCI_REG8(0x5001), 0x00 },
2526 + { CCI_REG8(0x5002), 0x35 }, { CCI_REG8(0x5004), 0xc0 },
2527 + { CCI_REG8(0x5068), 0x02 }, { CCI_REG8(0x3703), 0x6a },
2528 + { CCI_REG8(0x3709), 0xa3 }, { CCI_REG8(0x3a60), 0x60 },
2529 + { CCI_REG8(0x3a6f), 0x60 }, { CCI_REG8(0x3a5e), 0x99 },
2530 + { CCI_REG8(0x3a6d), 0x99 }, { CCI_REG8(0x3721), 0xc1 },
2531 + { CCI_REG8(0x5250), 0x06 }, { CCI_REG8(0x527a), 0x00 },
2532 + { CCI_REG8(0x527b), 0x65 }, { CCI_REG8(0x527c), 0x00 },
2533 + { CCI_REG8(0x527d), 0x82 }, { CCI_REG8(0x5280), 0x24 },
2534 + { CCI_REG8(0x5281), 0x40 }, { CCI_REG8(0x5282), 0x1b },
2535 + { CCI_REG8(0x5283), 0x40 }, { CCI_REG8(0x5284), 0x24 },
2536 + { CCI_REG8(0x5285), 0x40 }, { CCI_REG8(0x5286), 0x1b },
2537 + { CCI_REG8(0x5287), 0x40 }, { CCI_REG8(0x5200), 0x24 },
2538 + { CCI_REG8(0x5201), 0x40 }, { CCI_REG8(0x5202), 0x1b },
2539 + { CCI_REG8(0x5203), 0x40 }, { CCI_REG8(0x3684), 0x05 },
2540 + { CCI_REG8(0x481b), 0x20 }, { CCI_REG8(0x51b0), 0x38 },
2541 + { CCI_REG8(0x51b3), 0x0e }, { CCI_REG8(0x51b5), 0x04 },
2542 + { CCI_REG8(0x51b6), 0x00 }, { CCI_REG8(0x51b7), 0x00 },
2543 + { CCI_REG8(0x51b9), 0x70 }, { CCI_REG8(0x51bb), 0x10 },
2544 + { CCI_REG8(0x51bc), 0x00 }, { CCI_REG8(0x51bd), 0x00 },
2545 + { CCI_REG8(0x51b0), 0x38 }, { CCI_REG8(0x54b0), 0x38 },
2546 + { CCI_REG8(0x54b3), 0x0e }, { CCI_REG8(0x54b5), 0x04 },
2547 + { CCI_REG8(0x54b6), 0x00 }, { CCI_REG8(0x54b7), 0x00 },
2548 + { CCI_REG8(0x54b9), 0x70 }, { CCI_REG8(0x54bb), 0x10 },
2549 + { CCI_REG8(0x54bc), 0x00 }, { CCI_REG8(0x54bd), 0x00 },
2550 + { CCI_REG8(0x57b0), 0x38 }, { CCI_REG8(0x57b3), 0x0e },
2551 + { CCI_REG8(0x57b5), 0x04 }, { CCI_REG8(0x57b6), 0x00 },
2552 + { CCI_REG8(0x57b7), 0x00 }, { CCI_REG8(0x57b9), 0x70 },
2553 + { CCI_REG8(0x57bb), 0x10 }, { CCI_REG8(0x57bc), 0x00 },
2554 + { CCI_REG8(0x57bd), 0x00 }, { CCI_REG8(0x0305), 0x98 },
2555 + { CCI_REG8(0x0306), 0x04 }, { CCI_REG8(0x0307), 0x01 },
2556 + { CCI_REG8(0x4837), 0x1a }, { CCI_REG8(0x4888), 0x10 },
2557 + { CCI_REG8(0x4860), 0x00 }, { CCI_REG8(0x4850), 0x43 },
2558 + { CCI_REG8(0x480C), 0x92 }
2561 +static const struct cci_reg_sequence ov64a40_1920x1080[] = {
2562 + { CCI_REG8(0x034b), 0x02 }, { CCI_REG8(0x3504), 0x08 },
2563 + { CCI_REG8(0x360d), 0x82 }, { CCI_REG8(0x368a), 0x2e },
2564 + { CCI_REG8(0x3712), 0x00 }, { CCI_REG8(0x3822), 0x08 },
2565 + { CCI_REG8(0x3827), 0x40 }, { CCI_REG8(0x383d), 0x04 },
2566 + { CCI_REG8(0x383f), 0x00 }, { CCI_REG8(0x384c), 0x01 },
2567 + { CCI_REG8(0x384d), 0x12 }, { CCI_REG8(0x3852), 0x00 },
2568 + { CCI_REG8(0x3856), 0x04 }, { CCI_REG8(0x3857), 0x04 },
2569 + { CCI_REG8(0x3858), 0x08 }, { CCI_REG8(0x3859), 0x08 },
2570 + { CCI_REG8(0x4016), 0x07 }, { CCI_REG8(0x4018), 0x01 },
2571 + { CCI_REG8(0x4504), 0x00 }, { CCI_REG8(0x4523), 0x00 },
2572 + { CCI_REG8(0x45c0), 0x01 }, { CCI_REG8(0x4641), 0x24 },
2573 + { CCI_REG8(0x4643), 0x0c }, { CCI_REG8(0x4837), 0x0b },
2574 + { CCI_REG8(0x4915), 0x02 }, { CCI_REG8(0x4916), 0x1d },
2575 + { CCI_REG8(0x4a15), 0x02 }, { CCI_REG8(0x4a16), 0x1d },
2576 + { CCI_REG8(0x5000), 0x55 }, { CCI_REG8(0x5001), 0x00 },
2577 + { CCI_REG8(0x5002), 0x35 }, { CCI_REG8(0x5004), 0xc0 },
2578 + { CCI_REG8(0x5068), 0x02 }, { CCI_REG8(0x3703), 0x6a },
2579 + { CCI_REG8(0x3709), 0xa3 }, { CCI_REG8(0x3a60), 0x60 },
2580 + { CCI_REG8(0x3a6f), 0x60 }, { CCI_REG8(0x3a5e), 0x99 },
2581 + { CCI_REG8(0x3a6d), 0x99 }, { CCI_REG8(0x3721), 0xc1 },
2582 + { CCI_REG8(0x5250), 0x06 }, { CCI_REG8(0x527a), 0x00 },
2583 + { CCI_REG8(0x527b), 0x65 }, { CCI_REG8(0x527c), 0x00 },
2584 + { CCI_REG8(0x527d), 0x82 }, { CCI_REG8(0x5280), 0x24 },
2585 + { CCI_REG8(0x5281), 0x40 }, { CCI_REG8(0x5282), 0x1b },
2586 + { CCI_REG8(0x5283), 0x40 }, { CCI_REG8(0x5284), 0x24 },
2587 + { CCI_REG8(0x5285), 0x40 }, { CCI_REG8(0x5286), 0x1b },
2588 + { CCI_REG8(0x5287), 0x40 }, { CCI_REG8(0x5200), 0x24 },
2589 + { CCI_REG8(0x5201), 0x40 }, { CCI_REG8(0x5202), 0x1b },
2590 + { CCI_REG8(0x5203), 0x40 }, { CCI_REG8(0x3684), 0x05 },
2591 + { CCI_REG8(0x481b), 0x20 }, { CCI_REG8(0x51b0), 0x38 },
2592 + { CCI_REG8(0x51b3), 0x0e }, { CCI_REG8(0x51b5), 0x04 },
2593 + { CCI_REG8(0x51b6), 0x00 }, { CCI_REG8(0x51b7), 0x00 },
2594 + { CCI_REG8(0x51b9), 0x70 }, { CCI_REG8(0x51bb), 0x10 },
2595 + { CCI_REG8(0x51bc), 0x00 }, { CCI_REG8(0x51bd), 0x00 },
2596 + { CCI_REG8(0x51b0), 0x38 }, { CCI_REG8(0x54b0), 0x38 },
2597 + { CCI_REG8(0x54b3), 0x0e }, { CCI_REG8(0x54b5), 0x04 },
2598 + { CCI_REG8(0x54b6), 0x00 }, { CCI_REG8(0x54b7), 0x00 },
2599 + { CCI_REG8(0x54b9), 0x70 }, { CCI_REG8(0x54bb), 0x10 },
2600 + { CCI_REG8(0x54bc), 0x00 }, { CCI_REG8(0x54bd), 0x00 },
2601 + { CCI_REG8(0x57b0), 0x38 }, { CCI_REG8(0x57b3), 0x0e },
2602 + { CCI_REG8(0x57b5), 0x04 }, { CCI_REG8(0x57b6), 0x00 },
2603 + { CCI_REG8(0x57b7), 0x00 }, { CCI_REG8(0x57b9), 0x70 },
2604 + { CCI_REG8(0x57bb), 0x10 }, { CCI_REG8(0x57bc), 0x00 },
2605 + { CCI_REG8(0x57bd), 0x00 }, { CCI_REG8(0x0305), 0x98 },
2606 + { CCI_REG8(0x0306), 0x04 }, { CCI_REG8(0x0307), 0x01 },
2607 + { CCI_REG8(0x4837), 0x1a }, { CCI_REG8(0x4888), 0x10 },
2608 + { CCI_REG8(0x4860), 0x00 }, { CCI_REG8(0x4850), 0x43 },
2609 + { CCI_REG8(0x480C), 0x92 }
2612 +/* 456MHz MIPI link frequency with 24MHz input clock. */
2613 +static const struct cci_reg_sequence ov64a40_pll_config[] = {
2614 + { OV64A40_PLL1_PRE_DIV0, 0x88 },
2615 + { OV64A40_PLL1_PRE_DIV, 0x02 },
2616 + { OV64A40_PLL1_MULTIPLIER, 0x0098 },
2617 + { OV64A40_PLL1_M_DIV, 0x01 },
2618 + { OV64A40_PLL2_SEL_BAK_SA1, 0x00 },
2619 + { OV64A40_PLL2_PRE_DIV, 0x12 },
2620 + { OV64A40_PLL2_MULTIPLIER, 0x0190 },
2621 + { OV64A40_PLL2_PRE_DIV0, 0xd7 },
2622 + { OV64A40_PLL2_DIVSP, 0x00 },
2623 + { OV64A40_PLL2_DIVDAC, 0x00 },
2624 + { OV64A40_PLL2_DACPREDIV, 0x00 }
2627 +struct ov64a40_reglist {
2628 + unsigned int num_regs;
2629 + const struct cci_reg_sequence *regvals;
2632 +struct ov64a40_subsampling {
2633 + unsigned int x_odd_inc;
2634 + unsigned int x_even_inc;
2635 + unsigned int y_odd_inc;
2636 + unsigned int y_even_inc;
2641 +static struct ov64a40_mode {
2642 + unsigned int width;
2643 + unsigned int height;
2644 + struct ov64a40_timings {
2647 + } timings_default[OV64A40_NUM_LINK_FREQ];
2648 + const struct ov64a40_reglist reglist;
2649 + struct v4l2_rect analogue_crop;
2650 + struct v4l2_rect digital_crop;
2651 + struct ov64a40_subsampling subsampling;
2652 +} ov64a40_modes[] = {
2653 + /* Full resolution */
2657 + .timings_default = {
2659 + [OV64A40_LINK_FREQ_456M_ID] = {
2664 + [OV64A40_LINK_FREQ_360M_ID] = {
2670 + .num_regs = ARRAY_SIZE(ov64a40_9248x6944),
2671 + .regvals = ov64a40_9248x6944,
2673 + .analogue_crop = {
2694 + /* Analogue crop + digital crop */
2698 + .timings_default = {
2700 + [OV64A40_LINK_FREQ_456M_ID] = {
2705 + [OV64A40_LINK_FREQ_360M_ID] = {
2711 + .num_regs = ARRAY_SIZE(ov64a40_8000x6000),
2712 + .regvals = ov64a40_8000x6000,
2714 + .analogue_crop = {
2735 + /* 2x2 downscaled */
2739 + .timings_default = {
2741 + [OV64A40_LINK_FREQ_456M_ID] = {
2746 + [OV64A40_LINK_FREQ_360M_ID] = {
2752 + .num_regs = ARRAY_SIZE(ov64a40_4624_3472),
2753 + .regvals = ov64a40_4624_3472,
2755 + .analogue_crop = {
2776 + /* Analogue crop + 2x2 downscale + digital crop */
2780 + .timings_default = {
2782 + [OV64A40_LINK_FREQ_456M_ID] = {
2787 + [OV64A40_LINK_FREQ_360M_ID] = {
2793 + .num_regs = ARRAY_SIZE(ov64a40_3840x2160),
2794 + .regvals = ov64a40_3840x2160,
2796 + .analogue_crop = {
2817 + /* 4x4 downscaled */
2821 + .timings_default = {
2823 + [OV64A40_LINK_FREQ_456M_ID] = {
2828 + [OV64A40_LINK_FREQ_360M_ID] = {
2834 + .num_regs = ARRAY_SIZE(ov64a40_2312_1736),
2835 + .regvals = ov64a40_2312_1736,
2837 + .analogue_crop = {
2858 + /* Analogue crop + 4x4 downscale + digital crop */
2862 + .timings_default = {
2864 + [OV64A40_LINK_FREQ_456M_ID] = {
2869 + [OV64A40_LINK_FREQ_360M_ID] = {
2875 + .num_regs = ARRAY_SIZE(ov64a40_1920x1080),
2876 + .regvals = ov64a40_1920x1080,
2878 + .analogue_crop = {
2902 + struct device *dev;
2904 + struct v4l2_subdev sd;
2905 + struct media_pad pad;
2907 + struct regmap *cci;
2909 + struct ov64a40_mode *mode;
2913 + struct gpio_desc *reset_gpio;
2914 + struct regulator_bulk_data supplies[ARRAY_SIZE(ov64a40_supply_names)];
2916 + s64 *link_frequencies;
2917 + unsigned int num_link_frequencies;
2919 + struct v4l2_ctrl_handler ctrl_handler;
2920 + struct v4l2_ctrl *exposure;
2921 + struct v4l2_ctrl *link_freq;
2922 + struct v4l2_ctrl *vblank;
2923 + struct v4l2_ctrl *hblank;
2924 + struct v4l2_ctrl *vflip;
2925 + struct v4l2_ctrl *hflip;
2928 +static inline struct ov64a40 *sd_to_ov64a40(struct v4l2_subdev *sd)
2930 + return container_of(sd, struct ov64a40, sd);
2933 +static const struct ov64a40_timings *
2934 +ov64a40_get_timings(struct ov64a40 *ov64a40, unsigned int link_freq_index)
2936 + s64 link_freq = ov64a40->link_frequencies[link_freq_index];
2937 + unsigned int timings_index = link_freq == OV64A40_LINK_FREQ_360M
2938 + ? OV64A40_LINK_FREQ_360M_ID
2939 + : OV64A40_LINK_FREQ_456M_ID;
2941 + return &ov64a40->mode->timings_default[timings_index];
2944 +static int ov64a40_program_geometry(struct ov64a40 *ov64a40)
2946 + struct ov64a40_mode *mode = ov64a40->mode;
2947 + struct v4l2_rect *anacrop = &mode->analogue_crop;
2948 + struct v4l2_rect *digicrop = &mode->digital_crop;
2949 + const struct ov64a40_timings *timings;
2952 + /* Analogue crop. */
2953 + cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRL0,
2954 + anacrop->left, &ret);
2955 + cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRL2,
2956 + anacrop->top, &ret);
2957 + cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRL4,
2958 + anacrop->width + anacrop->left, &ret);
2959 + cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRL6,
2960 + anacrop->height + anacrop->top, &ret);
2962 + /* ISP windowing. */
2963 + cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRL10,
2964 + digicrop->left, &ret);
2965 + cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRL12,
2966 + digicrop->top, &ret);
2967 + cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRL8,
2968 + digicrop->width, &ret);
2969 + cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRLA,
2970 + digicrop->height, &ret);
2972 + /* Total timings. */
2973 + timings = ov64a40_get_timings(ov64a40, ov64a40->link_freq->cur.val);
2974 + cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRLC, timings->ppl, &ret);
2975 + cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRLE, timings->vts, &ret);
2980 +static int ov64a40_program_subsampling(struct ov64a40 *ov64a40)
2982 + struct ov64a40_subsampling *subsampling = &ov64a40->mode->subsampling;
2985 + /* Skipping configuration */
2986 + cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRL14,
2987 + OV64A40_SKIPPING_CONFIG(subsampling->x_odd_inc,
2988 + subsampling->x_even_inc), &ret);
2989 + cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRL15,
2990 + OV64A40_SKIPPING_CONFIG(subsampling->y_odd_inc,
2991 + subsampling->y_even_inc), &ret);
2993 + /* Binning configuration */
2994 + cci_update_bits(ov64a40->cci, OV64A40_REG_TIMING_CTRL_20,
2995 + OV64A40_TIMING_CTRL_20_VBIN,
2996 + subsampling->vbin ? OV64A40_TIMING_CTRL_20_VBIN : 0,
2998 + cci_update_bits(ov64a40->cci, OV64A40_REG_TIMING_CTRL_21,
2999 + OV64A40_TIMING_CTRL_21_HBIN_CONF,
3000 + subsampling->hbin ?
3001 + OV64A40_TIMING_CTRL_21_HBIN_CONF : 0, &ret);
3006 +static int ov64a40_start_streaming(struct ov64a40 *ov64a40,
3007 + struct v4l2_subdev_state *state)
3009 + const struct ov64a40_reglist *reglist = &ov64a40->mode->reglist;
3010 + const struct ov64a40_timings *timings;
3011 + unsigned long delay;
3014 + ret = pm_runtime_resume_and_get(ov64a40->dev);
3018 + ret = cci_multi_reg_write(ov64a40->cci, ov64a40_init,
3019 + ARRAY_SIZE(ov64a40_init), NULL);
3021 + goto error_power_off;
3023 + ret = cci_multi_reg_write(ov64a40->cci, reglist->regvals,
3024 + reglist->num_regs, NULL);
3026 + goto error_power_off;
3028 + ret = ov64a40_program_geometry(ov64a40);
3030 + goto error_power_off;
3032 + ret = ov64a40_program_subsampling(ov64a40);
3034 + goto error_power_off;
3036 + ret = __v4l2_ctrl_handler_setup(&ov64a40->ctrl_handler);
3038 + goto error_power_off;
3040 + ret = cci_write(ov64a40->cci, OV64A40_REG_SMIA,
3041 + OV64A40_REG_SMIA_STREAMING, NULL);
3043 + goto error_power_off;
3045 + /* Link frequency and flips cannot change while streaming. */
3046 + __v4l2_ctrl_grab(ov64a40->link_freq, true);
3047 + __v4l2_ctrl_grab(ov64a40->vflip, true);
3048 + __v4l2_ctrl_grab(ov64a40->hflip, true);
3050 + /* delay: max(4096 xclk pulses, 150usec) + exposure time */
3051 + timings = ov64a40_get_timings(ov64a40, ov64a40->link_freq->cur.val);
3052 + delay = DIV_ROUND_UP(4096, OV64A40_XCLK_FREQ / 1000 / 1000);
3053 + delay = max(delay, 150ul);
3055 + /* The sensor has an internal x4 multiplier on the line length. */
3056 + delay += DIV_ROUND_UP(timings->ppl * 4 * ov64a40->exposure->cur.val,
3057 + OV64A40_PIXEL_RATE / 1000 / 1000);
3063 + pm_runtime_mark_last_busy(ov64a40->dev);
3064 + pm_runtime_put_autosuspend(ov64a40->dev);
3069 +static int ov64a40_stop_streaming(struct ov64a40 *ov64a40,
3070 + struct v4l2_subdev_state *state)
3072 + cci_update_bits(ov64a40->cci, OV64A40_REG_SMIA, BIT(0), 0, NULL);
3073 + pm_runtime_mark_last_busy(ov64a40->dev);
3074 + pm_runtime_put_autosuspend(ov64a40->dev);
3076 + __v4l2_ctrl_grab(ov64a40->link_freq, false);
3077 + __v4l2_ctrl_grab(ov64a40->vflip, false);
3078 + __v4l2_ctrl_grab(ov64a40->hflip, false);
3083 +static int ov64a40_set_stream(struct v4l2_subdev *sd, int enable)
3085 + struct ov64a40 *ov64a40 = sd_to_ov64a40(sd);
3086 + struct v4l2_subdev_state *state;
3089 + state = v4l2_subdev_lock_and_get_active_state(sd);
3091 + ret = ov64a40_start_streaming(ov64a40, state);
3093 + ret = ov64a40_stop_streaming(ov64a40, state);
3094 + v4l2_subdev_unlock_state(state);
3099 +static const struct v4l2_subdev_video_ops ov64a40_video_ops = {
3100 + .s_stream = ov64a40_set_stream,
3103 +static u32 ov64a40_mbus_code(struct ov64a40 *ov64a40)
3105 + unsigned int index = ov64a40->hflip->val << 1 | ov64a40->vflip->val;
3107 + return ov64a40_mbus_codes[index];
3110 +static void ov64a40_update_pad_fmt(struct ov64a40 *ov64a40,
3111 + struct ov64a40_mode *mode,
3112 + struct v4l2_mbus_framefmt *fmt)
3114 + fmt->code = ov64a40_mbus_code(ov64a40);
3115 + fmt->width = mode->width;
3116 + fmt->height = mode->height;
3117 + fmt->field = V4L2_FIELD_NONE;
3118 + fmt->colorspace = V4L2_COLORSPACE_RAW;
3119 + fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE;
3120 + fmt->xfer_func = V4L2_XFER_FUNC_NONE;
3121 + fmt->ycbcr_enc = V4L2_YCBCR_ENC_601;
3124 +static int ov64a40_init_cfg(struct v4l2_subdev *sd,
3125 + struct v4l2_subdev_state *state)
3127 + struct ov64a40 *ov64a40 = sd_to_ov64a40(sd);
3128 + struct v4l2_mbus_framefmt *format;
3129 + struct v4l2_rect *crop;
3131 + format = v4l2_subdev_get_pad_format(sd, state, 0);
3132 + ov64a40_update_pad_fmt(ov64a40, &ov64a40_modes[0], format);
3134 + crop = v4l2_subdev_get_pad_crop(sd, state, 0);
3135 + crop->top = OV64A40_PIXEL_ARRAY_TOP;
3136 + crop->left = OV64A40_PIXEL_ARRAY_LEFT;
3137 + crop->width = OV64A40_PIXEL_ARRAY_WIDTH;
3138 + crop->height = OV64A40_PIXEL_ARRAY_HEIGHT;
3143 +static int ov64a40_enum_mbus_code(struct v4l2_subdev *sd,
3144 + struct v4l2_subdev_state *sd_state,
3145 + struct v4l2_subdev_mbus_code_enum *code)
3147 + struct ov64a40 *ov64a40 = sd_to_ov64a40(sd);
3152 + code->code = ov64a40_mbus_code(ov64a40);
3157 +static int ov64a40_enum_frame_size(struct v4l2_subdev *sd,
3158 + struct v4l2_subdev_state *sd_state,
3159 + struct v4l2_subdev_frame_size_enum *fse)
3161 + struct ov64a40 *ov64a40 = sd_to_ov64a40(sd);
3162 + struct ov64a40_mode *mode;
3165 + if (fse->index >= ARRAY_SIZE(ov64a40_modes))
3168 + code = ov64a40_mbus_code(ov64a40);
3169 + if (fse->code != code)
3172 + mode = &ov64a40_modes[fse->index];
3173 + fse->min_width = mode->width;
3174 + fse->max_width = mode->width;
3175 + fse->min_height = mode->height;
3176 + fse->max_height = mode->height;
3181 +static int ov64a40_get_selection(struct v4l2_subdev *sd,
3182 + struct v4l2_subdev_state *sd_state,
3183 + struct v4l2_subdev_selection *sel)
3185 + switch (sel->target) {
3186 + case V4L2_SEL_TGT_CROP:
3187 + sel->r = *v4l2_subdev_get_pad_crop(sd, sd_state, 0);
3191 + case V4L2_SEL_TGT_NATIVE_SIZE:
3194 + sel->r.width = OV64A40_NATIVE_WIDTH;
3195 + sel->r.height = OV64A40_NATIVE_HEIGHT;
3199 + case V4L2_SEL_TGT_CROP_DEFAULT:
3200 + case V4L2_SEL_TGT_CROP_BOUNDS:
3201 + sel->r.top = OV64A40_PIXEL_ARRAY_TOP;
3202 + sel->r.left = OV64A40_PIXEL_ARRAY_LEFT;
3203 + sel->r.width = OV64A40_PIXEL_ARRAY_WIDTH;
3204 + sel->r.height = OV64A40_PIXEL_ARRAY_HEIGHT;
3212 +static int ov64a40_set_format(struct v4l2_subdev *sd,
3213 + struct v4l2_subdev_state *sd_state,
3214 + struct v4l2_subdev_format *fmt)
3216 + struct ov64a40 *ov64a40 = sd_to_ov64a40(sd);
3217 + struct v4l2_mbus_framefmt *format;
3218 + struct ov64a40_mode *mode;
3220 + mode = v4l2_find_nearest_size(ov64a40_modes,
3221 + ARRAY_SIZE(ov64a40_modes),
3223 + fmt->format.width, fmt->format.height);
3225 + ov64a40_update_pad_fmt(ov64a40, mode, &fmt->format);
3227 + format = v4l2_subdev_get_pad_format(sd, sd_state, 0);
3228 + if (ov64a40->mode == mode && format->code == fmt->format.code)
3231 + if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
3232 + const struct ov64a40_timings *timings;
3233 + int vblank_max, vblank_def;
3237 + ov64a40->mode = mode;
3238 + *v4l2_subdev_get_pad_crop(sd, sd_state, 0) = mode->analogue_crop;
3240 + /* Update control limits according to the new mode. */
3241 + timings = ov64a40_get_timings(ov64a40,
3242 + ov64a40->link_freq->cur.val);
3243 + vblank_max = OV64A40_VTS_MAX - mode->height;
3244 + vblank_def = timings->vts - mode->height;
3245 + __v4l2_ctrl_modify_range(ov64a40->vblank, OV64A40_VBLANK_MIN,
3246 + vblank_max, 1, vblank_def);
3247 + __v4l2_ctrl_s_ctrl(ov64a40->vblank, vblank_def);
3249 + exp_max = timings->vts - OV64A40_EXPOSURE_MARGIN;
3250 + __v4l2_ctrl_modify_range(ov64a40->exposure,
3251 + OV64A40_EXPOSURE_MIN, exp_max,
3252 + 1, OV64A40_EXPOSURE_MIN);
3254 + hblank_val = timings->ppl * 4 - mode->width;
3255 + __v4l2_ctrl_modify_range(ov64a40->hblank,
3256 + hblank_val, hblank_val, 1, hblank_val);
3259 + *format = fmt->format;
3264 +static const struct v4l2_subdev_pad_ops ov64a40_pad_ops = {
3265 + .init_cfg = ov64a40_init_cfg,
3266 + .enum_mbus_code = ov64a40_enum_mbus_code,
3267 + .enum_frame_size = ov64a40_enum_frame_size,
3268 + .get_fmt = v4l2_subdev_get_fmt,
3269 + .set_fmt = ov64a40_set_format,
3270 + .get_selection = ov64a40_get_selection,
3273 +static const struct v4l2_subdev_core_ops ov64a40_core_ops = {
3274 + .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
3275 + .unsubscribe_event = v4l2_event_subdev_unsubscribe,
3278 +static const struct v4l2_subdev_ops ov64a40_subdev_ops = {
3279 + .core = &ov64a40_core_ops,
3280 + .video = &ov64a40_video_ops,
3281 + .pad = &ov64a40_pad_ops,
3284 +static int ov64a40_power_on(struct device *dev)
3286 + struct v4l2_subdev *sd = dev_get_drvdata(dev);
3287 + struct ov64a40 *ov64a40 = sd_to_ov64a40(sd);
3290 + ret = clk_prepare_enable(ov64a40->xclk);
3294 + ret = regulator_bulk_enable(ARRAY_SIZE(ov64a40_supply_names),
3295 + ov64a40->supplies);
3297 + clk_disable_unprepare(ov64a40->xclk);
3298 + dev_err(dev, "Failed to enable regulators: %d\n", ret);
3302 + gpiod_set_value_cansleep(ov64a40->reset_gpio, 0);
3309 +static int ov64a40_power_off(struct device *dev)
3311 + struct v4l2_subdev *sd = dev_get_drvdata(dev);
3312 + struct ov64a40 *ov64a40 = sd_to_ov64a40(sd);
3314 + gpiod_set_value_cansleep(ov64a40->reset_gpio, 1);
3315 + regulator_bulk_disable(ARRAY_SIZE(ov64a40_supply_names),
3316 + ov64a40->supplies);
3317 + clk_disable_unprepare(ov64a40->xclk);
3322 +static int ov64a40_link_freq_config(struct ov64a40 *ov64a40, int link_freq_id)
3324 + s64 link_frequency;
3327 + /* Default 456MHz with 24MHz input clock. */
3328 + cci_multi_reg_write(ov64a40->cci, ov64a40_pll_config,
3329 + ARRAY_SIZE(ov64a40_pll_config), &ret);
3331 + /* Decrease the PLL1 multiplier to obtain 360MHz mipi link frequency. */
3332 + link_frequency = ov64a40->link_frequencies[link_freq_id];
3333 + if (link_frequency == OV64A40_LINK_FREQ_360M)
3334 + cci_write(ov64a40->cci, OV64A40_PLL1_MULTIPLIER, 0x0078, &ret);
3339 +static int ov64a40_set_ctrl(struct v4l2_ctrl *ctrl)
3341 + struct ov64a40 *ov64a40 = container_of(ctrl->handler, struct ov64a40,
3346 + if (ctrl->id == V4L2_CID_VBLANK) {
3347 + int exp_max = ov64a40->mode->height + ctrl->val
3348 + - OV64A40_EXPOSURE_MARGIN;
3349 + int exp_val = min(ov64a40->exposure->cur.val, exp_max);
3351 + __v4l2_ctrl_modify_range(ov64a40->exposure,
3352 + ov64a40->exposure->minimum,
3353 + exp_max, 1, exp_val);
3356 + pm_status = pm_runtime_get_if_active(ov64a40->dev, true);
3360 + switch (ctrl->id) {
3361 + case V4L2_CID_EXPOSURE:
3362 + ret = cci_write(ov64a40->cci, OV64A40_REG_MEC_LONG_EXPO,
3365 + case V4L2_CID_ANALOGUE_GAIN:
3366 + ret = cci_write(ov64a40->cci, OV64A40_REG_MEC_LONG_GAIN,
3367 + ctrl->val << 1, NULL);
3369 + case V4L2_CID_VBLANK: {
3370 + int vts = ctrl->val + ov64a40->mode->height;
3372 + cci_write(ov64a40->cci, OV64A40_REG_TIMINGS_VTS_LOW, vts, &ret);
3373 + cci_write(ov64a40->cci, OV64A40_REG_TIMINGS_VTS_MID,
3374 + (vts >> 8), &ret);
3375 + cci_write(ov64a40->cci, OV64A40_REG_TIMINGS_VTS_HIGH,
3376 + (vts >> 16), &ret);
3379 + case V4L2_CID_VFLIP:
3380 + ret = cci_update_bits(ov64a40->cci, OV64A40_REG_TIMING_CTRL_20,
3381 + OV64A40_TIMING_CTRL_20_VFLIP,
3385 + case V4L2_CID_HFLIP:
3386 + ret = cci_update_bits(ov64a40->cci, OV64A40_REG_TIMING_CTRL_21,
3387 + OV64A40_TIMING_CTRL_21_HFLIP,
3389 + : OV64A40_TIMING_CTRL_21_HFLIP,
3392 + case V4L2_CID_TEST_PATTERN:
3393 + ret = cci_write(ov64a40->cci, OV64A40_REG_TEST_PATTERN,
3394 + ov64a40_test_pattern_val[ctrl->val], NULL);
3396 + case V4L2_CID_LINK_FREQ:
3397 + ret = ov64a40_link_freq_config(ov64a40, ctrl->val);
3400 + dev_err(ov64a40->dev, "Unhandled control: %#x\n", ctrl->id);
3405 + if (pm_status > 0) {
3406 + pm_runtime_mark_last_busy(ov64a40->dev);
3407 + pm_runtime_put_autosuspend(ov64a40->dev);
3413 +static const struct v4l2_ctrl_ops ov64a40_ctrl_ops = {
3414 + .s_ctrl = ov64a40_set_ctrl,
3417 +static int ov64a40_init_controls(struct ov64a40 *ov64a40)
3419 + int exp_max, hblank_val, vblank_max, vblank_def;
3420 + struct v4l2_ctrl_handler *hdlr = &ov64a40->ctrl_handler;
3421 + struct v4l2_fwnode_device_properties props;
3422 + const struct ov64a40_timings *timings;
3425 + ret = v4l2_ctrl_handler_init(hdlr, 11);
3429 + v4l2_ctrl_new_std(hdlr, &ov64a40_ctrl_ops, V4L2_CID_PIXEL_RATE,
3430 + OV64A40_PIXEL_RATE, OV64A40_PIXEL_RATE, 1,
3431 + OV64A40_PIXEL_RATE);
3433 + ov64a40->link_freq =
3434 + v4l2_ctrl_new_int_menu(hdlr, &ov64a40_ctrl_ops,
3435 + V4L2_CID_LINK_FREQ,
3436 + ov64a40->num_link_frequencies - 1,
3437 + 0, ov64a40->link_frequencies);
3439 + v4l2_ctrl_new_std_menu_items(hdlr, &ov64a40_ctrl_ops,
3440 + V4L2_CID_TEST_PATTERN,
3441 + ARRAY_SIZE(ov64a40_test_pattern_menu) - 1,
3442 + 0, 0, ov64a40_test_pattern_menu);
3444 + timings = ov64a40_get_timings(ov64a40, 0);
3445 + exp_max = timings->vts - OV64A40_EXPOSURE_MARGIN;
3446 + ov64a40->exposure = v4l2_ctrl_new_std(hdlr, &ov64a40_ctrl_ops,
3447 + V4L2_CID_EXPOSURE,
3448 + OV64A40_EXPOSURE_MIN, exp_max, 1,
3449 + OV64A40_EXPOSURE_MIN);
3451 + hblank_val = timings->ppl * 4 - ov64a40->mode->width;
3452 + ov64a40->hblank = v4l2_ctrl_new_std(hdlr, &ov64a40_ctrl_ops,
3453 + V4L2_CID_HBLANK, hblank_val,
3454 + hblank_val, 1, hblank_val);
3455 + if (ov64a40->hblank)
3456 + ov64a40->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
3458 + vblank_def = timings->vts - ov64a40->mode->height;
3459 + vblank_max = OV64A40_VTS_MAX - ov64a40->mode->height;
3460 + ov64a40->vblank = v4l2_ctrl_new_std(hdlr, &ov64a40_ctrl_ops,
3461 + V4L2_CID_VBLANK, OV64A40_VBLANK_MIN,
3462 + vblank_max, 1, vblank_def);
3464 + v4l2_ctrl_new_std(hdlr, &ov64a40_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
3465 + OV64A40_ANA_GAIN_MIN, OV64A40_ANA_GAIN_MAX, 1,
3466 + OV64A40_ANA_GAIN_DEFAULT);
3468 + ov64a40->hflip = v4l2_ctrl_new_std(hdlr, &ov64a40_ctrl_ops,
3469 + V4L2_CID_HFLIP, 0, 1, 1, 0);
3470 + if (ov64a40->hflip)
3471 + ov64a40->hflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT;
3473 + ov64a40->vflip = v4l2_ctrl_new_std(hdlr, &ov64a40_ctrl_ops,
3474 + V4L2_CID_VFLIP, 0, 1, 1, 0);
3475 + if (ov64a40->vflip)
3476 + ov64a40->vflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT;
3478 + if (hdlr->error) {
3479 + ret = hdlr->error;
3480 + dev_err(ov64a40->dev, "control init failed: %d\n", ret);
3481 + goto error_free_hdlr;
3484 + ret = v4l2_fwnode_device_parse(ov64a40->dev, &props);
3486 + goto error_free_hdlr;
3488 + ret = v4l2_ctrl_new_fwnode_properties(hdlr, &ov64a40_ctrl_ops,
3491 + goto error_free_hdlr;
3493 + ov64a40->sd.ctrl_handler = hdlr;
3498 + v4l2_ctrl_handler_free(hdlr);
3502 +static int ov64a40_identify(struct ov64a40 *ov64a40)
3507 + ret = cci_read(ov64a40->cci, OV64A40_REG_CHIP_ID, &id, NULL);
3509 + dev_err(ov64a40->dev, "Failed to read chip id: %d\n", ret);
3513 + if (id != OV64A40_CHIP_ID) {
3514 + dev_err(ov64a40->dev, "chip id mismatch: %#llx\n", id);
3518 + dev_dbg(ov64a40->dev, "OV64A40 chip identified: %#llx\n", id);
3523 +static int ov64a40_parse_dt(struct ov64a40 *ov64a40)
3525 + struct v4l2_fwnode_endpoint v4l2_fwnode = {
3526 + .bus_type = V4L2_MBUS_CSI2_DPHY
3528 + struct fwnode_handle *endpoint;
3529 + int ret = -EINVAL;
3532 + endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(ov64a40->dev),
3535 + dev_err(ov64a40->dev, "Failed to find endpoint\n");
3539 + if (v4l2_fwnode_endpoint_alloc_parse(endpoint, &v4l2_fwnode)) {
3540 + dev_err(ov64a40->dev, "Failed to parse endpoint\n");
3541 + goto error_put_fwnode;
3545 + if (v4l2_fwnode.bus.mipi_csi2.num_data_lanes != 2) {
3546 + dev_err(ov64a40->dev, "Unsupported number of data lanes: %u\n",
3547 + v4l2_fwnode.bus.mipi_csi2.num_data_lanes);
3548 + goto error_free_fwnode;
3551 + if (!v4l2_fwnode.nr_of_link_frequencies) {
3552 + dev_warn(ov64a40->dev, "no link frequencies defined\n");
3553 + goto error_free_fwnode;
3556 + if (v4l2_fwnode.nr_of_link_frequencies > 2) {
3557 + dev_warn(ov64a40->dev,
3558 + "Unsupported number of link frequencies\n");
3559 + goto error_free_fwnode;
3562 + ov64a40->link_frequencies =
3563 + devm_kcalloc(ov64a40->dev, v4l2_fwnode.nr_of_link_frequencies,
3564 + sizeof(v4l2_fwnode.link_frequencies[0]),
3566 + if (!ov64a40->link_frequencies) {
3568 + goto error_free_fwnode;
3570 + ov64a40->num_link_frequencies = v4l2_fwnode.nr_of_link_frequencies;
3572 + for (i = 0; i < v4l2_fwnode.nr_of_link_frequencies; ++i) {
3573 + if (v4l2_fwnode.link_frequencies[i] != OV64A40_LINK_FREQ_360M &&
3574 + v4l2_fwnode.link_frequencies[i] != OV64A40_LINK_FREQ_456M) {
3575 + dev_err(ov64a40->dev,
3576 + "Unsupported link frequency %lld\n",
3577 + v4l2_fwnode.link_frequencies[i]);
3578 + goto error_free_fwnode;
3581 + ov64a40->link_frequencies[i] = v4l2_fwnode.link_frequencies[i];
3584 + v4l2_fwnode_endpoint_free(&v4l2_fwnode);
3586 + /* Register the subdev on the endpoint, so don't put it yet. */
3587 + ov64a40->sd.fwnode = endpoint;
3592 + v4l2_fwnode_endpoint_free(&v4l2_fwnode);
3594 + fwnode_handle_put(endpoint);
3598 +static int ov64a40_get_regulators(struct ov64a40 *ov64a40)
3600 + struct i2c_client *client = v4l2_get_subdevdata(&ov64a40->sd);
3603 + for (i = 0; i < ARRAY_SIZE(ov64a40_supply_names); i++)
3604 + ov64a40->supplies[i].supply = ov64a40_supply_names[i];
3606 + return devm_regulator_bulk_get(&client->dev,
3607 + ARRAY_SIZE(ov64a40_supply_names),
3608 + ov64a40->supplies);
3611 +static int ov64a40_probe(struct i2c_client *client)
3613 + struct ov64a40 *ov64a40;
3617 + ov64a40 = devm_kzalloc(&client->dev, sizeof(*ov64a40), GFP_KERNEL);
3621 + ov64a40->dev = &client->dev;
3622 + v4l2_i2c_subdev_init(&ov64a40->sd, client, &ov64a40_subdev_ops);
3624 + ov64a40->cci = devm_cci_regmap_init_i2c(client, 16);
3625 + if (IS_ERR(ov64a40->cci)) {
3626 + dev_err(&client->dev, "Failed to initialize CCI\n");
3627 + return PTR_ERR(ov64a40->cci);
3630 + ov64a40->xclk = devm_clk_get(&client->dev, NULL);
3631 + if (!ov64a40->xclk)
3632 + return dev_err_probe(&client->dev, PTR_ERR(ov64a40->xclk),
3633 + "Failed to get clock\n");
3635 + xclk_freq = clk_get_rate(ov64a40->xclk);
3636 + if (xclk_freq != OV64A40_XCLK_FREQ) {
3637 + dev_err(&client->dev, "Unsupported xclk frequency %u\n",
3642 + ret = ov64a40_get_regulators(ov64a40);
3646 + ov64a40->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
3648 + if (IS_ERR(ov64a40->reset_gpio))
3649 + return dev_err_probe(&client->dev, PTR_ERR(ov64a40->reset_gpio),
3650 + "Failed to get reset gpio\n");
3652 + ret = ov64a40_parse_dt(ov64a40);
3656 + ret = ov64a40_power_on(&client->dev);
3658 + goto error_put_fwnode;
3660 + ret = ov64a40_identify(ov64a40);
3662 + goto error_poweroff;
3664 + ov64a40->mode = &ov64a40_modes[0];
3666 + pm_runtime_set_active(&client->dev);
3667 + pm_runtime_get_noresume(&client->dev);
3668 + pm_runtime_enable(&client->dev);
3669 + pm_runtime_set_autosuspend_delay(&client->dev, 1000);
3670 + pm_runtime_use_autosuspend(&client->dev);
3672 + ret = ov64a40_init_controls(ov64a40);
3674 + goto error_poweroff;
3676 + /* Initialize subdev */
3677 + ov64a40->sd.flags = V4L2_SUBDEV_FL_HAS_DEVNODE
3678 + | V4L2_SUBDEV_FL_HAS_EVENTS;
3679 + ov64a40->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
3681 + ov64a40->pad.flags = MEDIA_PAD_FL_SOURCE;
3682 + ret = media_entity_pads_init(&ov64a40->sd.entity, 1, &ov64a40->pad);
3684 + dev_err(&client->dev, "failed to init entity pads: %d\n", ret);
3685 + goto error_handler_free;
3688 + ov64a40->sd.state_lock = ov64a40->ctrl_handler.lock;
3689 + ret = v4l2_subdev_init_finalize(&ov64a40->sd);
3691 + dev_err(&client->dev, "subdev init error: %d\n", ret);
3692 + goto error_media_entity;
3695 + ret = v4l2_async_register_subdev_sensor(&ov64a40->sd);
3697 + dev_err(&client->dev,
3698 + "failed to register sensor sub-device: %d\n", ret);
3699 + goto error_subdev_cleanup;
3702 + pm_runtime_mark_last_busy(&client->dev);
3703 + pm_runtime_put_autosuspend(&client->dev);
3707 +error_subdev_cleanup:
3708 + v4l2_subdev_cleanup(&ov64a40->sd);
3709 +error_media_entity:
3710 + media_entity_cleanup(&ov64a40->sd.entity);
3711 +error_handler_free:
3712 + v4l2_ctrl_handler_free(ov64a40->sd.ctrl_handler);
3714 + ov64a40_power_off(&client->dev);
3715 + pm_runtime_set_suspended(&client->dev);
3717 + fwnode_handle_put(ov64a40->sd.fwnode);
3722 +static void ov64a40_remove(struct i2c_client *client)
3724 + struct v4l2_subdev *sd = i2c_get_clientdata(client);
3725 + struct ov64a40 *ov64a40 = sd_to_ov64a40(sd);
3727 + v4l2_async_unregister_subdev(sd);
3728 + fwnode_handle_put(ov64a40->sd.fwnode);
3729 + v4l2_subdev_cleanup(sd);
3730 + media_entity_cleanup(&sd->entity);
3731 + v4l2_ctrl_handler_free(sd->ctrl_handler);
3733 + pm_runtime_disable(&client->dev);
3734 + if (!pm_runtime_status_suspended(&client->dev))
3735 + ov64a40_power_off(&client->dev);
3736 + pm_runtime_set_suspended(&client->dev);
3739 +static const struct of_device_id ov64a40_of_ids[] = {
3740 + { .compatible = "ovti,ov64a40" },
3741 + { /* sentinel */ }
3743 +MODULE_DEVICE_TABLE(of, ov64a40_of_ids);
3745 +static const struct dev_pm_ops ov64a40_pm_ops = {
3746 + SET_RUNTIME_PM_OPS(ov64a40_power_off, ov64a40_power_on, NULL)
3749 +static struct i2c_driver ov64a40_i2c_driver = {
3751 + .name = "ov64a40",
3752 + .of_match_table = ov64a40_of_ids,
3753 + .pm = &ov64a40_pm_ops,
3755 + .probe_new = ov64a40_probe,
3756 + .remove = ov64a40_remove,
3759 +module_i2c_driver(ov64a40_i2c_driver);
3761 +MODULE_AUTHOR("Jacopo Mondi <jacopo.mondi@ideasonboard.com>");
3762 +MODULE_DESCRIPTION("OmniVision OV64A40 sensor driver");
3763 +MODULE_LICENSE("GPL");
projects / openwrt / staging / jow.git / blob