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mediatek: switch to pending XFI 10G Ethernet drivers
[openwrt/staging/jow.git] / target / linux / generic / pending-6.1 / 739-02-phy-add-driver-for-MediaTek-XFI-T-PHY.patch
1 From patchwork Thu Feb 1 21:53:06 2024
2 Content-Type: text/plain; charset="utf-8"
3 MIME-Version: 1.0
4 Content-Transfer-Encoding: 7bit
5 X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
6 X-Patchwork-Id: 13541843
7 Date: Thu, 1 Feb 2024 21:53:06 +0000
8 From: Daniel Golle <daniel@makrotopia.org>
9 To: Bc-bocun Chen <bc-bocun.chen@mediatek.com>,
10 Chunfeng Yun <chunfeng.yun@mediatek.com>,
11 Vinod Koul <vkoul@kernel.org>,
12 Kishon Vijay Abraham I <kishon@kernel.org>,
13 Rob Herring <robh@kernel.org>,
14 Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
15 Conor Dooley <conor+dt@kernel.org>,
16 Daniel Golle <daniel@makrotopia.org>,
17 Qingfang Deng <dqfext@gmail.com>,
18 SkyLake Huang <SkyLake.Huang@mediatek.com>,
19 Matthias Brugger <matthias.bgg@gmail.com>,
20 AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
21 Philipp Zabel <p.zabel@pengutronix.de>,
22 linux-arm-kernel@lists.infradead.org,
23 linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org,
24 devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
25 netdev@vger.kernel.org
26 Subject: [PATCH 2/2] phy: add driver for MediaTek XFI T-PHY
27 Message-ID:
28 <dd6b40ea1f7f8459a9a2cfe7fa60c1108332ade6.1706823233.git.daniel@makrotopia.org>
29 References:
30 <702afb0c1246d95c90b22e57105304028bdd3083.1706823233.git.daniel@makrotopia.org>
31 MIME-Version: 1.0
32 Content-Disposition: inline
33 In-Reply-To:
34 <702afb0c1246d95c90b22e57105304028bdd3083.1706823233.git.daniel@makrotopia.org>
35 List-Id: Linux Phy Mailing list <linux-phy.lists.infradead.org>
36
37 Add driver for MediaTek's XFI T-PHY, 10 Gigabit/s Ethernet SerDes PHY
38 which can be found in the MT7988 SoC.
39
40 The PHY can operates only in PHY_MODE_ETHERNET, the submode is one of
41 PHY_INTERFACE_MODE_* corresponding to the supported modes:
42
43 * USXGMII \
44 * 10GBase-R }- USXGMII PCS - XGDM \
45 * 5GBase-R / \
46 }- Ethernet MAC
47 * 2500Base-X \ /
48 * 1000Base-X }- LynxI PCS - GDM /
49 * Cisco SGMII (MAC side) /
50
51 In order to work-around a performance issue present on the first of
52 two XFI T-PHYs present in MT7988, special tuning is applied which can be
53 selected by adding the 'mediatek,usxgmii-performance-errata' property to
54 the device tree node.
55
56 There is no documentation for most registers used for the
57 analog/tuning part, however, most of the registers have been partially
58 reverse-engineered from MediaTek's SDK implementation (an opaque
59 sequence of 32-bit register writes) and descriptions for all relevant
60 digital registers and bits such as resets and muxes have been supplied
61 by MediaTek.
62
63 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
64 ---
65 MAINTAINERS | 1 +
66 drivers/phy/mediatek/Kconfig | 12 +
67 drivers/phy/mediatek/Makefile | 1 +
68 drivers/phy/mediatek/phy-mtk-xfi-tphy.c | 392 ++++++++++++++++++++++++
69 4 files changed, 406 insertions(+)
70 create mode 100644 drivers/phy/mediatek/phy-mtk-xfi-tphy.c
71
72 --- a/drivers/phy/mediatek/Kconfig
73 +++ b/drivers/phy/mediatek/Kconfig
74 @@ -13,6 +13,18 @@ config PHY_MTK_PCIE
75 callback for PCIe GEN3 port, it supports software efuse
76 initialization.
77
78 +config PHY_MTK_XFI_TPHY
79 + tristate "MediaTek XFI T-PHY Driver"
80 + depends on ARCH_MEDIATEK || COMPILE_TEST
81 + depends on OF && OF_ADDRESS
82 + depends on HAS_IOMEM
83 + select GENERIC_PHY
84 + help
85 + Say 'Y' here to add support for MediaTek XFI T-PHY driver.
86 + The driver provides access to the Ethernet SerDes T-PHY supporting
87 + 1GE and 2.5GE modes via the LynxI PCS, and 5GE and 10GE modes
88 + via the USXGMII PCS found in MediaTek SoCs with 10G Ethernet.
89 +
90 config PHY_MTK_TPHY
91 tristate "MediaTek T-PHY Driver"
92 depends on ARCH_MEDIATEK || COMPILE_TEST
93 --- a/drivers/phy/mediatek/Makefile
94 +++ b/drivers/phy/mediatek/Makefile
95 @@ -8,6 +8,7 @@ obj-$(CONFIG_PHY_MTK_PCIE) += phy-mtk-p
96 obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
97 obj-$(CONFIG_PHY_MTK_UFS) += phy-mtk-ufs.o
98 obj-$(CONFIG_PHY_MTK_XSPHY) += phy-mtk-xsphy.o
99 +obj-$(CONFIG_PHY_MTK_XFI_TPHY) += phy-mtk-xfi-tphy.o
100
101 phy-mtk-hdmi-drv-y := phy-mtk-hdmi.o
102 phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt2701.o
103 --- /dev/null
104 +++ b/drivers/phy/mediatek/phy-mtk-xfi-tphy.c
105 @@ -0,0 +1,392 @@
106 +// SPDX-License-Identifier: GPL-2.0-or-later
107 +/* MediaTek 10GE SerDes PHY driver
108 + *
109 + * Copyright (c) 2024 Daniel Golle <daniel@makrotopia.org>
110 + * Bc-bocun Chen <bc-bocun.chen@mediatek.com>
111 + * based on mtk_usxgmii.c found in MediaTek's SDK released under GPL-2.0
112 + * Copyright (c) 2022 MediaTek Inc.
113 + * Author: Henry Yen <henry.yen@mediatek.com>
114 + */
115 +
116 +#include <linux/module.h>
117 +#include <linux/device.h>
118 +#include <linux/platform_device.h>
119 +#include <linux/of.h>
120 +#include <linux/io.h>
121 +#include <linux/clk.h>
122 +#include <linux/reset.h>
123 +#include <linux/phy.h>
124 +#include <linux/phy/phy.h>
125 +
126 +#define MTK_XFI_TPHY_NUM_CLOCKS 2
127 +
128 +#define REG_DIG_GLB_70 0x0070
129 +#define XTP_PCS_RX_EQ_IN_PROGRESS(x) FIELD_PREP(GENMASK(25, 24), (x))
130 +#define XTP_PCS_MODE_MASK GENMASK(17, 16)
131 +#define XTP_PCS_MODE(x) FIELD_PREP(GENMASK(17, 16), (x))
132 +#define XTP_PCS_RST_B BIT(15)
133 +#define XTP_FRC_PCS_RST_B BIT(14)
134 +#define XTP_PCS_PWD_SYNC_MASK GENMASK(13, 12)
135 +#define XTP_PCS_PWD_SYNC(x) FIELD_PREP(XTP_PCS_PWD_SYNC_MASK, (x))
136 +#define XTP_PCS_PWD_ASYNC_MASK GENMASK(11, 10)
137 +#define XTP_PCS_PWD_ASYNC(x) FIELD_PREP(XTP_PCS_PWD_ASYNC_MASK, (x))
138 +#define XTP_FRC_PCS_PWD_ASYNC BIT(8)
139 +#define XTP_PCS_UPDT BIT(4)
140 +#define XTP_PCS_IN_FR_RG BIT(0)
141 +
142 +#define REG_DIG_GLB_F4 0x00f4
143 +#define XFI_DPHY_PCS_SEL BIT(0)
144 +#define XFI_DPHY_PCS_SEL_SGMII FIELD_PREP(XFI_DPHY_PCS_SEL, 1)
145 +#define XFI_DPHY_PCS_SEL_USXGMII FIELD_PREP(XFI_DPHY_PCS_SEL, 0)
146 +#define XFI_DPHY_AD_SGDT_FRC_EN BIT(5)
147 +
148 +#define REG_DIG_LN_TRX_40 0x3040
149 +#define XTP_LN_FRC_TX_DATA_EN BIT(29)
150 +#define XTP_LN_TX_DATA_EN BIT(28)
151 +
152 +#define REG_DIG_LN_TRX_B0 0x30b0
153 +#define XTP_LN_FRC_TX_MACCK_EN BIT(5)
154 +#define XTP_LN_TX_MACCK_EN BIT(4)
155 +
156 +#define REG_ANA_GLB_D0 0x90d0
157 +#define XTP_GLB_USXGMII_SEL_MASK GENMASK(3, 1)
158 +#define XTP_GLB_USXGMII_SEL(x) FIELD_PREP(GENMASK(3, 1), (x))
159 +#define XTP_GLB_USXGMII_EN BIT(0)
160 +
161 +struct mtk_xfi_tphy {
162 + void __iomem *base;
163 + struct device *dev;
164 + struct reset_control *reset;
165 + struct clk_bulk_data clocks[MTK_XFI_TPHY_NUM_CLOCKS];
166 + bool da_war;
167 +};
168 +
169 +static void mtk_xfi_tphy_write(struct mtk_xfi_tphy *xfi_tphy, u16 reg,
170 + u32 value)
171 +{
172 + iowrite32(value, xfi_tphy->base + reg);
173 +}
174 +
175 +static void mtk_xfi_tphy_rmw(struct mtk_xfi_tphy *xfi_tphy, u16 reg,
176 + u32 clr, u32 set)
177 +{
178 + u32 val;
179 +
180 + val = ioread32(xfi_tphy->base + reg);
181 + val &= ~clr;
182 + val |= set;
183 + iowrite32(val, xfi_tphy->base + reg);
184 +}
185 +
186 +static void mtk_xfi_tphy_set(struct mtk_xfi_tphy *xfi_tphy, u16 reg,
187 + u32 set)
188 +{
189 + mtk_xfi_tphy_rmw(xfi_tphy, reg, 0, set);
190 +}
191 +
192 +static void mtk_xfi_tphy_clear(struct mtk_xfi_tphy *xfi_tphy, u16 reg,
193 + u32 clr)
194 +{
195 + mtk_xfi_tphy_rmw(xfi_tphy, reg, clr, 0);
196 +}
197 +
198 +static void mtk_xfi_tphy_setup(struct mtk_xfi_tphy *xfi_tphy,
199 + phy_interface_t interface)
200 +{
201 + bool is_2p5g = (interface == PHY_INTERFACE_MODE_2500BASEX);
202 + bool is_1g = (interface == PHY_INTERFACE_MODE_1000BASEX ||
203 + interface == PHY_INTERFACE_MODE_SGMII);
204 + bool is_10g = (interface == PHY_INTERFACE_MODE_10GBASER ||
205 + interface == PHY_INTERFACE_MODE_USXGMII);
206 + bool is_5g = (interface == PHY_INTERFACE_MODE_5GBASER);
207 + bool is_xgmii = (is_10g || is_5g);
208 +
209 + dev_dbg(xfi_tphy->dev, "setting up for mode %s\n", phy_modes(interface));
210 +
211 + /* Setup PLL setting */
212 + mtk_xfi_tphy_rmw(xfi_tphy, 0x9024, 0x100000, is_10g ? 0x0 : 0x100000);
213 + mtk_xfi_tphy_rmw(xfi_tphy, 0x2020, 0x202000, is_5g ? 0x202000 : 0x0);
214 + mtk_xfi_tphy_rmw(xfi_tphy, 0x2030, 0x500, is_1g ? 0x0 : 0x500);
215 + mtk_xfi_tphy_rmw(xfi_tphy, 0x2034, 0xa00, is_1g ? 0x0 : 0xa00);
216 + mtk_xfi_tphy_rmw(xfi_tphy, 0x2040, 0x340000, is_1g ? 0x200000 :
217 + 0x140000);
218 +
219 + /* Setup RXFE BW setting */
220 + mtk_xfi_tphy_rmw(xfi_tphy, 0x50f0, 0xc10, is_1g ? 0x410 :
221 + is_5g ? 0x800 : 0x400);
222 + mtk_xfi_tphy_rmw(xfi_tphy, 0x50e0, 0x4000, is_5g ? 0x0 : 0x4000);
223 +
224 + /* Setup RX CDR setting */
225 + mtk_xfi_tphy_rmw(xfi_tphy, 0x506c, 0x30000, is_5g ? 0x0 : 0x30000);
226 + mtk_xfi_tphy_rmw(xfi_tphy, 0x5070, 0x670000, is_5g ? 0x620000 : 0x50000);
227 + mtk_xfi_tphy_rmw(xfi_tphy, 0x5074, 0x180000, is_5g ? 0x180000 : 0x0);
228 + mtk_xfi_tphy_rmw(xfi_tphy, 0x5078, 0xf000400, is_5g ? 0x8000000 :
229 + 0x7000400);
230 + mtk_xfi_tphy_rmw(xfi_tphy, 0x507c, 0x5000500, is_5g ? 0x4000400 :
231 + 0x1000100);
232 + mtk_xfi_tphy_rmw(xfi_tphy, 0x5080, 0x1410, is_1g ? 0x400 :
233 + is_5g ? 0x1010 : 0x0);
234 + mtk_xfi_tphy_rmw(xfi_tphy, 0x5084, 0x30300, is_1g ? 0x30300 :
235 + is_5g ? 0x30100 :
236 + 0x100);
237 + mtk_xfi_tphy_rmw(xfi_tphy, 0x5088, 0x60200, is_1g ? 0x20200 :
238 + is_5g ? 0x40000 :
239 + 0x20000);
240 +
241 + /* Setting RXFE adaptation range setting */
242 + mtk_xfi_tphy_rmw(xfi_tphy, 0x50e4, 0xc0000, is_5g ? 0x0 : 0xc0000);
243 + mtk_xfi_tphy_rmw(xfi_tphy, 0x50e8, 0x40000, is_5g ? 0x0 : 0x40000);
244 + mtk_xfi_tphy_rmw(xfi_tphy, 0x50ec, 0xa00, is_1g ? 0x200 : 0x800);
245 + mtk_xfi_tphy_rmw(xfi_tphy, 0x50a8, 0xee0000, is_5g ? 0x800000 :
246 + 0x6e0000);
247 + mtk_xfi_tphy_rmw(xfi_tphy, 0x6004, 0x190000, is_5g ? 0x0 : 0x190000);
248 + if (is_10g)
249 + mtk_xfi_tphy_write(xfi_tphy, 0x00f8, 0x01423342);
250 + else if (is_5g)
251 + mtk_xfi_tphy_write(xfi_tphy, 0x00f8, 0x00a132a1);
252 + else if (is_2p5g)
253 + mtk_xfi_tphy_write(xfi_tphy, 0x00f8, 0x009c329c);
254 + else
255 + mtk_xfi_tphy_write(xfi_tphy, 0x00f8, 0x00fa32fa);
256 +
257 + /* Force SGDT_OUT off and select PCS */
258 + mtk_xfi_tphy_rmw(xfi_tphy, REG_DIG_GLB_F4,
259 + XFI_DPHY_AD_SGDT_FRC_EN | XFI_DPHY_PCS_SEL,
260 + XFI_DPHY_AD_SGDT_FRC_EN |
261 + (is_xgmii ? XFI_DPHY_PCS_SEL_USXGMII :
262 + XFI_DPHY_PCS_SEL_SGMII));
263 +
264 +
265 + /* Force GLB_CKDET_OUT */
266 + mtk_xfi_tphy_set(xfi_tphy, 0x0030, 0xc00);
267 +
268 + /* Force AEQ on */
269 + mtk_xfi_tphy_write(xfi_tphy, REG_DIG_GLB_70,
270 + XTP_PCS_RX_EQ_IN_PROGRESS(2) |
271 + XTP_PCS_PWD_SYNC(2) |
272 + XTP_PCS_PWD_ASYNC(2));
273 +
274 + usleep_range(1, 5);
275 +
276 + /* Setup TX DA default value */
277 + mtk_xfi_tphy_rmw(xfi_tphy, 0x30b0, 0x30, 0x20);
278 + mtk_xfi_tphy_write(xfi_tphy, 0x3028, 0x00008a01);
279 + mtk_xfi_tphy_write(xfi_tphy, 0x302c, 0x0000a884);
280 + mtk_xfi_tphy_write(xfi_tphy, 0x3024, 0x00083002);
281 +
282 + /* Setup RG default value */
283 + if (is_xgmii) {
284 + mtk_xfi_tphy_write(xfi_tphy, 0x3010, 0x00022220);
285 + mtk_xfi_tphy_write(xfi_tphy, 0x5064, 0x0f020a01);
286 + mtk_xfi_tphy_write(xfi_tphy, 0x50b4, 0x06100600);
287 + if (interface == PHY_INTERFACE_MODE_USXGMII)
288 + mtk_xfi_tphy_write(xfi_tphy, 0x3048, 0x40704000);
289 + else
290 + mtk_xfi_tphy_write(xfi_tphy, 0x3048, 0x47684100);
291 + } else {
292 + mtk_xfi_tphy_write(xfi_tphy, 0x3010, 0x00011110);
293 + mtk_xfi_tphy_write(xfi_tphy, 0x3048, 0x40704000);
294 + }
295 +
296 + if (is_1g)
297 + mtk_xfi_tphy_write(xfi_tphy, 0x3064, 0x0000c000);
298 +
299 + /* Setup RX EQ initial value */
300 + mtk_xfi_tphy_rmw(xfi_tphy, 0x3050, 0xa8000000,
301 + (interface != PHY_INTERFACE_MODE_10GBASER) ?
302 + 0xa8000000 : 0x0);
303 + mtk_xfi_tphy_rmw(xfi_tphy, 0x3054, 0xaa,
304 + (interface != PHY_INTERFACE_MODE_10GBASER) ?
305 + 0xaa : 0x0);
306 +
307 + if (is_xgmii)
308 + mtk_xfi_tphy_write(xfi_tphy, 0x306c, 0x00000f00);
309 + else if (is_2p5g)
310 + mtk_xfi_tphy_write(xfi_tphy, 0x306c, 0x22000f00);
311 + else
312 + mtk_xfi_tphy_write(xfi_tphy, 0x306c, 0x20200f00);
313 +
314 + if (interface == PHY_INTERFACE_MODE_10GBASER && xfi_tphy->da_war)
315 + mtk_xfi_tphy_rmw(xfi_tphy, 0xa008, 0x10000, 0x10000);
316 +
317 + mtk_xfi_tphy_rmw(xfi_tphy, 0xa060, 0x50000, is_xgmii ? 0x40000 :
318 + 0x50000);
319 +
320 + /* Setup PHYA speed */
321 + mtk_xfi_tphy_rmw(xfi_tphy, REG_ANA_GLB_D0,
322 + XTP_GLB_USXGMII_SEL_MASK | XTP_GLB_USXGMII_EN,
323 + is_10g ? XTP_GLB_USXGMII_SEL(0) :
324 + is_5g ? XTP_GLB_USXGMII_SEL(1) :
325 + is_2p5g ? XTP_GLB_USXGMII_SEL(2) :
326 + XTP_GLB_USXGMII_SEL(3));
327 + mtk_xfi_tphy_set(xfi_tphy, REG_ANA_GLB_D0, XTP_GLB_USXGMII_EN);
328 +
329 + /* Release reset */
330 + mtk_xfi_tphy_set(xfi_tphy, REG_DIG_GLB_70,
331 + XTP_PCS_RST_B | XTP_FRC_PCS_RST_B);
332 + usleep_range(150, 500);
333 +
334 + /* Switch to P0 */
335 + mtk_xfi_tphy_rmw(xfi_tphy, REG_DIG_GLB_70,
336 + XTP_PCS_PWD_SYNC_MASK |
337 + XTP_PCS_PWD_ASYNC_MASK,
338 + XTP_FRC_PCS_PWD_ASYNC |
339 + XTP_PCS_UPDT | XTP_PCS_IN_FR_RG);
340 + usleep_range(1, 5);
341 +
342 + mtk_xfi_tphy_clear(xfi_tphy, REG_DIG_GLB_70, XTP_PCS_UPDT);
343 + usleep_range(15, 50);
344 +
345 + if (is_xgmii) {
346 + /* Switch to Gen3 */
347 + mtk_xfi_tphy_rmw(xfi_tphy, REG_DIG_GLB_70,
348 + XTP_PCS_MODE_MASK | XTP_PCS_UPDT,
349 + XTP_PCS_MODE(2) | XTP_PCS_UPDT);
350 + } else {
351 + /* Switch to Gen2 */
352 + mtk_xfi_tphy_rmw(xfi_tphy, REG_DIG_GLB_70,
353 + XTP_PCS_MODE_MASK | XTP_PCS_UPDT,
354 + XTP_PCS_MODE(1) | XTP_PCS_UPDT);
355 + }
356 + usleep_range(1, 5);
357 +
358 + mtk_xfi_tphy_clear(xfi_tphy, REG_DIG_GLB_70, XTP_PCS_UPDT);
359 +
360 + usleep_range(100, 500);
361 +
362 + /* Enable MAC CK */
363 + mtk_xfi_tphy_set(xfi_tphy, REG_DIG_LN_TRX_B0, XTP_LN_TX_MACCK_EN);
364 + mtk_xfi_tphy_clear(xfi_tphy, REG_DIG_GLB_F4, XFI_DPHY_AD_SGDT_FRC_EN);
365 +
366 + /* Enable TX data */
367 + mtk_xfi_tphy_set(xfi_tphy, REG_DIG_LN_TRX_40,
368 + XTP_LN_FRC_TX_DATA_EN | XTP_LN_TX_DATA_EN);
369 + usleep_range(400, 1000);
370 +}
371 +
372 +static int mtk_xfi_tphy_set_mode(struct phy *phy, enum phy_mode mode, int
373 + submode)
374 +{
375 + struct mtk_xfi_tphy *xfi_tphy = phy_get_drvdata(phy);
376 +
377 + if (mode != PHY_MODE_ETHERNET)
378 + return -EINVAL;
379 +
380 + switch (submode) {
381 + case PHY_INTERFACE_MODE_1000BASEX:
382 + case PHY_INTERFACE_MODE_2500BASEX:
383 + case PHY_INTERFACE_MODE_SGMII:
384 + case PHY_INTERFACE_MODE_5GBASER:
385 + case PHY_INTERFACE_MODE_10GBASER:
386 + case PHY_INTERFACE_MODE_USXGMII:
387 + mtk_xfi_tphy_setup(xfi_tphy, submode);
388 + return 0;
389 + default:
390 + return -EINVAL;
391 + }
392 +}
393 +
394 +static int mtk_xfi_tphy_reset(struct phy *phy)
395 +{
396 + struct mtk_xfi_tphy *xfi_tphy = phy_get_drvdata(phy);
397 +
398 + reset_control_assert(xfi_tphy->reset);
399 + usleep_range(100, 500);
400 + reset_control_deassert(xfi_tphy->reset);
401 + usleep_range(1, 10);
402 +
403 + return 0;
404 +}
405 +
406 +static int mtk_xfi_tphy_power_on(struct phy *phy)
407 +{
408 + struct mtk_xfi_tphy *xfi_tphy = phy_get_drvdata(phy);
409 +
410 + return clk_bulk_prepare_enable(MTK_XFI_TPHY_NUM_CLOCKS, xfi_tphy->clocks);
411 +}
412 +
413 +static int mtk_xfi_tphy_power_off(struct phy *phy)
414 +{
415 + struct mtk_xfi_tphy *xfi_tphy = phy_get_drvdata(phy);
416 +
417 + clk_bulk_disable_unprepare(MTK_XFI_TPHY_NUM_CLOCKS, xfi_tphy->clocks);
418 +
419 + return 0;
420 +}
421 +
422 +static const struct phy_ops mtk_xfi_tphy_ops = {
423 + .power_on = mtk_xfi_tphy_power_on,
424 + .power_off = mtk_xfi_tphy_power_off,
425 + .set_mode = mtk_xfi_tphy_set_mode,
426 + .reset = mtk_xfi_tphy_reset,
427 + .owner = THIS_MODULE,
428 +};
429 +
430 +static int mtk_xfi_tphy_probe(struct platform_device *pdev)
431 +{
432 + struct device_node *np = pdev->dev.of_node;
433 + struct phy_provider *phy_provider;
434 + struct mtk_xfi_tphy *xfi_tphy;
435 + struct phy *phy;
436 +
437 + if (!np)
438 + return -ENODEV;
439 +
440 + xfi_tphy = devm_kzalloc(&pdev->dev, sizeof(*xfi_tphy), GFP_KERNEL);
441 + if (!xfi_tphy)
442 + return -ENOMEM;
443 +
444 + xfi_tphy->base = devm_of_iomap(&pdev->dev, np, 0, NULL);
445 + if (!xfi_tphy->base)
446 + return -EIO;
447 +
448 + xfi_tphy->dev = &pdev->dev;
449 +
450 + xfi_tphy->clocks[0].id = "topxtal";
451 + xfi_tphy->clocks[0].clk = devm_clk_get(&pdev->dev, xfi_tphy->clocks[0].id);
452 + if (IS_ERR(xfi_tphy->clocks[0].clk))
453 + return PTR_ERR(xfi_tphy->clocks[0].clk);
454 +
455 + xfi_tphy->clocks[1].id = "xfipll";
456 + xfi_tphy->clocks[1].clk = devm_clk_get(&pdev->dev, xfi_tphy->clocks[1].id);
457 + if (IS_ERR(xfi_tphy->clocks[1].clk))
458 + return PTR_ERR(xfi_tphy->clocks[1].clk);
459 +
460 + xfi_tphy->reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);
461 + if (IS_ERR(xfi_tphy->reset))
462 + return PTR_ERR(xfi_tphy->reset);
463 +
464 + xfi_tphy->da_war = of_property_read_bool(np,
465 + "mediatek,usxgmii-performance-errata");
466 +
467 + phy = devm_phy_create(&pdev->dev, NULL, &mtk_xfi_tphy_ops);
468 + if (IS_ERR(phy))
469 + return PTR_ERR(phy);
470 +
471 + phy_set_drvdata(phy, xfi_tphy);
472 +
473 + phy_provider = devm_of_phy_provider_register(&pdev->dev,
474 + of_phy_simple_xlate);
475 +
476 + return PTR_ERR_OR_ZERO(phy_provider);
477 +}
478 +
479 +static const struct of_device_id mtk_xfi_tphy_match[] = {
480 + { .compatible = "mediatek,mt7988-xfi-tphy", },
481 + { }
482 +};
483 +MODULE_DEVICE_TABLE(of, mtk_xfi_tphy_match);
484 +
485 +static struct platform_driver mtk_xfi_tphy_driver = {
486 + .probe = mtk_xfi_tphy_probe,
487 + .driver = {
488 + .name = "mtk-xfi-tphy",
489 + .of_match_table = mtk_xfi_tphy_match,
490 + },
491 +};
492 +module_platform_driver(mtk_xfi_tphy_driver);
493 +
494 +MODULE_DESCRIPTION("MediaTek XFI T-PHY driver");
495 +MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
496 +MODULE_AUTHOR("Bc-bocun Chen <bc-bocun.chen@mediatek.com>");
497 +MODULE_LICENSE("GPL");
Staging tree of Jo-Philipp Wich