FEATURES:=squashfs ramdisk fpu nand rtc emmc
KERNELNAME:=Image dtbs
CPU_TYPE:=cortex-a53
-SUBTARGETS:=ipq807x
+SUBTARGETS:=ipq807x ipq60xx
KERNEL_PATCHVER:=6.1
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include "ipq6018-cpr-regulator.dtsi"
+
+&CPU0 {
+ cpu-supply = <&apc_vreg>;
+};
+
+&CPU1 {
+ cpu-supply = <&apc_vreg>;
+};
+
+&CPU2 {
+ cpu-supply = <&apc_vreg>;
+};
+
+&CPU3 {
+ cpu-supply = <&apc_vreg>;
+};
--- /dev/null
+/*
+ * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+&soc {
+ apc_apm: apm@b111000 {
+ compatible = "qcom,ipq807x-apm";
+ reg = <0x0 0xb111000 0x0 0x1000>;
+ reg-names = "pm-apcc-glb";
+ qcom,apm-post-halt-delay = <0x2>;
+ qcom,apm-halt-clk-delay = <0x11>;
+ qcom,apm-resume-clk-delay = <0x10>;
+ qcom,apm-sel-switch-delay = <0x01>;
+ };
+
+ apc_cpr: cpr4-ctrl@b018000 {
+ compatible = "qcom,cpr4-ipq6018-apss-regulator";
+ reg = <0x0 0xb018000 0x0 0x4000>, <0x0 0xa4000 0x0 0x1000>, <0x0 0x0193d008 0x0 0x4>;
+ reg-names = "cpr_ctrl", "fuse_base", "cpr_tcsr_reg";
+ interrupts = <GIC_SPI 15 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "cpr";
+ qcom,cpr-ctrl-name = "apc";
+ qcom,cpr-sensor-time = <1000>;
+ qcom,cpr-loop-time = <5000000>;
+ qcom,cpr-idle-cycles = <15>;
+ qcom,cpr-step-quot-init-min = <0>;
+ qcom,cpr-step-quot-init-max = <15>;
+ qcom,cpr-count-mode = <0>; /* All-at-once */
+ qcom,cpr-count-repeat = <1>;
+ qcom,cpr-down-error-step-limit = <1>;
+ qcom,cpr-up-error-step-limit = <1>;
+ qcom,apm-ctrl = <&apc_apm>;
+ qcom,apm-threshold-voltage = <850000>;
+ vdd-supply = <&ipq6018_s2>;
+ qcom,voltage-step = <12500>;
+
+ thread@0 {
+ qcom,cpr-thread-id = <0>;
+ qcom,cpr-consecutive-up = <2>;
+ qcom,cpr-consecutive-down = <2>;
+ qcom,cpr-up-threshold = <2>;
+ qcom,cpr-down-threshold = <2>;
+
+ apc_vreg: regulator {
+ regulator-name = "apc_corner";
+ regulator-min-microvolt = <1>;
+ regulator-max-microvolt = <6>;
+ qcom,cpr-fuse-corners = <4>;
+ qcom,cpr-fuse-combos = <8>;
+ qcom,cpr-corners = <6>;
+ qcom,cpr-speed-bins = <1>;
+ qcom,cpr-speed-bin-corners = <6>;
+ qcom,cpr-corner-fmax-map = <1 3 5 6>;
+ qcom,allow-voltage-interpolation;
+ qcom,allow-quotient-interpolation;
+ qcom,cpr-voltage-ceiling =
+ <725000 787500 862500
+ 925000 987500 1062500>;
+ qcom,cpr-voltage-floor =
+ <587500 650000 712500
+ 750000 787500 850000>;
+ qcom,corner-frequencies =
+ <864000000 1056000000 1320000000
+ 1440000000 1608000000 1800000000>;
+ qcom,cpr-ro-sel =
+ /* Speed bin 0; CPR rev 0..7 */
+ < 0 0 0 0>,
+ < 7 7 7 7>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>;
+
+ qcom,cpr-open-loop-voltage-fuse-adjustment =
+ /* Speed bin 0; CPR rev 0..7 */
+ /* SVS Nominal Turbo Turbo_L1 */
+ < 0 0 0 0>,
+ < 0 0 15000 0>,
+ < 0 0 15000 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>;
+
+ qcom,cpr-closed-loop-voltage-fuse-adjustment =
+ /* Speed bin 0; CPR rev 0..7 */
+ < 0 0 0 0>,
+ < 13000 0 13000 13000>,
+ < 13000 0 13000 13000>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>,
+ < 0 0 0 0>;
+
+ qcom,cpr-ro-scaling-factor =
+ < 2000 1770 1900 1670 1930 1770 1910 1800
+ 1870 1730 2000 1840 1800 2030 1700 1890 >,
+ < 2000 1770 1900 1670 1930 1770 1910 1800
+ 1870 1730 2000 1840 1800 2030 1700 1890 >,
+ < 2000 1770 1900 1670 1930 1770 1910 1800
+ 1870 1730 2000 1840 1800 2030 1700 1890 >,
+ < 2000 1770 1900 1670 1930 1770 1910 1800
+ 1870 1730 2000 1840 1800 2030 1700 1890 >;
+ regulator-always-on;
+ };
+ };
+ };
+};
--- /dev/null
+#include <dt-bindings/net/qcom-ipq-ess.h>
+
+&soc {
+ bias_pll_cc_clk: bias-pll-cc-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <300000000>;
+ clock-output-names = "bias_pll_cc_clk";
+ #clock-cells = <0>;
+ };
+
+ bias_pll_nss_noc_clk: bias-pll-nss-noc-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <416500000>;
+ clock-output-names = "bias_pll_nss_noc_clk";
+ #clock-cells = <0>;
+ };
+
+ edma: edma@3ab00000 {
+ compatible = "qcom,edma";
+ reg = <0x0 0x3ab00000 0x0 0xabe00>;
+ reg-names = "edma-reg-base";
+ qcom,txdesc-ring-start = <23>;
+ qcom,txdesc-rings = <1>;
+ qcom,txcmpl-ring-start = <23>;
+ qcom,txcmpl-rings = <1>;
+ qcom,rxfill-ring-start = <7>;
+ qcom,rxfill-rings = <1>;
+ qcom,rxdesc-ring-start = <15>;
+ qcom,rxdesc-rings = <1>;
+ interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&gcc GCC_EDMA_HW_RESET>;
+ reset-names = "edma_rst";
+ status = "disabled";
+ };
+
+ ess_instance: ess-instance {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ num_devices = <1>;
+
+ switch: ess-switch@3a000000 {
+ compatible = "qcom,ess-switch-ipq60xx";
+ reg = <0x3a000000 0x1000000>;
+ switch_access_mode = "local bus";
+ clocks = <&gcc GCC_CMN_12GPLL_AHB_CLK>,
+ <&gcc GCC_CMN_12GPLL_SYS_CLK>,
+ <&gcc GCC_UNIPHY0_AHB_CLK>,
+ <&gcc GCC_UNIPHY0_SYS_CLK>,
+ <&gcc GCC_UNIPHY1_AHB_CLK>,
+ <&gcc GCC_UNIPHY1_SYS_CLK>,
+ <&gcc GCC_PORT1_MAC_CLK>,
+ <&gcc GCC_PORT2_MAC_CLK>,
+ <&gcc GCC_PORT3_MAC_CLK>,
+ <&gcc GCC_PORT4_MAC_CLK>,
+ <&gcc GCC_PORT5_MAC_CLK>,
+ <&gcc GCC_NSS_PPE_CLK>,
+ <&gcc GCC_NSS_PPE_CFG_CLK>,
+ <&gcc GCC_NSSNOC_PPE_CLK>,
+ <&gcc GCC_NSSNOC_PPE_CFG_CLK>,
+ <&gcc GCC_NSS_EDMA_CLK>,
+ <&gcc GCC_NSS_EDMA_CFG_CLK>,
+ <&gcc GCC_NSS_PPE_IPE_CLK>,
+ <&gcc GCC_MDIO_AHB_CLK>,
+ <&gcc GCC_NSS_NOC_CLK>,
+ <&gcc GCC_NSSNOC_SNOC_CLK>,
+ <&gcc GCC_NSS_CRYPTO_CLK>,
+ <&gcc GCC_NSS_PTP_REF_CLK>,
+ <&gcc GCC_NSS_PORT1_RX_CLK>,
+ <&gcc GCC_NSS_PORT1_TX_CLK>,
+ <&gcc GCC_NSS_PORT2_RX_CLK>,
+ <&gcc GCC_NSS_PORT2_TX_CLK>,
+ <&gcc GCC_NSS_PORT3_RX_CLK>,
+ <&gcc GCC_NSS_PORT3_TX_CLK>,
+ <&gcc GCC_NSS_PORT4_RX_CLK>,
+ <&gcc GCC_NSS_PORT4_TX_CLK>,
+ <&gcc GCC_NSS_PORT5_RX_CLK>,
+ <&gcc GCC_NSS_PORT5_TX_CLK>,
+ <&gcc GCC_UNIPHY0_PORT1_RX_CLK>,
+ <&gcc GCC_UNIPHY0_PORT1_TX_CLK>,
+ <&gcc GCC_UNIPHY0_PORT2_RX_CLK>,
+ <&gcc GCC_UNIPHY0_PORT2_TX_CLK>,
+ <&gcc GCC_UNIPHY0_PORT3_RX_CLK>,
+ <&gcc GCC_UNIPHY0_PORT3_TX_CLK>,
+ <&gcc GCC_UNIPHY0_PORT4_RX_CLK>,
+ <&gcc GCC_UNIPHY0_PORT4_TX_CLK>,
+ <&gcc GCC_UNIPHY0_PORT5_RX_CLK>,
+ <&gcc GCC_UNIPHY0_PORT5_TX_CLK>,
+ <&gcc GCC_UNIPHY1_PORT5_RX_CLK>,
+ <&gcc GCC_UNIPHY1_PORT5_TX_CLK>,
+ <&gcc NSS_PORT5_RX_CLK_SRC>,
+ <&gcc NSS_PORT5_TX_CLK_SRC>,
+ <&gcc GCC_SNOC_NSSNOC_CLK>;
+ clock-names = "cmn_ahb_clk", "cmn_sys_clk",
+ "uniphy0_ahb_clk", "uniphy0_sys_clk",
+ "uniphy1_ahb_clk", "uniphy1_sys_clk",
+ "port1_mac_clk", "port2_mac_clk",
+ "port3_mac_clk", "port4_mac_clk",
+ "port5_mac_clk",
+ "nss_ppe_clk", "nss_ppe_cfg_clk",
+ "nssnoc_ppe_clk", "nssnoc_ppe_cfg_clk",
+ "nss_edma_clk", "nss_edma_cfg_clk",
+ "nss_ppe_ipe_clk",
+ "gcc_mdio_ahb_clk", "gcc_nss_noc_clk",
+ "gcc_nssnoc_snoc_clk",
+ "gcc_nss_crypto_clk",
+ "gcc_nss_ptp_ref_clk",
+ "nss_port1_rx_clk", "nss_port1_tx_clk",
+ "nss_port2_rx_clk", "nss_port2_tx_clk",
+ "nss_port3_rx_clk", "nss_port3_tx_clk",
+ "nss_port4_rx_clk", "nss_port4_tx_clk",
+ "nss_port5_rx_clk", "nss_port5_tx_clk",
+ "uniphy0_port1_rx_clk",
+ "uniphy0_port1_tx_clk",
+ "uniphy0_port2_rx_clk",
+ "uniphy0_port2_tx_clk",
+ "uniphy0_port3_rx_clk",
+ "uniphy0_port3_tx_clk",
+ "uniphy0_port4_rx_clk",
+ "uniphy0_port4_tx_clk",
+ "uniphy0_port5_rx_clk",
+ "uniphy0_port5_tx_clk",
+ "uniphy1_port5_rx_clk",
+ "uniphy1_port5_tx_clk",
+ "nss_port5_rx_clk_src",
+ "nss_port5_tx_clk_src",
+ "gcc_snoc_nssnoc_clk";
+ resets = <&gcc GCC_PPE_FULL_RESET>,
+ <&gcc GCC_UNIPHY0_SOFT_RESET>,
+ <&gcc GCC_UNIPHY0_XPCS_RESET>,
+ <&gcc GCC_UNIPHY1_SOFT_RESET>,
+ <&gcc GCC_UNIPHY1_XPCS_RESET>,
+ <&gcc GCC_NSSPORT1_RESET>,
+ <&gcc GCC_NSSPORT2_RESET>,
+ <&gcc GCC_NSSPORT3_RESET>,
+ <&gcc GCC_NSSPORT4_RESET>,
+ <&gcc GCC_NSSPORT5_RESET>,
+ <&gcc GCC_UNIPHY0_PORT1_ARES>,
+ <&gcc GCC_UNIPHY0_PORT2_ARES>,
+ <&gcc GCC_UNIPHY0_PORT3_ARES>,
+ <&gcc GCC_UNIPHY0_PORT4_ARES>,
+ <&gcc GCC_UNIPHY0_PORT5_ARES>,
+ <&gcc GCC_UNIPHY0_PORT_4_5_RESET>,
+ <&gcc GCC_UNIPHY0_PORT_4_RESET>;
+ reset-names = "ppe_rst", "uniphy0_soft_rst",
+ "uniphy0_xpcs_rst", "uniphy1_soft_rst",
+ "uniphy1_xpcs_rst", "nss_port1_rst",
+ "nss_port2_rst", "nss_port3_rst",
+ "nss_port4_rst", "nss_port5_rst",
+ "uniphy0_port1_dis",
+ "uniphy0_port2_dis",
+ "uniphy0_port3_dis",
+ "uniphy0_port4_dis",
+ "uniphy0_port5_dis",
+ "uniphy0_port_4_5_rst",
+ "uniphy0_port_4_rst";
+ mdio-bus = <&mdio>;
+
+ switch_cpu_bmp = <ESS_PORT0>; /* cpu port bitmap */
+ switch_inner_bmp = <(ESS_PORT6 | ESS_PORT7)>; /*inner port bitmap*/
+ switch_mac_mode = <MAC_MODE_DISABLED>; /* MAC mode for UNIPHY instance 0 */
+ switch_mac_mode1 = <MAC_MODE_DISABLED>; /* MAC mode for UNIPHY instance 1 */
+ switch_mac_mode2 = <MAC_MODE_DISABLED>; /* MAC mode for UNIPHY instance 2 */
+
+ status = "disabled";
+
+ bm_tick_mode = <0>; /* bm tick mode */
+ tm_tick_mode = <0>; /* tm tick mode */
+
+ port_scheduler_resource {
+ port@0 {
+ port_id = <0>;
+ ucast_queue = <0 143>;
+ mcast_queue = <256 271>;
+ l0sp = <0 35>;
+ l0cdrr = <0 47>;
+ l0edrr = <0 47>;
+ l1cdrr = <0 7>;
+ l1edrr = <0 7>;
+ };
+ port@1 {
+ port_id = <1>;
+ ucast_queue = <144 159>;
+ mcast_queue = <272 275>;
+ l0sp = <36 39>;
+ l0cdrr = <48 63>;
+ l0edrr = <48 63>;
+ l1cdrr = <8 11>;
+ l1edrr = <8 11>;
+ };
+ port@2 {
+ port_id = <2>;
+ ucast_queue = <160 175>;
+ mcast_queue = <276 279>;
+ l0sp = <40 43>;
+ l0cdrr = <64 79>;
+ l0edrr = <64 79>;
+ l1cdrr = <12 15>;
+ l1edrr = <12 15>;
+ };
+ port@3 {
+ port_id = <3>;
+ ucast_queue = <176 191>;
+ mcast_queue = <280 283>;
+ l0sp = <44 47>;
+ l0cdrr = <80 95>;
+ l0edrr = <80 95>;
+ l1cdrr = <16 19>;
+ l1edrr = <16 19>;
+ };
+ port@4 {
+ port_id = <4>;
+ ucast_queue = <192 207>;
+ mcast_queue = <284 287>;
+ l0sp = <48 51>;
+ l0cdrr = <96 111>;
+ l0edrr = <96 111>;
+ l1cdrr = <20 23>;
+ l1edrr = <20 23>;
+ };
+ port@5 {
+ port_id = <5>;
+ ucast_queue = <208 223>;
+ mcast_queue = <288 291>;
+ l0sp = <52 55>;
+ l0cdrr = <112 127>;
+ l0edrr = <112 127>;
+ l1cdrr = <24 27>;
+ l1edrr = <24 27>;
+ };
+ port@6 {
+ port_id = <6>;
+ ucast_queue = <224 239>;
+ mcast_queue = <292 295>;
+ l0sp = <56 59>;
+ l0cdrr = <128 143>;
+ l0edrr = <128 143>;
+ l1cdrr = <28 31>;
+ l1edrr = <28 31>;
+ };
+ port@7 {
+ port_id = <7>;
+ ucast_queue = <240 255>;
+ mcast_queue = <296 299>;
+ l0sp = <60 63>;
+ l0cdrr = <144 159>;
+ l0edrr = <144 159>;
+ l1cdrr = <32 35>;
+ l1edrr = <32 35>;
+ };
+ };
+ port_scheduler_config {
+ port@0 {
+ port_id = <0>;
+ l1scheduler {
+ group@0 {
+ sp = <0 1>; /*L0 SPs*/
+ /*cpri cdrr epri edrr*/
+ cfg = <0 0 0 0>;
+ };
+ };
+ l0scheduler {
+ group@0 {
+ /*unicast queues*/
+ ucast_queue = <0 4 8>;
+ /*multicast queues*/
+ mcast_queue = <256 260>;
+ /*sp cpricdrrepriedrr*/
+ cfg = <0 0 0 0 0>;
+ };
+ group@1 {
+ ucast_queue = <1 5 9>;
+ mcast_queue = <257 261>;
+ cfg = <0 1 1 1 1>;
+ };
+ group@2 {
+ ucast_queue = <2 6 10>;
+ mcast_queue = <258 262>;
+ cfg = <0 2 2 2 2>;
+ };
+ group@3 {
+ ucast_queue = <3 7 11>;
+ mcast_queue = <259 263>;
+ cfg = <0 3 3 3 3>;
+ };
+ };
+ };
+ port@1 {
+ port_id = <1>;
+ l1scheduler {
+ group@0 {
+ sp = <36>;
+ cfg = <0 8 0 8>;
+ };
+ group@1 {
+ sp = <37>;
+ cfg = <1 9 1 9>;
+ };
+ };
+ l0scheduler {
+ group@0 {
+ ucast_queue = <144>;
+ ucast_loop_pri = <16>;
+ mcast_queue = <272>;
+ mcast_loop_pri = <4>;
+ cfg = <36 0 48 0 48>;
+ };
+ };
+ };
+ port@2 {
+ port_id = <2>;
+ l1scheduler {
+ group@0 {
+ sp = <40>;
+ cfg = <0 12 0 12>;
+ };
+ group@1 {
+ sp = <41>;
+ cfg = <1 13 1 13>;
+ };
+ };
+ l0scheduler {
+ group@0 {
+ ucast_queue = <160>;
+ ucast_loop_pri = <16>;
+ mcast_queue = <276>;
+ mcast_loop_pri = <4>;
+ cfg = <40 0 64 0 64>;
+ };
+ };
+ };
+ port@3 {
+ port_id = <3>;
+ l1scheduler {
+ group@0 {
+ sp = <44>;
+ cfg = <0 16 0 16>;
+ };
+ group@1 {
+ sp = <45>;
+ cfg = <1 17 1 17>;
+ };
+ };
+ l0scheduler {
+ group@0 {
+ ucast_queue = <176>;
+ ucast_loop_pri = <16>;
+ mcast_queue = <280>;
+ mcast_loop_pri = <4>;
+ cfg = <44 0 80 0 80>;
+ };
+ };
+ };
+ port@4 {
+ port_id = <4>;
+ l1scheduler {
+ group@0 {
+ sp = <48>;
+ cfg = <0 20 0 20>;
+ };
+ group@1 {
+ sp = <49>;
+ cfg = <1 21 1 21>;
+ };
+ };
+ l0scheduler {
+ group@0 {
+ ucast_queue = <192>;
+ ucast_loop_pri = <16>;
+ mcast_queue = <284>;
+ mcast_loop_pri = <4>;
+ cfg = <48 0 96 0 96>;
+ };
+ };
+ };
+ port@5 {
+ port_id = <5>;
+ l1scheduler {
+ group@0 {
+ sp = <52>;
+ cfg = <0 24 0 24>;
+ };
+ group@1 {
+ sp = <53>;
+ cfg = <1 25 1 25>;
+ };
+ };
+ l0scheduler {
+ group@0 {
+ ucast_queue = <208>;
+ ucast_loop_pri = <16>;
+ mcast_queue = <288>;
+ mcast_loop_pri = <4>;
+ cfg = <52 0 112 0 112>;
+ };
+ };
+ };
+ port@6 {
+ port_id = <6>;
+ l1scheduler {
+ group@0 {
+ sp = <56>;
+ cfg = <0 28 0 28>;
+ };
+ group@1 {
+ sp = <57>;
+ cfg = <1 29 1 29>;
+ };
+ };
+ l0scheduler {
+ group@0 {
+ ucast_queue = <224>;
+ ucast_loop_pri = <16>;
+ mcast_queue = <292>;
+ mcast_loop_pri = <4>;
+ cfg = <56 0 128 0 128>;
+ };
+ };
+ };
+ port@7 {
+ port_id = <7>;
+ l1scheduler {
+ group@0 {
+ sp = <60>;
+ cfg = <0 32 0 32>;
+ };
+ group@1 {
+ sp = <61>;
+ cfg = <1 33 1 33>;
+ };
+ };
+ l0scheduler {
+ group@0 {
+ ucast_queue = <240>;
+ ucast_loop_pri = <16>;
+ mcast_queue = <296>;
+ cfg = <60 0 144 0 144>;
+ };
+ };
+ };
+ };
+ };
+
+ ess-uniphy@7a00000 {
+ compatible = "qcom,ess-uniphy";
+ reg = <0x7a00000 0x30000>;
+ uniphy_access_mode = "local bus";
+ };
+ };
+
+ dp1: dp1 {
+ device_type = "network";
+ compatible = "qcom,nss-dp";
+ qcom,id = <1>;
+ reg = <0x0 0x3a001000 0x0 0x200>;
+ qcom,mactype = <0>;
+ local-mac-address = [000000000000];
+ phy-mode = "sgmii";
+ status = "disabled";
+ };
+
+ dp2: dp2 {
+ device_type = "network";
+ compatible = "qcom,nss-dp";
+ qcom,id = <2>;
+ reg = <0x0 0x3a001200 0x0 0x200>;
+ qcom,mactype = <0>;
+ local-mac-address = [000000000000];
+ phy-mode = "sgmii";
+ status = "disabled";
+ };
+
+ dp3: dp3 {
+ device_type = "network";
+ compatible = "qcom,nss-dp";
+ qcom,id = <3>;
+ reg = <0x0 0x3a001400 0x0 0x200>;
+ qcom,mactype = <0>;
+ local-mac-address = [000000000000];
+ phy-mode = "sgmii";
+ status = "disabled";
+ };
+
+ dp4: dp4 {
+ device_type = "network";
+ compatible = "qcom,nss-dp";
+ qcom,id = <4>;
+ reg = <0x0 0x3a001600 0x0 0x200>;
+ qcom,mactype = <0>;
+ local-mac-address = [000000000000];
+ phy-mode = "sgmii";
+ status = "disabled";
+ };
+
+ dp5: dp5 {
+ device_type = "network";
+ compatible = "qcom,nss-dp";
+ qcom,id = <5>;
+ reg = <0x0 0x3a001800 0x0 0x200>;
+ qcom,mactype = <0>;
+ local-mac-address = [000000000000];
+ phy-mode = "sgmii";
+ status = "disabled";
+ };
+};
--- /dev/null
+CONFIG_IPQ_GCC_6018=y
+CONFIG_MTD_SPLIT_FIT_FW=y
+CONFIG_PINCTRL_IPQ6018=y
+CONFIG_QCOM_APM=y
+# CONFIG_QCOM_CLK_SMD_RPM is not set
+# CONFIG_QCOM_RPMPD is not set
+CONFIG_QCOM_SMD_RPM=y
+CONFIG_REGULATOR_CPR3=y
+# CONFIG_REGULATOR_CPR3_NPU is not set
+CONFIG_REGULATOR_CPR4_APSS=y
+CONFIG_REGULATOR_QCOM_SMD_RPM=y
--- /dev/null
+SUBTARGET:=ipq60xx
+FEATURES += source-only
+BOARDNAME:=Qualcomm Atheros IPQ60xx
+DEFAULT_PACKAGES += ath11k-firmware-ipq6018
+
+define Target/Description
+ Build firmware images for Qualcomm Atheros IPQ60xx based boards.
+endef
--- /dev/null
+From 1e8a314a1b87eaba496fcc6dc0efef573b3c186d Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Mon, 17 Apr 2023 19:44:07 +0200
+Subject: [PATCH] clk: qcom: gcc-ipq6018: drop redundant F define
+
+The same exact F frequency table entry is defined in clk-rcg.h
+Drop the redundant define to cleanup code.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20230417174408.23722-1-ansuelsmth@gmail.com
+---
+ drivers/clk/qcom/gcc-ipq6018.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+--- a/drivers/clk/qcom/gcc-ipq6018.c
++++ b/drivers/clk/qcom/gcc-ipq6018.c
+@@ -26,8 +26,6 @@
+ #include "clk-regmap-mux.h"
+ #include "reset.h"
+
+-#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
+-
+ enum {
+ P_XO,
+ P_BIAS_PLL,
--- /dev/null
+From 91e7c87f0ec1d644afb65cf3a16ded874c9d4ab9 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Fri, 26 May 2023 21:08:54 +0200
+Subject: [PATCH] clk: qcom: gcc-ipq6018: update UBI32 PLL
+
+Update the UBI32 alpha PLL config to the latest values from the downstream
+QCA 5.4 kernel.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20230526190855.2941291-1-robimarko@gmail.com
+---
+ drivers/clk/qcom/gcc-ipq6018.c | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+--- a/drivers/clk/qcom/gcc-ipq6018.c
++++ b/drivers/clk/qcom/gcc-ipq6018.c
+@@ -4143,15 +4143,20 @@ static struct clk_branch gcc_dcc_clk = {
+
+ static const struct alpha_pll_config ubi32_pll_config = {
+ .l = 0x3e,
+- .alpha = 0x57,
++ .alpha = 0x6667,
+ .config_ctl_val = 0x240d6aa8,
+ .config_ctl_hi_val = 0x3c2,
++ .config_ctl_val = 0x240d4828,
++ .config_ctl_hi_val = 0x6,
+ .main_output_mask = BIT(0),
+ .aux_output_mask = BIT(1),
+ .pre_div_val = 0x0,
+ .pre_div_mask = BIT(12),
+ .post_div_val = 0x0,
+ .post_div_mask = GENMASK(9, 8),
++ .alpha_en_mask = BIT(24),
++ .test_ctl_val = 0x1C0000C0,
++ .test_ctl_hi_val = 0x4000,
+ };
+
+ static const struct alpha_pll_config nss_crypto_pll_config = {
--- /dev/null
+From 3f2fbfe6e4f6f2bdd1da8ef5aceba3945c4ada57 Mon Sep 17 00:00:00 2001
+From: Arnd Bergmann <arnd@arndb.de>
+Date: Thu, 1 Jun 2023 23:34:12 +0200
+Subject: [PATCH] clk: qcom: gcc-ipq6018: remove duplicate initializers
+
+A recent change added new initializers for .config_ctl_val and
+.config_ctl_hi_val but left the old values in place:
+
+drivers/clk/qcom/gcc-ipq6018.c:4155:27: error: initialized field overwritten [-Werror=override-init]
+ 4155 | .config_ctl_val = 0x240d4828,
+ | ^~~~~~~~~~
+drivers/clk/qcom/gcc-ipq6018.c:4156:30: error: initialized field overwritten [-Werror=override-init]
+ 4156 | .config_ctl_hi_val = 0x6,
+ | ^~~
+
+Remove the unused ones now to avoid confusion.
+
+Fixes: f4f0c8acee0e4 ("clk: qcom: gcc-ipq6018: update UBI32 PLL")
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Reviewed-by: Robert Marko <robimarko@gmail.com>
+Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20230601213416.3373599-1-arnd@kernel.org
+---
+ drivers/clk/qcom/gcc-ipq6018.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+--- a/drivers/clk/qcom/gcc-ipq6018.c
++++ b/drivers/clk/qcom/gcc-ipq6018.c
+@@ -4144,8 +4144,6 @@ static struct clk_branch gcc_dcc_clk = {
+ static const struct alpha_pll_config ubi32_pll_config = {
+ .l = 0x3e,
+ .alpha = 0x6667,
+- .config_ctl_val = 0x240d6aa8,
+- .config_ctl_hi_val = 0x3c2,
+ .config_ctl_val = 0x240d4828,
+ .config_ctl_hi_val = 0x6,
+ .main_output_mask = BIT(0),
--- /dev/null
+From 62a5df451ab911421da96655fcc4d1e269ff6e2f Mon Sep 17 00:00:00 2001
+From: Mantas Pucka <mantas@8devices.com>
+Date: Tue, 23 Jan 2024 18:09:20 +0200
+Subject: [PATCH] phy: qcom-qmp-usb: fix serdes init sequence for IPQ6018
+
+Commit 23fd679249df ("phy: qcom-qmp: add USB3 PHY support for IPQ6018")
+noted that IPQ6018 init is identical to IPQ8074. Yet downstream uses
+separate serdes init sequence for IPQ6018. Since already existing IPQ9574
+serdes init sequence is identical, just reuse it and fix failing USB3 mode
+in IPQ6018.
+
+Fixes: 23fd679249df ("phy: qcom-qmp: add USB3 PHY support for IPQ6018")
+Signed-off-by: Mantas Pucka <mantas@8devices.com>
+Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Link: https://lore.kernel.org/r/1706026160-17520-3-git-send-email-mantas@8devices.com
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+---
+ drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 20 +++++++++++++++++++-
+ 1 file changed, 19 insertions(+), 1 deletion(-)
+
+--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
++++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+@@ -233,6 +233,43 @@ static const struct qmp_phy_init_tbl ipq
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
+ };
+
++static const struct qmp_phy_init_tbl ipq9574_usb3_serdes_tbl[] = {
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
++ /* PLL and Loop filter settings */
++ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x68),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0xab),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0xaa),
++ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x02),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x09),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
++ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
++ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0xa0),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xaa),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x29),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
++ /* SSC settings */
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x7d),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x0a),
++ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x05),
++};
++
+ static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
+@@ -1591,6 +1628,26 @@ static const char * const qmp_phy_vreg_l
+ "vdda-phy", "vdda-pll",
+ };
+
++static const struct qmp_phy_cfg ipq6018_usb3phy_cfg = {
++ .lanes = 1,
++
++ .serdes_tbl = ipq9574_usb3_serdes_tbl,
++ .serdes_tbl_num = ARRAY_SIZE(ipq9574_usb3_serdes_tbl),
++ .tx_tbl = msm8996_usb3_tx_tbl,
++ .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
++ .rx_tbl = ipq8074_usb3_rx_tbl,
++ .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
++ .pcs_tbl = ipq8074_usb3_pcs_tbl,
++ .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
++ .clk_list = msm8996_phy_clk_l,
++ .num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
++ .reset_list = msm8996_usb3phy_reset_l,
++ .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
++ .vreg_list = qmp_phy_vreg_l,
++ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
++ .regs = qmp_v3_usb3phy_regs_layout,
++};
++
+ static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
+ .lanes = 1,
+
+@@ -2534,7 +2591,7 @@ static const struct of_device_id qmp_usb
+ .data = &msm8996_usb3phy_cfg,
+ }, {
+ .compatible = "qcom,ipq6018-qmp-usb3-phy",
+- .data = &ipq8074_usb3phy_cfg,
++ .data = &ipq6018_usb3phy_cfg,
+ }, {
+ .compatible = "qcom,sc7180-qmp-usb3-phy",
+ .data = &sc7180_usb3phy_cfg,
--- /dev/null
+From fd712118aa1aa758da1fd1546b3f8a1b00e42cbc Mon Sep 17 00:00:00 2001
+From: Mantas Pucka <mantas@8devices.com>
+Date: Tue, 23 Jan 2024 11:26:09 +0200
+Subject: [PATCH] clk: qcom: gcc-ipq6018: add qdss_at clock needed for wifi
+ operation
+
+Without it system hangs upon wifi firmware load. It should be enabled by
+remoteproc/wifi driver. Bindings already exist for it, so add it based
+on vendor code.
+
+Signed-off-by: Mantas Pucka <mantas@8devices.com>
+Link: https://lore.kernel.org/r/1706001970-26032-1-git-send-email-mantas@8devices.com
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+---
+ drivers/clk/qcom/gcc-ipq6018.c | 17 +++++++++++++++++
+ 1 file changed, 17 insertions(+)
+
+--- a/drivers/clk/qcom/gcc-ipq6018.c
++++ b/drivers/clk/qcom/gcc-ipq6018.c
+@@ -3503,6 +3503,22 @@ static struct clk_branch gcc_prng_ahb_cl
+ },
+ };
+
++static struct clk_branch gcc_qdss_at_clk = {
++ .halt_reg = 0x29024,
++ .clkr = {
++ .enable_reg = 0x29024,
++ .enable_mask = BIT(0),
++ .hw.init = &(struct clk_init_data){
++ .name = "gcc_qdss_at_clk",
++ .parent_hws = (const struct clk_hw *[]){
++ &qdss_at_clk_src.clkr.hw },
++ .num_parents = 1,
++ .flags = CLK_SET_RATE_PARENT,
++ .ops = &clk_branch2_ops,
++ },
++ },
++};
++
+ static struct clk_branch gcc_qdss_dap_clk = {
+ .halt_reg = 0x29084,
+ .clkr = {
+@@ -4341,6 +4357,7 @@ static struct clk_regmap *gcc_ipq6018_cl
+ [GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr,
+ [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
+ [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
++ [GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr,
+ [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
+ [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
+ [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
--- /dev/null
+From 546f0617a22a481f3ca1f7e058aea0c40517c64e Mon Sep 17 00:00:00 2001
+From: Kathiravan T <quic_kathirav@quicinc.com>
+Date: Fri, 26 May 2023 18:23:04 +0530
+Subject: [PATCH] arm64: dts: qcom: ipq6018: add QFPROM node
+
+IPQ6018 has efuse region to determine the various HW quirks. Lets
+add the initial support and the individual fuses will be added as they
+are required.
+
+Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
+Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
+Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20230526125305.19626-4-quic_kathirav@quicinc.com
+---
+ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+@@ -179,6 +179,13 @@
+ dma-ranges;
+ compatible = "simple-bus";
+
++ qfprom: efuse@a4000 {
++ compatible = "qcom,ipq6018-qfprom", "qcom,qfprom";
++ reg = <0x0 0x000a4000 0x0 0x2000>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ };
++
+ prng: qrng@e1000 {
+ compatible = "qcom,prng-ee";
+ reg = <0x0 0xe3000 0x0 0x1000>;
--- /dev/null
+From 47e161a7873b0891f4e01a69a839f6161d816ea8 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Wed, 25 Oct 2023 14:57:57 +0530
+Subject: [PATCH] cpufreq: qcom-nvmem: add support for IPQ6018
+
+IPQ6018 SoC series comes in multiple SKU-s, and not all of them support
+high frequency OPP points.
+
+SoC itself does however have a single bit in QFPROM to indicate the CPU
+speed-bin.
+That bit is used to indicate frequency limit of 1.5GHz, but that alone is
+not enough as IPQ6000 only goes up to 1.2GHz, but SMEM ID can be used to
+limit it further.
+
+IPQ6018 compatible is blacklisted from DT platdev as the cpufreq device
+will get created by NVMEM CPUFreq driver.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+[ Viresh: Fixed rebase conflict. ]
+Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
+---
+ drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
+ drivers/cpufreq/qcom-cpufreq-nvmem.c | 58 ++++++++++++++++++++++++++++++++++++
+ 2 files changed, 59 insertions(+)
+
+--- a/drivers/cpufreq/cpufreq-dt-platdev.c
++++ b/drivers/cpufreq/cpufreq-dt-platdev.c
+@@ -163,6 +163,7 @@ static const struct of_device_id blockli
+ { .compatible = "ti,dra7", },
+ { .compatible = "ti,omap3", },
+
++ { .compatible = "qcom,ipq6018", },
+ { .compatible = "qcom,ipq8064", },
+ { .compatible = "qcom,ipq8074", },
+ { .compatible = "qcom,apq8064", },
+--- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
++++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
+@@ -36,6 +36,8 @@ enum ipq8074_versions {
+ IPQ8074_ACORN_VERSION,
+ };
+
++#define IPQ6000_VERSION BIT(2)
++
+ struct qcom_cpufreq_drv;
+
+ struct qcom_cpufreq_match_data {
+@@ -209,6 +211,57 @@ len_error:
+ return ret;
+ }
+
++static int qcom_cpufreq_ipq6018_name_version(struct device *cpu_dev,
++ struct nvmem_cell *speedbin_nvmem,
++ char **pvs_name,
++ struct qcom_cpufreq_drv *drv)
++{
++ u32 msm_id;
++ int ret;
++ u8 *speedbin;
++ *pvs_name = NULL;
++
++ ret = qcom_smem_get_soc_id(&msm_id);
++ if (ret)
++ return ret;
++
++ speedbin = nvmem_cell_read(speedbin_nvmem, NULL);
++ if (IS_ERR(speedbin))
++ return PTR_ERR(speedbin);
++
++ switch (msm_id) {
++ case QCOM_ID_IPQ6005:
++ case QCOM_ID_IPQ6010:
++ case QCOM_ID_IPQ6018:
++ case QCOM_ID_IPQ6028:
++ /* Fuse Value Freq BIT to set
++ * ---------------------------------
++ * 2’b0 No Limit BIT(0)
++ * 2’b1 1.5 GHz BIT(1)
++ */
++ drv->versions = 1 << (unsigned int)(*speedbin);
++ break;
++ case QCOM_ID_IPQ6000:
++ /*
++ * IPQ6018 family only has one bit to advertise the CPU
++ * speed-bin, but that is not enough for IPQ6000 which
++ * is only rated up to 1.2GHz.
++ * So for IPQ6000 manually set BIT(2) based on SMEM ID.
++ */
++ drv->versions = IPQ6000_VERSION;
++ break;
++ default:
++ dev_err(cpu_dev,
++ "SoC ID %u is not part of IPQ6018 family, limiting to 1.2GHz!\n",
++ msm_id);
++ drv->versions = IPQ6000_VERSION;
++ break;
++ }
++
++ kfree(speedbin);
++ return 0;
++}
++
+ static int qcom_cpufreq_ipq8074_name_version(struct device *cpu_dev,
+ struct nvmem_cell *speedbin_nvmem,
+ char **pvs_name,
+@@ -265,6 +318,10 @@ static const struct qcom_cpufreq_match_d
+ .get_version = qcom_cpufreq_ipq8074_name_version,
+ };
+
++static const struct qcom_cpufreq_match_data match_data_ipq6018 = {
++ .get_version = qcom_cpufreq_ipq6018_name_version,
++};
++
+ static int qcom_cpufreq_probe(struct platform_device *pdev)
+ {
+ struct qcom_cpufreq_drv *drv;
+@@ -409,6 +466,7 @@ static const struct of_device_id qcom_cp
+ { .compatible = "qcom,apq8096", .data = &match_data_kryo },
+ { .compatible = "qcom,msm8996", .data = &match_data_kryo },
+ { .compatible = "qcom,qcs404", .data = &match_data_qcs404 },
++ { .compatible = "qcom,ipq6018", .data = &match_data_ipq6018 },
+ { .compatible = "qcom,ipq8064", .data = &match_data_krait },
+ { .compatible = "qcom,ipq8074", .data = &match_data_ipq8074 },
+ { .compatible = "qcom,apq8064", .data = &match_data_krait },
--- /dev/null
+From a120815200adaf3ac28ccf3a1813c78b4be02cc4 Mon Sep 17 00:00:00 2001
+From: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
+Date: Thu, 14 Sep 2023 12:29:59 +0530
+Subject: [PATCH] arm64: dts: qcom: ipq6018: include the GPLL0 as clock
+ provider for mailbox
+
+While the kernel is booting up, APSS PLL will be running at 800MHz with
+GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be
+configured to the rate based on the opp table and the source also will
+be changed to APSS_PLL_EARLY. So allow the mailbox to consume the GPLL0,
+with this inclusion, CPU Freq correctly reports that CPU is running at
+800MHz rather than 24MHz.
+
+Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
+Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
+---
+ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+@@ -503,8 +503,8 @@
+ compatible = "qcom,ipq6018-apcs-apps-global";
+ reg = <0x0 0x0b111000 0x0 0x1000>;
+ #clock-cells = <1>;
+- clocks = <&a53pll>, <&xo>;
+- clock-names = "pll", "xo";
++ clocks = <&a53pll>, <&xo>, <&gcc GPLL0>;
++ clock-names = "pll", "xo", "gpll0";
+ #mbox-cells = <1>;
+ };
+
--- /dev/null
+From 9dd19a9ae36bc60d58287d0c52e53024d484e64d Mon Sep 17 00:00:00 2001
+From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
+Date: Fri, 29 Jan 2021 22:41:59 +0530
+Subject: [PATCH 2/3] remoteproc: qcom: wcss: populate driver data for IPQ6018
+
+Populate hardcoded param using driver data for IPQ6018 SoCs.
+
+Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
+---
+ drivers/remoteproc/qcom_q6v5_wcss.c | 19 +++++++++++++++++--
+ 1 file changed, 17 insertions(+), 2 deletions(-)
+
+--- a/drivers/remoteproc/qcom_q6v5_wcss.c
++++ b/drivers/remoteproc/qcom_q6v5_wcss.c
+@@ -970,7 +970,7 @@ static int q6v5_alloc_memory_region(stru
+ return 0;
+ }
+
+-static int ipq8074_init_clock(struct q6v5_wcss *wcss)
++static int ipq_init_clock(struct q6v5_wcss *wcss)
+ {
+ int ret;
+
+@@ -1179,7 +1179,7 @@ static int q6v5_wcss_remove(struct platf
+ }
+
+ static const struct wcss_data wcss_ipq8074_res_init = {
+- .init_clock = ipq8074_init_clock,
++ .init_clock = ipq_init_clock,
+ .q6_firmware_name = "IPQ8074/q6_fw.mdt",
+ .m3_firmware_name = "IPQ8074/m3_fw.mdt",
+ .crash_reason_smem = WCSS_CRASH_REASON,
+@@ -1193,6 +1193,20 @@ static const struct wcss_data wcss_ipq80
+ .need_auto_boot = false,
+ };
+
++static const struct wcss_data wcss_ipq6018_res_init = {
++ .init_clock = ipq_init_clock,
++ .q6_firmware_name = "IPQ6018/q6_fw.mdt",
++ .m3_firmware_name = "IPQ6018/m3_fw.mdt",
++ .crash_reason_smem = WCSS_CRASH_REASON,
++ .aon_reset_required = true,
++ .wcss_q6_reset_required = true,
++ .bcr_reset_required = false,
++ .ssr_name = "q6wcss",
++ .ops = &q6v5_wcss_ipq8074_ops,
++ .requires_force_stop = true,
++ .need_mem_protection = true,
++};
++
+ static const struct wcss_data wcss_qcs404_res_init = {
+ .init_clock = qcs404_init_clock,
+ .init_regulator = qcs404_init_regulator,
+@@ -1212,6 +1226,7 @@ static const struct wcss_data wcss_qcs40
+
+ static const struct of_device_id q6v5_wcss_of_match[] = {
+ { .compatible = "qcom,ipq8074-wcss-pil", .data = &wcss_ipq8074_res_init },
++ { .compatible = "qcom,ipq6018-wcss-pil", .data = &wcss_ipq6018_res_init },
+ { .compatible = "qcom,qcs404-wcss-pil", .data = &wcss_qcs404_res_init },
+ { },
+ };
--- /dev/null
+From e4d7544ce092807e8c5aeb618cec30e2eb9b40c2 Mon Sep 17 00:00:00 2001
+From: Mantas Pucka <mantas@8devices.com>
+Date: Mon, 24 Apr 2023 15:13:32 +0300
+Subject: [PATCH 3/3] arm64: dts: qcom: ipq6018: add SDHCI node
+
+IPQ6018 has one SD/eMMC controller, add node for it.
+
+Signed-off-by: Mantas Pucka <mantas@8devices.com>
+Tested-by: Robert Marko <robimarko@gmail.com>
+---
+ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 23 +++++++++++++++++++++++
+ 1 file changed, 23 insertions(+)
+
+--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+@@ -264,6 +264,29 @@
+ reg = <0x0 0x01937000 0x0 0x21000>;
+ };
+
++ sdhc_1: mmc@7804000 {
++ compatible = "qcom,ipq6018-sdhci", "qcom,sdhci-msm-v5";
++ reg = <0x0 0x07804000 0x0 0x1000>,
++ <0x0 0x07805000 0x0 0x1000>,
++ <0x0 0x07808000 0x0 0x2000>;
++ reg-names = "hc", "cqhci", "ice";
++
++ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
++ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "hc_irq", "pwr_irq";
++
++ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
++ <&gcc GCC_SDCC1_APPS_CLK>,
++ <&xo>,
++ <&gcc GCC_SDCC1_ICE_CORE_CLK>;
++ clock-names = "iface", "core", "xo", "ice";
++
++ resets = <&gcc GCC_SDCC1_BCR>;
++ supports-cqe;
++ bus-width = <8>;
++ status = "disabled";
++ };
++
+ blsp_dma: dma-controller@7884000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x0 0x07884000 0x0 0x2b000>;
--- /dev/null
+From a120815200adaf3ac28ccf3a1813c78b4be02cc4 Mon Sep 17 00:00:00 2001
+From: Vignesh Viswanathan <quic_viswanat@quicinc.com>
+Date: Tue, 5 Sep 2023 15:25:35 +0530
+Subject: [PATCH v2 2/2] hwspinlock: qcom: Remove IPQ6018 SOC specific compatible
+
+IPQ6018 has 32 tcsr_mutex hwlock registers with stride 0x1000.
+The compatible string qcom,ipq6018-tcsr-mutex is mapped to
+of_msm8226_tcsr_mutex which has 32 locks configured with stride of 0x80
+and doesn't match the HW present in IPQ6018.
+
+Remove IPQ6018 specific compatible string so that it fallsback to
+of_tcsr_mutex data which maps to the correct configuration for IPQ6018.
+
+Changes in v2:
+ - Updated commit message
+ - Added Fixes and stable tags
+
+Cc: stable@vger.kernel.org
+Fixes: 5d4753f741d8 ("hwspinlock: qcom: add support for MMIO on older SoCs")
+Signed-off-by: Vignesh Viswanathan <quic_viswanat@quicinc.com>
+---
+ drivers/hwspinlock/qcom_hwspinlock.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+--- a/drivers/hwspinlock/qcom_hwspinlock.c
++++ b/drivers/hwspinlock/qcom_hwspinlock.c
+@@ -115,7 +115,6 @@ static const struct of_device_id qcom_hw
+ { .compatible = "qcom,sfpb-mutex", .data = &of_sfpb_mutex },
+ { .compatible = "qcom,tcsr-mutex", .data = &of_tcsr_mutex },
+ { .compatible = "qcom,apq8084-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
+- { .compatible = "qcom,ipq6018-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
+ { .compatible = "qcom,msm8226-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
+ { .compatible = "qcom,msm8974-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
+ { .compatible = "qcom,msm8994-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },
--- /dev/null
+From d24bc08bfc66f47d6e0a294a080d62893a7696b5 Mon Sep 17 00:00:00 2001
+From: Chukun Pan <amadeus@jmu.edu.cn>
+Date: Thu, 18 Jan 2024 21:30:21 +0800
+Subject: [PATCH] arm64: dts: qcom: ipq6018: add LDOA2 regulator
+
+Add LDOA2 regulator of MP5496 to support SDCC voltage scaling.
+
+Suggested-by: Robert Marko <robimarko@gmail.com>
+Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
+---
+ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+@@ -840,6 +840,11 @@
+ regulator-max-microvolt = <1062500>;
+ regulator-always-on;
+ };
++
++ ipq6018_l2: l2 {
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ };
+ };
+ };
+ };
--- /dev/null
+From 946b1a565a60a04f8e5171a79a463f99485a3531 Mon Sep 17 00:00:00 2001
+From: Mantas Pucka <mantas@8devices.com>
+Date: Wed, 24 Jan 2024 15:07:24 +0200
+Subject: [PATCH 2/3] arm64: dts: qcom: ipq6018: add tsens node
+
+IPQ6018 has temperature sensing HW block compatible with IPQ8074. Add
+node for it.
+
+Signed-off-by: Mantas Pucka <mantas@8devices.com>
+---
+ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+@@ -193,6 +193,16 @@
+ clock-names = "core";
+ };
+
++ tsens: thermal-sensor@4a9000 {
++ compatible = "qcom,ipq6018-tsens", "qcom,ipq8074-tsens";
++ reg = <0x0 0x004a9000 0x0 0x1000>,
++ <0x0 0x004a8000 0x0 0x1000>;
++ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "combined";
++ #qcom,sensors = <16>;
++ #thermal-sensor-cells = <1>;
++ };
++
+ cryptobam: dma-controller@704000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x0 0x00704000 0x0 0x20000>;
--- /dev/null
+From 92c65f959ec2b8d1ab26efe246b29ed538b45c86 Mon Sep 17 00:00:00 2001
+From: Mantas Pucka <mantas@8devices.com>
+Date: Wed, 24 Jan 2024 15:10:43 +0200
+Subject: [PATCH 3/3] arm64: dts: qcom: ipq6018: add thermal zones
+
+Add thermal zones to make use of thermal sensors data. For CPU zone,
+add cooling device that uses CPU frequency scaling.
+
+Signed-off-by: Mantas Pucka <mantas@8devices.com>
+---
+ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 121 ++++++++++++++++++++++++++++++++++
+ 1 file changed, 121 insertions(+)
+
+--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+@@ -9,6 +9,7 @@
+ #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
+ #include <dt-bindings/reset/qcom,gcc-ipq6018.h>
+ #include <dt-bindings/clock/qcom,apss-ipq.h>
++#include <dt-bindings/thermal/thermal.h>
+
+ / {
+ #address-cells = <2>;
+@@ -43,6 +44,7 @@
+ clock-names = "cpu";
+ operating-points-v2 = <&cpu_opp_table>;
+ cpu-supply = <&ipq6018_s2>;
++ #cooling-cells = <2>;
+ };
+
+ CPU1: cpu@1 {
+@@ -55,6 +57,7 @@
+ clock-names = "cpu";
+ operating-points-v2 = <&cpu_opp_table>;
+ cpu-supply = <&ipq6018_s2>;
++ #cooling-cells = <2>;
+ };
+
+ CPU2: cpu@2 {
+@@ -67,6 +70,7 @@
+ clock-names = "cpu";
+ operating-points-v2 = <&cpu_opp_table>;
+ cpu-supply = <&ipq6018_s2>;
++ #cooling-cells = <2>;
+ };
+
+ CPU3: cpu@3 {
+@@ -79,6 +83,7 @@
+ clock-names = "cpu";
+ operating-points-v2 = <&cpu_opp_table>;
+ cpu-supply = <&ipq6018_s2>;
++ #cooling-cells = <2>;
+ };
+
+ L2_0: l2-cache {
+@@ -807,6 +812,122 @@
+ };
+ };
+ };
++
++ thermal-zones {
++ nss-top-thermal {
++ polling-delay-passive = <250>;
++ polling-delay = <1000>;
++ thermal-sensors = <&tsens 4>;
++
++ trips {
++ nss-top-critical {
++ temperature = <125000>;
++ hysteresis = <1000>;
++ type = "critical";
++ };
++ };
++ };
++
++ nss-thermal {
++ polling-delay-passive = <250>;
++ polling-delay = <1000>;
++ thermal-sensors = <&tsens 5>;
++
++ trips {
++ nss-critical {
++ temperature = <125000>;
++ hysteresis = <1000>;
++ type = "critical";
++ };
++ };
++ };
++
++ wcss-phya0-thermal {
++ polling-delay-passive = <250>;
++ polling-delay = <1000>;
++ thermal-sensors = <&tsens 7>;
++
++ trips {
++ wcss-phya0-critical {
++ temperature = <125000>;
++ hysteresis = <1000>;
++ type = "critical";
++ };
++ };
++ };
++
++ wcss-phya1-thermal {
++ polling-delay-passive = <250>;
++ polling-delay = <1000>;
++ thermal-sensors = <&tsens 8>;
++
++ trips {
++ wcss-phya1-critical {
++ temperature = <125000>;
++ hysteresis = <1000>;
++ type = "critical";
++ };
++ };
++ };
++
++ cpu-thermal {
++ polling-delay-passive = <250>;
++ polling-delay = <1000>;
++ thermal-sensors = <&tsens 13>;
++
++ trips {
++ cpu-critical {
++ temperature = <125000>;
++ hysteresis = <1000>;
++ type = "critical";
++ };
++
++ cpu_alert: cpu-passive {
++ temperature = <110000>;
++ hysteresis = <1000>;
++ type = "passive";
++ };
++ };
++
++ cooling-maps {
++ map0 {
++ trip = <&cpu_alert>;
++ cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
++ <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
++ <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
++ <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
++ };
++ };
++ };
++
++ lpass-thermal {
++ polling-delay-passive = <250>;
++ polling-delay = <1000>;
++ thermal-sensors = <&tsens 14>;
++
++ trips {
++ lpass-critical {
++ temperature = <125000>;
++ hysteresis = <1000>;
++ type = "critical";
++ };
++ };
++ };
++
++ ddrss-top-thermal {
++ polling-delay-passive = <250>;
++ polling-delay = <1000>;
++ thermal-sensors = <&tsens 15>;
++
++ trips {
++ ddrss-top-critical {
++ temperature = <125000>;
++ hysteresis = <1000>;
++ type = "critical";
++ };
++ };
++ };
++ };
+
+ wcss: wcss-smp2p {
+ compatible = "qcom,smp2p";
--- /dev/null
+From 83afcf14edb9217e58837eb119da96d734a4b3b1 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Sat, 21 Oct 2023 14:00:07 +0200
+Subject: [PATCH] arm64: dts: qcom: ipq6018: use CPUFreq NVMEM
+
+IPQ6018 comes in multiple SKU-s and some of them dont support all of the
+OPP-s that are current set, so lets utilize CPUFreq NVMEM to allow only
+supported OPP-s based on the SoC dynamically.
+
+As an example, IPQ6018 is generaly rated at 1.8GHz but some silicon only
+goes up to 1.5GHz and is marked as such via an eFuse.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
+Link: https://lore.kernel.org/r/20231021120048.231239-1-robimarko@gmail.com
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+---
+ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 14 +++++++++++++-
+ 1 file changed, 13 insertions(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+@@ -93,37 +93,49 @@
+ };
+
+ cpu_opp_table: opp-table-cpu {
+- compatible = "operating-points-v2";
++ compatible = "operating-points-v2-kryo-cpu";
++ nvmem-cells = <&cpu_speed_bin>;
+ opp-shared;
+
+ opp-864000000 {
+ opp-hz = /bits/ 64 <864000000>;
+ opp-microvolt = <725000>;
++ opp-supported-hw = <0xf>;
+ clock-latency-ns = <200000>;
+ };
++
+ opp-1056000000 {
+ opp-hz = /bits/ 64 <1056000000>;
+ opp-microvolt = <787500>;
++ opp-supported-hw = <0xf>;
+ clock-latency-ns = <200000>;
+ };
++
+ opp-1320000000 {
+ opp-hz = /bits/ 64 <1320000000>;
+ opp-microvolt = <862500>;
++ opp-supported-hw = <0x3>;
+ clock-latency-ns = <200000>;
+ };
++
+ opp-1440000000 {
+ opp-hz = /bits/ 64 <1440000000>;
+ opp-microvolt = <925000>;
++ opp-supported-hw = <0x3>;
+ clock-latency-ns = <200000>;
+ };
++
+ opp-1608000000 {
+ opp-hz = /bits/ 64 <1608000000>;
+ opp-microvolt = <987500>;
++ opp-supported-hw = <0x1>;
+ clock-latency-ns = <200000>;
+ };
++
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <1062500>;
++ opp-supported-hw = <0x1>;
+ clock-latency-ns = <200000>;
+ };
+ };
+@@ -189,6 +201,11 @@
+ reg = <0x0 0x000a4000 0x0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
++
++ cpu_speed_bin: cpu-speed-bin@135 {
++ reg = <0x135 0x1>;
++ bits = <7 1>;
++ };
+ };
+
+ prng: qrng@e1000 {
--- /dev/null
+From 563db68137475d011b355bfe674d1b7a24778091 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Sat, 8 Oct 2022 22:26:31 +0200
+Subject: [PATCH] psci: dont advertise OSI support for IPQ6018
+
+Some older IPQ60xx SoC series boards ship with TrustZone/QSEE firmware
+older than TZ.WNS.5.1-00084 which will advertise OSI[1] but are broken
+and trying to use OSI will cause the board to hang until WDT kicks in.
+
+So workaround it by checking for SoC compatible and returning false so
+OSI is not used.
+
+[1] https://www.spinics.net/lists/linux-arm-msm/msg79916.html
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+---
+ drivers/firmware/psci/psci.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+--- a/drivers/firmware/psci/psci.c
++++ b/drivers/firmware/psci/psci.c
+@@ -87,6 +87,18 @@ static inline bool psci_has_ext_power_st
+
+ bool psci_has_osi_support(void)
+ {
++ /*
++ * Some older IPQ60xx SoC series boards ship with
++ * TrustZone/QSEE firmware older than TZ.WNS.5.1-00084
++ * which will advertise OSI but is broken and trying
++ * to use OSI will cause the board to hang until WDT
++ * kicks in.
++ * So workaround it by checking for SoC compatible
++ * and returning false so OSI is not used.
++ */
++ if (of_machine_is_compatible("qcom,ipq6018"))
++ return false;
++
+ return psci_cpu_suspend_feature & PSCI_1_0_OS_INITIATED;
+ }
+
--- /dev/null
+From 0c5b5243ad55ae744e790ba90c5ad37a93bd1377 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Tue, 11 Oct 2022 23:38:45 +0200
+Subject: [PATCH] clk: qcom: ipq6018: workaround networking clock parenting
+
+Currently, networking clocks are only looked up by fw_name however,
+these are registered and setup by SSDK and are not available to the
+GCC driver at all, so work around that by providing a global name
+fallback.
+
+While we are here, provide global fallback for bias_pll_cc_clk and
+bias_pll_nss_noc_clk as well as these are fixed clocks also not available
+to the driver.
+
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+---
+ drivers/clk/qcom/gcc-ipq6018.c | 39 +++++++++++++++++-----------------
+ 1 file changed, 19 insertions(+), 20 deletions(-)
+
+--- a/drivers/clk/qcom/gcc-ipq6018.c
++++ b/drivers/clk/qcom/gcc-ipq6018.c
+@@ -361,7 +361,7 @@ static const struct freq_tbl ftbl_nss_pp
+
+ static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
+ { .fw_name = "xo" },
+- { .fw_name = "bias_pll_cc_clk" },
++ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll4.clkr.hw },
+ { .hw = &nss_crypto_pll.clkr.hw },
+@@ -527,12 +527,12 @@ static const struct freq_tbl ftbl_nss_po
+ static const struct clk_parent_data
+ gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
+ { .fw_name = "xo" },
+- { .fw_name = "uniphy0_gcc_rx_clk" },
+- { .fw_name = "uniphy0_gcc_tx_clk" },
+- { .fw_name = "uniphy1_gcc_rx_clk" },
+- { .fw_name = "uniphy1_gcc_tx_clk" },
++ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
++ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
++ { .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
++ { .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
+ { .hw = &ubi32_pll.clkr.hw },
+- { .fw_name = "bias_pll_cc_clk" },
++ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
+ };
+
+ static const struct parent_map
+@@ -574,12 +574,12 @@ static const struct freq_tbl ftbl_nss_po
+ static const struct clk_parent_data
+ gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
+ { .fw_name = "xo" },
+- { .fw_name = "uniphy0_gcc_tx_clk" },
+- { .fw_name = "uniphy0_gcc_rx_clk" },
+- { .fw_name = "uniphy1_gcc_tx_clk" },
+- { .fw_name = "uniphy1_gcc_rx_clk" },
++ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
++ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
++ { .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
++ { .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
+ { .hw = &ubi32_pll.clkr.hw },
+- { .fw_name = "bias_pll_cc_clk" },
++ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
+ };
+
+ static const struct parent_map
+@@ -715,10 +715,10 @@ static const struct freq_tbl ftbl_nss_po
+
+ static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
+ { .fw_name = "xo" },
+- { .fw_name = "uniphy0_gcc_rx_clk" },
+- { .fw_name = "uniphy0_gcc_tx_clk" },
++ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
++ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
+ { .hw = &ubi32_pll.clkr.hw },
+- { .fw_name = "bias_pll_cc_clk" },
++ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
+ };
+
+ static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
+@@ -751,10 +751,10 @@ static const struct freq_tbl ftbl_nss_po
+
+ static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
+ { .fw_name = "xo" },
+- { .fw_name = "uniphy0_gcc_tx_clk" },
+- { .fw_name = "uniphy0_gcc_rx_clk" },
++ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
++ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
+ { .hw = &ubi32_pll.clkr.hw },
+- { .fw_name = "bias_pll_cc_clk" },
++ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
+ };
+
+ static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
+@@ -1898,12 +1898,11 @@ static const struct freq_tbl ftbl_ubi32_
+ { }
+ };
+
+-static const struct clk_parent_data
+- gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk[] = {
++static const struct clk_parent_data gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk[] = {
+ { .fw_name = "xo" },
+ { .hw = &gpll0.clkr.hw },
+ { .hw = &gpll2.clkr.hw },
+- { .fw_name = "bias_pll_nss_noc_clk" },
++ { .fw_name = "bias_pll_nss_noc_clk", .name = "bias_pll_nss_noc_clk" },
+ };
+
+ static const struct parent_map gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk_map[] = {
--- /dev/null
+From 505f9c8653fc218ca47a153ec58ebc16bef5502f Mon Sep 17 00:00:00 2001
+From: Mantas Pucka <mantas@8devices.com>
+Date: Tue, 16 Jan 2024 10:42:40 +0200
+Subject: [PATCH 16/19] remoteproc: q6v5_wcss: change ssr name for ipq6018 wifi
+ subsystem
+
+On IPQ6018 this string ends up being sent to RPM when remoteproc stops
+(on crash or rmmod ath11k). "q6wcss" is not a valid name (not found by
+`strings` in rpm.mbn), so this causes RPM do 'something' (presumably crash)
+causing a system reboot followed by hang in XBL, with no WDT running.
+Let's change ssr_name to a more sensible 'wcnss', that does not cause such
+issues.
+
+Signed-off-by: Mantas Pucka <mantas@8devices.com>
+---
+ drivers/remoteproc/qcom_q6v5_wcss.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+--- a/drivers/remoteproc/qcom_q6v5_wcss.c
++++ b/drivers/remoteproc/qcom_q6v5_wcss.c
+@@ -1143,8 +1143,8 @@ static int q6v5_wcss_probe(struct platfo
+ if (ret)
+ goto free_rproc;
+
+- qcom_add_glink_subdev(rproc, &wcss->glink_subdev, "q6wcss");
+- qcom_add_ssr_subdev(rproc, &wcss->ssr_subdev, "q6wcss");
++ qcom_add_glink_subdev(rproc, &wcss->glink_subdev, desc->ssr_name);
++ qcom_add_ssr_subdev(rproc, &wcss->ssr_subdev, desc->ssr_name);
+
+ if (desc->ssctl_id)
+ wcss->sysmon = qcom_add_sysmon_subdev(rproc,
+@@ -1201,7 +1201,7 @@ static const struct wcss_data wcss_ipq60
+ .aon_reset_required = true,
+ .wcss_q6_reset_required = true,
+ .bcr_reset_required = false,
+- .ssr_name = "q6wcss",
++ .ssr_name = "wcnss",
+ .ops = &q6v5_wcss_ipq8074_ops,
+ .requires_force_stop = true,
+ .need_mem_protection = true,
--- /dev/null
+From 153c74fc80b9f33ed1a50d7790bf6979fdceb370 Mon Sep 17 00:00:00 2001
+From: Mantas Pucka <mantas@8devices.com>
+Date: Tue, 16 Jan 2024 11:41:06 +0200
+Subject: [PATCH 19/19] arm64: dts: qcom: ipq6018: add wifi node
+
+IPQ6018 has a AHB based Q6v5 802.11ax radios that are supported
+by the ath11k.
+
+Add the required DT node to enable the built-in radios.
+
+Signed-off-by: Mantas Pucka <mantas@8devices.com>
+---
+ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 96 +++++++++++++++++++++++++++++++++++
+ 1 file changed, 96 insertions(+)
+
+--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+@@ -637,6 +637,102 @@
+ };
+ };
+
++ wifi: wifi@c000000 {
++ compatible = "qcom,ipq6018-wifi";
++ reg = <0x0 0xc000000 0x0 0x1000000>;
++ qcom,rproc = <&q6v5_wcss>;
++ interrupts = <GIC_SPI 320 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 319 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 317 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 316 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 310 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 302 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 301 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 294 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 293 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 290 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 288 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 239 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 235 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 234 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 233 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 232 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 231 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 230 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 224 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 223 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 180 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 160 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>,
++ <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
++ interrupt-names = "misc-pulse1", "misc-latch", "sw-exception",
++ "watchdog", "ce0", "ce1", "ce2", "ce3", "ce4",
++ "ce5", "ce6", "ce7", "ce8", "ce9", "ce10",
++ "ce11", "host2wbm-desc-feed",
++ "host2reo-re-injection", "host2reo-command",
++ "host2rxdma-monitor-ring3",
++ "host2rxdma-monitor-ring2",
++ "host2rxdma-monitor-ring1",
++ "reo2ost-exception", "wbm2host-rx-release",
++ "reo2host-status",
++ "reo2host-destination-ring4",
++ "reo2host-destination-ring3",
++ "reo2host-destination-ring2",
++ "reo2host-destination-ring1",
++ "rxdma2host-monitor-destination-mac3",
++ "rxdma2host-monitor-destination-mac2",
++ "rxdma2host-monitor-destination-mac1",
++ "ppdu-end-interrupts-mac3",
++ "ppdu-end-interrupts-mac2",
++ "ppdu-end-interrupts-mac1",
++ "rxdma2host-monitor-status-ring-mac3",
++ "rxdma2host-monitor-status-ring-mac2",
++ "rxdma2host-monitor-status-ring-mac1",
++ "host2rxdma-host-buf-ring-mac3",
++ "host2rxdma-host-buf-ring-mac2",
++ "host2rxdma-host-buf-ring-mac1",
++ "rxdma2host-destination-ring-mac3",
++ "rxdma2host-destination-ring-mac2",
++ "rxdma2host-destination-ring-mac1",
++ "host2tcl-input-ring4",
++ "host2tcl-input-ring3",
++ "host2tcl-input-ring2",
++ "host2tcl-input-ring1",
++ "wbm2host-tx-completions-ring3",
++ "wbm2host-tx-completions-ring2",
++ "wbm2host-tx-completions-ring1",
++ "tcl2host-status-ring";
++ status = "disabled";
++ };
++
+ q6v5_wcss: remoteproc@cd00000 {
+ compatible = "qcom,ipq6018-wcss-pil";
+ reg = <0x0 0x0cd00000 0x0 0x4040>,
--- /dev/null
+From d93936f175bd914067df8f63f5fbe6e3b77bb4d2 Mon Sep 17 00:00:00 2001
+From: Mantas Pucka <mantas@8devices.com>
+Date: Tue, 23 May 2023 14:46:28 +0300
+Subject: [PATCH 11/19] soc: qcom: fix smp2p ack on ipq6018
+
+IPQ6018 seem to need different ack mechanism for smp2p messaging. This
+fixes q6v5_wcss remoteproc firmware reloading. Without this first load
+is OK, but subsequent loads would hang and fail to complete.
+
+Signed-off-by: Mantas Pucka <mantas@8devices.com>
+---
+ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 1 +
+ drivers/soc/qcom/smp2p.c | 6 +++++-
+ 2 files changed, 6 insertions(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+@@ -1056,6 +1056,7 @@
+
+ wcss_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
++ qcom,smp2p-feature-ssr-ack;
+ #qcom,smem-state-cells = <1>;
+ };
+
+--- a/drivers/soc/qcom/smp2p.c
++++ b/drivers/soc/qcom/smp2p.c
+@@ -158,6 +158,8 @@ struct qcom_smp2p {
+
+ struct list_head inbound;
+ struct list_head outbound;
++
++ bool need_ssr_ack;
+ };
+
+ static void qcom_smp2p_kick(struct qcom_smp2p *smp2p)
+@@ -306,7 +308,7 @@ static irqreturn_t qcom_smp2p_intr(int i
+ ack_restart = qcom_smp2p_check_ssr(smp2p);
+ qcom_smp2p_notify_in(smp2p);
+
+- if (ack_restart)
++ if (ack_restart || smp2p->need_ssr_ack)
+ qcom_smp2p_do_ssr_ack(smp2p);
+ }
+
+@@ -427,6 +429,7 @@ static int qcom_smp2p_outbound_entry(str
+
+ /* Make the logical entry reference the physical value */
+ entry->value = &out->entries[out->valid_entries].value;
++ smp2p->need_ssr_ack = of_property_read_bool(node, "qcom,smp2p-feature-ssr-ack");
+
+ out->valid_entries++;
+
--- /dev/null
+From 87dbcc69a7e3fe6ccddf4fe9bdbf51330f5e4a77 Mon Sep 17 00:00:00 2001
+From: Mantas Pucka <mantas@8devices.com>
+Date: Tue, 23 Jan 2024 11:04:04 +0200
+Subject: [PATCH] remoteproc: qcom_q6v5_wcss: add optional qdss_at clock
+
+IPQ6018 needs QDSS_AT clock enabled when loading wifi. Optionally enable it
+when provided by DT.
+
+Signed-off-by: Mantas Pucka <mantas@8devices.com>
+---
+ drivers/remoteproc/qcom_q6v5_wcss.c | 24 ++++++++++++++++++++++++
+ 1 file changed, 24 insertions(+)
+
+--- a/drivers/remoteproc/qcom_q6v5_wcss.c
++++ b/drivers/remoteproc/qcom_q6v5_wcss.c
+@@ -120,6 +120,7 @@ struct q6v5_wcss {
+ struct clk *qdsp6ss_core_gfmux;
+ struct clk *lcc_bcr_sleep;
+ struct clk *prng_clk;
++ struct clk *qdss_clk;
+ struct regulator *cx_supply;
+ struct qcom_sysmon *sysmon;
+
+@@ -259,6 +260,9 @@ static int q6v5_wcss_start(struct rproc
+ return ret;
+ }
+
++ if (wcss->qdss_clk)
++ clk_prepare_enable(wcss->qdss_clk);
++
+ qcom_q6v5_prepare(&wcss->q6v5);
+
+ if (wcss->need_mem_protection) {
+@@ -772,6 +776,8 @@ static int q6v5_wcss_stop(struct rproc *
+ }
+
+ pas_done:
++ if (wcss->qdss_clk)
++ clk_disable_unprepare(wcss->qdss_clk);
+ clk_disable_unprepare(wcss->prng_clk);
+ qcom_q6v5_unprepare(&wcss->q6v5);
+
+@@ -981,6 +987,12 @@ static int ipq_init_clock(struct q6v5_wc
+ dev_err(wcss->dev, "Failed to get prng clock\n");
+ return ret;
+ }
++
++ wcss->qdss_clk = devm_clk_get(wcss->dev, "qdss");
++ if (IS_ERR(wcss->qdss_clk)) {
++ wcss->qdss_clk = NULL;
++ }
++
+ return 0;
+ }
+
--- /dev/null
+From 71f30e25d21ae4981ecef6653a4ba7dfeb80db7b Mon Sep 17 00:00:00 2001
+From: Mantas Pucka <mantas@8devices.com>
+Date: Tue, 23 Jan 2024 11:04:57 +0200
+Subject: [PATCH] arm64: dts: qcom: ipq6018: assign QDSS_AT clock to wifi remoteproc
+
+IPQ6018 needs to enable QDSS_AT clock when loading wifi firmware,
+add it to wifi remoteproc clock list.
+
+Signed-off-by: Mantas Pucka <mantas@8devices.com>
+---
+ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 15 ++++++++-------
+ 1 file changed, 9 insertions(+), 8 deletions(-)
+
+--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+@@ -758,8 +758,8 @@
+ "wcss_reset",
+ "wcss_q6_reset";
+
+- clocks = <&gcc GCC_PRNG_AHB_CLK>;
+- clock-names = "prng";
++ clocks = <&gcc GCC_PRNG_AHB_CLK>, <&gcc GCC_QDSS_AT_CLK>;
++ clock-names = "prng", "qdss" ;
+
+ qcom,halt-regs = <&tcsr 0x18000 0x1b000 0xe000>;
+
--- /dev/null
+From c67a1814bb1d0df290cf1e3f9c966f04aa41b9b9 Mon Sep 17 00:00:00 2001
+From: Mantas Pucka <mantas@8devices.com>
+Date: Tue, 30 Jan 2024 12:43:56 +0200
+Subject: [PATCH] arm64: dts: qcom: ipq6018: change voltage to perf levels for
+ CPR4 driver
+
+Current CPR4 driver requires opp-microvolt to be an abstract
+performance level instead of actual voltage level.
+
+Signed-off-by: Mantas Pucka <mantas@8devices.com>
+---
+ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+@@ -99,42 +99,42 @@
+
+ opp-864000000 {
+ opp-hz = /bits/ 64 <864000000>;
+- opp-microvolt = <725000>;
++ opp-microvolt = <1>;
+ opp-supported-hw = <0xf>;
+ clock-latency-ns = <200000>;
+ };
+
+ opp-1056000000 {
+ opp-hz = /bits/ 64 <1056000000>;
+- opp-microvolt = <787500>;
++ opp-microvolt = <2>;
+ opp-supported-hw = <0xf>;
+ clock-latency-ns = <200000>;
+ };
+
+ opp-1320000000 {
+ opp-hz = /bits/ 64 <1320000000>;
+- opp-microvolt = <862500>;
++ opp-microvolt = <3>;
+ opp-supported-hw = <0x3>;
+ clock-latency-ns = <200000>;
+ };
+
+ opp-1440000000 {
+ opp-hz = /bits/ 64 <1440000000>;
+- opp-microvolt = <925000>;
++ opp-microvolt = <4>;
+ opp-supported-hw = <0x3>;
+ clock-latency-ns = <200000>;
+ };
+
+ opp-1608000000 {
+ opp-hz = /bits/ 64 <1608000000>;
+- opp-microvolt = <987500>;
++ opp-microvolt = <5>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <200000>;
+ };
+
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+- opp-microvolt = <1062500>;
++ opp-microvolt = <6>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <200000>;
+ };
projects / openwrt / staging / jow.git / commitdiff