target/linux/qualcommax/files/arch/arm64/boot/dts/qcom/ipq6018-ess.dtsi

   1 #include <dt-bindings/net/qcom-ipq-ess.h>
   2
   3 &soc {
   4         bias_pll_cc_clk: bias-pll-cc-clk {
   5                 compatible = "fixed-clock";
   6                 clock-frequency = <300000000>;
   7                 clock-output-names = "bias_pll_cc_clk";
   8                 #clock-cells = <0>;
   9         };
  10
  11         bias_pll_nss_noc_clk: bias-pll-nss-noc-clk {
  12                 compatible = "fixed-clock";
  13                 clock-frequency = <416500000>;
  14                 clock-output-names = "bias_pll_nss_noc_clk";
  15                 #clock-cells = <0>;
  16         };
  17
  18         edma: edma@3ab00000 {
  19                 compatible = "qcom,edma";
  20                 reg = <0x0 0x3ab00000 0x0 0xabe00>;
  21                 reg-names = "edma-reg-base";
  22                 qcom,txdesc-ring-start = <23>;
  23                 qcom,txdesc-rings = <1>;
  24                 qcom,txcmpl-ring-start = <23>;
  25                 qcom,txcmpl-rings = <1>;
  26                 qcom,rxfill-ring-start = <7>;
  27                 qcom,rxfill-rings = <1>;
  28                 qcom,rxdesc-ring-start = <15>;
  29                 qcom,rxdesc-rings = <1>;
  30                 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
  31                              <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
  32                              <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
  33                              <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
  34                 resets = <&gcc GCC_EDMA_HW_RESET>;
  35                 reset-names = "edma_rst";
  36                 status = "disabled";
  37         };
  38
  39         ess_instance: ess-instance {
  40                 #address-cells = <1>;
  41                 #size-cells = <1>;
  42                 num_devices = <1>;
  43
  44                 switch: ess-switch@3a000000 {
  45                         compatible = "qcom,ess-switch-ipq60xx";
  46                         reg = <0x3a000000 0x1000000>;
  47                         switch_access_mode = "local bus";
  48                         clocks = <&gcc GCC_CMN_12GPLL_AHB_CLK>,
  49                                  <&gcc GCC_CMN_12GPLL_SYS_CLK>,
  50                                  <&gcc GCC_UNIPHY0_AHB_CLK>,
  51                                  <&gcc GCC_UNIPHY0_SYS_CLK>,
  52                                  <&gcc GCC_UNIPHY1_AHB_CLK>,
  53                                  <&gcc GCC_UNIPHY1_SYS_CLK>,
  54                                  <&gcc GCC_PORT1_MAC_CLK>,
  55                                  <&gcc GCC_PORT2_MAC_CLK>,
  56                                  <&gcc GCC_PORT3_MAC_CLK>,
  57                                  <&gcc GCC_PORT4_MAC_CLK>,
  58                                  <&gcc GCC_PORT5_MAC_CLK>,
  59                                  <&gcc GCC_NSS_PPE_CLK>,
  60                                  <&gcc GCC_NSS_PPE_CFG_CLK>,
  61                                  <&gcc GCC_NSSNOC_PPE_CLK>,
  62                                  <&gcc GCC_NSSNOC_PPE_CFG_CLK>,
  63                                  <&gcc GCC_NSS_EDMA_CLK>,
  64                                  <&gcc GCC_NSS_EDMA_CFG_CLK>,
  65                                  <&gcc GCC_NSS_PPE_IPE_CLK>,
  66                                  <&gcc GCC_MDIO_AHB_CLK>,
  67                                  <&gcc GCC_NSS_NOC_CLK>,
  68                                  <&gcc GCC_NSSNOC_SNOC_CLK>,
  69                                  <&gcc GCC_NSS_CRYPTO_CLK>,
  70                                  <&gcc GCC_NSS_PTP_REF_CLK>,
  71                                  <&gcc GCC_NSS_PORT1_RX_CLK>,
  72                                  <&gcc GCC_NSS_PORT1_TX_CLK>,
  73                                  <&gcc GCC_NSS_PORT2_RX_CLK>,
  74                                  <&gcc GCC_NSS_PORT2_TX_CLK>,
  75                                  <&gcc GCC_NSS_PORT3_RX_CLK>,
  76                                  <&gcc GCC_NSS_PORT3_TX_CLK>,
  77                                  <&gcc GCC_NSS_PORT4_RX_CLK>,
  78                                  <&gcc GCC_NSS_PORT4_TX_CLK>,
  79                                  <&gcc GCC_NSS_PORT5_RX_CLK>,
  80                                  <&gcc GCC_NSS_PORT5_TX_CLK>,
  81                                  <&gcc GCC_UNIPHY0_PORT1_RX_CLK>,
  82                                  <&gcc GCC_UNIPHY0_PORT1_TX_CLK>,
  83                                  <&gcc GCC_UNIPHY0_PORT2_RX_CLK>,
  84                                  <&gcc GCC_UNIPHY0_PORT2_TX_CLK>,
  85                                  <&gcc GCC_UNIPHY0_PORT3_RX_CLK>,
  86                                  <&gcc GCC_UNIPHY0_PORT3_TX_CLK>,
  87                                  <&gcc GCC_UNIPHY0_PORT4_RX_CLK>,
  88                                  <&gcc GCC_UNIPHY0_PORT4_TX_CLK>,
  89                                  <&gcc GCC_UNIPHY0_PORT5_RX_CLK>,
  90                                  <&gcc GCC_UNIPHY0_PORT5_TX_CLK>,
  91                                  <&gcc GCC_UNIPHY1_PORT5_RX_CLK>,
  92                                  <&gcc GCC_UNIPHY1_PORT5_TX_CLK>,
  93                                  <&gcc NSS_PORT5_RX_CLK_SRC>,
  94                                  <&gcc NSS_PORT5_TX_CLK_SRC>,
  95                                  <&gcc GCC_SNOC_NSSNOC_CLK>;
  96                         clock-names = "cmn_ahb_clk", "cmn_sys_clk",
  97                                         "uniphy0_ahb_clk", "uniphy0_sys_clk",
  98                                         "uniphy1_ahb_clk", "uniphy1_sys_clk",
  99                                         "port1_mac_clk", "port2_mac_clk",
 100                                         "port3_mac_clk", "port4_mac_clk",
 101                                         "port5_mac_clk",
 102                                         "nss_ppe_clk", "nss_ppe_cfg_clk",
 103                                         "nssnoc_ppe_clk", "nssnoc_ppe_cfg_clk",
 104                                         "nss_edma_clk", "nss_edma_cfg_clk",
 105                                         "nss_ppe_ipe_clk",
 106                                         "gcc_mdio_ahb_clk", "gcc_nss_noc_clk",
 107                                         "gcc_nssnoc_snoc_clk",
 108                                         "gcc_nss_crypto_clk",
 109                                         "gcc_nss_ptp_ref_clk",
 110                                         "nss_port1_rx_clk", "nss_port1_tx_clk",
 111                                         "nss_port2_rx_clk", "nss_port2_tx_clk",
 112                                         "nss_port3_rx_clk", "nss_port3_tx_clk",
 113                                         "nss_port4_rx_clk", "nss_port4_tx_clk",
 114                                         "nss_port5_rx_clk", "nss_port5_tx_clk",
 115                                         "uniphy0_port1_rx_clk",
 116                                         "uniphy0_port1_tx_clk",
 117                                         "uniphy0_port2_rx_clk",
 118                                         "uniphy0_port2_tx_clk",
 119                                         "uniphy0_port3_rx_clk",
 120                                         "uniphy0_port3_tx_clk",
 121                                         "uniphy0_port4_rx_clk",
 122                                         "uniphy0_port4_tx_clk",
 123                                         "uniphy0_port5_rx_clk",
 124                                         "uniphy0_port5_tx_clk",
 125                                         "uniphy1_port5_rx_clk",
 126                                         "uniphy1_port5_tx_clk",
 127                                         "nss_port5_rx_clk_src",
 128                                         "nss_port5_tx_clk_src",
 129                                         "gcc_snoc_nssnoc_clk";
 130                         resets = <&gcc GCC_PPE_FULL_RESET>,
 131                                  <&gcc GCC_UNIPHY0_SOFT_RESET>,
 132                                  <&gcc GCC_UNIPHY0_XPCS_RESET>,
 133                                  <&gcc GCC_UNIPHY1_SOFT_RESET>,
 134                                  <&gcc GCC_UNIPHY1_XPCS_RESET>,
 135                                  <&gcc GCC_NSSPORT1_RESET>,
 136                                  <&gcc GCC_NSSPORT2_RESET>,
 137                                  <&gcc GCC_NSSPORT3_RESET>,
 138                                  <&gcc GCC_NSSPORT4_RESET>,
 139                                  <&gcc GCC_NSSPORT5_RESET>,
 140                                  <&gcc GCC_UNIPHY0_PORT1_ARES>,
 141                                  <&gcc GCC_UNIPHY0_PORT2_ARES>,
 142                                  <&gcc GCC_UNIPHY0_PORT3_ARES>,
 143                                  <&gcc GCC_UNIPHY0_PORT4_ARES>,
 144                                  <&gcc GCC_UNIPHY0_PORT5_ARES>,
 145                                  <&gcc GCC_UNIPHY0_PORT_4_5_RESET>,
 146                                  <&gcc GCC_UNIPHY0_PORT_4_RESET>;
 147                         reset-names = "ppe_rst", "uniphy0_soft_rst",
 148                                         "uniphy0_xpcs_rst", "uniphy1_soft_rst",
 149                                         "uniphy1_xpcs_rst", "nss_port1_rst",
 150                                         "nss_port2_rst", "nss_port3_rst",
 151                                         "nss_port4_rst", "nss_port5_rst",
 152                                         "uniphy0_port1_dis",
 153                                         "uniphy0_port2_dis",
 154                                         "uniphy0_port3_dis",
 155                                         "uniphy0_port4_dis",
 156                                         "uniphy0_port5_dis",
 157                                         "uniphy0_port_4_5_rst",
 158                                         "uniphy0_port_4_rst";
 159                         mdio-bus = <&mdio>;
 160
 161                         switch_cpu_bmp = <ESS_PORT0>;  /* cpu port bitmap */
 162                         switch_inner_bmp = <(ESS_PORT6 | ESS_PORT7)>; /*inner port bitmap*/
 163                         switch_mac_mode = <MAC_MODE_DISABLED>; /* MAC mode for UNIPHY instance 0 */
 164                         switch_mac_mode1 = <MAC_MODE_DISABLED>; /* MAC mode for UNIPHY instance 1 */
 165                         switch_mac_mode2 = <MAC_MODE_DISABLED>; /* MAC mode for UNIPHY instance 2 */
 166
 167                         status = "disabled";
 168
 169                         bm_tick_mode = <0>; /* bm tick mode */
 170                         tm_tick_mode = <0>; /* tm tick mode */
 171
 172                         port_scheduler_resource {
 173                                 port@0 {
 174                                         port_id = <0>;
 175                                         ucast_queue = <0 143>;
 176                                         mcast_queue = <256 271>;
 177                                         l0sp = <0 35>;
 178                                         l0cdrr = <0 47>;
 179                                         l0edrr = <0 47>;
 180                                         l1cdrr = <0 7>;
 181                                         l1edrr = <0 7>;
 182                                 };
 183                                 port@1 {
 184                                         port_id = <1>;
 185                                         ucast_queue = <144 159>;
 186                                         mcast_queue = <272 275>;
 187                                         l0sp = <36 39>;
 188                                         l0cdrr = <48 63>;
 189                                         l0edrr = <48 63>;
 190                                         l1cdrr = <8 11>;
 191                                         l1edrr = <8 11>;
 192                                 };
 193                                 port@2 {
 194                                         port_id = <2>;
 195                                         ucast_queue = <160 175>;
 196                                         mcast_queue = <276 279>;
 197                                         l0sp = <40 43>;
 198                                         l0cdrr = <64 79>;
 199                                         l0edrr = <64 79>;
 200                                         l1cdrr = <12 15>;
 201                                         l1edrr = <12 15>;
 202                                 };
 203                                 port@3 {
 204                                         port_id = <3>;
 205                                         ucast_queue = <176 191>;
 206                                         mcast_queue = <280 283>;
 207                                         l0sp = <44 47>;
 208                                         l0cdrr = <80 95>;
 209                                         l0edrr = <80 95>;
 210                                         l1cdrr = <16 19>;
 211                                         l1edrr = <16 19>;
 212                                 };
 213                                 port@4 {
 214                                         port_id = <4>;
 215                                         ucast_queue = <192 207>;
 216                                         mcast_queue = <284 287>;
 217                                         l0sp = <48 51>;
 218                                         l0cdrr = <96 111>;
 219                                         l0edrr = <96 111>;
 220                                         l1cdrr = <20 23>;
 221                                         l1edrr = <20 23>;
 222                                 };
 223                                 port@5 {
 224                                         port_id = <5>;
 225                                         ucast_queue = <208 223>;
 226                                         mcast_queue = <288 291>;
 227                                         l0sp = <52 55>;
 228                                         l0cdrr = <112 127>;
 229                                         l0edrr = <112 127>;
 230                                         l1cdrr = <24 27>;
 231                                         l1edrr = <24 27>;
 232                                 };
 233                                 port@6 {
 234                                         port_id = <6>;
 235                                         ucast_queue = <224 239>;
 236                                         mcast_queue = <292 295>;
 237                                         l0sp = <56 59>;
 238                                         l0cdrr = <128 143>;
 239                                         l0edrr = <128 143>;
 240                                         l1cdrr = <28 31>;
 241                                         l1edrr = <28 31>;
 242                                 };
 243                                 port@7 {
 244                                         port_id = <7>;
 245                                         ucast_queue = <240 255>;
 246                                         mcast_queue = <296 299>;
 247                                         l0sp = <60 63>;
 248                                         l0cdrr = <144 159>;
 249                                         l0edrr = <144 159>;
 250                                         l1cdrr = <32 35>;
 251                                         l1edrr = <32 35>;
 252                                 };
 253                         };
 254                         port_scheduler_config {
 255                                 port@0 {
 256                                         port_id = <0>;
 257                                         l1scheduler {
 258                                                 group@0 {
 259                                                         sp = <0 1>; /*L0 SPs*/
 260                                                         /*cpri cdrr epri edrr*/
 261                                                         cfg = <0 0 0 0>;
 262                                                 };
 263                                         };
 264                                         l0scheduler {
 265                                                 group@0 {
 266                                                         /*unicast queues*/
 267                                                         ucast_queue = <0 4 8>;
 268                                                         /*multicast queues*/
 269                                                         mcast_queue = <256 260>;
 270                                                         /*sp cpricdrrepriedrr*/
 271                                                         cfg = <0 0 0 0 0>;
 272                                                 };
 273                                                 group@1 {
 274                                                         ucast_queue = <1 5 9>;
 275                                                         mcast_queue = <257 261>;
 276                                                         cfg = <0 1 1 1 1>;
 277                                                 };
 278                                                 group@2 {
 279                                                         ucast_queue = <2 6 10>;
 280                                                         mcast_queue = <258 262>;
 281                                                         cfg = <0 2 2 2 2>;
 282                                                 };
 283                                                 group@3 {
 284                                                         ucast_queue = <3 7 11>;
 285                                                         mcast_queue = <259 263>;
 286                                                         cfg = <0 3 3 3 3>;
 287                                                 };
 288                                         };
 289                                 };
 290                                 port@1 {
 291                                         port_id = <1>;
 292                                         l1scheduler {
 293                                                 group@0 {
 294                                                         sp = <36>;
 295                                                         cfg = <0 8 0 8>;
 296                                                 };
 297                                                 group@1 {
 298                                                         sp = <37>;
 299                                                         cfg = <1 9 1 9>;
 300                                                 };
 301                                         };
 302                                         l0scheduler {
 303                                                 group@0 {
 304                                                         ucast_queue = <144>;
 305                                                         ucast_loop_pri = <16>;
 306                                                         mcast_queue = <272>;
 307                                                         mcast_loop_pri = <4>;
 308                                                         cfg = <36 0 48 0 48>;
 309                                                 };
 310                                         };
 311                                 };
 312                                 port@2 {
 313                                         port_id = <2>;
 314                                         l1scheduler {
 315                                                 group@0 {
 316                                                         sp = <40>;
 317                                                         cfg = <0 12 0 12>;
 318                                                 };
 319                                                 group@1 {
 320                                                         sp = <41>;
 321                                                         cfg = <1 13 1 13>;
 322                                                 };
 323                                         };
 324                                         l0scheduler {
 325                                                 group@0 {
 326                                                         ucast_queue = <160>;
 327                                                         ucast_loop_pri = <16>;
 328                                                         mcast_queue = <276>;
 329                                                         mcast_loop_pri = <4>;
 330                                                         cfg = <40 0 64 0 64>;
 331                                                 };
 332                                         };
 333                                 };
 334                                 port@3 {
 335                                         port_id = <3>;
 336                                         l1scheduler {
 337                                                 group@0 {
 338                                                         sp = <44>;
 339                                                         cfg = <0 16 0 16>;
 340                                                 };
 341                                                 group@1 {
 342                                                         sp = <45>;
 343                                                         cfg = <1 17 1 17>;
 344                                                 };
 345                                         };
 346                                         l0scheduler {
 347                                                 group@0 {
 348                                                         ucast_queue = <176>;
 349                                                         ucast_loop_pri = <16>;
 350                                                         mcast_queue = <280>;
 351                                                         mcast_loop_pri = <4>;
 352                                                         cfg = <44 0 80 0 80>;
 353                                                 };
 354                                         };
 355                                 };
 356                                 port@4 {
 357                                         port_id = <4>;
 358                                         l1scheduler {
 359                                                 group@0 {
 360                                                         sp = <48>;
 361                                                         cfg = <0 20 0 20>;
 362                                                 };
 363                                                 group@1 {
 364                                                         sp = <49>;
 365                                                         cfg = <1 21 1 21>;
 366                                                 };
 367                                         };
 368                                         l0scheduler {
 369                                                 group@0 {
 370                                                         ucast_queue = <192>;
 371                                                         ucast_loop_pri = <16>;
 372                                                         mcast_queue = <284>;
 373                                                         mcast_loop_pri = <4>;
 374                                                         cfg = <48 0 96 0 96>;
 375                                                 };
 376                                         };
 377                                 };
 378                                 port@5 {
 379                                         port_id = <5>;
 380                                         l1scheduler {
 381                                                 group@0 {
 382                                                         sp = <52>;
 383                                                         cfg = <0 24 0 24>;
 384                                                 };
 385                                                 group@1 {
 386                                                         sp = <53>;
 387                                                         cfg = <1 25 1 25>;
 388                                                 };
 389                                         };
 390                                         l0scheduler {
 391                                                 group@0 {
 392                                                         ucast_queue = <208>;
 393                                                         ucast_loop_pri = <16>;
 394                                                         mcast_queue = <288>;
 395                                                         mcast_loop_pri = <4>;
 396                                                         cfg = <52 0 112 0 112>;
 397                                                 };
 398                                         };
 399                                 };
 400                                 port@6 {
 401                                         port_id = <6>;
 402                                         l1scheduler {
 403                                                 group@0 {
 404                                                         sp = <56>;
 405                                                         cfg = <0 28 0 28>;
 406                                                 };
 407                                                 group@1 {
 408                                                         sp = <57>;
 409                                                         cfg = <1 29 1 29>;
 410                                                 };
 411                                         };
 412                                         l0scheduler {
 413                                                 group@0 {
 414                                                         ucast_queue = <224>;
 415                                                         ucast_loop_pri = <16>;
 416                                                         mcast_queue = <292>;
 417                                                         mcast_loop_pri = <4>;
 418                                                         cfg = <56 0 128 0 128>;
 419                                                 };
 420                                         };
 421                                 };
 422                                 port@7 {
 423                                         port_id = <7>;
 424                                         l1scheduler {
 425                                                 group@0 {
 426                                                         sp = <60>;
 427                                                         cfg = <0 32 0 32>;
 428                                                 };
 429                                                 group@1 {
 430                                                         sp = <61>;
 431                                                         cfg = <1 33 1 33>;
 432                                                 };
 433                                         };
 434                                         l0scheduler {
 435                                                 group@0 {
 436                                                         ucast_queue = <240>;
 437                                                         ucast_loop_pri = <16>;
 438                                                         mcast_queue = <296>;
 439                                                         cfg = <60 0 144 0 144>;
 440                                                 };
 441                                         };
 442                                 };
 443                         };
 444                 };
 445
 446                 ess-uniphy@7a00000 {
 447                         compatible = "qcom,ess-uniphy";
 448                         reg = <0x7a00000 0x30000>;
 449                         uniphy_access_mode = "local bus";
 450                 };
 451         };
 452
 453         dp1: dp1 {
 454                 device_type = "network";
 455                 compatible = "qcom,nss-dp";
 456                 qcom,id = <1>;
 457                 reg = <0x0 0x3a001000 0x0 0x200>;
 458                 qcom,mactype = <0>;
 459                 local-mac-address = [000000000000];
 460                 phy-mode = "sgmii";
 461                 status = "disabled";
 462         };
 463
 464         dp2: dp2 {
 465                 device_type = "network";
 466                 compatible = "qcom,nss-dp";
 467                 qcom,id = <2>;
 468                 reg = <0x0 0x3a001200 0x0 0x200>;
 469                 qcom,mactype = <0>;
 470                 local-mac-address = [000000000000];
 471                 phy-mode = "sgmii";
 472                 status = "disabled";
 473         };
 474
 475         dp3: dp3 {
 476                 device_type = "network";
 477                 compatible = "qcom,nss-dp";
 478                 qcom,id = <3>;
 479                 reg = <0x0 0x3a001400 0x0 0x200>;
 480                 qcom,mactype = <0>;
 481                 local-mac-address = [000000000000];
 482                 phy-mode = "sgmii";
 483                 status = "disabled";
 484         };
 485
 486         dp4: dp4 {
 487                 device_type = "network";
 488                 compatible = "qcom,nss-dp";
 489                 qcom,id = <4>;
 490                 reg = <0x0 0x3a001600 0x0 0x200>;
 491                 qcom,mactype = <0>;
 492                 local-mac-address = [000000000000];
 493                 phy-mode = "sgmii";
 494                 status = "disabled";
 495         };
 496
 497         dp5: dp5 {
 498                 device_type = "network";
 499                 compatible = "qcom,nss-dp";
 500                 qcom,id = <5>;
 501                 reg = <0x0 0x3a001800 0x0 0x200>;
 502                 qcom,mactype = <0>;
 503                 local-mac-address = [000000000000];
 504                 phy-mode = "sgmii";
 505                 status = "disabled";
 506         };
 507 };