kernel/ipq806x: Create kernel files for v6.6 (from v6.1)
authorChristian Marangi <ansuelsmth@gmail.com>
Wed, 20 Mar 2024 00:21:38 +0000 (01:21 +0100)
committerChristian Marangi <ansuelsmth@gmail.com>
Tue, 2 Apr 2024 21:45:59 +0000 (23:45 +0200)
This is an automatically generated commit.

When doing `git bisect`, consider `git bisect --skip`.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
66 files changed:
target/linux/ipq806x/config-6.1 [deleted file]
target/linux/ipq806x/config-6.6 [new file with mode: 0644]
target/linux/ipq806x/patches-6.1/001-v6.2-clk-qcom-kpss-xcc-register-it-as-clk-provider.patch [deleted file]
target/linux/ipq806x/patches-6.1/002-v6.2-01-clk-qcom-krait-cc-use-devm-variant-for-clk-notifier-.patch [deleted file]
target/linux/ipq806x/patches-6.1/002-v6.2-02-clk-qcom-krait-cc-fix-wrong-parent-order-for-seconda.patch [deleted file]
target/linux/ipq806x/patches-6.1/002-v6.2-03-clk-qcom-krait-cc-also-enable-secondary-mux-and-div-.patch [deleted file]
target/linux/ipq806x/patches-6.1/002-v6.2-04-clk-qcom-krait-cc-handle-secondary-mux-sourcing-out-.patch [deleted file]
target/linux/ipq806x/patches-6.1/002-v6.2-05-clk-qcom-krait-cc-convert-to-devm_clk_hw_register.patch [deleted file]
target/linux/ipq806x/patches-6.1/002-v6.2-06-clk-qcom-krait-cc-convert-to-parent_data-API.patch [deleted file]
target/linux/ipq806x/patches-6.1/003-v6.2-ARM-dts-qcom-ipq8064-disable-mmc-ddr-1_8v-for-sdcc1.patch [deleted file]
target/linux/ipq806x/patches-6.1/004-v6.2-01-thermal-drivers-qcom-tsens-Init-debugfs-only-with-su.patch [deleted file]
target/linux/ipq806x/patches-6.1/004-v6.2-02-thermal-drivers-qcom-tsens-Fix-wrong-version-id-dbg_.patch [deleted file]
target/linux/ipq806x/patches-6.1/004-v6.2-03-thermal-drivers-qcom-tsens-Rework-debugfs-file-struc.patch [deleted file]
target/linux/ipq806x/patches-6.1/102-mtd-rootfs-conflicts-with-OpenWrt-auto-mounting.patch [deleted file]
target/linux/ipq806x/patches-6.1/107-10-ARM-dts-qcom-add-saw-for-l2-cache-and-kraitcc-for.patch [deleted file]
target/linux/ipq806x/patches-6.1/107-13-ARM-dts-qcom-add-opp-table-for-cpu-and-l2-for-ipq.patch [deleted file]
target/linux/ipq806x/patches-6.1/107-15-ARM-dts-qcom-add-multiple-missing-binding-for-cpu.patch [deleted file]
target/linux/ipq806x/patches-6.1/108-01-ARM-dts-qcom-fix-wrong-nad_pins-definition-for-ipq80.patch [deleted file]
target/linux/ipq806x/patches-6.1/108-02-ARM-dts-qcom-add-MDIO-dedicated-controller-node-for-.patch [deleted file]
target/linux/ipq806x/patches-6.1/114-01-devfreq-qcom-Add-L2-Krait-Cache-devfreq-scaling-driv.patch [deleted file]
target/linux/ipq806x/patches-6.1/114-02-ARM-dts-qcom-add-krait-cache-compatible-for-ipq806x-.patch [deleted file]
target/linux/ipq806x/patches-6.1/115-01-devfreq-add-ipq806x-fabric-scaling-driver.patch [deleted file]
target/linux/ipq806x/patches-6.1/115-02-ARM-dts-qcom-add-fab-scaling-node-for-ipq806x.patch [deleted file]
target/linux/ipq806x/patches-6.1/122-01-clk-qcom-krait-cc-handle-qsb-clock-defined-in-DTS.patch [deleted file]
target/linux/ipq806x/patches-6.1/122-02-clk-qcom-krait-cc-register-REAL-qsb-fixed-clock.patch [deleted file]
target/linux/ipq806x/patches-6.1/122-03-clk-qcom-krait-cc-drop-pr_info-and-use-dev_info.patch [deleted file]
target/linux/ipq806x/patches-6.1/122-04-clk-qcom-krait-cc-rework-mux-reset-logic-and-reset-h.patch [deleted file]
target/linux/ipq806x/patches-6.1/122-05-clk-qcom-clk-krait-generilize-div-functions.patch [deleted file]
target/linux/ipq806x/patches-6.1/123-clk-qcom-gcc-ipq806x-remove-cc_register_board-for.patch [deleted file]
target/linux/ipq806x/patches-6.1/850-soc-add-qualcomm-syscon.patch [deleted file]
target/linux/ipq806x/patches-6.1/900-arm-add-cmdline-override.patch [deleted file]
target/linux/ipq806x/patches-6.1/901-01-ARM-decompressor-support-memory-start-validation-.patch [deleted file]
target/linux/ipq806x/patches-6.1/901-02-ARM-decompressor-add-option-to-ignore-MEM-ATAGs.patch [deleted file]
target/linux/ipq806x/patches-6.1/902-ARM-decompressor-support-for-ATAGs-rootblock-parsing.patch [deleted file]
target/linux/ipq806x/patches-6.6/001-v6.2-clk-qcom-kpss-xcc-register-it-as-clk-provider.patch [new file with mode: 0644]
target/linux/ipq806x/patches-6.6/002-v6.2-01-clk-qcom-krait-cc-use-devm-variant-for-clk-notifier-.patch [new file with mode: 0644]
target/linux/ipq806x/patches-6.6/002-v6.2-02-clk-qcom-krait-cc-fix-wrong-parent-order-for-seconda.patch [new file with mode: 0644]
target/linux/ipq806x/patches-6.6/002-v6.2-03-clk-qcom-krait-cc-also-enable-secondary-mux-and-div-.patch [new file with mode: 0644]
target/linux/ipq806x/patches-6.6/002-v6.2-04-clk-qcom-krait-cc-handle-secondary-mux-sourcing-out-.patch [new file with mode: 0644]
target/linux/ipq806x/patches-6.6/002-v6.2-05-clk-qcom-krait-cc-convert-to-devm_clk_hw_register.patch [new file with mode: 0644]
target/linux/ipq806x/patches-6.6/002-v6.2-06-clk-qcom-krait-cc-convert-to-parent_data-API.patch [new file with mode: 0644]
target/linux/ipq806x/patches-6.6/003-v6.2-ARM-dts-qcom-ipq8064-disable-mmc-ddr-1_8v-for-sdcc1.patch [new file with mode: 0644]
target/linux/ipq806x/patches-6.6/004-v6.2-01-thermal-drivers-qcom-tsens-Init-debugfs-only-with-su.patch [new file with mode: 0644]
target/linux/ipq806x/patches-6.6/004-v6.2-02-thermal-drivers-qcom-tsens-Fix-wrong-version-id-dbg_.patch [new file with mode: 0644]
target/linux/ipq806x/patches-6.6/004-v6.2-03-thermal-drivers-qcom-tsens-Rework-debugfs-file-struc.patch [new file with mode: 0644]
target/linux/ipq806x/patches-6.6/102-mtd-rootfs-conflicts-with-OpenWrt-auto-mounting.patch [new file with mode: 0644]
target/linux/ipq806x/patches-6.6/107-10-ARM-dts-qcom-add-saw-for-l2-cache-and-kraitcc-for.patch [new file with mode: 0644]
target/linux/ipq806x/patches-6.6/107-13-ARM-dts-qcom-add-opp-table-for-cpu-and-l2-for-ipq.patch [new file with mode: 0644]
target/linux/ipq806x/patches-6.6/107-15-ARM-dts-qcom-add-multiple-missing-binding-for-cpu.patch [new file with mode: 0644]
target/linux/ipq806x/patches-6.6/108-01-ARM-dts-qcom-fix-wrong-nad_pins-definition-for-ipq80.patch [new file with mode: 0644]
target/linux/ipq806x/patches-6.6/108-02-ARM-dts-qcom-add-MDIO-dedicated-controller-node-for-.patch [new file with mode: 0644]
target/linux/ipq806x/patches-6.6/114-01-devfreq-qcom-Add-L2-Krait-Cache-devfreq-scaling-driv.patch [new file with mode: 0644]
target/linux/ipq806x/patches-6.6/114-02-ARM-dts-qcom-add-krait-cache-compatible-for-ipq806x-.patch [new file with mode: 0644]
target/linux/ipq806x/patches-6.6/115-01-devfreq-add-ipq806x-fabric-scaling-driver.patch [new file with mode: 0644]
target/linux/ipq806x/patches-6.6/115-02-ARM-dts-qcom-add-fab-scaling-node-for-ipq806x.patch [new file with mode: 0644]
target/linux/ipq806x/patches-6.6/122-01-clk-qcom-krait-cc-handle-qsb-clock-defined-in-DTS.patch [new file with mode: 0644]
target/linux/ipq806x/patches-6.6/122-02-clk-qcom-krait-cc-register-REAL-qsb-fixed-clock.patch [new file with mode: 0644]
target/linux/ipq806x/patches-6.6/122-03-clk-qcom-krait-cc-drop-pr_info-and-use-dev_info.patch [new file with mode: 0644]
target/linux/ipq806x/patches-6.6/122-04-clk-qcom-krait-cc-rework-mux-reset-logic-and-reset-h.patch [new file with mode: 0644]
target/linux/ipq806x/patches-6.6/122-05-clk-qcom-clk-krait-generilize-div-functions.patch [new file with mode: 0644]
target/linux/ipq806x/patches-6.6/123-clk-qcom-gcc-ipq806x-remove-cc_register_board-for.patch [new file with mode: 0644]
target/linux/ipq806x/patches-6.6/850-soc-add-qualcomm-syscon.patch [new file with mode: 0644]
target/linux/ipq806x/patches-6.6/900-arm-add-cmdline-override.patch [new file with mode: 0644]
target/linux/ipq806x/patches-6.6/901-01-ARM-decompressor-support-memory-start-validation-.patch [new file with mode: 0644]
target/linux/ipq806x/patches-6.6/901-02-ARM-decompressor-add-option-to-ignore-MEM-ATAGs.patch [new file with mode: 0644]
target/linux/ipq806x/patches-6.6/902-ARM-decompressor-support-for-ATAGs-rootblock-parsing.patch [new file with mode: 0644]

diff --git a/target/linux/ipq806x/config-6.1 b/target/linux/ipq806x/config-6.1
deleted file mode 100644 (file)
index 18325c0..0000000
+++ /dev/null
@@ -1,538 +0,0 @@
-CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_APQ_GCC_8084 is not set
-# CONFIG_APQ_MMCC_8084 is not set
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-# CONFIG_ARCH_IPQ40XX is not set
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-# CONFIG_ARCH_MDM9615 is not set
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-# CONFIG_ARCH_MSM8909 is not set
-# CONFIG_ARCH_MSM8916 is not set
-CONFIG_ARCH_MSM8960=y
-CONFIG_ARCH_MSM8974=y
-CONFIG_ARCH_MSM8X60=y
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_QCOM=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_ATAG_DTB_COMPAT=y
-# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set
-CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE=y
-CONFIG_ARM_ATAG_DTB_COMPAT_IGNORE_MEM=y
-CONFIG_ARM_CPUIDLE=y
-CONFIG_ARM_CPU_SUSPEND=y
-# CONFIG_ARM_CPU_TOPOLOGY is not set
-CONFIG_ARM_GIC=y
-CONFIG_ARM_HAS_GROUP_RELOCS=y
-CONFIG_ARM_IPQ806X_FAB_DEVFREQ=y
-CONFIG_ARM_KRAIT_CACHE_DEVFREQ=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-CONFIG_ARM_PATCH_IDIV=y
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-# CONFIG_ARM_QCOM_CPUFREQ_HW is not set
-CONFIG_ARM_QCOM_CPUFREQ_NVMEM=y
-CONFIG_ARM_QCOM_SPM_CPUIDLE=y
-# CONFIG_ARM_SMMU is not set
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BOUNCE=y
-# CONFIG_CACHE_L2X0 is not set
-CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_CC_NO_ARRAY_BOUNDS=y
-CONFIG_CLKSRC_QCOM=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE_OVERRIDE=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMMON_CLK_QCOM=y
-CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONTEXT_TRACKING=y
-CONFIG_CONTEXT_TRACKING_IDLE=y
-CONFIG_CPUFREQ_DT=y
-CONFIG_CPUFREQ_DT_PLATDEV=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
-CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
-# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_SPECTRE=y
-CONFIG_CPU_THERMAL=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRC16=y
-# CONFIG_CRC32_SARWATE is not set
-CONFIG_CRC32_SLICEBY8=y
-CONFIG_CRC8=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_DEV_QCOM_RNG=y
-CONFIG_CRYPTO_DRBG=y
-CONFIG_CRYPTO_DRBG_HMAC=y
-CONFIG_CRYPTO_DRBG_MENU=y
-CONFIG_CRYPTO_HASH_INFO=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_JITTERENTROPY=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_SHA1=y
-CONFIG_CRYPTO_LIB_SHA256=y
-CONFIG_CRYPTO_LIB_UTILS=y
-CONFIG_CRYPTO_LZO=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_SHA256=y
-CONFIG_CRYPTO_SHA512=y
-CONFIG_CRYPTO_ZSTD=y
-CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_GPIO=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-CONFIG_DEVFREQ_GOV_PASSIVE=y
-# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set
-# CONFIG_DEVFREQ_GOV_POWERSAVE is not set
-# CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND is not set
-# CONFIG_DEVFREQ_GOV_USERSPACE is not set
-# CONFIG_DEVFREQ_THERMAL is not set
-CONFIG_DMADEVICES=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_OPS=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DTC=y
-CONFIG_DT_IDLE_STATES=y
-# CONFIG_DWMAC_GENERIC is not set
-CONFIG_DWMAC_IPQ806X=y
-# CONFIG_DWMAC_QCOM_ETHQOS is not set
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MIGRATION=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GENERIC_VDSO_32=y
-CONFIG_GLOB=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GRO_CELLS=y
-CONFIG_HARDEN_BRANCH_PREDICTOR=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HAVE_SMP=y
-CONFIG_HIGHMEM=y
-# CONFIG_HIGHPTE is not set
-CONFIG_HOTPLUG_CPU=y
-CONFIG_HWMON=y
-CONFIG_HWSPINLOCK=y
-CONFIG_HWSPINLOCK_QCOM=y
-CONFIG_HW_RANDOM=y
-CONFIG_HZ_FIXED=0
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_HELPER_AUTO=y
-# CONFIG_I2C_QCOM_CCI is not set
-CONFIG_I2C_QUP=y
-CONFIG_INITRAMFS_SOURCE=""
-# CONFIG_IOMMU_DEBUGFS is not set
-# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
-# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
-CONFIG_IOMMU_SUPPORT=y
-# CONFIG_IPQ_APSS_PLL is not set
-# CONFIG_IPQ_GCC_4019 is not set
-# CONFIG_IPQ_GCC_6018 is not set
-CONFIG_IPQ_GCC_806X=y
-# CONFIG_IPQ_GCC_8074 is not set
-# CONFIG_IPQ_LCC_806X is not set
-CONFIG_IRQCHIP=y
-CONFIG_IRQSTACKS=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_KMAP_LOCAL=y
-CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
-CONFIG_KPSS_XCC=y
-CONFIG_KRAITCC=y
-CONFIG_KRAIT_CLOCKS=y
-CONFIG_KRAIT_L2_ACCESSORS=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_MDIO_BITBANG=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MDIO_GPIO=y
-CONFIG_MDIO_IPQ8064=y
-# CONFIG_MDM_GCC_9615 is not set
-# CONFIG_MDM_LCC_9615 is not set
-CONFIG_MEMFD_CREATE=y
-# CONFIG_MFD_HI6421_SPMI is not set
-CONFIG_MFD_QCOM_RPM=y
-# CONFIG_MFD_SPMI_PMIC is not set
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_ARMMMCI=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_BLOCK_MINORS=16
-CONFIG_MMC_CQHCI=y
-CONFIG_MMC_QCOM_DML=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_IO_ACCESSORS=y
-CONFIG_MMC_SDHCI_MSM=y
-# CONFIG_MMC_SDHCI_PCI is not set
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MSM_GCC_8660=y
-# CONFIG_MSM_GCC_8909 is not set
-# CONFIG_MSM_GCC_8916 is not set
-# CONFIG_MSM_GCC_8939 is not set
-# CONFIG_MSM_GCC_8960 is not set
-# CONFIG_MSM_GCC_8974 is not set
-# CONFIG_MSM_GCC_8976 is not set
-# CONFIG_MSM_GCC_8994 is not set
-# CONFIG_MSM_GCC_8996 is not set
-# CONFIG_MSM_GCC_8998 is not set
-# CONFIG_MSM_GPUCC_8998 is not set
-# CONFIG_MSM_IOMMU is not set
-# CONFIG_MSM_LCC_8960 is not set
-# CONFIG_MSM_MMCC_8960 is not set
-# CONFIG_MSM_MMCC_8974 is not set
-# CONFIG_MSM_MMCC_8996 is not set
-# CONFIG_MSM_MMCC_8998 is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_ECC_SW_HAMMING=y
-CONFIG_MTD_NAND_QCOM=y
-CONFIG_MTD_QCOMSMEM_PARTS=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_FIT_FW=y
-CONFIG_MTD_SPLIT_UIMAGE_FW=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_BEB_LIMIT=20
-CONFIG_MTD_UBI_BLOCK=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEON=y
-CONFIG_NET_DEVLINK=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_QCA8K=y
-CONFIG_NET_DSA_QCA8K_LEDS_SUPPORT=y
-CONFIG_NET_DSA_TAG_QCA=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_SWITCHDEV=y
-CONFIG_NLS=y
-CONFIG_NO_HZ=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=2
-CONFIG_NVMEM=y
-CONFIG_NVMEM_LAYOUTS=y
-CONFIG_NVMEM_QCOM_QFPROM=y
-# CONFIG_NVMEM_QCOM_SEC_QFPROM is not set
-# CONFIG_NVMEM_SPMI_SDAM is not set
-CONFIG_NVMEM_SYSFS=y
-CONFIG_NVMEM_U_BOOT_ENV=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_PADATA=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
-CONFIG_PCI=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_DW=y
-CONFIG_PCIE_DW_HOST=y
-CONFIG_PCIE_QCOM=y
-CONFIG_PCI_DEBUG=y
-CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PCS_XPCS=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PHYLIB_LEDS=y
-CONFIG_PHYLINK=y
-# CONFIG_PHY_QCOM_APQ8064_SATA is not set
-# CONFIG_PHY_QCOM_EDP is not set
-# CONFIG_PHY_QCOM_IPQ4019_USB is not set
-CONFIG_PHY_QCOM_IPQ806X_SATA=y
-# CONFIG_PHY_QCOM_IPQ806X_USB is not set
-# CONFIG_PHY_QCOM_PCIE2 is not set
-# CONFIG_PHY_QCOM_QMP is not set
-# CONFIG_PHY_QCOM_QUSB2 is not set
-# CONFIG_PHY_QCOM_USB_HS_28NM is not set
-# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set
-# CONFIG_PHY_QCOM_USB_SS is not set
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_APQ8064 is not set
-# CONFIG_PINCTRL_APQ8084 is not set
-# CONFIG_PINCTRL_IPQ4019 is not set
-CONFIG_PINCTRL_IPQ8064=y
-# CONFIG_PINCTRL_MDM9615 is not set
-CONFIG_PINCTRL_MSM=y
-# CONFIG_PINCTRL_MSM8226 is not set
-# CONFIG_PINCTRL_MSM8660 is not set
-# CONFIG_PINCTRL_MSM8909 is not set
-# CONFIG_PINCTRL_MSM8916 is not set
-# CONFIG_PINCTRL_MSM8960 is not set
-# CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set
-# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set
-# CONFIG_PINCTRL_SDX65 is not set
-CONFIG_PM_DEVFREQ=y
-# CONFIG_PM_DEVFREQ_EVENT is not set
-CONFIG_PM_OPP=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_MSM=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PPS=y
-CONFIG_PREEMPT_NONE_BUILD=y
-CONFIG_PRINTK_TIME=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_QCA83XX_PHY=y
-# CONFIG_QCM_DISPCC_2290 is not set
-# CONFIG_QCM_GCC_2290 is not set
-# CONFIG_QCOM_A53PLL is not set
-CONFIG_QCOM_ADM=y
-CONFIG_QCOM_BAM_DMA=y
-CONFIG_QCOM_CLK_RPM=y
-# CONFIG_QCOM_COMMAND_DB is not set
-# CONFIG_QCOM_CPR is not set
-# CONFIG_QCOM_EBI2 is not set
-# CONFIG_QCOM_GENI_SE is not set
-CONFIG_QCOM_GSBI=y
-CONFIG_QCOM_HFPLL=y
-# CONFIG_QCOM_ICC_BWMON is not set
-# CONFIG_QCOM_IOMMU is not set
-# CONFIG_QCOM_LLCC is not set
-CONFIG_QCOM_NET_PHYLIB=y
-# CONFIG_QCOM_OCMEM is not set
-# CONFIG_QCOM_PDC is not set
-# CONFIG_QCOM_RMTFS_MEM is not set
-CONFIG_QCOM_RPMCC=y
-# CONFIG_QCOM_RPMH is not set
-CONFIG_QCOM_SCM=y
-# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set
-CONFIG_QCOM_SMEM=y
-# CONFIG_QCOM_SMSM is not set
-CONFIG_QCOM_SOCINFO=y
-CONFIG_QCOM_SPM=y
-# CONFIG_QCOM_STATS is not set
-CONFIG_QCOM_TCSR=y
-CONFIG_QCOM_TSENS=y
-CONFIG_QCOM_WDT=y
-# CONFIG_QCS_GCC_404 is not set
-# CONFIG_QCS_Q6SSTOP_404 is not set
-# CONFIG_QCS_TURING_404 is not set
-CONFIG_RANDSTRUCT_NONE=y
-CONFIG_RAS=y
-CONFIG_RATIONAL=y
-CONFIG_RCU_CPU_STALL_TIMEOUT=21
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-# CONFIG_REGULATOR_QCOM_LABIBB is not set
-CONFIG_REGULATOR_QCOM_RPM=y
-# CONFIG_REGULATOR_QCOM_SPMI is not set
-# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
-# CONFIG_REGULATOR_VQMMC_IPQ4019 is not set
-CONFIG_RESET_CONTROLLER=y
-# CONFIG_RESET_QCOM_AOSS is not set
-# CONFIG_RESET_QCOM_PDC is not set
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RTC_MC146818_LIB=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-# CONFIG_SC_CAMCC_7280 is not set
-# CONFIG_SC_DISPCC_7180 is not set
-# CONFIG_SC_GCC_7180 is not set
-# CONFIG_SC_GCC_8280XP is not set
-# CONFIG_SC_GPUCC_7180 is not set
-# CONFIG_SC_LPASSCC_7280 is not set
-# CONFIG_SC_LPASS_CORECC_7180 is not set
-# CONFIG_SC_LPASS_CORECC_7280 is not set
-# CONFIG_SC_MSS_7180 is not set
-# CONFIG_SC_VIDEOCC_7180 is not set
-# CONFIG_SDM_CAMCC_845 is not set
-# CONFIG_SDM_DISPCC_845 is not set
-# CONFIG_SDM_GCC_660 is not set
-# CONFIG_SDM_GCC_845 is not set
-# CONFIG_SDM_GPUCC_845 is not set
-# CONFIG_SDM_LPASSCC_845 is not set
-# CONFIG_SDM_VIDEOCC_845 is not set
-# CONFIG_SDX_GCC_65 is not set
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_MSM=y
-CONFIG_SERIAL_MSM_CONSOLE=y
-CONFIG_SGL_ALLOC=y
-CONFIG_SMP=y
-CONFIG_SMP_ON_UP=y
-# CONFIG_SM_CAMCC_8450 is not set
-# CONFIG_SM_GCC_8150 is not set
-# CONFIG_SM_GCC_8250 is not set
-# CONFIG_SM_GCC_8450 is not set
-# CONFIG_SM_GPUCC_6350 is not set
-# CONFIG_SM_GPUCC_8150 is not set
-# CONFIG_SM_GPUCC_8250 is not set
-# CONFIG_SM_GPUCC_8350 is not set
-# CONFIG_SM_VIDEOCC_8150 is not set
-# CONFIG_SM_VIDEOCC_8250 is not set
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SOC_BUS=y
-CONFIG_SOFTIRQ_ON_OWN_STACK=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-CONFIG_SPI_QUP=y
-CONFIG_SPMI=y
-# CONFIG_SPMI_HISI3670 is not set
-CONFIG_SPMI_MSM_PMIC_ARB=y
-# CONFIG_SPMI_PMIC_CLKDIV is not set
-CONFIG_SRCU=y
-CONFIG_STMMAC_ETH=y
-CONFIG_STMMAC_PLATFORM=y
-CONFIG_SWPHY=y
-CONFIG_SWP_EMULATE=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_HWMON=y
-CONFIG_THERMAL_OF=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_UBIFS_FS=y
-CONFIG_UBIFS_FS_ADVANCED_COMPR=y
-# CONFIG_UCLAMP_TASK is not set
-CONFIG_UEVENT_HELPER_PATH=""
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XPS=y
-CONFIG_XXHASH=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZSTD_COMMON=y
-CONFIG_ZSTD_COMPRESS=y
-CONFIG_ZSTD_DECOMPRESS=y
diff --git a/target/linux/ipq806x/config-6.6 b/target/linux/ipq806x/config-6.6
new file mode 100644 (file)
index 0000000..18325c0
--- /dev/null
@@ -0,0 +1,538 @@
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_APQ_GCC_8084 is not set
+# CONFIG_APQ_MMCC_8084 is not set
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+# CONFIG_ARCH_IPQ40XX is not set
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+# CONFIG_ARCH_MDM9615 is not set
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+# CONFIG_ARCH_MSM8909 is not set
+# CONFIG_ARCH_MSM8916 is not set
+CONFIG_ARCH_MSM8960=y
+CONFIG_ARCH_MSM8974=y
+CONFIG_ARCH_MSM8X60=y
+CONFIG_ARCH_MULTIPLATFORM=y
+CONFIG_ARCH_MULTI_V6_V7=y
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_ARCH_NR_GPIO=0
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+CONFIG_ARCH_QCOM=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARM=y
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
+# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set
+CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE=y
+CONFIG_ARM_ATAG_DTB_COMPAT_IGNORE_MEM=y
+CONFIG_ARM_CPUIDLE=y
+CONFIG_ARM_CPU_SUSPEND=y
+# CONFIG_ARM_CPU_TOPOLOGY is not set
+CONFIG_ARM_GIC=y
+CONFIG_ARM_HAS_GROUP_RELOCS=y
+CONFIG_ARM_IPQ806X_FAB_DEVFREQ=y
+CONFIG_ARM_KRAIT_CACHE_DEVFREQ=y
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+CONFIG_ARM_PATCH_IDIV=y
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+# CONFIG_ARM_QCOM_CPUFREQ_HW is not set
+CONFIG_ARM_QCOM_CPUFREQ_NVMEM=y
+CONFIG_ARM_QCOM_SPM_CPUIDLE=y
+# CONFIG_ARM_SMMU is not set
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_UNWIND=y
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BOUNCE=y
+# CONFIG_CACHE_L2X0 is not set
+CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CLKSRC_QCOM=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE_OVERRIDE=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_QCOM=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPUFREQ_DT_PLATDEV=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_SPECTRE=y
+CONFIG_CPU_THERMAL=y
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_V7=y
+CONFIG_CRC16=y
+# CONFIG_CRC32_SARWATE is not set
+CONFIG_CRC32_SLICEBY8=y
+CONFIG_CRC8=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_DEV_QCOM_RNG=y
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_DRBG_HMAC=y
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_SHA256=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_GPIO=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+CONFIG_DEVFREQ_GOV_PASSIVE=y
+# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set
+# CONFIG_DEVFREQ_GOV_POWERSAVE is not set
+# CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND is not set
+# CONFIG_DEVFREQ_GOV_USERSPACE is not set
+# CONFIG_DEVFREQ_THERMAL is not set
+CONFIG_DMADEVICES=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_OPS=y
+CONFIG_DMA_VIRTUAL_CHANNELS=y
+CONFIG_DTC=y
+CONFIG_DT_IDLE_STATES=y
+# CONFIG_DWMAC_GENERIC is not set
+CONFIG_DWMAC_IPQ806X=y
+# CONFIG_DWMAC_QCOM_ETHQOS is not set
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC11_NO_ARRAY_BOUNDS=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_VDSO_32=y
+CONFIG_GLOB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GRO_CELLS=y
+CONFIG_HARDEN_BRANCH_PREDICTOR=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HAVE_SMP=y
+CONFIG_HIGHMEM=y
+# CONFIG_HIGHPTE is not set
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HWMON=y
+CONFIG_HWSPINLOCK=y
+CONFIG_HWSPINLOCK_QCOM=y
+CONFIG_HW_RANDOM=y
+CONFIG_HZ_FIXED=0
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+# CONFIG_I2C_QCOM_CCI is not set
+CONFIG_I2C_QUP=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_IOMMU_DEBUGFS is not set
+# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
+# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
+CONFIG_IOMMU_SUPPORT=y
+# CONFIG_IPQ_APSS_PLL is not set
+# CONFIG_IPQ_GCC_4019 is not set
+# CONFIG_IPQ_GCC_6018 is not set
+CONFIG_IPQ_GCC_806X=y
+# CONFIG_IPQ_GCC_8074 is not set
+# CONFIG_IPQ_LCC_806X is not set
+CONFIG_IRQCHIP=y
+CONFIG_IRQSTACKS=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+CONFIG_KMAP_LOCAL=y
+CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
+CONFIG_KPSS_XCC=y
+CONFIG_KRAITCC=y
+CONFIG_KRAIT_CLOCKS=y
+CONFIG_KRAIT_L2_ACCESSORS=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MDIO_BITBANG=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MDIO_GPIO=y
+CONFIG_MDIO_IPQ8064=y
+# CONFIG_MDM_GCC_9615 is not set
+# CONFIG_MDM_LCC_9615 is not set
+CONFIG_MEMFD_CREATE=y
+# CONFIG_MFD_HI6421_SPMI is not set
+CONFIG_MFD_QCOM_RPM=y
+# CONFIG_MFD_SPMI_PMIC is not set
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_ARMMMCI=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=16
+CONFIG_MMC_CQHCI=y
+CONFIG_MMC_QCOM_DML=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+CONFIG_MMC_SDHCI_MSM=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MSM_GCC_8660=y
+# CONFIG_MSM_GCC_8909 is not set
+# CONFIG_MSM_GCC_8916 is not set
+# CONFIG_MSM_GCC_8939 is not set
+# CONFIG_MSM_GCC_8960 is not set
+# CONFIG_MSM_GCC_8974 is not set
+# CONFIG_MSM_GCC_8976 is not set
+# CONFIG_MSM_GCC_8994 is not set
+# CONFIG_MSM_GCC_8996 is not set
+# CONFIG_MSM_GCC_8998 is not set
+# CONFIG_MSM_GPUCC_8998 is not set
+# CONFIG_MSM_IOMMU is not set
+# CONFIG_MSM_LCC_8960 is not set
+# CONFIG_MSM_MMCC_8960 is not set
+# CONFIG_MSM_MMCC_8974 is not set
+# CONFIG_MSM_MMCC_8996 is not set
+# CONFIG_MSM_MMCC_8998 is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+CONFIG_MTD_NAND_QCOM=y
+CONFIG_MTD_QCOMSMEM_PARTS=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_SPLIT_FIT_FW=y
+CONFIG_MTD_SPLIT_UIMAGE_FW=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEON=y
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_QCA8K=y
+CONFIG_NET_DSA_QCA8K_LEDS_SUPPORT=y
+CONFIG_NET_DSA_TAG_QCA=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NLS=y
+CONFIG_NO_HZ=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=2
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_NVMEM_QCOM_QFPROM=y
+# CONFIG_NVMEM_QCOM_SEC_QFPROM is not set
+# CONFIG_NVMEM_SPMI_SDAM is not set
+CONFIG_NVMEM_SYSFS=y
+CONFIG_NVMEM_U_BOOT_ENV=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_PADATA=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
+CONFIG_PCI=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_DW=y
+CONFIG_PCIE_DW_HOST=y
+CONFIG_PCIE_QCOM=y
+CONFIG_PCI_DEBUG=y
+CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_MSI_IRQ_DOMAIN=y
+CONFIG_PCS_XPCS=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+CONFIG_PHYLINK=y
+# CONFIG_PHY_QCOM_APQ8064_SATA is not set
+# CONFIG_PHY_QCOM_EDP is not set
+# CONFIG_PHY_QCOM_IPQ4019_USB is not set
+CONFIG_PHY_QCOM_IPQ806X_SATA=y
+# CONFIG_PHY_QCOM_IPQ806X_USB is not set
+# CONFIG_PHY_QCOM_PCIE2 is not set
+# CONFIG_PHY_QCOM_QMP is not set
+# CONFIG_PHY_QCOM_QUSB2 is not set
+# CONFIG_PHY_QCOM_USB_HS_28NM is not set
+# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set
+# CONFIG_PHY_QCOM_USB_SS is not set
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_APQ8064 is not set
+# CONFIG_PINCTRL_APQ8084 is not set
+# CONFIG_PINCTRL_IPQ4019 is not set
+CONFIG_PINCTRL_IPQ8064=y
+# CONFIG_PINCTRL_MDM9615 is not set
+CONFIG_PINCTRL_MSM=y
+# CONFIG_PINCTRL_MSM8226 is not set
+# CONFIG_PINCTRL_MSM8660 is not set
+# CONFIG_PINCTRL_MSM8909 is not set
+# CONFIG_PINCTRL_MSM8916 is not set
+# CONFIG_PINCTRL_MSM8960 is not set
+# CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set
+# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set
+# CONFIG_PINCTRL_SDX65 is not set
+CONFIG_PM_DEVFREQ=y
+# CONFIG_PM_DEVFREQ_EVENT is not set
+CONFIG_PM_OPP=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_MSM=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PPS=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PRINTK_TIME=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_QCA83XX_PHY=y
+# CONFIG_QCM_DISPCC_2290 is not set
+# CONFIG_QCM_GCC_2290 is not set
+# CONFIG_QCOM_A53PLL is not set
+CONFIG_QCOM_ADM=y
+CONFIG_QCOM_BAM_DMA=y
+CONFIG_QCOM_CLK_RPM=y
+# CONFIG_QCOM_COMMAND_DB is not set
+# CONFIG_QCOM_CPR is not set
+# CONFIG_QCOM_EBI2 is not set
+# CONFIG_QCOM_GENI_SE is not set
+CONFIG_QCOM_GSBI=y
+CONFIG_QCOM_HFPLL=y
+# CONFIG_QCOM_ICC_BWMON is not set
+# CONFIG_QCOM_IOMMU is not set
+# CONFIG_QCOM_LLCC is not set
+CONFIG_QCOM_NET_PHYLIB=y
+# CONFIG_QCOM_OCMEM is not set
+# CONFIG_QCOM_PDC is not set
+# CONFIG_QCOM_RMTFS_MEM is not set
+CONFIG_QCOM_RPMCC=y
+# CONFIG_QCOM_RPMH is not set
+CONFIG_QCOM_SCM=y
+# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set
+CONFIG_QCOM_SMEM=y
+# CONFIG_QCOM_SMSM is not set
+CONFIG_QCOM_SOCINFO=y
+CONFIG_QCOM_SPM=y
+# CONFIG_QCOM_STATS is not set
+CONFIG_QCOM_TCSR=y
+CONFIG_QCOM_TSENS=y
+CONFIG_QCOM_WDT=y
+# CONFIG_QCS_GCC_404 is not set
+# CONFIG_QCS_Q6SSTOP_404 is not set
+# CONFIG_QCS_TURING_404 is not set
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+CONFIG_RCU_CPU_STALL_TIMEOUT=21
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+# CONFIG_REGULATOR_QCOM_LABIBB is not set
+CONFIG_REGULATOR_QCOM_RPM=y
+# CONFIG_REGULATOR_QCOM_SPMI is not set
+# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
+# CONFIG_REGULATOR_VQMMC_IPQ4019 is not set
+CONFIG_RESET_CONTROLLER=y
+# CONFIG_RESET_QCOM_AOSS is not set
+# CONFIG_RESET_QCOM_PDC is not set
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RTC_MC146818_LIB=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+# CONFIG_SC_CAMCC_7280 is not set
+# CONFIG_SC_DISPCC_7180 is not set
+# CONFIG_SC_GCC_7180 is not set
+# CONFIG_SC_GCC_8280XP is not set
+# CONFIG_SC_GPUCC_7180 is not set
+# CONFIG_SC_LPASSCC_7280 is not set
+# CONFIG_SC_LPASS_CORECC_7180 is not set
+# CONFIG_SC_LPASS_CORECC_7280 is not set
+# CONFIG_SC_MSS_7180 is not set
+# CONFIG_SC_VIDEOCC_7180 is not set
+# CONFIG_SDM_CAMCC_845 is not set
+# CONFIG_SDM_DISPCC_845 is not set
+# CONFIG_SDM_GCC_660 is not set
+# CONFIG_SDM_GCC_845 is not set
+# CONFIG_SDM_GPUCC_845 is not set
+# CONFIG_SDM_LPASSCC_845 is not set
+# CONFIG_SDM_VIDEOCC_845 is not set
+# CONFIG_SDX_GCC_65 is not set
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_MSM=y
+CONFIG_SERIAL_MSM_CONSOLE=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SMP=y
+CONFIG_SMP_ON_UP=y
+# CONFIG_SM_CAMCC_8450 is not set
+# CONFIG_SM_GCC_8150 is not set
+# CONFIG_SM_GCC_8250 is not set
+# CONFIG_SM_GCC_8450 is not set
+# CONFIG_SM_GPUCC_6350 is not set
+# CONFIG_SM_GPUCC_8150 is not set
+# CONFIG_SM_GPUCC_8250 is not set
+# CONFIG_SM_GPUCC_8350 is not set
+# CONFIG_SM_VIDEOCC_8150 is not set
+# CONFIG_SM_VIDEOCC_8250 is not set
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SOC_BUS=y
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SPI_QUP=y
+CONFIG_SPMI=y
+# CONFIG_SPMI_HISI3670 is not set
+CONFIG_SPMI_MSM_PMIC_ARB=y
+# CONFIG_SPMI_PMIC_CLKDIV is not set
+CONFIG_SRCU=y
+CONFIG_STMMAC_ETH=y
+CONFIG_STMMAC_PLATFORM=y
+CONFIG_SWPHY=y
+CONFIG_SWP_EMULATE=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_OF=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
+# CONFIG_UCLAMP_TASK is not set
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNWINDER_ARM=y
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_OF=y
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZSTD_COMMON=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y
diff --git a/target/linux/ipq806x/patches-6.1/001-v6.2-clk-qcom-kpss-xcc-register-it-as-clk-provider.patch b/target/linux/ipq806x/patches-6.1/001-v6.2-clk-qcom-kpss-xcc-register-it-as-clk-provider.patch
deleted file mode 100644 (file)
index 9395f1b..0000000
+++ /dev/null
@@ -1,60 +0,0 @@
-From 09be1a39e685d8c5edd471fd1cac9a8f8280d2de Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Tue, 8 Nov 2022 22:17:34 +0100
-Subject: [PATCH] clk: qcom: kpss-xcc: register it as clk provider
-
-krait-cc use this driver for the secondary mux. Register it as a clk
-provider to correctly use this clk in other drivers.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221108211734.3707-1-ansuelsmth@gmail.com
----
- drivers/clk/qcom/kpss-xcc.c | 13 +++++++++----
- 1 file changed, 9 insertions(+), 4 deletions(-)
-
---- a/drivers/clk/qcom/kpss-xcc.c
-+++ b/drivers/clk/qcom/kpss-xcc.c
-@@ -31,12 +31,13 @@ MODULE_DEVICE_TABLE(of, kpss_xcc_match_t
- static int kpss_xcc_driver_probe(struct platform_device *pdev)
- {
-+      struct device *dev = &pdev->dev;
-       const struct of_device_id *id;
-       void __iomem *base;
-       struct clk_hw *hw;
-       const char *name;
--      id = of_match_device(kpss_xcc_match_table, &pdev->dev);
-+      id = of_match_device(kpss_xcc_match_table, dev);
-       if (!id)
-               return -ENODEV;
-@@ -45,7 +46,7 @@ static int kpss_xcc_driver_probe(struct
-               return PTR_ERR(base);
-       if (id->data) {
--              if (of_property_read_string_index(pdev->dev.of_node,
-+              if (of_property_read_string_index(dev->of_node,
-                                                 "clock-output-names",
-                                                 0, &name))
-                       return -ENODEV;
-@@ -55,12 +56,16 @@ static int kpss_xcc_driver_probe(struct
-               base += 0x28;
-       }
--      hw = devm_clk_hw_register_mux_parent_data_table(&pdev->dev, name, aux_parents,
-+      hw = devm_clk_hw_register_mux_parent_data_table(dev, name, aux_parents,
-                                                       ARRAY_SIZE(aux_parents), 0,
-                                                       base, 0, 0x3,
-                                                       0, aux_parent_map, NULL);
-+      if (IS_ERR(hw))
-+              return PTR_ERR(hw);
--      return PTR_ERR_OR_ZERO(hw);
-+      of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, hw);
-+
-+      return 0;
- }
- static struct platform_driver kpss_xcc_driver = {
diff --git a/target/linux/ipq806x/patches-6.1/002-v6.2-01-clk-qcom-krait-cc-use-devm-variant-for-clk-notifier-.patch b/target/linux/ipq806x/patches-6.1/002-v6.2-01-clk-qcom-krait-cc-use-devm-variant-for-clk-notifier-.patch
deleted file mode 100644 (file)
index 65c1fc1..0000000
+++ /dev/null
@@ -1,27 +0,0 @@
-From 3198106a99e73dbc4c02bd5128cec0997c73af82 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Tue, 8 Nov 2022 22:58:27 +0100
-Subject: [PATCH 1/6] clk: qcom: krait-cc: use devm variant for clk notifier
- register
-
-Use devm variant for clk notifier register and correctly handle free
-resource on driver remove.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221108215827.30475-1-ansuelsmth@gmail.com
----
- drivers/clk/qcom/krait-cc.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/clk/qcom/krait-cc.c
-+++ b/drivers/clk/qcom/krait-cc.c
-@@ -62,7 +62,7 @@ static int krait_notifier_register(struc
-       int ret = 0;
-       mux->clk_nb.notifier_call = krait_notifier_cb;
--      ret = clk_notifier_register(clk, &mux->clk_nb);
-+      ret = devm_clk_notifier_register(dev, clk, &mux->clk_nb);
-       if (ret)
-               dev_err(dev, "failed to register clock notifier: %d\n", ret);
diff --git a/target/linux/ipq806x/patches-6.1/002-v6.2-02-clk-qcom-krait-cc-fix-wrong-parent-order-for-seconda.patch b/target/linux/ipq806x/patches-6.1/002-v6.2-02-clk-qcom-krait-cc-fix-wrong-parent-order-for-seconda.patch
deleted file mode 100644 (file)
index 2dcb693..0000000
+++ /dev/null
@@ -1,46 +0,0 @@
-From 8e456411abcbf899c04740b9dbb3dcefcd61c946 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Wed, 9 Nov 2022 01:56:27 +0100
-Subject: [PATCH 2/6] clk: qcom: krait-cc: fix wrong parent order for secondary
- mux
-
-The secondary mux parent order is swapped.
-This currently doesn't cause problems as the secondary mux is used for idle
-clk and as a safe clk source while reprogramming the hfpll.
-
-Each mux have 2 or more output but he always have a safe source to
-switch while reprogramming the connected pll. We use a clk notifier to
-switch to the correct parent before clk core can apply the correct rate.
-The parent to switch is hardcoded in the mux struct.
-
-For the secondary mux the safe source to use is the qsb parent as it's
-the only fixed clk as the acpus_aux is a pll that can source from pxo or
-from pll8.
-
-The hardcoded safe parent for the secondary mux is set to index 0 that
-in the secondary mux map is set to 2.
-
-But the index 0 is actually acpu_aux in the parent list.
-
-Fix the swapped parents to correctly handle idle frequency and output a
-sane clk_summary report.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221109005631.3189-1-ansuelsmth@gmail.com
----
- drivers/clk/qcom/krait-cc.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/clk/qcom/krait-cc.c
-+++ b/drivers/clk/qcom/krait-cc.c
-@@ -116,8 +116,8 @@ krait_add_sec_mux(struct device *dev, in
-       int ret;
-       struct krait_mux_clk *mux;
-       static const char *sec_mux_list[] = {
--              "acpu_aux",
-               "qsb",
-+              "acpu_aux",
-       };
-       struct clk_init_data init = {
-               .parent_names = sec_mux_list,
diff --git a/target/linux/ipq806x/patches-6.1/002-v6.2-03-clk-qcom-krait-cc-also-enable-secondary-mux-and-div-.patch b/target/linux/ipq806x/patches-6.1/002-v6.2-03-clk-qcom-krait-cc-also-enable-secondary-mux-and-div-.patch
deleted file mode 100644 (file)
index 6261a94..0000000
+++ /dev/null
@@ -1,68 +0,0 @@
-From 18ae57b1e8abee6c453381470f6e18991d2901a8 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Wed, 9 Nov 2022 01:56:28 +0100
-Subject: [PATCH 3/6] clk: qcom: krait-cc: also enable secondary mux and div
- clk
-
-clk-krait ignore any rate change if clk is not flagged as enabled.
-Correctly enable the secondary mux and div clk to correctly change rate
-instead of silently ignoring the request.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221109005631.3189-2-ansuelsmth@gmail.com
----
- drivers/clk/qcom/krait-cc.c | 21 ++++++++++++++++++++-
- 1 file changed, 20 insertions(+), 1 deletion(-)
-
---- a/drivers/clk/qcom/krait-cc.c
-+++ b/drivers/clk/qcom/krait-cc.c
-@@ -80,6 +80,7 @@ krait_add_div(struct device *dev, int id
-       };
-       const char *p_names[1];
-       struct clk *clk;
-+      int cpu;
-       div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
-       if (!div)
-@@ -103,6 +104,17 @@ krait_add_div(struct device *dev, int id
-       }
-       clk = devm_clk_register(dev, &div->hw);
-+      if (IS_ERR(clk))
-+              goto err;
-+
-+      /* clk-krait ignore any rate change if mux is not flagged as enabled */
-+      if (id < 0)
-+              for_each_online_cpu(cpu)
-+                      clk_prepare_enable(div->hw.clk);
-+      else
-+              clk_prepare_enable(div->hw.clk);
-+
-+err:
-       kfree(p_names[0]);
-       kfree(init.name);
-@@ -113,7 +125,7 @@ static int
- krait_add_sec_mux(struct device *dev, int id, const char *s,
-                 unsigned int offset, bool unique_aux)
- {
--      int ret;
-+      int cpu, ret;
-       struct krait_mux_clk *mux;
-       static const char *sec_mux_list[] = {
-               "qsb",
-@@ -165,6 +177,13 @@ krait_add_sec_mux(struct device *dev, in
-       if (ret)
-               goto unique_aux;
-+      /* clk-krait ignore any rate change if mux is not flagged as enabled */
-+      if (id < 0)
-+              for_each_online_cpu(cpu)
-+                      clk_prepare_enable(mux->hw.clk);
-+      else
-+              clk_prepare_enable(mux->hw.clk);
-+
- unique_aux:
-       if (unique_aux)
-               kfree(sec_mux_list[0]);
diff --git a/target/linux/ipq806x/patches-6.1/002-v6.2-04-clk-qcom-krait-cc-handle-secondary-mux-sourcing-out-.patch b/target/linux/ipq806x/patches-6.1/002-v6.2-04-clk-qcom-krait-cc-handle-secondary-mux-sourcing-out-.patch
deleted file mode 100644 (file)
index fabb299..0000000
+++ /dev/null
@@ -1,48 +0,0 @@
-From e5dc1a4c01510da8438dddfdf4200b79d73990dc Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Wed, 9 Nov 2022 01:56:29 +0100
-Subject: [PATCH 4/6] clk: qcom: krait-cc: handle secondary mux sourcing out of
- acpu_aux
-
-Some bootloader may leave the system in an even more undefined state
-with the secondary mux of L2 or other cores sourcing out of the acpu_aux
-parent. This results in the clk set to the PXO rate or a PLL8 rate.
-
-The current logic to reset the mux and set them to a defined state only
-handle if the mux are configured to source out of QSB. Change this and
-force a new and defined state if the current clk is lower than the aux
-rate. This way we can handle any wrong configuration where the mux is
-sourcing out of QSB (rate 225MHz, currently set to a virtual rate of 1),
-PXO rate (rate 25MHz) or PLL8 (needs to be configured to run at 384Mhz).
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221109005631.3189-3-ansuelsmth@gmail.com
----
- drivers/clk/qcom/krait-cc.c | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
---- a/drivers/clk/qcom/krait-cc.c
-+++ b/drivers/clk/qcom/krait-cc.c
-@@ -383,8 +383,8 @@ static int krait_cc_probe(struct platfor
-        */
-       cur_rate = clk_get_rate(l2_pri_mux_clk);
-       aux_rate = 384000000;
--      if (cur_rate == 1) {
--              pr_info("L2 @ QSB rate. Forcing new rate.\n");
-+      if (cur_rate < aux_rate) {
-+              pr_info("L2 @ Undefined rate. Forcing new rate.\n");
-               cur_rate = aux_rate;
-       }
-       clk_set_rate(l2_pri_mux_clk, aux_rate);
-@@ -394,8 +394,8 @@ static int krait_cc_probe(struct platfor
-       for_each_possible_cpu(cpu) {
-               clk = clks[cpu];
-               cur_rate = clk_get_rate(clk);
--              if (cur_rate == 1) {
--                      pr_info("CPU%d @ QSB rate. Forcing new rate.\n", cpu);
-+              if (cur_rate < aux_rate) {
-+                      pr_info("CPU%d @ Undefined rate. Forcing new rate.\n", cpu);
-                       cur_rate = aux_rate;
-               }
diff --git a/target/linux/ipq806x/patches-6.1/002-v6.2-05-clk-qcom-krait-cc-convert-to-devm_clk_hw_register.patch b/target/linux/ipq806x/patches-6.1/002-v6.2-05-clk-qcom-krait-cc-convert-to-devm_clk_hw_register.patch
deleted file mode 100644 (file)
index 049b1fa..0000000
+++ /dev/null
@@ -1,104 +0,0 @@
-From 8ea9fb841a7e528bc8ae79d726ce951dcf7b46e2 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Wed, 9 Nov 2022 01:56:30 +0100
-Subject: [PATCH 5/6] clk: qcom: krait-cc: convert to devm_clk_hw_register
-
-clk_register is now deprecated. Convert the driver to devm_clk_hw_register.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221109005631.3189-4-ansuelsmth@gmail.com
----
- drivers/clk/qcom/krait-cc.c | 31 +++++++++++++++++++------------
- 1 file changed, 19 insertions(+), 12 deletions(-)
-
---- a/drivers/clk/qcom/krait-cc.c
-+++ b/drivers/clk/qcom/krait-cc.c
-@@ -79,8 +79,7 @@ krait_add_div(struct device *dev, int id
-               .flags = CLK_SET_RATE_PARENT,
-       };
-       const char *p_names[1];
--      struct clk *clk;
--      int cpu;
-+      int cpu, ret;
-       div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
-       if (!div)
-@@ -103,8 +102,8 @@ krait_add_div(struct device *dev, int id
-               return -ENOMEM;
-       }
--      clk = devm_clk_register(dev, &div->hw);
--      if (IS_ERR(clk))
-+      ret = devm_clk_hw_register(dev, &div->hw);
-+      if (ret)
-               goto err;
-       /* clk-krait ignore any rate change if mux is not flagged as enabled */
-@@ -118,7 +117,7 @@ err:
-       kfree(p_names[0]);
-       kfree(init.name);
--      return PTR_ERR_OR_ZERO(clk);
-+      return ret;
- }
- static int
-@@ -137,7 +136,6 @@ krait_add_sec_mux(struct device *dev, in
-               .ops = &krait_mux_clk_ops,
-               .flags = CLK_SET_RATE_PARENT,
-       };
--      struct clk *clk;
-       mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
-       if (!mux)
-@@ -166,14 +164,16 @@ krait_add_sec_mux(struct device *dev, in
-       if (unique_aux) {
-               sec_mux_list[0] = kasprintf(GFP_KERNEL, "acpu%s_aux", s);
-               if (!sec_mux_list[0]) {
--                      clk = ERR_PTR(-ENOMEM);
-+                      ret = -ENOMEM;
-                       goto err_aux;
-               }
-       }
--      clk = devm_clk_register(dev, &mux->hw);
-+      ret = devm_clk_hw_register(dev, &mux->hw);
-+      if (ret)
-+              goto unique_aux;
--      ret = krait_notifier_register(dev, clk, mux);
-+      ret = krait_notifier_register(dev, mux->hw.clk, mux);
-       if (ret)
-               goto unique_aux;
-@@ -189,7 +189,7 @@ unique_aux:
-               kfree(sec_mux_list[0]);
- err_aux:
-       kfree(init.name);
--      return PTR_ERR_OR_ZERO(clk);
-+      return ret;
- }
- static struct clk *
-@@ -241,11 +241,18 @@ krait_add_pri_mux(struct device *dev, in
-               goto err_p2;
-       }
--      clk = devm_clk_register(dev, &mux->hw);
-+      ret = devm_clk_hw_register(dev, &mux->hw);
-+      if (ret) {
-+              clk = ERR_PTR(ret);
-+              goto err_p3;
-+      }
-+
-+      clk = mux->hw.clk;
-       ret = krait_notifier_register(dev, clk, mux);
-       if (ret)
--              goto err_p3;
-+              clk = ERR_PTR(ret);
-+
- err_p3:
-       kfree(p_names[2]);
- err_p2:
diff --git a/target/linux/ipq806x/patches-6.1/002-v6.2-06-clk-qcom-krait-cc-convert-to-parent_data-API.patch b/target/linux/ipq806x/patches-6.1/002-v6.2-06-clk-qcom-krait-cc-convert-to-parent_data-API.patch
deleted file mode 100644 (file)
index 453a37d..0000000
+++ /dev/null
@@ -1,414 +0,0 @@
-From 56a655e1c41a86445cf2de656649ad93424b2a63 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Wed, 9 Nov 2022 01:56:31 +0100
-Subject: [PATCH 6/6] clk: qcom: krait-cc: convert to parent_data API
-
-Modernize the krait-cc driver to parent-data API and refactor to drop
-any use of parent_names. From Documentation all the required clocks should
-be declared in DTS so fw_name can be correctly used to get the parents
-for all the muxes. .name is also declared to save compatibility with old
-DT.
-
-While at it also drop some hardcoded index and introduce an enum to make
-index values more clear.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221109005631.3189-5-ansuelsmth@gmail.com
----
- drivers/clk/qcom/krait-cc.c | 202 ++++++++++++++++++++----------------
- 1 file changed, 112 insertions(+), 90 deletions(-)
-
---- a/drivers/clk/qcom/krait-cc.c
-+++ b/drivers/clk/qcom/krait-cc.c
-@@ -15,6 +15,16 @@
- #include "clk-krait.h"
-+enum {
-+      cpu0_mux = 0,
-+      cpu1_mux,
-+      cpu2_mux,
-+      cpu3_mux,
-+      l2_mux,
-+
-+      clks_max,
-+};
-+
- static unsigned int sec_mux_map[] = {
-       2,
-       0,
-@@ -69,21 +79,23 @@ static int krait_notifier_register(struc
-       return ret;
- }
--static int
-+static struct clk_hw *
- krait_add_div(struct device *dev, int id, const char *s, unsigned int offset)
- {
-       struct krait_div2_clk *div;
-+      static struct clk_parent_data p_data[1];
-       struct clk_init_data init = {
--              .num_parents = 1,
-+              .num_parents = ARRAY_SIZE(p_data),
-               .ops = &krait_div2_clk_ops,
-               .flags = CLK_SET_RATE_PARENT,
-       };
--      const char *p_names[1];
-+      struct clk_hw *clk;
-+      char *parent_name;
-       int cpu, ret;
-       div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
-       if (!div)
--              return -ENOMEM;
-+              return ERR_PTR(-ENOMEM);
-       div->width = 2;
-       div->shift = 6;
-@@ -93,18 +105,25 @@ krait_add_div(struct device *dev, int id
-       init.name = kasprintf(GFP_KERNEL, "hfpll%s_div", s);
-       if (!init.name)
--              return -ENOMEM;
-+              return ERR_PTR(-ENOMEM);
--      init.parent_names = p_names;
--      p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s);
--      if (!p_names[0]) {
--              kfree(init.name);
--              return -ENOMEM;
-+      init.parent_data = p_data;
-+      parent_name = kasprintf(GFP_KERNEL, "hfpll%s", s);
-+      if (!parent_name) {
-+              clk = ERR_PTR(-ENOMEM);
-+              goto err_parent_name;
-       }
-+      p_data[0].fw_name = parent_name;
-+      p_data[0].name = parent_name;
-+
-       ret = devm_clk_hw_register(dev, &div->hw);
--      if (ret)
--              goto err;
-+      if (ret) {
-+              clk = ERR_PTR(ret);
-+              goto err_clk;
-+      }
-+
-+      clk = &div->hw;
-       /* clk-krait ignore any rate change if mux is not flagged as enabled */
-       if (id < 0)
-@@ -113,33 +132,36 @@ krait_add_div(struct device *dev, int id
-       else
-               clk_prepare_enable(div->hw.clk);
--err:
--      kfree(p_names[0]);
-+err_clk:
-+      kfree(parent_name);
-+err_parent_name:
-       kfree(init.name);
--      return ret;
-+      return clk;
- }
--static int
-+static struct clk_hw *
- krait_add_sec_mux(struct device *dev, int id, const char *s,
-                 unsigned int offset, bool unique_aux)
- {
-       int cpu, ret;
-       struct krait_mux_clk *mux;
--      static const char *sec_mux_list[] = {
--              "qsb",
--              "acpu_aux",
-+      static struct clk_parent_data sec_mux_list[2] = {
-+              { .name = "qsb", .fw_name = "qsb" },
-+              {},
-       };
-       struct clk_init_data init = {
--              .parent_names = sec_mux_list,
-+              .parent_data = sec_mux_list,
-               .num_parents = ARRAY_SIZE(sec_mux_list),
-               .ops = &krait_mux_clk_ops,
-               .flags = CLK_SET_RATE_PARENT,
-       };
-+      struct clk_hw *clk;
-+      char *parent_name;
-       mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
-       if (!mux)
--              return -ENOMEM;
-+              return ERR_PTR(-ENOMEM);
-       mux->offset = offset;
-       mux->lpl = id >= 0;
-@@ -159,23 +181,33 @@ krait_add_sec_mux(struct device *dev, in
-       init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
-       if (!init.name)
--              return -ENOMEM;
-+              return ERR_PTR(-ENOMEM);
-       if (unique_aux) {
--              sec_mux_list[0] = kasprintf(GFP_KERNEL, "acpu%s_aux", s);
--              if (!sec_mux_list[0]) {
--                      ret = -ENOMEM;
-+              parent_name = kasprintf(GFP_KERNEL, "acpu%s_aux", s);
-+              if (!parent_name) {
-+                      clk = ERR_PTR(-ENOMEM);
-                       goto err_aux;
-               }
-+              sec_mux_list[1].fw_name = parent_name;
-+              sec_mux_list[1].name = parent_name;
-+      } else {
-+              sec_mux_list[1].name = "apu_aux";
-       }
-       ret = devm_clk_hw_register(dev, &mux->hw);
--      if (ret)
--              goto unique_aux;
-+      if (ret) {
-+              clk = ERR_PTR(ret);
-+              goto err_clk;
-+      }
-+
-+      clk = &mux->hw;
-       ret = krait_notifier_register(dev, mux->hw.clk, mux);
--      if (ret)
--              goto unique_aux;
-+      if (ret) {
-+              clk = ERR_PTR(ret);
-+              goto err_clk;
-+      }
-       /* clk-krait ignore any rate change if mux is not flagged as enabled */
-       if (id < 0)
-@@ -184,28 +216,29 @@ krait_add_sec_mux(struct device *dev, in
-       else
-               clk_prepare_enable(mux->hw.clk);
--unique_aux:
-+err_clk:
-       if (unique_aux)
--              kfree(sec_mux_list[0]);
-+              kfree(parent_name);
- err_aux:
-       kfree(init.name);
--      return ret;
-+      return clk;
- }
--static struct clk *
--krait_add_pri_mux(struct device *dev, int id, const char *s,
--                unsigned int offset)
-+static struct clk_hw *
-+krait_add_pri_mux(struct device *dev, struct clk_hw *hfpll_div, struct clk_hw *sec_mux,
-+                int id, const char *s, unsigned int offset)
- {
-       int ret;
-       struct krait_mux_clk *mux;
--      const char *p_names[3];
-+      static struct clk_parent_data p_data[3];
-       struct clk_init_data init = {
--              .parent_names = p_names,
--              .num_parents = ARRAY_SIZE(p_names),
-+              .parent_data = p_data,
-+              .num_parents = ARRAY_SIZE(p_data),
-               .ops = &krait_mux_clk_ops,
-               .flags = CLK_SET_RATE_PARENT,
-       };
--      struct clk *clk;
-+      struct clk_hw *clk;
-+      char *hfpll_name;
-       mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
-       if (!mux)
-@@ -223,55 +256,44 @@ krait_add_pri_mux(struct device *dev, in
-       if (!init.name)
-               return ERR_PTR(-ENOMEM);
--      p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s);
--      if (!p_names[0]) {
-+      hfpll_name = kasprintf(GFP_KERNEL, "hfpll%s", s);
-+      if (!hfpll_name) {
-               clk = ERR_PTR(-ENOMEM);
--              goto err_p0;
-+              goto err_hfpll;
-       }
--      p_names[1] = kasprintf(GFP_KERNEL, "hfpll%s_div", s);
--      if (!p_names[1]) {
--              clk = ERR_PTR(-ENOMEM);
--              goto err_p1;
--      }
-+      p_data[0].fw_name = hfpll_name;
-+      p_data[0].name = hfpll_name;
--      p_names[2] = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
--      if (!p_names[2]) {
--              clk = ERR_PTR(-ENOMEM);
--              goto err_p2;
--      }
-+      p_data[1].hw = hfpll_div;
-+      p_data[2].hw = sec_mux;
-       ret = devm_clk_hw_register(dev, &mux->hw);
-       if (ret) {
-               clk = ERR_PTR(ret);
--              goto err_p3;
-+              goto err_clk;
-       }
--      clk = mux->hw.clk;
-+      clk = &mux->hw;
--      ret = krait_notifier_register(dev, clk, mux);
-+      ret = krait_notifier_register(dev, mux->hw.clk, mux);
-       if (ret)
-               clk = ERR_PTR(ret);
--err_p3:
--      kfree(p_names[2]);
--err_p2:
--      kfree(p_names[1]);
--err_p1:
--      kfree(p_names[0]);
--err_p0:
-+err_clk:
-+      kfree(hfpll_name);
-+err_hfpll:
-       kfree(init.name);
-       return clk;
- }
- /* id < 0 for L2, otherwise id == physical CPU number */
--static struct clk *krait_add_clks(struct device *dev, int id, bool unique_aux)
-+static struct clk_hw *krait_add_clks(struct device *dev, int id, bool unique_aux)
- {
--      int ret;
-+      struct clk_hw *hfpll_div, *sec_mux, *pri_mux;
-       unsigned int offset;
-       void *p = NULL;
-       const char *s;
--      struct clk *clk;
-       if (id >= 0) {
-               offset = 0x4501 + (0x1000 * id);
-@@ -283,22 +305,23 @@ static struct clk *krait_add_clks(struct
-               s = "_l2";
-       }
--      ret = krait_add_div(dev, id, s, offset);
--      if (ret) {
--              clk = ERR_PTR(ret);
-+      hfpll_div = krait_add_div(dev, id, s, offset);
-+      if (IS_ERR(hfpll_div)) {
-+              pri_mux = hfpll_div;
-               goto err;
-       }
--      ret = krait_add_sec_mux(dev, id, s, offset, unique_aux);
--      if (ret) {
--              clk = ERR_PTR(ret);
-+      sec_mux = krait_add_sec_mux(dev, id, s, offset, unique_aux);
-+      if (IS_ERR(sec_mux)) {
-+              pri_mux = sec_mux;
-               goto err;
-       }
--      clk = krait_add_pri_mux(dev, id, s, offset);
-+      pri_mux = krait_add_pri_mux(dev, hfpll_div, sec_mux, id, s, offset);
-+
- err:
-       kfree(p);
--      return clk;
-+      return pri_mux;
- }
- static struct clk *krait_of_get(struct of_phandle_args *clkspec, void *data)
-@@ -306,7 +329,7 @@ static struct clk *krait_of_get(struct o
-       unsigned int idx = clkspec->args[0];
-       struct clk **clks = data;
--      if (idx >= 5) {
-+      if (idx >= clks_max) {
-               pr_err("%s: invalid clock index %d\n", __func__, idx);
-               return ERR_PTR(-EINVAL);
-       }
-@@ -327,9 +350,8 @@ static int krait_cc_probe(struct platfor
-       const struct of_device_id *id;
-       unsigned long cur_rate, aux_rate;
-       int cpu;
--      struct clk *clk;
--      struct clk **clks;
--      struct clk *l2_pri_mux_clk;
-+      struct clk_hw *mux, *l2_pri_mux;
-+      struct clk *clk, **clks;
-       id = of_match_device(krait_cc_match_table, dev);
-       if (!id)
-@@ -348,21 +370,21 @@ static int krait_cc_probe(struct platfor
-       }
-       /* Krait configurations have at most 4 CPUs and one L2 */
--      clks = devm_kcalloc(dev, 5, sizeof(*clks), GFP_KERNEL);
-+      clks = devm_kcalloc(dev, clks_max, sizeof(*clks), GFP_KERNEL);
-       if (!clks)
-               return -ENOMEM;
-       for_each_possible_cpu(cpu) {
--              clk = krait_add_clks(dev, cpu, id->data);
-+              mux = krait_add_clks(dev, cpu, id->data);
-               if (IS_ERR(clk))
-                       return PTR_ERR(clk);
--              clks[cpu] = clk;
-+              clks[cpu] = mux->clk;
-       }
--      l2_pri_mux_clk = krait_add_clks(dev, -1, id->data);
--      if (IS_ERR(l2_pri_mux_clk))
--              return PTR_ERR(l2_pri_mux_clk);
--      clks[4] = l2_pri_mux_clk;
-+      l2_pri_mux = krait_add_clks(dev, -1, id->data);
-+      if (IS_ERR(l2_pri_mux))
-+              return PTR_ERR(l2_pri_mux);
-+      clks[l2_mux] = l2_pri_mux->clk;
-       /*
-        * We don't want the CPU or L2 clocks to be turned off at late init
-@@ -372,7 +394,7 @@ static int krait_cc_probe(struct platfor
-        * they take over.
-        */
-       for_each_online_cpu(cpu) {
--              clk_prepare_enable(l2_pri_mux_clk);
-+              clk_prepare_enable(clks[l2_mux]);
-               WARN(clk_prepare_enable(clks[cpu]),
-                    "Unable to turn on CPU%d clock", cpu);
-       }
-@@ -388,16 +410,16 @@ static int krait_cc_probe(struct platfor
-        * two different rates to force a HFPLL reinit under all
-        * circumstances.
-        */
--      cur_rate = clk_get_rate(l2_pri_mux_clk);
-+      cur_rate = clk_get_rate(clks[l2_mux]);
-       aux_rate = 384000000;
-       if (cur_rate < aux_rate) {
-               pr_info("L2 @ Undefined rate. Forcing new rate.\n");
-               cur_rate = aux_rate;
-       }
--      clk_set_rate(l2_pri_mux_clk, aux_rate);
--      clk_set_rate(l2_pri_mux_clk, 2);
--      clk_set_rate(l2_pri_mux_clk, cur_rate);
--      pr_info("L2 @ %lu KHz\n", clk_get_rate(l2_pri_mux_clk) / 1000);
-+      clk_set_rate(clks[l2_mux], aux_rate);
-+      clk_set_rate(clks[l2_mux], 2);
-+      clk_set_rate(clks[l2_mux], cur_rate);
-+      pr_info("L2 @ %lu KHz\n", clk_get_rate(clks[l2_mux]) / 1000);
-       for_each_possible_cpu(cpu) {
-               clk = clks[cpu];
-               cur_rate = clk_get_rate(clk);
diff --git a/target/linux/ipq806x/patches-6.1/003-v6.2-ARM-dts-qcom-ipq8064-disable-mmc-ddr-1_8v-for-sdcc1.patch b/target/linux/ipq806x/patches-6.1/003-v6.2-ARM-dts-qcom-ipq8064-disable-mmc-ddr-1_8v-for-sdcc1.patch
deleted file mode 100644 (file)
index 7e65f4c..0000000
+++ /dev/null
@@ -1,28 +0,0 @@
-From c9713e4ede1e5d044b64fe4d3cbb84223625637f Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Tue, 25 Oct 2022 01:38:17 +0200
-Subject: [PATCH] ARM: dts: qcom: ipq8064: disable mmc-ddr-1_8v for sdcc1
-
-It was reported non working mmc with this option enabled.
-Both mmc for ipq8064 are supplied by a fixed 3.3v regulator so mmc can't
-be run at 1.8v.
-Disable it to restore correct functionality of this SoC feature.
-
-Tested-by: Hendrik Koerner <koerhen@web.de>
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221024233817.27410-1-ansuelsmth@gmail.com
----
- arch/arm/boot/dts/qcom-ipq8064.dtsi | 1 -
- 1 file changed, 1 deletion(-)
-
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -756,7 +756,6 @@
-                               non-removable;
-                               cap-sd-highspeed;
-                               cap-mmc-highspeed;
--                              mmc-ddr-1_8v;
-                               vmmc-supply = <&vsdcc_fixed>;
-                               dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
-                               dma-names = "tx", "rx";
diff --git a/target/linux/ipq806x/patches-6.1/004-v6.2-01-thermal-drivers-qcom-tsens-Init-debugfs-only-with-su.patch b/target/linux/ipq806x/patches-6.1/004-v6.2-01-thermal-drivers-qcom-tsens-Init-debugfs-only-with-su.patch
deleted file mode 100644 (file)
index 76df0f5..0000000
+++ /dev/null
@@ -1,42 +0,0 @@
-From de48d8766afcd97d147699aaff78a338081c9973 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Sat, 22 Oct 2022 14:56:55 +0200
-Subject: [PATCH 1/3] thermal/drivers/qcom/tsens: Init debugfs only with
- successful probe
-
-Calibrate and tsens_register can fail or PROBE_DEFER. This will cause a
-double or a wrong init of the debugfs information. Init debugfs only
-with successful probe fixing warning about directory already present.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Acked-by: Thara Gopinath <thara.gopinath@linaro.org>
-Link: https://lore.kernel.org/r/20221022125657.22530-2-ansuelsmth@gmail.com
-Signed-off-by: Daniel Lezcano <daniel.lezcano@kernel.org>
----
- drivers/thermal/qcom/tsens.c | 8 +++++---
- 1 file changed, 5 insertions(+), 3 deletions(-)
-
---- a/drivers/thermal/qcom/tsens.c
-+++ b/drivers/thermal/qcom/tsens.c
-@@ -918,8 +918,6 @@ int __init init_common(struct tsens_priv
-       if (tsens_version(priv) >= VER_0_1)
-               tsens_enable_irq(priv);
--      tsens_debug_init(op);
--
- err_put_device:
-       put_device(&op->dev);
-       return ret;
-@@ -1156,7 +1154,11 @@ static int tsens_probe(struct platform_d
-               }
-       }
--      return tsens_register(priv);
-+      ret = tsens_register(priv);
-+      if (!ret)
-+              tsens_debug_init(pdev);
-+
-+      return ret;
- }
- static int tsens_remove(struct platform_device *pdev)
diff --git a/target/linux/ipq806x/patches-6.1/004-v6.2-02-thermal-drivers-qcom-tsens-Fix-wrong-version-id-dbg_.patch b/target/linux/ipq806x/patches-6.1/004-v6.2-02-thermal-drivers-qcom-tsens-Fix-wrong-version-id-dbg_.patch
deleted file mode 100644 (file)
index 10f1e36..0000000
+++ /dev/null
@@ -1,29 +0,0 @@
-From c7e077e921fa94e0c06c8d14af6c0504c8a5f4bd Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Sat, 22 Oct 2022 14:56:56 +0200
-Subject: [PATCH 2/3] thermal/drivers/qcom/tsens: Fix wrong version id
- dbg_version_show
-
-For VER_0 the version was incorrectly reported as 0.1.0.
-
-Fix that and correctly report the major version for this old tsens
-revision.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Link: https://lore.kernel.org/r/20221022125657.22530-3-ansuelsmth@gmail.com
-Signed-off-by: Daniel Lezcano <daniel.lezcano@kernel.org>
----
- drivers/thermal/qcom/tsens.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/thermal/qcom/tsens.c
-+++ b/drivers/thermal/qcom/tsens.c
-@@ -692,7 +692,7 @@ static int dbg_version_show(struct seq_f
-                       return ret;
-               seq_printf(s, "%d.%d.%d\n", maj_ver, min_ver, step_ver);
-       } else {
--              seq_puts(s, "0.1.0\n");
-+              seq_printf(s, "0.%d.0\n", priv->feat->ver_major);
-       }
-       return 0;
diff --git a/target/linux/ipq806x/patches-6.1/004-v6.2-03-thermal-drivers-qcom-tsens-Rework-debugfs-file-struc.patch b/target/linux/ipq806x/patches-6.1/004-v6.2-03-thermal-drivers-qcom-tsens-Rework-debugfs-file-struc.patch
deleted file mode 100644 (file)
index 63cce79..0000000
+++ /dev/null
@@ -1,54 +0,0 @@
-From 89992d95ed1046338c7866ef7bbe6de543a2af91 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Sat, 22 Oct 2022 14:56:57 +0200
-Subject: [PATCH 3/3] thermal/drivers/qcom/tsens: Rework debugfs file structure
-
-The current tsens debugfs structure is composed by:
-- a tsens dir in debugfs with a version file
-- a directory for each tsens istance with sensors file to dump all the
-  sensors value.
-
-This works on the assumption that we have the same version for each
-istance but this assumption seems fragile and with more than one tsens
-istance results in the version file not tracking each of them.
-
-A better approach is to just create a subdirectory for each tsens
-istance and put there version and sensors debugfs file.
-
-Using this new implementation results in less code since debugfs entry
-are created only on successful tsens probe.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Link: https://lore.kernel.org/r/20221022125657.22530-4-ansuelsmth@gmail.com
-Signed-off-by: Daniel Lezcano <daniel.lezcano@kernel.org>
----
- drivers/thermal/qcom/tsens.c | 13 +++----------
- 1 file changed, 3 insertions(+), 10 deletions(-)
-
---- a/drivers/thermal/qcom/tsens.c
-+++ b/drivers/thermal/qcom/tsens.c
-@@ -704,21 +704,14 @@ DEFINE_SHOW_ATTRIBUTE(dbg_sensors);
- static void tsens_debug_init(struct platform_device *pdev)
- {
-       struct tsens_priv *priv = platform_get_drvdata(pdev);
--      struct dentry *root, *file;
--      root = debugfs_lookup("tsens", NULL);
--      if (!root)
-+      priv->debug_root = debugfs_lookup("tsens", NULL);
-+      if (!priv->debug_root)
-               priv->debug_root = debugfs_create_dir("tsens", NULL);
--      else
--              priv->debug_root = root;
--
--      file = debugfs_lookup("version", priv->debug_root);
--      if (!file)
--              debugfs_create_file("version", 0444, priv->debug_root,
--                                  pdev, &dbg_version_fops);
-       /* A directory for each instance of the TSENS IP */
-       priv->debug = debugfs_create_dir(dev_name(&pdev->dev), priv->debug_root);
-+      debugfs_create_file("version", 0444, priv->debug, pdev, &dbg_version_fops);
-       debugfs_create_file("sensors", 0444, priv->debug, pdev, &dbg_sensors_fops);
- }
- #else
diff --git a/target/linux/ipq806x/patches-6.1/102-mtd-rootfs-conflicts-with-OpenWrt-auto-mounting.patch b/target/linux/ipq806x/patches-6.1/102-mtd-rootfs-conflicts-with-OpenWrt-auto-mounting.patch
deleted file mode 100644 (file)
index e0c195f..0000000
+++ /dev/null
@@ -1,25 +0,0 @@
-From 5001f2e1a325b68dbf225bd17f69a4d3d975cca5 Mon Sep 17 00:00:00 2001
-From: John Crispin <john@phrozen.org>
-Date: Thu, 9 Mar 2017 09:31:44 +0100
-Subject: [PATCH 61/69] mtd: "rootfs" conflicts with OpenWrt auto mounting
-
-Signed-off-by: John Crispin <john@phrozen.org>
----
- drivers/mtd/mtdpart.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/drivers/mtd/mtdpart.c
-+++ b/drivers/mtd/mtdpart.c
-@@ -51,7 +51,11 @@ static struct mtd_info *allocate_partiti
-       /* allocate the partition structure */
-       child = kzalloc(sizeof(*child), GFP_KERNEL);
--      name = kstrdup(part->name, GFP_KERNEL);
-+      /* "rootfs" conflicts with OpenWrt auto mounting */
-+      if (mtd_type_is_nand(parent) && !strcmp(part->name, "rootfs"))
-+              name = "ubi";
-+      else
-+              name = kstrdup(part->name, GFP_KERNEL);
-       if (!name || !child) {
-               printk(KERN_ERR"memory allocation error while creating partitions for \"%s\"\n",
-                      parent->name);
diff --git a/target/linux/ipq806x/patches-6.1/107-10-ARM-dts-qcom-add-saw-for-l2-cache-and-kraitcc-for.patch b/target/linux/ipq806x/patches-6.1/107-10-ARM-dts-qcom-add-saw-for-l2-cache-and-kraitcc-for.patch
deleted file mode 100644 (file)
index 0a594b2..0000000
+++ /dev/null
@@ -1,89 +0,0 @@
-From bef5018abb7cf94efafdc05087b4c998891ae4ec Mon Sep 17 00:00:00 2001
-From: Ansuel Smith <ansuelsmth@gmail.com>
-Date: Mon, 17 Jan 2022 23:39:34 +0100
-Subject: [PATCH v3 10/18] ARM: dts: qcom: add saw for l2 cache and kraitcc for
- ipq8064
-
-Add saw compatible for l2 cache and kraitcc node for ipq8064 dtsi.
-Also declare clock-output-names for acc0 and acc1 and qsb fixed clock
-for the secondary mux.
-
-Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
-Tested-by: Jonathan McDowell <noodles@earth.li>
----
- arch/arm/boot/dts/qcom-ipq8064.dtsi | 34 +++++++++++++++++++++++++++--
- 1 file changed, 32 insertions(+), 2 deletions(-)
-
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -301,6 +301,12 @@
-       };
-       clocks {
-+              qsb: qsb {
-+                      compatible = "fixed-clock";
-+                      clock-frequency = <225000000>;
-+                      #clock-cells = <0>;
-+              };
-+
-               cxo_board: cxo_board {
-                       compatible = "fixed-clock";
-                       #clock-cells = <0>;
-@@ -575,15 +581,30 @@
-                       clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
-                       clock-names = "pll8_vote", "pxo";
-                       clock-output-names = "acpu_l2_aux";
-+                      #clock-cells = <0>;
-+              };
-+
-+              kraitcc: clock-controller {
-+                      compatible = "qcom,krait-cc-v1";
-+                      clocks = <&gcc PLL9>, <&gcc PLL10>, <&gcc PLL12>,
-+                               <&acc0>, <&acc1>, <&l2cc>, <&qsb>, <&pxo_board>;
-+                      clock-names = "hfpll0", "hfpll1", "hfpll_l2",
-+                                    "acpu0_aux", "acpu1_aux", "acpu_l2_aux",
-+                                    "qsb", "pxo";
-+                      #clock-cells = <1>;
-               };
-               acc0: clock-controller@2088000 {
-                       compatible = "qcom,kpss-acc-v1";
-                       reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
-+                      clock-output-names = "acpu0_aux";
-+                      clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
-+                      clock-names = "pll8_vote", "pxo";
-+                      #clock-cells = <0>;
-               };
-               saw0: regulator@2089000 {
--                      compatible = "qcom,saw2";
-+                      compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
-                       reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
-                       regulator;
-               };
-@@ -591,14 +612,24 @@
-               acc1: clock-controller@2098000 {
-                       compatible = "qcom,kpss-acc-v1";
-                       reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
-+                      clock-output-names = "acpu1_aux";
-+                      clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
-+                      clock-names = "pll8_vote", "pxo";
-+                      #clock-cells = <0>;
-               };
-               saw1: regulator@2099000 {
--                      compatible = "qcom,saw2";
-+                      compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
-                       reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
-                       regulator;
-               };
-+              saw_l2: regulator@02012000 {
-+                      compatible = "qcom,saw2", "syscon";
-+                      reg = <0x02012000 0x1000>;
-+                      regulator;
-+              };
-+
-               nss_common: syscon@03000000 {
-                       compatible = "syscon";
-                       reg = <0x03000000 0x0000FFFF>;
diff --git a/target/linux/ipq806x/patches-6.1/107-13-ARM-dts-qcom-add-opp-table-for-cpu-and-l2-for-ipq.patch b/target/linux/ipq806x/patches-6.1/107-13-ARM-dts-qcom-add-opp-table-for-cpu-and-l2-for-ipq.patch
deleted file mode 100644 (file)
index 16e924b..0000000
+++ /dev/null
@@ -1,268 +0,0 @@
-From 076ebb6e1799c4c7a1d2e07510d88b9e9b57b551 Mon Sep 17 00:00:00 2001
-From: Ansuel Smith <ansuelsmth@gmail.com>
-Date: Tue, 18 Jan 2022 00:03:47 +0100
-Subject: [PATCH v3 13/18] ARM: dts: qcom: add opp table for cpu and l2 for
- ipq8064
-
-Add opp table for cpu and l2 cache. While the current cpufreq is
-the generic one that doesn't scale the L2 cache, we add the l2
-cache opp anyway for the sake of completeness. This will be handy in the
-future when a dedicated cpufreq driver is introduced for krait cores
-that will correctly scale l2 cache with the core freq.
-
-Opp-level is set based on the logic of
-0: idle level
-1: normal level
-2: turbo level
-
-Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
-Tested-by: Jonathan McDowell <noodles@earth.li>
----
- arch/arm/boot/dts/qcom-ipq8064.dtsi | 99 +++++++++++++++++++++++++++++
- 1 file changed, 99 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -48,6 +48,105 @@
-               };
-       };
-+      opp_table_l2: opp_table_l2 {
-+              compatible = "operating-points-v2";
-+
-+              opp-384000000 {
-+                      opp-hz = /bits/ 64 <384000000>;
-+                      opp-microvolt = <1100000>;
-+                      clock-latency-ns = <100000>;
-+                      opp-level = <0>;
-+              };
-+
-+              opp-1000000000 {
-+                      opp-hz = /bits/ 64 <1000000000>;
-+                      opp-microvolt = <1100000>;
-+                      clock-latency-ns = <100000>;
-+                      opp-level = <1>;
-+              };
-+
-+              opp-1200000000 {
-+                      opp-hz = /bits/ 64 <1200000000>;
-+                      opp-microvolt = <1150000>;
-+                      clock-latency-ns = <100000>;
-+                      opp-level = <2>;
-+              };
-+      };
-+
-+      opp_table0: opp_table0 {
-+              compatible = "operating-points-v2-kryo-cpu";
-+              nvmem-cells = <&speedbin_efuse>;
-+
-+              /*
-+               * Voltage thresholds are <target min max>
-+               */
-+              opp-384000000 {
-+                      opp-hz = /bits/ 64 <384000000>;
-+                      opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;
-+                      opp-microvolt-speed0-pvs1-v0 = <925000 878750 971250>;
-+                      opp-microvolt-speed0-pvs2-v0 = <875000 831250 918750>;
-+                      opp-microvolt-speed0-pvs3-v0 = <800000 760000 840000>;
-+                      opp-supported-hw = <0x1>;
-+                      clock-latency-ns = <100000>;
-+                      opp-level = <0>;
-+              };
-+
-+              opp-600000000 {
-+                      opp-hz = /bits/ 64 <600000000>;
-+                      opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;
-+                      opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>;
-+                      opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>;
-+                      opp-microvolt-speed0-pvs3-v0 = <850000 807500 892500>;
-+                      opp-supported-hw = <0x1>;
-+                      clock-latency-ns = <100000>;
-+                      opp-level = <1>;
-+              };
-+
-+              opp-800000000 {
-+                      opp-hz = /bits/ 64 <800000000>;
-+                      opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;
-+                      opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>;
-+                      opp-microvolt-speed0-pvs2-v0 = <995000 945250 1044750>;
-+                      opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>;
-+                      opp-supported-hw = <0x1>;
-+                      clock-latency-ns = <100000>;
-+                      opp-level = <1>;
-+              };
-+
-+              opp-1000000000 {
-+                      opp-hz = /bits/ 64 <1000000000>;
-+                      opp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>;
-+                      opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;
-+                      opp-microvolt-speed0-pvs2-v0 = <1025000 973750 1076250>;
-+                      opp-microvolt-speed0-pvs3-v0 = <950000 902500 997500>;
-+                      opp-supported-hw = <0x1>;
-+                      clock-latency-ns = <100000>;
-+                      opp-level = <1>;
-+              };
-+
-+              opp-1200000000 {
-+                      opp-hz = /bits/ 64 <1200000000>;
-+                      opp-microvolt-speed0-pvs0-v0 = <1200000 1140000 1260000>;
-+                      opp-microvolt-speed0-pvs1-v0 = <1125000 1068750 1181250>;
-+                      opp-microvolt-speed0-pvs2-v0 = <1075000 1021250 1128750>;
-+                      opp-microvolt-speed0-pvs3-v0 = <1000000 950000 1050000>;
-+                      opp-supported-hw = <0x1>;
-+                      clock-latency-ns = <100000>;
-+                      opp-level = <2>;
-+              };
-+
-+              opp-1400000000 {
-+                      opp-hz = /bits/ 64 <1400000000>;
-+                      opp-microvolt-speed0-pvs0-v0 = <1250000 1187500 1312500>;
-+                      opp-microvolt-speed0-pvs1-v0 = <1175000 1116250 1233750>;
-+                      opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>;
-+                      opp-microvolt-speed0-pvs3-v0 = <1050000 997500 1102500>;
-+                      opp-supported-hw = <0x1>;
-+                      clock-latency-ns = <100000>;
-+                      opp-level = <2>;
-+              };
-+      };
-+
-       thermal-zones {
-               sensor0-thermal {
-                       polling-delay-passive = <0>;
---- a/arch/arm/boot/dts/qcom-ipq8065.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8065.dtsi
-@@ -6,3 +6,92 @@
-       model = "Qualcomm Technologies, Inc. IPQ8065";
-       compatible = "qcom,ipq8065", "qcom,ipq8064";
- };
-+
-+&opp_table_l2 {
-+      /delete-node/opp-1200000000;
-+
-+      opp-1400000000 {
-+              opp-hz = /bits/ 64 <1400000000>;
-+              opp-microvolt = <1150000>;
-+              clock-latency-ns = <100000>;
-+              opp-level = <2>;
-+      };
-+};
-+
-+&opp_table0 {
-+      /*
-+       * On ipq8065 1.2 ghz freq is not present
-+       * Remove it to make cpufreq work and not
-+       * complain for missing definition
-+       */
-+
-+      /delete-node/opp-1200000000;
-+
-+      /*
-+       * Voltage thresholds are <target min max>
-+       */
-+      opp-384000000 {
-+              opp-microvolt-speed0-pvs0-v0 = <975000 926250 1023750>;
-+              opp-microvolt-speed0-pvs1-v0 = <950000 902500 997500>;
-+              opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>;
-+              opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>;
-+              opp-microvolt-speed0-pvs4-v0 = <875000 831250 918750>;
-+              opp-microvolt-speed0-pvs5-v0 = <825000 783750 866250>;
-+              opp-microvolt-speed0-pvs6-v0 = <775000 736250 813750>;
-+      };
-+
-+      opp-600000000 {
-+              opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;
-+              opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>;
-+              opp-microvolt-speed0-pvs2-v0 = <950000 902500 997500>;
-+              opp-microvolt-speed0-pvs3-v0 = <925000 878750 971250>;
-+              opp-microvolt-speed0-pvs4-v0 = <900000 855000 945000>;
-+              opp-microvolt-speed0-pvs5-v0 = <850000 807500 892500>;
-+              opp-microvolt-speed0-pvs6-v0 = <800000 760000 840000>;
-+      };
-+
-+      opp-800000000 {
-+              opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;
-+              opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>;
-+              opp-microvolt-speed0-pvs2-v0 = <1000000 950000 1050000>;
-+              opp-microvolt-speed0-pvs3-v0 = <975000 926250 1023750>;
-+              opp-microvolt-speed0-pvs4-v0 = <950000 902500 997500>;
-+              opp-microvolt-speed0-pvs5-v0 = <900000 855000 945000>;
-+              opp-microvolt-speed0-pvs6-v0 = <850000 807500 892500>;
-+      };
-+
-+      opp-1000000000 {
-+              opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;
-+              opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;
-+              opp-microvolt-speed0-pvs2-v0 = <1050000 997500 1102500>;
-+              opp-microvolt-speed0-pvs3-v0 = <1025000 973750 1076250>;
-+              opp-microvolt-speed0-pvs4-v0 = <1000000 950000 1050000>;
-+              opp-microvolt-speed0-pvs5-v0 = <950000 902500 997500>;
-+              opp-microvolt-speed0-pvs6-v0 = <900000 855000 945000>;
-+      };
-+
-+      opp-1400000000 {
-+              opp-microvolt-speed0-pvs0-v0 = <1175000 1116250 1233750>;
-+              opp-microvolt-speed0-pvs1-v0 = <1150000 1092500 1207500>;
-+              opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>;
-+              opp-microvolt-speed0-pvs3-v0 = <1100000 1045000 1155000>;
-+              opp-microvolt-speed0-pvs4-v0 = <1075000 1021250 1128750>;
-+              opp-microvolt-speed0-pvs5-v0 = <1025000 973750 1076250>;
-+              opp-microvolt-speed0-pvs6-v0 = <975000 926250 1023750>;
-+              opp-level = <1>;
-+      };
-+
-+      opp-1725000000 {
-+              opp-hz = /bits/ 64 <1725000000>;
-+              opp-microvolt-speed0-pvs0-v0 = <1262500 1199375 1325625>;
-+              opp-microvolt-speed0-pvs1-v0 = <1225000 1163750 1286250>;
-+              opp-microvolt-speed0-pvs2-v0 = <1200000 1140000 1260000>;
-+              opp-microvolt-speed0-pvs3-v0 = <1175000 1116250 1233750>;
-+              opp-microvolt-speed0-pvs4-v0 = <1150000 1092500 1207500>;
-+              opp-microvolt-speed0-pvs5-v0 = <1100000 1045000 1155000>;
-+              opp-microvolt-speed0-pvs6-v0 = <1050000 997500 1102500>;
-+              opp-supported-hw = <0x1>;
-+              clock-latency-ns = <100000>;
-+              opp-level = <2>;
-+      };
-+};
---- a/arch/arm/boot/dts/qcom-ipq8062.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8062.dtsi
-@@ -6,3 +6,39 @@
-       model = "Qualcomm Technologies, Inc. IPQ8062";
-       compatible = "qcom,ipq8062", "qcom,ipq8064";
- };
-+
-+&opp_table0 {
-+      /delete-node/opp-1200000000;
-+      /delete-node/opp-1400000000;
-+
-+      /*
-+       * Voltage thresholds are <target min max>
-+       */
-+      opp-384000000 {
-+              opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;
-+              opp-microvolt-speed0-pvs1-v0 = < 925000 878750  971250>;
-+              opp-microvolt-speed0-pvs2-v0 = < 875000 831250  918750>;
-+              opp-microvolt-speed0-pvs3-v0 = < 800000 760000  840000>;
-+      };
-+
-+      opp-600000000 {
-+              opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;
-+              opp-microvolt-speed0-pvs1-v0 = < 975000 926250 1023750>;
-+              opp-microvolt-speed0-pvs2-v0 = < 925000 878750  971250>;
-+              opp-microvolt-speed0-pvs3-v0 = < 850000 807500  892500>;
-+      };
-+
-+      opp-800000000 {
-+              opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;
-+              opp-microvolt-speed0-pvs1-v0 = <1025000  973750 1076250>;
-+              opp-microvolt-speed0-pvs2-v0 = < 995000  945250 1044750>;
-+              opp-microvolt-speed0-pvs3-v0 = < 900000  855000  945000>;
-+      };
-+
-+      opp-1000000000 {
-+              opp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>;
-+              opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;
-+              opp-microvolt-speed0-pvs2-v0 = <1025000  973750 1076250>;
-+              opp-microvolt-speed0-pvs3-v0 = < 950000  902500  997500>;
-+      };
-+};
diff --git a/target/linux/ipq806x/patches-6.1/107-15-ARM-dts-qcom-add-multiple-missing-binding-for-cpu.patch b/target/linux/ipq806x/patches-6.1/107-15-ARM-dts-qcom-add-multiple-missing-binding-for-cpu.patch
deleted file mode 100644 (file)
index cf27aaa..0000000
+++ /dev/null
@@ -1,153 +0,0 @@
-From 211fc0c0a63c99b68663a27182e643316c2d8cbe Mon Sep 17 00:00:00 2001
-From: Ansuel Smith <ansuelsmth@gmail.com>
-Date: Tue, 18 Jan 2022 00:07:57 +0100
-Subject: [PATCH v3 15/18] ARM: dts: qcom: add multiple missing binding for cpu
- and l2 for ipq8064
-
-Add multiple binding for cpu node, l2 node and add idle-states
-definition for ipq8064 dtsi.
-
-Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
-Tested-by: Jonathan McDowell <noodles@earth.li>
----
- arch/arm/boot/dts/qcom-ipq8064.dtsi | 36 +++++++++++++++++++++++++++++
- 1 file changed, 36 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -30,6 +30,15 @@
-                       next-level-cache = <&L2>;
-                       qcom,acc = <&acc0>;
-                       qcom,saw = <&saw0>;
-+                      clocks = <&kraitcc 0>, <&kraitcc 4>;
-+                      clock-names = "cpu", "l2";
-+                      clock-latency = <100000>;
-+                      operating-points-v2 = <&opp_table0>;
-+                      voltage-tolerance = <5>;
-+                      cooling-min-state = <0>;
-+                      cooling-max-state = <10>;
-+                      #cooling-cells = <2>;
-+                      cpu-idle-states = <&CPU_SPC>;
-               };
-               cpu1: cpu@1 {
-@@ -40,11 +49,35 @@
-                       next-level-cache = <&L2>;
-                       qcom,acc = <&acc1>;
-                       qcom,saw = <&saw1>;
-+                      clocks = <&kraitcc 1>, <&kraitcc 4>;
-+                      clock-names = "cpu", "l2";
-+                      clock-latency = <100000>;
-+                      operating-points-v2 = <&opp_table0>;
-+                      voltage-tolerance = <5>;
-+                      cooling-min-state = <0>;
-+                      cooling-max-state = <10>;
-+                      #cooling-cells = <2>;
-+                      cpu-idle-states = <&CPU_SPC>;
-+              };
-+
-+              idle-states {
-+                      CPU_SPC: spc {
-+                              compatible = "qcom,idle-state-spc";
-+                              status = "disabled";
-+                              entry-latency-us = <400>;
-+                              exit-latency-us = <900>;
-+                              min-residency-us = <3000>;
-+                      };
-               };
-               L2: l2-cache {
-                       compatible = "cache";
-                       cache-level = <2>;
-+                      qcom,saw = <&saw_l2>;
-+
-+                      clocks = <&kraitcc 4>;
-+                      clock-names = "l2";
-+                      operating-points-v2 = <&opp_table_l2>;
-               };
-       };
---- a/arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi
-@@ -2,6 +2,18 @@
- #include "qcom-ipq8064.dtsi"
-+&cpu0 {
-+      cpu-supply = <&smb208_s2a>;
-+};
-+
-+&cpu1 {
-+      cpu-supply = <&smb208_s2b>;
-+};
-+
-+&L2 {
-+      l2-supply = <&smb208_s1a>;
-+};
-+
- &rpm {
-       smb208_regulators: regulators {
-               compatible = "qcom,rpm-smb208-regulators";
---- a/arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi
-@@ -2,6 +2,18 @@
- #include "qcom-ipq8064-v2.0.dtsi"
-+&cpu0 {
-+      cpu-supply = <&smb208_s2a>;
-+};
-+
-+&cpu1 {
-+      cpu-supply = <&smb208_s2b>;
-+};
-+
-+&L2 {
-+      l2-supply = <&smb208_s1a>;
-+};
-+
- &rpm {
-       smb208_regulators: regulators {
-               compatible = "qcom,rpm-smb208-regulators";
---- a/arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi
-@@ -2,6 +2,18 @@
- #include "qcom-ipq8062.dtsi"
-+&cpu0 {
-+      cpu-supply = <&smb208_s2a>;
-+};
-+
-+&cpu1 {
-+      cpu-supply = <&smb208_s2b>;
-+};
-+
-+&L2 {
-+      l2-supply = <&smb208_s1a>;
-+};
-+
- &rpm {
-       smb208_regulators: regulators {
-               compatible = "qcom,rpm-smb208-regulators";
---- a/arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi
-@@ -2,6 +2,18 @@
- #include "qcom-ipq8065.dtsi"
-+&cpu0 {
-+      cpu-supply = <&smb208_s2a>;
-+};
-+
-+&cpu1 {
-+      cpu-supply = <&smb208_s2b>;
-+};
-+
-+&L2 {
-+      l2-supply = <&smb208_s1a>;
-+};
-+
- &rpm {
-       smb208_regulators: regulators {
-               compatible = "qcom,rpm-smb208-regulators";
diff --git a/target/linux/ipq806x/patches-6.1/108-01-ARM-dts-qcom-fix-wrong-nad_pins-definition-for-ipq80.patch b/target/linux/ipq806x/patches-6.1/108-01-ARM-dts-qcom-fix-wrong-nad_pins-definition-for-ipq80.patch
deleted file mode 100644 (file)
index 6be9334..0000000
+++ /dev/null
@@ -1,29 +0,0 @@
-From 6c94e0184e56f9e9f1f5d5f54b20758433e498d2 Mon Sep 17 00:00:00 2001
-From: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
-Date: Wed, 15 Jun 2022 16:47:09 +0200
-Subject: [PATCH 1/2] ARM: dts: qcom: fix wrong nad_pins definition for ipq806x
-
-Fix wrong nand_pings definition for bias-disable pins.
-
-Signed-off-by: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
----
- arch/arm/boot/dts/qcom-ipq8064.dtsi | 7 ++-----
- 1 file changed, 2 insertions(+), 5 deletions(-)
-
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -599,12 +599,9 @@
-                       };
-                       nand_pins: nand_pins {
--                              mux {
-+                              disable {
-                                       pins = "gpio34", "gpio35", "gpio36",
--                                             "gpio37", "gpio38", "gpio39",
--                                             "gpio40", "gpio41", "gpio42",
--                                             "gpio43", "gpio44", "gpio45",
--                                             "gpio46", "gpio47";
-+                                             "gpio37", "gpio38";
-                                       function = "nand";
-                                       drive-strength = <10>;
-                                       bias-disable;
diff --git a/target/linux/ipq806x/patches-6.1/108-02-ARM-dts-qcom-add-MDIO-dedicated-controller-node-for-.patch b/target/linux/ipq806x/patches-6.1/108-02-ARM-dts-qcom-add-MDIO-dedicated-controller-node-for-.patch
deleted file mode 100644 (file)
index a35bb38..0000000
+++ /dev/null
@@ -1,188 +0,0 @@
-From 504188183408fac0f61b59f5ed8ea1773fe43669 Mon Sep 17 00:00:00 2001
-From: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
-Date: Wed, 15 Jun 2022 16:59:30 +0200
-Subject: [PATCH 2/2] ARM: dts: qcom: add MDIO dedicated controller node for
- ipq806x
-
-Add MDIO dedicated controller attached to gmac0 and fix rb3011 dts to
-correctly use the new tag.
-
-Signed-off-by: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
----
- arch/arm/boot/dts/qcom-ipq8064-rb3011.dts | 134 +++++++++++-----------
- arch/arm/boot/dts/qcom-ipq8064.dtsi       |  14 +++
- 2 files changed, 81 insertions(+), 67 deletions(-)
-
---- a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
-+++ b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
-@@ -25,73 +25,6 @@
-               device_type = "memory";
-       };
--      mdio0: mdio-0 {
--              status = "okay";
--              compatible = "virtual,mdio-gpio";
--              gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>,
--                      <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
--              #address-cells = <1>;
--              #size-cells = <0>;
--
--              pinctrl-0 = <&mdio0_pins>;
--              pinctrl-names = "default";
--
--              switch0: switch@10 {
--                      compatible = "qca,qca8337";
--                      #address-cells = <1>;
--                      #size-cells = <0>;
--
--                      dsa,member = <0 0>;
--
--                      pinctrl-0 = <&sw0_reset_pin>;
--                      pinctrl-names = "default";
--
--                      reset-gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;
--                      reg = <0x10>;
--
--                      ports {
--                              #address-cells = <1>;
--                              #size-cells = <0>;
--
--                              switch0cpu: port@0 {
--                                      reg = <0>;
--                                      label = "cpu";
--                                      ethernet = <&gmac0>;
--                                      phy-mode = "rgmii-id";
--                                      fixed-link {
--                                              speed = <1000>;
--                                              full-duplex;
--                                      };
--                              };
--
--                              port@1 {
--                                      reg = <1>;
--                                      label = "sw1";
--                              };
--
--                              port@2 {
--                                      reg = <2>;
--                                      label = "sw2";
--                              };
--
--                              port@3 {
--                                      reg = <3>;
--                                      label = "sw3";
--                              };
--
--                              port@4 {
--                                      reg = <4>;
--                                      label = "sw4";
--                              };
--
--                              port@5 {
--                                      reg = <5>;
--                                      label = "sw5";
--                              };
--                      };
--              };
--      };
--
-       mdio1: mdio-1 {
-               status = "okay";
-               compatible = "virtual,mdio-gpio";
-@@ -222,6 +155,73 @@
-       status = "okay";
- };
-+&mdio0 {
-+      status = "okay";
-+      compatible = "virtual,mdio-gpio";
-+      gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>,
-+              <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
-+      #address-cells = <1>;
-+      #size-cells = <0>;
-+
-+      pinctrl-0 = <&mdio0_pins>;
-+      pinctrl-names = "default";
-+
-+      switch0: switch@10 {
-+              compatible = "qca,qca8337";
-+              #address-cells = <1>;
-+              #size-cells = <0>;
-+
-+              dsa,member = <0 0>;
-+
-+              pinctrl-0 = <&sw0_reset_pin>;
-+              pinctrl-names = "default";
-+
-+              reset-gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;
-+              reg = <0x10>;
-+
-+              ports {
-+                      #address-cells = <1>;
-+                      #size-cells = <0>;
-+
-+                      switch0cpu: port@0 {
-+                              reg = <0>;
-+                              label = "cpu";
-+                              ethernet = <&gmac0>;
-+                              phy-mode = "rgmii-id";
-+                              fixed-link {
-+                                      speed = <1000>;
-+                                      full-duplex;
-+                              };
-+                      };
-+
-+                      port@1 {
-+                              reg = <1>;
-+                              label = "sw1";
-+                      };
-+
-+                      port@2 {
-+                              reg = <2>;
-+                              label = "sw2";
-+                      };
-+
-+                      port@3 {
-+                              reg = <3>;
-+                              label = "sw3";
-+                      };
-+
-+                      port@4 {
-+                              reg = <4>;
-+                              label = "sw4";
-+                      };
-+
-+                      port@5 {
-+                              reg = <5>;
-+                              label = "sw5";
-+                      };
-+              };
-+      };
-+};
-+
- &gmac0 {
-       status = "okay";
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -476,6 +476,20 @@
-                       snps,blen = <16 0 0 0 0 0 0>;
-               };
-+              mdio0: mdio@37000000 {
-+                      #address-cells = <1>;
-+                      #size-cells = <0>;
-+
-+                      compatible = "qcom,ipq8064-mdio", "syscon";
-+                      reg = <0x37000000 0x200000>;
-+                      resets = <&gcc GMAC_CORE1_RESET>;
-+                      reset-names = "stmmaceth";
-+                      clocks = <&gcc GMAC_CORE1_CLK>;
-+                      clock-names = "stmmaceth";
-+
-+                      status = "disabled";
-+              };
-+
-               vsdcc_fixed: vsdcc-regulator {
-                       compatible = "regulator-fixed";
-                       regulator-name = "SDCC Power";
diff --git a/target/linux/ipq806x/patches-6.1/114-01-devfreq-qcom-Add-L2-Krait-Cache-devfreq-scaling-driv.patch b/target/linux/ipq806x/patches-6.1/114-01-devfreq-qcom-Add-L2-Krait-Cache-devfreq-scaling-driv.patch
deleted file mode 100644 (file)
index 9de7328..0000000
+++ /dev/null
@@ -1,235 +0,0 @@
-From b044ae89862132a86fb511648e9c52ea3cdf8c30 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Wed, 5 Aug 2020 14:19:23 +0200
-Subject: [PATCH 1/4] devfreq: qcom: Add L2 Krait Cache devfreq scaling driver
-
-Qcom L2 Krait CPUs use the generic cpufreq-dt driver and doesn't actually
-scale the Cache frequency when the CPU frequency is changed. This
-devfreq driver register with the cpu notifier and scale the Cache
-based on the max Freq across all core as the CPU cache is shared across
-all of them. If provided this also scale the voltage of the regulator
-attached to the CPU cache. The scaling logic is based on the CPU freq
-and the 3 scaling interval are set by the device dts.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- drivers/devfreq/Kconfig               |  11 ++
- drivers/devfreq/Makefile              |   1 +
- drivers/devfreq/krait-cache-devfreq.c | 188 ++++++++++++++++++++++++++
- 3 files changed, 200 insertions(+)
- create mode 100644 drivers/devfreq/krait-cache-devfreq.c
-
---- a/drivers/devfreq/Kconfig
-+++ b/drivers/devfreq/Kconfig
-@@ -151,6 +151,17 @@ config ARM_SUN8I_A33_MBUS_DEVFREQ
-         This adds the DEVFREQ driver for the MBUS controller in some
-         Allwinner sun8i (A33 through H3) and sun50i (A64 and H5) SoCs.
-+config ARM_KRAIT_CACHE_DEVFREQ
-+      tristate "Scaling support for Krait CPU Cache Devfreq"
-+      depends on ARCH_QCOM || COMPILE_TEST
-+      select DEVFREQ_GOV_PASSIVE
-+      help
-+        This adds the DEVFREQ driver for the Krait CPU L2 Cache shared by all cores.
-+
-+        The driver register with the cpufreq notifier and find the right frequency
-+        based on the max frequency across all core and the range set in the device
-+        dts. If provided this scale also the regulator attached to the l2 cache.
-+
- source "drivers/devfreq/event/Kconfig"
- endif # PM_DEVFREQ
---- a/drivers/devfreq/Makefile
-+++ b/drivers/devfreq/Makefile
-@@ -15,6 +15,7 @@ obj-$(CONFIG_ARM_MEDIATEK_CCI_DEVFREQ)       +
- obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ)  += rk3399_dmc.o
- obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ)      += sun8i-a33-mbus.o
- obj-$(CONFIG_ARM_TEGRA_DEVFREQ)               += tegra30-devfreq.o
-+obj-$(CONFIG_ARM_KRAIT_CACHE_DEVFREQ) += krait-cache-devfreq.o
- # DEVFREQ Event Drivers
- obj-$(CONFIG_PM_DEVFREQ_EVENT)                += event/
---- /dev/null
-+++ b/drivers/devfreq/krait-cache-devfreq.c
-@@ -0,0 +1,181 @@
-+// SPDX-License-Identifier: GPL-2.0
-+
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/cpufreq.h>
-+#include <linux/devfreq.h>
-+#include <linux/of.h>
-+#include <linux/platform_device.h>
-+#include <linux/clk.h>
-+#include <linux/slab.h>
-+#include <linux/regulator/consumer.h>
-+#include <linux/pm_opp.h>
-+
-+#include "governor.h"
-+
-+struct krait_cache_data {
-+      struct clk *clk;
-+      unsigned long idle_freq;
-+      int token;
-+};
-+
-+static int krait_cache_config_clk(struct device *dev, struct opp_table *opp_table,
-+                      struct dev_pm_opp *old_opp, struct dev_pm_opp *opp,
-+                      void *data, bool scaling_down)
-+{
-+      struct krait_cache_data *kdata;
-+      unsigned long old_freq, freq;
-+      unsigned long idle_freq;
-+      struct clk *clk;
-+      int ret;
-+
-+      kdata = dev_get_drvdata(dev);
-+      idle_freq = kdata->idle_freq;
-+      clk = kdata->clk;
-+
-+      old_freq = dev_pm_opp_get_freq(old_opp);
-+      freq = dev_pm_opp_get_freq(opp);
-+
-+      /*
-+       * Set to idle bin if switching from normal to high bin
-+       * or vice versa. It has been notice that a bug is triggered
-+       * in cache scaling when more than one bin is scaled, to fix
-+       * this we first need to transition to the base rate and then
-+       * to target rate
-+       */
-+      if (likely(freq != idle_freq && old_freq != idle_freq)) {
-+              ret = clk_set_rate(clk, idle_freq);
-+              if (ret)
-+                      return ret;
-+      }
-+
-+      return clk_set_rate(clk, freq);
-+};
-+
-+static int krait_cache_get_cur_freq(struct device *dev, unsigned long *freq)
-+{
-+      struct krait_cache_data *data = dev_get_drvdata(dev);
-+
-+      *freq = clk_get_rate(data->clk);
-+
-+      return 0;
-+};
-+
-+static int krait_cache_target(struct device *dev, unsigned long *freq,
-+                            u32 flags)
-+{
-+      struct dev_pm_opp *opp;
-+
-+      opp = dev_pm_opp_find_freq_ceil(dev, freq);
-+      if (unlikely(IS_ERR(opp)))
-+              return PTR_ERR(opp);
-+
-+      dev_pm_opp_put(opp);
-+
-+      return dev_pm_opp_set_rate(dev, *freq);
-+};
-+
-+static int krait_cache_get_dev_status(struct device *dev,
-+                                    struct devfreq_dev_status *stat)
-+{
-+      struct krait_cache_data *data = dev_get_drvdata(dev);
-+
-+      stat->busy_time = 0;
-+      stat->total_time = 0;
-+      stat->current_frequency = clk_get_rate(data->clk);
-+
-+      return 0;
-+};
-+
-+static struct devfreq_dev_profile krait_cache_devfreq_profile = {
-+      .target = krait_cache_target,
-+      .get_dev_status = krait_cache_get_dev_status,
-+      .get_cur_freq = krait_cache_get_cur_freq
-+};
-+
-+static struct devfreq_passive_data devfreq_gov_data = {
-+      .parent_type = CPUFREQ_PARENT_DEV,
-+};
-+
-+static int krait_cache_probe(struct platform_device *pdev)
-+{
-+      struct dev_pm_opp_config config = { };
-+      struct device *dev = &pdev->dev;
-+      struct krait_cache_data *data;
-+      struct devfreq *devfreq;
-+      struct dev_pm_opp *opp;
-+      struct clk *clk;
-+      int ret, token;
-+
-+      data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
-+      if (!data)
-+              return -ENOMEM;
-+
-+      clk = devm_clk_get(dev, "l2");
-+      if (IS_ERR(clk))
-+              return PTR_ERR(clk);
-+
-+      config.regulator_names = (const char *[]){ "l2", NULL };
-+      config.clk_names = (const char *[]){ "l2", NULL };
-+      config.config_clks = krait_cache_config_clk;
-+
-+      token = dev_pm_opp_set_config(dev, &config);
-+      if (token < 0)
-+              return token;
-+
-+      ret = devm_pm_opp_of_add_table(dev);
-+      if (ret)
-+              goto free_opp;
-+
-+      opp = dev_pm_opp_find_freq_ceil(dev, &data->idle_freq);
-+      if (IS_ERR(opp)) {
-+              ret = PTR_ERR(opp);
-+              goto free_opp;
-+      }
-+      dev_pm_opp_put(opp);
-+
-+      data->token = token;
-+      data->clk = clk;
-+      dev_set_drvdata(dev, data);
-+      devfreq = devm_devfreq_add_device(dev, &krait_cache_devfreq_profile,
-+                                        DEVFREQ_GOV_PASSIVE, &devfreq_gov_data);
-+      if (IS_ERR(devfreq)) {
-+              ret = PTR_ERR(devfreq);
-+              goto free_opp;
-+      }
-+
-+      return 0;
-+
-+free_opp:
-+      dev_pm_opp_clear_config(token);
-+      return ret;
-+};
-+
-+static int krait_cache_remove(struct platform_device *pdev)
-+{
-+      struct krait_cache_data *data = dev_get_drvdata(&pdev->dev);
-+
-+      dev_pm_opp_clear_config(data->token);
-+
-+      return 0;
-+};
-+
-+static const struct of_device_id krait_cache_match_table[] = {
-+      { .compatible = "qcom,krait-cache" },
-+      {}
-+};
-+
-+static struct platform_driver krait_cache_driver = {
-+      .probe          = krait_cache_probe,
-+      .remove         = krait_cache_remove,
-+      .driver         = {
-+              .name   = "krait-cache-scaling",
-+              .of_match_table = krait_cache_match_table,
-+      },
-+};
-+module_platform_driver(krait_cache_driver);
-+
-+MODULE_DESCRIPTION("Krait CPU Cache Scaling driver");
-+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
-+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/ipq806x/patches-6.1/114-02-ARM-dts-qcom-add-krait-cache-compatible-for-ipq806x-.patch b/target/linux/ipq806x/patches-6.1/114-02-ARM-dts-qcom-add-krait-cache-compatible-for-ipq806x-.patch
deleted file mode 100644 (file)
index 45f05dd..0000000
+++ /dev/null
@@ -1,50 +0,0 @@
-From ef124ad0ff8abfbf4ebe3fe6d7dcef4541dec13a Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Thu, 16 Jun 2022 18:39:21 +0200
-Subject: [PATCH] ARM: dts: qcom: add krait-cache compatible for ipq806x dtsi
-
-Add qcom,krait-cache compatible to enable cache devfreq driver for
-ipq806x SoC and move the L2 node to the soc node to make the devfreq
-driver correctly probe.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- arch/arm/boot/dts/qcom-ipq8064.dtsi | 22 +++++++++++-----------
- 1 file changed, 11 insertions(+), 11 deletions(-)
-
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -69,16 +69,6 @@
-                               min-residency-us = <3000>;
-                       };
-               };
--
--              L2: l2-cache {
--                      compatible = "cache";
--                      cache-level = <2>;
--                      qcom,saw = <&saw_l2>;
--
--                      clocks = <&kraitcc 4>;
--                      clock-names = "l2";
--                      operating-points-v2 = <&opp_table_l2>;
--              };
-       };
-       opp_table_l2: opp_table_l2 {
-@@ -1409,6 +1399,16 @@
-                       #reset-cells = <1>;
-               };
-+              L2: l2-cache {
-+                      compatible = "cache", "qcom,krait-cache";
-+                      cache-level = <2>;
-+                      qcom,saw = <&saw_l2>;
-+
-+                      clocks = <&kraitcc 4>;
-+                      clock-names = "l2";
-+                      operating-points-v2 = <&opp_table_l2>;
-+              };
-+
-               lpass@28100000 {
-                       compatible = "qcom,lpass-cpu";
-                       status = "disabled";
diff --git a/target/linux/ipq806x/patches-6.1/115-01-devfreq-add-ipq806x-fabric-scaling-driver.patch b/target/linux/ipq806x/patches-6.1/115-01-devfreq-add-ipq806x-fabric-scaling-driver.patch
deleted file mode 100644 (file)
index c9cd3eb..0000000
+++ /dev/null
@@ -1,203 +0,0 @@
-From 13f075999935bb696dbab63243923179f06fa05e Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Thu, 16 Jun 2022 19:56:08 +0200
-Subject: [PATCH 3/4] devfreq: add ipq806x fabric scaling driver
-
-Add ipq806x fabric scaling driver using the devfreq passive governor.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- drivers/devfreq/Kconfig               |  11 ++
- drivers/devfreq/Makefile              |   1 +
- drivers/devfreq/ipq806x-fab-devfreq.c | 155 ++++++++++++++++++++++++++
- 3 files changed, 167 insertions(+)
- create mode 100644 drivers/devfreq/ipq806x-fab-devfreq.c
-
---- a/drivers/devfreq/Kconfig
-+++ b/drivers/devfreq/Kconfig
-@@ -162,6 +162,17 @@ config ARM_KRAIT_CACHE_DEVFREQ
-         based on the max frequency across all core and the range set in the device
-         dts. If provided this scale also the regulator attached to the l2 cache.
-+config ARM_IPQ806X_FAB_DEVFREQ
-+      tristate "Scaling support for ipq806x Soc Fabric"
-+      depends on ARCH_QCOM || COMPILE_TEST
-+      select DEVFREQ_GOV_PASSIVE
-+      help
-+        This adds the DEVFREQ driver for the ipq806x Soc Fabric.
-+
-+        The driver register with the cpufreq notifier and find the right frequency
-+        based on the max frequency across all core and the range set in the device
-+        dts.
-+
- source "drivers/devfreq/event/Kconfig"
- endif # PM_DEVFREQ
---- a/drivers/devfreq/Makefile
-+++ b/drivers/devfreq/Makefile
-@@ -16,6 +16,7 @@ obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) +=
- obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ)      += sun8i-a33-mbus.o
- obj-$(CONFIG_ARM_TEGRA_DEVFREQ)               += tegra30-devfreq.o
- obj-$(CONFIG_ARM_KRAIT_CACHE_DEVFREQ) += krait-cache-devfreq.o
-+obj-$(CONFIG_ARM_IPQ806X_FAB_DEVFREQ) += ipq806x-fab-devfreq.o
- # DEVFREQ Event Drivers
- obj-$(CONFIG_PM_DEVFREQ_EVENT)                += event/
---- /dev/null
-+++ b/drivers/devfreq/ipq806x-fab-devfreq.c
-@@ -0,0 +1,155 @@
-+// SPDX-License-Identifier: GPL-2.0
-+
-+#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/cpufreq.h>
-+#include <linux/devfreq.h>
-+#include <linux/of.h>
-+#include <linux/platform_device.h>
-+#include <linux/clk.h>
-+#include <linux/slab.h>
-+#include <linux/pm_opp.h>
-+
-+#include "governor.h"
-+
-+struct ipq806x_fab_data {
-+      struct clk *fab_clk;
-+      struct clk *ddr_clk;
-+};
-+
-+static int ipq806x_fab_get_cur_freq(struct device *dev, unsigned long *freq)
-+{
-+      struct ipq806x_fab_data *data = dev_get_drvdata(dev);
-+
-+      *freq = clk_get_rate(data->fab_clk);
-+
-+      return 0;
-+};
-+
-+static int ipq806x_fab_target(struct device *dev, unsigned long *freq,
-+                            u32 flags)
-+{
-+      struct ipq806x_fab_data *data = dev_get_drvdata(dev);
-+      struct dev_pm_opp *opp;
-+      int ret;
-+
-+      opp = dev_pm_opp_find_freq_ceil(dev, freq);
-+      if (unlikely(IS_ERR(opp)))
-+              return PTR_ERR(opp);
-+
-+      dev_pm_opp_put(opp);
-+
-+      ret = clk_set_rate(data->fab_clk, *freq);
-+      if (ret)
-+              return ret;
-+
-+      return clk_set_rate(data->ddr_clk, *freq);
-+};
-+
-+static int ipq806x_fab_get_dev_status(struct device *dev,
-+                                    struct devfreq_dev_status *stat)
-+{
-+      struct ipq806x_fab_data *data = dev_get_drvdata(dev);
-+
-+      stat->busy_time = 0;
-+      stat->total_time = 0;
-+      stat->current_frequency = clk_get_rate(data->fab_clk);
-+
-+      return 0;
-+};
-+
-+static struct devfreq_dev_profile ipq806x_fab_devfreq_profile = {
-+      .target = ipq806x_fab_target,
-+      .get_dev_status = ipq806x_fab_get_dev_status,
-+      .get_cur_freq = ipq806x_fab_get_cur_freq
-+};
-+
-+static struct devfreq_passive_data devfreq_gov_data = {
-+      .parent_type = CPUFREQ_PARENT_DEV,
-+};
-+
-+static int ipq806x_fab_probe(struct platform_device *pdev)
-+{
-+      struct device *dev = &pdev->dev;
-+      struct ipq806x_fab_data *data;
-+      struct devfreq *devfreq;
-+      struct clk *clk;
-+      int ret;
-+
-+      data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
-+      if (!data)
-+              return -ENOMEM;
-+
-+      clk = devm_clk_get(dev, "apps-fab-clk");
-+      if (IS_ERR(clk)) {
-+              dev_err_probe(dev, PTR_ERR(clk), "failed to get apps fab clk\n");
-+              return PTR_ERR(clk);
-+      }
-+
-+      clk_prepare_enable(clk);
-+      data->fab_clk = clk;
-+
-+      clk = devm_clk_get(dev, "ddr-fab-clk");
-+      if (IS_ERR(clk)) {
-+              dev_err_probe(dev, PTR_ERR(clk), "failed to get ddr fab clk\n");
-+              goto err_ddr;
-+      }
-+
-+      clk_prepare_enable(clk);
-+      data->ddr_clk = clk;
-+
-+      ret = dev_pm_opp_of_add_table(dev);
-+      if (ret) {
-+              dev_err(dev, "failed to parse fab freq thresholds\n");
-+              return ret;
-+      }
-+
-+      dev_set_drvdata(dev, data);
-+
-+      devfreq = devm_devfreq_add_device(&pdev->dev, &ipq806x_fab_devfreq_profile,
-+                                        DEVFREQ_GOV_PASSIVE, &devfreq_gov_data);
-+      if (IS_ERR(devfreq))
-+              dev_pm_opp_remove_table(dev);
-+
-+      return PTR_ERR_OR_ZERO(devfreq);
-+
-+err_ddr:
-+      clk_unprepare(data->fab_clk);
-+      clk_put(data->fab_clk);
-+      return PTR_ERR(clk);
-+};
-+
-+static int ipq806x_fab_remove(struct platform_device *pdev)
-+{
-+      struct ipq806x_fab_data *data = dev_get_drvdata(&pdev->dev);
-+
-+      clk_unprepare(data->fab_clk);
-+      clk_put(data->fab_clk);
-+
-+      clk_unprepare(data->ddr_clk);
-+      clk_put(data->ddr_clk);
-+
-+      dev_pm_opp_remove_table(&pdev->dev);
-+
-+      return 0;
-+};
-+
-+static const struct of_device_id ipq806x_fab_match_table[] = {
-+      { .compatible = "qcom,fab-scaling" },
-+      {}
-+};
-+
-+static struct platform_driver ipq806x_fab_driver = {
-+      .probe          = ipq806x_fab_probe,
-+      .remove         = ipq806x_fab_remove,
-+      .driver         = {
-+              .name   = "ipq806x-fab-scaling",
-+              .of_match_table = ipq806x_fab_match_table,
-+      },
-+};
-+module_platform_driver(ipq806x_fab_driver);
-+
-+MODULE_DESCRIPTION("ipq806x Fab Scaling driver");
-+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
-+MODULE_LICENSE("GPL v2");
diff --git a/target/linux/ipq806x/patches-6.1/115-02-ARM-dts-qcom-add-fab-scaling-node-for-ipq806x.patch b/target/linux/ipq806x/patches-6.1/115-02-ARM-dts-qcom-add-fab-scaling-node-for-ipq806x.patch
deleted file mode 100644 (file)
index 24e0ecf..0000000
+++ /dev/null
@@ -1,48 +0,0 @@
-From c3573f0907dadb0a6e9933aae2a46a489abcbd48 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Thu, 16 Jun 2022 20:03:05 +0200
-Subject: [PATCH 4/4] ARM: dts: qcom: add fab scaling node for ipq806x
-
-Add fabric scaling node for ipq806x to correctly scale apps and ddr
-fabric clk.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- arch/arm/boot/dts/qcom-ipq8064.dtsi | 19 +++++++++++++++++++
- 1 file changed, 19 insertions(+)
-
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -170,6 +170,18 @@
-               };
-       };
-+      opp_table_fab: opp_table_fab {
-+              compatible = "operating-points-v2";
-+
-+              opp-533000000 {
-+                      opp-hz = /bits/ 64 <533000000>;
-+              };
-+
-+              opp-400000000 {
-+                      opp-hz = /bits/ 64 <400000000>;
-+              };
-+      };
-+
-       thermal-zones {
-               sensor0-thermal {
-                       polling-delay-passive = <0>;
-@@ -1409,6 +1421,13 @@
-                       operating-points-v2 = <&opp_table_l2>;
-               };
-+              fab-scaling {
-+                      compatible = "qcom,fab-scaling";
-+                      clocks = <&rpmcc RPM_APPS_FABRIC_A_CLK>, <&rpmcc RPM_EBI1_A_CLK>;
-+                      clock-names = "apps-fab-clk", "ddr-fab-clk";
-+                      operating-points-v2 = <&opp_table_fab>;
-+              };
-+
-               lpass@28100000 {
-                       compatible = "qcom,lpass-cpu";
-                       status = "disabled";
diff --git a/target/linux/ipq806x/patches-6.1/122-01-clk-qcom-krait-cc-handle-qsb-clock-defined-in-DTS.patch b/target/linux/ipq806x/patches-6.1/122-01-clk-qcom-krait-cc-handle-qsb-clock-defined-in-DTS.patch
deleted file mode 100644 (file)
index c30c245..0000000
+++ /dev/null
@@ -1,47 +0,0 @@
-From 666c1b745e93ccddde841d5057c33f97b29a316a Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Thu, 15 Sep 2022 02:19:28 +0200
-Subject: [PATCH 3/9] clk: qcom: krait-cc: handle qsb clock defined in DTS
-
-qsb fixed clk may be defined in DTS and correctly passed in the clocks
-list. Add related code to handle this and modify the logic to
-dynamically read qsb clock frequency.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- drivers/clk/qcom/krait-cc.c | 14 +++++++++++---
- 1 file changed, 11 insertions(+), 3 deletions(-)
-
---- a/drivers/clk/qcom/krait-cc.c
-+++ b/drivers/clk/qcom/krait-cc.c
-@@ -348,7 +348,7 @@ static int krait_cc_probe(struct platfor
- {
-       struct device *dev = &pdev->dev;
-       const struct of_device_id *id;
--      unsigned long cur_rate, aux_rate;
-+      unsigned long cur_rate, aux_rate, qsb_rate;
-       int cpu;
-       struct clk_hw *mux, *l2_pri_mux;
-       struct clk *clk, **clks;
-@@ -357,11 +357,19 @@ static int krait_cc_probe(struct platfor
-       if (!id)
-               return -ENODEV;
--      /* Rate is 1 because 0 causes problems for __clk_mux_determine_rate */
--      clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1);
-+      /*
-+       * Per Documentation qsb should be provided from DTS.
-+       * To address old implementation, register the fixed clock anyway.
-+       * Rate is 1 because 0 causes problems for __clk_mux_determine_rate
-+       */
-+      clk = clk_get(dev, "qsb");
-+      if (IS_ERR(clk))
-+              clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1);
-       if (IS_ERR(clk))
-               return PTR_ERR(clk);
-+      qsb_rate = clk_get_rate(clk);
-+
-       if (!id->data) {
-               clk = clk_register_fixed_factor(dev, "acpu_aux",
-                                               "gpll0_vote", 0, 1, 2);
diff --git a/target/linux/ipq806x/patches-6.1/122-02-clk-qcom-krait-cc-register-REAL-qsb-fixed-clock.patch b/target/linux/ipq806x/patches-6.1/122-02-clk-qcom-krait-cc-register-REAL-qsb-fixed-clock.patch
deleted file mode 100644 (file)
index e2f78f7..0000000
+++ /dev/null
@@ -1,36 +0,0 @@
-From fca6f185a9d9ef0892a719bc6da955b22d326ec7 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Thu, 15 Sep 2022 02:24:33 +0200
-Subject: [PATCH 4/9] clk: qcom: krait-cc: register REAL qsb fixed clock
-
-With some tools it was discovered the real frequency of the qsb fixed
-clock. While not 100% correct it's still better than using 1 as a dummy
-frequency.
-Correctly register the qsb fixed clock with the frequency of 225 MHz
-instead of 1.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- drivers/clk/qcom/krait-cc.c | 8 +++++---
- 1 file changed, 5 insertions(+), 3 deletions(-)
-
---- a/drivers/clk/qcom/krait-cc.c
-+++ b/drivers/clk/qcom/krait-cc.c
-@@ -25,6 +25,8 @@ enum {
-       clks_max,
- };
-+#define QSB_RATE      2250000000
-+
- static unsigned int sec_mux_map[] = {
-       2,
-       0,
-@@ -364,7 +366,7 @@ static int krait_cc_probe(struct platfor
-        */
-       clk = clk_get(dev, "qsb");
-       if (IS_ERR(clk))
--              clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1);
-+              clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, QSB_RATE);
-       if (IS_ERR(clk))
-               return PTR_ERR(clk);
diff --git a/target/linux/ipq806x/patches-6.1/122-03-clk-qcom-krait-cc-drop-pr_info-and-use-dev_info.patch b/target/linux/ipq806x/patches-6.1/122-03-clk-qcom-krait-cc-drop-pr_info-and-use-dev_info.patch
deleted file mode 100644 (file)
index d95a63f..0000000
+++ /dev/null
@@ -1,44 +0,0 @@
-From 2399d181557d94ae9a2686926cd25768f132e4b4 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Fri, 18 Mar 2022 16:12:14 +0100
-Subject: [PATCH 7/9] clk: qcom: krait-cc: drop pr_info and use dev_info
-
-Replace pr_info() with dev_info() to provide better diagnostics.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- drivers/clk/qcom/krait-cc.c | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
---- a/drivers/clk/qcom/krait-cc.c
-+++ b/drivers/clk/qcom/krait-cc.c
-@@ -423,25 +423,25 @@ static int krait_cc_probe(struct platfor
-       cur_rate = clk_get_rate(clks[l2_mux]);
-       aux_rate = 384000000;
-       if (cur_rate < aux_rate) {
--              pr_info("L2 @ Undefined rate. Forcing new rate.\n");
-+              dev_info(dev, "L2 @ Undefined rate. Forcing new rate.\n");
-               cur_rate = aux_rate;
-       }
-       clk_set_rate(clks[l2_mux], aux_rate);
-       clk_set_rate(clks[l2_mux], 2);
-       clk_set_rate(clks[l2_mux], cur_rate);
--      pr_info("L2 @ %lu KHz\n", clk_get_rate(clks[l2_mux]) / 1000);
-+      dev_info(dev, "L2 @ %lu KHz\n", clk_get_rate(clks[l2_mux]) / 1000);
-       for_each_possible_cpu(cpu) {
-               clk = clks[cpu];
-               cur_rate = clk_get_rate(clk);
-               if (cur_rate < aux_rate) {
--                      pr_info("CPU%d @ Undefined rate. Forcing new rate.\n", cpu);
-+                      dev_info(dev, "CPU%d @ Undefined rate. Forcing new rate.\n", cpu);
-                       cur_rate = aux_rate;
-               }
-               clk_set_rate(clk, aux_rate);
-               clk_set_rate(clk, 2);
-               clk_set_rate(clk, cur_rate);
--              pr_info("CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000);
-+              dev_info(dev, "CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000);
-       }
-       of_clk_add_provider(dev->of_node, krait_of_get, clks);
diff --git a/target/linux/ipq806x/patches-6.1/122-04-clk-qcom-krait-cc-rework-mux-reset-logic-and-reset-h.patch b/target/linux/ipq806x/patches-6.1/122-04-clk-qcom-krait-cc-rework-mux-reset-logic-and-reset-h.patch
deleted file mode 100644 (file)
index 8f88e06..0000000
+++ /dev/null
@@ -1,88 +0,0 @@
-From 6a77cf3f5f95ec0058e1b4d1ada018748cb0b83b Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Thu, 15 Sep 2022 03:33:13 +0200
-Subject: [PATCH 9/9] clk: qcom: krait-cc: rework mux reset logic and reset
- hfpll
-
-Rework and clean mux reset logic.
-Compact it to a for loop to handle both CPU and L2 in one place.
-Move hardcoded aux_rate to define and add a new hfpll_rate value to
-reset hfpll settings.
-Change logic to now reset the hfpll to the lowest value of 600 Mhz and
-then restoring the previous frequency. This permits to reset the hfpll if
-the primary mux was set to source out of the secondary mux.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- drivers/clk/qcom/krait-cc.c | 50 +++++++++++++++++--------------------
- 1 file changed, 23 insertions(+), 27 deletions(-)
-
---- a/drivers/clk/qcom/krait-cc.c
-+++ b/drivers/clk/qcom/krait-cc.c
-@@ -25,7 +25,9 @@ enum {
-       clks_max,
- };
--#define QSB_RATE      2250000000
-+#define QSB_RATE      225000000
-+#define AUX_RATE      384000000
-+#define HFPLL_RATE    600000000
- static unsigned int sec_mux_map[] = {
-       2,
-@@ -350,7 +352,7 @@ static int krait_cc_probe(struct platfor
- {
-       struct device *dev = &pdev->dev;
-       const struct of_device_id *id;
--      unsigned long cur_rate, aux_rate, qsb_rate;
-+      unsigned long cur_rate, qsb_rate;
-       int cpu;
-       struct clk_hw *mux, *l2_pri_mux;
-       struct clk *clk, **clks;
-@@ -420,28 +422,29 @@ static int krait_cc_probe(struct platfor
-        * two different rates to force a HFPLL reinit under all
-        * circumstances.
-        */
--      cur_rate = clk_get_rate(clks[l2_mux]);
--      aux_rate = 384000000;
--      if (cur_rate < aux_rate) {
--              dev_info(dev, "L2 @ Undefined rate. Forcing new rate.\n");
--              cur_rate = aux_rate;
--      }
--      clk_set_rate(clks[l2_mux], aux_rate);
--      clk_set_rate(clks[l2_mux], 2);
--      clk_set_rate(clks[l2_mux], cur_rate);
--      dev_info(dev, "L2 @ %lu KHz\n", clk_get_rate(clks[l2_mux]) / 1000);
--      for_each_possible_cpu(cpu) {
-+      for (cpu = 0; cpu < 5; cpu++) {
-+              const char *l2_s = "L2";
-+              char cpu_s[5];
-+
-               clk = clks[cpu];
-+              if (!clk)
-+                      continue;
-+
-+              if (cpu < 4)
-+                      snprintf(cpu_s, 5, "CPU%d", cpu);
-+
-               cur_rate = clk_get_rate(clk);
--              if (cur_rate < aux_rate) {
--                      dev_info(dev, "CPU%d @ Undefined rate. Forcing new rate.\n", cpu);
--                      cur_rate = aux_rate;
-+              if (cur_rate < AUX_RATE) {
-+                      dev_info(dev, "%s @ Undefined rate. Forcing new rate.\n",
-+                               cpu < 4 ? cpu_s : l2_s);
-+                      cur_rate = AUX_RATE;
-               }
--              clk_set_rate(clk, aux_rate);
--              clk_set_rate(clk, 2);
-+              clk_set_rate(clk, AUX_RATE);
-+              clk_set_rate(clk, HFPLL_RATE);
-               clk_set_rate(clk, cur_rate);
--              dev_info(dev, "CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000);
-+              dev_info(dev, "%s @ %lu KHz\n", cpu < 4 ? cpu_s : l2_s,
-+                       clk_get_rate(clk) / 1000);
-       }
-       of_clk_add_provider(dev->of_node, krait_of_get, clks);
diff --git a/target/linux/ipq806x/patches-6.1/122-05-clk-qcom-clk-krait-generilize-div-functions.patch b/target/linux/ipq806x/patches-6.1/122-05-clk-qcom-clk-krait-generilize-div-functions.patch
deleted file mode 100644 (file)
index a7c0f04..0000000
+++ /dev/null
@@ -1,156 +0,0 @@
-From 908c361b3c3a139eb3e6a798cb620a6da7514d5c Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Fri, 23 Sep 2022 19:05:39 +0200
-Subject: [PATCH 2/4] clk: qcom: clk-krait: generilize div functions
-
-Generilize div functions and remove hardcode to a divisor of 2.
-This is just a cleanup and permit to make it more clear the settings of
-the devisor when used by the krait-cc driver.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- drivers/clk/qcom/clk-krait.c | 57 ++++++++++++++++++++----------------
- drivers/clk/qcom/clk-krait.h | 11 ++++---
- drivers/clk/qcom/krait-cc.c  |  7 +++--
- 3 files changed, 42 insertions(+), 33 deletions(-)
-
---- a/drivers/clk/qcom/clk-krait.c
-+++ b/drivers/clk/qcom/clk-krait.c
-@@ -97,53 +97,58 @@ const struct clk_ops krait_mux_clk_ops =
- EXPORT_SYMBOL_GPL(krait_mux_clk_ops);
- /* The divider can divide by 2, 4, 6 and 8. But we only really need div-2. */
--static long krait_div2_round_rate(struct clk_hw *hw, unsigned long rate,
-+static long krait_div_round_rate(struct clk_hw *hw, unsigned long rate,
-                                 unsigned long *parent_rate)
- {
--      *parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), rate * 2);
--      return DIV_ROUND_UP(*parent_rate, 2);
-+      struct krait_div_clk *d = to_krait_div_clk(hw);
-+
-+      *parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
-+                                       rate * d->divisor);
-+
-+      return DIV_ROUND_UP(*parent_rate, d->divisor);
- }
--static int krait_div2_set_rate(struct clk_hw *hw, unsigned long rate,
-+static int krait_div_set_rate(struct clk_hw *hw, unsigned long rate,
-                              unsigned long parent_rate)
- {
--      struct krait_div2_clk *d = to_krait_div2_clk(hw);
-+      struct krait_div_clk *d = to_krait_div_clk(hw);
-+      u8 div_val = krait_div_to_val(d->divisor);
-       unsigned long flags;
--      u32 val;
--      u32 mask = BIT(d->width) - 1;
--
--      if (d->lpl)
--              mask = mask << (d->shift + LPL_SHIFT) | mask << d->shift;
--      else
--              mask <<= d->shift;
-+      u32 regval;
-       spin_lock_irqsave(&krait_clock_reg_lock, flags);
--      val = krait_get_l2_indirect_reg(d->offset);
--      val &= ~mask;
--      krait_set_l2_indirect_reg(d->offset, val);
-+      regval = krait_get_l2_indirect_reg(d->offset);
-+
-+      regval &= ~(d->mask << d->shift);
-+      regval |= (div_val & d->mask) << d->shift;
-+
-+      if (d->lpl) {
-+              regval &= ~(d->mask << (d->shift + LPL_SHIFT));
-+              regval |= (div_val & d->mask) << (d->shift + LPL_SHIFT);
-+      }
-+
-+      krait_set_l2_indirect_reg(d->offset, regval);
-       spin_unlock_irqrestore(&krait_clock_reg_lock, flags);
-       return 0;
- }
- static unsigned long
--krait_div2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
-+krait_div_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
- {
--      struct krait_div2_clk *d = to_krait_div2_clk(hw);
--      u32 mask = BIT(d->width) - 1;
-+      struct krait_div_clk *d = to_krait_div_clk(hw);
-       u32 div;
-       div = krait_get_l2_indirect_reg(d->offset);
-       div >>= d->shift;
--      div &= mask;
--      div = (div + 1) * 2;
-+      div &= d->mask;
--      return DIV_ROUND_UP(parent_rate, div);
-+      return DIV_ROUND_UP(parent_rate, krait_val_to_div(div));
- }
--const struct clk_ops krait_div2_clk_ops = {
--      .round_rate = krait_div2_round_rate,
--      .set_rate = krait_div2_set_rate,
--      .recalc_rate = krait_div2_recalc_rate,
-+const struct clk_ops krait_div_clk_ops = {
-+      .round_rate = krait_div_round_rate,
-+      .set_rate = krait_div_set_rate,
-+      .recalc_rate = krait_div_recalc_rate,
- };
--EXPORT_SYMBOL_GPL(krait_div2_clk_ops);
-+EXPORT_SYMBOL_GPL(krait_div_clk_ops);
---- a/drivers/clk/qcom/clk-krait.h
-+++ b/drivers/clk/qcom/clk-krait.h
-@@ -25,17 +25,20 @@ struct krait_mux_clk {
- extern const struct clk_ops krait_mux_clk_ops;
--struct krait_div2_clk {
-+struct krait_div_clk {
-       u32             offset;
--      u8              width;
-+      u32             mask;
-+      u8              divisor;
-       u32             shift;
-       bool            lpl;
-       struct clk_hw   hw;
- };
--#define to_krait_div2_clk(_hw) container_of(_hw, struct krait_div2_clk, hw)
-+#define to_krait_div_clk(_hw) container_of(_hw, struct krait_div_clk, hw)
-+#define krait_div_to_val(_div)                ((_div) / 2) - 1
-+#define krait_val_to_div(_val)                ((_val) + 1) * 2
--extern const struct clk_ops krait_div2_clk_ops;
-+extern const struct clk_ops krait_div_clk_ops;
- #endif
---- a/drivers/clk/qcom/krait-cc.c
-+++ b/drivers/clk/qcom/krait-cc.c
-@@ -86,11 +86,11 @@ static int krait_notifier_register(struc
- static struct clk_hw *
- krait_add_div(struct device *dev, int id, const char *s, unsigned int offset)
- {
--      struct krait_div2_clk *div;
-+      struct krait_div_clk *div;
-       static struct clk_parent_data p_data[1];
-       struct clk_init_data init = {
-               .num_parents = ARRAY_SIZE(p_data),
--              .ops = &krait_div2_clk_ops,
-+              .ops = &krait_div_clk_ops,
-               .flags = CLK_SET_RATE_PARENT,
-       };
-       struct clk_hw *clk;
-@@ -101,7 +101,8 @@ krait_add_div(struct device *dev, int id
-       if (!div)
-               return ERR_PTR(-ENOMEM);
--      div->width = 2;
-+      div->mask = 0x3;
-+      div->divisor = 2;
-       div->shift = 6;
-       div->lpl = id >= 0;
-       div->offset = offset;
diff --git a/target/linux/ipq806x/patches-6.1/123-clk-qcom-gcc-ipq806x-remove-cc_register_board-for.patch b/target/linux/ipq806x/patches-6.1/123-clk-qcom-gcc-ipq806x-remove-cc_register_board-for.patch
deleted file mode 100644 (file)
index 0df29a0..0000000
+++ /dev/null
@@ -1,31 +0,0 @@
-From ac84ac819a2e8fd3d87122b452c502a386c54437 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Tue, 5 Jul 2022 18:30:18 +0200
-Subject: [PATCH v2 4/4] clk: qcom: gcc-ipq806x: remove cc_register_board for
- pxo and cxo
-
-Now that these clock are defined as fixed clk in dts, we can drop the
-register_board_clk for cxo_board and pxo_board in gcc_ipq806x_probe.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- drivers/clk/qcom/gcc-ipq806x.c | 8 --------
- 1 file changed, 8 deletions(-)
-
---- a/drivers/clk/qcom/gcc-ipq806x.c
-+++ b/drivers/clk/qcom/gcc-ipq806x.c
-@@ -3386,14 +3386,6 @@ static int gcc_ipq806x_probe(struct plat
-       struct regmap *regmap;
-       int ret;
--      ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 25000000);
--      if (ret)
--              return ret;
--
--      ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 25000000);
--      if (ret)
--              return ret;
--
-       if (of_machine_is_compatible("qcom,ipq8065")) {
-               ubi32_core1_src_clk.freq_tbl = clk_tbl_nss_ipq8065;
-               ubi32_core2_src_clk.freq_tbl = clk_tbl_nss_ipq8065;
diff --git a/target/linux/ipq806x/patches-6.1/850-soc-add-qualcomm-syscon.patch b/target/linux/ipq806x/patches-6.1/850-soc-add-qualcomm-syscon.patch
deleted file mode 100644 (file)
index 397c448..0000000
+++ /dev/null
@@ -1,121 +0,0 @@
-From: Christian Lamparter <chunkeey@googlemail.com>
-Subject: SoC: add qualcomm syscon
---- a/drivers/soc/qcom/Makefile
-+++ b/drivers/soc/qcom/Makefile
-@@ -23,6 +23,7 @@ obj-$(CONFIG_QCOM_SOCINFO)   += socinfo.o
- obj-$(CONFIG_QCOM_SPM)                += spm.o
- obj-$(CONFIG_QCOM_STATS)      += qcom_stats.o
- obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o
-+obj-$(CONFIG_QCOM_TCSR)        += qcom_tcsr.o
- obj-$(CONFIG_QCOM_APR) += apr.o
- obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o
- obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o
---- a/drivers/soc/qcom/Kconfig
-+++ b/drivers/soc/qcom/Kconfig
-@@ -213,6 +213,13 @@ config QCOM_STATS
-         various SoC level low power modes statistics and export to debugfs
-         interface.
-+config QCOM_TCSR
-+      tristate "QCOM Top Control and Status Registers"
-+      depends on ARCH_QCOM
-+      help
-+        Say y here to enable TCSR support.  The TCSR provides control
-+        functions for various peripherals.
-+
- config QCOM_WCNSS_CTRL
-       tristate "Qualcomm WCNSS control driver"
-       depends on ARCH_QCOM || COMPILE_TEST
---- /dev/null
-+++ b/drivers/soc/qcom/qcom_tcsr.c
-@@ -0,0 +1,64 @@
-+/*
-+ * Copyright (c) 2014, The Linux foundation. All rights reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License rev 2 and
-+ * only rev 2 as published by the free Software foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
-+#include <linux/clk.h>
-+#include <linux/err.h>
-+#include <linux/io.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/of_platform.h>
-+#include <linux/platform_device.h>
-+
-+#define TCSR_USB_PORT_SEL     0xb0
-+
-+static int tcsr_probe(struct platform_device *pdev)
-+{
-+      struct resource *res;
-+      const struct device_node *node = pdev->dev.of_node;
-+      void __iomem *base;
-+      u32 val;
-+
-+      res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+      base = devm_ioremap_resource(&pdev->dev, res);
-+      if (IS_ERR(base))
-+              return PTR_ERR(base);
-+
-+      if (!of_property_read_u32(node, "qcom,usb-ctrl-select", &val)) {
-+              dev_err(&pdev->dev, "setting usb port select = %d\n", val);
-+              writel(val, base + TCSR_USB_PORT_SEL);
-+      }
-+
-+      return 0;
-+}
-+
-+static const struct of_device_id tcsr_dt_match[] = {
-+      { .compatible = "qcom,tcsr", },
-+      { },
-+};
-+
-+MODULE_DEVICE_TABLE(of, tcsr_dt_match);
-+
-+static struct platform_driver tcsr_driver = {
-+      .driver = {
-+              .name           = "tcsr",
-+              .owner          = THIS_MODULE,
-+              .of_match_table = tcsr_dt_match,
-+      },
-+      .probe = tcsr_probe,
-+};
-+
-+module_platform_driver(tcsr_driver);
-+
-+MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
-+MODULE_DESCRIPTION("QCOM TCSR driver");
-+MODULE_LICENSE("GPL v2");
---- /dev/null
-+++ b/include/dt-bindings/soc/qcom,tcsr.h
-@@ -0,0 +1,23 @@
-+/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 and
-+ * only version 2 as published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+#ifndef __DT_BINDINGS_QCOM_TCSR_H
-+#define __DT_BINDINGS_QCOM_TCSR_H
-+
-+#define TCSR_USB_SELECT_USB3_P0               0x1
-+#define TCSR_USB_SELECT_USB3_P1               0x2
-+#define TCSR_USB_SELECT_USB3_DUAL     0x3
-+
-+/* TCSR A/B REG */
-+#define IPQ806X_TCSR_REG_A_ADM_CRCI_MUX_SEL     0
-+#define IPQ806X_TCSR_REG_B_ADM_CRCI_MUX_SEL     1
-+
-+#endif
diff --git a/target/linux/ipq806x/patches-6.1/900-arm-add-cmdline-override.patch b/target/linux/ipq806x/patches-6.1/900-arm-add-cmdline-override.patch
deleted file mode 100644 (file)
index c958354..0000000
+++ /dev/null
@@ -1,37 +0,0 @@
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -1589,6 +1589,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
- endchoice
-+config CMDLINE_OVERRIDE
-+      bool "Use alternative cmdline from device tree"
-+      help
-+        Some bootloaders may have uneditable bootargs. While CMDLINE_FORCE can
-+        be used, this is not a good option for kernels that are shared across
-+        devices. This setting enables using "chosen/cmdline-override" as the
-+        cmdline if it exists in the device tree.
-+
- config CMDLINE
-       string "Default kernel command string"
-       default ""
---- a/drivers/of/fdt.c
-+++ b/drivers/of/fdt.c
-@@ -1187,6 +1187,17 @@ int __init early_init_dt_scan_chosen(cha
-       if (p != NULL && l > 0)
-               strlcat(cmdline, p, min_t(int, strlen(cmdline) + (int)l, COMMAND_LINE_SIZE));
-+    /* CONFIG_CMDLINE_OVERRIDE is used to fallback to a different
-+     * device tree option of chosen/bootargs-override. This is
-+     * helpful on boards where u-boot sets bootargs, and is unable
-+     * to be modified.
-+     */
-+#ifdef CONFIG_CMDLINE_OVERRIDE
-+      p = of_get_flat_dt_prop(node, "bootargs-override", &l);
-+      if (p != NULL && l > 0)
-+              strlcpy(cmdline, p, min((int)l, COMMAND_LINE_SIZE));
-+#endif
-+
- handle_cmdline:
-       /*
-        * CONFIG_CMDLINE is meant to be a default in case nothing else
diff --git a/target/linux/ipq806x/patches-6.1/901-01-ARM-decompressor-support-memory-start-validation-.patch b/target/linux/ipq806x/patches-6.1/901-01-ARM-decompressor-support-memory-start-validation-.patch
deleted file mode 100644 (file)
index 04e2a0c..0000000
+++ /dev/null
@@ -1,75 +0,0 @@
-From 2f86b9b71a11f86e3d850214ab781ebb17d7260e Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Fri, 19 Jan 2024 19:48:30 +0100
-Subject: [PATCH v2 1/2] ARM: decompressor: support memory start validation for
- appended DTB
-
-There is currently a problem with a very specific sets of kernel config
-and AUTO_ZRELADDR.
-
-For the most common case AUTO_ZRELADDR check the PC register and
-calculate the start of the physical memory. Then fdt_check_mem_start is
-called to make sure the detected value makes sense by comparing it with
-what is present in DTB in the memory nodes and if additional fixup are
-required with the use of linux,usable-memory-range in the chosen node to
-hardcode usable memory range in case some reserved space needs to be
-addressed. With the help of this function the right address is
-calculated and the kernel correctly decompress and loads.
-
-Things starts to become problematic when in the mix,
-CONFIG_ARM_APPENDED_DTB is used. This is a particular kernel config is
-used when legacy systems doesn't support passing a DTB directly and a
-DTB is appended at the end of the image.
-
-In such case, fdt_check_mem_start is skipped in AUTO_ZRELADDR iteration
-as the appended DTB can be augumented later with ATAGS passed from the
-bootloader (if CONFIG_ARM_ATAG_DTB_COMPAT is enabled).
-
-The main problem and what this patch address is the fact that
-fdt_check_mem_start is never called later when the appended DTB is
-augumented, hence any fixup and validation is not done making AUTO_ZRELADDR
-detection inconsistent and most of the time wrong.
-
-Add support in head.S for this by checking if AUTO_ZRELADDR is enabled
-and calling fdt_check_mem_start with the appended DTB and the augumented
-values permitting legacy device to provide info in DTB instead of
-disabling AUTO_ZRELADDR and hardcoding the physical address offsets.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
-Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
----
- arch/arm/boot/compressed/head.S | 22 ++++++++++++++++++++++
- 1 file changed, 22 insertions(+)
-
---- a/arch/arm/boot/compressed/head.S
-+++ b/arch/arm/boot/compressed/head.S
-@@ -443,6 +443,28 @@ restart:  adr     r0, LC1
-               add     r6, r6, r5
-               add     r10, r10, r5
-               add     sp, sp, r5
-+
-+#ifdef CONFIG_AUTO_ZRELADDR
-+              /*
-+               * Validate calculated start of physical memory with appended DTB.
-+               * In the first iteration for physical memory start calculation,
-+               * we skipped validating it as it could have been augumented by
-+               * ATAGS stored at an offset from the same start of physical memory.
-+               *
-+               * We now have parsed them and augumented the appended DTB if asked
-+               * so we can finally validate the start of physical memory.
-+               *
-+               * This is needed to apply additional fixup with
-+               * linux,usable-memory-range or to make sure AUTO_ZRELADDR detected
-+               * the correct value.
-+               */
-+              sub     r0, r4, #TEXT_OFFSET    @ revert to base address
-+              mov     r1, r8                  @ use appended DTB
-+              bl      fdt_check_mem_start
-+
-+              /* Determine final kernel image address. */
-+              add     r4, r0, #TEXT_OFFSET
-+#endif
- dtb_check_done:
- #endif
diff --git a/target/linux/ipq806x/patches-6.1/901-02-ARM-decompressor-add-option-to-ignore-MEM-ATAGs.patch b/target/linux/ipq806x/patches-6.1/901-02-ARM-decompressor-add-option-to-ignore-MEM-ATAGs.patch
deleted file mode 100644 (file)
index 2e4c4de..0000000
+++ /dev/null
@@ -1,54 +0,0 @@
-From 781d7cd4c3364e9d38fa12a342c5ad4c7e33a5ba Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Fri, 19 Jan 2024 20:33:10 +0100
-Subject: [PATCH v2 2/2] ARM: decompressor: add option to ignore MEM ATAGs
-
-Some bootloaders can pass broken MEM ATAGs that provide hardcoded
-information about mounted RAM size and physical location.
-Example booloader provide RAM of size 1.7Gb but actual mounted RAM
-size is 512Mb causing kernel panic.
-
-Add option CONFIG_ARM_ATAG_DTB_COMPAT_IGNORE_MEM to ignore these ATAG
-and not augument appended DTB memory node.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Acked-by: Linus Walleij <linus.walleij@linaro.org>
----
- arch/arm/Kconfig                        | 12 ++++++++++++
- arch/arm/boot/compressed/atags_to_fdt.c |  4 ++++
- 2 files changed, 16 insertions(+)
-
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -1570,6 +1570,18 @@ config ARM_ATAG_DTB_COMPAT
-         bootloaders, this option allows zImage to extract the information
-         from the ATAG list and store it at run time into the appended DTB.
-+config ARM_ATAG_DTB_COMPAT_IGNORE_MEM
-+      bool "Ignore MEM ATAG information from bootloader"
-+      depends on ARM_ATAG_DTB_COMPAT
-+      help
-+        Some bootloaders can pass broken MEM ATAGs that provide hardcoded
-+        information about mounted RAM size and physical location.
-+        Example booloader provide RAM of size 1.7Gb but actual mounted RAM
-+        size is 512Mb causing kernel panic.
-+
-+        Enable this option if MEM ATAGs should be ignored and the memory
-+        node in the appended DTB should NOT be augumented.
-+
- choice
-       prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
-       default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
---- a/arch/arm/boot/compressed/atags_to_fdt.c
-+++ b/arch/arm/boot/compressed/atags_to_fdt.c
-@@ -169,6 +169,10 @@ int atags_to_fdt(void *atag_list, void *
-                               setprop_string(fdt, "/chosen", "bootargs",
-                                              atag->u.cmdline.cmdline);
-               } else if (atag->hdr.tag == ATAG_MEM) {
-+                      /* Bootloader MEM ATAG are broken and should be ignored */
-+                      if (IS_ENABLED(CONFIG_ARM_ATAG_DTB_COMPAT_IGNORE_MEM))
-+                              continue;
-+
-                       if (memcount >= sizeof(mem_reg_property)/4)
-                               continue;
-                       if (!atag->u.mem.size)
diff --git a/target/linux/ipq806x/patches-6.1/902-ARM-decompressor-support-for-ATAGs-rootblock-parsing.patch b/target/linux/ipq806x/patches-6.1/902-ARM-decompressor-support-for-ATAGs-rootblock-parsing.patch
deleted file mode 100644 (file)
index 60b80fe..0000000
+++ /dev/null
@@ -1,197 +0,0 @@
-From 13bb6d8dd9138927950a520a288401db82871dc9 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Sun, 21 Jan 2024 23:36:57 +0100
-Subject: [PATCH] ARM: decompressor: support for ATAGs rootblock parsing
-
-The command-line arguments provided by the boot loader will be
-appended to a new device tree property: bootloader-args.
-
-If there is a property "append-rootblock" in DT under /chosen
-and a root= option in bootloaders command line it will be parsed
-and added to DT bootargs with the form: <append-rootblock>XX.
-
-This is usefull in dual boot systems, to get the current root partition
-without afecting the rest of the system.
-
-Signed-off-by: Adrian Panella <ianchi74@outlook.com>
-[ reworked to a cleaner patch ]
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- arch/arm/Kconfig                        |  10 +++
- arch/arm/boot/compressed/atags_to_fdt.c | 102 ++++++++++++++++++++++--
- init/main.c                             |  12 +++
- 3 files changed, 117 insertions(+), 7 deletions(-)
-
---- a/arch/arm/Kconfig
-+++ b/arch/arm/Kconfig
-@@ -1599,6 +1599,16 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
-         The command-line arguments provided by the boot loader will be
-         appended to the the device tree bootargs property.
-+config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
-+      bool "Append rootblock parsing bootloader's kernel arguments"
-+      help
-+        The command-line arguments provided by the boot loader will be
-+        appended to a new device tree property: bootloader-args.
-+
-+        If there is a property "append-rootblock" in DT under /chosen
-+        and a root= option in bootloaders command line it will be parsed
-+        and added to DT bootargs with the form: <append-rootblock>XX.
-+
- endchoice
- config CMDLINE_OVERRIDE
---- a/arch/arm/boot/compressed/atags_to_fdt.c
-+++ b/arch/arm/boot/compressed/atags_to_fdt.c
-@@ -3,7 +3,8 @@
- #include <asm/setup.h>
- #include <libfdt.h>
--#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND)
-+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND) || \
-+      defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
- #define do_extend_cmdline 1
- #else
- #define do_extend_cmdline 0
-@@ -69,6 +70,83 @@ static uint32_t get_cell_size(const void
-       return cell_size;
- }
-+/**
-+ * taken from arch/x86/boot/string.c
-+ * local_strstr - Find the first substring in a %NUL terminated string
-+ * @s1: The string to be searched
-+ * @s2: The string to search for
-+ */
-+static char *local_strstr(const char *s1, const char *s2)
-+{
-+      size_t l1, l2;
-+
-+      l2 = strlen(s2);
-+      if (!l2)
-+              return (char *)s1;
-+      l1 = strlen(s1);
-+      while (l1 >= l2) {
-+              l1--;
-+              if (!memcmp(s1, s2, l2))
-+                      return (char *)s1;
-+              s1++;
-+      }
-+      return NULL;
-+}
-+
-+static char *append_rootblock(char *dest, const char *str, int len, void *fdt)
-+{
-+      char *ptr, *end, *tmp;
-+      const char *root="root=";
-+      const char *find_rootblock;
-+      int i, l;
-+      const char *rootblock;
-+
-+      find_rootblock = getprop(fdt, "/chosen", "find-rootblock", &l);
-+      if (!find_rootblock)
-+              find_rootblock = root;
-+
-+      /* ARM doesn't have __HAVE_ARCH_STRSTR, so it was copied from x86 */
-+      ptr = local_strstr(str, find_rootblock);
-+      if (!ptr)
-+              return dest;
-+
-+      end = strchr(ptr, ' ');
-+      end = end ? (end - 1) : (strchr(ptr, 0) - 1);
-+
-+      /* Some boards ubi.mtd=XX,ZZZZ, so let's check for '," too. */
-+      tmp = strchr(ptr, ',');
-+      if (tmp)
-+              end = end < tmp ? end : tmp - 1;
-+
-+      /*
-+       * find partition number
-+       * (assumes format root=/dev/mtdXX | /dev/mtdblockXX | yy:XX | ubi.mtd=XX,ZZZZ )
-+       */
-+      for (i = 0; end >= ptr && *end >= '0' && *end <= '9'; end--, i++);
-+
-+      ptr = end + 1;
-+
-+      /* if append-rootblock property is set use it to append to command line */
-+      rootblock = getprop(fdt, "/chosen", "append-rootblock", &l);
-+      if (rootblock != NULL) {
-+              if (*dest != ' ') {
-+                      *dest = ' ';
-+                      dest++;
-+                      len++;
-+              }
-+
-+              if (len + l + i <= COMMAND_LINE_SIZE) {
-+                      memcpy(dest, rootblock, l);
-+                      dest += l - 1;
-+
-+                      memcpy(dest, ptr, i);
-+                      dest += i;
-+              }
-+      }
-+
-+      return dest;
-+}
-+
- static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline)
- {
-       char cmdline[COMMAND_LINE_SIZE];
-@@ -86,13 +164,23 @@ static void merge_fdt_bootargs(void *fdt
-                       ptr += len - 1;
-               }
--      /* and append the ATAG_CMDLINE */
-       if (fdt_cmdline) {
--              len = strlen(fdt_cmdline);
--              if (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) {
--                      *ptr++ = ' ';
--                      memcpy(ptr, fdt_cmdline, len);
--                      ptr += len;
-+              if (IS_ENABLED(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)) {
-+                      /*
-+                      * save original bootloader args
-+                      * and append ubi.mtd with root partition number
-+                      * to current cmdline
-+                      */
-+                      setprop_string(fdt, "/chosen", "bootloader-args", fdt_cmdline);
-+                      ptr = append_rootblock(ptr, fdt_cmdline, len, fdt);
-+              } else {
-+                      /* and append the ATAG_CMDLINE */
-+                      len = strlen(fdt_cmdline);
-+                      if (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) {
-+                              *ptr++ = ' ';
-+                              memcpy(ptr, fdt_cmdline, len);
-+                              ptr += len;
-+                      }
-               }
-       }
-       *ptr = '\0';
---- a/init/main.c
-+++ b/init/main.c
-@@ -28,6 +28,7 @@
- #include <linux/initrd.h>
- #include <linux/memblock.h>
- #include <linux/acpi.h>
-+#include <linux/of.h>
- #include <linux/bootconfig.h>
- #include <linux/console.h>
- #include <linux/nmi.h>
-@@ -995,6 +996,17 @@ asmlinkage __visible void __init __no_sa
-       pr_notice("Kernel command line: %s\n", saved_command_line);
-       /* parameters may set static keys */
-       jump_label_init();
-+
-+      /* Show bootloader's original command line for reference */
-+      if (IS_ENABLED(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) && of_chosen) {
-+              const char *prop = of_get_property(of_chosen, "bootloader-args", NULL);
-+
-+              if(prop)
-+                      pr_notice("Bootloader command line (ignored): %s\n", prop);
-+              else
-+                      pr_notice("Bootloader command line not present\n");
-+      }
-+
-       parse_early_param();
-       after_dashes = parse_args("Booting kernel",
-                                 static_command_line, __start___param,
diff --git a/target/linux/ipq806x/patches-6.6/001-v6.2-clk-qcom-kpss-xcc-register-it-as-clk-provider.patch b/target/linux/ipq806x/patches-6.6/001-v6.2-clk-qcom-kpss-xcc-register-it-as-clk-provider.patch
new file mode 100644 (file)
index 0000000..9395f1b
--- /dev/null
@@ -0,0 +1,60 @@
+From 09be1a39e685d8c5edd471fd1cac9a8f8280d2de Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 8 Nov 2022 22:17:34 +0100
+Subject: [PATCH] clk: qcom: kpss-xcc: register it as clk provider
+
+krait-cc use this driver for the secondary mux. Register it as a clk
+provider to correctly use this clk in other drivers.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20221108211734.3707-1-ansuelsmth@gmail.com
+---
+ drivers/clk/qcom/kpss-xcc.c | 13 +++++++++----
+ 1 file changed, 9 insertions(+), 4 deletions(-)
+
+--- a/drivers/clk/qcom/kpss-xcc.c
++++ b/drivers/clk/qcom/kpss-xcc.c
+@@ -31,12 +31,13 @@ MODULE_DEVICE_TABLE(of, kpss_xcc_match_t
+ static int kpss_xcc_driver_probe(struct platform_device *pdev)
+ {
++      struct device *dev = &pdev->dev;
+       const struct of_device_id *id;
+       void __iomem *base;
+       struct clk_hw *hw;
+       const char *name;
+-      id = of_match_device(kpss_xcc_match_table, &pdev->dev);
++      id = of_match_device(kpss_xcc_match_table, dev);
+       if (!id)
+               return -ENODEV;
+@@ -45,7 +46,7 @@ static int kpss_xcc_driver_probe(struct
+               return PTR_ERR(base);
+       if (id->data) {
+-              if (of_property_read_string_index(pdev->dev.of_node,
++              if (of_property_read_string_index(dev->of_node,
+                                                 "clock-output-names",
+                                                 0, &name))
+                       return -ENODEV;
+@@ -55,12 +56,16 @@ static int kpss_xcc_driver_probe(struct
+               base += 0x28;
+       }
+-      hw = devm_clk_hw_register_mux_parent_data_table(&pdev->dev, name, aux_parents,
++      hw = devm_clk_hw_register_mux_parent_data_table(dev, name, aux_parents,
+                                                       ARRAY_SIZE(aux_parents), 0,
+                                                       base, 0, 0x3,
+                                                       0, aux_parent_map, NULL);
++      if (IS_ERR(hw))
++              return PTR_ERR(hw);
+-      return PTR_ERR_OR_ZERO(hw);
++      of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get, hw);
++
++      return 0;
+ }
+ static struct platform_driver kpss_xcc_driver = {
diff --git a/target/linux/ipq806x/patches-6.6/002-v6.2-01-clk-qcom-krait-cc-use-devm-variant-for-clk-notifier-.patch b/target/linux/ipq806x/patches-6.6/002-v6.2-01-clk-qcom-krait-cc-use-devm-variant-for-clk-notifier-.patch
new file mode 100644 (file)
index 0000000..65c1fc1
--- /dev/null
@@ -0,0 +1,27 @@
+From 3198106a99e73dbc4c02bd5128cec0997c73af82 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 8 Nov 2022 22:58:27 +0100
+Subject: [PATCH 1/6] clk: qcom: krait-cc: use devm variant for clk notifier
+ register
+
+Use devm variant for clk notifier register and correctly handle free
+resource on driver remove.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20221108215827.30475-1-ansuelsmth@gmail.com
+---
+ drivers/clk/qcom/krait-cc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/clk/qcom/krait-cc.c
++++ b/drivers/clk/qcom/krait-cc.c
+@@ -62,7 +62,7 @@ static int krait_notifier_register(struc
+       int ret = 0;
+       mux->clk_nb.notifier_call = krait_notifier_cb;
+-      ret = clk_notifier_register(clk, &mux->clk_nb);
++      ret = devm_clk_notifier_register(dev, clk, &mux->clk_nb);
+       if (ret)
+               dev_err(dev, "failed to register clock notifier: %d\n", ret);
diff --git a/target/linux/ipq806x/patches-6.6/002-v6.2-02-clk-qcom-krait-cc-fix-wrong-parent-order-for-seconda.patch b/target/linux/ipq806x/patches-6.6/002-v6.2-02-clk-qcom-krait-cc-fix-wrong-parent-order-for-seconda.patch
new file mode 100644 (file)
index 0000000..2dcb693
--- /dev/null
@@ -0,0 +1,46 @@
+From 8e456411abcbf899c04740b9dbb3dcefcd61c946 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Wed, 9 Nov 2022 01:56:27 +0100
+Subject: [PATCH 2/6] clk: qcom: krait-cc: fix wrong parent order for secondary
+ mux
+
+The secondary mux parent order is swapped.
+This currently doesn't cause problems as the secondary mux is used for idle
+clk and as a safe clk source while reprogramming the hfpll.
+
+Each mux have 2 or more output but he always have a safe source to
+switch while reprogramming the connected pll. We use a clk notifier to
+switch to the correct parent before clk core can apply the correct rate.
+The parent to switch is hardcoded in the mux struct.
+
+For the secondary mux the safe source to use is the qsb parent as it's
+the only fixed clk as the acpus_aux is a pll that can source from pxo or
+from pll8.
+
+The hardcoded safe parent for the secondary mux is set to index 0 that
+in the secondary mux map is set to 2.
+
+But the index 0 is actually acpu_aux in the parent list.
+
+Fix the swapped parents to correctly handle idle frequency and output a
+sane clk_summary report.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20221109005631.3189-1-ansuelsmth@gmail.com
+---
+ drivers/clk/qcom/krait-cc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/clk/qcom/krait-cc.c
++++ b/drivers/clk/qcom/krait-cc.c
+@@ -116,8 +116,8 @@ krait_add_sec_mux(struct device *dev, in
+       int ret;
+       struct krait_mux_clk *mux;
+       static const char *sec_mux_list[] = {
+-              "acpu_aux",
+               "qsb",
++              "acpu_aux",
+       };
+       struct clk_init_data init = {
+               .parent_names = sec_mux_list,
diff --git a/target/linux/ipq806x/patches-6.6/002-v6.2-03-clk-qcom-krait-cc-also-enable-secondary-mux-and-div-.patch b/target/linux/ipq806x/patches-6.6/002-v6.2-03-clk-qcom-krait-cc-also-enable-secondary-mux-and-div-.patch
new file mode 100644 (file)
index 0000000..6261a94
--- /dev/null
@@ -0,0 +1,68 @@
+From 18ae57b1e8abee6c453381470f6e18991d2901a8 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Wed, 9 Nov 2022 01:56:28 +0100
+Subject: [PATCH 3/6] clk: qcom: krait-cc: also enable secondary mux and div
+ clk
+
+clk-krait ignore any rate change if clk is not flagged as enabled.
+Correctly enable the secondary mux and div clk to correctly change rate
+instead of silently ignoring the request.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20221109005631.3189-2-ansuelsmth@gmail.com
+---
+ drivers/clk/qcom/krait-cc.c | 21 ++++++++++++++++++++-
+ 1 file changed, 20 insertions(+), 1 deletion(-)
+
+--- a/drivers/clk/qcom/krait-cc.c
++++ b/drivers/clk/qcom/krait-cc.c
+@@ -80,6 +80,7 @@ krait_add_div(struct device *dev, int id
+       };
+       const char *p_names[1];
+       struct clk *clk;
++      int cpu;
+       div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
+       if (!div)
+@@ -103,6 +104,17 @@ krait_add_div(struct device *dev, int id
+       }
+       clk = devm_clk_register(dev, &div->hw);
++      if (IS_ERR(clk))
++              goto err;
++
++      /* clk-krait ignore any rate change if mux is not flagged as enabled */
++      if (id < 0)
++              for_each_online_cpu(cpu)
++                      clk_prepare_enable(div->hw.clk);
++      else
++              clk_prepare_enable(div->hw.clk);
++
++err:
+       kfree(p_names[0]);
+       kfree(init.name);
+@@ -113,7 +125,7 @@ static int
+ krait_add_sec_mux(struct device *dev, int id, const char *s,
+                 unsigned int offset, bool unique_aux)
+ {
+-      int ret;
++      int cpu, ret;
+       struct krait_mux_clk *mux;
+       static const char *sec_mux_list[] = {
+               "qsb",
+@@ -165,6 +177,13 @@ krait_add_sec_mux(struct device *dev, in
+       if (ret)
+               goto unique_aux;
++      /* clk-krait ignore any rate change if mux is not flagged as enabled */
++      if (id < 0)
++              for_each_online_cpu(cpu)
++                      clk_prepare_enable(mux->hw.clk);
++      else
++              clk_prepare_enable(mux->hw.clk);
++
+ unique_aux:
+       if (unique_aux)
+               kfree(sec_mux_list[0]);
diff --git a/target/linux/ipq806x/patches-6.6/002-v6.2-04-clk-qcom-krait-cc-handle-secondary-mux-sourcing-out-.patch b/target/linux/ipq806x/patches-6.6/002-v6.2-04-clk-qcom-krait-cc-handle-secondary-mux-sourcing-out-.patch
new file mode 100644 (file)
index 0000000..fabb299
--- /dev/null
@@ -0,0 +1,48 @@
+From e5dc1a4c01510da8438dddfdf4200b79d73990dc Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Wed, 9 Nov 2022 01:56:29 +0100
+Subject: [PATCH 4/6] clk: qcom: krait-cc: handle secondary mux sourcing out of
+ acpu_aux
+
+Some bootloader may leave the system in an even more undefined state
+with the secondary mux of L2 or other cores sourcing out of the acpu_aux
+parent. This results in the clk set to the PXO rate or a PLL8 rate.
+
+The current logic to reset the mux and set them to a defined state only
+handle if the mux are configured to source out of QSB. Change this and
+force a new and defined state if the current clk is lower than the aux
+rate. This way we can handle any wrong configuration where the mux is
+sourcing out of QSB (rate 225MHz, currently set to a virtual rate of 1),
+PXO rate (rate 25MHz) or PLL8 (needs to be configured to run at 384Mhz).
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20221109005631.3189-3-ansuelsmth@gmail.com
+---
+ drivers/clk/qcom/krait-cc.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+--- a/drivers/clk/qcom/krait-cc.c
++++ b/drivers/clk/qcom/krait-cc.c
+@@ -383,8 +383,8 @@ static int krait_cc_probe(struct platfor
+        */
+       cur_rate = clk_get_rate(l2_pri_mux_clk);
+       aux_rate = 384000000;
+-      if (cur_rate == 1) {
+-              pr_info("L2 @ QSB rate. Forcing new rate.\n");
++      if (cur_rate < aux_rate) {
++              pr_info("L2 @ Undefined rate. Forcing new rate.\n");
+               cur_rate = aux_rate;
+       }
+       clk_set_rate(l2_pri_mux_clk, aux_rate);
+@@ -394,8 +394,8 @@ static int krait_cc_probe(struct platfor
+       for_each_possible_cpu(cpu) {
+               clk = clks[cpu];
+               cur_rate = clk_get_rate(clk);
+-              if (cur_rate == 1) {
+-                      pr_info("CPU%d @ QSB rate. Forcing new rate.\n", cpu);
++              if (cur_rate < aux_rate) {
++                      pr_info("CPU%d @ Undefined rate. Forcing new rate.\n", cpu);
+                       cur_rate = aux_rate;
+               }
diff --git a/target/linux/ipq806x/patches-6.6/002-v6.2-05-clk-qcom-krait-cc-convert-to-devm_clk_hw_register.patch b/target/linux/ipq806x/patches-6.6/002-v6.2-05-clk-qcom-krait-cc-convert-to-devm_clk_hw_register.patch
new file mode 100644 (file)
index 0000000..049b1fa
--- /dev/null
@@ -0,0 +1,104 @@
+From 8ea9fb841a7e528bc8ae79d726ce951dcf7b46e2 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Wed, 9 Nov 2022 01:56:30 +0100
+Subject: [PATCH 5/6] clk: qcom: krait-cc: convert to devm_clk_hw_register
+
+clk_register is now deprecated. Convert the driver to devm_clk_hw_register.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20221109005631.3189-4-ansuelsmth@gmail.com
+---
+ drivers/clk/qcom/krait-cc.c | 31 +++++++++++++++++++------------
+ 1 file changed, 19 insertions(+), 12 deletions(-)
+
+--- a/drivers/clk/qcom/krait-cc.c
++++ b/drivers/clk/qcom/krait-cc.c
+@@ -79,8 +79,7 @@ krait_add_div(struct device *dev, int id
+               .flags = CLK_SET_RATE_PARENT,
+       };
+       const char *p_names[1];
+-      struct clk *clk;
+-      int cpu;
++      int cpu, ret;
+       div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
+       if (!div)
+@@ -103,8 +102,8 @@ krait_add_div(struct device *dev, int id
+               return -ENOMEM;
+       }
+-      clk = devm_clk_register(dev, &div->hw);
+-      if (IS_ERR(clk))
++      ret = devm_clk_hw_register(dev, &div->hw);
++      if (ret)
+               goto err;
+       /* clk-krait ignore any rate change if mux is not flagged as enabled */
+@@ -118,7 +117,7 @@ err:
+       kfree(p_names[0]);
+       kfree(init.name);
+-      return PTR_ERR_OR_ZERO(clk);
++      return ret;
+ }
+ static int
+@@ -137,7 +136,6 @@ krait_add_sec_mux(struct device *dev, in
+               .ops = &krait_mux_clk_ops,
+               .flags = CLK_SET_RATE_PARENT,
+       };
+-      struct clk *clk;
+       mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
+       if (!mux)
+@@ -166,14 +164,16 @@ krait_add_sec_mux(struct device *dev, in
+       if (unique_aux) {
+               sec_mux_list[0] = kasprintf(GFP_KERNEL, "acpu%s_aux", s);
+               if (!sec_mux_list[0]) {
+-                      clk = ERR_PTR(-ENOMEM);
++                      ret = -ENOMEM;
+                       goto err_aux;
+               }
+       }
+-      clk = devm_clk_register(dev, &mux->hw);
++      ret = devm_clk_hw_register(dev, &mux->hw);
++      if (ret)
++              goto unique_aux;
+-      ret = krait_notifier_register(dev, clk, mux);
++      ret = krait_notifier_register(dev, mux->hw.clk, mux);
+       if (ret)
+               goto unique_aux;
+@@ -189,7 +189,7 @@ unique_aux:
+               kfree(sec_mux_list[0]);
+ err_aux:
+       kfree(init.name);
+-      return PTR_ERR_OR_ZERO(clk);
++      return ret;
+ }
+ static struct clk *
+@@ -241,11 +241,18 @@ krait_add_pri_mux(struct device *dev, in
+               goto err_p2;
+       }
+-      clk = devm_clk_register(dev, &mux->hw);
++      ret = devm_clk_hw_register(dev, &mux->hw);
++      if (ret) {
++              clk = ERR_PTR(ret);
++              goto err_p3;
++      }
++
++      clk = mux->hw.clk;
+       ret = krait_notifier_register(dev, clk, mux);
+       if (ret)
+-              goto err_p3;
++              clk = ERR_PTR(ret);
++
+ err_p3:
+       kfree(p_names[2]);
+ err_p2:
diff --git a/target/linux/ipq806x/patches-6.6/002-v6.2-06-clk-qcom-krait-cc-convert-to-parent_data-API.patch b/target/linux/ipq806x/patches-6.6/002-v6.2-06-clk-qcom-krait-cc-convert-to-parent_data-API.patch
new file mode 100644 (file)
index 0000000..453a37d
--- /dev/null
@@ -0,0 +1,414 @@
+From 56a655e1c41a86445cf2de656649ad93424b2a63 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Wed, 9 Nov 2022 01:56:31 +0100
+Subject: [PATCH 6/6] clk: qcom: krait-cc: convert to parent_data API
+
+Modernize the krait-cc driver to parent-data API and refactor to drop
+any use of parent_names. From Documentation all the required clocks should
+be declared in DTS so fw_name can be correctly used to get the parents
+for all the muxes. .name is also declared to save compatibility with old
+DT.
+
+While at it also drop some hardcoded index and introduce an enum to make
+index values more clear.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20221109005631.3189-5-ansuelsmth@gmail.com
+---
+ drivers/clk/qcom/krait-cc.c | 202 ++++++++++++++++++++----------------
+ 1 file changed, 112 insertions(+), 90 deletions(-)
+
+--- a/drivers/clk/qcom/krait-cc.c
++++ b/drivers/clk/qcom/krait-cc.c
+@@ -15,6 +15,16 @@
+ #include "clk-krait.h"
++enum {
++      cpu0_mux = 0,
++      cpu1_mux,
++      cpu2_mux,
++      cpu3_mux,
++      l2_mux,
++
++      clks_max,
++};
++
+ static unsigned int sec_mux_map[] = {
+       2,
+       0,
+@@ -69,21 +79,23 @@ static int krait_notifier_register(struc
+       return ret;
+ }
+-static int
++static struct clk_hw *
+ krait_add_div(struct device *dev, int id, const char *s, unsigned int offset)
+ {
+       struct krait_div2_clk *div;
++      static struct clk_parent_data p_data[1];
+       struct clk_init_data init = {
+-              .num_parents = 1,
++              .num_parents = ARRAY_SIZE(p_data),
+               .ops = &krait_div2_clk_ops,
+               .flags = CLK_SET_RATE_PARENT,
+       };
+-      const char *p_names[1];
++      struct clk_hw *clk;
++      char *parent_name;
+       int cpu, ret;
+       div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
+       if (!div)
+-              return -ENOMEM;
++              return ERR_PTR(-ENOMEM);
+       div->width = 2;
+       div->shift = 6;
+@@ -93,18 +105,25 @@ krait_add_div(struct device *dev, int id
+       init.name = kasprintf(GFP_KERNEL, "hfpll%s_div", s);
+       if (!init.name)
+-              return -ENOMEM;
++              return ERR_PTR(-ENOMEM);
+-      init.parent_names = p_names;
+-      p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s);
+-      if (!p_names[0]) {
+-              kfree(init.name);
+-              return -ENOMEM;
++      init.parent_data = p_data;
++      parent_name = kasprintf(GFP_KERNEL, "hfpll%s", s);
++      if (!parent_name) {
++              clk = ERR_PTR(-ENOMEM);
++              goto err_parent_name;
+       }
++      p_data[0].fw_name = parent_name;
++      p_data[0].name = parent_name;
++
+       ret = devm_clk_hw_register(dev, &div->hw);
+-      if (ret)
+-              goto err;
++      if (ret) {
++              clk = ERR_PTR(ret);
++              goto err_clk;
++      }
++
++      clk = &div->hw;
+       /* clk-krait ignore any rate change if mux is not flagged as enabled */
+       if (id < 0)
+@@ -113,33 +132,36 @@ krait_add_div(struct device *dev, int id
+       else
+               clk_prepare_enable(div->hw.clk);
+-err:
+-      kfree(p_names[0]);
++err_clk:
++      kfree(parent_name);
++err_parent_name:
+       kfree(init.name);
+-      return ret;
++      return clk;
+ }
+-static int
++static struct clk_hw *
+ krait_add_sec_mux(struct device *dev, int id, const char *s,
+                 unsigned int offset, bool unique_aux)
+ {
+       int cpu, ret;
+       struct krait_mux_clk *mux;
+-      static const char *sec_mux_list[] = {
+-              "qsb",
+-              "acpu_aux",
++      static struct clk_parent_data sec_mux_list[2] = {
++              { .name = "qsb", .fw_name = "qsb" },
++              {},
+       };
+       struct clk_init_data init = {
+-              .parent_names = sec_mux_list,
++              .parent_data = sec_mux_list,
+               .num_parents = ARRAY_SIZE(sec_mux_list),
+               .ops = &krait_mux_clk_ops,
+               .flags = CLK_SET_RATE_PARENT,
+       };
++      struct clk_hw *clk;
++      char *parent_name;
+       mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
+       if (!mux)
+-              return -ENOMEM;
++              return ERR_PTR(-ENOMEM);
+       mux->offset = offset;
+       mux->lpl = id >= 0;
+@@ -159,23 +181,33 @@ krait_add_sec_mux(struct device *dev, in
+       init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
+       if (!init.name)
+-              return -ENOMEM;
++              return ERR_PTR(-ENOMEM);
+       if (unique_aux) {
+-              sec_mux_list[0] = kasprintf(GFP_KERNEL, "acpu%s_aux", s);
+-              if (!sec_mux_list[0]) {
+-                      ret = -ENOMEM;
++              parent_name = kasprintf(GFP_KERNEL, "acpu%s_aux", s);
++              if (!parent_name) {
++                      clk = ERR_PTR(-ENOMEM);
+                       goto err_aux;
+               }
++              sec_mux_list[1].fw_name = parent_name;
++              sec_mux_list[1].name = parent_name;
++      } else {
++              sec_mux_list[1].name = "apu_aux";
+       }
+       ret = devm_clk_hw_register(dev, &mux->hw);
+-      if (ret)
+-              goto unique_aux;
++      if (ret) {
++              clk = ERR_PTR(ret);
++              goto err_clk;
++      }
++
++      clk = &mux->hw;
+       ret = krait_notifier_register(dev, mux->hw.clk, mux);
+-      if (ret)
+-              goto unique_aux;
++      if (ret) {
++              clk = ERR_PTR(ret);
++              goto err_clk;
++      }
+       /* clk-krait ignore any rate change if mux is not flagged as enabled */
+       if (id < 0)
+@@ -184,28 +216,29 @@ krait_add_sec_mux(struct device *dev, in
+       else
+               clk_prepare_enable(mux->hw.clk);
+-unique_aux:
++err_clk:
+       if (unique_aux)
+-              kfree(sec_mux_list[0]);
++              kfree(parent_name);
+ err_aux:
+       kfree(init.name);
+-      return ret;
++      return clk;
+ }
+-static struct clk *
+-krait_add_pri_mux(struct device *dev, int id, const char *s,
+-                unsigned int offset)
++static struct clk_hw *
++krait_add_pri_mux(struct device *dev, struct clk_hw *hfpll_div, struct clk_hw *sec_mux,
++                int id, const char *s, unsigned int offset)
+ {
+       int ret;
+       struct krait_mux_clk *mux;
+-      const char *p_names[3];
++      static struct clk_parent_data p_data[3];
+       struct clk_init_data init = {
+-              .parent_names = p_names,
+-              .num_parents = ARRAY_SIZE(p_names),
++              .parent_data = p_data,
++              .num_parents = ARRAY_SIZE(p_data),
+               .ops = &krait_mux_clk_ops,
+               .flags = CLK_SET_RATE_PARENT,
+       };
+-      struct clk *clk;
++      struct clk_hw *clk;
++      char *hfpll_name;
+       mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
+       if (!mux)
+@@ -223,55 +256,44 @@ krait_add_pri_mux(struct device *dev, in
+       if (!init.name)
+               return ERR_PTR(-ENOMEM);
+-      p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s);
+-      if (!p_names[0]) {
++      hfpll_name = kasprintf(GFP_KERNEL, "hfpll%s", s);
++      if (!hfpll_name) {
+               clk = ERR_PTR(-ENOMEM);
+-              goto err_p0;
++              goto err_hfpll;
+       }
+-      p_names[1] = kasprintf(GFP_KERNEL, "hfpll%s_div", s);
+-      if (!p_names[1]) {
+-              clk = ERR_PTR(-ENOMEM);
+-              goto err_p1;
+-      }
++      p_data[0].fw_name = hfpll_name;
++      p_data[0].name = hfpll_name;
+-      p_names[2] = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
+-      if (!p_names[2]) {
+-              clk = ERR_PTR(-ENOMEM);
+-              goto err_p2;
+-      }
++      p_data[1].hw = hfpll_div;
++      p_data[2].hw = sec_mux;
+       ret = devm_clk_hw_register(dev, &mux->hw);
+       if (ret) {
+               clk = ERR_PTR(ret);
+-              goto err_p3;
++              goto err_clk;
+       }
+-      clk = mux->hw.clk;
++      clk = &mux->hw;
+-      ret = krait_notifier_register(dev, clk, mux);
++      ret = krait_notifier_register(dev, mux->hw.clk, mux);
+       if (ret)
+               clk = ERR_PTR(ret);
+-err_p3:
+-      kfree(p_names[2]);
+-err_p2:
+-      kfree(p_names[1]);
+-err_p1:
+-      kfree(p_names[0]);
+-err_p0:
++err_clk:
++      kfree(hfpll_name);
++err_hfpll:
+       kfree(init.name);
+       return clk;
+ }
+ /* id < 0 for L2, otherwise id == physical CPU number */
+-static struct clk *krait_add_clks(struct device *dev, int id, bool unique_aux)
++static struct clk_hw *krait_add_clks(struct device *dev, int id, bool unique_aux)
+ {
+-      int ret;
++      struct clk_hw *hfpll_div, *sec_mux, *pri_mux;
+       unsigned int offset;
+       void *p = NULL;
+       const char *s;
+-      struct clk *clk;
+       if (id >= 0) {
+               offset = 0x4501 + (0x1000 * id);
+@@ -283,22 +305,23 @@ static struct clk *krait_add_clks(struct
+               s = "_l2";
+       }
+-      ret = krait_add_div(dev, id, s, offset);
+-      if (ret) {
+-              clk = ERR_PTR(ret);
++      hfpll_div = krait_add_div(dev, id, s, offset);
++      if (IS_ERR(hfpll_div)) {
++              pri_mux = hfpll_div;
+               goto err;
+       }
+-      ret = krait_add_sec_mux(dev, id, s, offset, unique_aux);
+-      if (ret) {
+-              clk = ERR_PTR(ret);
++      sec_mux = krait_add_sec_mux(dev, id, s, offset, unique_aux);
++      if (IS_ERR(sec_mux)) {
++              pri_mux = sec_mux;
+               goto err;
+       }
+-      clk = krait_add_pri_mux(dev, id, s, offset);
++      pri_mux = krait_add_pri_mux(dev, hfpll_div, sec_mux, id, s, offset);
++
+ err:
+       kfree(p);
+-      return clk;
++      return pri_mux;
+ }
+ static struct clk *krait_of_get(struct of_phandle_args *clkspec, void *data)
+@@ -306,7 +329,7 @@ static struct clk *krait_of_get(struct o
+       unsigned int idx = clkspec->args[0];
+       struct clk **clks = data;
+-      if (idx >= 5) {
++      if (idx >= clks_max) {
+               pr_err("%s: invalid clock index %d\n", __func__, idx);
+               return ERR_PTR(-EINVAL);
+       }
+@@ -327,9 +350,8 @@ static int krait_cc_probe(struct platfor
+       const struct of_device_id *id;
+       unsigned long cur_rate, aux_rate;
+       int cpu;
+-      struct clk *clk;
+-      struct clk **clks;
+-      struct clk *l2_pri_mux_clk;
++      struct clk_hw *mux, *l2_pri_mux;
++      struct clk *clk, **clks;
+       id = of_match_device(krait_cc_match_table, dev);
+       if (!id)
+@@ -348,21 +370,21 @@ static int krait_cc_probe(struct platfor
+       }
+       /* Krait configurations have at most 4 CPUs and one L2 */
+-      clks = devm_kcalloc(dev, 5, sizeof(*clks), GFP_KERNEL);
++      clks = devm_kcalloc(dev, clks_max, sizeof(*clks), GFP_KERNEL);
+       if (!clks)
+               return -ENOMEM;
+       for_each_possible_cpu(cpu) {
+-              clk = krait_add_clks(dev, cpu, id->data);
++              mux = krait_add_clks(dev, cpu, id->data);
+               if (IS_ERR(clk))
+                       return PTR_ERR(clk);
+-              clks[cpu] = clk;
++              clks[cpu] = mux->clk;
+       }
+-      l2_pri_mux_clk = krait_add_clks(dev, -1, id->data);
+-      if (IS_ERR(l2_pri_mux_clk))
+-              return PTR_ERR(l2_pri_mux_clk);
+-      clks[4] = l2_pri_mux_clk;
++      l2_pri_mux = krait_add_clks(dev, -1, id->data);
++      if (IS_ERR(l2_pri_mux))
++              return PTR_ERR(l2_pri_mux);
++      clks[l2_mux] = l2_pri_mux->clk;
+       /*
+        * We don't want the CPU or L2 clocks to be turned off at late init
+@@ -372,7 +394,7 @@ static int krait_cc_probe(struct platfor
+        * they take over.
+        */
+       for_each_online_cpu(cpu) {
+-              clk_prepare_enable(l2_pri_mux_clk);
++              clk_prepare_enable(clks[l2_mux]);
+               WARN(clk_prepare_enable(clks[cpu]),
+                    "Unable to turn on CPU%d clock", cpu);
+       }
+@@ -388,16 +410,16 @@ static int krait_cc_probe(struct platfor
+        * two different rates to force a HFPLL reinit under all
+        * circumstances.
+        */
+-      cur_rate = clk_get_rate(l2_pri_mux_clk);
++      cur_rate = clk_get_rate(clks[l2_mux]);
+       aux_rate = 384000000;
+       if (cur_rate < aux_rate) {
+               pr_info("L2 @ Undefined rate. Forcing new rate.\n");
+               cur_rate = aux_rate;
+       }
+-      clk_set_rate(l2_pri_mux_clk, aux_rate);
+-      clk_set_rate(l2_pri_mux_clk, 2);
+-      clk_set_rate(l2_pri_mux_clk, cur_rate);
+-      pr_info("L2 @ %lu KHz\n", clk_get_rate(l2_pri_mux_clk) / 1000);
++      clk_set_rate(clks[l2_mux], aux_rate);
++      clk_set_rate(clks[l2_mux], 2);
++      clk_set_rate(clks[l2_mux], cur_rate);
++      pr_info("L2 @ %lu KHz\n", clk_get_rate(clks[l2_mux]) / 1000);
+       for_each_possible_cpu(cpu) {
+               clk = clks[cpu];
+               cur_rate = clk_get_rate(clk);
diff --git a/target/linux/ipq806x/patches-6.6/003-v6.2-ARM-dts-qcom-ipq8064-disable-mmc-ddr-1_8v-for-sdcc1.patch b/target/linux/ipq806x/patches-6.6/003-v6.2-ARM-dts-qcom-ipq8064-disable-mmc-ddr-1_8v-for-sdcc1.patch
new file mode 100644 (file)
index 0000000..7e65f4c
--- /dev/null
@@ -0,0 +1,28 @@
+From c9713e4ede1e5d044b64fe4d3cbb84223625637f Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 25 Oct 2022 01:38:17 +0200
+Subject: [PATCH] ARM: dts: qcom: ipq8064: disable mmc-ddr-1_8v for sdcc1
+
+It was reported non working mmc with this option enabled.
+Both mmc for ipq8064 are supplied by a fixed 3.3v regulator so mmc can't
+be run at 1.8v.
+Disable it to restore correct functionality of this SoC feature.
+
+Tested-by: Hendrik Koerner <koerhen@web.de>
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+Link: https://lore.kernel.org/r/20221024233817.27410-1-ansuelsmth@gmail.com
+---
+ arch/arm/boot/dts/qcom-ipq8064.dtsi | 1 -
+ 1 file changed, 1 deletion(-)
+
+--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
+@@ -756,7 +756,6 @@
+                               non-removable;
+                               cap-sd-highspeed;
+                               cap-mmc-highspeed;
+-                              mmc-ddr-1_8v;
+                               vmmc-supply = <&vsdcc_fixed>;
+                               dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
+                               dma-names = "tx", "rx";
diff --git a/target/linux/ipq806x/patches-6.6/004-v6.2-01-thermal-drivers-qcom-tsens-Init-debugfs-only-with-su.patch b/target/linux/ipq806x/patches-6.6/004-v6.2-01-thermal-drivers-qcom-tsens-Init-debugfs-only-with-su.patch
new file mode 100644 (file)
index 0000000..76df0f5
--- /dev/null
@@ -0,0 +1,42 @@
+From de48d8766afcd97d147699aaff78a338081c9973 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Sat, 22 Oct 2022 14:56:55 +0200
+Subject: [PATCH 1/3] thermal/drivers/qcom/tsens: Init debugfs only with
+ successful probe
+
+Calibrate and tsens_register can fail or PROBE_DEFER. This will cause a
+double or a wrong init of the debugfs information. Init debugfs only
+with successful probe fixing warning about directory already present.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Acked-by: Thara Gopinath <thara.gopinath@linaro.org>
+Link: https://lore.kernel.org/r/20221022125657.22530-2-ansuelsmth@gmail.com
+Signed-off-by: Daniel Lezcano <daniel.lezcano@kernel.org>
+---
+ drivers/thermal/qcom/tsens.c | 8 +++++---
+ 1 file changed, 5 insertions(+), 3 deletions(-)
+
+--- a/drivers/thermal/qcom/tsens.c
++++ b/drivers/thermal/qcom/tsens.c
+@@ -918,8 +918,6 @@ int __init init_common(struct tsens_priv
+       if (tsens_version(priv) >= VER_0_1)
+               tsens_enable_irq(priv);
+-      tsens_debug_init(op);
+-
+ err_put_device:
+       put_device(&op->dev);
+       return ret;
+@@ -1156,7 +1154,11 @@ static int tsens_probe(struct platform_d
+               }
+       }
+-      return tsens_register(priv);
++      ret = tsens_register(priv);
++      if (!ret)
++              tsens_debug_init(pdev);
++
++      return ret;
+ }
+ static int tsens_remove(struct platform_device *pdev)
diff --git a/target/linux/ipq806x/patches-6.6/004-v6.2-02-thermal-drivers-qcom-tsens-Fix-wrong-version-id-dbg_.patch b/target/linux/ipq806x/patches-6.6/004-v6.2-02-thermal-drivers-qcom-tsens-Fix-wrong-version-id-dbg_.patch
new file mode 100644 (file)
index 0000000..10f1e36
--- /dev/null
@@ -0,0 +1,29 @@
+From c7e077e921fa94e0c06c8d14af6c0504c8a5f4bd Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Sat, 22 Oct 2022 14:56:56 +0200
+Subject: [PATCH 2/3] thermal/drivers/qcom/tsens: Fix wrong version id
+ dbg_version_show
+
+For VER_0 the version was incorrectly reported as 0.1.0.
+
+Fix that and correctly report the major version for this old tsens
+revision.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Link: https://lore.kernel.org/r/20221022125657.22530-3-ansuelsmth@gmail.com
+Signed-off-by: Daniel Lezcano <daniel.lezcano@kernel.org>
+---
+ drivers/thermal/qcom/tsens.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/thermal/qcom/tsens.c
++++ b/drivers/thermal/qcom/tsens.c
+@@ -692,7 +692,7 @@ static int dbg_version_show(struct seq_f
+                       return ret;
+               seq_printf(s, "%d.%d.%d\n", maj_ver, min_ver, step_ver);
+       } else {
+-              seq_puts(s, "0.1.0\n");
++              seq_printf(s, "0.%d.0\n", priv->feat->ver_major);
+       }
+       return 0;
diff --git a/target/linux/ipq806x/patches-6.6/004-v6.2-03-thermal-drivers-qcom-tsens-Rework-debugfs-file-struc.patch b/target/linux/ipq806x/patches-6.6/004-v6.2-03-thermal-drivers-qcom-tsens-Rework-debugfs-file-struc.patch
new file mode 100644 (file)
index 0000000..63cce79
--- /dev/null
@@ -0,0 +1,54 @@
+From 89992d95ed1046338c7866ef7bbe6de543a2af91 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Sat, 22 Oct 2022 14:56:57 +0200
+Subject: [PATCH 3/3] thermal/drivers/qcom/tsens: Rework debugfs file structure
+
+The current tsens debugfs structure is composed by:
+- a tsens dir in debugfs with a version file
+- a directory for each tsens istance with sensors file to dump all the
+  sensors value.
+
+This works on the assumption that we have the same version for each
+istance but this assumption seems fragile and with more than one tsens
+istance results in the version file not tracking each of them.
+
+A better approach is to just create a subdirectory for each tsens
+istance and put there version and sensors debugfs file.
+
+Using this new implementation results in less code since debugfs entry
+are created only on successful tsens probe.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Link: https://lore.kernel.org/r/20221022125657.22530-4-ansuelsmth@gmail.com
+Signed-off-by: Daniel Lezcano <daniel.lezcano@kernel.org>
+---
+ drivers/thermal/qcom/tsens.c | 13 +++----------
+ 1 file changed, 3 insertions(+), 10 deletions(-)
+
+--- a/drivers/thermal/qcom/tsens.c
++++ b/drivers/thermal/qcom/tsens.c
+@@ -704,21 +704,14 @@ DEFINE_SHOW_ATTRIBUTE(dbg_sensors);
+ static void tsens_debug_init(struct platform_device *pdev)
+ {
+       struct tsens_priv *priv = platform_get_drvdata(pdev);
+-      struct dentry *root, *file;
+-      root = debugfs_lookup("tsens", NULL);
+-      if (!root)
++      priv->debug_root = debugfs_lookup("tsens", NULL);
++      if (!priv->debug_root)
+               priv->debug_root = debugfs_create_dir("tsens", NULL);
+-      else
+-              priv->debug_root = root;
+-
+-      file = debugfs_lookup("version", priv->debug_root);
+-      if (!file)
+-              debugfs_create_file("version", 0444, priv->debug_root,
+-                                  pdev, &dbg_version_fops);
+       /* A directory for each instance of the TSENS IP */
+       priv->debug = debugfs_create_dir(dev_name(&pdev->dev), priv->debug_root);
++      debugfs_create_file("version", 0444, priv->debug, pdev, &dbg_version_fops);
+       debugfs_create_file("sensors", 0444, priv->debug, pdev, &dbg_sensors_fops);
+ }
+ #else
diff --git a/target/linux/ipq806x/patches-6.6/102-mtd-rootfs-conflicts-with-OpenWrt-auto-mounting.patch b/target/linux/ipq806x/patches-6.6/102-mtd-rootfs-conflicts-with-OpenWrt-auto-mounting.patch
new file mode 100644 (file)
index 0000000..e0c195f
--- /dev/null
@@ -0,0 +1,25 @@
+From 5001f2e1a325b68dbf225bd17f69a4d3d975cca5 Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Thu, 9 Mar 2017 09:31:44 +0100
+Subject: [PATCH 61/69] mtd: "rootfs" conflicts with OpenWrt auto mounting
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ drivers/mtd/mtdpart.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/drivers/mtd/mtdpart.c
++++ b/drivers/mtd/mtdpart.c
+@@ -51,7 +51,11 @@ static struct mtd_info *allocate_partiti
+       /* allocate the partition structure */
+       child = kzalloc(sizeof(*child), GFP_KERNEL);
+-      name = kstrdup(part->name, GFP_KERNEL);
++      /* "rootfs" conflicts with OpenWrt auto mounting */
++      if (mtd_type_is_nand(parent) && !strcmp(part->name, "rootfs"))
++              name = "ubi";
++      else
++              name = kstrdup(part->name, GFP_KERNEL);
+       if (!name || !child) {
+               printk(KERN_ERR"memory allocation error while creating partitions for \"%s\"\n",
+                      parent->name);
diff --git a/target/linux/ipq806x/patches-6.6/107-10-ARM-dts-qcom-add-saw-for-l2-cache-and-kraitcc-for.patch b/target/linux/ipq806x/patches-6.6/107-10-ARM-dts-qcom-add-saw-for-l2-cache-and-kraitcc-for.patch
new file mode 100644 (file)
index 0000000..0a594b2
--- /dev/null
@@ -0,0 +1,89 @@
+From bef5018abb7cf94efafdc05087b4c998891ae4ec Mon Sep 17 00:00:00 2001
+From: Ansuel Smith <ansuelsmth@gmail.com>
+Date: Mon, 17 Jan 2022 23:39:34 +0100
+Subject: [PATCH v3 10/18] ARM: dts: qcom: add saw for l2 cache and kraitcc for
+ ipq8064
+
+Add saw compatible for l2 cache and kraitcc node for ipq8064 dtsi.
+Also declare clock-output-names for acc0 and acc1 and qsb fixed clock
+for the secondary mux.
+
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+Tested-by: Jonathan McDowell <noodles@earth.li>
+---
+ arch/arm/boot/dts/qcom-ipq8064.dtsi | 34 +++++++++++++++++++++++++++--
+ 1 file changed, 32 insertions(+), 2 deletions(-)
+
+--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
+@@ -301,6 +301,12 @@
+       };
+       clocks {
++              qsb: qsb {
++                      compatible = "fixed-clock";
++                      clock-frequency = <225000000>;
++                      #clock-cells = <0>;
++              };
++
+               cxo_board: cxo_board {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+@@ -575,15 +581,30 @@
+                       clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
+                       clock-names = "pll8_vote", "pxo";
+                       clock-output-names = "acpu_l2_aux";
++                      #clock-cells = <0>;
++              };
++
++              kraitcc: clock-controller {
++                      compatible = "qcom,krait-cc-v1";
++                      clocks = <&gcc PLL9>, <&gcc PLL10>, <&gcc PLL12>,
++                               <&acc0>, <&acc1>, <&l2cc>, <&qsb>, <&pxo_board>;
++                      clock-names = "hfpll0", "hfpll1", "hfpll_l2",
++                                    "acpu0_aux", "acpu1_aux", "acpu_l2_aux",
++                                    "qsb", "pxo";
++                      #clock-cells = <1>;
+               };
+               acc0: clock-controller@2088000 {
+                       compatible = "qcom,kpss-acc-v1";
+                       reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
++                      clock-output-names = "acpu0_aux";
++                      clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
++                      clock-names = "pll8_vote", "pxo";
++                      #clock-cells = <0>;
+               };
+               saw0: regulator@2089000 {
+-                      compatible = "qcom,saw2";
++                      compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
+                       reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
+                       regulator;
+               };
+@@ -591,14 +612,24 @@
+               acc1: clock-controller@2098000 {
+                       compatible = "qcom,kpss-acc-v1";
+                       reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
++                      clock-output-names = "acpu1_aux";
++                      clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
++                      clock-names = "pll8_vote", "pxo";
++                      #clock-cells = <0>;
+               };
+               saw1: regulator@2099000 {
+-                      compatible = "qcom,saw2";
++                      compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
+                       reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
+                       regulator;
+               };
++              saw_l2: regulator@02012000 {
++                      compatible = "qcom,saw2", "syscon";
++                      reg = <0x02012000 0x1000>;
++                      regulator;
++              };
++
+               nss_common: syscon@03000000 {
+                       compatible = "syscon";
+                       reg = <0x03000000 0x0000FFFF>;
diff --git a/target/linux/ipq806x/patches-6.6/107-13-ARM-dts-qcom-add-opp-table-for-cpu-and-l2-for-ipq.patch b/target/linux/ipq806x/patches-6.6/107-13-ARM-dts-qcom-add-opp-table-for-cpu-and-l2-for-ipq.patch
new file mode 100644 (file)
index 0000000..16e924b
--- /dev/null
@@ -0,0 +1,268 @@
+From 076ebb6e1799c4c7a1d2e07510d88b9e9b57b551 Mon Sep 17 00:00:00 2001
+From: Ansuel Smith <ansuelsmth@gmail.com>
+Date: Tue, 18 Jan 2022 00:03:47 +0100
+Subject: [PATCH v3 13/18] ARM: dts: qcom: add opp table for cpu and l2 for
+ ipq8064
+
+Add opp table for cpu and l2 cache. While the current cpufreq is
+the generic one that doesn't scale the L2 cache, we add the l2
+cache opp anyway for the sake of completeness. This will be handy in the
+future when a dedicated cpufreq driver is introduced for krait cores
+that will correctly scale l2 cache with the core freq.
+
+Opp-level is set based on the logic of
+0: idle level
+1: normal level
+2: turbo level
+
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+Tested-by: Jonathan McDowell <noodles@earth.li>
+---
+ arch/arm/boot/dts/qcom-ipq8064.dtsi | 99 +++++++++++++++++++++++++++++
+ 1 file changed, 99 insertions(+)
+
+--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
+@@ -48,6 +48,105 @@
+               };
+       };
++      opp_table_l2: opp_table_l2 {
++              compatible = "operating-points-v2";
++
++              opp-384000000 {
++                      opp-hz = /bits/ 64 <384000000>;
++                      opp-microvolt = <1100000>;
++                      clock-latency-ns = <100000>;
++                      opp-level = <0>;
++              };
++
++              opp-1000000000 {
++                      opp-hz = /bits/ 64 <1000000000>;
++                      opp-microvolt = <1100000>;
++                      clock-latency-ns = <100000>;
++                      opp-level = <1>;
++              };
++
++              opp-1200000000 {
++                      opp-hz = /bits/ 64 <1200000000>;
++                      opp-microvolt = <1150000>;
++                      clock-latency-ns = <100000>;
++                      opp-level = <2>;
++              };
++      };
++
++      opp_table0: opp_table0 {
++              compatible = "operating-points-v2-kryo-cpu";
++              nvmem-cells = <&speedbin_efuse>;
++
++              /*
++               * Voltage thresholds are <target min max>
++               */
++              opp-384000000 {
++                      opp-hz = /bits/ 64 <384000000>;
++                      opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;
++                      opp-microvolt-speed0-pvs1-v0 = <925000 878750 971250>;
++                      opp-microvolt-speed0-pvs2-v0 = <875000 831250 918750>;
++                      opp-microvolt-speed0-pvs3-v0 = <800000 760000 840000>;
++                      opp-supported-hw = <0x1>;
++                      clock-latency-ns = <100000>;
++                      opp-level = <0>;
++              };
++
++              opp-600000000 {
++                      opp-hz = /bits/ 64 <600000000>;
++                      opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;
++                      opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>;
++                      opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>;
++                      opp-microvolt-speed0-pvs3-v0 = <850000 807500 892500>;
++                      opp-supported-hw = <0x1>;
++                      clock-latency-ns = <100000>;
++                      opp-level = <1>;
++              };
++
++              opp-800000000 {
++                      opp-hz = /bits/ 64 <800000000>;
++                      opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;
++                      opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>;
++                      opp-microvolt-speed0-pvs2-v0 = <995000 945250 1044750>;
++                      opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>;
++                      opp-supported-hw = <0x1>;
++                      clock-latency-ns = <100000>;
++                      opp-level = <1>;
++              };
++
++              opp-1000000000 {
++                      opp-hz = /bits/ 64 <1000000000>;
++                      opp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>;
++                      opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;
++                      opp-microvolt-speed0-pvs2-v0 = <1025000 973750 1076250>;
++                      opp-microvolt-speed0-pvs3-v0 = <950000 902500 997500>;
++                      opp-supported-hw = <0x1>;
++                      clock-latency-ns = <100000>;
++                      opp-level = <1>;
++              };
++
++              opp-1200000000 {
++                      opp-hz = /bits/ 64 <1200000000>;
++                      opp-microvolt-speed0-pvs0-v0 = <1200000 1140000 1260000>;
++                      opp-microvolt-speed0-pvs1-v0 = <1125000 1068750 1181250>;
++                      opp-microvolt-speed0-pvs2-v0 = <1075000 1021250 1128750>;
++                      opp-microvolt-speed0-pvs3-v0 = <1000000 950000 1050000>;
++                      opp-supported-hw = <0x1>;
++                      clock-latency-ns = <100000>;
++                      opp-level = <2>;
++              };
++
++              opp-1400000000 {
++                      opp-hz = /bits/ 64 <1400000000>;
++                      opp-microvolt-speed0-pvs0-v0 = <1250000 1187500 1312500>;
++                      opp-microvolt-speed0-pvs1-v0 = <1175000 1116250 1233750>;
++                      opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>;
++                      opp-microvolt-speed0-pvs3-v0 = <1050000 997500 1102500>;
++                      opp-supported-hw = <0x1>;
++                      clock-latency-ns = <100000>;
++                      opp-level = <2>;
++              };
++      };
++
+       thermal-zones {
+               sensor0-thermal {
+                       polling-delay-passive = <0>;
+--- a/arch/arm/boot/dts/qcom-ipq8065.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq8065.dtsi
+@@ -6,3 +6,92 @@
+       model = "Qualcomm Technologies, Inc. IPQ8065";
+       compatible = "qcom,ipq8065", "qcom,ipq8064";
+ };
++
++&opp_table_l2 {
++      /delete-node/opp-1200000000;
++
++      opp-1400000000 {
++              opp-hz = /bits/ 64 <1400000000>;
++              opp-microvolt = <1150000>;
++              clock-latency-ns = <100000>;
++              opp-level = <2>;
++      };
++};
++
++&opp_table0 {
++      /*
++       * On ipq8065 1.2 ghz freq is not present
++       * Remove it to make cpufreq work and not
++       * complain for missing definition
++       */
++
++      /delete-node/opp-1200000000;
++
++      /*
++       * Voltage thresholds are <target min max>
++       */
++      opp-384000000 {
++              opp-microvolt-speed0-pvs0-v0 = <975000 926250 1023750>;
++              opp-microvolt-speed0-pvs1-v0 = <950000 902500 997500>;
++              opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>;
++              opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>;
++              opp-microvolt-speed0-pvs4-v0 = <875000 831250 918750>;
++              opp-microvolt-speed0-pvs5-v0 = <825000 783750 866250>;
++              opp-microvolt-speed0-pvs6-v0 = <775000 736250 813750>;
++      };
++
++      opp-600000000 {
++              opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;
++              opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>;
++              opp-microvolt-speed0-pvs2-v0 = <950000 902500 997500>;
++              opp-microvolt-speed0-pvs3-v0 = <925000 878750 971250>;
++              opp-microvolt-speed0-pvs4-v0 = <900000 855000 945000>;
++              opp-microvolt-speed0-pvs5-v0 = <850000 807500 892500>;
++              opp-microvolt-speed0-pvs6-v0 = <800000 760000 840000>;
++      };
++
++      opp-800000000 {
++              opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;
++              opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>;
++              opp-microvolt-speed0-pvs2-v0 = <1000000 950000 1050000>;
++              opp-microvolt-speed0-pvs3-v0 = <975000 926250 1023750>;
++              opp-microvolt-speed0-pvs4-v0 = <950000 902500 997500>;
++              opp-microvolt-speed0-pvs5-v0 = <900000 855000 945000>;
++              opp-microvolt-speed0-pvs6-v0 = <850000 807500 892500>;
++      };
++
++      opp-1000000000 {
++              opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;
++              opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;
++              opp-microvolt-speed0-pvs2-v0 = <1050000 997500 1102500>;
++              opp-microvolt-speed0-pvs3-v0 = <1025000 973750 1076250>;
++              opp-microvolt-speed0-pvs4-v0 = <1000000 950000 1050000>;
++              opp-microvolt-speed0-pvs5-v0 = <950000 902500 997500>;
++              opp-microvolt-speed0-pvs6-v0 = <900000 855000 945000>;
++      };
++
++      opp-1400000000 {
++              opp-microvolt-speed0-pvs0-v0 = <1175000 1116250 1233750>;
++              opp-microvolt-speed0-pvs1-v0 = <1150000 1092500 1207500>;
++              opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>;
++              opp-microvolt-speed0-pvs3-v0 = <1100000 1045000 1155000>;
++              opp-microvolt-speed0-pvs4-v0 = <1075000 1021250 1128750>;
++              opp-microvolt-speed0-pvs5-v0 = <1025000 973750 1076250>;
++              opp-microvolt-speed0-pvs6-v0 = <975000 926250 1023750>;
++              opp-level = <1>;
++      };
++
++      opp-1725000000 {
++              opp-hz = /bits/ 64 <1725000000>;
++              opp-microvolt-speed0-pvs0-v0 = <1262500 1199375 1325625>;
++              opp-microvolt-speed0-pvs1-v0 = <1225000 1163750 1286250>;
++              opp-microvolt-speed0-pvs2-v0 = <1200000 1140000 1260000>;
++              opp-microvolt-speed0-pvs3-v0 = <1175000 1116250 1233750>;
++              opp-microvolt-speed0-pvs4-v0 = <1150000 1092500 1207500>;
++              opp-microvolt-speed0-pvs5-v0 = <1100000 1045000 1155000>;
++              opp-microvolt-speed0-pvs6-v0 = <1050000 997500 1102500>;
++              opp-supported-hw = <0x1>;
++              clock-latency-ns = <100000>;
++              opp-level = <2>;
++      };
++};
+--- a/arch/arm/boot/dts/qcom-ipq8062.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq8062.dtsi
+@@ -6,3 +6,39 @@
+       model = "Qualcomm Technologies, Inc. IPQ8062";
+       compatible = "qcom,ipq8062", "qcom,ipq8064";
+ };
++
++&opp_table0 {
++      /delete-node/opp-1200000000;
++      /delete-node/opp-1400000000;
++
++      /*
++       * Voltage thresholds are <target min max>
++       */
++      opp-384000000 {
++              opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;
++              opp-microvolt-speed0-pvs1-v0 = < 925000 878750  971250>;
++              opp-microvolt-speed0-pvs2-v0 = < 875000 831250  918750>;
++              opp-microvolt-speed0-pvs3-v0 = < 800000 760000  840000>;
++      };
++
++      opp-600000000 {
++              opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;
++              opp-microvolt-speed0-pvs1-v0 = < 975000 926250 1023750>;
++              opp-microvolt-speed0-pvs2-v0 = < 925000 878750  971250>;
++              opp-microvolt-speed0-pvs3-v0 = < 850000 807500  892500>;
++      };
++
++      opp-800000000 {
++              opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;
++              opp-microvolt-speed0-pvs1-v0 = <1025000  973750 1076250>;
++              opp-microvolt-speed0-pvs2-v0 = < 995000  945250 1044750>;
++              opp-microvolt-speed0-pvs3-v0 = < 900000  855000  945000>;
++      };
++
++      opp-1000000000 {
++              opp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>;
++              opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;
++              opp-microvolt-speed0-pvs2-v0 = <1025000  973750 1076250>;
++              opp-microvolt-speed0-pvs3-v0 = < 950000  902500  997500>;
++      };
++};
diff --git a/target/linux/ipq806x/patches-6.6/107-15-ARM-dts-qcom-add-multiple-missing-binding-for-cpu.patch b/target/linux/ipq806x/patches-6.6/107-15-ARM-dts-qcom-add-multiple-missing-binding-for-cpu.patch
new file mode 100644 (file)
index 0000000..cf27aaa
--- /dev/null
@@ -0,0 +1,153 @@
+From 211fc0c0a63c99b68663a27182e643316c2d8cbe Mon Sep 17 00:00:00 2001
+From: Ansuel Smith <ansuelsmth@gmail.com>
+Date: Tue, 18 Jan 2022 00:07:57 +0100
+Subject: [PATCH v3 15/18] ARM: dts: qcom: add multiple missing binding for cpu
+ and l2 for ipq8064
+
+Add multiple binding for cpu node, l2 node and add idle-states
+definition for ipq8064 dtsi.
+
+Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
+Tested-by: Jonathan McDowell <noodles@earth.li>
+---
+ arch/arm/boot/dts/qcom-ipq8064.dtsi | 36 +++++++++++++++++++++++++++++
+ 1 file changed, 36 insertions(+)
+
+--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
+@@ -30,6 +30,15 @@
+                       next-level-cache = <&L2>;
+                       qcom,acc = <&acc0>;
+                       qcom,saw = <&saw0>;
++                      clocks = <&kraitcc 0>, <&kraitcc 4>;
++                      clock-names = "cpu", "l2";
++                      clock-latency = <100000>;
++                      operating-points-v2 = <&opp_table0>;
++                      voltage-tolerance = <5>;
++                      cooling-min-state = <0>;
++                      cooling-max-state = <10>;
++                      #cooling-cells = <2>;
++                      cpu-idle-states = <&CPU_SPC>;
+               };
+               cpu1: cpu@1 {
+@@ -40,11 +49,35 @@
+                       next-level-cache = <&L2>;
+                       qcom,acc = <&acc1>;
+                       qcom,saw = <&saw1>;
++                      clocks = <&kraitcc 1>, <&kraitcc 4>;
++                      clock-names = "cpu", "l2";
++                      clock-latency = <100000>;
++                      operating-points-v2 = <&opp_table0>;
++                      voltage-tolerance = <5>;
++                      cooling-min-state = <0>;
++                      cooling-max-state = <10>;
++                      #cooling-cells = <2>;
++                      cpu-idle-states = <&CPU_SPC>;
++              };
++
++              idle-states {
++                      CPU_SPC: spc {
++                              compatible = "qcom,idle-state-spc";
++                              status = "disabled";
++                              entry-latency-us = <400>;
++                              exit-latency-us = <900>;
++                              min-residency-us = <3000>;
++                      };
+               };
+               L2: l2-cache {
+                       compatible = "cache";
+                       cache-level = <2>;
++                      qcom,saw = <&saw_l2>;
++
++                      clocks = <&kraitcc 4>;
++                      clock-names = "l2";
++                      operating-points-v2 = <&opp_table_l2>;
+               };
+       };
+--- a/arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi
+@@ -2,6 +2,18 @@
+ #include "qcom-ipq8064.dtsi"
++&cpu0 {
++      cpu-supply = <&smb208_s2a>;
++};
++
++&cpu1 {
++      cpu-supply = <&smb208_s2b>;
++};
++
++&L2 {
++      l2-supply = <&smb208_s1a>;
++};
++
+ &rpm {
+       smb208_regulators: regulators {
+               compatible = "qcom,rpm-smb208-regulators";
+--- a/arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq8064-v2.0-smb208.dtsi
+@@ -2,6 +2,18 @@
+ #include "qcom-ipq8064-v2.0.dtsi"
++&cpu0 {
++      cpu-supply = <&smb208_s2a>;
++};
++
++&cpu1 {
++      cpu-supply = <&smb208_s2b>;
++};
++
++&L2 {
++      l2-supply = <&smb208_s1a>;
++};
++
+ &rpm {
+       smb208_regulators: regulators {
+               compatible = "qcom,rpm-smb208-regulators";
+--- a/arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq8062-smb208.dtsi
+@@ -2,6 +2,18 @@
+ #include "qcom-ipq8062.dtsi"
++&cpu0 {
++      cpu-supply = <&smb208_s2a>;
++};
++
++&cpu1 {
++      cpu-supply = <&smb208_s2b>;
++};
++
++&L2 {
++      l2-supply = <&smb208_s1a>;
++};
++
+ &rpm {
+       smb208_regulators: regulators {
+               compatible = "qcom,rpm-smb208-regulators";
+--- a/arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq8065-smb208.dtsi
+@@ -2,6 +2,18 @@
+ #include "qcom-ipq8065.dtsi"
++&cpu0 {
++      cpu-supply = <&smb208_s2a>;
++};
++
++&cpu1 {
++      cpu-supply = <&smb208_s2b>;
++};
++
++&L2 {
++      l2-supply = <&smb208_s1a>;
++};
++
+ &rpm {
+       smb208_regulators: regulators {
+               compatible = "qcom,rpm-smb208-regulators";
diff --git a/target/linux/ipq806x/patches-6.6/108-01-ARM-dts-qcom-fix-wrong-nad_pins-definition-for-ipq80.patch b/target/linux/ipq806x/patches-6.6/108-01-ARM-dts-qcom-fix-wrong-nad_pins-definition-for-ipq80.patch
new file mode 100644 (file)
index 0000000..6be9334
--- /dev/null
@@ -0,0 +1,29 @@
+From 6c94e0184e56f9e9f1f5d5f54b20758433e498d2 Mon Sep 17 00:00:00 2001
+From: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
+Date: Wed, 15 Jun 2022 16:47:09 +0200
+Subject: [PATCH 1/2] ARM: dts: qcom: fix wrong nad_pins definition for ipq806x
+
+Fix wrong nand_pings definition for bias-disable pins.
+
+Signed-off-by: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
+---
+ arch/arm/boot/dts/qcom-ipq8064.dtsi | 7 ++-----
+ 1 file changed, 2 insertions(+), 5 deletions(-)
+
+--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
+@@ -599,12 +599,9 @@
+                       };
+                       nand_pins: nand_pins {
+-                              mux {
++                              disable {
+                                       pins = "gpio34", "gpio35", "gpio36",
+-                                             "gpio37", "gpio38", "gpio39",
+-                                             "gpio40", "gpio41", "gpio42",
+-                                             "gpio43", "gpio44", "gpio45",
+-                                             "gpio46", "gpio47";
++                                             "gpio37", "gpio38";
+                                       function = "nand";
+                                       drive-strength = <10>;
+                                       bias-disable;
diff --git a/target/linux/ipq806x/patches-6.6/108-02-ARM-dts-qcom-add-MDIO-dedicated-controller-node-for-.patch b/target/linux/ipq806x/patches-6.6/108-02-ARM-dts-qcom-add-MDIO-dedicated-controller-node-for-.patch
new file mode 100644 (file)
index 0000000..a35bb38
--- /dev/null
@@ -0,0 +1,188 @@
+From 504188183408fac0f61b59f5ed8ea1773fe43669 Mon Sep 17 00:00:00 2001
+From: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
+Date: Wed, 15 Jun 2022 16:59:30 +0200
+Subject: [PATCH 2/2] ARM: dts: qcom: add MDIO dedicated controller node for
+ ipq806x
+
+Add MDIO dedicated controller attached to gmac0 and fix rb3011 dts to
+correctly use the new tag.
+
+Signed-off-by: Christian 'Ansuel' Marangi <ansuelsmth@gmail.com>
+---
+ arch/arm/boot/dts/qcom-ipq8064-rb3011.dts | 134 +++++++++++-----------
+ arch/arm/boot/dts/qcom-ipq8064.dtsi       |  14 +++
+ 2 files changed, 81 insertions(+), 67 deletions(-)
+
+--- a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
++++ b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
+@@ -25,73 +25,6 @@
+               device_type = "memory";
+       };
+-      mdio0: mdio-0 {
+-              status = "okay";
+-              compatible = "virtual,mdio-gpio";
+-              gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>,
+-                      <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
+-              #address-cells = <1>;
+-              #size-cells = <0>;
+-
+-              pinctrl-0 = <&mdio0_pins>;
+-              pinctrl-names = "default";
+-
+-              switch0: switch@10 {
+-                      compatible = "qca,qca8337";
+-                      #address-cells = <1>;
+-                      #size-cells = <0>;
+-
+-                      dsa,member = <0 0>;
+-
+-                      pinctrl-0 = <&sw0_reset_pin>;
+-                      pinctrl-names = "default";
+-
+-                      reset-gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;
+-                      reg = <0x10>;
+-
+-                      ports {
+-                              #address-cells = <1>;
+-                              #size-cells = <0>;
+-
+-                              switch0cpu: port@0 {
+-                                      reg = <0>;
+-                                      label = "cpu";
+-                                      ethernet = <&gmac0>;
+-                                      phy-mode = "rgmii-id";
+-                                      fixed-link {
+-                                              speed = <1000>;
+-                                              full-duplex;
+-                                      };
+-                              };
+-
+-                              port@1 {
+-                                      reg = <1>;
+-                                      label = "sw1";
+-                              };
+-
+-                              port@2 {
+-                                      reg = <2>;
+-                                      label = "sw2";
+-                              };
+-
+-                              port@3 {
+-                                      reg = <3>;
+-                                      label = "sw3";
+-                              };
+-
+-                              port@4 {
+-                                      reg = <4>;
+-                                      label = "sw4";
+-                              };
+-
+-                              port@5 {
+-                                      reg = <5>;
+-                                      label = "sw5";
+-                              };
+-                      };
+-              };
+-      };
+-
+       mdio1: mdio-1 {
+               status = "okay";
+               compatible = "virtual,mdio-gpio";
+@@ -222,6 +155,73 @@
+       status = "okay";
+ };
++&mdio0 {
++      status = "okay";
++      compatible = "virtual,mdio-gpio";
++      gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>,
++              <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
++      #address-cells = <1>;
++      #size-cells = <0>;
++
++      pinctrl-0 = <&mdio0_pins>;
++      pinctrl-names = "default";
++
++      switch0: switch@10 {
++              compatible = "qca,qca8337";
++              #address-cells = <1>;
++              #size-cells = <0>;
++
++              dsa,member = <0 0>;
++
++              pinctrl-0 = <&sw0_reset_pin>;
++              pinctrl-names = "default";
++
++              reset-gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;
++              reg = <0x10>;
++
++              ports {
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++
++                      switch0cpu: port@0 {
++                              reg = <0>;
++                              label = "cpu";
++                              ethernet = <&gmac0>;
++                              phy-mode = "rgmii-id";
++                              fixed-link {
++                                      speed = <1000>;
++                                      full-duplex;
++                              };
++                      };
++
++                      port@1 {
++                              reg = <1>;
++                              label = "sw1";
++                      };
++
++                      port@2 {
++                              reg = <2>;
++                              label = "sw2";
++                      };
++
++                      port@3 {
++                              reg = <3>;
++                              label = "sw3";
++                      };
++
++                      port@4 {
++                              reg = <4>;
++                              label = "sw4";
++                      };
++
++                      port@5 {
++                              reg = <5>;
++                              label = "sw5";
++                      };
++              };
++      };
++};
++
+ &gmac0 {
+       status = "okay";
+--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
+@@ -476,6 +476,20 @@
+                       snps,blen = <16 0 0 0 0 0 0>;
+               };
++              mdio0: mdio@37000000 {
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++
++                      compatible = "qcom,ipq8064-mdio", "syscon";
++                      reg = <0x37000000 0x200000>;
++                      resets = <&gcc GMAC_CORE1_RESET>;
++                      reset-names = "stmmaceth";
++                      clocks = <&gcc GMAC_CORE1_CLK>;
++                      clock-names = "stmmaceth";
++
++                      status = "disabled";
++              };
++
+               vsdcc_fixed: vsdcc-regulator {
+                       compatible = "regulator-fixed";
+                       regulator-name = "SDCC Power";
diff --git a/target/linux/ipq806x/patches-6.6/114-01-devfreq-qcom-Add-L2-Krait-Cache-devfreq-scaling-driv.patch b/target/linux/ipq806x/patches-6.6/114-01-devfreq-qcom-Add-L2-Krait-Cache-devfreq-scaling-driv.patch
new file mode 100644 (file)
index 0000000..9de7328
--- /dev/null
@@ -0,0 +1,235 @@
+From b044ae89862132a86fb511648e9c52ea3cdf8c30 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Wed, 5 Aug 2020 14:19:23 +0200
+Subject: [PATCH 1/4] devfreq: qcom: Add L2 Krait Cache devfreq scaling driver
+
+Qcom L2 Krait CPUs use the generic cpufreq-dt driver and doesn't actually
+scale the Cache frequency when the CPU frequency is changed. This
+devfreq driver register with the cpu notifier and scale the Cache
+based on the max Freq across all core as the CPU cache is shared across
+all of them. If provided this also scale the voltage of the regulator
+attached to the CPU cache. The scaling logic is based on the CPU freq
+and the 3 scaling interval are set by the device dts.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ drivers/devfreq/Kconfig               |  11 ++
+ drivers/devfreq/Makefile              |   1 +
+ drivers/devfreq/krait-cache-devfreq.c | 188 ++++++++++++++++++++++++++
+ 3 files changed, 200 insertions(+)
+ create mode 100644 drivers/devfreq/krait-cache-devfreq.c
+
+--- a/drivers/devfreq/Kconfig
++++ b/drivers/devfreq/Kconfig
+@@ -151,6 +151,17 @@ config ARM_SUN8I_A33_MBUS_DEVFREQ
+         This adds the DEVFREQ driver for the MBUS controller in some
+         Allwinner sun8i (A33 through H3) and sun50i (A64 and H5) SoCs.
++config ARM_KRAIT_CACHE_DEVFREQ
++      tristate "Scaling support for Krait CPU Cache Devfreq"
++      depends on ARCH_QCOM || COMPILE_TEST
++      select DEVFREQ_GOV_PASSIVE
++      help
++        This adds the DEVFREQ driver for the Krait CPU L2 Cache shared by all cores.
++
++        The driver register with the cpufreq notifier and find the right frequency
++        based on the max frequency across all core and the range set in the device
++        dts. If provided this scale also the regulator attached to the l2 cache.
++
+ source "drivers/devfreq/event/Kconfig"
+ endif # PM_DEVFREQ
+--- a/drivers/devfreq/Makefile
++++ b/drivers/devfreq/Makefile
+@@ -15,6 +15,7 @@ obj-$(CONFIG_ARM_MEDIATEK_CCI_DEVFREQ)       +
+ obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ)  += rk3399_dmc.o
+ obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ)      += sun8i-a33-mbus.o
+ obj-$(CONFIG_ARM_TEGRA_DEVFREQ)               += tegra30-devfreq.o
++obj-$(CONFIG_ARM_KRAIT_CACHE_DEVFREQ) += krait-cache-devfreq.o
+ # DEVFREQ Event Drivers
+ obj-$(CONFIG_PM_DEVFREQ_EVENT)                += event/
+--- /dev/null
++++ b/drivers/devfreq/krait-cache-devfreq.c
+@@ -0,0 +1,181 @@
++// SPDX-License-Identifier: GPL-2.0
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/cpufreq.h>
++#include <linux/devfreq.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/clk.h>
++#include <linux/slab.h>
++#include <linux/regulator/consumer.h>
++#include <linux/pm_opp.h>
++
++#include "governor.h"
++
++struct krait_cache_data {
++      struct clk *clk;
++      unsigned long idle_freq;
++      int token;
++};
++
++static int krait_cache_config_clk(struct device *dev, struct opp_table *opp_table,
++                      struct dev_pm_opp *old_opp, struct dev_pm_opp *opp,
++                      void *data, bool scaling_down)
++{
++      struct krait_cache_data *kdata;
++      unsigned long old_freq, freq;
++      unsigned long idle_freq;
++      struct clk *clk;
++      int ret;
++
++      kdata = dev_get_drvdata(dev);
++      idle_freq = kdata->idle_freq;
++      clk = kdata->clk;
++
++      old_freq = dev_pm_opp_get_freq(old_opp);
++      freq = dev_pm_opp_get_freq(opp);
++
++      /*
++       * Set to idle bin if switching from normal to high bin
++       * or vice versa. It has been notice that a bug is triggered
++       * in cache scaling when more than one bin is scaled, to fix
++       * this we first need to transition to the base rate and then
++       * to target rate
++       */
++      if (likely(freq != idle_freq && old_freq != idle_freq)) {
++              ret = clk_set_rate(clk, idle_freq);
++              if (ret)
++                      return ret;
++      }
++
++      return clk_set_rate(clk, freq);
++};
++
++static int krait_cache_get_cur_freq(struct device *dev, unsigned long *freq)
++{
++      struct krait_cache_data *data = dev_get_drvdata(dev);
++
++      *freq = clk_get_rate(data->clk);
++
++      return 0;
++};
++
++static int krait_cache_target(struct device *dev, unsigned long *freq,
++                            u32 flags)
++{
++      struct dev_pm_opp *opp;
++
++      opp = dev_pm_opp_find_freq_ceil(dev, freq);
++      if (unlikely(IS_ERR(opp)))
++              return PTR_ERR(opp);
++
++      dev_pm_opp_put(opp);
++
++      return dev_pm_opp_set_rate(dev, *freq);
++};
++
++static int krait_cache_get_dev_status(struct device *dev,
++                                    struct devfreq_dev_status *stat)
++{
++      struct krait_cache_data *data = dev_get_drvdata(dev);
++
++      stat->busy_time = 0;
++      stat->total_time = 0;
++      stat->current_frequency = clk_get_rate(data->clk);
++
++      return 0;
++};
++
++static struct devfreq_dev_profile krait_cache_devfreq_profile = {
++      .target = krait_cache_target,
++      .get_dev_status = krait_cache_get_dev_status,
++      .get_cur_freq = krait_cache_get_cur_freq
++};
++
++static struct devfreq_passive_data devfreq_gov_data = {
++      .parent_type = CPUFREQ_PARENT_DEV,
++};
++
++static int krait_cache_probe(struct platform_device *pdev)
++{
++      struct dev_pm_opp_config config = { };
++      struct device *dev = &pdev->dev;
++      struct krait_cache_data *data;
++      struct devfreq *devfreq;
++      struct dev_pm_opp *opp;
++      struct clk *clk;
++      int ret, token;
++
++      data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
++      if (!data)
++              return -ENOMEM;
++
++      clk = devm_clk_get(dev, "l2");
++      if (IS_ERR(clk))
++              return PTR_ERR(clk);
++
++      config.regulator_names = (const char *[]){ "l2", NULL };
++      config.clk_names = (const char *[]){ "l2", NULL };
++      config.config_clks = krait_cache_config_clk;
++
++      token = dev_pm_opp_set_config(dev, &config);
++      if (token < 0)
++              return token;
++
++      ret = devm_pm_opp_of_add_table(dev);
++      if (ret)
++              goto free_opp;
++
++      opp = dev_pm_opp_find_freq_ceil(dev, &data->idle_freq);
++      if (IS_ERR(opp)) {
++              ret = PTR_ERR(opp);
++              goto free_opp;
++      }
++      dev_pm_opp_put(opp);
++
++      data->token = token;
++      data->clk = clk;
++      dev_set_drvdata(dev, data);
++      devfreq = devm_devfreq_add_device(dev, &krait_cache_devfreq_profile,
++                                        DEVFREQ_GOV_PASSIVE, &devfreq_gov_data);
++      if (IS_ERR(devfreq)) {
++              ret = PTR_ERR(devfreq);
++              goto free_opp;
++      }
++
++      return 0;
++
++free_opp:
++      dev_pm_opp_clear_config(token);
++      return ret;
++};
++
++static int krait_cache_remove(struct platform_device *pdev)
++{
++      struct krait_cache_data *data = dev_get_drvdata(&pdev->dev);
++
++      dev_pm_opp_clear_config(data->token);
++
++      return 0;
++};
++
++static const struct of_device_id krait_cache_match_table[] = {
++      { .compatible = "qcom,krait-cache" },
++      {}
++};
++
++static struct platform_driver krait_cache_driver = {
++      .probe          = krait_cache_probe,
++      .remove         = krait_cache_remove,
++      .driver         = {
++              .name   = "krait-cache-scaling",
++              .of_match_table = krait_cache_match_table,
++      },
++};
++module_platform_driver(krait_cache_driver);
++
++MODULE_DESCRIPTION("Krait CPU Cache Scaling driver");
++MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
++MODULE_LICENSE("GPL v2");
diff --git a/target/linux/ipq806x/patches-6.6/114-02-ARM-dts-qcom-add-krait-cache-compatible-for-ipq806x-.patch b/target/linux/ipq806x/patches-6.6/114-02-ARM-dts-qcom-add-krait-cache-compatible-for-ipq806x-.patch
new file mode 100644 (file)
index 0000000..45f05dd
--- /dev/null
@@ -0,0 +1,50 @@
+From ef124ad0ff8abfbf4ebe3fe6d7dcef4541dec13a Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Thu, 16 Jun 2022 18:39:21 +0200
+Subject: [PATCH] ARM: dts: qcom: add krait-cache compatible for ipq806x dtsi
+
+Add qcom,krait-cache compatible to enable cache devfreq driver for
+ipq806x SoC and move the L2 node to the soc node to make the devfreq
+driver correctly probe.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ arch/arm/boot/dts/qcom-ipq8064.dtsi | 22 +++++++++++-----------
+ 1 file changed, 11 insertions(+), 11 deletions(-)
+
+--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
+@@ -69,16 +69,6 @@
+                               min-residency-us = <3000>;
+                       };
+               };
+-
+-              L2: l2-cache {
+-                      compatible = "cache";
+-                      cache-level = <2>;
+-                      qcom,saw = <&saw_l2>;
+-
+-                      clocks = <&kraitcc 4>;
+-                      clock-names = "l2";
+-                      operating-points-v2 = <&opp_table_l2>;
+-              };
+       };
+       opp_table_l2: opp_table_l2 {
+@@ -1409,6 +1399,16 @@
+                       #reset-cells = <1>;
+               };
++              L2: l2-cache {
++                      compatible = "cache", "qcom,krait-cache";
++                      cache-level = <2>;
++                      qcom,saw = <&saw_l2>;
++
++                      clocks = <&kraitcc 4>;
++                      clock-names = "l2";
++                      operating-points-v2 = <&opp_table_l2>;
++              };
++
+               lpass@28100000 {
+                       compatible = "qcom,lpass-cpu";
+                       status = "disabled";
diff --git a/target/linux/ipq806x/patches-6.6/115-01-devfreq-add-ipq806x-fabric-scaling-driver.patch b/target/linux/ipq806x/patches-6.6/115-01-devfreq-add-ipq806x-fabric-scaling-driver.patch
new file mode 100644 (file)
index 0000000..c9cd3eb
--- /dev/null
@@ -0,0 +1,203 @@
+From 13f075999935bb696dbab63243923179f06fa05e Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Thu, 16 Jun 2022 19:56:08 +0200
+Subject: [PATCH 3/4] devfreq: add ipq806x fabric scaling driver
+
+Add ipq806x fabric scaling driver using the devfreq passive governor.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ drivers/devfreq/Kconfig               |  11 ++
+ drivers/devfreq/Makefile              |   1 +
+ drivers/devfreq/ipq806x-fab-devfreq.c | 155 ++++++++++++++++++++++++++
+ 3 files changed, 167 insertions(+)
+ create mode 100644 drivers/devfreq/ipq806x-fab-devfreq.c
+
+--- a/drivers/devfreq/Kconfig
++++ b/drivers/devfreq/Kconfig
+@@ -162,6 +162,17 @@ config ARM_KRAIT_CACHE_DEVFREQ
+         based on the max frequency across all core and the range set in the device
+         dts. If provided this scale also the regulator attached to the l2 cache.
++config ARM_IPQ806X_FAB_DEVFREQ
++      tristate "Scaling support for ipq806x Soc Fabric"
++      depends on ARCH_QCOM || COMPILE_TEST
++      select DEVFREQ_GOV_PASSIVE
++      help
++        This adds the DEVFREQ driver for the ipq806x Soc Fabric.
++
++        The driver register with the cpufreq notifier and find the right frequency
++        based on the max frequency across all core and the range set in the device
++        dts.
++
+ source "drivers/devfreq/event/Kconfig"
+ endif # PM_DEVFREQ
+--- a/drivers/devfreq/Makefile
++++ b/drivers/devfreq/Makefile
+@@ -16,6 +16,7 @@ obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) +=
+ obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ)      += sun8i-a33-mbus.o
+ obj-$(CONFIG_ARM_TEGRA_DEVFREQ)               += tegra30-devfreq.o
+ obj-$(CONFIG_ARM_KRAIT_CACHE_DEVFREQ) += krait-cache-devfreq.o
++obj-$(CONFIG_ARM_IPQ806X_FAB_DEVFREQ) += ipq806x-fab-devfreq.o
+ # DEVFREQ Event Drivers
+ obj-$(CONFIG_PM_DEVFREQ_EVENT)                += event/
+--- /dev/null
++++ b/drivers/devfreq/ipq806x-fab-devfreq.c
+@@ -0,0 +1,155 @@
++// SPDX-License-Identifier: GPL-2.0
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/cpufreq.h>
++#include <linux/devfreq.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/clk.h>
++#include <linux/slab.h>
++#include <linux/pm_opp.h>
++
++#include "governor.h"
++
++struct ipq806x_fab_data {
++      struct clk *fab_clk;
++      struct clk *ddr_clk;
++};
++
++static int ipq806x_fab_get_cur_freq(struct device *dev, unsigned long *freq)
++{
++      struct ipq806x_fab_data *data = dev_get_drvdata(dev);
++
++      *freq = clk_get_rate(data->fab_clk);
++
++      return 0;
++};
++
++static int ipq806x_fab_target(struct device *dev, unsigned long *freq,
++                            u32 flags)
++{
++      struct ipq806x_fab_data *data = dev_get_drvdata(dev);
++      struct dev_pm_opp *opp;
++      int ret;
++
++      opp = dev_pm_opp_find_freq_ceil(dev, freq);
++      if (unlikely(IS_ERR(opp)))
++              return PTR_ERR(opp);
++
++      dev_pm_opp_put(opp);
++
++      ret = clk_set_rate(data->fab_clk, *freq);
++      if (ret)
++              return ret;
++
++      return clk_set_rate(data->ddr_clk, *freq);
++};
++
++static int ipq806x_fab_get_dev_status(struct device *dev,
++                                    struct devfreq_dev_status *stat)
++{
++      struct ipq806x_fab_data *data = dev_get_drvdata(dev);
++
++      stat->busy_time = 0;
++      stat->total_time = 0;
++      stat->current_frequency = clk_get_rate(data->fab_clk);
++
++      return 0;
++};
++
++static struct devfreq_dev_profile ipq806x_fab_devfreq_profile = {
++      .target = ipq806x_fab_target,
++      .get_dev_status = ipq806x_fab_get_dev_status,
++      .get_cur_freq = ipq806x_fab_get_cur_freq
++};
++
++static struct devfreq_passive_data devfreq_gov_data = {
++      .parent_type = CPUFREQ_PARENT_DEV,
++};
++
++static int ipq806x_fab_probe(struct platform_device *pdev)
++{
++      struct device *dev = &pdev->dev;
++      struct ipq806x_fab_data *data;
++      struct devfreq *devfreq;
++      struct clk *clk;
++      int ret;
++
++      data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
++      if (!data)
++              return -ENOMEM;
++
++      clk = devm_clk_get(dev, "apps-fab-clk");
++      if (IS_ERR(clk)) {
++              dev_err_probe(dev, PTR_ERR(clk), "failed to get apps fab clk\n");
++              return PTR_ERR(clk);
++      }
++
++      clk_prepare_enable(clk);
++      data->fab_clk = clk;
++
++      clk = devm_clk_get(dev, "ddr-fab-clk");
++      if (IS_ERR(clk)) {
++              dev_err_probe(dev, PTR_ERR(clk), "failed to get ddr fab clk\n");
++              goto err_ddr;
++      }
++
++      clk_prepare_enable(clk);
++      data->ddr_clk = clk;
++
++      ret = dev_pm_opp_of_add_table(dev);
++      if (ret) {
++              dev_err(dev, "failed to parse fab freq thresholds\n");
++              return ret;
++      }
++
++      dev_set_drvdata(dev, data);
++
++      devfreq = devm_devfreq_add_device(&pdev->dev, &ipq806x_fab_devfreq_profile,
++                                        DEVFREQ_GOV_PASSIVE, &devfreq_gov_data);
++      if (IS_ERR(devfreq))
++              dev_pm_opp_remove_table(dev);
++
++      return PTR_ERR_OR_ZERO(devfreq);
++
++err_ddr:
++      clk_unprepare(data->fab_clk);
++      clk_put(data->fab_clk);
++      return PTR_ERR(clk);
++};
++
++static int ipq806x_fab_remove(struct platform_device *pdev)
++{
++      struct ipq806x_fab_data *data = dev_get_drvdata(&pdev->dev);
++
++      clk_unprepare(data->fab_clk);
++      clk_put(data->fab_clk);
++
++      clk_unprepare(data->ddr_clk);
++      clk_put(data->ddr_clk);
++
++      dev_pm_opp_remove_table(&pdev->dev);
++
++      return 0;
++};
++
++static const struct of_device_id ipq806x_fab_match_table[] = {
++      { .compatible = "qcom,fab-scaling" },
++      {}
++};
++
++static struct platform_driver ipq806x_fab_driver = {
++      .probe          = ipq806x_fab_probe,
++      .remove         = ipq806x_fab_remove,
++      .driver         = {
++              .name   = "ipq806x-fab-scaling",
++              .of_match_table = ipq806x_fab_match_table,
++      },
++};
++module_platform_driver(ipq806x_fab_driver);
++
++MODULE_DESCRIPTION("ipq806x Fab Scaling driver");
++MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
++MODULE_LICENSE("GPL v2");
diff --git a/target/linux/ipq806x/patches-6.6/115-02-ARM-dts-qcom-add-fab-scaling-node-for-ipq806x.patch b/target/linux/ipq806x/patches-6.6/115-02-ARM-dts-qcom-add-fab-scaling-node-for-ipq806x.patch
new file mode 100644 (file)
index 0000000..24e0ecf
--- /dev/null
@@ -0,0 +1,48 @@
+From c3573f0907dadb0a6e9933aae2a46a489abcbd48 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Thu, 16 Jun 2022 20:03:05 +0200
+Subject: [PATCH 4/4] ARM: dts: qcom: add fab scaling node for ipq806x
+
+Add fabric scaling node for ipq806x to correctly scale apps and ddr
+fabric clk.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ arch/arm/boot/dts/qcom-ipq8064.dtsi | 19 +++++++++++++++++++
+ 1 file changed, 19 insertions(+)
+
+--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
+@@ -170,6 +170,18 @@
+               };
+       };
++      opp_table_fab: opp_table_fab {
++              compatible = "operating-points-v2";
++
++              opp-533000000 {
++                      opp-hz = /bits/ 64 <533000000>;
++              };
++
++              opp-400000000 {
++                      opp-hz = /bits/ 64 <400000000>;
++              };
++      };
++
+       thermal-zones {
+               sensor0-thermal {
+                       polling-delay-passive = <0>;
+@@ -1409,6 +1421,13 @@
+                       operating-points-v2 = <&opp_table_l2>;
+               };
++              fab-scaling {
++                      compatible = "qcom,fab-scaling";
++                      clocks = <&rpmcc RPM_APPS_FABRIC_A_CLK>, <&rpmcc RPM_EBI1_A_CLK>;
++                      clock-names = "apps-fab-clk", "ddr-fab-clk";
++                      operating-points-v2 = <&opp_table_fab>;
++              };
++
+               lpass@28100000 {
+                       compatible = "qcom,lpass-cpu";
+                       status = "disabled";
diff --git a/target/linux/ipq806x/patches-6.6/122-01-clk-qcom-krait-cc-handle-qsb-clock-defined-in-DTS.patch b/target/linux/ipq806x/patches-6.6/122-01-clk-qcom-krait-cc-handle-qsb-clock-defined-in-DTS.patch
new file mode 100644 (file)
index 0000000..c30c245
--- /dev/null
@@ -0,0 +1,47 @@
+From 666c1b745e93ccddde841d5057c33f97b29a316a Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Thu, 15 Sep 2022 02:19:28 +0200
+Subject: [PATCH 3/9] clk: qcom: krait-cc: handle qsb clock defined in DTS
+
+qsb fixed clk may be defined in DTS and correctly passed in the clocks
+list. Add related code to handle this and modify the logic to
+dynamically read qsb clock frequency.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ drivers/clk/qcom/krait-cc.c | 14 +++++++++++---
+ 1 file changed, 11 insertions(+), 3 deletions(-)
+
+--- a/drivers/clk/qcom/krait-cc.c
++++ b/drivers/clk/qcom/krait-cc.c
+@@ -348,7 +348,7 @@ static int krait_cc_probe(struct platfor
+ {
+       struct device *dev = &pdev->dev;
+       const struct of_device_id *id;
+-      unsigned long cur_rate, aux_rate;
++      unsigned long cur_rate, aux_rate, qsb_rate;
+       int cpu;
+       struct clk_hw *mux, *l2_pri_mux;
+       struct clk *clk, **clks;
+@@ -357,11 +357,19 @@ static int krait_cc_probe(struct platfor
+       if (!id)
+               return -ENODEV;
+-      /* Rate is 1 because 0 causes problems for __clk_mux_determine_rate */
+-      clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1);
++      /*
++       * Per Documentation qsb should be provided from DTS.
++       * To address old implementation, register the fixed clock anyway.
++       * Rate is 1 because 0 causes problems for __clk_mux_determine_rate
++       */
++      clk = clk_get(dev, "qsb");
++      if (IS_ERR(clk))
++              clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1);
+       if (IS_ERR(clk))
+               return PTR_ERR(clk);
++      qsb_rate = clk_get_rate(clk);
++
+       if (!id->data) {
+               clk = clk_register_fixed_factor(dev, "acpu_aux",
+                                               "gpll0_vote", 0, 1, 2);
diff --git a/target/linux/ipq806x/patches-6.6/122-02-clk-qcom-krait-cc-register-REAL-qsb-fixed-clock.patch b/target/linux/ipq806x/patches-6.6/122-02-clk-qcom-krait-cc-register-REAL-qsb-fixed-clock.patch
new file mode 100644 (file)
index 0000000..e2f78f7
--- /dev/null
@@ -0,0 +1,36 @@
+From fca6f185a9d9ef0892a719bc6da955b22d326ec7 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Thu, 15 Sep 2022 02:24:33 +0200
+Subject: [PATCH 4/9] clk: qcom: krait-cc: register REAL qsb fixed clock
+
+With some tools it was discovered the real frequency of the qsb fixed
+clock. While not 100% correct it's still better than using 1 as a dummy
+frequency.
+Correctly register the qsb fixed clock with the frequency of 225 MHz
+instead of 1.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ drivers/clk/qcom/krait-cc.c | 8 +++++---
+ 1 file changed, 5 insertions(+), 3 deletions(-)
+
+--- a/drivers/clk/qcom/krait-cc.c
++++ b/drivers/clk/qcom/krait-cc.c
+@@ -25,6 +25,8 @@ enum {
+       clks_max,
+ };
++#define QSB_RATE      2250000000
++
+ static unsigned int sec_mux_map[] = {
+       2,
+       0,
+@@ -364,7 +366,7 @@ static int krait_cc_probe(struct platfor
+        */
+       clk = clk_get(dev, "qsb");
+       if (IS_ERR(clk))
+-              clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1);
++              clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, QSB_RATE);
+       if (IS_ERR(clk))
+               return PTR_ERR(clk);
diff --git a/target/linux/ipq806x/patches-6.6/122-03-clk-qcom-krait-cc-drop-pr_info-and-use-dev_info.patch b/target/linux/ipq806x/patches-6.6/122-03-clk-qcom-krait-cc-drop-pr_info-and-use-dev_info.patch
new file mode 100644 (file)
index 0000000..d95a63f
--- /dev/null
@@ -0,0 +1,44 @@
+From 2399d181557d94ae9a2686926cd25768f132e4b4 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Fri, 18 Mar 2022 16:12:14 +0100
+Subject: [PATCH 7/9] clk: qcom: krait-cc: drop pr_info and use dev_info
+
+Replace pr_info() with dev_info() to provide better diagnostics.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ drivers/clk/qcom/krait-cc.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+--- a/drivers/clk/qcom/krait-cc.c
++++ b/drivers/clk/qcom/krait-cc.c
+@@ -423,25 +423,25 @@ static int krait_cc_probe(struct platfor
+       cur_rate = clk_get_rate(clks[l2_mux]);
+       aux_rate = 384000000;
+       if (cur_rate < aux_rate) {
+-              pr_info("L2 @ Undefined rate. Forcing new rate.\n");
++              dev_info(dev, "L2 @ Undefined rate. Forcing new rate.\n");
+               cur_rate = aux_rate;
+       }
+       clk_set_rate(clks[l2_mux], aux_rate);
+       clk_set_rate(clks[l2_mux], 2);
+       clk_set_rate(clks[l2_mux], cur_rate);
+-      pr_info("L2 @ %lu KHz\n", clk_get_rate(clks[l2_mux]) / 1000);
++      dev_info(dev, "L2 @ %lu KHz\n", clk_get_rate(clks[l2_mux]) / 1000);
+       for_each_possible_cpu(cpu) {
+               clk = clks[cpu];
+               cur_rate = clk_get_rate(clk);
+               if (cur_rate < aux_rate) {
+-                      pr_info("CPU%d @ Undefined rate. Forcing new rate.\n", cpu);
++                      dev_info(dev, "CPU%d @ Undefined rate. Forcing new rate.\n", cpu);
+                       cur_rate = aux_rate;
+               }
+               clk_set_rate(clk, aux_rate);
+               clk_set_rate(clk, 2);
+               clk_set_rate(clk, cur_rate);
+-              pr_info("CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000);
++              dev_info(dev, "CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000);
+       }
+       of_clk_add_provider(dev->of_node, krait_of_get, clks);
diff --git a/target/linux/ipq806x/patches-6.6/122-04-clk-qcom-krait-cc-rework-mux-reset-logic-and-reset-h.patch b/target/linux/ipq806x/patches-6.6/122-04-clk-qcom-krait-cc-rework-mux-reset-logic-and-reset-h.patch
new file mode 100644 (file)
index 0000000..8f88e06
--- /dev/null
@@ -0,0 +1,88 @@
+From 6a77cf3f5f95ec0058e1b4d1ada018748cb0b83b Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Thu, 15 Sep 2022 03:33:13 +0200
+Subject: [PATCH 9/9] clk: qcom: krait-cc: rework mux reset logic and reset
+ hfpll
+
+Rework and clean mux reset logic.
+Compact it to a for loop to handle both CPU and L2 in one place.
+Move hardcoded aux_rate to define and add a new hfpll_rate value to
+reset hfpll settings.
+Change logic to now reset the hfpll to the lowest value of 600 Mhz and
+then restoring the previous frequency. This permits to reset the hfpll if
+the primary mux was set to source out of the secondary mux.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ drivers/clk/qcom/krait-cc.c | 50 +++++++++++++++++--------------------
+ 1 file changed, 23 insertions(+), 27 deletions(-)
+
+--- a/drivers/clk/qcom/krait-cc.c
++++ b/drivers/clk/qcom/krait-cc.c
+@@ -25,7 +25,9 @@ enum {
+       clks_max,
+ };
+-#define QSB_RATE      2250000000
++#define QSB_RATE      225000000
++#define AUX_RATE      384000000
++#define HFPLL_RATE    600000000
+ static unsigned int sec_mux_map[] = {
+       2,
+@@ -350,7 +352,7 @@ static int krait_cc_probe(struct platfor
+ {
+       struct device *dev = &pdev->dev;
+       const struct of_device_id *id;
+-      unsigned long cur_rate, aux_rate, qsb_rate;
++      unsigned long cur_rate, qsb_rate;
+       int cpu;
+       struct clk_hw *mux, *l2_pri_mux;
+       struct clk *clk, **clks;
+@@ -420,28 +422,29 @@ static int krait_cc_probe(struct platfor
+        * two different rates to force a HFPLL reinit under all
+        * circumstances.
+        */
+-      cur_rate = clk_get_rate(clks[l2_mux]);
+-      aux_rate = 384000000;
+-      if (cur_rate < aux_rate) {
+-              dev_info(dev, "L2 @ Undefined rate. Forcing new rate.\n");
+-              cur_rate = aux_rate;
+-      }
+-      clk_set_rate(clks[l2_mux], aux_rate);
+-      clk_set_rate(clks[l2_mux], 2);
+-      clk_set_rate(clks[l2_mux], cur_rate);
+-      dev_info(dev, "L2 @ %lu KHz\n", clk_get_rate(clks[l2_mux]) / 1000);
+-      for_each_possible_cpu(cpu) {
++      for (cpu = 0; cpu < 5; cpu++) {
++              const char *l2_s = "L2";
++              char cpu_s[5];
++
+               clk = clks[cpu];
++              if (!clk)
++                      continue;
++
++              if (cpu < 4)
++                      snprintf(cpu_s, 5, "CPU%d", cpu);
++
+               cur_rate = clk_get_rate(clk);
+-              if (cur_rate < aux_rate) {
+-                      dev_info(dev, "CPU%d @ Undefined rate. Forcing new rate.\n", cpu);
+-                      cur_rate = aux_rate;
++              if (cur_rate < AUX_RATE) {
++                      dev_info(dev, "%s @ Undefined rate. Forcing new rate.\n",
++                               cpu < 4 ? cpu_s : l2_s);
++                      cur_rate = AUX_RATE;
+               }
+-              clk_set_rate(clk, aux_rate);
+-              clk_set_rate(clk, 2);
++              clk_set_rate(clk, AUX_RATE);
++              clk_set_rate(clk, HFPLL_RATE);
+               clk_set_rate(clk, cur_rate);
+-              dev_info(dev, "CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000);
++              dev_info(dev, "%s @ %lu KHz\n", cpu < 4 ? cpu_s : l2_s,
++                       clk_get_rate(clk) / 1000);
+       }
+       of_clk_add_provider(dev->of_node, krait_of_get, clks);
diff --git a/target/linux/ipq806x/patches-6.6/122-05-clk-qcom-clk-krait-generilize-div-functions.patch b/target/linux/ipq806x/patches-6.6/122-05-clk-qcom-clk-krait-generilize-div-functions.patch
new file mode 100644 (file)
index 0000000..a7c0f04
--- /dev/null
@@ -0,0 +1,156 @@
+From 908c361b3c3a139eb3e6a798cb620a6da7514d5c Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Fri, 23 Sep 2022 19:05:39 +0200
+Subject: [PATCH 2/4] clk: qcom: clk-krait: generilize div functions
+
+Generilize div functions and remove hardcode to a divisor of 2.
+This is just a cleanup and permit to make it more clear the settings of
+the devisor when used by the krait-cc driver.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ drivers/clk/qcom/clk-krait.c | 57 ++++++++++++++++++++----------------
+ drivers/clk/qcom/clk-krait.h | 11 ++++---
+ drivers/clk/qcom/krait-cc.c  |  7 +++--
+ 3 files changed, 42 insertions(+), 33 deletions(-)
+
+--- a/drivers/clk/qcom/clk-krait.c
++++ b/drivers/clk/qcom/clk-krait.c
+@@ -97,53 +97,58 @@ const struct clk_ops krait_mux_clk_ops =
+ EXPORT_SYMBOL_GPL(krait_mux_clk_ops);
+ /* The divider can divide by 2, 4, 6 and 8. But we only really need div-2. */
+-static long krait_div2_round_rate(struct clk_hw *hw, unsigned long rate,
++static long krait_div_round_rate(struct clk_hw *hw, unsigned long rate,
+                                 unsigned long *parent_rate)
+ {
+-      *parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), rate * 2);
+-      return DIV_ROUND_UP(*parent_rate, 2);
++      struct krait_div_clk *d = to_krait_div_clk(hw);
++
++      *parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
++                                       rate * d->divisor);
++
++      return DIV_ROUND_UP(*parent_rate, d->divisor);
+ }
+-static int krait_div2_set_rate(struct clk_hw *hw, unsigned long rate,
++static int krait_div_set_rate(struct clk_hw *hw, unsigned long rate,
+                              unsigned long parent_rate)
+ {
+-      struct krait_div2_clk *d = to_krait_div2_clk(hw);
++      struct krait_div_clk *d = to_krait_div_clk(hw);
++      u8 div_val = krait_div_to_val(d->divisor);
+       unsigned long flags;
+-      u32 val;
+-      u32 mask = BIT(d->width) - 1;
+-
+-      if (d->lpl)
+-              mask = mask << (d->shift + LPL_SHIFT) | mask << d->shift;
+-      else
+-              mask <<= d->shift;
++      u32 regval;
+       spin_lock_irqsave(&krait_clock_reg_lock, flags);
+-      val = krait_get_l2_indirect_reg(d->offset);
+-      val &= ~mask;
+-      krait_set_l2_indirect_reg(d->offset, val);
++      regval = krait_get_l2_indirect_reg(d->offset);
++
++      regval &= ~(d->mask << d->shift);
++      regval |= (div_val & d->mask) << d->shift;
++
++      if (d->lpl) {
++              regval &= ~(d->mask << (d->shift + LPL_SHIFT));
++              regval |= (div_val & d->mask) << (d->shift + LPL_SHIFT);
++      }
++
++      krait_set_l2_indirect_reg(d->offset, regval);
+       spin_unlock_irqrestore(&krait_clock_reg_lock, flags);
+       return 0;
+ }
+ static unsigned long
+-krait_div2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
++krait_div_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+ {
+-      struct krait_div2_clk *d = to_krait_div2_clk(hw);
+-      u32 mask = BIT(d->width) - 1;
++      struct krait_div_clk *d = to_krait_div_clk(hw);
+       u32 div;
+       div = krait_get_l2_indirect_reg(d->offset);
+       div >>= d->shift;
+-      div &= mask;
+-      div = (div + 1) * 2;
++      div &= d->mask;
+-      return DIV_ROUND_UP(parent_rate, div);
++      return DIV_ROUND_UP(parent_rate, krait_val_to_div(div));
+ }
+-const struct clk_ops krait_div2_clk_ops = {
+-      .round_rate = krait_div2_round_rate,
+-      .set_rate = krait_div2_set_rate,
+-      .recalc_rate = krait_div2_recalc_rate,
++const struct clk_ops krait_div_clk_ops = {
++      .round_rate = krait_div_round_rate,
++      .set_rate = krait_div_set_rate,
++      .recalc_rate = krait_div_recalc_rate,
+ };
+-EXPORT_SYMBOL_GPL(krait_div2_clk_ops);
++EXPORT_SYMBOL_GPL(krait_div_clk_ops);
+--- a/drivers/clk/qcom/clk-krait.h
++++ b/drivers/clk/qcom/clk-krait.h
+@@ -25,17 +25,20 @@ struct krait_mux_clk {
+ extern const struct clk_ops krait_mux_clk_ops;
+-struct krait_div2_clk {
++struct krait_div_clk {
+       u32             offset;
+-      u8              width;
++      u32             mask;
++      u8              divisor;
+       u32             shift;
+       bool            lpl;
+       struct clk_hw   hw;
+ };
+-#define to_krait_div2_clk(_hw) container_of(_hw, struct krait_div2_clk, hw)
++#define to_krait_div_clk(_hw) container_of(_hw, struct krait_div_clk, hw)
++#define krait_div_to_val(_div)                ((_div) / 2) - 1
++#define krait_val_to_div(_val)                ((_val) + 1) * 2
+-extern const struct clk_ops krait_div2_clk_ops;
++extern const struct clk_ops krait_div_clk_ops;
+ #endif
+--- a/drivers/clk/qcom/krait-cc.c
++++ b/drivers/clk/qcom/krait-cc.c
+@@ -86,11 +86,11 @@ static int krait_notifier_register(struc
+ static struct clk_hw *
+ krait_add_div(struct device *dev, int id, const char *s, unsigned int offset)
+ {
+-      struct krait_div2_clk *div;
++      struct krait_div_clk *div;
+       static struct clk_parent_data p_data[1];
+       struct clk_init_data init = {
+               .num_parents = ARRAY_SIZE(p_data),
+-              .ops = &krait_div2_clk_ops,
++              .ops = &krait_div_clk_ops,
+               .flags = CLK_SET_RATE_PARENT,
+       };
+       struct clk_hw *clk;
+@@ -101,7 +101,8 @@ krait_add_div(struct device *dev, int id
+       if (!div)
+               return ERR_PTR(-ENOMEM);
+-      div->width = 2;
++      div->mask = 0x3;
++      div->divisor = 2;
+       div->shift = 6;
+       div->lpl = id >= 0;
+       div->offset = offset;
diff --git a/target/linux/ipq806x/patches-6.6/123-clk-qcom-gcc-ipq806x-remove-cc_register_board-for.patch b/target/linux/ipq806x/patches-6.6/123-clk-qcom-gcc-ipq806x-remove-cc_register_board-for.patch
new file mode 100644 (file)
index 0000000..0df29a0
--- /dev/null
@@ -0,0 +1,31 @@
+From ac84ac819a2e8fd3d87122b452c502a386c54437 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 5 Jul 2022 18:30:18 +0200
+Subject: [PATCH v2 4/4] clk: qcom: gcc-ipq806x: remove cc_register_board for
+ pxo and cxo
+
+Now that these clock are defined as fixed clk in dts, we can drop the
+register_board_clk for cxo_board and pxo_board in gcc_ipq806x_probe.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ drivers/clk/qcom/gcc-ipq806x.c | 8 --------
+ 1 file changed, 8 deletions(-)
+
+--- a/drivers/clk/qcom/gcc-ipq806x.c
++++ b/drivers/clk/qcom/gcc-ipq806x.c
+@@ -3386,14 +3386,6 @@ static int gcc_ipq806x_probe(struct plat
+       struct regmap *regmap;
+       int ret;
+-      ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 25000000);
+-      if (ret)
+-              return ret;
+-
+-      ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 25000000);
+-      if (ret)
+-              return ret;
+-
+       if (of_machine_is_compatible("qcom,ipq8065")) {
+               ubi32_core1_src_clk.freq_tbl = clk_tbl_nss_ipq8065;
+               ubi32_core2_src_clk.freq_tbl = clk_tbl_nss_ipq8065;
diff --git a/target/linux/ipq806x/patches-6.6/850-soc-add-qualcomm-syscon.patch b/target/linux/ipq806x/patches-6.6/850-soc-add-qualcomm-syscon.patch
new file mode 100644 (file)
index 0000000..397c448
--- /dev/null
@@ -0,0 +1,121 @@
+From: Christian Lamparter <chunkeey@googlemail.com>
+Subject: SoC: add qualcomm syscon
+--- a/drivers/soc/qcom/Makefile
++++ b/drivers/soc/qcom/Makefile
+@@ -23,6 +23,7 @@ obj-$(CONFIG_QCOM_SOCINFO)   += socinfo.o
+ obj-$(CONFIG_QCOM_SPM)                += spm.o
+ obj-$(CONFIG_QCOM_STATS)      += qcom_stats.o
+ obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o
++obj-$(CONFIG_QCOM_TCSR)        += qcom_tcsr.o
+ obj-$(CONFIG_QCOM_APR) += apr.o
+ obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o
+ obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o
+--- a/drivers/soc/qcom/Kconfig
++++ b/drivers/soc/qcom/Kconfig
+@@ -213,6 +213,13 @@ config QCOM_STATS
+         various SoC level low power modes statistics and export to debugfs
+         interface.
++config QCOM_TCSR
++      tristate "QCOM Top Control and Status Registers"
++      depends on ARCH_QCOM
++      help
++        Say y here to enable TCSR support.  The TCSR provides control
++        functions for various peripherals.
++
+ config QCOM_WCNSS_CTRL
+       tristate "Qualcomm WCNSS control driver"
+       depends on ARCH_QCOM || COMPILE_TEST
+--- /dev/null
++++ b/drivers/soc/qcom/qcom_tcsr.c
+@@ -0,0 +1,64 @@
++/*
++ * Copyright (c) 2014, The Linux foundation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License rev 2 and
++ * only rev 2 as published by the free Software foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/clk.h>
++#include <linux/err.h>
++#include <linux/io.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_platform.h>
++#include <linux/platform_device.h>
++
++#define TCSR_USB_PORT_SEL     0xb0
++
++static int tcsr_probe(struct platform_device *pdev)
++{
++      struct resource *res;
++      const struct device_node *node = pdev->dev.of_node;
++      void __iomem *base;
++      u32 val;
++
++      res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++      base = devm_ioremap_resource(&pdev->dev, res);
++      if (IS_ERR(base))
++              return PTR_ERR(base);
++
++      if (!of_property_read_u32(node, "qcom,usb-ctrl-select", &val)) {
++              dev_err(&pdev->dev, "setting usb port select = %d\n", val);
++              writel(val, base + TCSR_USB_PORT_SEL);
++      }
++
++      return 0;
++}
++
++static const struct of_device_id tcsr_dt_match[] = {
++      { .compatible = "qcom,tcsr", },
++      { },
++};
++
++MODULE_DEVICE_TABLE(of, tcsr_dt_match);
++
++static struct platform_driver tcsr_driver = {
++      .driver = {
++              .name           = "tcsr",
++              .owner          = THIS_MODULE,
++              .of_match_table = tcsr_dt_match,
++      },
++      .probe = tcsr_probe,
++};
++
++module_platform_driver(tcsr_driver);
++
++MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
++MODULE_DESCRIPTION("QCOM TCSR driver");
++MODULE_LICENSE("GPL v2");
+--- /dev/null
++++ b/include/dt-bindings/soc/qcom,tcsr.h
+@@ -0,0 +1,23 @@
++/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 and
++ * only version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++#ifndef __DT_BINDINGS_QCOM_TCSR_H
++#define __DT_BINDINGS_QCOM_TCSR_H
++
++#define TCSR_USB_SELECT_USB3_P0               0x1
++#define TCSR_USB_SELECT_USB3_P1               0x2
++#define TCSR_USB_SELECT_USB3_DUAL     0x3
++
++/* TCSR A/B REG */
++#define IPQ806X_TCSR_REG_A_ADM_CRCI_MUX_SEL     0
++#define IPQ806X_TCSR_REG_B_ADM_CRCI_MUX_SEL     1
++
++#endif
diff --git a/target/linux/ipq806x/patches-6.6/900-arm-add-cmdline-override.patch b/target/linux/ipq806x/patches-6.6/900-arm-add-cmdline-override.patch
new file mode 100644 (file)
index 0000000..c958354
--- /dev/null
@@ -0,0 +1,37 @@
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -1589,6 +1589,14 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
+ endchoice
++config CMDLINE_OVERRIDE
++      bool "Use alternative cmdline from device tree"
++      help
++        Some bootloaders may have uneditable bootargs. While CMDLINE_FORCE can
++        be used, this is not a good option for kernels that are shared across
++        devices. This setting enables using "chosen/cmdline-override" as the
++        cmdline if it exists in the device tree.
++
+ config CMDLINE
+       string "Default kernel command string"
+       default ""
+--- a/drivers/of/fdt.c
++++ b/drivers/of/fdt.c
+@@ -1187,6 +1187,17 @@ int __init early_init_dt_scan_chosen(cha
+       if (p != NULL && l > 0)
+               strlcat(cmdline, p, min_t(int, strlen(cmdline) + (int)l, COMMAND_LINE_SIZE));
++    /* CONFIG_CMDLINE_OVERRIDE is used to fallback to a different
++     * device tree option of chosen/bootargs-override. This is
++     * helpful on boards where u-boot sets bootargs, and is unable
++     * to be modified.
++     */
++#ifdef CONFIG_CMDLINE_OVERRIDE
++      p = of_get_flat_dt_prop(node, "bootargs-override", &l);
++      if (p != NULL && l > 0)
++              strlcpy(cmdline, p, min((int)l, COMMAND_LINE_SIZE));
++#endif
++
+ handle_cmdline:
+       /*
+        * CONFIG_CMDLINE is meant to be a default in case nothing else
diff --git a/target/linux/ipq806x/patches-6.6/901-01-ARM-decompressor-support-memory-start-validation-.patch b/target/linux/ipq806x/patches-6.6/901-01-ARM-decompressor-support-memory-start-validation-.patch
new file mode 100644 (file)
index 0000000..04e2a0c
--- /dev/null
@@ -0,0 +1,75 @@
+From 2f86b9b71a11f86e3d850214ab781ebb17d7260e Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Fri, 19 Jan 2024 19:48:30 +0100
+Subject: [PATCH v2 1/2] ARM: decompressor: support memory start validation for
+ appended DTB
+
+There is currently a problem with a very specific sets of kernel config
+and AUTO_ZRELADDR.
+
+For the most common case AUTO_ZRELADDR check the PC register and
+calculate the start of the physical memory. Then fdt_check_mem_start is
+called to make sure the detected value makes sense by comparing it with
+what is present in DTB in the memory nodes and if additional fixup are
+required with the use of linux,usable-memory-range in the chosen node to
+hardcode usable memory range in case some reserved space needs to be
+addressed. With the help of this function the right address is
+calculated and the kernel correctly decompress and loads.
+
+Things starts to become problematic when in the mix,
+CONFIG_ARM_APPENDED_DTB is used. This is a particular kernel config is
+used when legacy systems doesn't support passing a DTB directly and a
+DTB is appended at the end of the image.
+
+In such case, fdt_check_mem_start is skipped in AUTO_ZRELADDR iteration
+as the appended DTB can be augumented later with ATAGS passed from the
+bootloader (if CONFIG_ARM_ATAG_DTB_COMPAT is enabled).
+
+The main problem and what this patch address is the fact that
+fdt_check_mem_start is never called later when the appended DTB is
+augumented, hence any fixup and validation is not done making AUTO_ZRELADDR
+detection inconsistent and most of the time wrong.
+
+Add support in head.S for this by checking if AUTO_ZRELADDR is enabled
+and calling fdt_check_mem_start with the appended DTB and the augumented
+values permitting legacy device to provide info in DTB instead of
+disabling AUTO_ZRELADDR and hardcoding the physical address offsets.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ arch/arm/boot/compressed/head.S | 22 ++++++++++++++++++++++
+ 1 file changed, 22 insertions(+)
+
+--- a/arch/arm/boot/compressed/head.S
++++ b/arch/arm/boot/compressed/head.S
+@@ -443,6 +443,28 @@ restart:  adr     r0, LC1
+               add     r6, r6, r5
+               add     r10, r10, r5
+               add     sp, sp, r5
++
++#ifdef CONFIG_AUTO_ZRELADDR
++              /*
++               * Validate calculated start of physical memory with appended DTB.
++               * In the first iteration for physical memory start calculation,
++               * we skipped validating it as it could have been augumented by
++               * ATAGS stored at an offset from the same start of physical memory.
++               *
++               * We now have parsed them and augumented the appended DTB if asked
++               * so we can finally validate the start of physical memory.
++               *
++               * This is needed to apply additional fixup with
++               * linux,usable-memory-range or to make sure AUTO_ZRELADDR detected
++               * the correct value.
++               */
++              sub     r0, r4, #TEXT_OFFSET    @ revert to base address
++              mov     r1, r8                  @ use appended DTB
++              bl      fdt_check_mem_start
++
++              /* Determine final kernel image address. */
++              add     r4, r0, #TEXT_OFFSET
++#endif
+ dtb_check_done:
+ #endif
diff --git a/target/linux/ipq806x/patches-6.6/901-02-ARM-decompressor-add-option-to-ignore-MEM-ATAGs.patch b/target/linux/ipq806x/patches-6.6/901-02-ARM-decompressor-add-option-to-ignore-MEM-ATAGs.patch
new file mode 100644 (file)
index 0000000..2e4c4de
--- /dev/null
@@ -0,0 +1,54 @@
+From 781d7cd4c3364e9d38fa12a342c5ad4c7e33a5ba Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Fri, 19 Jan 2024 20:33:10 +0100
+Subject: [PATCH v2 2/2] ARM: decompressor: add option to ignore MEM ATAGs
+
+Some bootloaders can pass broken MEM ATAGs that provide hardcoded
+information about mounted RAM size and physical location.
+Example booloader provide RAM of size 1.7Gb but actual mounted RAM
+size is 512Mb causing kernel panic.
+
+Add option CONFIG_ARM_ATAG_DTB_COMPAT_IGNORE_MEM to ignore these ATAG
+and not augument appended DTB memory node.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Acked-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ arch/arm/Kconfig                        | 12 ++++++++++++
+ arch/arm/boot/compressed/atags_to_fdt.c |  4 ++++
+ 2 files changed, 16 insertions(+)
+
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -1570,6 +1570,18 @@ config ARM_ATAG_DTB_COMPAT
+         bootloaders, this option allows zImage to extract the information
+         from the ATAG list and store it at run time into the appended DTB.
++config ARM_ATAG_DTB_COMPAT_IGNORE_MEM
++      bool "Ignore MEM ATAG information from bootloader"
++      depends on ARM_ATAG_DTB_COMPAT
++      help
++        Some bootloaders can pass broken MEM ATAGs that provide hardcoded
++        information about mounted RAM size and physical location.
++        Example booloader provide RAM of size 1.7Gb but actual mounted RAM
++        size is 512Mb causing kernel panic.
++
++        Enable this option if MEM ATAGs should be ignored and the memory
++        node in the appended DTB should NOT be augumented.
++
+ choice
+       prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
+       default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
+--- a/arch/arm/boot/compressed/atags_to_fdt.c
++++ b/arch/arm/boot/compressed/atags_to_fdt.c
+@@ -169,6 +169,10 @@ int atags_to_fdt(void *atag_list, void *
+                               setprop_string(fdt, "/chosen", "bootargs",
+                                              atag->u.cmdline.cmdline);
+               } else if (atag->hdr.tag == ATAG_MEM) {
++                      /* Bootloader MEM ATAG are broken and should be ignored */
++                      if (IS_ENABLED(CONFIG_ARM_ATAG_DTB_COMPAT_IGNORE_MEM))
++                              continue;
++
+                       if (memcount >= sizeof(mem_reg_property)/4)
+                               continue;
+                       if (!atag->u.mem.size)
diff --git a/target/linux/ipq806x/patches-6.6/902-ARM-decompressor-support-for-ATAGs-rootblock-parsing.patch b/target/linux/ipq806x/patches-6.6/902-ARM-decompressor-support-for-ATAGs-rootblock-parsing.patch
new file mode 100644 (file)
index 0000000..60b80fe
--- /dev/null
@@ -0,0 +1,197 @@
+From 13bb6d8dd9138927950a520a288401db82871dc9 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Sun, 21 Jan 2024 23:36:57 +0100
+Subject: [PATCH] ARM: decompressor: support for ATAGs rootblock parsing
+
+The command-line arguments provided by the boot loader will be
+appended to a new device tree property: bootloader-args.
+
+If there is a property "append-rootblock" in DT under /chosen
+and a root= option in bootloaders command line it will be parsed
+and added to DT bootargs with the form: <append-rootblock>XX.
+
+This is usefull in dual boot systems, to get the current root partition
+without afecting the rest of the system.
+
+Signed-off-by: Adrian Panella <ianchi74@outlook.com>
+[ reworked to a cleaner patch ]
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ arch/arm/Kconfig                        |  10 +++
+ arch/arm/boot/compressed/atags_to_fdt.c | 102 ++++++++++++++++++++++--
+ init/main.c                             |  12 +++
+ 3 files changed, 117 insertions(+), 7 deletions(-)
+
+--- a/arch/arm/Kconfig
++++ b/arch/arm/Kconfig
+@@ -1599,6 +1599,16 @@ config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEN
+         The command-line arguments provided by the boot loader will be
+         appended to the the device tree bootargs property.
++config ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE
++      bool "Append rootblock parsing bootloader's kernel arguments"
++      help
++        The command-line arguments provided by the boot loader will be
++        appended to a new device tree property: bootloader-args.
++
++        If there is a property "append-rootblock" in DT under /chosen
++        and a root= option in bootloaders command line it will be parsed
++        and added to DT bootargs with the form: <append-rootblock>XX.
++
+ endchoice
+ config CMDLINE_OVERRIDE
+--- a/arch/arm/boot/compressed/atags_to_fdt.c
++++ b/arch/arm/boot/compressed/atags_to_fdt.c
+@@ -3,7 +3,8 @@
+ #include <asm/setup.h>
+ #include <libfdt.h>
+-#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND)
++#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND) || \
++      defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)
+ #define do_extend_cmdline 1
+ #else
+ #define do_extend_cmdline 0
+@@ -69,6 +70,83 @@ static uint32_t get_cell_size(const void
+       return cell_size;
+ }
++/**
++ * taken from arch/x86/boot/string.c
++ * local_strstr - Find the first substring in a %NUL terminated string
++ * @s1: The string to be searched
++ * @s2: The string to search for
++ */
++static char *local_strstr(const char *s1, const char *s2)
++{
++      size_t l1, l2;
++
++      l2 = strlen(s2);
++      if (!l2)
++              return (char *)s1;
++      l1 = strlen(s1);
++      while (l1 >= l2) {
++              l1--;
++              if (!memcmp(s1, s2, l2))
++                      return (char *)s1;
++              s1++;
++      }
++      return NULL;
++}
++
++static char *append_rootblock(char *dest, const char *str, int len, void *fdt)
++{
++      char *ptr, *end, *tmp;
++      const char *root="root=";
++      const char *find_rootblock;
++      int i, l;
++      const char *rootblock;
++
++      find_rootblock = getprop(fdt, "/chosen", "find-rootblock", &l);
++      if (!find_rootblock)
++              find_rootblock = root;
++
++      /* ARM doesn't have __HAVE_ARCH_STRSTR, so it was copied from x86 */
++      ptr = local_strstr(str, find_rootblock);
++      if (!ptr)
++              return dest;
++
++      end = strchr(ptr, ' ');
++      end = end ? (end - 1) : (strchr(ptr, 0) - 1);
++
++      /* Some boards ubi.mtd=XX,ZZZZ, so let's check for '," too. */
++      tmp = strchr(ptr, ',');
++      if (tmp)
++              end = end < tmp ? end : tmp - 1;
++
++      /*
++       * find partition number
++       * (assumes format root=/dev/mtdXX | /dev/mtdblockXX | yy:XX | ubi.mtd=XX,ZZZZ )
++       */
++      for (i = 0; end >= ptr && *end >= '0' && *end <= '9'; end--, i++);
++
++      ptr = end + 1;
++
++      /* if append-rootblock property is set use it to append to command line */
++      rootblock = getprop(fdt, "/chosen", "append-rootblock", &l);
++      if (rootblock != NULL) {
++              if (*dest != ' ') {
++                      *dest = ' ';
++                      dest++;
++                      len++;
++              }
++
++              if (len + l + i <= COMMAND_LINE_SIZE) {
++                      memcpy(dest, rootblock, l);
++                      dest += l - 1;
++
++                      memcpy(dest, ptr, i);
++                      dest += i;
++              }
++      }
++
++      return dest;
++}
++
+ static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline)
+ {
+       char cmdline[COMMAND_LINE_SIZE];
+@@ -86,13 +164,23 @@ static void merge_fdt_bootargs(void *fdt
+                       ptr += len - 1;
+               }
+-      /* and append the ATAG_CMDLINE */
+       if (fdt_cmdline) {
+-              len = strlen(fdt_cmdline);
+-              if (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) {
+-                      *ptr++ = ' ';
+-                      memcpy(ptr, fdt_cmdline, len);
+-                      ptr += len;
++              if (IS_ENABLED(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE)) {
++                      /*
++                      * save original bootloader args
++                      * and append ubi.mtd with root partition number
++                      * to current cmdline
++                      */
++                      setprop_string(fdt, "/chosen", "bootloader-args", fdt_cmdline);
++                      ptr = append_rootblock(ptr, fdt_cmdline, len, fdt);
++              } else {
++                      /* and append the ATAG_CMDLINE */
++                      len = strlen(fdt_cmdline);
++                      if (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) {
++                              *ptr++ = ' ';
++                              memcpy(ptr, fdt_cmdline, len);
++                              ptr += len;
++                      }
+               }
+       }
+       *ptr = '\0';
+--- a/init/main.c
++++ b/init/main.c
+@@ -28,6 +28,7 @@
+ #include <linux/initrd.h>
+ #include <linux/memblock.h>
+ #include <linux/acpi.h>
++#include <linux/of.h>
+ #include <linux/bootconfig.h>
+ #include <linux/console.h>
+ #include <linux/nmi.h>
+@@ -995,6 +996,17 @@ asmlinkage __visible void __init __no_sa
+       pr_notice("Kernel command line: %s\n", saved_command_line);
+       /* parameters may set static keys */
+       jump_label_init();
++
++      /* Show bootloader's original command line for reference */
++      if (IS_ENABLED(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE) && of_chosen) {
++              const char *prop = of_get_property(of_chosen, "bootloader-args", NULL);
++
++              if(prop)
++                      pr_notice("Bootloader command line (ignored): %s\n", prop);
++              else
++                      pr_notice("Bootloader command line not present\n");
++      }
++
+       parse_early_param();
+       after_dashes = parse_args("Booting kernel",
+                                 static_command_line, __start___param,