target/linux/ipq806x/patches-6.1/107-10-ARM-dts-qcom-add-saw-for-l2-cache-and-kraitcc-for.patch

   1 From bef5018abb7cf94efafdc05087b4c998891ae4ec Mon Sep 17 00:00:00 2001
   2 From: Ansuel Smith <ansuelsmth@gmail.com>
   3 Date: Mon, 17 Jan 2022 23:39:34 +0100
   4 Subject: [PATCH v3 10/18] ARM: dts: qcom: add saw for l2 cache and kraitcc for
   5  ipq8064
   6
   7 Add saw compatible for l2 cache and kraitcc node for ipq8064 dtsi.
   8 Also declare clock-output-names for acc0 and acc1 and qsb fixed clock
   9 for the secondary mux.
  10
  11 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
  12 Tested-by: Jonathan McDowell <noodles@earth.li>
  13 ---
  14  arch/arm/boot/dts/qcom-ipq8064.dtsi | 34 +++++++++++++++++++++++++++--
  15  1 file changed, 32 insertions(+), 2 deletions(-)
  16
  17 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
  18 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
  19 @@ -301,6 +301,12 @@
  20         };
  21
  22         clocks {
  23 +               qsb: qsb {
  24 +                       compatible = "fixed-clock";
  25 +                       clock-frequency = <225000000>;
  26 +                       #clock-cells = <0>;
  27 +               };
  28 +
  29                 cxo_board: cxo_board {
  30                         compatible = "fixed-clock";
  31                         #clock-cells = <0>;
  32 @@ -575,15 +581,30 @@
  33                         clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
  34                         clock-names = "pll8_vote", "pxo";
  35                         clock-output-names = "acpu_l2_aux";
  36 +                       #clock-cells = <0>;
  37 +               };
  38 +
  39 +               kraitcc: clock-controller {
  40 +                       compatible = "qcom,krait-cc-v1";
  41 +                       clocks = <&gcc PLL9>, <&gcc PLL10>, <&gcc PLL12>,
  42 +                                <&acc0>, <&acc1>, <&l2cc>, <&qsb>, <&pxo_board>;
  43 +                       clock-names = "hfpll0", "hfpll1", "hfpll_l2",
  44 +                                     "acpu0_aux", "acpu1_aux", "acpu_l2_aux",
  45 +                                     "qsb", "pxo";
  46 +                       #clock-cells = <1>;
  47                 };
  48
  49                 acc0: clock-controller@2088000 {
  50                         compatible = "qcom,kpss-acc-v1";
  51                         reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
  52 +                       clock-output-names = "acpu0_aux";
  53 +                       clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
  54 +                       clock-names = "pll8_vote", "pxo";
  55 +                       #clock-cells = <0>;
  56                 };
  57
  58                 saw0: regulator@2089000 {
  59 -                       compatible = "qcom,saw2";
  60 +                       compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
  61                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
  62                         regulator;
  63                 };
  64 @@ -591,14 +612,24 @@
  65                 acc1: clock-controller@2098000 {
  66                         compatible = "qcom,kpss-acc-v1";
  67                         reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
  68 +                       clock-output-names = "acpu1_aux";
  69 +                       clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
  70 +                       clock-names = "pll8_vote", "pxo";
  71 +                       #clock-cells = <0>;
  72                 };
  73
  74                 saw1: regulator@2099000 {
  75 -                       compatible = "qcom,saw2";
  76 +                       compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
  77                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
  78                         regulator;
  79                 };
  80
  81 +               saw_l2: regulator@02012000 {
  82 +                       compatible = "qcom,saw2", "syscon";
  83 +                       reg = <0x02012000 0x1000>;
  84 +                       regulator;
  85 +               };
  86 +
  87                 nss_common: syscon@03000000 {
  88                         compatible = "syscon";
  89                         reg = <0x03000000 0x0000FFFF>;