mediatek: 6.6: drop patches backported as fixes

Drop patches backported as fixes in later kernel version.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>

diff --git a/target/linux/mediatek/patches-6.6/020-v6.7-arm64-dts-mt7986-define-3W-max-power-to-both-SFP-on-.patch b/target/linux/mediatek/patches-6.6/020-v6.7-arm64-dts-mt7986-define-3W-max-power-to-both-SFP-on-.patch
deleted file mode 100644 (file)
index 8cba3b2..0000000
--- a/target/linux/mediatek/patches-6.6/020-v6.7-arm64-dts-mt7986-define-3W-max-power-to-both-SFP-on-.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From f8ed4088ed9c61ae92193da6130d04c37e7b19f2 Mon Sep 17 00:00:00 2001
-From: Frank Wunderlich <frank-w@public-files.de>
-Date: Sun, 20 Aug 2023 17:31:33 +0200
-Subject: [PATCH 20/22] arm64: dts: mt7986: define 3W max power to both SFP on
- BPI-R3
-
-All SFP power supplies are connected to the system VDD33 which is 3v3/8A.
-Set 3A per SFP slot to allow SFPs work which need more power than the
-default 1W.
-
-Fixes: 8e01fb15b815 ("arm64: dts: mt7986: add Bananapi R3")
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
----
- arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
-@@ -126,6 +126,7 @@
-               compatible = "sff,sfp";
-               i2c-bus = <&i2c_sfp1>;
-               los-gpios = <&pio 46 GPIO_ACTIVE_HIGH>;
-+              maximum-power-milliwatt = <3000>;
-               mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>;
-               tx-disable-gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
-               tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
-@@ -137,6 +138,7 @@
-               i2c-bus = <&i2c_sfp2>;
-               los-gpios = <&pio 31 GPIO_ACTIVE_HIGH>;
-               mod-def0-gpios = <&pio 47 GPIO_ACTIVE_LOW>;
-+              maximum-power-milliwatt = <3000>;
-               tx-disable-gpios = <&pio 15 GPIO_ACTIVE_HIGH>;
-               tx-fault-gpios = <&pio 48 GPIO_ACTIVE_HIGH>;
-       };

diff --git a/target/linux/mediatek/patches-6.6/021-v6.7-arm64-dts-mt7986-change-cooling-trips.patch b/target/linux/mediatek/patches-6.6/021-v6.7-arm64-dts-mt7986-change-cooling-trips.patch
deleted file mode 100644 (file)
index 20d4468..0000000
--- a/target/linux/mediatek/patches-6.6/021-v6.7-arm64-dts-mt7986-change-cooling-trips.patch
+++ /dev/null
@@ -1,59 +0,0 @@
-From aa3d6df9803c267725dc72286bb91602b7579882 Mon Sep 17 00:00:00 2001
-From: Frank Wunderlich <frank-w@public-files.de>
-Date: Sun, 20 Aug 2023 17:31:34 +0200
-Subject: [PATCH 21/22] arm64: dts: mt7986: change cooling trips
-
-Add Critical and hot trips for emergency system shutdown and limiting
-system load.
-
-Change passive trip to active to make sure fan is activated on the
-lowest trip.
-
-Fixes: 1f5be05132f3 ("arm64: dts: mt7986: add thermal-zones")
-Suggested-by: Daniel Golle <daniel@makrotopia.org>
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
----
- arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 20 ++++++++++++++++----
- 1 file changed, 16 insertions(+), 4 deletions(-)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
-@@ -610,22 +610,34 @@
-                       thermal-sensors = <&thermal 0>;
- 
-                       trips {
-+                              cpu_trip_crit: crit {
-+                                      temperature = <125000>;
-+                                      hysteresis = <2000>;
-+                                      type = "critical";
-+                              };
-+
-+                              cpu_trip_hot: hot {
-+                                      temperature = <120000>;
-+                                      hysteresis = <2000>;
-+                                      type = "hot";
-+                              };
-+
-                               cpu_trip_active_high: active-high {
-                                       temperature = <115000>;
-                                       hysteresis = <2000>;
-                                       type = "active";
-                               };
- 
--                              cpu_trip_active_low: active-low {
-+                              cpu_trip_active_med: active-med {
-                                       temperature = <85000>;
-                                       hysteresis = <2000>;
-                                       type = "active";
-                               };
- 
--                              cpu_trip_passive: passive {
--                                      temperature = <40000>;
-+                              cpu_trip_active_low: active-low {
-+                                      temperature = <60000>;
-                                       hysteresis = <2000>;
--                                      type = "passive";
-+                                      type = "active";
-                               };
-                       };
-               };

diff --git a/target/linux/mediatek/patches-6.6/022-v6.7-arm64-dts-mt7986-change-thermal-trips-on-BPI-R3.patch b/target/linux/mediatek/patches-6.6/022-v6.7-arm64-dts-mt7986-change-thermal-trips-on-BPI-R3.patch
deleted file mode 100644 (file)
index 7166ab6..0000000
--- a/target/linux/mediatek/patches-6.6/022-v6.7-arm64-dts-mt7986-change-thermal-trips-on-BPI-R3.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From 6ddf23526955b8dbedfeaa57e691261fd73f9d4e Mon Sep 17 00:00:00 2001
-From: Frank Wunderlich <frank-w@public-files.de>
-Date: Sun, 20 Aug 2023 17:31:35 +0200
-Subject: [PATCH 22/22] arm64: dts: mt7986: change thermal trips on BPI-R3
-
-Apply new naming after mt7986 thermal trips were changed.
-
-Fixes: c26f779a2295 ("arm64: dts: mt7986: add pwm-fan and cooling-maps to BPI-R3 dts")
-Suggested-by: Daniel Golle <daniel@makrotopia.org>
-Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
----
- .../boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts      | 10 +++++-----
- 1 file changed, 5 insertions(+), 5 deletions(-)
-
---- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts
-@@ -152,16 +152,16 @@
-                       trip = <&cpu_trip_active_high>;
-               };
- 
--              cpu-active-low {
-+              cpu-active-med {
-                       /* active: set fan to cooling level 1 */
-                       cooling-device = <&fan 1 1>;
--                      trip = <&cpu_trip_active_low>;
-+                      trip = <&cpu_trip_active_med>;
-               };
- 
--              cpu-passive {
--                      /* passive: set fan to cooling level 0 */
-+              cpu-active-low {
-+                      /* active: set fan to cooling level 0 */
-                       cooling-device = <&fan 0 0>;
--                      trip = <&cpu_trip_passive>;
-+                      trip = <&cpu_trip_active_low>;
-               };
-       };
- };

diff --git a/target/linux/mediatek/patches-6.6/734-v6.8-net-phy-mediatek-ge-soc-sync-driver-with-MediaTek-SD.patch b/target/linux/mediatek/patches-6.6/734-v6.8-net-phy-mediatek-ge-soc-sync-driver-with-MediaTek-SD.patch
deleted file mode 100644 (file)
index 5daa62b..0000000
--- a/target/linux/mediatek/patches-6.6/734-v6.8-net-phy-mediatek-ge-soc-sync-driver-with-MediaTek-SD.patch
+++ /dev/null
@@ -1,270 +0,0 @@
-From f2195279c234c0f618946424b8236026126bc595 Mon Sep 17 00:00:00 2001
-Message-ID: <f2195279c234c0f618946424b8236026126bc595.1706071311.git.daniel@makrotopia.org>
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Wed, 24 Jan 2024 02:27:04 +0000
-Subject: [PATCH net] net: phy: mediatek-ge-soc: sync driver with MediaTek SDK
-To: Daniel Golle <daniel@makrotopia.org>,
-    Qingfang Deng <dqfext@gmail.com>,
-    SkyLake Huang <SkyLake.Huang@mediatek.com>,
-    Andrew Lunn <andrew@lunn.ch>,
-    Heiner Kallweit <hkallweit1@gmail.com>,
-    Russell King <linux@armlinux.org.uk>,
-    David S. Miller <davem@davemloft.net>,
-    Eric Dumazet <edumazet@google.com>,
-    Jakub Kicinski <kuba@kernel.org>,
-    Paolo Abeni <pabeni@redhat.com>,
-    Matthias Brugger <matthias.bgg@gmail.com>,
-    AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
-    netdev@vger.kernel.org,
-    linux-kernel@vger.kernel.org,
-    linux-arm-kernel@lists.infradead.org,
-    linux-mediatek@lists.infradead.org
-
-Sync initialization and calibration routines with MediaTek's reference
-driver. Improves compliance and resolves link stability issues with
-CH340 IoT devices connected to MT798x built-in PHYs.
-
-Fixes: 98c485eaf509 ("net: phy: add driver for MediaTek SoC built-in GE PHYs")
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/net/phy/mediatek-ge-soc.c | 147 ++++++++++++++++--------------
- 1 file changed, 81 insertions(+), 66 deletions(-)
-
---- a/drivers/net/phy/mediatek-ge-soc.c
-+++ b/drivers/net/phy/mediatek-ge-soc.c
-@@ -491,7 +491,7 @@ static int tx_r50_fill_result(struct phy
-       u16 reg, val;
- 
-       if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988)
--              bias = -2;
-+              bias = -1;
- 
-       val = clamp_val(bias + tx_r50_cal_val, 0, 63);
- 
-@@ -707,6 +707,11 @@ restore:
- static void mt798x_phy_common_finetune(struct phy_device *phydev)
- {
-       phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
-+      /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */
-+      __phy_write(phydev, 0x11, 0xc71);
-+      __phy_write(phydev, 0x12, 0xc);
-+      __phy_write(phydev, 0x10, 0x8fae);
-+
-       /* EnabRandUpdTrig = 1 */
-       __phy_write(phydev, 0x11, 0x2f00);
-       __phy_write(phydev, 0x12, 0xe);
-@@ -717,15 +722,56 @@ static void mt798x_phy_common_finetune(s
-       __phy_write(phydev, 0x12, 0x0);
-       __phy_write(phydev, 0x10, 0x83aa);
- 
--      /* TrFreeze = 0 */
-+      /* FfeUpdGainForce = 1(Enable), FfeUpdGainForceVal = 4 */
-+      __phy_write(phydev, 0x11, 0x240);
-+      __phy_write(phydev, 0x12, 0x0);
-+      __phy_write(phydev, 0x10, 0x9680);
-+
-+      /* TrFreeze = 0 (mt7988 default) */
-       __phy_write(phydev, 0x11, 0x0);
-       __phy_write(phydev, 0x12, 0x0);
-       __phy_write(phydev, 0x10, 0x9686);
- 
-+      /* SSTrKp100 = 5 */
-+      /* SSTrKf100 = 6 */
-+      /* SSTrKp1000Mas = 5 */
-+      /* SSTrKf1000Mas = 6 */
-       /* SSTrKp1000Slv = 5 */
-+      /* SSTrKf1000Slv = 6 */
-       __phy_write(phydev, 0x11, 0xbaef);
-       __phy_write(phydev, 0x12, 0x2e);
-       __phy_write(phydev, 0x10, 0x968c);
-+      phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-+}
-+
-+static void mt7981_phy_finetune(struct phy_device *phydev)
-+{
-+      u16 val[8] = { 0x01ce, 0x01c1,
-+                     0x020f, 0x0202,
-+                     0x03d0, 0x03c0,
-+                     0x0013, 0x0005 };
-+      int i, k;
-+
-+      /* 100M eye finetune:
-+       * Keep middle level of TX MLT3 shapper as default.
-+       * Only change TX MLT3 overshoot level here.
-+       */
-+      for (k = 0, i = 1; i < 12; i++) {
-+              if (i % 3 == 0)
-+                      continue;
-+              phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]);
-+      }
-+
-+      phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
-+      /* ResetSyncOffset = 6 */
-+      __phy_write(phydev, 0x11, 0x600);
-+      __phy_write(phydev, 0x12, 0x0);
-+      __phy_write(phydev, 0x10, 0x8fc0);
-+
-+      /* VgaDecRate = 1 */
-+      __phy_write(phydev, 0x11, 0x4c2a);
-+      __phy_write(phydev, 0x12, 0x3e);
-+      __phy_write(phydev, 0x10, 0x8fa4);
- 
-       /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2,
-        * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2
-@@ -740,7 +786,7 @@ static void mt798x_phy_common_finetune(s
-       __phy_write(phydev, 0x10, 0x8ec0);
-       phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
- 
--      /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9*/
-+      /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9 */
-       phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
-                      MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
-                      BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9));
-@@ -773,48 +819,6 @@ static void mt798x_phy_common_finetune(s
-       phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222);
- }
- 
--static void mt7981_phy_finetune(struct phy_device *phydev)
--{
--      u16 val[8] = { 0x01ce, 0x01c1,
--                     0x020f, 0x0202,
--                     0x03d0, 0x03c0,
--                     0x0013, 0x0005 };
--      int i, k;
--
--      /* 100M eye finetune:
--       * Keep middle level of TX MLT3 shapper as default.
--       * Only change TX MLT3 overshoot level here.
--       */
--      for (k = 0, i = 1; i < 12; i++) {
--              if (i % 3 == 0)
--                      continue;
--              phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]);
--      }
--
--      phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
--      /* SlvDSPreadyTime = 24, MasDSPreadyTime = 24 */
--      __phy_write(phydev, 0x11, 0xc71);
--      __phy_write(phydev, 0x12, 0xc);
--      __phy_write(phydev, 0x10, 0x8fae);
--
--      /* ResetSyncOffset = 6 */
--      __phy_write(phydev, 0x11, 0x600);
--      __phy_write(phydev, 0x12, 0x0);
--      __phy_write(phydev, 0x10, 0x8fc0);
--
--      /* VgaDecRate = 1 */
--      __phy_write(phydev, 0x11, 0x4c2a);
--      __phy_write(phydev, 0x12, 0x3e);
--      __phy_write(phydev, 0x10, 0x8fa4);
--
--      /* FfeUpdGainForce = 4 */
--      __phy_write(phydev, 0x11, 0x240);
--      __phy_write(phydev, 0x12, 0x0);
--      __phy_write(phydev, 0x10, 0x9680);
--
--      phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
--}
--
- static void mt7988_phy_finetune(struct phy_device *phydev)
- {
-       u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182,
-@@ -829,17 +833,7 @@ static void mt7988_phy_finetune(struct p
-       /* TCT finetune */
-       phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5);
- 
--      /* Disable TX power saving */
--      phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
--                     MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8);
--
-       phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
--
--      /* SlvDSPreadyTime = 24, MasDSPreadyTime = 12 */
--      __phy_write(phydev, 0x11, 0x671);
--      __phy_write(phydev, 0x12, 0xc);
--      __phy_write(phydev, 0x10, 0x8fae);
--
-       /* ResetSyncOffset = 5 */
-       __phy_write(phydev, 0x11, 0x500);
-       __phy_write(phydev, 0x12, 0x0);
-@@ -847,13 +841,27 @@ static void mt7988_phy_finetune(struct p
- 
-       /* VgaDecRate is 1 at default on mt7988 */
- 
--      phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-+      /* MrvlTrFix100Kp = 6, MrvlTrFix100Kf = 7,
-+       * MrvlTrFix1000Kp = 6, MrvlTrFix1000Kf = 7
-+       */
-+      __phy_write(phydev, 0x11, 0xb90a);
-+      __phy_write(phydev, 0x12, 0x6f);
-+      __phy_write(phydev, 0x10, 0x8f82);
-+
-+      /* RemAckCntLimitCtrl = 1 */
-+      __phy_write(phydev, 0x11, 0xfbba);
-+      __phy_write(phydev, 0x12, 0xc3);
-+      __phy_write(phydev, 0x10, 0x87f8);
- 
--      phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_2A30);
--      /* TxClkOffset = 2 */
--      __phy_modify(phydev, MTK_PHY_ANARG_RG, MTK_PHY_TCLKOFFSET_MASK,
--                   FIELD_PREP(MTK_PHY_TCLKOFFSET_MASK, 0x2));
-       phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
-+
-+      /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 10 */
-+      phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234,
-+                     MTK_PHY_TR_OPEN_LOOP_EN_MASK | MTK_PHY_LPF_X_AVERAGE_MASK,
-+                     BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0xa));
-+
-+      /* rg_tr_lpf_cnt_val = 1023 */
-+      phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x3ff);
- }
- 
- static void mt798x_phy_eee(struct phy_device *phydev)
-@@ -886,11 +894,11 @@ static void mt798x_phy_eee(struct phy_de
-                      MTK_PHY_LPI_SLV_SEND_TX_EN,
-                      FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120));
- 
--      phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239,
--                     MTK_PHY_LPI_SEND_LOC_TIMER_MASK |
--                     MTK_PHY_LPI_TXPCS_LOC_RCV,
--                     FIELD_PREP(MTK_PHY_LPI_SEND_LOC_TIMER_MASK, 0x117));
-+      /* Keep MTK_PHY_LPI_SEND_LOC_TIMER as 375 */
-+      phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239,
-+                         MTK_PHY_LPI_TXPCS_LOC_RCV);
- 
-+      /* This also fixes some IoT issues, such as CH340 */
-       phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7,
-                      MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK,
-                      FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) |
-@@ -924,7 +932,7 @@ static void mt798x_phy_eee(struct phy_de
-       __phy_write(phydev, 0x12, 0x0);
-       __phy_write(phydev, 0x10, 0x9690);
- 
--      /* REG_EEE_st2TrKf1000 = 3 */
-+      /* REG_EEE_st2TrKf1000 = 2 */
-       __phy_write(phydev, 0x11, 0x114f);
-       __phy_write(phydev, 0x12, 0x2);
-       __phy_write(phydev, 0x10, 0x969a);
-@@ -949,7 +957,7 @@ static void mt798x_phy_eee(struct phy_de
-       __phy_write(phydev, 0x12, 0x0);
-       __phy_write(phydev, 0x10, 0x96b8);
- 
--      /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 1 */
-+      /* REGEEE_wake_slv_tr_wait_dfesigdet_en = 0 */
-       __phy_write(phydev, 0x11, 0x1463);
-       __phy_write(phydev, 0x12, 0x0);
-       __phy_write(phydev, 0x10, 0x96ca);
-@@ -1461,6 +1469,13 @@ static int mt7988_phy_probe(struct phy_d
-       if (err)
-               return err;
- 
-+      /* Disable TX power saving at probing to:
-+       * 1. Meet common mode compliance test criteria
-+       * 2. Make sure that TX-VCM calibration works fine
-+       */
-+      phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7,
-+                     MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8);
-+
-       return mt798x_phy_calibration(phydev);
- }
- 

diff --git a/target/linux/mediatek/patches-6.6/830-v6.7-44-thermal-drivers-mediatek-Fix-probe-for-THERMAL_V2.patch b/target/linux/mediatek/patches-6.6/830-v6.7-44-thermal-drivers-mediatek-Fix-probe-for-THERMAL_V2.patch
deleted file mode 100644 (file)
index 88f383c..0000000
--- a/target/linux/mediatek/patches-6.6/830-v6.7-44-thermal-drivers-mediatek-Fix-probe-for-THERMAL_V2.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From e6f43063f2fe9f08b34797bc6d223f7d63b01910 Mon Sep 17 00:00:00 2001
-From: Markus Schneider-Pargmann <msp@baylibre.com>
-Date: Mon, 18 Sep 2023 12:07:06 +0200
-Subject: [PATCH 39/42] thermal/drivers/mediatek: Fix probe for THERMAL_V2
-
-Fix the probe function to call mtk_thermal_release_periodic_ts for
-everything != MTK_THERMAL_V1. This was accidentally changed from V1
-to V2 in the original patch.
-
-Reported-by: Frank Wunderlich <frank-w@public-files.de>
-Closes: https://lore.kernel.org/lkml/B0B3775B-B8D1-4284-814F-4F41EC22F532@public-files.de/
-Reported-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Closes: https://lore.kernel.org/lkml/07a569b9-e691-64ea-dd65-3b49842af33d@linaro.org/
-Fixes: 33140e668b10 ("thermal/drivers/mediatek: Control buffer enablement tweaks")
-Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com>
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
-Link: https://lore.kernel.org/r/20230918100706.1229239-1-msp@baylibre.com
----
- drivers/thermal/mediatek/auxadc_thermal.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/thermal/mediatek/auxadc_thermal.c
-+++ b/drivers/thermal/mediatek/auxadc_thermal.c
-@@ -1268,7 +1268,7 @@ static int mtk_thermal_probe(struct plat
- 
-       mtk_thermal_turn_on_buffer(mt, apmixed_base);
- 
--      if (mt->conf->version != MTK_THERMAL_V2)
-+      if (mt->conf->version != MTK_THERMAL_V1)
-               mtk_thermal_release_periodic_ts(mt, auxadc_base);
- 
-       if (mt->conf->version == MTK_THERMAL_V1)