+++ /dev/null
-From e6c5115d6845f25eda7e162dcd783a2044215867 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Sun, 30 Oct 2022 18:57:01 +0100
-Subject: [PATCH] clk: qcom: ipq8074: convert to parent data
-
-Convert the IPQ8074 GCC driver to use parent data instead of global
-name matching.
-
-Utilize ARRAY_SIZE for num_parents instead of hardcoding the value.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20221030175703.1103224-1-robimarko@gmail.com
----
- drivers/clk/qcom/gcc-ipq8074.c | 1781 +++++++++++++++-----------------
- 1 file changed, 813 insertions(+), 968 deletions(-)
-
---- a/drivers/clk/qcom/gcc-ipq8074.c
-+++ b/drivers/clk/qcom/gcc-ipq8074.c
-@@ -49,349 +49,6 @@ enum {
- P_UNIPHY2_TX,
- };
-
--static const char * const gcc_xo_gpll0_gpll0_out_main_div2[] = {
-- "xo",
-- "gpll0",
-- "gpll0_out_main_div2",
--};
--
--static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0, 1 },
-- { P_GPLL0_DIV2, 4 },
--};
--
--static const struct parent_map gcc_xo_gpll0_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0, 1 },
--};
--
--static const char * const gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
-- "xo",
-- "gpll0",
-- "gpll2",
-- "gpll0_out_main_div2",
--};
--
--static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0, 1 },
-- { P_GPLL2, 2 },
-- { P_GPLL0_DIV2, 4 },
--};
--
--static const char * const gcc_xo_gpll0_sleep_clk[] = {
-- "xo",
-- "gpll0",
-- "sleep_clk",
--};
--
--static const struct parent_map gcc_xo_gpll0_sleep_clk_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0, 2 },
-- { P_SLEEP_CLK, 6 },
--};
--
--static const char * const gcc_xo_gpll6_gpll0_gpll0_out_main_div2[] = {
-- "xo",
-- "gpll6",
-- "gpll0",
-- "gpll0_out_main_div2",
--};
--
--static const struct parent_map gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map[] = {
-- { P_XO, 0 },
-- { P_GPLL6, 1 },
-- { P_GPLL0, 3 },
-- { P_GPLL0_DIV2, 4 },
--};
--
--static const char * const gcc_xo_gpll0_out_main_div2_gpll0[] = {
-- "xo",
-- "gpll0_out_main_div2",
-- "gpll0",
--};
--
--static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0_DIV2, 2 },
-- { P_GPLL0, 1 },
--};
--
--static const char * const gcc_usb3phy_0_cc_pipe_clk_xo[] = {
-- "usb3phy_0_cc_pipe_clk",
-- "xo",
--};
--
--static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
-- { P_USB3PHY_0_PIPE, 0 },
-- { P_XO, 2 },
--};
--
--static const char * const gcc_usb3phy_1_cc_pipe_clk_xo[] = {
-- "usb3phy_1_cc_pipe_clk",
-- "xo",
--};
--
--static const struct parent_map gcc_usb3phy_1_cc_pipe_clk_xo_map[] = {
-- { P_USB3PHY_1_PIPE, 0 },
-- { P_XO, 2 },
--};
--
--static const char * const gcc_pcie20_phy0_pipe_clk_xo[] = {
-- "pcie20_phy0_pipe_clk",
-- "xo",
--};
--
--static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = {
-- { P_PCIE20_PHY0_PIPE, 0 },
-- { P_XO, 2 },
--};
--
--static const char * const gcc_pcie20_phy1_pipe_clk_xo[] = {
-- "pcie20_phy1_pipe_clk",
-- "xo",
--};
--
--static const struct parent_map gcc_pcie20_phy1_pipe_clk_xo_map[] = {
-- { P_PCIE20_PHY1_PIPE, 0 },
-- { P_XO, 2 },
--};
--
--static const char * const gcc_xo_gpll0_gpll6_gpll0_div2[] = {
-- "xo",
-- "gpll0",
-- "gpll6",
-- "gpll0_out_main_div2",
--};
--
--static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_div2_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0, 1 },
-- { P_GPLL6, 2 },
-- { P_GPLL0_DIV2, 4 },
--};
--
--static const char * const gcc_xo_gpll0_gpll6_gpll0_out_main_div2[] = {
-- "xo",
-- "gpll0",
-- "gpll6",
-- "gpll0_out_main_div2",
--};
--
--static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0, 1 },
-- { P_GPLL6, 2 },
-- { P_GPLL0_DIV2, 3 },
--};
--
--static const char * const gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
-- "xo",
-- "bias_pll_nss_noc_clk",
-- "gpll0",
-- "gpll2",
--};
--
--static const struct parent_map gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map[] = {
-- { P_XO, 0 },
-- { P_BIAS_PLL_NSS_NOC, 1 },
-- { P_GPLL0, 2 },
-- { P_GPLL2, 3 },
--};
--
--static const char * const gcc_xo_nss_crypto_pll_gpll0[] = {
-- "xo",
-- "nss_crypto_pll",
-- "gpll0",
--};
--
--static const struct parent_map gcc_xo_nss_crypto_pll_gpll0_map[] = {
-- { P_XO, 0 },
-- { P_NSS_CRYPTO_PLL, 1 },
-- { P_GPLL0, 2 },
--};
--
--static const char * const gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6[] = {
-- "xo",
-- "ubi32_pll",
-- "gpll0",
-- "gpll2",
-- "gpll4",
-- "gpll6",
--};
--
--static const struct parent_map gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map[] = {
-- { P_XO, 0 },
-- { P_UBI32_PLL, 1 },
-- { P_GPLL0, 2 },
-- { P_GPLL2, 3 },
-- { P_GPLL4, 4 },
-- { P_GPLL6, 5 },
--};
--
--static const char * const gcc_xo_gpll0_out_main_div2[] = {
-- "xo",
-- "gpll0_out_main_div2",
--};
--
--static const struct parent_map gcc_xo_gpll0_out_main_div2_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0_DIV2, 1 },
--};
--
--static const char * const gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
-- "xo",
-- "bias_pll_cc_clk",
-- "gpll0",
-- "gpll4",
-- "nss_crypto_pll",
-- "ubi32_pll",
--};
--
--static const struct parent_map gcc_xo_bias_gpll0_gpll4_nss_ubi32_map[] = {
-- { P_XO, 0 },
-- { P_BIAS_PLL, 1 },
-- { P_GPLL0, 2 },
-- { P_GPLL4, 3 },
-- { P_NSS_CRYPTO_PLL, 4 },
-- { P_UBI32_PLL, 5 },
--};
--
--static const char * const gcc_xo_gpll0_gpll4[] = {
-- "xo",
-- "gpll0",
-- "gpll4",
--};
--
--static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0, 1 },
-- { P_GPLL4, 2 },
--};
--
--static const char * const gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
-- "xo",
-- "uniphy0_gcc_rx_clk",
-- "uniphy0_gcc_tx_clk",
-- "ubi32_pll",
-- "bias_pll_cc_clk",
--};
--
--static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
-- { P_XO, 0 },
-- { P_UNIPHY0_RX, 1 },
-- { P_UNIPHY0_TX, 2 },
-- { P_UBI32_PLL, 5 },
-- { P_BIAS_PLL, 6 },
--};
--
--static const char * const gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
-- "xo",
-- "uniphy0_gcc_tx_clk",
-- "uniphy0_gcc_rx_clk",
-- "ubi32_pll",
-- "bias_pll_cc_clk",
--};
--
--static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
-- { P_XO, 0 },
-- { P_UNIPHY0_TX, 1 },
-- { P_UNIPHY0_RX, 2 },
-- { P_UBI32_PLL, 5 },
-- { P_BIAS_PLL, 6 },
--};
--
--static const char * const gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
-- "xo",
-- "uniphy0_gcc_rx_clk",
-- "uniphy0_gcc_tx_clk",
-- "uniphy1_gcc_rx_clk",
-- "uniphy1_gcc_tx_clk",
-- "ubi32_pll",
-- "bias_pll_cc_clk",
--};
--
--static const struct parent_map
--gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map[] = {
-- { P_XO, 0 },
-- { P_UNIPHY0_RX, 1 },
-- { P_UNIPHY0_TX, 2 },
-- { P_UNIPHY1_RX, 3 },
-- { P_UNIPHY1_TX, 4 },
-- { P_UBI32_PLL, 5 },
-- { P_BIAS_PLL, 6 },
--};
--
--static const char * const gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
-- "xo",
-- "uniphy0_gcc_tx_clk",
-- "uniphy0_gcc_rx_clk",
-- "uniphy1_gcc_tx_clk",
-- "uniphy1_gcc_rx_clk",
-- "ubi32_pll",
-- "bias_pll_cc_clk",
--};
--
--static const struct parent_map
--gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map[] = {
-- { P_XO, 0 },
-- { P_UNIPHY0_TX, 1 },
-- { P_UNIPHY0_RX, 2 },
-- { P_UNIPHY1_TX, 3 },
-- { P_UNIPHY1_RX, 4 },
-- { P_UBI32_PLL, 5 },
-- { P_BIAS_PLL, 6 },
--};
--
--static const char * const gcc_xo_uniphy2_rx_tx_ubi32_bias[] = {
-- "xo",
-- "uniphy2_gcc_rx_clk",
-- "uniphy2_gcc_tx_clk",
-- "ubi32_pll",
-- "bias_pll_cc_clk",
--};
--
--static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = {
-- { P_XO, 0 },
-- { P_UNIPHY2_RX, 1 },
-- { P_UNIPHY2_TX, 2 },
-- { P_UBI32_PLL, 5 },
-- { P_BIAS_PLL, 6 },
--};
--
--static const char * const gcc_xo_uniphy2_tx_rx_ubi32_bias[] = {
-- "xo",
-- "uniphy2_gcc_tx_clk",
-- "uniphy2_gcc_rx_clk",
-- "ubi32_pll",
-- "bias_pll_cc_clk",
--};
--
--static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = {
-- { P_XO, 0 },
-- { P_UNIPHY2_TX, 1 },
-- { P_UNIPHY2_RX, 2 },
-- { P_UBI32_PLL, 5 },
-- { P_BIAS_PLL, 6 },
--};
--
--static const char * const gcc_xo_gpll0_gpll6_gpll0_sleep_clk[] = {
-- "xo",
-- "gpll0",
-- "gpll6",
-- "gpll0_out_main_div2",
-- "sleep_clk",
--};
--
--static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map[] = {
-- { P_XO, 0 },
-- { P_GPLL0, 1 },
-- { P_GPLL6, 2 },
-- { P_GPLL0_DIV2, 4 },
-- { P_SLEEP_CLK, 6 },
--};
--
- static struct clk_alpha_pll gpll0_main = {
- .offset = 0x21000,
- .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
-@@ -400,8 +57,9 @@ static struct clk_alpha_pll gpll0_main =
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gpll0_main",
-- .parent_names = (const char *[]){
-- "xo"
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "xo",
-+ .name = "xo",
- },
- .num_parents = 1,
- .ops = &clk_alpha_pll_ops,
-@@ -414,9 +72,8 @@ static struct clk_fixed_factor gpll0_out
- .div = 2,
- .hw.init = &(struct clk_init_data){
- .name = "gpll0_out_main_div2",
-- .parent_names = (const char *[]){
-- "gpll0_main"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gpll0_main.clkr.hw },
- .num_parents = 1,
- .ops = &clk_fixed_factor_ops,
- },
-@@ -428,9 +85,8 @@ static struct clk_alpha_pll_postdiv gpll
- .width = 4,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gpll0",
-- .parent_names = (const char *[]){
-- "gpll0_main"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gpll0_main.clkr.hw },
- .num_parents = 1,
- .ops = &clk_alpha_pll_postdiv_ro_ops,
- },
-@@ -444,8 +100,9 @@ static struct clk_alpha_pll gpll2_main =
- .enable_mask = BIT(2),
- .hw.init = &(struct clk_init_data){
- .name = "gpll2_main",
-- .parent_names = (const char *[]){
-- "xo"
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "xo",
-+ .name = "xo",
- },
- .num_parents = 1,
- .ops = &clk_alpha_pll_ops,
-@@ -460,9 +117,8 @@ static struct clk_alpha_pll_postdiv gpll
- .width = 4,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gpll2",
-- .parent_names = (const char *[]){
-- "gpll2_main"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gpll2_main.clkr.hw },
- .num_parents = 1,
- .ops = &clk_alpha_pll_postdiv_ro_ops,
- },
-@@ -476,8 +132,9 @@ static struct clk_alpha_pll gpll4_main =
- .enable_mask = BIT(5),
- .hw.init = &(struct clk_init_data){
- .name = "gpll4_main",
-- .parent_names = (const char *[]){
-- "xo"
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "xo",
-+ .name = "xo",
- },
- .num_parents = 1,
- .ops = &clk_alpha_pll_ops,
-@@ -492,9 +149,8 @@ static struct clk_alpha_pll_postdiv gpll
- .width = 4,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gpll4",
-- .parent_names = (const char *[]){
-- "gpll4_main"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gpll4_main.clkr.hw },
- .num_parents = 1,
- .ops = &clk_alpha_pll_postdiv_ro_ops,
- },
-@@ -509,8 +165,9 @@ static struct clk_alpha_pll gpll6_main =
- .enable_mask = BIT(7),
- .hw.init = &(struct clk_init_data){
- .name = "gpll6_main",
-- .parent_names = (const char *[]){
-- "xo"
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "xo",
-+ .name = "xo",
- },
- .num_parents = 1,
- .ops = &clk_alpha_pll_ops,
-@@ -525,9 +182,8 @@ static struct clk_alpha_pll_postdiv gpll
- .width = 2,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gpll6",
-- .parent_names = (const char *[]){
-- "gpll6_main"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gpll6_main.clkr.hw },
- .num_parents = 1,
- .ops = &clk_alpha_pll_postdiv_ro_ops,
- },
-@@ -538,9 +194,8 @@ static struct clk_fixed_factor gpll6_out
- .div = 2,
- .hw.init = &(struct clk_init_data){
- .name = "gpll6_out_main_div2",
-- .parent_names = (const char *[]){
-- "gpll6_main"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gpll6_main.clkr.hw },
- .num_parents = 1,
- .ops = &clk_fixed_factor_ops,
- },
-@@ -555,8 +210,9 @@ static struct clk_alpha_pll ubi32_pll_ma
- .enable_mask = BIT(6),
- .hw.init = &(struct clk_init_data){
- .name = "ubi32_pll_main",
-- .parent_names = (const char *[]){
-- "xo"
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "xo",
-+ .name = "xo",
- },
- .num_parents = 1,
- .ops = &clk_alpha_pll_huayra_ops,
-@@ -570,9 +226,8 @@ static struct clk_alpha_pll_postdiv ubi3
- .width = 2,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "ubi32_pll",
-- .parent_names = (const char *[]){
-- "ubi32_pll_main"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &ubi32_pll_main.clkr.hw },
- .num_parents = 1,
- .ops = &clk_alpha_pll_postdiv_ro_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -587,8 +242,9 @@ static struct clk_alpha_pll nss_crypto_p
- .enable_mask = BIT(4),
- .hw.init = &(struct clk_init_data){
- .name = "nss_crypto_pll_main",
-- .parent_names = (const char *[]){
-- "xo"
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "xo",
-+ .name = "xo",
- },
- .num_parents = 1,
- .ops = &clk_alpha_pll_ops,
-@@ -602,9 +258,8 @@ static struct clk_alpha_pll_postdiv nss_
- .width = 4,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_crypto_pll",
-- .parent_names = (const char *[]){
-- "nss_crypto_pll_main"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_crypto_pll_main.clkr.hw },
- .num_parents = 1,
- .ops = &clk_alpha_pll_postdiv_ro_ops,
- },
-@@ -617,6 +272,18 @@ static const struct freq_tbl ftbl_pcnoc_
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .hw = &gpll0.clkr.hw},
-+ { .hw = &gpll0_out_main_div2.hw},
-+};
-+
-+static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL0, 1 },
-+ { P_GPLL0_DIV2, 4 },
-+};
-+
- static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
- .cmd_rcgr = 0x27000,
- .freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
-@@ -624,8 +291,8 @@ static struct clk_rcg2 pcnoc_bfdcd_clk_s
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "pcnoc_bfdcd_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- .flags = CLK_IS_CRITICAL,
- },
-@@ -636,9 +303,8 @@ static struct clk_fixed_factor pcnoc_clk
- .div = 1,
- .hw.init = &(struct clk_init_data){
- .name = "pcnoc_clk_src",
-- .parent_names = (const char *[]){
-- "pcnoc_bfdcd_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_bfdcd_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_fixed_factor_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -652,8 +318,9 @@ static struct clk_branch gcc_sleep_clk_s
- .enable_mask = BIT(1),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sleep_clk_src",
-- .parent_names = (const char *[]){
-- "sleep_clk"
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "sleep_clk",
-+ .name = "sleep_clk",
- },
- .num_parents = 1,
- .ops = &clk_branch2_ops,
-@@ -676,8 +343,8 @@ static struct clk_rcg2 blsp1_qup1_i2c_ap
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup1_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -702,8 +369,8 @@ static struct clk_rcg2 blsp1_qup1_spi_ap
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup1_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -715,8 +382,8 @@ static struct clk_rcg2 blsp1_qup2_i2c_ap
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup2_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -729,8 +396,8 @@ static struct clk_rcg2 blsp1_qup2_spi_ap
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup2_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -742,8 +409,8 @@ static struct clk_rcg2 blsp1_qup3_i2c_ap
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup3_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -756,8 +423,8 @@ static struct clk_rcg2 blsp1_qup3_spi_ap
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup3_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -769,8 +436,8 @@ static struct clk_rcg2 blsp1_qup4_i2c_ap
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup4_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -783,8 +450,8 @@ static struct clk_rcg2 blsp1_qup4_spi_ap
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup4_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -796,8 +463,8 @@ static struct clk_rcg2 blsp1_qup5_i2c_ap
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup5_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -810,8 +477,8 @@ static struct clk_rcg2 blsp1_qup5_spi_ap
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup5_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -823,8 +490,8 @@ static struct clk_rcg2 blsp1_qup6_i2c_ap
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup6_i2c_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -837,8 +504,8 @@ static struct clk_rcg2 blsp1_qup6_spi_ap
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_qup6_spi_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -871,8 +538,8 @@ static struct clk_rcg2 blsp1_uart1_apps_
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart1_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -885,8 +552,8 @@ static struct clk_rcg2 blsp1_uart2_apps_
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart2_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -899,8 +566,8 @@ static struct clk_rcg2 blsp1_uart3_apps_
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart3_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -913,8 +580,8 @@ static struct clk_rcg2 blsp1_uart4_apps_
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart4_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -927,8 +594,8 @@ static struct clk_rcg2 blsp1_uart5_apps_
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart5_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -941,8 +608,8 @@ static struct clk_rcg2 blsp1_uart6_apps_
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "blsp1_uart6_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -952,6 +619,11 @@ static const struct clk_parent_data gcc_
- { .hw = &gpll0.clkr.hw },
- };
-
-+static const struct parent_map gcc_xo_gpll0_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL0, 1 },
-+};
-+
- static const struct freq_tbl ftbl_pcie_axi_clk_src[] = {
- F(19200000, P_XO, 1, 0, 0),
- F(200000000, P_GPLL0, 4, 0, 0),
-@@ -966,7 +638,7 @@ static struct clk_rcg2 pcie0_axi_clk_src
- .clkr.hw.init = &(struct clk_init_data){
- .name = "pcie0_axi_clk_src",
- .parent_data = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -975,6 +647,18 @@ static const struct freq_tbl ftbl_pcie_a
- F(19200000, P_XO, 1, 0, 0),
- };
-
-+static const struct clk_parent_data gcc_xo_gpll0_sleep_clk[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .hw = &gpll0.clkr.hw },
-+ { .fw_name = "sleep_clk", .name = "sleep_clk" },
-+};
-+
-+static const struct parent_map gcc_xo_gpll0_sleep_clk_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL0, 2 },
-+ { P_SLEEP_CLK, 6 },
-+};
-+
- static struct clk_rcg2 pcie0_aux_clk_src = {
- .cmd_rcgr = 0x75024,
- .freq_tbl = ftbl_pcie_aux_clk_src,
-@@ -983,12 +667,22 @@ static struct clk_rcg2 pcie0_aux_clk_src
- .parent_map = gcc_xo_gpll0_sleep_clk_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "pcie0_aux_clk_src",
-- .parent_names = gcc_xo_gpll0_sleep_clk,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_sleep_clk,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk),
- .ops = &clk_rcg2_ops,
- },
- };
-
-+static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = {
-+ { .name = "pcie20_phy0_pipe_clk" },
-+ { .fw_name = "xo", .name = "xo" },
-+};
-+
-+static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = {
-+ { P_PCIE20_PHY0_PIPE, 0 },
-+ { P_XO, 2 },
-+};
-+
- static struct clk_regmap_mux pcie0_pipe_clk_src = {
- .reg = 0x7501c,
- .shift = 8,
-@@ -997,8 +691,8 @@ static struct clk_regmap_mux pcie0_pipe_
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "pcie0_pipe_clk_src",
-- .parent_names = gcc_pcie20_phy0_pipe_clk_xo,
-- .num_parents = 2,
-+ .parent_data = gcc_pcie20_phy0_pipe_clk_xo,
-+ .num_parents = ARRAY_SIZE(gcc_pcie20_phy0_pipe_clk_xo),
- .ops = &clk_regmap_mux_closest_ops,
- .flags = CLK_SET_RATE_PARENT,
- },
-@@ -1013,7 +707,7 @@ static struct clk_rcg2 pcie1_axi_clk_src
- .clkr.hw.init = &(struct clk_init_data){
- .name = "pcie1_axi_clk_src",
- .parent_data = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1026,12 +720,22 @@ static struct clk_rcg2 pcie1_aux_clk_src
- .parent_map = gcc_xo_gpll0_sleep_clk_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "pcie1_aux_clk_src",
-- .parent_names = gcc_xo_gpll0_sleep_clk,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_sleep_clk,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk),
- .ops = &clk_rcg2_ops,
- },
- };
-
-+static const struct clk_parent_data gcc_pcie20_phy1_pipe_clk_xo[] = {
-+ { .name = "pcie20_phy1_pipe_clk" },
-+ { .fw_name = "xo", .name = "xo" },
-+};
-+
-+static const struct parent_map gcc_pcie20_phy1_pipe_clk_xo_map[] = {
-+ { P_PCIE20_PHY1_PIPE, 0 },
-+ { P_XO, 2 },
-+};
-+
- static struct clk_regmap_mux pcie1_pipe_clk_src = {
- .reg = 0x7601c,
- .shift = 8,
-@@ -1040,8 +744,8 @@ static struct clk_regmap_mux pcie1_pipe_
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "pcie1_pipe_clk_src",
-- .parent_names = gcc_pcie20_phy1_pipe_clk_xo,
-- .num_parents = 2,
-+ .parent_data = gcc_pcie20_phy1_pipe_clk_xo,
-+ .num_parents = ARRAY_SIZE(gcc_pcie20_phy1_pipe_clk_xo),
- .ops = &clk_regmap_mux_closest_ops,
- .flags = CLK_SET_RATE_PARENT,
- },
-@@ -1060,6 +764,20 @@ static const struct freq_tbl ftbl_sdcc_a
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .hw = &gpll0.clkr.hw },
-+ { .hw = &gpll2.clkr.hw },
-+ { .hw = &gpll0_out_main_div2.hw },
-+};
-+
-+static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL0, 1 },
-+ { P_GPLL2, 2 },
-+ { P_GPLL0_DIV2, 4 },
-+};
-+
- static struct clk_rcg2 sdcc1_apps_clk_src = {
- .cmd_rcgr = 0x42004,
- .freq_tbl = ftbl_sdcc_apps_clk_src,
-@@ -1068,8 +786,8 @@ static struct clk_rcg2 sdcc1_apps_clk_sr
- .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "sdcc1_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
-- .num_parents = 4,
-+ .parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),
- .ops = &clk_rcg2_floor_ops,
- },
- };
-@@ -1080,6 +798,20 @@ static const struct freq_tbl ftbl_sdcc_i
- F(308570000, P_GPLL6, 3.5, 0, 0),
- };
-
-+static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_div2[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .hw = &gpll0.clkr.hw },
-+ { .hw = &gpll6.clkr.hw },
-+ { .hw = &gpll0_out_main_div2.hw },
-+};
-+
-+static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_div2_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL0, 1 },
-+ { P_GPLL6, 2 },
-+ { P_GPLL0_DIV2, 4 },
-+};
-+
- static struct clk_rcg2 sdcc1_ice_core_clk_src = {
- .cmd_rcgr = 0x5d000,
- .freq_tbl = ftbl_sdcc_ice_core_clk_src,
-@@ -1088,8 +820,8 @@ static struct clk_rcg2 sdcc1_ice_core_cl
- .parent_map = gcc_xo_gpll0_gpll6_gpll0_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "sdcc1_ice_core_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll6_gpll0_div2,
-- .num_parents = 4,
-+ .parent_data = gcc_xo_gpll0_gpll6_gpll0_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1102,8 +834,8 @@ static struct clk_rcg2 sdcc2_apps_clk_sr
- .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "sdcc2_apps_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
-- .num_parents = 4,
-+ .parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),
- .ops = &clk_rcg2_floor_ops,
- },
- };
-@@ -1115,6 +847,18 @@ static const struct freq_tbl ftbl_usb_ma
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_gpll0_out_main_div2_gpll0[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .hw = &gpll0_out_main_div2.hw },
-+ { .hw = &gpll0.clkr.hw },
-+};
-+
-+static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL0_DIV2, 2 },
-+ { P_GPLL0, 1 },
-+};
-+
- static struct clk_rcg2 usb0_master_clk_src = {
- .cmd_rcgr = 0x3e00c,
- .freq_tbl = ftbl_usb_master_clk_src,
-@@ -1123,8 +867,8 @@ static struct clk_rcg2 usb0_master_clk_s
- .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb0_master_clk_src",
-- .parent_names = gcc_xo_gpll0_out_main_div2_gpll0,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1142,8 +886,8 @@ static struct clk_rcg2 usb0_aux_clk_src
- .parent_map = gcc_xo_gpll0_sleep_clk_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb0_aux_clk_src",
-- .parent_names = gcc_xo_gpll0_sleep_clk,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_sleep_clk,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1155,6 +899,20 @@ static const struct freq_tbl ftbl_usb_mo
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_gpll6_gpll0_gpll0_out_main_div2[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .hw = &gpll6.clkr.hw },
-+ { .hw = &gpll0.clkr.hw },
-+ { .hw = &gpll0_out_main_div2.hw },
-+};
-+
-+static const struct parent_map gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL6, 1 },
-+ { P_GPLL0, 3 },
-+ { P_GPLL0_DIV2, 4 },
-+};
-+
- static struct clk_rcg2 usb0_mock_utmi_clk_src = {
- .cmd_rcgr = 0x3e020,
- .freq_tbl = ftbl_usb_mock_utmi_clk_src,
-@@ -1163,12 +921,22 @@ static struct clk_rcg2 usb0_mock_utmi_cl
- .parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb0_mock_utmi_clk_src",
-- .parent_names = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
-- .num_parents = 4,
-+ .parent_data = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll6_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-
-+static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = {
-+ { .name = "usb3phy_0_cc_pipe_clk" },
-+ { .fw_name = "xo", .name = "xo" },
-+};
-+
-+static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
-+ { P_USB3PHY_0_PIPE, 0 },
-+ { P_XO, 2 },
-+};
-+
- static struct clk_regmap_mux usb0_pipe_clk_src = {
- .reg = 0x3e048,
- .shift = 8,
-@@ -1177,8 +945,8 @@ static struct clk_regmap_mux usb0_pipe_c
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "usb0_pipe_clk_src",
-- .parent_names = gcc_usb3phy_0_cc_pipe_clk_xo,
-- .num_parents = 2,
-+ .parent_data = gcc_usb3phy_0_cc_pipe_clk_xo,
-+ .num_parents = ARRAY_SIZE(gcc_usb3phy_0_cc_pipe_clk_xo),
- .ops = &clk_regmap_mux_closest_ops,
- .flags = CLK_SET_RATE_PARENT,
- },
-@@ -1193,8 +961,8 @@ static struct clk_rcg2 usb1_master_clk_s
- .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb1_master_clk_src",
-- .parent_names = gcc_xo_gpll0_out_main_div2_gpll0,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1207,8 +975,8 @@ static struct clk_rcg2 usb1_aux_clk_src
- .parent_map = gcc_xo_gpll0_sleep_clk_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb1_aux_clk_src",
-- .parent_names = gcc_xo_gpll0_sleep_clk,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_sleep_clk,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_sleep_clk),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1221,12 +989,22 @@ static struct clk_rcg2 usb1_mock_utmi_cl
- .parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "usb1_mock_utmi_clk_src",
-- .parent_names = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
-- .num_parents = 4,
-+ .parent_data = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll6_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-
-+static const struct clk_parent_data gcc_usb3phy_1_cc_pipe_clk_xo[] = {
-+ { .name = "usb3phy_1_cc_pipe_clk" },
-+ { .fw_name = "xo", .name = "xo" },
-+};
-+
-+static const struct parent_map gcc_usb3phy_1_cc_pipe_clk_xo_map[] = {
-+ { P_USB3PHY_1_PIPE, 0 },
-+ { P_XO, 2 },
-+};
-+
- static struct clk_regmap_mux usb1_pipe_clk_src = {
- .reg = 0x3f048,
- .shift = 8,
-@@ -1235,8 +1013,8 @@ static struct clk_regmap_mux usb1_pipe_c
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "usb1_pipe_clk_src",
-- .parent_names = gcc_usb3phy_1_cc_pipe_clk_xo,
-- .num_parents = 2,
-+ .parent_data = gcc_usb3phy_1_cc_pipe_clk_xo,
-+ .num_parents = ARRAY_SIZE(gcc_usb3phy_1_cc_pipe_clk_xo),
- .ops = &clk_regmap_mux_closest_ops,
- .flags = CLK_SET_RATE_PARENT,
- },
-@@ -1250,8 +1028,9 @@ static struct clk_branch gcc_xo_clk_src
- .enable_mask = BIT(1),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_xo_clk_src",
-- .parent_names = (const char *[]){
-- "xo"
-+ .parent_data = &(const struct clk_parent_data){
-+ .fw_name = "xo",
-+ .name = "xo",
- },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
-@@ -1265,9 +1044,8 @@ static struct clk_fixed_factor gcc_xo_di
- .div = 4,
- .hw.init = &(struct clk_init_data){
- .name = "gcc_xo_div4_clk_src",
-- .parent_names = (const char *[]){
-- "gcc_xo_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gcc_xo_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_fixed_factor_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1285,6 +1063,20 @@ static const struct freq_tbl ftbl_system
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_out_main_div2[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .hw = &gpll0.clkr.hw },
-+ { .hw = &gpll6.clkr.hw },
-+ { .hw = &gpll0_out_main_div2.hw },
-+};
-+
-+static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL0, 1 },
-+ { P_GPLL6, 2 },
-+ { P_GPLL0_DIV2, 3 },
-+};
-+
- static struct clk_rcg2 system_noc_bfdcd_clk_src = {
- .cmd_rcgr = 0x26004,
- .freq_tbl = ftbl_system_noc_bfdcd_clk_src,
-@@ -1292,8 +1084,8 @@ static struct clk_rcg2 system_noc_bfdcd_
- .parent_map = gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "system_noc_bfdcd_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll6_gpll0_out_main_div2,
-- .num_parents = 4,
-+ .parent_data = gcc_xo_gpll0_gpll6_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- .flags = CLK_IS_CRITICAL,
- },
-@@ -1304,9 +1096,8 @@ static struct clk_fixed_factor system_no
- .div = 1,
- .hw.init = &(struct clk_init_data){
- .name = "system_noc_clk_src",
-- .parent_names = (const char *[]){
-- "system_noc_bfdcd_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &system_noc_bfdcd_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_fixed_factor_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1327,7 +1118,7 @@ static struct clk_rcg2 nss_ce_clk_src =
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_ce_clk_src",
- .parent_data = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1338,6 +1129,20 @@ static const struct freq_tbl ftbl_nss_no
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .name = "bias_pll_nss_noc_clk" },
-+ { .hw = &gpll0.clkr.hw },
-+ { .hw = &gpll2.clkr.hw },
-+};
-+
-+static const struct parent_map gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map[] = {
-+ { P_XO, 0 },
-+ { P_BIAS_PLL_NSS_NOC, 1 },
-+ { P_GPLL0, 2 },
-+ { P_GPLL2, 3 },
-+};
-+
- static struct clk_rcg2 nss_noc_bfdcd_clk_src = {
- .cmd_rcgr = 0x68088,
- .freq_tbl = ftbl_nss_noc_bfdcd_clk_src,
-@@ -1345,8 +1150,8 @@ static struct clk_rcg2 nss_noc_bfdcd_clk
- .parent_map = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_noc_bfdcd_clk_src",
-- .parent_names = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2,
-- .num_parents = 4,
-+ .parent_data = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1356,9 +1161,8 @@ static struct clk_fixed_factor nss_noc_c
- .div = 1,
- .hw.init = &(struct clk_init_data){
- .name = "nss_noc_clk_src",
-- .parent_names = (const char *[]){
-- "nss_noc_bfdcd_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_noc_bfdcd_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_fixed_factor_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1371,6 +1175,18 @@ static const struct freq_tbl ftbl_nss_cr
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_nss_crypto_pll_gpll0[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .hw = &nss_crypto_pll.clkr.hw },
-+ { .hw = &gpll0.clkr.hw },
-+};
-+
-+static const struct parent_map gcc_xo_nss_crypto_pll_gpll0_map[] = {
-+ { P_XO, 0 },
-+ { P_NSS_CRYPTO_PLL, 1 },
-+ { P_GPLL0, 2 },
-+};
-+
- static struct clk_rcg2 nss_crypto_clk_src = {
- .cmd_rcgr = 0x68144,
- .freq_tbl = ftbl_nss_crypto_clk_src,
-@@ -1379,8 +1195,8 @@ static struct clk_rcg2 nss_crypto_clk_sr
- .parent_map = gcc_xo_nss_crypto_pll_gpll0_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_crypto_clk_src",
-- .parent_names = gcc_xo_nss_crypto_pll_gpll0,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_nss_crypto_pll_gpll0,
-+ .num_parents = ARRAY_SIZE(gcc_xo_nss_crypto_pll_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1394,6 +1210,24 @@ static const struct freq_tbl ftbl_nss_ub
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .hw = &ubi32_pll.clkr.hw },
-+ { .hw = &gpll0.clkr.hw },
-+ { .hw = &gpll2.clkr.hw },
-+ { .hw = &gpll4.clkr.hw },
-+ { .hw = &gpll6.clkr.hw },
-+};
-+
-+static const struct parent_map gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map[] = {
-+ { P_XO, 0 },
-+ { P_UBI32_PLL, 1 },
-+ { P_GPLL0, 2 },
-+ { P_GPLL2, 3 },
-+ { P_GPLL4, 4 },
-+ { P_GPLL6, 5 },
-+};
-+
- static struct clk_rcg2 nss_ubi0_clk_src = {
- .cmd_rcgr = 0x68104,
- .freq_tbl = ftbl_nss_ubi_clk_src,
-@@ -1401,8 +1235,8 @@ static struct clk_rcg2 nss_ubi0_clk_src
- .parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_ubi0_clk_src",
-- .parent_names = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
-- .num_parents = 6,
-+ .parent_data = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
-+ .num_parents = ARRAY_SIZE(gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6),
- .ops = &clk_rcg2_ops,
- .flags = CLK_SET_RATE_PARENT,
- },
-@@ -1415,9 +1249,8 @@ static struct clk_regmap_div nss_ubi0_di
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "nss_ubi0_div_clk_src",
-- .parent_names = (const char *[]){
-- "nss_ubi0_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ubi0_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_regmap_div_ro_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1432,8 +1265,8 @@ static struct clk_rcg2 nss_ubi1_clk_src
- .parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_ubi1_clk_src",
-- .parent_names = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
-- .num_parents = 6,
-+ .parent_data = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
-+ .num_parents = ARRAY_SIZE(gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6),
- .ops = &clk_rcg2_ops,
- .flags = CLK_SET_RATE_PARENT,
- },
-@@ -1446,9 +1279,8 @@ static struct clk_regmap_div nss_ubi1_di
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "nss_ubi1_div_clk_src",
-- .parent_names = (const char *[]){
-- "nss_ubi1_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ubi1_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_regmap_div_ro_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1462,6 +1294,16 @@ static const struct freq_tbl ftbl_ubi_mp
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_gpll0_out_main_div2[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .hw = &gpll0_out_main_div2.hw },
-+};
-+
-+static const struct parent_map gcc_xo_gpll0_out_main_div2_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL0_DIV2, 1 },
-+};
-+
- static struct clk_rcg2 ubi_mpt_clk_src = {
- .cmd_rcgr = 0x68090,
- .freq_tbl = ftbl_ubi_mpt_clk_src,
-@@ -1469,8 +1311,8 @@ static struct clk_rcg2 ubi_mpt_clk_src =
- .parent_map = gcc_xo_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "ubi_mpt_clk_src",
-- .parent_names = gcc_xo_gpll0_out_main_div2,
-- .num_parents = 2,
-+ .parent_data = gcc_xo_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1481,6 +1323,18 @@ static const struct freq_tbl ftbl_nss_im
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .hw = &gpll0.clkr.hw },
-+ { .hw = &gpll4.clkr.hw },
-+};
-+
-+static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL0, 1 },
-+ { P_GPLL4, 2 },
-+};
-+
- static struct clk_rcg2 nss_imem_clk_src = {
- .cmd_rcgr = 0x68158,
- .freq_tbl = ftbl_nss_imem_clk_src,
-@@ -1488,8 +1342,8 @@ static struct clk_rcg2 nss_imem_clk_src
- .parent_map = gcc_xo_gpll0_gpll4_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_imem_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll4,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll4,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1500,6 +1354,24 @@ static const struct freq_tbl ftbl_nss_pp
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .name = "bias_pll_cc_clk" },
-+ { .hw = &gpll0.clkr.hw },
-+ { .hw = &gpll4.clkr.hw },
-+ { .hw = &nss_crypto_pll.clkr.hw },
-+ { .hw = &ubi32_pll.clkr.hw },
-+};
-+
-+static const struct parent_map gcc_xo_bias_gpll0_gpll4_nss_ubi32_map[] = {
-+ { P_XO, 0 },
-+ { P_BIAS_PLL, 1 },
-+ { P_GPLL0, 2 },
-+ { P_GPLL4, 3 },
-+ { P_NSS_CRYPTO_PLL, 4 },
-+ { P_UBI32_PLL, 5 },
-+};
-+
- static struct clk_rcg2 nss_ppe_clk_src = {
- .cmd_rcgr = 0x68080,
- .freq_tbl = ftbl_nss_ppe_clk_src,
-@@ -1507,8 +1379,8 @@ static struct clk_rcg2 nss_ppe_clk_src =
- .parent_map = gcc_xo_bias_gpll0_gpll4_nss_ubi32_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_ppe_clk_src",
-- .parent_names = gcc_xo_bias_gpll0_gpll4_nss_ubi32,
-- .num_parents = 6,
-+ .parent_data = gcc_xo_bias_gpll0_gpll4_nss_ubi32,
-+ .num_parents = ARRAY_SIZE(gcc_xo_bias_gpll0_gpll4_nss_ubi32),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1518,9 +1390,8 @@ static struct clk_fixed_factor nss_ppe_c
- .div = 4,
- .hw.init = &(struct clk_init_data){
- .name = "nss_ppe_cdiv_clk_src",
-- .parent_names = (const char *[]){
-- "nss_ppe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_fixed_factor_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1534,6 +1405,22 @@ static const struct freq_tbl ftbl_nss_po
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .name = "uniphy0_gcc_rx_clk" },
-+ { .name = "uniphy0_gcc_tx_clk" },
-+ { .hw = &ubi32_pll.clkr.hw },
-+ { .name = "bias_pll_cc_clk" },
-+};
-+
-+static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
-+ { P_XO, 0 },
-+ { P_UNIPHY0_RX, 1 },
-+ { P_UNIPHY0_TX, 2 },
-+ { P_UBI32_PLL, 5 },
-+ { P_BIAS_PLL, 6 },
-+};
-+
- static struct clk_rcg2 nss_port1_rx_clk_src = {
- .cmd_rcgr = 0x68020,
- .freq_tbl = ftbl_nss_port1_rx_clk_src,
-@@ -1541,8 +1428,8 @@ static struct clk_rcg2 nss_port1_rx_clk_
- .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_port1_rx_clk_src",
-- .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
-- .num_parents = 5,
-+ .parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
-+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_ubi32_bias),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1554,9 +1441,8 @@ static struct clk_regmap_div nss_port1_r
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "nss_port1_rx_div_clk_src",
-- .parent_names = (const char *[]){
-- "nss_port1_rx_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port1_rx_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_regmap_div_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1571,6 +1457,22 @@ static const struct freq_tbl ftbl_nss_po
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .name = "uniphy0_gcc_tx_clk" },
-+ { .name = "uniphy0_gcc_rx_clk" },
-+ { .hw = &ubi32_pll.clkr.hw },
-+ { .name = "bias_pll_cc_clk" },
-+};
-+
-+static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
-+ { P_XO, 0 },
-+ { P_UNIPHY0_TX, 1 },
-+ { P_UNIPHY0_RX, 2 },
-+ { P_UBI32_PLL, 5 },
-+ { P_BIAS_PLL, 6 },
-+};
-+
- static struct clk_rcg2 nss_port1_tx_clk_src = {
- .cmd_rcgr = 0x68028,
- .freq_tbl = ftbl_nss_port1_tx_clk_src,
-@@ -1578,8 +1480,8 @@ static struct clk_rcg2 nss_port1_tx_clk_
- .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_port1_tx_clk_src",
-- .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
-- .num_parents = 5,
-+ .parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
-+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_ubi32_bias),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1591,9 +1493,8 @@ static struct clk_regmap_div nss_port1_t
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "nss_port1_tx_div_clk_src",
-- .parent_names = (const char *[]){
-- "nss_port1_tx_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port1_tx_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_regmap_div_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1608,8 +1509,8 @@ static struct clk_rcg2 nss_port2_rx_clk_
- .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_port2_rx_clk_src",
-- .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
-- .num_parents = 5,
-+ .parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
-+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_ubi32_bias),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1621,9 +1522,8 @@ static struct clk_regmap_div nss_port2_r
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "nss_port2_rx_div_clk_src",
-- .parent_names = (const char *[]){
-- "nss_port2_rx_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port2_rx_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_regmap_div_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1638,8 +1538,8 @@ static struct clk_rcg2 nss_port2_tx_clk_
- .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_port2_tx_clk_src",
-- .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
-- .num_parents = 5,
-+ .parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
-+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_ubi32_bias),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1651,9 +1551,8 @@ static struct clk_regmap_div nss_port2_t
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "nss_port2_tx_div_clk_src",
-- .parent_names = (const char *[]){
-- "nss_port2_tx_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port2_tx_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_regmap_div_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1668,8 +1567,8 @@ static struct clk_rcg2 nss_port3_rx_clk_
- .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_port3_rx_clk_src",
-- .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
-- .num_parents = 5,
-+ .parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
-+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_ubi32_bias),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1681,9 +1580,8 @@ static struct clk_regmap_div nss_port3_r
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "nss_port3_rx_div_clk_src",
-- .parent_names = (const char *[]){
-- "nss_port3_rx_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port3_rx_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_regmap_div_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1698,8 +1596,8 @@ static struct clk_rcg2 nss_port3_tx_clk_
- .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_port3_tx_clk_src",
-- .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
-- .num_parents = 5,
-+ .parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
-+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_ubi32_bias),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1711,9 +1609,8 @@ static struct clk_regmap_div nss_port3_t
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "nss_port3_tx_div_clk_src",
-- .parent_names = (const char *[]){
-- "nss_port3_tx_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port3_tx_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_regmap_div_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1728,8 +1625,8 @@ static struct clk_rcg2 nss_port4_rx_clk_
- .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_port4_rx_clk_src",
-- .parent_names = gcc_xo_uniphy0_rx_tx_ubi32_bias,
-- .num_parents = 5,
-+ .parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias,
-+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_ubi32_bias),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1741,9 +1638,8 @@ static struct clk_regmap_div nss_port4_r
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "nss_port4_rx_div_clk_src",
-- .parent_names = (const char *[]){
-- "nss_port4_rx_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port4_rx_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_regmap_div_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1758,8 +1654,8 @@ static struct clk_rcg2 nss_port4_tx_clk_
- .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_port4_tx_clk_src",
-- .parent_names = gcc_xo_uniphy0_tx_rx_ubi32_bias,
-- .num_parents = 5,
-+ .parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias,
-+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_ubi32_bias),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1771,9 +1667,8 @@ static struct clk_regmap_div nss_port4_t
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "nss_port4_tx_div_clk_src",
-- .parent_names = (const char *[]){
-- "nss_port4_tx_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port4_tx_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_regmap_div_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1793,6 +1688,27 @@ static const struct freq_tbl ftbl_nss_po
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .name = "uniphy0_gcc_rx_clk" },
-+ { .name = "uniphy0_gcc_tx_clk" },
-+ { .name = "uniphy1_gcc_rx_clk" },
-+ { .name = "uniphy1_gcc_tx_clk" },
-+ { .hw = &ubi32_pll.clkr.hw },
-+ { .name = "bias_pll_cc_clk" },
-+};
-+
-+static const struct parent_map
-+gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map[] = {
-+ { P_XO, 0 },
-+ { P_UNIPHY0_RX, 1 },
-+ { P_UNIPHY0_TX, 2 },
-+ { P_UNIPHY1_RX, 3 },
-+ { P_UNIPHY1_TX, 4 },
-+ { P_UBI32_PLL, 5 },
-+ { P_BIAS_PLL, 6 },
-+};
-+
- static struct clk_rcg2 nss_port5_rx_clk_src = {
- .cmd_rcgr = 0x68060,
- .freq_tbl = ftbl_nss_port5_rx_clk_src,
-@@ -1800,8 +1716,8 @@ static struct clk_rcg2 nss_port5_rx_clk_
- .parent_map = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_port5_rx_clk_src",
-- .parent_names = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias,
-- .num_parents = 7,
-+ .parent_data = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias,
-+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1813,9 +1729,8 @@ static struct clk_regmap_div nss_port5_r
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "nss_port5_rx_div_clk_src",
-- .parent_names = (const char *[]){
-- "nss_port5_rx_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port5_rx_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_regmap_div_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1835,6 +1750,27 @@ static const struct freq_tbl ftbl_nss_po
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .name = "uniphy0_gcc_tx_clk" },
-+ { .name = "uniphy0_gcc_rx_clk" },
-+ { .name = "uniphy1_gcc_tx_clk" },
-+ { .name = "uniphy1_gcc_rx_clk" },
-+ { .hw = &ubi32_pll.clkr.hw },
-+ { .name = "bias_pll_cc_clk" },
-+};
-+
-+static const struct parent_map
-+gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map[] = {
-+ { P_XO, 0 },
-+ { P_UNIPHY0_TX, 1 },
-+ { P_UNIPHY0_RX, 2 },
-+ { P_UNIPHY1_TX, 3 },
-+ { P_UNIPHY1_RX, 4 },
-+ { P_UBI32_PLL, 5 },
-+ { P_BIAS_PLL, 6 },
-+};
-+
- static struct clk_rcg2 nss_port5_tx_clk_src = {
- .cmd_rcgr = 0x68068,
- .freq_tbl = ftbl_nss_port5_tx_clk_src,
-@@ -1842,8 +1778,8 @@ static struct clk_rcg2 nss_port5_tx_clk_
- .parent_map = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_port5_tx_clk_src",
-- .parent_names = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias,
-- .num_parents = 7,
-+ .parent_data = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias,
-+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1855,9 +1791,8 @@ static struct clk_regmap_div nss_port5_t
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "nss_port5_tx_div_clk_src",
-- .parent_names = (const char *[]){
-- "nss_port5_tx_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port5_tx_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_regmap_div_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1877,6 +1812,22 @@ static const struct freq_tbl ftbl_nss_po
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_uniphy2_rx_tx_ubi32_bias[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .name = "uniphy2_gcc_rx_clk" },
-+ { .name = "uniphy2_gcc_tx_clk" },
-+ { .hw = &ubi32_pll.clkr.hw },
-+ { .name = "bias_pll_cc_clk" },
-+};
-+
-+static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = {
-+ { P_XO, 0 },
-+ { P_UNIPHY2_RX, 1 },
-+ { P_UNIPHY2_TX, 2 },
-+ { P_UBI32_PLL, 5 },
-+ { P_BIAS_PLL, 6 },
-+};
-+
- static struct clk_rcg2 nss_port6_rx_clk_src = {
- .cmd_rcgr = 0x68070,
- .freq_tbl = ftbl_nss_port6_rx_clk_src,
-@@ -1884,8 +1835,8 @@ static struct clk_rcg2 nss_port6_rx_clk_
- .parent_map = gcc_xo_uniphy2_rx_tx_ubi32_bias_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_port6_rx_clk_src",
-- .parent_names = gcc_xo_uniphy2_rx_tx_ubi32_bias,
-- .num_parents = 5,
-+ .parent_data = gcc_xo_uniphy2_rx_tx_ubi32_bias,
-+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy2_rx_tx_ubi32_bias),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1897,9 +1848,8 @@ static struct clk_regmap_div nss_port6_r
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "nss_port6_rx_div_clk_src",
-- .parent_names = (const char *[]){
-- "nss_port6_rx_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port6_rx_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_regmap_div_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1919,6 +1869,22 @@ static const struct freq_tbl ftbl_nss_po
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_uniphy2_tx_rx_ubi32_bias[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .name = "uniphy2_gcc_tx_clk" },
-+ { .name = "uniphy2_gcc_rx_clk" },
-+ { .hw = &ubi32_pll.clkr.hw },
-+ { .name = "bias_pll_cc_clk" },
-+};
-+
-+static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = {
-+ { P_XO, 0 },
-+ { P_UNIPHY2_TX, 1 },
-+ { P_UNIPHY2_RX, 2 },
-+ { P_UBI32_PLL, 5 },
-+ { P_BIAS_PLL, 6 },
-+};
-+
- static struct clk_rcg2 nss_port6_tx_clk_src = {
- .cmd_rcgr = 0x68078,
- .freq_tbl = ftbl_nss_port6_tx_clk_src,
-@@ -1926,8 +1892,8 @@ static struct clk_rcg2 nss_port6_tx_clk_
- .parent_map = gcc_xo_uniphy2_tx_rx_ubi32_bias_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "nss_port6_tx_clk_src",
-- .parent_names = gcc_xo_uniphy2_tx_rx_ubi32_bias,
-- .num_parents = 5,
-+ .parent_data = gcc_xo_uniphy2_tx_rx_ubi32_bias,
-+ .num_parents = ARRAY_SIZE(gcc_xo_uniphy2_tx_rx_ubi32_bias),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1939,9 +1905,8 @@ static struct clk_regmap_div nss_port6_t
- .clkr = {
- .hw.init = &(struct clk_init_data){
- .name = "nss_port6_tx_div_clk_src",
-- .parent_names = (const char *[]){
-- "nss_port6_tx_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port6_tx_clk_src.clkr.hw },
- .num_parents = 1,
- .ops = &clk_regmap_div_ops,
- .flags = CLK_SET_RATE_PARENT,
-@@ -1964,8 +1929,8 @@ static struct clk_rcg2 crypto_clk_src =
- .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "crypto_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
-- .num_parents = 3,
-+ .parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1975,6 +1940,22 @@ static struct freq_tbl ftbl_gp_clk_src[]
- { }
- };
-
-+static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_sleep_clk[] = {
-+ { .fw_name = "xo", .name = "xo" },
-+ { .hw = &gpll0.clkr.hw },
-+ { .hw = &gpll6.clkr.hw },
-+ { .hw = &gpll0_out_main_div2.hw },
-+ { .fw_name = "sleep_clk", .name = "sleep_clk" },
-+};
-+
-+static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map[] = {
-+ { P_XO, 0 },
-+ { P_GPLL0, 1 },
-+ { P_GPLL6, 2 },
-+ { P_GPLL0_DIV2, 4 },
-+ { P_SLEEP_CLK, 6 },
-+};
-+
- static struct clk_rcg2 gp1_clk_src = {
- .cmd_rcgr = 0x08004,
- .freq_tbl = ftbl_gp_clk_src,
-@@ -1983,8 +1964,8 @@ static struct clk_rcg2 gp1_clk_src = {
- .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gp1_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
-- .num_parents = 5,
-+ .parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_sleep_clk),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -1997,8 +1978,8 @@ static struct clk_rcg2 gp2_clk_src = {
- .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gp2_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
-- .num_parents = 5,
-+ .parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_sleep_clk),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -2011,8 +1992,8 @@ static struct clk_rcg2 gp3_clk_src = {
- .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gp3_clk_src",
-- .parent_names = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
-- .num_parents = 5,
-+ .parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll6_gpll0_sleep_clk),
- .ops = &clk_rcg2_ops,
- },
- };
-@@ -2024,9 +2005,8 @@ static struct clk_branch gcc_blsp1_ahb_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_ahb_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2041,9 +2021,8 @@ static struct clk_branch gcc_blsp1_qup1_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup1_i2c_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_qup1_i2c_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_qup1_i2c_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2058,9 +2037,8 @@ static struct clk_branch gcc_blsp1_qup1_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup1_spi_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_qup1_spi_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_qup1_spi_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2075,9 +2053,8 @@ static struct clk_branch gcc_blsp1_qup2_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup2_i2c_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_qup2_i2c_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_qup2_i2c_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2092,9 +2069,8 @@ static struct clk_branch gcc_blsp1_qup2_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup2_spi_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_qup2_spi_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_qup2_spi_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2109,9 +2085,8 @@ static struct clk_branch gcc_blsp1_qup3_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup3_i2c_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_qup3_i2c_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_qup3_i2c_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2126,9 +2101,8 @@ static struct clk_branch gcc_blsp1_qup3_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup3_spi_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_qup3_spi_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_qup3_spi_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2143,9 +2117,8 @@ static struct clk_branch gcc_blsp1_qup4_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup4_i2c_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_qup4_i2c_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_qup4_i2c_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2160,9 +2133,8 @@ static struct clk_branch gcc_blsp1_qup4_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup4_spi_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_qup4_spi_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_qup4_spi_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2177,9 +2149,8 @@ static struct clk_branch gcc_blsp1_qup5_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup5_i2c_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_qup5_i2c_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_qup5_i2c_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2194,9 +2165,8 @@ static struct clk_branch gcc_blsp1_qup5_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup5_spi_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_qup5_spi_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_qup5_spi_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2211,9 +2181,8 @@ static struct clk_branch gcc_blsp1_qup6_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup6_i2c_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_qup6_i2c_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_qup6_i2c_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2228,9 +2197,8 @@ static struct clk_branch gcc_blsp1_qup6_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_qup6_spi_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_qup6_spi_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_qup6_spi_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2245,9 +2213,8 @@ static struct clk_branch gcc_blsp1_uart1
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_uart1_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_uart1_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_uart1_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2262,9 +2229,8 @@ static struct clk_branch gcc_blsp1_uart2
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_uart2_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_uart2_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_uart2_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2279,9 +2245,8 @@ static struct clk_branch gcc_blsp1_uart3
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_uart3_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_uart3_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_uart3_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2296,9 +2261,8 @@ static struct clk_branch gcc_blsp1_uart4
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_uart4_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_uart4_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_uart4_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2313,9 +2277,8 @@ static struct clk_branch gcc_blsp1_uart5
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_uart5_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_uart5_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_uart5_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2330,9 +2293,8 @@ static struct clk_branch gcc_blsp1_uart6
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_blsp1_uart6_apps_clk",
-- .parent_names = (const char *[]){
-- "blsp1_uart6_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &blsp1_uart6_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2348,9 +2310,8 @@ static struct clk_branch gcc_prng_ahb_cl
- .enable_mask = BIT(8),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_prng_ahb_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2365,9 +2326,8 @@ static struct clk_branch gcc_qpic_ahb_cl
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_qpic_ahb_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2382,9 +2342,8 @@ static struct clk_branch gcc_qpic_clk =
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_qpic_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2399,9 +2358,8 @@ static struct clk_branch gcc_pcie0_ahb_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie0_ahb_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2416,9 +2374,8 @@ static struct clk_branch gcc_pcie0_aux_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie0_aux_clk",
-- .parent_names = (const char *[]){
-- "pcie0_aux_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcie0_aux_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2433,9 +2390,8 @@ static struct clk_branch gcc_pcie0_axi_m
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie0_axi_m_clk",
-- .parent_names = (const char *[]){
-- "pcie0_axi_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcie0_axi_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2450,9 +2406,8 @@ static struct clk_branch gcc_pcie0_axi_s
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie0_axi_s_clk",
-- .parent_names = (const char *[]){
-- "pcie0_axi_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcie0_axi_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2468,9 +2423,8 @@ static struct clk_branch gcc_pcie0_pipe_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie0_pipe_clk",
-- .parent_names = (const char *[]){
-- "pcie0_pipe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcie0_pipe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2485,9 +2439,8 @@ static struct clk_branch gcc_sys_noc_pci
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sys_noc_pcie0_axi_clk",
-- .parent_names = (const char *[]){
-- "pcie0_axi_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcie0_axi_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2502,9 +2455,8 @@ static struct clk_branch gcc_pcie1_ahb_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie1_ahb_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2519,9 +2471,8 @@ static struct clk_branch gcc_pcie1_aux_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie1_aux_clk",
-- .parent_names = (const char *[]){
-- "pcie1_aux_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcie1_aux_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2536,9 +2487,8 @@ static struct clk_branch gcc_pcie1_axi_m
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie1_axi_m_clk",
-- .parent_names = (const char *[]){
-- "pcie1_axi_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcie1_axi_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2553,9 +2503,8 @@ static struct clk_branch gcc_pcie1_axi_s
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie1_axi_s_clk",
-- .parent_names = (const char *[]){
-- "pcie1_axi_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcie1_axi_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2571,9 +2520,8 @@ static struct clk_branch gcc_pcie1_pipe_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_pcie1_pipe_clk",
-- .parent_names = (const char *[]){
-- "pcie1_pipe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcie1_pipe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2588,9 +2536,8 @@ static struct clk_branch gcc_sys_noc_pci
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sys_noc_pcie1_axi_clk",
-- .parent_names = (const char *[]){
-- "pcie1_axi_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcie1_axi_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2605,9 +2552,8 @@ static struct clk_branch gcc_usb0_aux_cl
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb0_aux_clk",
-- .parent_names = (const char *[]){
-- "usb0_aux_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &usb0_aux_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2622,9 +2568,8 @@ static struct clk_branch gcc_sys_noc_usb
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sys_noc_usb0_axi_clk",
-- .parent_names = (const char *[]){
-- "usb0_master_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &usb0_master_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2639,9 +2584,8 @@ static struct clk_branch gcc_usb0_master
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb0_master_clk",
-- .parent_names = (const char *[]){
-- "usb0_master_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &usb0_master_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2656,9 +2600,8 @@ static struct clk_branch gcc_usb0_mock_u
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb0_mock_utmi_clk",
-- .parent_names = (const char *[]){
-- "usb0_mock_utmi_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &usb0_mock_utmi_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2673,9 +2616,8 @@ static struct clk_branch gcc_usb0_phy_cf
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb0_phy_cfg_ahb_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2691,9 +2633,8 @@ static struct clk_branch gcc_usb0_pipe_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb0_pipe_clk",
-- .parent_names = (const char *[]){
-- "usb0_pipe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &usb0_pipe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2708,9 +2649,8 @@ static struct clk_branch gcc_usb0_sleep_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb0_sleep_clk",
-- .parent_names = (const char *[]){
-- "gcc_sleep_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gcc_sleep_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2725,9 +2665,8 @@ static struct clk_branch gcc_usb1_aux_cl
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb1_aux_clk",
-- .parent_names = (const char *[]){
-- "usb1_aux_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &usb1_aux_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2742,9 +2681,8 @@ static struct clk_branch gcc_sys_noc_usb
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sys_noc_usb1_axi_clk",
-- .parent_names = (const char *[]){
-- "usb1_master_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &usb1_master_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2759,9 +2697,8 @@ static struct clk_branch gcc_usb1_master
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb1_master_clk",
-- .parent_names = (const char *[]){
-- "usb1_master_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &usb1_master_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2776,9 +2713,8 @@ static struct clk_branch gcc_usb1_mock_u
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb1_mock_utmi_clk",
-- .parent_names = (const char *[]){
-- "usb1_mock_utmi_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &usb1_mock_utmi_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2793,9 +2729,8 @@ static struct clk_branch gcc_usb1_phy_cf
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb1_phy_cfg_ahb_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2811,9 +2746,8 @@ static struct clk_branch gcc_usb1_pipe_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb1_pipe_clk",
-- .parent_names = (const char *[]){
-- "usb1_pipe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &usb1_pipe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2828,9 +2762,8 @@ static struct clk_branch gcc_usb1_sleep_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_usb1_sleep_clk",
-- .parent_names = (const char *[]){
-- "gcc_sleep_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gcc_sleep_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2845,9 +2778,8 @@ static struct clk_branch gcc_sdcc1_ahb_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc1_ahb_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2862,9 +2794,8 @@ static struct clk_branch gcc_sdcc1_apps_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc1_apps_clk",
-- .parent_names = (const char *[]){
-- "sdcc1_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &sdcc1_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2879,9 +2810,8 @@ static struct clk_branch gcc_sdcc1_ice_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc1_ice_core_clk",
-- .parent_names = (const char *[]){
-- "sdcc1_ice_core_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &sdcc1_ice_core_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2896,9 +2826,8 @@ static struct clk_branch gcc_sdcc2_ahb_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc2_ahb_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2913,9 +2842,8 @@ static struct clk_branch gcc_sdcc2_apps_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_sdcc2_apps_clk",
-- .parent_names = (const char *[]){
-- "sdcc2_apps_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &sdcc2_apps_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2930,9 +2858,8 @@ static struct clk_branch gcc_mem_noc_nss
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mem_noc_nss_axi_clk",
-- .parent_names = (const char *[]){
-- "nss_noc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_noc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2947,9 +2874,8 @@ static struct clk_branch gcc_nss_ce_apb_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_ce_apb_clk",
-- .parent_names = (const char *[]){
-- "nss_ce_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ce_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2964,9 +2890,8 @@ static struct clk_branch gcc_nss_ce_axi_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_ce_axi_clk",
-- .parent_names = (const char *[]){
-- "nss_ce_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ce_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2981,9 +2906,8 @@ static struct clk_branch gcc_nss_cfg_clk
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_cfg_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -2998,9 +2922,8 @@ static struct clk_branch gcc_nss_crypto_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_crypto_clk",
-- .parent_names = (const char *[]){
-- "nss_crypto_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_crypto_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3015,9 +2938,8 @@ static struct clk_branch gcc_nss_csr_clk
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_csr_clk",
-- .parent_names = (const char *[]){
-- "nss_ce_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ce_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3032,9 +2954,8 @@ static struct clk_branch gcc_nss_edma_cf
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_edma_cfg_clk",
-- .parent_names = (const char *[]){
-- "nss_ppe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3049,9 +2970,8 @@ static struct clk_branch gcc_nss_edma_cl
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_edma_clk",
-- .parent_names = (const char *[]){
-- "nss_ppe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3066,9 +2986,8 @@ static struct clk_branch gcc_nss_imem_cl
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_imem_clk",
-- .parent_names = (const char *[]){
-- "nss_imem_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_imem_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3083,9 +3002,8 @@ static struct clk_branch gcc_nss_noc_clk
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_noc_clk",
-- .parent_names = (const char *[]){
-- "nss_noc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_noc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3100,9 +3018,8 @@ static struct clk_branch gcc_nss_ppe_btq
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_ppe_btq_clk",
-- .parent_names = (const char *[]){
-- "nss_ppe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3117,9 +3034,8 @@ static struct clk_branch gcc_nss_ppe_cfg
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_ppe_cfg_clk",
-- .parent_names = (const char *[]){
-- "nss_ppe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3134,9 +3050,8 @@ static struct clk_branch gcc_nss_ppe_clk
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_ppe_clk",
-- .parent_names = (const char *[]){
-- "nss_ppe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3151,9 +3066,8 @@ static struct clk_branch gcc_nss_ppe_ipe
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_ppe_ipe_clk",
-- .parent_names = (const char *[]){
-- "nss_ppe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3168,9 +3082,8 @@ static struct clk_branch gcc_nss_ptp_ref
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_ptp_ref_clk",
-- .parent_names = (const char *[]){
-- "nss_ppe_cdiv_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_cdiv_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3186,9 +3099,8 @@ static struct clk_branch gcc_crypto_ppe_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_crypto_ppe_clk",
-- .parent_names = (const char *[]){
-- "nss_ppe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3203,9 +3115,8 @@ static struct clk_branch gcc_nssnoc_ce_a
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nssnoc_ce_apb_clk",
-- .parent_names = (const char *[]){
-- "nss_ce_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ce_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3220,9 +3131,8 @@ static struct clk_branch gcc_nssnoc_ce_a
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nssnoc_ce_axi_clk",
-- .parent_names = (const char *[]){
-- "nss_ce_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ce_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3237,9 +3147,8 @@ static struct clk_branch gcc_nssnoc_cryp
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nssnoc_crypto_clk",
-- .parent_names = (const char *[]){
-- "nss_crypto_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_crypto_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3254,9 +3163,8 @@ static struct clk_branch gcc_nssnoc_ppe_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nssnoc_ppe_cfg_clk",
-- .parent_names = (const char *[]){
-- "nss_ppe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3271,9 +3179,8 @@ static struct clk_branch gcc_nssnoc_ppe_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nssnoc_ppe_clk",
-- .parent_names = (const char *[]){
-- "nss_ppe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3288,9 +3195,8 @@ static struct clk_branch gcc_nssnoc_qosg
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nssnoc_qosgen_ref_clk",
-- .parent_names = (const char *[]){
-- "gcc_xo_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gcc_xo_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3305,9 +3211,8 @@ static struct clk_branch gcc_nssnoc_snoc
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nssnoc_snoc_clk",
-- .parent_names = (const char *[]){
-- "system_noc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &system_noc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3322,9 +3227,8 @@ static struct clk_branch gcc_nssnoc_time
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nssnoc_timeout_ref_clk",
-- .parent_names = (const char *[]){
-- "gcc_xo_div4_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gcc_xo_div4_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3339,9 +3243,8 @@ static struct clk_branch gcc_nssnoc_ubi0
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nssnoc_ubi0_ahb_clk",
-- .parent_names = (const char *[]){
-- "nss_ce_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ce_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3356,9 +3259,8 @@ static struct clk_branch gcc_nssnoc_ubi1
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nssnoc_ubi1_ahb_clk",
-- .parent_names = (const char *[]){
-- "nss_ce_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ce_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3374,9 +3276,8 @@ static struct clk_branch gcc_ubi0_ahb_cl
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ubi0_ahb_clk",
-- .parent_names = (const char *[]){
-- "nss_ce_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ce_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3392,9 +3293,8 @@ static struct clk_branch gcc_ubi0_axi_cl
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ubi0_axi_clk",
-- .parent_names = (const char *[]){
-- "nss_noc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_noc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3410,9 +3310,8 @@ static struct clk_branch gcc_ubi0_nc_axi
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ubi0_nc_axi_clk",
-- .parent_names = (const char *[]){
-- "nss_noc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_noc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3428,9 +3327,8 @@ static struct clk_branch gcc_ubi0_core_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ubi0_core_clk",
-- .parent_names = (const char *[]){
-- "nss_ubi0_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ubi0_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3446,9 +3344,8 @@ static struct clk_branch gcc_ubi0_mpt_cl
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ubi0_mpt_clk",
-- .parent_names = (const char *[]){
-- "ubi_mpt_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &ubi_mpt_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3464,9 +3361,8 @@ static struct clk_branch gcc_ubi1_ahb_cl
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ubi1_ahb_clk",
-- .parent_names = (const char *[]){
-- "nss_ce_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ce_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3482,9 +3378,8 @@ static struct clk_branch gcc_ubi1_axi_cl
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ubi1_axi_clk",
-- .parent_names = (const char *[]){
-- "nss_noc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_noc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3500,9 +3395,8 @@ static struct clk_branch gcc_ubi1_nc_axi
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ubi1_nc_axi_clk",
-- .parent_names = (const char *[]){
-- "nss_noc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_noc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3518,9 +3412,8 @@ static struct clk_branch gcc_ubi1_core_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ubi1_core_clk",
-- .parent_names = (const char *[]){
-- "nss_ubi1_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ubi1_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3536,9 +3429,8 @@ static struct clk_branch gcc_ubi1_mpt_cl
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_ubi1_mpt_clk",
-- .parent_names = (const char *[]){
-- "ubi_mpt_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &ubi_mpt_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3553,9 +3445,8 @@ static struct clk_branch gcc_cmn_12gpll_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_cmn_12gpll_ahb_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3570,9 +3461,8 @@ static struct clk_branch gcc_cmn_12gpll_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_cmn_12gpll_sys_clk",
-- .parent_names = (const char *[]){
-- "gcc_xo_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gcc_xo_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3587,9 +3477,8 @@ static struct clk_branch gcc_mdio_ahb_cl
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_mdio_ahb_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3604,9 +3493,8 @@ static struct clk_branch gcc_uniphy0_ahb
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy0_ahb_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3621,9 +3509,8 @@ static struct clk_branch gcc_uniphy0_sys
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy0_sys_clk",
-- .parent_names = (const char *[]){
-- "gcc_xo_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gcc_xo_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3638,9 +3525,8 @@ static struct clk_branch gcc_uniphy1_ahb
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy1_ahb_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3655,9 +3541,8 @@ static struct clk_branch gcc_uniphy1_sys
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy1_sys_clk",
-- .parent_names = (const char *[]){
-- "gcc_xo_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gcc_xo_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3672,9 +3557,8 @@ static struct clk_branch gcc_uniphy2_ahb
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy2_ahb_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3689,9 +3573,8 @@ static struct clk_branch gcc_uniphy2_sys
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy2_sys_clk",
-- .parent_names = (const char *[]){
-- "gcc_xo_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gcc_xo_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3706,9 +3589,8 @@ static struct clk_branch gcc_nss_port1_r
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_port1_rx_clk",
-- .parent_names = (const char *[]){
-- "nss_port1_rx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port1_rx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3723,9 +3605,8 @@ static struct clk_branch gcc_nss_port1_t
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_port1_tx_clk",
-- .parent_names = (const char *[]){
-- "nss_port1_tx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port1_tx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3740,9 +3621,8 @@ static struct clk_branch gcc_nss_port2_r
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_port2_rx_clk",
-- .parent_names = (const char *[]){
-- "nss_port2_rx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port2_rx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3757,9 +3637,8 @@ static struct clk_branch gcc_nss_port2_t
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_port2_tx_clk",
-- .parent_names = (const char *[]){
-- "nss_port2_tx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port2_tx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3774,9 +3653,8 @@ static struct clk_branch gcc_nss_port3_r
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_port3_rx_clk",
-- .parent_names = (const char *[]){
-- "nss_port3_rx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port3_rx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3791,9 +3669,8 @@ static struct clk_branch gcc_nss_port3_t
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_port3_tx_clk",
-- .parent_names = (const char *[]){
-- "nss_port3_tx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port3_tx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3808,9 +3685,8 @@ static struct clk_branch gcc_nss_port4_r
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_port4_rx_clk",
-- .parent_names = (const char *[]){
-- "nss_port4_rx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port4_rx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3825,9 +3701,8 @@ static struct clk_branch gcc_nss_port4_t
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_port4_tx_clk",
-- .parent_names = (const char *[]){
-- "nss_port4_tx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port4_tx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3842,9 +3717,8 @@ static struct clk_branch gcc_nss_port5_r
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_port5_rx_clk",
-- .parent_names = (const char *[]){
-- "nss_port5_rx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port5_rx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3859,9 +3733,8 @@ static struct clk_branch gcc_nss_port5_t
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_port5_tx_clk",
-- .parent_names = (const char *[]){
-- "nss_port5_tx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port5_tx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3876,9 +3749,8 @@ static struct clk_branch gcc_nss_port6_r
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_port6_rx_clk",
-- .parent_names = (const char *[]){
-- "nss_port6_rx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port6_rx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3893,9 +3765,8 @@ static struct clk_branch gcc_nss_port6_t
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_nss_port6_tx_clk",
-- .parent_names = (const char *[]){
-- "nss_port6_tx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port6_tx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3910,9 +3781,8 @@ static struct clk_branch gcc_port1_mac_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_port1_mac_clk",
-- .parent_names = (const char *[]){
-- "nss_ppe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3927,9 +3797,8 @@ static struct clk_branch gcc_port2_mac_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_port2_mac_clk",
-- .parent_names = (const char *[]){
-- "nss_ppe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3944,9 +3813,8 @@ static struct clk_branch gcc_port3_mac_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_port3_mac_clk",
-- .parent_names = (const char *[]){
-- "nss_ppe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3961,9 +3829,8 @@ static struct clk_branch gcc_port4_mac_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_port4_mac_clk",
-- .parent_names = (const char *[]){
-- "nss_ppe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3978,9 +3845,8 @@ static struct clk_branch gcc_port5_mac_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_port5_mac_clk",
-- .parent_names = (const char *[]){
-- "nss_ppe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -3995,9 +3861,8 @@ static struct clk_branch gcc_port6_mac_c
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_port6_mac_clk",
-- .parent_names = (const char *[]){
-- "nss_ppe_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_ppe_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4012,9 +3877,8 @@ static struct clk_branch gcc_uniphy0_por
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy0_port1_rx_clk",
-- .parent_names = (const char *[]){
-- "nss_port1_rx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port1_rx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4029,9 +3893,8 @@ static struct clk_branch gcc_uniphy0_por
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy0_port1_tx_clk",
-- .parent_names = (const char *[]){
-- "nss_port1_tx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port1_tx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4046,9 +3909,8 @@ static struct clk_branch gcc_uniphy0_por
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy0_port2_rx_clk",
-- .parent_names = (const char *[]){
-- "nss_port2_rx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port2_rx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4063,9 +3925,8 @@ static struct clk_branch gcc_uniphy0_por
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy0_port2_tx_clk",
-- .parent_names = (const char *[]){
-- "nss_port2_tx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port2_tx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4080,9 +3941,8 @@ static struct clk_branch gcc_uniphy0_por
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy0_port3_rx_clk",
-- .parent_names = (const char *[]){
-- "nss_port3_rx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port3_rx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4097,9 +3957,8 @@ static struct clk_branch gcc_uniphy0_por
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy0_port3_tx_clk",
-- .parent_names = (const char *[]){
-- "nss_port3_tx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port3_tx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4114,9 +3973,8 @@ static struct clk_branch gcc_uniphy0_por
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy0_port4_rx_clk",
-- .parent_names = (const char *[]){
-- "nss_port4_rx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port4_rx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4131,9 +3989,8 @@ static struct clk_branch gcc_uniphy0_por
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy0_port4_tx_clk",
-- .parent_names = (const char *[]){
-- "nss_port4_tx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port4_tx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4148,9 +4005,8 @@ static struct clk_branch gcc_uniphy0_por
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy0_port5_rx_clk",
-- .parent_names = (const char *[]){
-- "nss_port5_rx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port5_rx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4165,9 +4021,8 @@ static struct clk_branch gcc_uniphy0_por
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy0_port5_tx_clk",
-- .parent_names = (const char *[]){
-- "nss_port5_tx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port5_tx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4182,9 +4037,8 @@ static struct clk_branch gcc_uniphy1_por
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy1_port5_rx_clk",
-- .parent_names = (const char *[]){
-- "nss_port5_rx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port5_rx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4199,9 +4053,8 @@ static struct clk_branch gcc_uniphy1_por
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy1_port5_tx_clk",
-- .parent_names = (const char *[]){
-- "nss_port5_tx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port5_tx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4216,9 +4069,8 @@ static struct clk_branch gcc_uniphy2_por
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy2_port6_rx_clk",
-- .parent_names = (const char *[]){
-- "nss_port6_rx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port6_rx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4233,9 +4085,8 @@ static struct clk_branch gcc_uniphy2_por
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_uniphy2_port6_tx_clk",
-- .parent_names = (const char *[]){
-- "nss_port6_tx_div_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &nss_port6_tx_div_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4251,9 +4102,8 @@ static struct clk_branch gcc_crypto_ahb_
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_crypto_ahb_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4269,9 +4119,8 @@ static struct clk_branch gcc_crypto_axi_
- .enable_mask = BIT(1),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_crypto_axi_clk",
-- .parent_names = (const char *[]){
-- "pcnoc_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &pcnoc_clk_src.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4287,9 +4136,8 @@ static struct clk_branch gcc_crypto_clk
- .enable_mask = BIT(2),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_crypto_clk",
-- .parent_names = (const char *[]){
-- "crypto_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &crypto_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4304,9 +4152,8 @@ static struct clk_branch gcc_gp1_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_gp1_clk",
-- .parent_names = (const char *[]){
-- "gp1_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gp1_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4321,9 +4168,8 @@ static struct clk_branch gcc_gp2_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_gp2_clk",
-- .parent_names = (const char *[]){
-- "gp2_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gp2_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4338,9 +4184,8 @@ static struct clk_branch gcc_gp3_clk = {
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gcc_gp3_clk",
-- .parent_names = (const char *[]){
-- "gp3_clk_src"
-- },
-+ .parent_hws = (const struct clk_hw *[]){
-+ &gp3_clk_src.clkr.hw },
- .num_parents = 1,
- .flags = CLK_SET_RATE_PARENT,
- .ops = &clk_branch2_ops,
-@@ -4362,7 +4207,7 @@ static struct clk_rcg2 pcie0_rchng_clk_s
- .clkr.hw.init = &(struct clk_init_data){
- .name = "pcie0_rchng_clk_src",
- .parent_data = gcc_xo_gpll0,
-- .num_parents = 2,
-+ .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
- .ops = &clk_rcg2_ops,
- },
- };
projects / openwrt / staging / stintel.git / commitdiff