--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include "mt7981.dtsi"
+
+/ {
+ model = "Edgecore EAP111";
+ compatible = "edgecore,eap111", "mediatek,mt7981";
+
+ aliases {
+ serial0 = &uart0;
+ led-boot = &led_green;
+ led-failsafe = &led_green;
+ led-running = &led_green;
+ led-upgrade = &led_green;
+ };
+
+ chosen {
+ bootargs-override = "console=ttyS0,115200n8";
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&pio 1 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_green: led-green {
+ gpios = <&pio 9 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_INDICATOR;
+ };
+
+ led_orange: led-orange {
+ gpios = <&pio 34 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_ORANGE>;
+ function = LED_FUNCTION_INDICATOR;
+ };
+
+ led_blue: led-blue {
+ gpios = <&pio 35 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_INDICATOR;
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&watchdog {
+ status = "okay";
+};
+
+&pio {
+ spi0_flash_pins: spi0-pins {
+ mux {
+ function = "spi";
+ groups = "spi0", "spi0_wp_hold";
+ };
+ };
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_flash_pins>;
+ cs-gpios = <0>, <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-nand";
+ reg = <0>;
+ spi-max-frequency = <52000000>;
+
+ spi-cal-enable;
+ spi-cal-mode = "read-data";
+ spi-cal-datalen = <7>;
+ spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>;
+ spi-cal-addrlen = <5>;
+ spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>;
+
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ mediatek,nmbm;
+ mediatek,bmt-max-ratio = <1>;
+ mediatek,bmt-max-reserved-blocks = <64>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "BL2";
+ reg = <0x00000 0x100000>;
+ read-only;
+ };
+
+ partition@100000 {
+ label = "u-boot-env";
+ reg = <0x100000 0x80000>;
+ };
+
+ partition@180000 {
+ label = "Factory";
+ reg = <0x180000 0x200000>;
+ read-only;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ eeprom_factory: eeprom@0 {
+ reg = <0x0 0x1000>;
+ };
+
+ macaddr_wan: macaddr@2a {
+ reg = <0x2a 0x6>;
+ };
+
+ macaddr_lan: macaddr@24 {
+ reg = <0x24 0x6>;
+ };
+ };
+ };
+
+ partition@380000 {
+ label = "FIP";
+ reg = <0x380000 0x200000>;
+ read-only;
+ };
+
+ partition@580000 {
+ label = "ubi";
+ reg = <0x580000 0x4000000>;
+ compatible = "linux,ubi";
+ };
+ };
+ };
+};
+
+&mdio_bus {
+ reset-gpios = <&pio 39 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <10000>;
+ reset-post-delay-us = <10000>;
+
+ en8801sc: ethernet-phy@24 {
+ reg = <24>;
+ compatible = "ethernet-phy-id03a2.9471";
+ phy-mode = "sgmii";
+ };
+};
+
+ð {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio_pins>;
+ status = "okay";
+
+ gmac0: mac@0 {
+ compatible = "mediatek,eth-mac";
+ reg = <0>;
+ phy-mode = "sgmii";
+ phy-handle = <&en8801sc>;
+ managed = "in-band-status";
+ nvmem-cells = <&macaddr_lan>;
+ nvmem-cell-names = "mac-address";
+ };
+
+ gmac1: mac@1 {
+ compatible = "mediatek,eth-mac";
+ reg = <1>;
+ phy-mode = "gmii";
+ phy-handle = <&int_gbe_phy>;
+ nvmem-cells = <&macaddr_wan>;
+ nvmem-cell-names = "mac-address";
+ };
+};
+
+&wifi {
+ nvmem-cells = <&eeprom_factory>;
+ nvmem-cell-names = "eeprom";
+ status = "okay";
+};
projects / openwrt / staging / stintel.git / commitdiff