Backport few upstream changes included between v5.15 and v6.1.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
--- /dev/null
+From 12cf1b89a66828719b2135891b65bd5d03eedea9 Mon Sep 17 00:00:00 2001
+From: Bhadram Varka <vbhadram@nvidia.com>
+Date: Tue, 21 Jun 2022 09:10:27 +0530
+Subject: [PATCH] net: phy: Add support for AQR113C EPHY
+
+Add support multi-gigabit and single-port Ethernet
+PHY transceiver (AQR113C).
+
+Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
+Link: https://lore.kernel.org/r/20220621034027.56508-1-vbhadram@nvidia.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/aquantia_main.c | 20 ++++++++++++++++++++
+ 1 file changed, 20 insertions(+)
+
+--- a/drivers/net/phy/aquantia_main.c
++++ b/drivers/net/phy/aquantia_main.c
+@@ -22,6 +22,7 @@
+ #define PHY_ID_AQR107 0x03a1b4e0
+ #define PHY_ID_AQCS109 0x03a1b5c2
+ #define PHY_ID_AQR405 0x03a1b4b0
++#define PHY_ID_AQR113C 0x31c31c12
+
+ #define MDIO_PHYXS_VEND_IF_STATUS 0xe812
+ #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3)
+@@ -744,6 +745,24 @@ static struct phy_driver aqr_driver[] =
+ .handle_interrupt = aqr_handle_interrupt,
+ .read_status = aqr_read_status,
+ },
++{
++ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C),
++ .name = "Aquantia AQR113C",
++ .probe = aqr107_probe,
++ .config_init = aqr107_config_init,
++ .config_aneg = aqr_config_aneg,
++ .config_intr = aqr_config_intr,
++ .handle_interrupt = aqr_handle_interrupt,
++ .read_status = aqr107_read_status,
++ .get_tunable = aqr107_get_tunable,
++ .set_tunable = aqr107_set_tunable,
++ .suspend = aqr107_suspend,
++ .resume = aqr107_resume,
++ .get_sset_count = aqr107_get_sset_count,
++ .get_strings = aqr107_get_strings,
++ .get_stats = aqr107_get_stats,
++ .link_change_notify = aqr107_link_change_notify,
++},
+ };
+
+ module_phy_driver(aqr_driver);
+@@ -756,6 +775,7 @@ static struct mdio_device_id __maybe_unu
+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },
+ { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },
+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
++ { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
+ { }
+ };
+
--- /dev/null
+From 7de26bf144f6a72858ab60afb2bd2b43265ee0ad Mon Sep 17 00:00:00 2001
+From: Sean Anderson <sean.anderson@seco.com>
+Date: Tue, 20 Sep 2022 18:12:34 -0400
+Subject: [PATCH] net: phy: aquantia: Add some additional phy interfaces
+
+These are documented in the AQR115 register reference. I haven't tested
+them, but perhaps they'll be useful to someone.
+
+Signed-off-by: Sean Anderson <sean.anderson@seco.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/aquantia_main.c | 17 ++++++++++++++++-
+ 1 file changed, 16 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/phy/aquantia_main.c
++++ b/drivers/net/phy/aquantia_main.c
+@@ -27,9 +27,12 @@
+ #define MDIO_PHYXS_VEND_IF_STATUS 0xe812
+ #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3)
+ #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR 0
++#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX 1
+ #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI 2
+ #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII 3
++#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI 4
+ #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII 6
++#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI 7
+ #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII 10
+
+ #define MDIO_AN_VEND_PROV 0xc400
+@@ -401,15 +404,24 @@ static int aqr107_read_status(struct phy
+ case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR:
+ phydev->interface = PHY_INTERFACE_MODE_10GKR;
+ break;
++ case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX:
++ phydev->interface = PHY_INTERFACE_MODE_1000BASEKX;
++ break;
+ case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI:
+ phydev->interface = PHY_INTERFACE_MODE_10GBASER;
+ break;
+ case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII:
+ phydev->interface = PHY_INTERFACE_MODE_USXGMII;
+ break;
++ case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI:
++ phydev->interface = PHY_INTERFACE_MODE_XAUI;
++ break;
+ case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII:
+ phydev->interface = PHY_INTERFACE_MODE_SGMII;
+ break;
++ case MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI:
++ phydev->interface = PHY_INTERFACE_MODE_RXAUI;
++ break;
+ case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII:
+ phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
+ break;
+@@ -522,11 +534,14 @@ static int aqr107_config_init(struct phy
+
+ /* Check that the PHY interface type is compatible */
+ if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
++ phydev->interface != PHY_INTERFACE_MODE_1000BASEKX &&
+ phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
+ phydev->interface != PHY_INTERFACE_MODE_XGMII &&
+ phydev->interface != PHY_INTERFACE_MODE_USXGMII &&
+ phydev->interface != PHY_INTERFACE_MODE_10GKR &&
+- phydev->interface != PHY_INTERFACE_MODE_10GBASER)
++ phydev->interface != PHY_INTERFACE_MODE_10GBASER &&
++ phydev->interface != PHY_INTERFACE_MODE_XAUI &&
++ phydev->interface != PHY_INTERFACE_MODE_RXAUI)
+ return -ENODEV;
+
+ WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII,
--- /dev/null
+From 3c42563b30417afc8855a3b4c1b38c2f36f78657 Mon Sep 17 00:00:00 2001
+From: Sean Anderson <sean.anderson@seco.com>
+Date: Tue, 20 Sep 2022 18:12:35 -0400
+Subject: [PATCH] net: phy: aquantia: Add support for rate matching
+
+This adds support for rate matching for phys similar to the AQR107. We
+assume that all phys using aqr107_read_status support rate matching.
+However, it could be possible to determine support based on the firmware
+revision if there are phys discovered which do not support rate
+matching. However, as rate matching is advertised in the datasheets for
+these phys, I suspect it is supported most boards.
+
+Despite the name, the "config" registers are updated with the current
+rate matching method (if any). Because they appear to be updated
+automatically, I don't know if these registers can be used to disable
+rate matching.
+
+Signed-off-by: Sean Anderson <sean.anderson@seco.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/aquantia_main.c | 51 ++++++++++++++++++++++++++++++---
+ 1 file changed, 47 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/phy/aquantia_main.c
++++ b/drivers/net/phy/aquantia_main.c
+@@ -97,6 +97,19 @@
+ #define VEND1_GLOBAL_GEN_STAT2 0xc831
+ #define VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG BIT(15)
+
++/* The following registers all have similar layouts; first the registers... */
++#define VEND1_GLOBAL_CFG_10M 0x0310
++#define VEND1_GLOBAL_CFG_100M 0x031b
++#define VEND1_GLOBAL_CFG_1G 0x031c
++#define VEND1_GLOBAL_CFG_2_5G 0x031d
++#define VEND1_GLOBAL_CFG_5G 0x031e
++#define VEND1_GLOBAL_CFG_10G 0x031f
++/* ...and now the fields */
++#define VEND1_GLOBAL_CFG_RATE_ADAPT GENMASK(8, 7)
++#define VEND1_GLOBAL_CFG_RATE_ADAPT_NONE 0
++#define VEND1_GLOBAL_CFG_RATE_ADAPT_USX 1
++#define VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE 2
++
+ #define VEND1_GLOBAL_RSVD_STAT1 0xc885
+ #define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID GENMASK(7, 4)
+ #define VEND1_GLOBAL_RSVD_STAT1_PROV_ID GENMASK(3, 0)
+@@ -347,40 +360,57 @@ static int aqr_read_status(struct phy_de
+
+ static int aqr107_read_rate(struct phy_device *phydev)
+ {
++ u32 config_reg;
+ int val;
+
+ val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1);
+ if (val < 0)
+ return val;
+
++ if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX)
++ phydev->duplex = DUPLEX_FULL;
++ else
++ phydev->duplex = DUPLEX_HALF;
++
+ switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) {
+ case MDIO_AN_TX_VEND_STATUS1_10BASET:
+ phydev->speed = SPEED_10;
++ config_reg = VEND1_GLOBAL_CFG_10M;
+ break;
+ case MDIO_AN_TX_VEND_STATUS1_100BASETX:
+ phydev->speed = SPEED_100;
++ config_reg = VEND1_GLOBAL_CFG_100M;
+ break;
+ case MDIO_AN_TX_VEND_STATUS1_1000BASET:
+ phydev->speed = SPEED_1000;
++ config_reg = VEND1_GLOBAL_CFG_1G;
+ break;
+ case MDIO_AN_TX_VEND_STATUS1_2500BASET:
+ phydev->speed = SPEED_2500;
++ config_reg = VEND1_GLOBAL_CFG_2_5G;
+ break;
+ case MDIO_AN_TX_VEND_STATUS1_5000BASET:
+ phydev->speed = SPEED_5000;
++ config_reg = VEND1_GLOBAL_CFG_5G;
+ break;
+ case MDIO_AN_TX_VEND_STATUS1_10GBASET:
+ phydev->speed = SPEED_10000;
++ config_reg = VEND1_GLOBAL_CFG_10G;
+ break;
+ default:
+ phydev->speed = SPEED_UNKNOWN;
+- break;
++ return 0;
+ }
+
+- if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX)
+- phydev->duplex = DUPLEX_FULL;
++ val = phy_read_mmd(phydev, MDIO_MMD_VEND1, config_reg);
++ if (val < 0)
++ return val;
++
++ if (FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val) ==
++ VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE)
++ phydev->rate_matching = RATE_MATCH_PAUSE;
+ else
+- phydev->duplex = DUPLEX_HALF;
++ phydev->rate_matching = RATE_MATCH_NONE;
+
+ return 0;
+ }
+@@ -647,6 +677,16 @@ static int aqr107_wait_processor_intensi
+ return 0;
+ }
+
++static int aqr107_get_rate_matching(struct phy_device *phydev,
++ phy_interface_t iface)
++{
++ if (iface == PHY_INTERFACE_MODE_10GBASER ||
++ iface == PHY_INTERFACE_MODE_2500BASEX ||
++ iface == PHY_INTERFACE_MODE_NA)
++ return RATE_MATCH_PAUSE;
++ return RATE_MATCH_NONE;
++}
++
+ static int aqr107_suspend(struct phy_device *phydev)
+ {
+ int err;
+@@ -720,6 +760,7 @@ static struct phy_driver aqr_driver[] =
+ PHY_ID_MATCH_MODEL(PHY_ID_AQR107),
+ .name = "Aquantia AQR107",
+ .probe = aqr107_probe,
++ .get_rate_matching = aqr107_get_rate_matching,
+ .config_init = aqr107_config_init,
+ .config_aneg = aqr_config_aneg,
+ .config_intr = aqr_config_intr,
+@@ -738,6 +779,7 @@ static struct phy_driver aqr_driver[] =
+ PHY_ID_MATCH_MODEL(PHY_ID_AQCS109),
+ .name = "Aquantia AQCS109",
+ .probe = aqr107_probe,
++ .get_rate_matching = aqr107_get_rate_matching,
+ .config_init = aqcs109_config_init,
+ .config_aneg = aqr_config_aneg,
+ .config_intr = aqr_config_intr,
+@@ -764,6 +806,7 @@ static struct phy_driver aqr_driver[] =
+ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C),
+ .name = "Aquantia AQR113C",
+ .probe = aqr107_probe,
++ .get_rate_matching = aqr107_get_rate_matching,
+ .config_init = aqr107_config_init,
+ .config_aneg = aqr_config_aneg,
+ .config_intr = aqr_config_intr,
--- a/drivers/net/phy/aquantia_main.c
+++ b/drivers/net/phy/aquantia_main.c
-@@ -20,8 +20,10 @@
- #define PHY_ID_AQR105 0x03a1b4a2
- #define PHY_ID_AQR106 0x03a1b4d0
- #define PHY_ID_AQR107 0x03a1b4e0
-+#define PHY_ID_AQR113C 0x31c31c12
+@@ -23,6 +23,7 @@
#define PHY_ID_AQCS109 0x03a1b5c2
#define PHY_ID_AQR405 0x03a1b4b0
+ #define PHY_ID_AQR113C 0x31c31c12
+#define PHY_ID_AQR813 0x31c31cb2
#define MDIO_PHYXS_VEND_IF_STATUS 0xe812
#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3)
-@@ -381,6 +383,49 @@ static int aqr107_read_rate(struct phy_d
+@@ -415,6 +416,49 @@ static int aqr107_read_rate(struct phy_d
return 0;
}
static int aqr107_read_status(struct phy_device *phydev)
{
int val, ret;
-@@ -511,7 +556,7 @@ static void aqr107_chip_info(struct phy_
+@@ -554,7 +598,7 @@ static void aqr107_chip_info(struct phy_
build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val);
prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val);
fw_major, fw_minor, build_id, prov_id);
}
-@@ -719,6 +764,24 @@ static struct phy_driver aqr_driver[] =
+@@ -811,7 +855,7 @@ static struct phy_driver aqr_driver[] =
+ .config_aneg = aqr_config_aneg,
+ .config_intr = aqr_config_intr,
+ .handle_interrupt = aqr_handle_interrupt,
+- .read_status = aqr107_read_status,
++ .read_status = aqr113c_read_status,
+ .get_tunable = aqr107_get_tunable,
+ .set_tunable = aqr107_set_tunable,
+ .suspend = aqr107_suspend,
+@@ -821,6 +865,24 @@ static struct phy_driver aqr_driver[] =
+ .get_stats = aqr107_get_stats,
.link_change_notify = aqr107_link_change_notify,
},
- {
-+ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C),
-+ .name = "Aquantia AQR113C",
-+ .probe = aqr107_probe,
-+ .config_init = aqr107_config_init,
-+ .config_aneg = aqr_config_aneg,
-+ .config_intr = aqr_config_intr,
-+ .handle_interrupt = aqr_handle_interrupt,
-+ .read_status = aqr113c_read_status,
-+ .get_tunable = aqr107_get_tunable,
-+ .set_tunable = aqr107_set_tunable,
-+ .suspend = aqr107_suspend,
-+ .resume = aqr107_resume,
-+ .get_sset_count = aqr107_get_sset_count,
-+ .get_strings = aqr107_get_strings,
-+ .get_stats = aqr107_get_stats,
-+ .link_change_notify = aqr107_link_change_notify,
-+},
-+{
- PHY_ID_MATCH_MODEL(PHY_ID_AQCS109),
- .name = "Aquantia AQCS109",
- .probe = aqr107_probe,
-@@ -744,6 +807,24 @@ static struct phy_driver aqr_driver[] =
- .handle_interrupt = aqr_handle_interrupt,
- .read_status = aqr_read_status,
- },
+{
+ PHY_ID_MATCH_MODEL(PHY_ID_AQR813),
+ .name = "Aquantia AQR813",
};
module_phy_driver(aqr_driver);
-@@ -754,8 +835,10 @@ static struct mdio_device_id __maybe_unu
- { PHY_ID_MATCH_MODEL(PHY_ID_AQR105) },
- { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) },
- { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },
-+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
+@@ -834,6 +896,7 @@ static struct mdio_device_id __maybe_unu
{ PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR813) },
{ }
};
--- a/drivers/net/phy/aquantia_main.c
+++ b/drivers/net/phy/aquantia_main.c
-@@ -20,9 +20,11 @@
- #define PHY_ID_AQR105 0x03a1b4a2
- #define PHY_ID_AQR106 0x03a1b4d0
- #define PHY_ID_AQR107 0x03a1b4e0
-+#define PHY_ID_AQR112 0x03a1b662
- #define PHY_ID_AQR113C 0x31c31c12
- #define PHY_ID_AQCS109 0x03a1b5c2
+@@ -24,6 +24,8 @@
#define PHY_ID_AQR405 0x03a1b4b0
-+#define PHY_ID_AQR412 0x03a1b712
+ #define PHY_ID_AQR113C 0x31c31c12
#define PHY_ID_AQR813 0x31c31cb2
++#define PHY_ID_AQR112 0x03a1b662
++#define PHY_ID_AQR412 0x03a1b712
#define MDIO_PHYXS_VEND_IF_STATUS 0xe812
-@@ -135,6 +137,29 @@
+ #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3)
+@@ -151,6 +153,29 @@
#define AQR107_OP_IN_PROG_SLEEP 1000
#define AQR107_OP_IN_PROG_TIMEOUT 100000
struct aqr107_hw_stat {
const char *name;
int reg;
-@@ -266,6 +291,51 @@ static int aqr_config_aneg(struct phy_de
+@@ -282,6 +307,51 @@ static int aqr_config_aneg(struct phy_de
return genphy_c45_check_and_restart_aneg(phydev, changed);
}
static int aqr_config_intr(struct phy_device *phydev)
{
bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED;
-@@ -825,6 +895,30 @@ static struct phy_driver aqr_driver[] =
+@@ -883,6 +953,30 @@ static struct phy_driver aqr_driver[] =
.get_stats = aqr107_get_stats,
.link_change_notify = aqr107_link_change_notify,
},
};
module_phy_driver(aqr_driver);
-@@ -835,9 +929,11 @@ static struct mdio_device_id __maybe_unu
- { PHY_ID_MATCH_MODEL(PHY_ID_AQR105) },
- { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) },
- { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },
-+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR112) },
- { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
- { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },
+@@ -897,6 +991,8 @@ static struct mdio_device_id __maybe_unu
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
-+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR412) },
+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR813) },
++ { PHY_ID_MATCH_MODEL(PHY_ID_AQR112) },
++ { PHY_ID_MATCH_MODEL(PHY_ID_AQR412) },
{ }
};
+
--- a/drivers/net/phy/aquantia_main.c
+++ b/drivers/net/phy/aquantia_main.c
-@@ -324,10 +324,16 @@ static int aqr_config_aneg_set_prot(stru
+@@ -340,10 +340,16 @@ static int aqr_config_aneg_set_prot(stru
phy_write_mmd(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GSTART_RATE,
aquantia_syscfg[if_type].start_rate);
--- a/drivers/net/phy/aquantia_main.c
+++ b/drivers/net/phy/aquantia_main.c
-@@ -21,6 +21,7 @@
- #define PHY_ID_AQR106 0x03a1b4d0
- #define PHY_ID_AQR107 0x03a1b4e0
+@@ -26,6 +26,7 @@
+ #define PHY_ID_AQR813 0x31c31cb2
#define PHY_ID_AQR112 0x03a1b662
+ #define PHY_ID_AQR412 0x03a1b712
+#define PHY_ID_AQR113 0x31c31c40
- #define PHY_ID_AQR113C 0x31c31c12
- #define PHY_ID_AQCS109 0x03a1b5c2
- #define PHY_ID_AQR405 0x03a1b4b0
-@@ -914,6 +915,14 @@ static struct phy_driver aqr_driver[] =
+
+ #define MDIO_PHYXS_VEND_IF_STATUS 0xe812
+ #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3)
+@@ -972,6 +973,14 @@ static struct phy_driver aqr_driver[] =
.get_stats = aqr107_get_stats,
},
{
PHY_ID_MATCH_MODEL(PHY_ID_AQR412),
.name = "Aquantia AQR412",
.probe = aqr107_probe,
-@@ -936,6 +945,7 @@ static struct mdio_device_id __maybe_unu
- { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) },
- { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },
+@@ -999,6 +1008,7 @@ static struct mdio_device_id __maybe_unu
+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR813) },
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR112) },
+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR412) },
+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR113) },
- { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
- { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },
- { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
+ { }
+ };
+
--- a/drivers/net/phy/aquantia_main.c
+++ b/drivers/net/phy/aquantia_main.c
-@@ -21,6 +21,8 @@
- #define PHY_ID_AQR106 0x03a1b4d0
- #define PHY_ID_AQR107 0x03a1b4e0
+@@ -27,6 +27,8 @@
#define PHY_ID_AQR112 0x03a1b662
+ #define PHY_ID_AQR412 0x03a1b712
+ #define PHY_ID_AQR113 0x31c31c40
+#define PHY_ID_AQR112C 0x03a1b790
+#define PHY_ID_AQR112R 0x31c31d12
- #define PHY_ID_AQR113 0x31c31c40
- #define PHY_ID_AQR113C 0x31c31c12
- #define PHY_ID_AQCS109 0x03a1b5c2
-@@ -915,6 +917,30 @@ static struct phy_driver aqr_driver[] =
+
+ #define MDIO_PHYXS_VEND_IF_STATUS 0xe812
+ #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3)
+@@ -973,6 +975,30 @@ static struct phy_driver aqr_driver[] =
.get_stats = aqr107_get_stats,
},
{
PHY_ID_MATCH_MODEL(PHY_ID_AQR113),
.name = "Aquantia AQR113",
.config_aneg = aqr_config_aneg,
-@@ -945,6 +971,8 @@ static struct mdio_device_id __maybe_unu
- { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) },
- { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },
+@@ -1009,6 +1035,8 @@ static struct mdio_device_id __maybe_unu
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR112) },
+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR412) },
+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR113) },
+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR112C) },
+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR112R) },
- { PHY_ID_MATCH_MODEL(PHY_ID_AQR113) },
- { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
- { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },
+ { }
+ };
+
Signed-off-by: Thomas Kupper <thomas.kupper@gmail.com>
--- a/drivers/net/phy/aquantia_main.c
+++ b/drivers/net/phy/aquantia_main.c
-@@ -20,6 +20,8 @@
- #define PHY_ID_AQR105 0x03a1b4a2
- #define PHY_ID_AQR106 0x03a1b4d0
- #define PHY_ID_AQR107 0x03a1b4e0
+@@ -24,6 +24,8 @@
+ #define PHY_ID_AQR405 0x03a1b4b0
+ #define PHY_ID_AQR113C 0x31c31c12
+ #define PHY_ID_AQR813 0x31c31cb2
+#define PHY_ID_AQR111 0x03a1b610
+#define PHY_ID_AQR111B0 0x03a1b612
#define PHY_ID_AQR112 0x03a1b662
- #define PHY_ID_AQR112C 0x03a1b790
- #define PHY_ID_AQR112R 0x31c31d12
-@@ -686,6 +688,33 @@ static int aqcs109_config_init(struct ph
+ #define PHY_ID_AQR412 0x03a1b712
+ #define PHY_ID_AQR113 0x31c31c40
+@@ -731,6 +733,33 @@ static int aqcs109_config_init(struct ph
return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
}
static void aqr107_link_change_notify(struct phy_device *phydev)
{
u8 fw_major, fw_minor;
-@@ -905,6 +934,42 @@ static struct phy_driver aqr_driver[] =
+@@ -963,6 +992,42 @@ static struct phy_driver aqr_driver[] =
.link_change_notify = aqr107_link_change_notify,
},
{
PHY_ID_MATCH_MODEL(PHY_ID_AQR112),
.name = "Aquantia AQR112",
.probe = aqr107_probe,
-@@ -970,6 +1035,8 @@ static struct mdio_device_id __maybe_unu
- { PHY_ID_MATCH_MODEL(PHY_ID_AQR105) },
- { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) },
- { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },
+@@ -1032,6 +1097,8 @@ static struct mdio_device_id __maybe_unu
+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR813) },
+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR111) },
+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR111B0) },
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR112) },
- { PHY_ID_MATCH_MODEL(PHY_ID_AQR112C) },
- { PHY_ID_MATCH_MODEL(PHY_ID_AQR112R) },
+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR412) },
+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR113) },
projects / openwrt / staging / stintel.git / commitdiff