target/linux/ramips/patches-6.1/825-i2c-MIPS-adds-ralink-I2C-driver.patch

   1 From 723b8beaabf3c3c4b1ce69480141f1e926f3f3b2 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sun, 27 Jul 2014 09:52:56 +0100
   4 Subject: [PATCH 44/53] i2c: MIPS: adds ralink I2C driver
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  .../devicetree/bindings/i2c/i2c-ralink.txt         |   27 ++
   9  drivers/i2c/busses/Kconfig                         |    4 +
  10  drivers/i2c/busses/Makefile                        |    1 +
  11  drivers/i2c/busses/i2c-ralink.c                    |  327 ++++++++++++++++++++
  12  4 files changed, 359 insertions(+)
  13  create mode 100644 Documentation/devicetree/bindings/i2c/i2c-ralink.txt
  14  create mode 100644 drivers/i2c/busses/i2c-ralink.c
  15
  16 --- /dev/null
  17 +++ b/Documentation/devicetree/bindings/i2c/i2c-ralink.txt
  18 @@ -0,0 +1,27 @@
  19 +I2C for Ralink platforms
  20 +
  21 +Required properties :
  22 +- compatible : Must be "link,rt3052-i2c"
  23 +- reg: physical base address of the controller and length of memory mapped
  24 +     region.
  25 +- #address-cells = <1>;
  26 +- #size-cells = <0>;
  27 +
  28 +Optional properties:
  29 +- Child nodes conforming to i2c bus binding
  30 +
  31 +Example :
  32 +
  33 +palmbus@10000000 {
  34 +       i2c@900 {
  35 +               compatible = "link,rt3052-i2c";
  36 +               reg = <0x900 0x100>;
  37 +               #address-cells = <1>;
  38 +               #size-cells = <0>;
  39 +
  40 +               hwmon@4b {
  41 +                       compatible = "national,lm92";
  42 +                       reg = <0x4b>;
  43 +               };
  44 +       };
  45 +};
  46 --- a/drivers/i2c/busses/Kconfig
  47 +++ b/drivers/i2c/busses/Kconfig
  48 @@ -998,6 +998,11 @@ config I2C_RK3X
  49           This driver can also be built as a module. If so, the module will
  50           be called i2c-rk3x.
  51
  52 +config I2C_RALINK
  53 +       tristate "Ralink I2C Controller"
  54 +       depends on RALINK && !SOC_MT7621
  55 +       select OF_I2C
  56 +
  57  config I2C_RZV2M
  58         tristate "Renesas RZ/V2M adapter"
  59         depends on ARCH_RENESAS || COMPILE_TEST
  60 --- a/drivers/i2c/busses/Makefile
  61 +++ b/drivers/i2c/busses/Makefile
  62 @@ -95,6 +95,7 @@ obj-$(CONFIG_I2C_PCA_PLATFORM)        += i2c-pc
  63  obj-$(CONFIG_I2C_PNX)          += i2c-pnx.o
  64  obj-$(CONFIG_I2C_PXA)          += i2c-pxa.o
  65  obj-$(CONFIG_I2C_PXA_PCI)      += i2c-pxa-pci.o
  66 +obj-$(CONFIG_I2C_RALINK)       += i2c-ralink.o
  67  obj-$(CONFIG_I2C_QCOM_CCI)     += i2c-qcom-cci.o
  68  obj-$(CONFIG_I2C_QCOM_GENI)    += i2c-qcom-geni.o
  69  obj-$(CONFIG_I2C_QUP)          += i2c-qup.o
  70 --- /dev/null
  71 +++ b/drivers/i2c/busses/i2c-ralink.c
  72 @@ -0,0 +1,440 @@
  73 +/*
  74 + * drivers/i2c/busses/i2c-ralink.c
  75 + *
  76 + * Copyright (C) 2013 Steven Liu <steven_liu@mediatek.com>
  77 + * Copyright (C) 2016 Michael Lee <igvtee@gmail.com>
  78 + *
  79 + * Improve driver for i2cdetect from i2c-tools to detect i2c devices on the bus.
  80 + * (C) 2014 Sittisak <sittisaks@hotmail.com>
  81 + *
  82 + * This software is licensed under the terms of the GNU General Public
  83 + * License version 2, as published by the Free Software Foundation, and
  84 + * may be copied, distributed, and modified under those terms.
  85 + *
  86 + * This program is distributed in the hope that it will be useful,
  87 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  88 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  89 + * GNU General Public License for more details.
  90 + *
  91 + */
  92 +
  93 +#include <linux/interrupt.h>
  94 +#include <linux/kernel.h>
  95 +#include <linux/module.h>
  96 +#include <linux/reset.h>
  97 +#include <linux/delay.h>
  98 +#include <linux/slab.h>
  99 +#include <linux/init.h>
 100 +#include <linux/errno.h>
 101 +#include <linux/platform_device.h>
 102 +#include <linux/of_platform.h>
 103 +#include <linux/i2c.h>
 104 +#include <linux/io.h>
 105 +#include <linux/err.h>
 106 +#include <linux/clk.h>
 107 +
 108 +#define REG_CONFIG_REG         0x00
 109 +#define REG_CLKDIV_REG         0x04
 110 +#define REG_DEVADDR_REG                0x08
 111 +#define REG_ADDR_REG           0x0C
 112 +#define REG_DATAOUT_REG                0x10
 113 +#define REG_DATAIN_REG         0x14
 114 +#define REG_STATUS_REG         0x18
 115 +#define REG_STARTXFR_REG       0x1C
 116 +#define REG_BYTECNT_REG                0x20
 117 +
 118 +/* REG_CONFIG_REG */
 119 +#define I2C_ADDRLEN_OFFSET     5
 120 +#define I2C_DEVADLEN_OFFSET    2
 121 +#define I2C_ADDRLEN_MASK       0x3
 122 +#define I2C_ADDR_DIS           BIT(1)
 123 +#define I2C_DEVADDR_DIS                BIT(0)
 124 +#define I2C_ADDRLEN_8          (7 << I2C_ADDRLEN_OFFSET)
 125 +#define I2C_DEVADLEN_7         (6 << I2C_DEVADLEN_OFFSET)
 126 +#define I2C_CONF_DEFAULT       (I2C_ADDRLEN_8 | I2C_DEVADLEN_7)
 127 +
 128 +/* REG_CLKDIV_REG */
 129 +#define I2C_CLKDIV_MASK                0xffff
 130 +
 131 +/* REG_DEVADDR_REG */
 132 +#define I2C_DEVADDR_MASK       0x7f
 133 +
 134 +/* REG_ADDR_REG */
 135 +#define I2C_ADDR_MASK          0xff
 136 +
 137 +/* REG_STATUS_REG */
 138 +#define I2C_STARTERR           BIT(4)
 139 +#define I2C_ACKERR             BIT(3)
 140 +#define I2C_DATARDY            BIT(2)
 141 +#define I2C_SDOEMPTY           BIT(1)
 142 +#define I2C_BUSY               BIT(0)
 143 +
 144 +/* REG_STARTXFR_REG */
 145 +#define NOSTOP_CMD             BIT(2)
 146 +#define NODATA_CMD             BIT(1)
 147 +#define READ_CMD               BIT(0)
 148 +
 149 +/* REG_BYTECNT_REG */
 150 +#define BYTECNT_MAX            64
 151 +#define SET_BYTECNT(x)         (x - 1)
 152 +
 153 +/* timeout waiting for I2C devices to respond (clock streching) */
 154 +#define TIMEOUT_MS              1000
 155 +#define DELAY_INTERVAL_US       100
 156 +
 157 +struct rt_i2c {
 158 +       void __iomem *base;
 159 +       struct clk *clk;
 160 +       struct device *dev;
 161 +       struct i2c_adapter adap;
 162 +       u32 cur_clk;
 163 +       u32 clk_div;
 164 +       u32 flags;
 165 +};
 166 +
 167 +static void rt_i2c_w32(struct rt_i2c *i2c, u32 val, unsigned reg)
 168 +{
 169 +       iowrite32(val, i2c->base + reg);
 170 +}
 171 +
 172 +static u32 rt_i2c_r32(struct rt_i2c *i2c, unsigned reg)
 173 +{
 174 +       return ioread32(i2c->base + reg);
 175 +}
 176 +
 177 +static int poll_down_timeout(void __iomem *addr, u32 mask)
 178 +{
 179 +       unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS);
 180 +
 181 +       do {
 182 +               if (!(readl_relaxed(addr) & mask))
 183 +                       return 0;
 184 +
 185 +               usleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50);
 186 +       } while (time_before(jiffies, timeout));
 187 +
 188 +       return (readl_relaxed(addr) & mask) ? -EAGAIN : 0;
 189 +}
 190 +
 191 +static int rt_i2c_wait_idle(struct rt_i2c *i2c)
 192 +{
 193 +       int ret;
 194 +
 195 +       ret = poll_down_timeout(i2c->base + REG_STATUS_REG, I2C_BUSY);
 196 +       if (ret < 0)
 197 +               dev_dbg(i2c->dev, "idle err(%d)\n", ret);
 198 +
 199 +       return ret;
 200 +}
 201 +
 202 +static int poll_up_timeout(void __iomem *addr, u32 mask)
 203 +{
 204 +       unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS);
 205 +       u32 status;
 206 +
 207 +       do {
 208 +               status = readl_relaxed(addr);
 209 +
 210 +               /* check error status */
 211 +               if (status & I2C_STARTERR)
 212 +                       return -EAGAIN;
 213 +               else if (status & I2C_ACKERR)
 214 +                       return -ENXIO;
 215 +               else if (status & mask)
 216 +                       return 0;
 217 +
 218 +               usleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50);
 219 +       } while (time_before(jiffies, timeout));
 220 +
 221 +       return -ETIMEDOUT;
 222 +}
 223 +
 224 +static int rt_i2c_wait_rx_done(struct rt_i2c *i2c)
 225 +{
 226 +       int ret;
 227 +
 228 +       ret = poll_up_timeout(i2c->base + REG_STATUS_REG, I2C_DATARDY);
 229 +       if (ret < 0)
 230 +               dev_dbg(i2c->dev, "rx err(%d)\n", ret);
 231 +
 232 +       return ret;
 233 +}
 234 +
 235 +static int rt_i2c_wait_tx_done(struct rt_i2c *i2c)
 236 +{
 237 +       int ret;
 238 +
 239 +       ret = poll_up_timeout(i2c->base + REG_STATUS_REG, I2C_SDOEMPTY);
 240 +       if (ret < 0)
 241 +               dev_dbg(i2c->dev, "tx err(%d)\n", ret);
 242 +
 243 +       return ret;
 244 +}
 245 +
 246 +static void rt_i2c_reset(struct rt_i2c *i2c)
 247 +{
 248 +       int ret;
 249 +
 250 +       ret = device_reset(i2c->adap.dev.parent);
 251 +       if (ret)
 252 +               dev_err(i2c->dev, "Failed to reset device");
 253 +
 254 +       barrier();
 255 +       rt_i2c_w32(i2c, i2c->clk_div, REG_CLKDIV_REG);
 256 +}
 257 +
 258 +static void rt_i2c_dump_reg(struct rt_i2c *i2c)
 259 +{
 260 +       dev_dbg(i2c->dev, "conf %08x, clkdiv %08x, devaddr %08x, " \
 261 +                       "addr %08x, dataout %08x, datain %08x, " \
 262 +                       "status %08x, startxfr %08x, bytecnt %08x\n",
 263 +                       rt_i2c_r32(i2c, REG_CONFIG_REG),
 264 +                       rt_i2c_r32(i2c, REG_CLKDIV_REG),
 265 +                       rt_i2c_r32(i2c, REG_DEVADDR_REG),
 266 +                       rt_i2c_r32(i2c, REG_ADDR_REG),
 267 +                       rt_i2c_r32(i2c, REG_DATAOUT_REG),
 268 +                       rt_i2c_r32(i2c, REG_DATAIN_REG),
 269 +                       rt_i2c_r32(i2c, REG_STATUS_REG),
 270 +                       rt_i2c_r32(i2c, REG_STARTXFR_REG),
 271 +                       rt_i2c_r32(i2c, REG_BYTECNT_REG));
 272 +}
 273 +
 274 +static int rt_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
 275 +               int num)
 276 +{
 277 +       struct rt_i2c *i2c;
 278 +       struct i2c_msg *pmsg;
 279 +       unsigned char addr;
 280 +       int i, j, ret;
 281 +       u32 cmd;
 282 +
 283 +       i2c = i2c_get_adapdata(adap);
 284 +
 285 +       for (i = 0; i < num; i++) {
 286 +               pmsg = &msgs[i];
 287 +               if (i == (num - 1))
 288 +                       cmd = 0;
 289 +               else
 290 +                       cmd = NOSTOP_CMD;
 291 +
 292 +               dev_dbg(i2c->dev, "addr: 0x%x, len: %d, flags: 0x%x, stop: %d\n",
 293 +                               pmsg->addr, pmsg->len, pmsg->flags,
 294 +                               (cmd == 0)? 1 : 0);
 295 +
 296 +               /* wait hardware idle */
 297 +               if ((ret = rt_i2c_wait_idle(i2c)))
 298 +                       goto err_timeout;
 299 +
 300 +               if (pmsg->flags & I2C_M_TEN) {
 301 +                       rt_i2c_w32(i2c, I2C_CONF_DEFAULT, REG_CONFIG_REG);
 302 +                       /* 10 bits address */
 303 +                       addr = 0x78 | ((pmsg->addr >> 8) & 0x03);
 304 +                       rt_i2c_w32(i2c, addr & I2C_DEVADDR_MASK,
 305 +                                       REG_DEVADDR_REG);
 306 +                       rt_i2c_w32(i2c, pmsg->addr & I2C_ADDR_MASK,
 307 +                                       REG_ADDR_REG);
 308 +               } else {
 309 +                       rt_i2c_w32(i2c, I2C_CONF_DEFAULT | I2C_ADDR_DIS,
 310 +                                       REG_CONFIG_REG);
 311 +                       /* 7 bits address */
 312 +                       rt_i2c_w32(i2c, pmsg->addr & I2C_DEVADDR_MASK,
 313 +                                       REG_DEVADDR_REG);
 314 +               }
 315 +
 316 +               /* buffer length */
 317 +               if (pmsg->len == 0)
 318 +                       cmd |= NODATA_CMD;
 319 +               else
 320 +                       rt_i2c_w32(i2c, SET_BYTECNT(pmsg->len),
 321 +                                       REG_BYTECNT_REG);
 322 +
 323 +               j = 0;
 324 +               if (pmsg->flags & I2C_M_RD) {
 325 +                       cmd |= READ_CMD;
 326 +                       /* start transfer */
 327 +                       barrier();
 328 +                       rt_i2c_w32(i2c, cmd, REG_STARTXFR_REG);
 329 +                       do {
 330 +                               /* wait */
 331 +                               if ((ret = rt_i2c_wait_rx_done(i2c)))
 332 +                                       goto err_timeout;
 333 +                               /* read data */
 334 +                               if (pmsg->len)
 335 +                                       pmsg->buf[j] = rt_i2c_r32(i2c,
 336 +                                                       REG_DATAIN_REG);
 337 +                               j++;
 338 +                       } while (j < pmsg->len);
 339 +               } else {
 340 +                       do {
 341 +                               /* write data */
 342 +                               if (pmsg->len)
 343 +                                       rt_i2c_w32(i2c, pmsg->buf[j],
 344 +                                                       REG_DATAOUT_REG);
 345 +                               /* start transfer */
 346 +                               if (j == 0) {
 347 +                                       barrier();
 348 +                                       rt_i2c_w32(i2c, cmd, REG_STARTXFR_REG);
 349 +                               }
 350 +                               /* wait */
 351 +                               if ((ret = rt_i2c_wait_tx_done(i2c)))
 352 +                                       goto err_timeout;
 353 +                               j++;
 354 +                       } while (j < pmsg->len);
 355 +               }
 356 +       }
 357 +       /* the return value is number of executed messages */
 358 +       ret = i;
 359 +
 360 +       return ret;
 361 +
 362 +err_timeout:
 363 +       rt_i2c_dump_reg(i2c);
 364 +       rt_i2c_reset(i2c);
 365 +       return ret;
 366 +}
 367 +
 368 +static u32 rt_i2c_func(struct i2c_adapter *a)
 369 +{
 370 +       return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 371 +}
 372 +
 373 +static const struct i2c_algorithm rt_i2c_algo = {
 374 +       .master_xfer    = rt_i2c_master_xfer,
 375 +       .functionality  = rt_i2c_func,
 376 +};
 377 +
 378 +static const struct of_device_id i2c_rt_dt_ids[] = {
 379 +       { .compatible = "ralink,rt2880-i2c" },
 380 +       { /* sentinel */ }
 381 +};
 382 +
 383 +MODULE_DEVICE_TABLE(of, i2c_rt_dt_ids);
 384 +
 385 +static struct i2c_adapter_quirks rt_i2c_quirks = {
 386 +        .max_write_len = BYTECNT_MAX,
 387 +        .max_read_len = BYTECNT_MAX,
 388 +};
 389 +
 390 +static int rt_i2c_init(struct rt_i2c *i2c)
 391 +{
 392 +       u32 reg;
 393 +
 394 +       /* i2c_sclk = periph_clk / ((2 * clk_div) + 5) */
 395 +       i2c->clk_div = (clk_get_rate(i2c->clk) - (5 * i2c->cur_clk)) /
 396 +               (2 * i2c->cur_clk);
 397 +       if (i2c->clk_div < 8)
 398 +               i2c->clk_div = 8;
 399 +       if (i2c->clk_div > I2C_CLKDIV_MASK)
 400 +               i2c->clk_div = I2C_CLKDIV_MASK;
 401 +
 402 +       /* check support combinde/repeated start message */
 403 +       rt_i2c_w32(i2c, NOSTOP_CMD, REG_STARTXFR_REG);
 404 +       reg = rt_i2c_r32(i2c, REG_STARTXFR_REG) & NOSTOP_CMD;
 405 +
 406 +       rt_i2c_reset(i2c);
 407 +
 408 +       return reg;
 409 +}
 410 +
 411 +static int rt_i2c_probe(struct platform_device *pdev)
 412 +{
 413 +       struct resource *res;
 414 +       struct rt_i2c *i2c;
 415 +       struct i2c_adapter *adap;
 416 +       const struct of_device_id *match;
 417 +       int ret, restart;
 418 +
 419 +       match = of_match_device(i2c_rt_dt_ids, &pdev->dev);
 420 +
 421 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 422 +       if (!res) {
 423 +               dev_err(&pdev->dev, "no memory resource found\n");
 424 +               return -ENODEV;
 425 +       }
 426 +
 427 +       i2c = devm_kzalloc(&pdev->dev, sizeof(struct rt_i2c), GFP_KERNEL);
 428 +       if (!i2c) {
 429 +               dev_err(&pdev->dev, "failed to allocate i2c_adapter\n");
 430 +               return -ENOMEM;
 431 +       }
 432 +
 433 +       i2c->base = devm_ioremap_resource(&pdev->dev, res);
 434 +       if (IS_ERR(i2c->base))
 435 +               return PTR_ERR(i2c->base);
 436 +
 437 +       i2c->clk = devm_clk_get(&pdev->dev, NULL);
 438 +       if (IS_ERR(i2c->clk)) {
 439 +               dev_err(&pdev->dev, "no clock defined\n");
 440 +               return -ENODEV;
 441 +       }
 442 +       clk_prepare_enable(i2c->clk);
 443 +       i2c->dev = &pdev->dev;
 444 +
 445 +       if (of_property_read_u32(pdev->dev.of_node,
 446 +                               "clock-frequency", &i2c->cur_clk))
 447 +               i2c->cur_clk = 100000;
 448 +
 449 +       adap = &i2c->adap;
 450 +       adap->owner = THIS_MODULE;
 451 +       adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
 452 +       adap->algo = &rt_i2c_algo;
 453 +       adap->retries = 3;
 454 +       adap->dev.parent = &pdev->dev;
 455 +       i2c_set_adapdata(adap, i2c);
 456 +       adap->dev.of_node = pdev->dev.of_node;
 457 +       strlcpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name));
 458 +       adap->quirks = &rt_i2c_quirks;
 459 +
 460 +       platform_set_drvdata(pdev, i2c);
 461 +
 462 +       restart = rt_i2c_init(i2c);
 463 +
 464 +       ret = i2c_add_adapter(adap);
 465 +       if (ret < 0) {
 466 +               dev_err(&pdev->dev, "failed to add adapter\n");
 467 +               clk_disable_unprepare(i2c->clk);
 468 +               return ret;
 469 +       }
 470 +
 471 +       dev_info(&pdev->dev, "clock %uKHz, re-start %ssupport\n",
 472 +                       i2c->cur_clk/1000, restart ? "" : "not ");
 473 +
 474 +       return ret;
 475 +}
 476 +
 477 +static int rt_i2c_remove(struct platform_device *pdev)
 478 +{
 479 +       struct rt_i2c *i2c = platform_get_drvdata(pdev);
 480 +
 481 +       i2c_del_adapter(&i2c->adap);
 482 +       clk_disable_unprepare(i2c->clk);
 483 +
 484 +       return 0;
 485 +}
 486 +
 487 +static struct platform_driver rt_i2c_driver = {
 488 +       .probe          = rt_i2c_probe,
 489 +       .remove         = rt_i2c_remove,
 490 +       .driver         = {
 491 +               .owner  = THIS_MODULE,
 492 +               .name   = "i2c-ralink",
 493 +               .of_match_table = i2c_rt_dt_ids,
 494 +       },
 495 +};
 496 +
 497 +static int __init i2c_rt_init (void)
 498 +{
 499 +       return platform_driver_register(&rt_i2c_driver);
 500 +}
 501 +subsys_initcall(i2c_rt_init);
 502 +
 503 +static void __exit i2c_rt_exit (void)
 504 +{
 505 +       platform_driver_unregister(&rt_i2c_driver);
 506 +}
 507 +module_exit(i2c_rt_exit);
 508 +
 509 +MODULE_AUTHOR("Steven Liu <steven_liu@mediatek.com>");
 510 +MODULE_DESCRIPTION("Ralink I2c host driver");
 511 +MODULE_LICENSE("GPL");
 512 +MODULE_ALIAS("platform:Ralink-I2C");