target/linux/qualcommax/patches-6.1/0055-v6.8-arm64-dts-ipq6018-Add-remaining-QUP-UART-node.patch

   1 From e6c32770ef83f3e8cc057f3920b1c06aa9d1c9c2 Mon Sep 17 00:00:00 2001
   2 From: Chukun Pan <amadeus@jmu.edu.cn>
   3 Date: Sun, 3 Dec 2023 23:39:14 +0800
   4 Subject: [PATCH] arm64: dts: qcom: ipq6018: Add remaining QUP UART node
   5
   6 Add node to support all the QUP UART node controller inside of IPQ6018.
   7 Some routers use these bus to connect Bluetooth chips.
   8
   9 Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
  10 Link: https://lore.kernel.org/r/20231203153914.532654-1-amadeus@jmu.edu.cn
  11 Signed-off-by: Bjorn Andersson <andersson@kernel.org>
  12 ---
  13  arch/arm64/boot/dts/qcom/ipq6018.dtsi | 50 +++++++++++++++++++++++++++
  14  1 file changed, 50 insertions(+)
  15
  16 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
  17 +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
  18 @@ -458,6 +458,26 @@
  19                         qcom,ee = <0>;
  20                 };
  21
  22 +               blsp1_uart1: serial@78af000 {
  23 +                       compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
  24 +                       reg = <0x0 0x78af000 0x0 0x200>;
  25 +                       interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
  26 +                       clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
  27 +                                <&gcc GCC_BLSP1_AHB_CLK>;
  28 +                       clock-names = "core", "iface";
  29 +                       status = "disabled";
  30 +               };
  31 +
  32 +               blsp1_uart2: serial@78b0000 {
  33 +                       compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
  34 +                       reg = <0x0 0x78b0000 0x0 0x200>;
  35 +                       interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
  36 +                       clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
  37 +                                <&gcc GCC_BLSP1_AHB_CLK>;
  38 +                       clock-names = "core", "iface";
  39 +                       status = "disabled";
  40 +               };
  41 +
  42                 blsp1_uart3: serial@78b1000 {
  43                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
  44                         reg = <0x0 0x078b1000 0x0 0x200>;
  45 @@ -466,6 +486,36 @@
  46                                  <&gcc GCC_BLSP1_AHB_CLK>;
  47                         clock-names = "core", "iface";
  48                         status = "disabled";
  49 +               };
  50 +
  51 +               blsp1_uart4: serial@78b2000 {
  52 +                       compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
  53 +                       reg = <0x0 0x078b2000 0x0 0x200>;
  54 +                       interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
  55 +                       clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>,
  56 +                                <&gcc GCC_BLSP1_AHB_CLK>;
  57 +                       clock-names = "core", "iface";
  58 +                       status = "disabled";
  59 +               };
  60 +
  61 +               blsp1_uart5: serial@78b3000 {
  62 +                       compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
  63 +                       reg = <0x0 0x78b3000 0x0 0x200>;
  64 +                       interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
  65 +                       clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>,
  66 +                                <&gcc GCC_BLSP1_AHB_CLK>;
  67 +                       clock-names = "core", "iface";
  68 +                       status = "disabled";
  69 +               };
  70 +
  71 +               blsp1_uart6: serial@78b4000 {
  72 +                       compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
  73 +                       reg = <0x0 0x078b4000 0x0 0x200>;
  74 +                       interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
  75 +                       clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>,
  76 +                                <&gcc GCC_BLSP1_AHB_CLK>;
  77 +                       clock-names = "core", "iface";
  78 +                       status = "disabled";
  79                 };
  80
  81                 blsp1_spi1: spi@78b5000 {