1 From 83afcf14edb9217e58837eb119da96d734a4b3b1 Mon Sep 17 00:00:00 2001
2 From: Robert Marko <robimarko@gmail.com>
3 Date: Sat, 21 Oct 2023 14:00:07 +0200
4 Subject: [PATCH] arm64: dts: qcom: ipq6018: use CPUFreq NVMEM
6 IPQ6018 comes in multiple SKU-s and some of them dont support all of the
7 OPP-s that are current set, so lets utilize CPUFreq NVMEM to allow only
8 supported OPP-s based on the SoC dynamically.
10 As an example, IPQ6018 is generaly rated at 1.8GHz but some silicon only
11 goes up to 1.5GHz and is marked as such via an eFuse.
13 Signed-off-by: Robert Marko <robimarko@gmail.com>
14 Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
15 Link: https://lore.kernel.org/r/20231021120048.231239-1-robimarko@gmail.com
16 Signed-off-by: Bjorn Andersson <andersson@kernel.org>
18 arch/arm64/boot/dts/qcom/ipq6018.dtsi | 14 +++++++++++++-
19 1 file changed, 13 insertions(+), 1 deletion(-)
21 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
22 +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
26 cpu_opp_table: opp-table-cpu {
27 - compatible = "operating-points-v2";
28 + compatible = "operating-points-v2-kryo-cpu";
29 + nvmem-cells = <&cpu_speed_bin>;
33 opp-hz = /bits/ 64 <864000000>;
34 opp-microvolt = <725000>;
35 + opp-supported-hw = <0xf>;
36 clock-latency-ns = <200000>;
40 opp-hz = /bits/ 64 <1056000000>;
41 opp-microvolt = <787500>;
42 + opp-supported-hw = <0xf>;
43 clock-latency-ns = <200000>;
47 opp-hz = /bits/ 64 <1320000000>;
48 opp-microvolt = <862500>;
49 + opp-supported-hw = <0x3>;
50 clock-latency-ns = <200000>;
54 opp-hz = /bits/ 64 <1440000000>;
55 opp-microvolt = <925000>;
56 + opp-supported-hw = <0x3>;
57 clock-latency-ns = <200000>;
61 opp-hz = /bits/ 64 <1608000000>;
62 opp-microvolt = <987500>;
63 + opp-supported-hw = <0x1>;
64 clock-latency-ns = <200000>;
68 opp-hz = /bits/ 64 <1800000000>;
69 opp-microvolt = <1062500>;
70 + opp-supported-hw = <0x1>;
71 clock-latency-ns = <200000>;
75 reg = <0x0 0x000a4000 0x0 0x2000>;
79 + cpu_speed_bin: cpu-speed-bin@135 {