target/linux/mediatek/dts/mt7986a-asus-tuf-ax6000.dts

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2
   3 /dts-v1/;
   4 #include <dt-bindings/input/input.h>
   5 #include <dt-bindings/gpio/gpio.h>
   6 #include <dt-bindings/leds/common.h>
   7
   8 #include "mt7986a.dtsi"
   9
  10 / {
  11         model = "ASUS TUF-AX6000";
  12         compatible = "asus,tuf-ax6000", "mediatek,mt7986a";
  13
  14         aliases {
  15                 serial0 = &uart0;
  16                 label-mac-device = &gmac0;
  17                 led-boot = &led_system;
  18                 led-failsafe = &led_system;
  19                 led-running = &led_system;
  20                 led-upgrade = &led_system;
  21         };
  22
  23         chosen {
  24                 stdout-path = "serial0:115200n8";
  25                 bootargs-override = "";
  26         };
  27
  28         memory {
  29                 reg = <0 0x40000000 0 0x20000000>;
  30         };
  31
  32         keys {
  33                 compatible = "gpio-keys";
  34
  35                 reset {
  36                         label = "reset";
  37                         gpios = <&pio 9 GPIO_ACTIVE_LOW>;
  38                         linux,code = <KEY_RESTART>;
  39                 };
  40
  41                 mesh {
  42                         label = "wps";
  43                         gpios = <&pio 10 GPIO_ACTIVE_LOW>;
  44                         linux,code = <KEY_WPS_BUTTON>;
  45                 };
  46         };
  47
  48         leds {
  49                 compatible = "gpio-leds";
  50
  51                 wlan {
  52                         function = LED_FUNCTION_WLAN;
  53                         color = <LED_COLOR_ID_WHITE>;
  54                         gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
  55                         linux,default-trigger = "phy1tpt";
  56                 };
  57
  58                 led_system: system {
  59                         label = "white:system";
  60                         gpios = <&pio 11 GPIO_ACTIVE_HIGH>;
  61                 };
  62
  63                 wan-red {
  64                         function = LED_FUNCTION_WAN;
  65                         color = <LED_COLOR_ID_RED>;
  66                         gpios = <&pio 12 GPIO_ACTIVE_LOW>;
  67                 };
  68
  69                 cover-blue {
  70                         label = "blue:cover";
  71                         gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
  72                 };
  73         };
  74
  75         reg_3p3v: regulator-3p3v {
  76                 compatible = "regulator-fixed";
  77                 regulator-name = "fixed-3.3V";
  78                 regulator-min-microvolt = <3300000>;
  79                 regulator-max-microvolt = <3300000>;
  80                 regulator-boot-on;
  81                 regulator-always-on;
  82         };
  83
  84         reg_5v: regulator-5v {
  85                 compatible = "regulator-fixed";
  86                 regulator-name = "fixed-5V";
  87                 regulator-min-microvolt = <5000000>;
  88                 regulator-max-microvolt = <5000000>;
  89                 regulator-boot-on;
  90                 regulator-always-on;
  91         };
  92 };
  93
  94 &crypto {
  95         status = "okay";
  96 };
  97
  98 &eth {
  99         status = "okay";
 100
 101         gmac0: mac@0 {
 102                 /* LAN */
 103                 compatible = "mediatek,eth-mac";
 104                 reg = <0>;
 105                 nvmem-cells = <&macaddr_factory_4>;
 106                 nvmem-cell-names = "mac-address";
 107                 phy-mode = "2500base-x";
 108
 109                 fixed-link {
 110                         speed = <2500>;
 111                         full-duplex;
 112                         pause;
 113                 };
 114         };
 115
 116         gmac1: mac@1 {
 117                 /* WAN */
 118                 compatible = "mediatek,eth-mac";
 119                 reg = <1>;
 120                 phy-mode = "2500base-x";
 121                 phy-handle = <&phy6>;
 122         };
 123
 124         mdio: mdio-bus {
 125                 #address-cells = <1>;
 126                 #size-cells = <0>;
 127         };
 128 };
 129
 130 &mdio {
 131         reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>;
 132         reset-delay-us = <50000>;
 133         reset-post-delay-us = <20000>;
 134
 135         phy5: phy@5 {
 136                 compatible = "ethernet-phy-ieee802.3-c45";
 137                 reg = <5>;
 138
 139                 mxl,led-drive-vdd;
 140                 mxl,led-config = <0x03f0 0x0 0x0 0x0>;
 141         };
 142
 143         phy6: phy@6 {
 144                 compatible = "ethernet-phy-ieee802.3-c45";
 145                 reg = <6>;
 146
 147                 /* LED0: CONN (WAN white) */
 148                 mxl,led-config = <0x03f0 0x0 0x0 0x0>;
 149         };
 150
 151         switch: switch@1f {
 152                 compatible = "mediatek,mt7531";
 153                 reg = <31>;
 154
 155                 reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
 156                 reset-assert-us = <10000>;
 157                 reset-deassert-us = <10000>;
 158         };
 159 };
 160
 161 &pio {
 162         spi_flash_pins: spi-flash-pins-33-to-38 {
 163                 mux {
 164                         function = "spi";
 165                         groups = "spi0", "spi0_wp_hold";
 166                 };
 167                 conf-pu {
 168                         pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
 169                         drive-strength = <8>;
 170                         mediatek,pull-up-adv = <0>; /* bias-disable */
 171                 };
 172                 conf-pd {
 173                         pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
 174                         drive-strength = <8>;
 175                         mediatek,pull-down-adv = <0>; /* bias-disable */
 176                 };
 177         };
 178
 179         wf_2g_5g_pins: wf_2g_5g-pins {
 180                 mux {
 181                         function = "wifi";
 182                         groups = "wf_2g", "wf_5g";
 183                 };
 184                 conf {
 185                         pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
 186                                "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
 187                                "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
 188                                "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
 189                                "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
 190                                "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
 191                                "WF1_TOP_CLK", "WF1_TOP_DATA";
 192                         drive-strength = <4>;
 193                 };
 194         };
 195
 196         wf_dbdc_pins: wf-dbdc-pins {
 197                 mux {
 198                         function = "wifi";
 199                         groups = "wf_dbdc";
 200                 };
 201                 conf {
 202                         pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
 203                                 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
 204                                 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
 205                                 "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
 206                                 "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
 207                                 "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
 208                                 "WF1_TOP_CLK", "WF1_TOP_DATA";
 209                         drive-strength = <4>;
 210                 };
 211         };
 212 };
 213
 214 &pcie_phy {
 215         status = "okay";
 216 };
 217
 218 &spi0 {
 219         pinctrl-names = "default";
 220         pinctrl-0 = <&spi_flash_pins>;
 221         status = "okay";
 222
 223         spi_nand_flash: flash@0 {
 224                 compatible = "spi-nand";
 225                 reg = <0>;
 226                 #address-cells = <1>;
 227                 #size-cells = <1>;
 228
 229                 spi-max-frequency = <20000000>;
 230                 spi-tx-bus-width = <4>;
 231                 spi-rx-bus-width = <4>;
 232
 233                 /*
 234                  * ASUS bootloader tries to replace the partitions defined in
 235                  * Device Tree and by that also deletes all additional properties
 236                  * needed for UBI and NVMEM-on-UBI.
 237                  * Prevent this from happening by tricking the loader to delete and
 238                  * replace a bait node instead.
 239                  */
 240                 partitions: dummy {
 241                         compatible = "u-boot-dummy-partitions";
 242                         #address-cells = <1>;
 243                         #size-cells = <1>;
 244
 245                         partition@0 {
 246                                 reg = <0x0 0x0>;
 247                                 label = "remove_me";
 248                         };
 249                 };
 250
 251                 partitions {
 252                         compatible = "fixed-partitions";
 253                         #address-cells = <1>;
 254                         #size-cells = <1>;
 255
 256                         partition@0 {
 257                                 reg = <0x0 0x400000>;
 258                                 label = "bootloader";
 259                                 read-only;
 260                         };
 261
 262                         partition@400000 {
 263                                 compatible = "linux,ubi";
 264                                 reg = <0x400000 0xfc00000>;
 265                                 label = "UBI_DEV";
 266
 267                                 volumes {
 268                                         ubi_factory: ubi-volume-factory {
 269                                                 volname = "Factory";
 270                                         };
 271                                 };
 272                         };
 273                 };
 274         };
 275 };
 276
 277 &ubi_factory {
 278         nvmem-layout {
 279                 compatible = "fixed-layout";
 280                 #address-cells = <1>;
 281                 #size-cells = <1>;
 282
 283                 eeprom_factory_0: eeprom@0 {
 284                         reg = <0x0 0x1000>;
 285                 };
 286
 287                 macaddr_factory_4: macaddr@4 {
 288                         reg = <0x4 0x6>;
 289                 };
 290         };
 291 };
 292
 293 &switch {
 294         ports {
 295                 #address-cells = <1>;
 296                 #size-cells = <0>;
 297
 298                 port@1 {
 299                         reg = <4>;
 300                         label = "lan1";
 301                         phy-handle = <&swphy1>;
 302                 };
 303
 304                 port@2 {
 305                         reg = <3>;
 306                         label = "lan2";
 307                         phy-handle = <&swphy2>;
 308                 };
 309
 310                 port@3 {
 311                         reg = <2>;
 312                         label = "lan3";
 313                         phy-handle = <&swphy3>;
 314                 };
 315
 316                 port@4 {
 317                         reg = <1>;
 318                         label = "lan4";
 319                         phy-handle = <&swphy4>;
 320                 };
 321
 322                 port@5 {
 323                         reg = <5>;
 324                         label = "lan5";
 325                         phy-mode = "2500base-x";
 326                         phy-handle = <&phy5>;
 327
 328                 };
 329
 330                 port@6 {
 331                         reg = <6>;
 332                         label = "cpu";
 333                         ethernet = <&gmac0>;
 334                         phy-mode = "2500base-x";
 335
 336                         fixed-link {
 337                                 speed = <2500>;
 338                                 full-duplex;
 339                                 pause;
 340                         };
 341                 };
 342         };
 343
 344         mdio {
 345                 #address-cells = <1>;
 346                 #size-cells = <0>;
 347
 348                 swphy1: phy@1 {
 349                         reg = <1>;
 350
 351                         mediatek,led-config = <
 352                                 0x21 0x8009 /* BASIC_CTRL */
 353                                 0x22 0x0c00 /* ON_DURATION */
 354                                 0x23 0x1400 /* BLINK_DURATION */
 355                                 0x24 0x8000 /* LED0_ON_CTRL */
 356                                 0x25 0x0000 /* LED0_BLINK_CTRL */
 357                                 0x26 0xc007 /* LED1_ON_CTRL */
 358                                 0x27 0x003f /* LED1_BLINK_CTRL */
 359                         >;
 360                 };
 361
 362                 swphy2: phy@2 {
 363                         reg = <2>;
 364
 365                         mediatek,led-config = <
 366                                 0x21 0x8009 /* BASIC_CTRL */
 367                                 0x22 0x0c00 /* ON_DURATION */
 368                                 0x23 0x1400 /* BLINK_DURATION */
 369                                 0x24 0x8000 /* LED0_ON_CTRL */
 370                                 0x25 0x0000 /* LED0_BLINK_CTRL */
 371                                 0x26 0xc007 /* LED1_ON_CTRL */
 372                                 0x27 0x003f /* LED1_BLINK_CTRL */
 373                         >;
 374                 };
 375
 376                 swphy3: phy@3 {
 377                         reg = <3>;
 378
 379                         mediatek,led-config = <
 380                                 0x21 0x8009 /* BASIC_CTRL */
 381                                 0x22 0x0c00 /* ON_DURATION */
 382                                 0x23 0x1400 /* BLINK_DURATION */
 383                                 0x24 0x8000 /* LED0_ON_CTRL */
 384                                 0x25 0x0000 /* LED0_BLINK_CTRL */
 385                                 0x26 0xc007 /* LED1_ON_CTRL */
 386                                 0x27 0x003f /* LED1_BLINK_CTRL */
 387                         >;
 388                 };
 389
 390                 swphy4: phy@4 {
 391                         reg = <4>;
 392
 393                         mediatek,led-config = <
 394                                 0x21 0x8009 /* BASIC_CTRL */
 395                                 0x22 0x0c00 /* ON_DURATION */
 396                                 0x23 0x1400 /* BLINK_DURATION */
 397                                 0x24 0x8000 /* LED0_ON_CTRL */
 398                                 0x25 0x0000 /* LED0_BLINK_CTRL */
 399                                 0x26 0xc007 /* LED1_ON_CTRL */
 400                                 0x27 0x003f /* LED1_BLINK_CTRL */
 401                         >;
 402                 };
 403         };
 404 };
 405
 406 &watchdog {
 407         status = "okay";
 408 };
 409
 410 &wifi {
 411         nvmem-cells = <&eeprom_factory_0>;
 412         nvmem-cell-names = "eeprom";
 413         pinctrl-names = "default", "dbdc";
 414         pinctrl-0 = <&wf_2g_5g_pins>;
 415         pinctrl-1 = <&wf_dbdc_pins>;
 416         status = "okay";
 417 };
 418
 419 &trng {
 420         status = "okay";
 421 };
 422
 423 &uart0 {
 424         status = "okay";
 425 };
 426
 427 &ssusb {
 428         vusb33-supply = <&reg_3p3v>;
 429         vbus-supply = <&reg_5v>;
 430         status = "okay";
 431 };
 432
 433 &usb_phy {
 434         status = "okay";
 435 };