target/linux/mediatek/dts/mt7986a-asus-tuf-ax4200.dts

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2
   3 /dts-v1/;
   4 #include <dt-bindings/input/input.h>
   5 #include <dt-bindings/gpio/gpio.h>
   6 #include <dt-bindings/leds/common.h>
   7
   8 #include "mt7986a.dtsi"
   9
  10 / {
  11         model = "ASUS TUF-AX4200";
  12         compatible = "asus,tuf-ax4200", "mediatek,mt7986a";
  13
  14         aliases {
  15                 serial0 = &uart0;
  16                 label-mac-device = &gmac0;
  17                 led-boot = &led_system;
  18                 led-failsafe = &led_system;
  19                 led-running = &led_system;
  20                 led-upgrade = &led_system;
  21         };
  22
  23         chosen {
  24                 stdout-path = "serial0:115200n8";
  25                 bootargs-override = "";
  26         };
  27
  28         memory {
  29                 reg = <0 0x40000000 0 0x20000000>;
  30         };
  31
  32         keys {
  33                 compatible = "gpio-keys";
  34
  35                 reset {
  36                         label = "reset";
  37                         gpios = <&pio 9 GPIO_ACTIVE_LOW>;
  38                         linux,code = <KEY_RESTART>;
  39                 };
  40
  41                 mesh {
  42                         label = "wps";
  43                         gpios = <&pio 10 GPIO_ACTIVE_LOW>;
  44                         linux,code = <KEY_WPS_BUTTON>;
  45                 };
  46         };
  47
  48         leds {
  49                 compatible = "gpio-leds";
  50
  51                 wlan24 {
  52                         label = "white:wlan24";
  53                         gpios = <&pio 1 GPIO_ACTIVE_HIGH>;
  54                         linux,default-trigger = "phy0tpt";
  55                 };
  56
  57                 wlan5 {
  58                         label = "white:wlan5";
  59                         gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
  60                         linux,default-trigger = "phy1tpt";
  61                 };
  62
  63                 led_system: system {
  64                         label = "white:system";
  65                         gpios = <&pio 11 GPIO_ACTIVE_HIGH>;
  66                 };
  67
  68                 wan-red {
  69                         function = LED_FUNCTION_WAN;
  70                         color = <LED_COLOR_ID_RED>;
  71                         gpios = <&pio 12 GPIO_ACTIVE_LOW>;
  72                 };
  73         };
  74
  75         reg_3p3v: regulator-3p3v {
  76                 compatible = "regulator-fixed";
  77                 regulator-name = "fixed-3.3V";
  78                 regulator-min-microvolt = <3300000>;
  79                 regulator-max-microvolt = <3300000>;
  80                 regulator-boot-on;
  81                 regulator-always-on;
  82         };
  83
  84         reg_5v: regulator-5v {
  85                 compatible = "regulator-fixed";
  86                 regulator-name = "fixed-5V";
  87                 regulator-min-microvolt = <5000000>;
  88                 regulator-max-microvolt = <5000000>;
  89                 regulator-boot-on;
  90                 regulator-always-on;
  91         };
  92 };
  93
  94 &crypto {
  95         status = "okay";
  96 };
  97
  98 &eth {
  99         status = "okay";
 100
 101         gmac0: mac@0 {
 102                 /* LAN */
 103                 compatible = "mediatek,eth-mac";
 104                 reg = <0>;
 105                 nvmem-cells = <&macaddr_factory_4>;
 106                 nvmem-cell-names = "mac-address";
 107                 phy-mode = "2500base-x";
 108
 109                 fixed-link {
 110                         speed = <2500>;
 111                         full-duplex;
 112                         pause;
 113                 };
 114         };
 115
 116         gmac1: mac@1 {
 117                 /* WAN */
 118                 compatible = "mediatek,eth-mac";
 119                 reg = <1>;
 120                 phy-mode = "2500base-x";
 121                 phy-handle = <&phy6>;
 122         };
 123
 124         mdio: mdio-bus {
 125                 #address-cells = <1>;
 126                 #size-cells = <0>;
 127         };
 128 };
 129
 130 &mdio {
 131         phy6: phy@6 {
 132                 compatible = "ethernet-phy-ieee802.3-c45";
 133                 reg = <6>;
 134
 135                 reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>;
 136                 reset-assert-us = <10000>;
 137                 reset-deassert-us = <10000>;
 138
 139                 /* LED0: CONN (WAN white) */
 140                 mxl,led-config = <0x03f0 0x0 0x0 0x0>;
 141         };
 142
 143         switch: switch@1f {
 144                 compatible = "mediatek,mt7531";
 145                 reg = <31>;
 146
 147                 reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
 148                 reset-assert-us = <10000>;
 149                 reset-deassert-us = <10000>;
 150         };
 151 };
 152
 153 &pio {
 154         spi_flash_pins: spi-flash-pins-33-to-38 {
 155                 mux {
 156                         function = "spi";
 157                         groups = "spi0", "spi0_wp_hold";
 158                 };
 159                 conf-pu {
 160                         pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
 161                         drive-strength = <8>;
 162                         mediatek,pull-up-adv = <0>; /* bias-disable */
 163                 };
 164                 conf-pd {
 165                         pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
 166                         drive-strength = <8>;
 167                         mediatek,pull-down-adv = <0>; /* bias-disable */
 168                 };
 169         };
 170
 171         wf_2g_5g_pins: wf_2g_5g-pins {
 172                 mux {
 173                         function = "wifi";
 174                         groups = "wf_2g", "wf_5g";
 175                 };
 176                 conf {
 177                         pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
 178                                "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
 179                                "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
 180                                "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
 181                                "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
 182                                "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
 183                                "WF1_TOP_CLK", "WF1_TOP_DATA";
 184                         drive-strength = <4>;
 185                 };
 186         };
 187
 188         wf_dbdc_pins: wf-dbdc-pins {
 189                 mux {
 190                         function = "wifi";
 191                         groups = "wf_dbdc";
 192                 };
 193                 conf {
 194                         pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
 195                                 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
 196                                 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
 197                                 "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
 198                                 "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
 199                                 "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
 200                                 "WF1_TOP_CLK", "WF1_TOP_DATA";
 201                         drive-strength = <4>;
 202                 };
 203         };
 204 };
 205
 206 &spi0 {
 207         pinctrl-names = "default";
 208         pinctrl-0 = <&spi_flash_pins>;
 209         status = "okay";
 210
 211         spi_nand_flash: flash@0 {
 212                 compatible = "spi-nand";
 213                 #address-cells = <1>;
 214                 #size-cells = <1>;
 215                 reg = <0>;
 216
 217                 spi-max-frequency = <20000000>;
 218                 spi-tx-bus-width = <4>;
 219                 spi-rx-bus-width = <4>;
 220
 221                 /*
 222                  * ASUS bootloader tries to replace the partitions defined in
 223                  * Device Tree and by that also deletes all additional properties
 224                  * needed for UBI and NVMEM-on-UBI.
 225                  * Prevent this from happening by tricking the loader to delete and
 226                  * replace a bait node instead.
 227                  */
 228                 partitions: dummy {
 229                         compatible = "u-boot-dummy-partitions";
 230                         #address-cells = <1>;
 231                         #size-cells = <1>;
 232
 233                         partition@0 {
 234                                 reg = <0x0 0x0>;
 235                                 label = "remove_me";
 236                         };
 237                 };
 238
 239                 partitions {
 240                         compatible = "fixed-partitions";
 241                         #address-cells = <1>;
 242                         #size-cells = <1>;
 243
 244                         partition@0 {
 245                                 reg = <0x0 0x400000>;
 246                                 label = "bootloader";
 247                                 read-only;
 248                         };
 249
 250                         partition@400000 {
 251                                 compatible = "linux,ubi";
 252                                 reg = <0x400000 0xfc00000>;
 253                                 label = "UBI_DEV";
 254
 255                                 volumes {
 256                                         ubi_factory: ubi-volume-factory {
 257                                                 volname = "Factory";
 258                                         };
 259                                 };
 260                         };
 261                 };
 262         };
 263 };
 264
 265 &ubi_factory {
 266         nvmem-layout {
 267                 compatible = "fixed-layout";
 268                 #address-cells = <1>;
 269                 #size-cells = <1>;
 270
 271                 eeprom_factory_0: eeprom@0 {
 272                         reg = <0x0 0x1000>;
 273                 };
 274
 275                 macaddr_factory_4: macaddr@4 {
 276                         reg = <0x4 0x6>;
 277                 };
 278         };
 279 };
 280
 281 &switch {
 282         ports {
 283                 #address-cells = <1>;
 284                 #size-cells = <0>;
 285
 286                 port@1 {
 287                         reg = <1>;
 288                         label = "lan1";
 289                         phy-handle = <&swphy1>;
 290                 };
 291
 292                 port@2 {
 293                         reg = <2>;
 294                         label = "lan2";
 295                         phy-handle = <&swphy2>;
 296                 };
 297
 298                 port@3 {
 299                         reg = <3>;
 300                         label = "lan3";
 301                         phy-handle = <&swphy3>;
 302                 };
 303
 304                 port@4 {
 305                         reg = <4>;
 306                         label = "lan4";
 307                         phy-handle = <&swphy4>;
 308                 };
 309
 310                 port@6 {
 311                         reg = <6>;
 312                         label = "cpu";
 313                         ethernet = <&gmac0>;
 314                         phy-mode = "2500base-x";
 315
 316                         fixed-link {
 317                                 speed = <2500>;
 318                                 full-duplex;
 319                                 pause;
 320                         };
 321                 };
 322         };
 323
 324         mdio {
 325                 #address-cells = <1>;
 326                 #size-cells = <0>;
 327
 328                 swphy1: phy@1 {
 329                         reg = <1>;
 330
 331                         mediatek,led-config = <
 332                                 0x21 0x8009 /* BASIC_CTRL */
 333                                 0x22 0x0c00 /* ON_DURATION */
 334                                 0x23 0x1400 /* BLINK_DURATION */
 335                                 0x24 0x8000 /* LED0_ON_CTRL */
 336                                 0x25 0x0000 /* LED0_BLINK_CTRL */
 337                                 0x26 0xc007 /* LED1_ON_CTRL */
 338                                 0x27 0x003f /* LED1_BLINK_CTRL */
 339                         >;
 340                 };
 341
 342                 swphy2: phy@2 {
 343                         reg = <2>;
 344
 345                         mediatek,led-config = <
 346                                 0x21 0x8009 /* BASIC_CTRL */
 347                                 0x22 0x0c00 /* ON_DURATION */
 348                                 0x23 0x1400 /* BLINK_DURATION */
 349                                 0x24 0x8000 /* LED0_ON_CTRL */
 350                                 0x25 0x0000 /* LED0_BLINK_CTRL */
 351                                 0x26 0xc007 /* LED1_ON_CTRL */
 352                                 0x27 0x003f /* LED1_BLINK_CTRL */
 353                         >;
 354                 };
 355
 356                 swphy3: phy@3 {
 357                         reg = <3>;
 358
 359                         mediatek,led-config = <
 360                                 0x21 0x8009 /* BASIC_CTRL */
 361                                 0x22 0x0c00 /* ON_DURATION */
 362                                 0x23 0x1400 /* BLINK_DURATION */
 363                                 0x24 0x8000 /* LED0_ON_CTRL */
 364                                 0x25 0x0000 /* LED0_BLINK_CTRL */
 365                                 0x26 0xc007 /* LED1_ON_CTRL */
 366                                 0x27 0x003f /* LED1_BLINK_CTRL */
 367                         >;
 368                 };
 369
 370                 swphy4: phy@4 {
 371                         reg = <4>;
 372
 373                         mediatek,led-config = <
 374                                 0x21 0x8009 /* BASIC_CTRL */
 375                                 0x22 0x0c00 /* ON_DURATION */
 376                                 0x23 0x1400 /* BLINK_DURATION */
 377                                 0x24 0x8000 /* LED0_ON_CTRL */
 378                                 0x25 0x0000 /* LED0_BLINK_CTRL */
 379                                 0x26 0xc007 /* LED1_ON_CTRL */
 380                                 0x27 0x003f /* LED1_BLINK_CTRL */
 381                         >;
 382                 };
 383         };
 384 };
 385
 386 &watchdog {
 387         status = "okay";
 388 };
 389
 390 &wifi {
 391         nvmem-cells = <&eeprom_factory_0>;
 392         nvmem-cell-names = "eeprom";
 393         pinctrl-0 = <&wf_2g_5g_pins>;
 394         pinctrl-1 = <&wf_dbdc_pins>;
 395         pinctrl-names = "default", "dbdc";
 396         status = "okay";
 397 };
 398
 399 &trng {
 400         status = "okay";
 401 };
 402
 403 &uart0 {
 404         status = "okay";
 405 };
 406
 407 &ssusb {
 408         vusb33-supply = <&reg_3p3v>;
 409         vbus-supply = <&reg_5v>;
 410         status = "okay";
 411 };
 412
 413 &usb_phy {
 414         status = "okay";
 415 };