target/linux/generic/pending-6.1/796-net-dsa-mt7530-trap-link-local-frames-regardless-of-.patch

   1 From b7427d66cb3d6dca5165de5f7d80d59f08c2795b Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
   3 Date: Tue, 9 Apr 2024 18:01:14 +0300
   4 Subject: [PATCH 2/2] net: dsa: mt7530: trap link-local frames regardless of ST
   5  Port State
   6 MIME-Version: 1.0
   7 Content-Type: text/plain; charset=UTF-8
   8 Content-Transfer-Encoding: 8bit
   9
  10 In Clause 5 of IEEE Std 802-2014, two sublayers of the data link layer
  11 (DLL) of the Open Systems Interconnection basic reference model (OSI/RM)
  12 are described; the medium access control (MAC) and logical link control
  13 (LLC) sublayers. The MAC sublayer is the one facing the physical layer.
  14
  15 In 8.2 of IEEE Std 802.1Q-2022, the Bridge architecture is described. A
  16 Bridge component comprises a MAC Relay Entity for interconnecting the Ports
  17 of the Bridge, at least two Ports, and higher layer entities with at least
  18 a Spanning Tree Protocol Entity included.
  19
  20 Each Bridge Port also functions as an end station and shall provide the MAC
  21 Service to an LLC Entity. Each instance of the MAC Service is provided to a
  22 distinct LLC Entity that supports protocol identification, multiplexing,
  23 and demultiplexing, for protocol data unit (PDU) transmission and reception
  24 by one or more higher layer entities.
  25
  26 It is described in 8.13.9 of IEEE Std 802.1Q-2022 that in a Bridge, the LLC
  27 Entity associated with each Bridge Port is modeled as being directly
  28 connected to the attached Local Area Network (LAN).
  29
  30 On the switch with CPU port architecture, CPU port functions as Management
  31 Port, and the Management Port functionality is provided by software which
  32 functions as an end station. Software is connected to an IEEE 802 LAN that
  33 is wholly contained within the system that incorporates the Bridge.
  34 Software provides access to the LLC Entity associated with each Bridge Port
  35 by the value of the source port field on the special tag on the frame
  36 received by software.
  37
  38 We call frames that carry control information to determine the active
  39 topology and current extent of each Virtual Local Area Network (VLAN),
  40 i.e., spanning tree or Shortest Path Bridging (SPB) and Multiple VLAN
  41 Registration Protocol Data Units (MVRPDUs), and frames from other link
  42 constrained protocols, such as Extensible Authentication Protocol over LAN
  43 (EAPOL) and Link Layer Discovery Protocol (LLDP), link-local frames. They
  44 are not forwarded by a Bridge. Permanently configured entries in the
  45 filtering database (FDB) ensure that such frames are discarded by the
  46 Forwarding Process. In 8.6.3 of IEEE Std 802.1Q-2022, this is described in
  47 detail:
  48
  49 Each of the reserved MAC addresses specified in Table 8-1
  50 (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]) shall be
  51 permanently configured in the FDB in C-VLAN components and ERs.
  52
  53 Each of the reserved MAC addresses specified in Table 8-2
  54 (01-80-C2-00-00-[01,02,03,04,05,06,07,08,09,0A,0E]) shall be permanently
  55 configured in the FDB in S-VLAN components.
  56
  57 Each of the reserved MAC addresses specified in Table 8-3
  58 (01-80-C2-00-00-[01,02,04,0E]) shall be permanently configured in the FDB
  59 in TPMR components.
  60
  61 The FDB entries for reserved MAC addresses shall specify filtering for all
  62 Bridge Ports and all VIDs. Management shall not provide the capability to
  63 modify or remove entries for reserved MAC addresses.
  64
  65 The addresses in Table 8-1, Table 8-2, and Table 8-3 determine the scope of
  66 propagation of PDUs within a Bridged Network, as follows:
  67
  68   The Nearest Bridge group address (01-80-C2-00-00-0E) is an address that
  69   no conformant Two-Port MAC Relay (TPMR) component, Service VLAN (S-VLAN)
  70   component, Customer VLAN (C-VLAN) component, or MAC Bridge can forward.
  71   PDUs transmitted using this destination address, or any other addresses
  72   that appear in Table 8-1, Table 8-2, and Table 8-3
  73   (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]), can
  74   therefore travel no further than those stations that can be reached via a
  75   single individual LAN from the originating station.
  76
  77   The Nearest non-TPMR Bridge group address (01-80-C2-00-00-03), is an
  78   address that no conformant S-VLAN component, C-VLAN component, or MAC
  79   Bridge can forward; however, this address is relayed by a TPMR component.
  80   PDUs using this destination address, or any of the other addresses that
  81   appear in both Table 8-1 and Table 8-2 but not in Table 8-3
  82   (01-80-C2-00-00-[00,03,05,06,07,08,09,0A,0B,0C,0D,0F]), will be relayed
  83   by any TPMRs but will propagate no further than the nearest S-VLAN
  84   component, C-VLAN component, or MAC Bridge.
  85
  86   The Nearest Customer Bridge group address (01-80-C2-00-00-00) is an
  87   address that no conformant C-VLAN component, MAC Bridge can forward;
  88   however, it is relayed by TPMR components and S-VLAN components. PDUs
  89   using this destination address, or any of the other addresses that appear
  90   in Table 8-1 but not in either Table 8-2 or Table 8-3
  91   (01-80-C2-00-00-[00,0B,0C,0D,0F]), will be relayed by TPMR components and
  92   S-VLAN components but will propagate no further than the nearest C-VLAN
  93   component or MAC Bridge.
  94
  95 Because the LLC Entity associated with each Bridge Port is provided via CPU
  96 port, we must not filter these frames but forward them to CPU port.
  97
  98 In a Bridge, the transmission Port is majorly decided by ingress and egress
  99 rules, FDB, and spanning tree Port State functions of the Forwarding
 100 Process. For link-local frames, only CPU port should be designated as
 101 destination port in the FDB, and the other functions of the Forwarding
 102 Process must not interfere with the decision of the transmission Port. We
 103 call this process trapping frames to CPU port.
 104
 105 Therefore, on the switch with CPU port architecture, link-local frames must
 106 be trapped to CPU port, and certain link-local frames received by a Port of
 107 a Bridge comprising a TPMR component or an S-VLAN component must be
 108 excluded from it.
 109
 110 A Bridge of the switch with CPU port architecture cannot comprise a
 111 Two-Port MAC Relay (TPMR) component as a TPMR component supports only a
 112 subset of the functionality of a MAC Bridge. A Bridge comprising two Ports
 113 (Management Port doesn't count) of this architecture will either function
 114 as a standard MAC Bridge or a standard VLAN Bridge.
 115
 116 Therefore, a Bridge of this architecture can only comprise S-VLAN
 117 components, C-VLAN components, or MAC Bridge components. Since there's no
 118 TPMR component, we don't need to relay PDUs using the destination addresses
 119 specified on the Nearest non-TPMR section, and the proportion of the
 120 Nearest Customer Bridge section where they must be relayed by TPMR
 121 components.
 122
 123 One option to trap link-local frames to CPU port is to add static FDB
 124 entries with CPU port designated as destination port. However, because that
 125 Independent VLAN Learning (IVL) is being used on every VID, each entry only
 126 applies to a single VLAN Identifier (VID). For a Bridge comprising a MAC
 127 Bridge component or a C-VLAN component, there would have to be 16 times
 128 4096 entries. This switch intellectual property can only hold a maximum of
 129 2048 entries. Using this option, there also isn't a mechanism to prevent
 130 link-local frames from being discarded when the spanning tree Port State of
 131 the reception Port is discarding.
 132
 133 The remaining option is to utilise the BPC, RGAC1, RGAC2, RGAC3, and RGAC4
 134 registers. Whilst this applies to every VID, it doesn't contain all of the
 135 reserved MAC addresses without affecting the remaining Standard Group MAC
 136 Addresses. The REV_UN frame tag utilised using the RGAC4 register covers
 137 the remaining 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] destination
 138 addresses. It also includes the 01-80-C2-00-00-22 to 01-80-C2-00-00-FF
 139 destination addresses which may be relayed by MAC Bridges or VLAN Bridges.
 140 The latter option provides better but not complete conformance.
 141
 142 This switch intellectual property also does not provide a mechanism to trap
 143 link-local frames with specific destination addresses to CPU port by
 144 Bridge, to conform to the filtering rules for the distinct Bridge
 145 components.
 146
 147 Therefore, regardless of the type of the Bridge component, link-local
 148 frames with these destination addresses will be trapped to CPU port:
 149
 150 01-80-C2-00-00-[00,01,02,03,0E]
 151
 152 In a Bridge comprising a MAC Bridge component or a C-VLAN component:
 153
 154   Link-local frames with these destination addresses won't be trapped to
 155   CPU port which won't conform to IEEE Std 802.1Q-2022:
 156
 157   01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F]
 158
 159 In a Bridge comprising an S-VLAN component:
 160
 161   Link-local frames with these destination addresses will be trapped to CPU
 162   port which won't conform to IEEE Std 802.1Q-2022:
 163
 164   01-80-C2-00-00-00
 165
 166   Link-local frames with these destination addresses won't be trapped to
 167   CPU port which won't conform to IEEE Std 802.1Q-2022:
 168
 169   01-80-C2-00-00-[04,05,06,07,08,09,0A]
 170
 171 Currently on this switch intellectual property, if the spanning tree Port
 172 State of the reception Port is discarding, link-local frames will be
 173 discarded.
 174
 175 To trap link-local frames regardless of the spanning tree Port State, make
 176 the switch regard them as Bridge Protocol Data Units (BPDUs). This switch
 177 intellectual property only lets the frames regarded as BPDUs bypass the
 178 spanning tree Port State function of the Forwarding Process.
 179
 180 With this change, the only remaining interference is the ingress rules.
 181 When the reception Port has no PVID assigned on software, VLAN-untagged
 182 frames won't be allowed in. There doesn't seem to be a mechanism on the
 183 switch intellectual property to have link-local frames bypass this function
 184 of the Forwarding Process.
 185
 186 Fixes: b8f126a8d543 ("net-next: dsa: add dsa support for Mediatek MT7530 switch")
 187 Reviewed-by: Daniel Golle <daniel@makrotopia.org>
 188 Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
 189 ---
 190  drivers/net/dsa/mt7530.c | 229 +++++++++++++++++++++++++++++++++------
 191  drivers/net/dsa/mt7530.h |   5 +
 192  2 files changed, 200 insertions(+), 34 deletions(-)
 193
 194 --- a/drivers/net/dsa/mt7530.c
 195 +++ b/drivers/net/dsa/mt7530.c
 196 @@ -943,20 +943,173 @@ static void mt7530_setup_port5(struct ds
 197         mutex_unlock(&priv->reg_mutex);
 198  }
 199
 200 -/* On page 205, section "8.6.3 Frame filtering" of the active standard, IEEE Std
 201 - * 802.1Q™-2022, it is stated that frames with 01:80:C2:00:00:00-0F as MAC DA
 202 - * must only be propagated to C-VLAN and MAC Bridge components. That means
 203 - * VLAN-aware and VLAN-unaware bridges. On the switch designs with CPU ports,
 204 - * these frames are supposed to be processed by the CPU (software). So we make
 205 - * the switch only forward them to the CPU port. And if received from a CPU
 206 - * port, forward to a single port. The software is responsible of making the
 207 - * switch conform to the latter by setting a single port as destination port on
 208 - * the special tag.
 209 - *
 210 - * This switch intellectual property cannot conform to this part of the standard
 211 - * fully. Whilst the REV_UN frame tag covers the remaining :04-0D and :0F MAC
 212 - * DAs, it also includes :22-FF which the scope of propagation is not supposed
 213 - * to be restricted for these MAC DAs.
 214 +/* In Clause 5 of IEEE Std 802-2014, two sublayers of the data link layer (DLL)
 215 + * of the Open Systems Interconnection basic reference model (OSI/RM) are
 216 + * described; the medium access control (MAC) and logical link control (LLC)
 217 + * sublayers. The MAC sublayer is the one facing the physical layer.
 218 + *
 219 + * In 8.2 of IEEE Std 802.1Q-2022, the Bridge architecture is described. A
 220 + * Bridge component comprises a MAC Relay Entity for interconnecting the Ports
 221 + * of the Bridge, at least two Ports, and higher layer entities with at least a
 222 + * Spanning Tree Protocol Entity included.
 223 + *
 224 + * Each Bridge Port also functions as an end station and shall provide the MAC
 225 + * Service to an LLC Entity. Each instance of the MAC Service is provided to a
 226 + * distinct LLC Entity that supports protocol identification, multiplexing, and
 227 + * demultiplexing, for protocol data unit (PDU) transmission and reception by
 228 + * one or more higher layer entities.
 229 + *
 230 + * It is described in 8.13.9 of IEEE Std 802.1Q-2022 that in a Bridge, the LLC
 231 + * Entity associated with each Bridge Port is modeled as being directly
 232 + * connected to the attached Local Area Network (LAN).
 233 + *
 234 + * On the switch with CPU port architecture, CPU port functions as Management
 235 + * Port, and the Management Port functionality is provided by software which
 236 + * functions as an end station. Software is connected to an IEEE 802 LAN that is
 237 + * wholly contained within the system that incorporates the Bridge. Software
 238 + * provides access to the LLC Entity associated with each Bridge Port by the
 239 + * value of the source port field on the special tag on the frame received by
 240 + * software.
 241 + *
 242 + * We call frames that carry control information to determine the active
 243 + * topology and current extent of each Virtual Local Area Network (VLAN), i.e.,
 244 + * spanning tree or Shortest Path Bridging (SPB) and Multiple VLAN Registration
 245 + * Protocol Data Units (MVRPDUs), and frames from other link constrained
 246 + * protocols, such as Extensible Authentication Protocol over LAN (EAPOL) and
 247 + * Link Layer Discovery Protocol (LLDP), link-local frames. They are not
 248 + * forwarded by a Bridge. Permanently configured entries in the filtering
 249 + * database (FDB) ensure that such frames are discarded by the Forwarding
 250 + * Process. In 8.6.3 of IEEE Std 802.1Q-2022, this is described in detail:
 251 + *
 252 + * Each of the reserved MAC addresses specified in Table 8-1
 253 + * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]) shall be
 254 + * permanently configured in the FDB in C-VLAN components and ERs.
 255 + *
 256 + * Each of the reserved MAC addresses specified in Table 8-2
 257 + * (01-80-C2-00-00-[01,02,03,04,05,06,07,08,09,0A,0E]) shall be permanently
 258 + * configured in the FDB in S-VLAN components.
 259 + *
 260 + * Each of the reserved MAC addresses specified in Table 8-3
 261 + * (01-80-C2-00-00-[01,02,04,0E]) shall be permanently configured in the FDB in
 262 + * TPMR components.
 263 + *
 264 + * The FDB entries for reserved MAC addresses shall specify filtering for all
 265 + * Bridge Ports and all VIDs. Management shall not provide the capability to
 266 + * modify or remove entries for reserved MAC addresses.
 267 + *
 268 + * The addresses in Table 8-1, Table 8-2, and Table 8-3 determine the scope of
 269 + * propagation of PDUs within a Bridged Network, as follows:
 270 + *
 271 + *   The Nearest Bridge group address (01-80-C2-00-00-0E) is an address that no
 272 + *   conformant Two-Port MAC Relay (TPMR) component, Service VLAN (S-VLAN)
 273 + *   component, Customer VLAN (C-VLAN) component, or MAC Bridge can forward.
 274 + *   PDUs transmitted using this destination address, or any other addresses
 275 + *   that appear in Table 8-1, Table 8-2, and Table 8-3
 276 + *   (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]), can
 277 + *   therefore travel no further than those stations that can be reached via a
 278 + *   single individual LAN from the originating station.
 279 + *
 280 + *   The Nearest non-TPMR Bridge group address (01-80-C2-00-00-03), is an
 281 + *   address that no conformant S-VLAN component, C-VLAN component, or MAC
 282 + *   Bridge can forward; however, this address is relayed by a TPMR component.
 283 + *   PDUs using this destination address, or any of the other addresses that
 284 + *   appear in both Table 8-1 and Table 8-2 but not in Table 8-3
 285 + *   (01-80-C2-00-00-[00,03,05,06,07,08,09,0A,0B,0C,0D,0F]), will be relayed by
 286 + *   any TPMRs but will propagate no further than the nearest S-VLAN component,
 287 + *   C-VLAN component, or MAC Bridge.
 288 + *
 289 + *   The Nearest Customer Bridge group address (01-80-C2-00-00-00) is an address
 290 + *   that no conformant C-VLAN component, MAC Bridge can forward; however, it is
 291 + *   relayed by TPMR components and S-VLAN components. PDUs using this
 292 + *   destination address, or any of the other addresses that appear in Table 8-1
 293 + *   but not in either Table 8-2 or Table 8-3 (01-80-C2-00-00-[00,0B,0C,0D,0F]),
 294 + *   will be relayed by TPMR components and S-VLAN components but will propagate
 295 + *   no further than the nearest C-VLAN component or MAC Bridge.
 296 + *
 297 + * Because the LLC Entity associated with each Bridge Port is provided via CPU
 298 + * port, we must not filter these frames but forward them to CPU port.
 299 + *
 300 + * In a Bridge, the transmission Port is majorly decided by ingress and egress
 301 + * rules, FDB, and spanning tree Port State functions of the Forwarding Process.
 302 + * For link-local frames, only CPU port should be designated as destination port
 303 + * in the FDB, and the other functions of the Forwarding Process must not
 304 + * interfere with the decision of the transmission Port. We call this process
 305 + * trapping frames to CPU port.
 306 + *
 307 + * Therefore, on the switch with CPU port architecture, link-local frames must
 308 + * be trapped to CPU port, and certain link-local frames received by a Port of a
 309 + * Bridge comprising a TPMR component or an S-VLAN component must be excluded
 310 + * from it.
 311 + *
 312 + * A Bridge of the switch with CPU port architecture cannot comprise a Two-Port
 313 + * MAC Relay (TPMR) component as a TPMR component supports only a subset of the
 314 + * functionality of a MAC Bridge. A Bridge comprising two Ports (Management Port
 315 + * doesn't count) of this architecture will either function as a standard MAC
 316 + * Bridge or a standard VLAN Bridge.
 317 + *
 318 + * Therefore, a Bridge of this architecture can only comprise S-VLAN components,
 319 + * C-VLAN components, or MAC Bridge components. Since there's no TPMR component,
 320 + * we don't need to relay PDUs using the destination addresses specified on the
 321 + * Nearest non-TPMR section, and the proportion of the Nearest Customer Bridge
 322 + * section where they must be relayed by TPMR components.
 323 + *
 324 + * One option to trap link-local frames to CPU port is to add static FDB entries
 325 + * with CPU port designated as destination port. However, because that
 326 + * Independent VLAN Learning (IVL) is being used on every VID, each entry only
 327 + * applies to a single VLAN Identifier (VID). For a Bridge comprising a MAC
 328 + * Bridge component or a C-VLAN component, there would have to be 16 times 4096
 329 + * entries. This switch intellectual property can only hold a maximum of 2048
 330 + * entries. Using this option, there also isn't a mechanism to prevent
 331 + * link-local frames from being discarded when the spanning tree Port State of
 332 + * the reception Port is discarding.
 333 + *
 334 + * The remaining option is to utilise the BPC, RGAC1, RGAC2, RGAC3, and RGAC4
 335 + * registers. Whilst this applies to every VID, it doesn't contain all of the
 336 + * reserved MAC addresses without affecting the remaining Standard Group MAC
 337 + * Addresses. The REV_UN frame tag utilised using the RGAC4 register covers the
 338 + * remaining 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] destination
 339 + * addresses. It also includes the 01-80-C2-00-00-22 to 01-80-C2-00-00-FF
 340 + * destination addresses which may be relayed by MAC Bridges or VLAN Bridges.
 341 + * The latter option provides better but not complete conformance.
 342 + *
 343 + * This switch intellectual property also does not provide a mechanism to trap
 344 + * link-local frames with specific destination addresses to CPU port by Bridge,
 345 + * to conform to the filtering rules for the distinct Bridge components.
 346 + *
 347 + * Therefore, regardless of the type of the Bridge component, link-local frames
 348 + * with these destination addresses will be trapped to CPU port:
 349 + *
 350 + * 01-80-C2-00-00-[00,01,02,03,0E]
 351 + *
 352 + * In a Bridge comprising a MAC Bridge component or a C-VLAN component:
 353 + *
 354 + *   Link-local frames with these destination addresses won't be trapped to CPU
 355 + *   port which won't conform to IEEE Std 802.1Q-2022:
 356 + *
 357 + *   01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F]
 358 + *
 359 + * In a Bridge comprising an S-VLAN component:
 360 + *
 361 + *   Link-local frames with these destination addresses will be trapped to CPU
 362 + *   port which won't conform to IEEE Std 802.1Q-2022:
 363 + *
 364 + *   01-80-C2-00-00-00
 365 + *
 366 + *   Link-local frames with these destination addresses won't be trapped to CPU
 367 + *   port which won't conform to IEEE Std 802.1Q-2022:
 368 + *
 369 + *   01-80-C2-00-00-[04,05,06,07,08,09,0A]
 370 + *
 371 + * To trap link-local frames to CPU port as conformant as this switch
 372 + * intellectual property can allow, link-local frames are made to be regarded as
 373 + * Bridge Protocol Data Units (BPDUs). This is because this switch intellectual
 374 + * property only lets the frames regarded as BPDUs bypass the spanning tree Port
 375 + * State function of the Forwarding Process.
 376 + *
 377 + * The only remaining interference is the ingress rules. When the reception Port
 378 + * has no PVID assigned on software, VLAN-untagged frames won't be allowed in.
 379 + * There doesn't seem to be a mechanism on the switch intellectual property to
 380 + * have link-local frames bypass this function of the Forwarding Process.
 381   */
 382  static void
 383  mt753x_trap_frames(struct mt7530_priv *priv)
 384 @@ -964,35 +1117,43 @@ mt753x_trap_frames(struct mt7530_priv *p
 385         /* Trap 802.1X PAE frames and BPDUs to the CPU port(s) and egress them
 386          * VLAN-untagged.
 387          */
 388 -       mt7530_rmw(priv, MT753X_BPC, MT753X_PAE_EG_TAG_MASK |
 389 -                  MT753X_PAE_PORT_FW_MASK | MT753X_BPDU_EG_TAG_MASK |
 390 -                  MT753X_BPDU_PORT_FW_MASK,
 391 -                  MT753X_PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
 392 -                  MT753X_PAE_PORT_FW(MT753X_BPDU_CPU_ONLY) |
 393 -                  MT753X_BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
 394 -                  MT753X_BPDU_CPU_ONLY);
 395 +       mt7530_rmw(priv, MT753X_BPC,
 396 +                  MT753X_PAE_BPDU_FR | MT753X_PAE_EG_TAG_MASK |
 397 +                          MT753X_PAE_PORT_FW_MASK | MT753X_BPDU_EG_TAG_MASK |
 398 +                          MT753X_BPDU_PORT_FW_MASK,
 399 +                  MT753X_PAE_BPDU_FR |
 400 +                          MT753X_PAE_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
 401 +                          MT753X_PAE_PORT_FW(MT753X_BPDU_CPU_ONLY) |
 402 +                          MT753X_BPDU_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
 403 +                          MT753X_BPDU_CPU_ONLY);
 404
 405         /* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and egress
 406          * them VLAN-untagged.
 407          */
 408 -       mt7530_rmw(priv, MT753X_RGAC1, MT753X_R02_EG_TAG_MASK |
 409 -                  MT753X_R02_PORT_FW_MASK | MT753X_R01_EG_TAG_MASK |
 410 -                  MT753X_R01_PORT_FW_MASK,
 411 -                  MT753X_R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
 412 -                  MT753X_R02_PORT_FW(MT753X_BPDU_CPU_ONLY) |
 413 -                  MT753X_R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
 414 -                  MT753X_BPDU_CPU_ONLY);
 415 +       mt7530_rmw(priv, MT753X_RGAC1,
 416 +                  MT753X_R02_BPDU_FR | MT753X_R02_EG_TAG_MASK |
 417 +                          MT753X_R02_PORT_FW_MASK | MT753X_R01_BPDU_FR |
 418 +                          MT753X_R01_EG_TAG_MASK | MT753X_R01_PORT_FW_MASK,
 419 +                  MT753X_R02_BPDU_FR |
 420 +                          MT753X_R02_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
 421 +                          MT753X_R02_PORT_FW(MT753X_BPDU_CPU_ONLY) |
 422 +                          MT753X_R01_BPDU_FR |
 423 +                          MT753X_R01_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
 424 +                          MT753X_BPDU_CPU_ONLY);
 425
 426         /* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and egress
 427          * them VLAN-untagged.
 428          */
 429 -       mt7530_rmw(priv, MT753X_RGAC2, MT753X_R0E_EG_TAG_MASK |
 430 -                  MT753X_R0E_PORT_FW_MASK | MT753X_R03_EG_TAG_MASK |
 431 -                  MT753X_R03_PORT_FW_MASK,
 432 -                  MT753X_R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
 433 -                  MT753X_R0E_PORT_FW(MT753X_BPDU_CPU_ONLY) |
 434 -                  MT753X_R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
 435 -                  MT753X_BPDU_CPU_ONLY);
 436 +       mt7530_rmw(priv, MT753X_RGAC2,
 437 +                  MT753X_R0E_BPDU_FR | MT753X_R0E_EG_TAG_MASK |
 438 +                          MT753X_R0E_PORT_FW_MASK | MT753X_R03_BPDU_FR |
 439 +                          MT753X_R03_EG_TAG_MASK | MT753X_R03_PORT_FW_MASK,
 440 +                  MT753X_R0E_BPDU_FR |
 441 +                          MT753X_R0E_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
 442 +                          MT753X_R0E_PORT_FW(MT753X_BPDU_CPU_ONLY) |
 443 +                          MT753X_R03_BPDU_FR |
 444 +                          MT753X_R03_EG_TAG(MT7530_VLAN_EG_UNTAGGED) |
 445 +                          MT753X_BPDU_CPU_ONLY);
 446  }
 447
 448  static void
 449 --- a/drivers/net/dsa/mt7530.h
 450 +++ b/drivers/net/dsa/mt7530.h
 451 @@ -65,6 +65,7 @@ enum mt753x_id {
 452
 453  /* Registers for BPDU and PAE frame control*/
 454  #define MT753X_BPC                     0x24
 455 +#define  MT753X_PAE_BPDU_FR            BIT(25)
 456  #define  MT753X_PAE_EG_TAG_MASK                GENMASK(24, 22)
 457  #define  MT753X_PAE_EG_TAG(x)          FIELD_PREP(MT753X_PAE_EG_TAG_MASK, x)
 458  #define  MT753X_PAE_PORT_FW_MASK       GENMASK(18, 16)
 459 @@ -75,20 +76,24 @@ enum mt753x_id {
 460
 461  /* Register for :01 and :02 MAC DA frame control */
 462  #define MT753X_RGAC1                   0x28
 463 +#define  MT753X_R02_BPDU_FR            BIT(25)
 464  #define  MT753X_R02_EG_TAG_MASK                GENMASK(24, 22)
 465  #define  MT753X_R02_EG_TAG(x)          FIELD_PREP(MT753X_R02_EG_TAG_MASK, x)
 466  #define  MT753X_R02_PORT_FW_MASK       GENMASK(18, 16)
 467  #define  MT753X_R02_PORT_FW(x)         FIELD_PREP(MT753X_R02_PORT_FW_MASK, x)
 468 +#define  MT753X_R01_BPDU_FR            BIT(9)
 469  #define  MT753X_R01_EG_TAG_MASK                GENMASK(8, 6)
 470  #define  MT753X_R01_EG_TAG(x)          FIELD_PREP(MT753X_R01_EG_TAG_MASK, x)
 471  #define  MT753X_R01_PORT_FW_MASK       GENMASK(2, 0)
 472
 473  /* Register for :03 and :0E MAC DA frame control */
 474  #define MT753X_RGAC2                   0x2c
 475 +#define  MT753X_R0E_BPDU_FR            BIT(25)
 476  #define  MT753X_R0E_EG_TAG_MASK                GENMASK(24, 22)
 477  #define  MT753X_R0E_EG_TAG(x)          FIELD_PREP(MT753X_R0E_EG_TAG_MASK, x)
 478  #define  MT753X_R0E_PORT_FW_MASK       GENMASK(18, 16)
 479  #define  MT753X_R0E_PORT_FW(x)         FIELD_PREP(MT753X_R0E_PORT_FW_MASK, x)
 480 +#define  MT753X_R03_BPDU_FR            BIT(9)
 481  #define  MT753X_R03_EG_TAG_MASK                GENMASK(8, 6)
 482  #define  MT753X_R03_EG_TAG(x)          FIELD_PREP(MT753X_R03_EG_TAG_MASK, x)
 483  #define  MT753X_R03_PORT_FW_MASK       GENMASK(2, 0)