target/linux/ipq40xx/patches-5.4/102-ARM-dts-qcom-ipq4019-add-USB-devicetree-nodes.patch

   1 From 193856b5fe11c50a0b6ff22457dd674c1a45fec6 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <john@phrozen.org>
   3 Date: Wed, 9 Sep 2020 18:31:03 +0200
   4 Subject: [PATCH] ARM: dts: qcom: ipq4019: add USB devicetree nodes
   5
   6 Since we now have driver for the USB PHY, and USB controller is already supported by the DWC3 driver lets add the necessary nodes to DTSI.
   7
   8 Signed-off-by: John Crispin <john@phrozen.org>
   9 Signed-off-by: Robert Marko <robert.marko@sartura.hr>
  10 Cc: Luka Perkov <luka.perkov@sartura.hr>
  11 Reviewed-by: Vinod Koul <vkoul@kernel.org>
  12 ---
  13  arch/arm/boot/dts/qcom-ipq4019.dtsi | 74 +++++++++++++++++++++++++++++
  14  1 file changed, 74 insertions(+)
  15
  16 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
  17 +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
  18 @@ -615,5 +615,79 @@
  19                                 reg = <4>;
  20                         };
  21                 };
  22 +
  23 +               usb3_ss_phy: ssphy@9a000 {
  24 +                       compatible = "qcom,usb-ss-ipq4019-phy";
  25 +                       #phy-cells = <0>;
  26 +                       reg = <0x9a000 0x800>;
  27 +                       reg-names = "phy_base";
  28 +                       resets = <&gcc USB3_UNIPHY_PHY_ARES>;
  29 +                       reset-names = "por_rst";
  30 +                       status = "disabled";
  31 +               };
  32 +
  33 +               usb3_hs_phy: hsphy@a6000 {
  34 +                       compatible = "qcom,usb-hs-ipq4019-phy";
  35 +                       #phy-cells = <0>;
  36 +                       reg = <0xa6000 0x40>;
  37 +                       reg-names = "phy_base";
  38 +                       resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
  39 +                       reset-names = "por_rst", "srif_rst";
  40 +                       status = "disabled";
  41 +               };
  42 +
  43 +               usb3: usb3@8af8800 {
  44 +                       compatible = "qcom,dwc3";
  45 +                       reg = <0x8af8800 0x100>;
  46 +                       #address-cells = <1>;
  47 +                       #size-cells = <1>;
  48 +                       clocks = <&gcc GCC_USB3_MASTER_CLK>,
  49 +                                <&gcc GCC_USB3_SLEEP_CLK>,
  50 +                                <&gcc GCC_USB3_MOCK_UTMI_CLK>;
  51 +                       clock-names = "master", "sleep", "mock_utmi";
  52 +                       ranges;
  53 +                       status = "disabled";
  54 +
  55 +                       dwc3@8a00000 {
  56 +                               compatible = "snps,dwc3";
  57 +                               reg = <0x8a00000 0xf8000>;
  58 +                               interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
  59 +                               phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
  60 +                               phy-names = "usb2-phy", "usb3-phy";
  61 +                               dr_mode = "host";
  62 +                       };
  63 +               };
  64 +
  65 +               usb2_hs_phy: hsphy@a8000 {
  66 +                       compatible = "qcom,usb-hs-ipq4019-phy";
  67 +                       #phy-cells = <0>;
  68 +                       reg = <0xa8000 0x40>;
  69 +                       reg-names = "phy_base";
  70 +                       resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
  71 +                       reset-names = "por_rst", "srif_rst";
  72 +                       status = "disabled";
  73 +               };
  74 +
  75 +               usb2: usb2@60f8800 {
  76 +                       compatible = "qcom,dwc3";
  77 +                       reg = <0x60f8800 0x100>;
  78 +                       #address-cells = <1>;
  79 +                       #size-cells = <1>;
  80 +                       clocks = <&gcc GCC_USB2_MASTER_CLK>,
  81 +                                <&gcc GCC_USB2_SLEEP_CLK>,
  82 +                                <&gcc GCC_USB2_MOCK_UTMI_CLK>;
  83 +                       clock-names = "master", "sleep", "mock_utmi";
  84 +                       ranges;
  85 +                       status = "disabled";
  86 +
  87 +                       dwc3@6000000 {
  88 +                               compatible = "snps,dwc3";
  89 +                               reg = <0x6000000 0xf8000>;
  90 +                               interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
  91 +                               phys = <&usb2_hs_phy>;
  92 +                               phy-names = "usb2-phy";
  93 +                               dr_mode = "host";
  94 +                       };
  95 +               };
  96         };
  97  };