Drop all of the patches that have been already been included in kernel 6.1.
Signed-off-by: Robert Marko <robimarko@gmail.com>
+++ /dev/null
-From adf62d2727d4aa2b587e2db59eafb5be776a653c Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Sun, 5 Sep 2021 18:58:16 +0200
-Subject: [PATCH] arm64: dts: qcom: ipq8074: add SPMI bus
-
-IPQ8074 uses SPMI for communication with the PMIC, so
-since its already supported add the DT node for it.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20210905165816.655275-1-robimarko@gmail.com
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 19 +++++++++++++++++++
- 1 file changed, 19 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -320,6 +320,25 @@
- #reset-cells = <0x1>;
- };
-
-+ spmi_bus: spmi@200f000 {
-+ compatible = "qcom,spmi-pmic-arb";
-+ reg = <0x0200f000 0x001000>,
-+ <0x02400000 0x800000>,
-+ <0x02c00000 0x800000>,
-+ <0x03800000 0x200000>,
-+ <0x0200a000 0x000700>;
-+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
-+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-names = "periph_irq";
-+ qcom,ee = <0>;
-+ qcom,channel = <0>;
-+ #address-cells = <2>;
-+ #size-cells = <0>;
-+ interrupt-controller;
-+ #interrupt-cells = <4>;
-+ cell-index = <0>;
-+ };
-+
- sdhc_1: sdhci@7824900 {
- compatible = "qcom,sdhci-msm-v4";
- reg = <0x7824900 0x500>, <0x7824000 0x800>;
+++ /dev/null
-From 94343612f165fc8b4f95fcbe6fd044d6f63d4a28 Mon Sep 17 00:00:00 2001
-From: Shawn Guo <shawn.guo@linaro.org>
-Date: Tue, 31 Aug 2021 13:23:25 +0800
-Subject: [PATCH] arm64: dts: qcom: Update BAM DMA node name per DT schema
-
-Follow dma-controller.yaml schema to use `dma-controller` as node name
-of BAM DMA devices.
-
-Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20210831052325.21229-1-shawn.guo@linaro.org
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -239,7 +239,7 @@
- status = "disabled";
- };
-
-- cryptobam: dma@704000 {
-+ cryptobam: dma-controller@704000 {
- compatible = "qcom,bam-v1.7.0";
- reg = <0x00704000 0x20000>;
- interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
+++ /dev/null
-From ccc5b088058bccdf454bd296867c47e56c415cde Mon Sep 17 00:00:00 2001
-From: Chukun Pan <amadeus@jmu.edu.cn>
-Date: Fri, 1 Oct 2021 22:54:21 +0800
-Subject: [PATCH] arm64: dts: qcom: ipq8074: Add QUP5 I2C node
-
-Add node to support the QUP5 I2C controller inside of IPQ8074.
-It is exactly the same as QUP2 controllers.
-Some routers like ZTE MF269 use this bus.
-
-Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20211001145421.18302-1-amadeus@jmu.edu.cn
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 15 +++++++++++++++
- 1 file changed, 15 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -457,6 +457,21 @@
- status = "disabled";
- };
-
-+ blsp1_i2c5: i2c@78b9000 {
-+ compatible = "qcom,i2c-qup-v2.2.1";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0x78b9000 0x600>;
-+ interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
-+ <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
-+ clock-names = "iface", "core";
-+ clock-frequency = <400000>;
-+ dmas = <&blsp_dma 21>, <&blsp_dma 20>;
-+ dma-names = "rx", "tx";
-+ status = "disabled";
-+ };
-+
- blsp1_i2c6: i2c@78ba000 {
- compatible = "qcom,i2c-qup-v2.2.1";
- #address-cells = <1>;
+++ /dev/null
-From 1a82d7080001d395563ad8266d120d4cf63ad0a5 Mon Sep 17 00:00:00 2001
-From: Shawn Guo <shawn.guo@linaro.org>
-Date: Wed, 29 Sep 2021 11:42:46 +0800
-Subject: [PATCH] arm64: dts: qcom: msm8996: Move '#clock-cells' to QMP PHY
- child node
-
-'#clock-cells' is a required property of QMP PHY child node, not itself.
-Move it to fix the dtbs_check warnings.
-
-There are only '#clock-cells' removal from SM8350 QMP PHY nodes, because
-child nodes already have the property.
-
-Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20210929034253.24570-4-shawn.guo@linaro.org
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -91,7 +91,6 @@
- ssphy_1: phy@58000 {
- compatible = "qcom,ipq8074-qmp-usb3-phy";
- reg = <0x00058000 0x1c4>;
-- #clock-cells = <1>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-@@ -112,6 +111,7 @@
- <0x00058800 0x1f8>, /* PCS */
- <0x00058600 0x044>; /* PCS misc*/
- #phy-cells = <0>;
-+ #clock-cells = <1>;
- clocks = <&gcc GCC_USB1_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb3phy_1_cc_pipe_clk";
-@@ -134,7 +134,6 @@
- ssphy_0: phy@78000 {
- compatible = "qcom,ipq8074-qmp-usb3-phy";
- reg = <0x00078000 0x1c4>;
-- #clock-cells = <1>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-@@ -155,6 +154,7 @@
- <0x00078800 0x1f8>, /* PCS */
- <0x00078600 0x044>; /* PCS misc*/
- #phy-cells = <0>;
-+ #clock-cells = <1>;
- clocks = <&gcc GCC_USB0_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb3phy_0_cc_pipe_clk";
+++ /dev/null
-From 036e332e29ee24396ad877cc6a1275d86a1c4b3d Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Thu, 7 Oct 2021 13:58:46 +0200
-Subject: [PATCH] arm64: dts: qcom: ipq8074: add MDIO bus
-
-IPQ8074 uses an IPQ4019 compatible MDIO controller that is already
-supported in the kernel, so add the DT node in order to use it.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20211007115846.26255-1-robimarko@gmail.com
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 12 ++++++++++++
- 1 file changed, 12 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -231,6 +231,18 @@
- };
- };
-
-+ mdio: mdio@90000 {
-+ compatible = "qcom,ipq4019-mdio";
-+ reg = <0x00090000 0x64>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ clocks = <&gcc GCC_MDIO_AHB_CLK>;
-+ clock-names = "gcc_mdio_ahb_clk";
-+
-+ status = "disabled";
-+ };
-+
- prng: rng@e3000 {
- compatible = "qcom,prng-ee";
- reg = <0x000e3000 0x1000>;
+++ /dev/null
-From 29e135cf87900ac1da457bb27e98e30ca7f723ea Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Thu, 6 Jan 2022 22:25:12 +0100
-Subject: [PATCH] arm64: dts: qcom: ipq8074: add SMEM support
-
-IPQ8074 uses SMEM like other modern QCA SoC-s, so since its already
-supported by the kernel add the required DT nodes.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220106212512.1970828-1-robimarko@gmail.com
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 20 ++++++++++++++++++++
- 1 file changed, 20 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -76,6 +76,20 @@
- method = "smc";
- };
-
-+ reserved-memory {
-+ #address-cells = <2>;
-+ #size-cells = <2>;
-+ ranges;
-+
-+ smem@4ab00000 {
-+ compatible = "qcom,smem";
-+ reg = <0x0 0x4ab00000 0x0 0x00100000>;
-+ no-map;
-+
-+ hwlocks = <&tcsr_mutex 0>;
-+ };
-+ };
-+
- firmware {
- scm {
- compatible = "qcom,scm-ipq8074", "qcom,scm";
-@@ -332,6 +346,12 @@
- #reset-cells = <0x1>;
- };
-
-+ tcsr_mutex: hwlock@1905000 {
-+ compatible = "qcom,tcsr-mutex";
-+ reg = <0x01905000 0x20000>;
-+ #hwlock-cells = <1>;
-+ };
-+
- spmi_bus: spmi@200f000 {
- compatible = "qcom,spmi-pmic-arb";
- reg = <0x0200f000 0x001000>,
+++ /dev/null
-From 0f1cdeea7f237de21f244c06f2c102f93dbd9c4e Mon Sep 17 00:00:00 2001
-From: Kathiravan T <quic_kathirav@quicinc.com>
-Date: Fri, 7 Jan 2022 18:24:38 +0530
-Subject: [PATCH] arm64: dts: qcom: ipq8074: add the reserved-memory node
-
-On IPQ8074, 4MB of memory is needed for TZ. So mark that region
-as reserved.
-
-Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
-[bjorn: Squash with existing reserved-memory node]
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/1641560078-860-1-git-send-email-quic_kathirav@quicinc.com
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -88,6 +88,11 @@
-
- hwlocks = <&tcsr_mutex 0>;
- };
-+
-+ memory@4ac00000 {
-+ no-map;
-+ reg = <0x0 0x4ac00000 0x0 0x00400000>;
-+ };
- };
-
- firmware {
+++ /dev/null
-From a505f23abf0c31f40a2c3070d82e961b7c045664 Mon Sep 17 00:00:00 2001
-From: Kathiravan T <quic_kathirav@quicinc.com>
-Date: Tue, 8 Feb 2022 21:05:24 +0530
-Subject: [PATCH] arm64: dts: qcom: ipq8074: enable the GICv2m support
-
-GIC used in the IPQ8074 SoCs has one instance of the GICv2m extension,
-which supports upto 32 MSI interrupts. Lets add support for the same.
-
-Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/1644334525-11577-2-git-send-email-quic_kathirav@quicinc.com
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -635,9 +635,18 @@
-
- intc: interrupt-controller@b000000 {
- compatible = "qcom,msm-qgic2";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
- interrupt-controller;
- #interrupt-cells = <0x3>;
- reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
-+ ranges = <0 0xb00a000 0xffd>;
-+
-+ v2m@0 {
-+ compatible = "arm,gic-v2m-frame";
-+ msi-controller;
-+ reg = <0x0 0xffd>;
-+ };
- };
-
- timer {
+++ /dev/null
-From 2a73fa24be1d5a263062696f55dcc90725f9159c Mon Sep 17 00:00:00 2001
-From: Kathiravan T <quic_kathirav@quicinc.com>
-Date: Wed, 2 Feb 2022 22:05:08 +0530
-Subject: [PATCH] arm64: dts: qcom: ipq8074: drop the clock-frequency property
-
-Drop the clock-frequency property from the MMIO timer node, since it
-is already configured by the bootloader.
-
-Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/1643819709-5410-2-git-send-email-quic_kathirav@quicinc.com
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 1 -
- 1 file changed, 1 deletion(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -671,7 +671,6 @@
- ranges;
- compatible = "arm,armv7-timer-mem";
- reg = <0x0b120000 0x1000>;
-- clock-frequency = <19200000>;
-
- frame@b120000 {
- frame-number = <0>;
+++ /dev/null
-From 6f39b05b13e7be39919fd8d235bb0e63ecabf190 Mon Sep 17 00:00:00 2001
-From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Date: Tue, 5 Apr 2022 08:34:43 +0200
-Subject: [PATCH] arm64: dts: qcom: align dmas in I2C/SPI/UART with DT schema
-
-The DT schema expects dma channels in tx-rx order. No functional
-change.
-
-Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220405063451.12011-2-krzysztof.kozlowski@linaro.org
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 16 ++++++++--------
- 1 file changed, 8 insertions(+), 8 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -472,8 +472,8 @@
- <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
- clock-names = "iface", "core";
- clock-frequency = <400000>;
-- dmas = <&blsp_dma 15>, <&blsp_dma 14>;
-- dma-names = "rx", "tx";
-+ dmas = <&blsp_dma 14>, <&blsp_dma 15>;
-+ dma-names = "tx", "rx";
- pinctrl-0 = <&i2c_0_pins>;
- pinctrl-names = "default";
- status = "disabled";
-@@ -489,8 +489,8 @@
- <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
- clock-names = "iface", "core";
- clock-frequency = <100000>;
-- dmas = <&blsp_dma 17>, <&blsp_dma 16>;
-- dma-names = "rx", "tx";
-+ dmas = <&blsp_dma 16>, <&blsp_dma 17>;
-+ dma-names = "tx", "rx";
- status = "disabled";
- };
-
-@@ -504,8 +504,8 @@
- <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
- clock-names = "iface", "core";
- clock-frequency = <400000>;
-- dmas = <&blsp_dma 21>, <&blsp_dma 20>;
-- dma-names = "rx", "tx";
-+ dmas = <&blsp_dma 20>, <&blsp_dma 21>;
-+ dma-names = "tx", "rx";
- status = "disabled";
- };
-
-@@ -519,8 +519,8 @@
- <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
- clock-names = "iface", "core";
- clock-frequency = <100000>;
-- dmas = <&blsp_dma 23>, <&blsp_dma 22>;
-- dma-names = "rx", "tx";
-+ dmas = <&blsp_dma 22>, <&blsp_dma 23>;
-+ dma-names = "tx", "rx";
- status = "disabled";
- };
-
+++ /dev/null
-From 61d4a1751cfe5a22e5f18478fe16ffb1ee12607d Mon Sep 17 00:00:00 2001
-From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Date: Tue, 5 Apr 2022 08:34:44 +0200
-Subject: [PATCH] arm64: dts: qcom: align clocks in I2C/SPI with DT schema
-
-The DT schema expects clocks core-iface order. No functional change.
-
-Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220405063451.12011-3-krzysztof.kozlowski@linaro.org
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 24 ++++++++++++------------
- 1 file changed, 12 insertions(+), 12 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -468,9 +468,9 @@
- #size-cells = <0>;
- reg = <0x078b6000 0x600>;
- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
-- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
-- <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
-- clock-names = "iface", "core";
-+ clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
-+ <&gcc GCC_BLSP1_AHB_CLK>;
-+ clock-names = "core", "iface";
- clock-frequency = <400000>;
- dmas = <&blsp_dma 14>, <&blsp_dma 15>;
- dma-names = "tx", "rx";
-@@ -485,9 +485,9 @@
- #size-cells = <0>;
- reg = <0x078b7000 0x600>;
- interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
-- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
-- <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
-- clock-names = "iface", "core";
-+ clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
-+ <&gcc GCC_BLSP1_AHB_CLK>;
-+ clock-names = "core", "iface";
- clock-frequency = <100000>;
- dmas = <&blsp_dma 16>, <&blsp_dma 17>;
- dma-names = "tx", "rx";
-@@ -500,9 +500,9 @@
- #size-cells = <0>;
- reg = <0x78b9000 0x600>;
- interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
-- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
-- <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
-- clock-names = "iface", "core";
-+ clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
-+ <&gcc GCC_BLSP1_AHB_CLK>;
-+ clock-names = "core", "iface";
- clock-frequency = <400000>;
- dmas = <&blsp_dma 20>, <&blsp_dma 21>;
- dma-names = "tx", "rx";
-@@ -515,9 +515,9 @@
- #size-cells = <0>;
- reg = <0x078ba000 0x600>;
- interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
-- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
-- <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
-- clock-names = "iface", "core";
-+ clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
-+ <&gcc GCC_BLSP1_AHB_CLK>;
-+ clock-names = "core", "iface";
- clock-frequency = <100000>;
- dmas = <&blsp_dma 22>, <&blsp_dma 23>;
- dma-names = "tx", "rx";
+++ /dev/null
-From ee9002a825695b5dca76f758a9365ca7f7d18265 Mon Sep 17 00:00:00 2001
-From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Date: Wed, 4 May 2022 15:19:16 +0200
-Subject: [PATCH] arm64: dts: qcom: correct DWC3 node names and unit addresses
-
-Align DWC3 USB node names with DT schema ("usb" is expected) and correct
-the unit addresses to match the "reg" property. This also implies
-overriding nodes by label, instead of full path.
-
-Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Link: https://lore.kernel.org/r/20220504131923.214367-7-krzysztof.kozlowski@linaro.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -579,7 +579,7 @@
- resets = <&gcc GCC_USB0_BCR>;
- status = "disabled";
-
-- dwc_0: dwc3@8a00000 {
-+ dwc_0: usb@8a00000 {
- compatible = "snps,dwc3";
- reg = <0x8a00000 0xcd00>;
- interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
-@@ -619,7 +619,7 @@
- resets = <&gcc GCC_USB1_BCR>;
- status = "disabled";
-
-- dwc_1: dwc3@8c00000 {
-+ dwc_1: usb@8c00000 {
- compatible = "snps,dwc3";
- reg = <0x8c00000 0xcd00>;
- interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+++ /dev/null
-From 71061acf1a9343317e4d34a2c4578ed9301112cc Mon Sep 17 00:00:00 2001
-From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Date: Wed, 4 May 2022 15:19:17 +0200
-Subject: [PATCH] arm64: dts: qcom: ipq8074: add dedicated qcom,ipq8074-dwc3
- compatible
-
-Add dedicated compatible for DWC3 USB node name to allow more accurate
-DT schema matching.
-
-Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Link: https://lore.kernel.org/r/20220504131923.214367-8-krzysztof.kozlowski@linaro.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -554,7 +554,7 @@
- };
-
- usb_0: usb@8af8800 {
-- compatible = "qcom,dwc3";
-+ compatible = "qcom,ipq8074-dwc3", "qcom,dwc3";
- reg = <0x08af8800 0x400>;
- #address-cells = <1>;
- #size-cells = <1>;
-@@ -594,7 +594,7 @@
- };
-
- usb_1: usb@8cf8800 {
-- compatible = "qcom,dwc3";
-+ compatible = "qcom,ipq8074-dwc3", "qcom,dwc3";
- reg = <0x08cf8800 0x400>;
- #address-cells = <1>;
- #size-cells = <1>;
+++ /dev/null
-From 159cbe595c1018a0172c637374ec69af643fa9f5 Mon Sep 17 00:00:00 2001
-From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Date: Wed, 4 May 2022 15:19:22 +0200
-Subject: [PATCH] arm64: dts: qcom: align DWC3 USB clocks with DT schema
-
-Align order of clocks and their names with Qualcomm DWC3 USB DT schema.
-No functional impact expected.
-
-Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Link: https://lore.kernel.org/r/20220504131923.214367-13-krzysztof.kozlowski@linaro.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -564,8 +564,8 @@
- <&gcc GCC_USB0_MASTER_CLK>,
- <&gcc GCC_USB0_SLEEP_CLK>,
- <&gcc GCC_USB0_MOCK_UTMI_CLK>;
-- clock-names = "sys_noc_axi",
-- "master",
-+ clock-names = "cfg_noc",
-+ "core",
- "sleep",
- "mock_utmi";
-
-@@ -604,8 +604,8 @@
- <&gcc GCC_USB1_MASTER_CLK>,
- <&gcc GCC_USB1_SLEEP_CLK>,
- <&gcc GCC_USB1_MOCK_UTMI_CLK>;
-- clock-names = "sys_noc_axi",
-- "master",
-+ clock-names = "cfg_noc",
-+ "core",
- "sleep",
- "mock_utmi";
-
+++ /dev/null
-From a9f7dc27469ca9588d7aa572bdfdfd5f0f1aab6a Mon Sep 17 00:00:00 2001
-From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Date: Thu, 26 May 2022 22:42:47 +0200
-Subject: [PATCH] arm64: dts: qcom: adjust whitespace around '='
-
-Fix whitespace coding style: use single space instead of tabs or
-multiple spaces around '=' sign in property assignment. No functional
-changes (same DTB).
-
-Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220526204248.832139-1-krzysztof.kozlowski@linaro.org
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -119,7 +119,7 @@
- <&xo>;
- clock-names = "aux", "cfg_ahb", "ref";
-
-- resets = <&gcc GCC_USB1_PHY_BCR>,
-+ resets = <&gcc GCC_USB1_PHY_BCR>,
- <&gcc GCC_USB3PHY_1_PHY_BCR>;
- reset-names = "phy","common";
- status = "disabled";
-@@ -162,7 +162,7 @@
- <&xo>;
- clock-names = "aux", "cfg_ahb", "ref";
-
-- resets = <&gcc GCC_USB0_PHY_BCR>,
-+ resets = <&gcc GCC_USB0_PHY_BCR>,
- <&gcc GCC_USB3PHY_0_PHY_BCR>;
- reset-names = "phy","common";
- status = "disabled";
+++ /dev/null
-From 2e9703ffe97a1c447c0d00c061526fbeeade6107 Mon Sep 17 00:00:00 2001
-From: Bhupesh Sharma <bhupesh.sharma@linaro.org>
-Date: Sun, 15 May 2022 03:24:19 +0530
-Subject: [PATCH] arm64: dts: qcom: Fix sdhci node names - use 'mmc@'
-
-Since the Qualcomm sdhci-msm device-tree binding has been converted
-to yaml format, 'make dtbs_check' reports issues with
-inconsistent 'sdhci@' convention used for specifying the
-sdhci nodes. The generic mmc bindings expect 'mmc@' format
-instead.
-
-Fix the same.
-
-Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
-Cc: Rob Herring <robh@kernel.org>
-Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
-[bjorn: Moved non-arm64 changes to separate commit]
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220514215424.1007718-2-bhupesh.sharma@linaro.org
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -376,7 +376,7 @@
- cell-index = <0>;
- };
-
-- sdhc_1: sdhci@7824900 {
-+ sdhc_1: mmc@7824900 {
- compatible = "qcom,sdhci-msm-v4";
- reg = <0x7824900 0x500>, <0x7824000 0x800>;
- reg-names = "hc_mem", "core_mem";
+++ /dev/null
-From 18363f691e931abf0e9bdc9b5169fb15aa10224d Mon Sep 17 00:00:00 2001
-From: Bhupesh Sharma <bhupesh.sharma@linaro.org>
-Date: Sun, 15 May 2022 03:24:22 +0530
-Subject: [PATCH] arm64: dts: qcom: Fix ordering of 'clocks' & 'clock-names'
- for sdhci nodes
-
-Since the Qualcomm sdhci-msm device-tree binding has been converted
-to yaml format, 'make dtbs_check' reports a number of issues with
-ordering of 'clocks' & 'clock-names' for sdhci nodes:
-
- arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dtb: sdhci@7824900:
- clock-names:0: 'iface' was expected
-
- arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dtb: sdhci@7824900:
- clock-names:1: 'core' was expected
-
- arch/arm64/boot/dts/qcom/ipq8074-hk10-c2.dtb: sdhci@7824900:
- clock-names:2: 'xo' was expected
-
-Fix the same by updating the offending 'dts' files.
-
-Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
-Cc: Rob Herring <robh@kernel.org>
-Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220514215424.1007718-5-bhupesh.sharma@linaro.org
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -385,10 +385,10 @@
- <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hc_irq", "pwr_irq";
-
-- clocks = <&xo>,
-- <&gcc GCC_SDCC1_AHB_CLK>,
-- <&gcc GCC_SDCC1_APPS_CLK>;
-- clock-names = "xo", "iface", "core";
-+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
-+ <&gcc GCC_SDCC1_APPS_CLK>,
-+ <&xo>;
-+ clock-names = "iface", "core", "xo";
- max-frequency = <384000000>;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
+++ /dev/null
-From aa14b0c11f6442cd489d33c2855941055a3d4fa6 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Sun, 15 May 2022 23:00:41 +0200
-Subject: [PATCH] dt-bindings: clock: qcom: ipq8074: add PPE crypto clock
-
-Add binding for the PPE crypto clock in IPQ8074.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220515210048.483898-4-robimarko@gmail.com
----
- include/dt-bindings/clock/qcom,gcc-ipq8074.h | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h
-+++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
-@@ -233,6 +233,7 @@
- #define GCC_PCIE0_AXI_S_BRIDGE_CLK 224
- #define GCC_PCIE0_RCHNG_CLK_SRC 225
- #define GCC_PCIE0_RCHNG_CLK 226
-+#define GCC_CRYPTO_PPE_CLK 227
-
- #define GCC_BLSP1_BCR 0
- #define GCC_BLSP1_QUP1_BCR 1
+++ /dev/null
-From f91d0e8bd6c1f812bc2589050c05a90ee886c749 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Sun, 15 May 2022 23:00:42 +0200
-Subject: [PATCH] clk: qcom: ipq8074: add PPE crypto clock
-
-The built-in PPE engine has a dedicated clock for the EIP-197 crypto
-engine.
-
-So, since the required clock currently missing add support for it.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220515210048.483898-5-robimarko@gmail.com
----
- drivers/clk/qcom/gcc-ipq8074.c | 19 +++++++++++++++++++
- 1 file changed, 19 insertions(+)
-
---- a/drivers/clk/qcom/gcc-ipq8074.c
-+++ b/drivers/clk/qcom/gcc-ipq8074.c
-@@ -3183,6 +3183,24 @@ static struct clk_branch gcc_nss_ptp_ref
- },
- };
-
-+static struct clk_branch gcc_crypto_ppe_clk = {
-+ .halt_reg = 0x68310,
-+ .halt_bit = 31,
-+ .clkr = {
-+ .enable_reg = 0x68310,
-+ .enable_mask = BIT(0),
-+ .hw.init = &(struct clk_init_data){
-+ .name = "gcc_crypto_ppe_clk",
-+ .parent_names = (const char *[]){
-+ "nss_ppe_clk_src"
-+ },
-+ .num_parents = 1,
-+ .flags = CLK_SET_RATE_PARENT,
-+ .ops = &clk_branch2_ops,
-+ },
-+ },
-+};
-+
- static struct clk_branch gcc_nssnoc_ce_apb_clk = {
- .halt_reg = 0x6830c,
- .clkr = {
-@@ -4655,6 +4673,7 @@ static struct clk_regmap *gcc_ipq8074_cl
- [GCC_PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr,
- [GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,
- [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
-+ [GCC_CRYPTO_PPE_CLK] = &gcc_crypto_ppe_clk.clkr,
- };
-
- static const struct qcom_reset_map gcc_ipq8074_resets[] = {
+++ /dev/null
-From f5441c669d5442d247c69bab3eb27c074c0dd19a Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Sun, 15 May 2022 23:00:45 +0200
-Subject: [PATCH] dt-bindings: clock: qcom: ipq8074: add USB GDSCs
-
-Add bindings for the USB GDSCs found in IPQ8074 GCC.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220515210048.483898-8-robimarko@gmail.com
----
- include/dt-bindings/clock/qcom,gcc-ipq8074.h | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h
-+++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
-@@ -368,4 +368,7 @@
- #define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130
- #define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 131
-
-+#define USB0_GDSC 0
-+#define USB1_GDSC 1
-+
- #endif
+++ /dev/null
-From ff35d239b7b64f71d7dd9d0ce887647de2cacfcc Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Sun, 15 May 2022 23:00:46 +0200
-Subject: [PATCH] clk: qcom: ipq8074: add USB GDSCs
-
-Add GDSC-s for each of the two USB controllers built-in the IPQ8074.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220515210048.483898-9-robimarko@gmail.com
----
- drivers/clk/qcom/Kconfig | 1 +
- drivers/clk/qcom/gcc-ipq8074.c | 24 ++++++++++++++++++++++++
- 2 files changed, 25 insertions(+)
-
---- a/drivers/clk/qcom/Kconfig
-+++ b/drivers/clk/qcom/Kconfig
-@@ -166,6 +166,7 @@ config IPQ_LCC_806X
-
- config IPQ_GCC_8074
- tristate "IPQ8074 Global Clock Controller"
-+ select QCOM_GDSC
- help
- Support for global clock controller on ipq8074 devices.
- Say Y if you want to use peripheral devices such as UART, SPI,
---- a/drivers/clk/qcom/gcc-ipq8074.c
-+++ b/drivers/clk/qcom/gcc-ipq8074.c
-@@ -22,6 +22,7 @@
- #include "clk-alpha-pll.h"
- #include "clk-regmap-divider.h"
- #include "clk-regmap-mux.h"
-+#include "gdsc.h"
- #include "reset.h"
-
- enum {
-@@ -4408,6 +4409,22 @@ static struct clk_branch gcc_pcie0_axi_s
- },
- };
-
-+static struct gdsc usb0_gdsc = {
-+ .gdscr = 0x3e078,
-+ .pd = {
-+ .name = "usb0_gdsc",
-+ },
-+ .pwrsts = PWRSTS_OFF_ON,
-+};
-+
-+static struct gdsc usb1_gdsc = {
-+ .gdscr = 0x3f078,
-+ .pd = {
-+ .name = "usb1_gdsc",
-+ },
-+ .pwrsts = PWRSTS_OFF_ON,
-+};
-+
- static const struct alpha_pll_config ubi32_pll_config = {
- .l = 0x4e,
- .config_ctl_val = 0x200d4aa8,
-@@ -4811,6 +4828,11 @@ static const struct qcom_reset_map gcc_i
- [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
- };
-
-+static struct gdsc *gcc_ipq8074_gdscs[] = {
-+ [USB0_GDSC] = &usb0_gdsc,
-+ [USB1_GDSC] = &usb1_gdsc,
-+};
-+
- static const struct of_device_id gcc_ipq8074_match_table[] = {
- { .compatible = "qcom,gcc-ipq8074" },
- { }
-@@ -4833,6 +4855,8 @@ static const struct qcom_cc_desc gcc_ipq
- .num_resets = ARRAY_SIZE(gcc_ipq8074_resets),
- .clk_hws = gcc_ipq8074_hws,
- .num_clk_hws = ARRAY_SIZE(gcc_ipq8074_hws),
-+ .gdscs = gcc_ipq8074_gdscs,
-+ .num_gdscs = ARRAY_SIZE(gcc_ipq8074_gdscs),
- };
-
- static int gcc_ipq8074_probe(struct platform_device *pdev)
+++ /dev/null
-From 53211e85006ebb9bf7fb4482288639612f3146e7 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Sun, 15 May 2022 23:00:48 +0200
-Subject: [PATCH] arm64: dts: qcom: ipq8074: add USB power domains
-
-Add USB power domains provided by GCC GDSCs.
-Add the required #power-domain-cells to the GCC as well.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220515210048.483898-11-robimarko@gmail.com
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -348,6 +348,7 @@
- compatible = "qcom,gcc-ipq8074";
- reg = <0x01800000 0x80000>;
- #clock-cells = <0x1>;
-+ #power-domain-cells = <1>;
- #reset-cells = <0x1>;
- };
-
-@@ -576,6 +577,8 @@
- <133330000>,
- <19200000>;
-
-+ power-domains = <&gcc USB0_GDSC>;
-+
- resets = <&gcc GCC_USB0_BCR>;
- status = "disabled";
-
-@@ -616,6 +619,8 @@
- <133330000>,
- <19200000>;
-
-+ power-domains = <&gcc USB1_GDSC>;
-+
- resets = <&gcc GCC_USB1_BCR>;
- status = "disabled";
-
+++ /dev/null
-From 85a9cab9b9bb471eae016cdbfabd928585c23cce Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Mon, 4 Jul 2022 13:33:18 +0200
-Subject: [PATCH] arm64: dts: qcom: ipq8074: move ARMv8 timer out of SoC node
-
-The ARM timer is usually considered not part of SoC node, just like
-other ARM designed blocks (PMU, PSCI). This fixes dtbs_check warning:
-
-arch/arm64/boot/dts/qcom/ipq8072-ax9000.dtb: soc: timer: {'compatible': ['arm,armv8-timer'], 'interrupts': [[1, 2, 3848], [1, 3, 3848], [1, 4, 3848], [1, 1, 3848]]} should not be valid under {'type': 'object'}
- From schema: dtschema/schemas/simple-bus.yaml
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-[bjorn: Moved node after "soc" for alphabetical ordering]
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220704113318.623102-1-robimarko@gmail.com
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 16 ++++++++--------
- 1 file changed, 8 insertions(+), 8 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -654,14 +654,6 @@
- };
- };
-
-- timer {
-- compatible = "arm,armv8-timer";
-- interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-- <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-- <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-- <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
-- };
--
- watchdog: watchdog@b017000 {
- compatible = "qcom,kpss-wdt";
- reg = <0xb017000 0x1000>;
-@@ -853,4 +845,12 @@
- status = "disabled";
- };
- };
-+
-+ timer {
-+ compatible = "arm,armv8-timer";
-+ interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-+ <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-+ <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
-+ };
- };
+++ /dev/null
-From 8e6af077ced3931ac18e37f0eb3fc6f1a20b0e4a Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Mon, 4 Jul 2022 16:35:54 +0200
-Subject: [PATCH] arm64: dts: qcom: ipq8074: add reset to SDHCI
-
-Add reset to SDHCI controller so it can be reset to avoid timeout issues
-after software reset due to bootloader set configuration.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
-Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220704143554.1180927-2-robimarko@gmail.com
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -390,6 +390,7 @@
- <&gcc GCC_SDCC1_APPS_CLK>,
- <&xo>;
- clock-names = "iface", "core", "xo";
-+ resets = <&gcc GCC_SDCC1_BCR>;
- max-frequency = <384000000>;
- mmc-ddr-1_8v;
- mmc-hs200-1_8v;
+++ /dev/null
-From 0171978734227bdd7813bc6d805f609126e3849e Mon Sep 17 00:00:00 2001
-From: Johan Hovold <johan+linaro@kernel.org>
-Date: Tue, 5 Jul 2022 13:40:22 +0200
-Subject: [PATCH] arm64: dts: qcom: ipq8074: drop USB PHY clock index
-
-The QMP USB PHY provides a single clock so drop the redundant clock
-index.
-
-Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
-Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220705114032.22787-5-johan+linaro@kernel.org
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -130,7 +130,7 @@
- <0x00058800 0x1f8>, /* PCS */
- <0x00058600 0x044>; /* PCS misc*/
- #phy-cells = <0>;
-- #clock-cells = <1>;
-+ #clock-cells = <0>;
- clocks = <&gcc GCC_USB1_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb3phy_1_cc_pipe_clk";
-@@ -173,7 +173,7 @@
- <0x00078800 0x1f8>, /* PCS */
- <0x00078600 0x044>; /* PCS misc*/
- #phy-cells = <0>;
-- #clock-cells = <1>;
-+ #clock-cells = <0>;
- clocks = <&gcc GCC_USB0_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb3phy_0_cc_pipe_clk";
+++ /dev/null
-From a6e1d17fbfd41113bf47345e65953873e717ca63 Mon Sep 17 00:00:00 2001
-From: Shawn Guo <shawn.guo@linaro.org>
-Date: Tue, 14 Sep 2021 09:40:48 +0800
-Subject: [PATCH] mailbox: qcom-apcs-ipc: Consolidate msm8994 type apcs_data
-
-The msm8994 type of apcs_data is defined multiple times with different
-SoC name encoded. Consolidate them on msm8994 and remove the data
-duplication.
-
-Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
-Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
----
- drivers/mailbox/qcom-apcs-ipc-mailbox.c | 26 +++++--------------------
- 1 file changed, 5 insertions(+), 21 deletions(-)
-
---- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
-+++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
-@@ -33,10 +33,6 @@ static const struct qcom_apcs_ipc_data i
- .offset = 8, .clk_name = "qcom,apss-ipq6018-clk"
- };
-
--static const struct qcom_apcs_ipc_data ipq8074_apcs_data = {
-- .offset = 8, .clk_name = NULL
--};
--
- static const struct qcom_apcs_ipc_data msm8916_apcs_data = {
- .offset = 8, .clk_name = "qcom-apcs-msm8916-clk"
- };
-@@ -49,18 +45,6 @@ static const struct qcom_apcs_ipc_data m
- .offset = 16, .clk_name = NULL
- };
-
--static const struct qcom_apcs_ipc_data msm8998_apcs_data = {
-- .offset = 8, .clk_name = NULL
--};
--
--static const struct qcom_apcs_ipc_data sdm660_apcs_data = {
-- .offset = 8, .clk_name = NULL
--};
--
--static const struct qcom_apcs_ipc_data sm6125_apcs_data = {
-- .offset = 8, .clk_name = NULL
--};
--
- static const struct qcom_apcs_ipc_data apps_shared_apcs_data = {
- .offset = 12, .clk_name = NULL
- };
-@@ -160,21 +144,21 @@ static int qcom_apcs_ipc_remove(struct p
- /* .data is the offset of the ipc register within the global block */
- static const struct of_device_id qcom_apcs_ipc_of_match[] = {
- { .compatible = "qcom,ipq6018-apcs-apps-global", .data = &ipq6018_apcs_data },
-- { .compatible = "qcom,ipq8074-apcs-apps-global", .data = &ipq8074_apcs_data },
-+ { .compatible = "qcom,ipq8074-apcs-apps-global", .data = &msm8994_apcs_data },
- { .compatible = "qcom,msm8916-apcs-kpss-global", .data = &msm8916_apcs_data },
- { .compatible = "qcom,msm8939-apcs-kpss-global", .data = &msm8916_apcs_data },
- { .compatible = "qcom,msm8953-apcs-kpss-global", .data = &msm8994_apcs_data },
- { .compatible = "qcom,msm8994-apcs-kpss-global", .data = &msm8994_apcs_data },
- { .compatible = "qcom,msm8996-apcs-hmss-global", .data = &msm8996_apcs_data },
-- { .compatible = "qcom,msm8998-apcs-hmss-global", .data = &msm8998_apcs_data },
-+ { .compatible = "qcom,msm8998-apcs-hmss-global", .data = &msm8994_apcs_data },
- { .compatible = "qcom,qcs404-apcs-apps-global", .data = &msm8916_apcs_data },
- { .compatible = "qcom,sc7180-apss-shared", .data = &apps_shared_apcs_data },
- { .compatible = "qcom,sc8180x-apss-shared", .data = &apps_shared_apcs_data },
-- { .compatible = "qcom,sdm660-apcs-hmss-global", .data = &sdm660_apcs_data },
-+ { .compatible = "qcom,sdm660-apcs-hmss-global", .data = &msm8994_apcs_data },
- { .compatible = "qcom,sdm845-apss-shared", .data = &apps_shared_apcs_data },
-- { .compatible = "qcom,sm6125-apcs-hmss-global", .data = &sm6125_apcs_data },
-+ { .compatible = "qcom,sm6125-apcs-hmss-global", .data = &msm8994_apcs_data },
- { .compatible = "qcom,sm8150-apss-shared", .data = &apps_shared_apcs_data },
-- { .compatible = "qcom,sm6115-apcs-hmss-global", .data = &sdm660_apcs_data },
-+ { .compatible = "qcom,sm6115-apcs-hmss-global", .data = &msm8994_apcs_data },
- { .compatible = "qcom,sdx55-apcs-gcc", .data = &sdx55_apcs_data },
- {}
- };
+++ /dev/null
-From 28e239ecd69a99748181bfdf5d2238ff1a8d0646 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Fri, 19 Aug 2022 00:08:48 +0200
-Subject: [PATCH] mailbox: qcom-apcs-ipc: add IPQ8074 APSS clock support
-
-IPQ8074 has the APSS clock controller utilizing the same register space as
-the APCS, so provide access to the APSS utilizing a child device like
-IPQ6018.
-
-IPQ6018 and IPQ8074 use the same controller and driver, so just utilize
-IPQ6018 match data for IPQ8074.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
----
- drivers/mailbox/qcom-apcs-ipc-mailbox.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
-+++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
-@@ -144,7 +144,7 @@ static int qcom_apcs_ipc_remove(struct p
- /* .data is the offset of the ipc register within the global block */
- static const struct of_device_id qcom_apcs_ipc_of_match[] = {
- { .compatible = "qcom,ipq6018-apcs-apps-global", .data = &ipq6018_apcs_data },
-- { .compatible = "qcom,ipq8074-apcs-apps-global", .data = &msm8994_apcs_data },
-+ { .compatible = "qcom,ipq8074-apcs-apps-global", .data = &ipq6018_apcs_data },
- { .compatible = "qcom,msm8916-apcs-kpss-global", .data = &msm8916_apcs_data },
- { .compatible = "qcom,msm8939-apcs-kpss-global", .data = &msm8916_apcs_data },
- { .compatible = "qcom,msm8953-apcs-kpss-global", .data = &msm8994_apcs_data },
+++ /dev/null
-From aea90e172420a062197849d7914b2fa032de0228 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Thu, 7 Jul 2022 19:37:33 +0200
-Subject: [PATCH] arm64: dts: qcom: ipq8074: add APCS node
-
-APCS now has support for providing the APSS clocks as the child device
-for IPQ8074.
-
-So, add the required DT node for it as it will later be used as the CPU
-clocksource.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-[bjorn: Sorted node based on address]
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220707173733.404947-4-robimarko@gmail.com
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -663,6 +663,14 @@
- timeout-sec = <30>;
- };
-
-+ apcs_glb: mailbox@b111000 {
-+ compatible = "qcom,ipq8074-apcs-apps-global";
-+ reg = <0x0b111000 0x6000>;
-+
-+ #clock-cells = <1>;
-+ #mbox-cells = <1>;
-+ };
-+
- timer@b120000 {
- #address-cells = <1>;
- #size-cells = <1>;
+++ /dev/null
-From a3f36600fd758173c1ec315684e4ae72c6e85654 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Fri, 8 Jul 2022 15:38:45 +0200
-Subject: [PATCH] arm64: dts: qcom: ipq8074: add #size/address-cells to DTSI
-
-Add #size-cells and #address-cells to the SoC DTSI to avoid duplicating
-the same properties in board DTS files.
-
-Remove the mentioned properties from current board DTS files.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220708133846.599735-1-robimarko@gmail.com
----
- arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 2 --
- arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi | 3 ---
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 3 +++
- 3 files changed, 3 insertions(+), 5 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
-+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
-@@ -5,8 +5,6 @@
- #include "ipq8074.dtsi"
-
- / {
-- #address-cells = <0x2>;
-- #size-cells = <0x2>;
- model = "Qualcomm Technologies, Inc. IPQ8074-HK01";
- compatible = "qcom,ipq8074-hk01", "qcom,ipq8074";
- interrupt-parent = <&intc>;
---- a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
-@@ -7,9 +7,6 @@
- #include "ipq8074.dtsi"
-
- / {
-- #address-cells = <0x2>;
-- #size-cells = <0x2>;
--
- interrupt-parent = <&intc>;
-
- aliases {
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -7,6 +7,9 @@
- #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
-
- / {
-+ #address-cells = <2>;
-+ #size-cells = <2>;
-+
- model = "Qualcomm Technologies, Inc. IPQ8074";
- compatible = "qcom,ipq8074";
-
+++ /dev/null
-From 7d57ca4d56856b7f7b97adda6e97cf5db4dcce93 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Fri, 8 Jul 2022 15:38:46 +0200
-Subject: [PATCH] arm64: dts: qcom: ipq8074: add interrupt-parent to DTSI
-
-Add interrupt-parent to the SoC DTSI to avoid duplicating it in each board
-DTS file.
-
-Remove interrupt-parent from existing board DTS files.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20220708133846.599735-2-robimarko@gmail.com
----
- arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 1 -
- arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi | 2 --
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 1 +
- 3 files changed, 1 insertion(+), 3 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
-+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
-@@ -7,7 +7,6 @@
- / {
- model = "Qualcomm Technologies, Inc. IPQ8074-HK01";
- compatible = "qcom,ipq8074-hk01", "qcom,ipq8074";
-- interrupt-parent = <&intc>;
-
- aliases {
- serial0 = &blsp1_uart5;
---- a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
-@@ -7,8 +7,6 @@
- #include "ipq8074.dtsi"
-
- / {
-- interrupt-parent = <&intc>;
--
- aliases {
- serial0 = &blsp1_uart5;
- };
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -12,6 +12,7 @@
-
- model = "Qualcomm Technologies, Inc. IPQ8074";
- compatible = "qcom,ipq8074";
-+ interrupt-parent = <&intc>;
-
- clocks {
- sleep_clk: sleep_clk {
+++ /dev/null
-From a19df563230af392f2e84e57d69367f96b4a8c56 Mon Sep 17 00:00:00 2001
-From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Date: Tue, 12 Jul 2022 16:42:43 +0200
-Subject: [PATCH] arm64: dts: qcom: align SDHCI reg-names with DT schema
-
-DT schema requires SDHCI reg names to be hc/core without "_mem" suffix,
-just like TXT bindings were expecting before the conversion.
-
-Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Reviewed-by: Douglas Anderson <dianders@chromium.org>
-Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20220712144245.17417-4-krzysztof.kozlowski@linaro.org
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -384,7 +384,7 @@
- sdhc_1: mmc@7824900 {
- compatible = "qcom,sdhci-msm-v4";
- reg = <0x7824900 0x500>, <0x7824000 0x800>;
-- reg-names = "hc_mem", "core_mem";
-+ reg-names = "hc", "core";
-
- interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+++ /dev/null
-From 7bd608426c407a79debea54b2b243950f330c5b8 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Fri, 19 Aug 2022 00:06:24 +0200
-Subject: [PATCH] clk: qcom: apss-ipq-pll: use OF match data for Alpha PLL
- config
-
-Convert the driver to use OF match data for providing the Alpha PLL config
-per compatible.
-This is required for IPQ8074 support since it uses a different Alpha PLL
-config.
-
-While we are here rename "ipq_pll_config" to "ipq6018_pll_config" to make
-it clear that it is for IPQ6018 only.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20220818220628.339366-5-robimarko@gmail.com
----
- drivers/clk/qcom/apss-ipq-pll.c | 12 +++++++++---
- 1 file changed, 9 insertions(+), 3 deletions(-)
-
---- a/drivers/clk/qcom/apss-ipq-pll.c
-+++ b/drivers/clk/qcom/apss-ipq-pll.c
-@@ -2,6 +2,7 @@
- // Copyright (c) 2018, The Linux Foundation. All rights reserved.
- #include <linux/clk-provider.h>
- #include <linux/module.h>
-+#include <linux/of_device.h>
- #include <linux/platform_device.h>
- #include <linux/regmap.h>
-
-@@ -36,7 +37,7 @@ static struct clk_alpha_pll ipq_pll = {
- },
- };
-
--static const struct alpha_pll_config ipq_pll_config = {
-+static const struct alpha_pll_config ipq6018_pll_config = {
- .l = 0x37,
- .config_ctl_val = 0x04141200,
- .config_ctl_hi_val = 0x0,
-@@ -54,6 +55,7 @@ static const struct regmap_config ipq_pl
-
- static int apss_ipq_pll_probe(struct platform_device *pdev)
- {
-+ const struct alpha_pll_config *ipq_pll_config;
- struct device *dev = &pdev->dev;
- struct regmap *regmap;
- void __iomem *base;
-@@ -67,7 +69,11 @@ static int apss_ipq_pll_probe(struct pla
- if (IS_ERR(regmap))
- return PTR_ERR(regmap);
-
-- clk_alpha_pll_configure(&ipq_pll, regmap, &ipq_pll_config);
-+ ipq_pll_config = of_device_get_match_data(&pdev->dev);
-+ if (!ipq_pll_config)
-+ return -ENODEV;
-+
-+ clk_alpha_pll_configure(&ipq_pll, regmap, ipq_pll_config);
-
- ret = devm_clk_register_regmap(dev, &ipq_pll.clkr);
- if (ret)
-@@ -78,7 +84,7 @@ static int apss_ipq_pll_probe(struct pla
- }
-
- static const struct of_device_id apss_ipq_pll_match_table[] = {
-- { .compatible = "qcom,ipq6018-a53pll" },
-+ { .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_config },
- { }
- };
- MODULE_DEVICE_TABLE(of, apss_ipq_pll_match_table);
+++ /dev/null
-From d22c8f1bd94602d1bf2b377c3befe54e749b963d Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Fri, 19 Aug 2022 00:06:25 +0200
-Subject: [PATCH] clk: qcom: apss-ipq-pll: update IPQ6018 Alpha PLL config
-
-Update the IPQ6018 Alpha PLL config to the latest one from the downstream
-5.4 kernel[1].
-
-This one should match the production SoC-s.
-
-Tested on IPQ6018 CP01-C1 reference board.
-
-[1] https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.1.r4/drivers/clk/qcom/apss-ipq-pll.c#L41
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20220818220628.339366-6-robimarko@gmail.com
----
- drivers/clk/qcom/apss-ipq-pll.c | 8 ++++++--
- 1 file changed, 6 insertions(+), 2 deletions(-)
-
---- a/drivers/clk/qcom/apss-ipq-pll.c
-+++ b/drivers/clk/qcom/apss-ipq-pll.c
-@@ -39,10 +39,14 @@ static struct clk_alpha_pll ipq_pll = {
-
- static const struct alpha_pll_config ipq6018_pll_config = {
- .l = 0x37,
-- .config_ctl_val = 0x04141200,
-- .config_ctl_hi_val = 0x0,
-+ .config_ctl_val = 0x240d4828,
-+ .config_ctl_hi_val = 0x6,
- .early_output_mask = BIT(3),
-+ .aux2_output_mask = BIT(2),
-+ .aux_output_mask = BIT(1),
- .main_output_mask = BIT(0),
-+ .test_ctl_val = 0x1c0000C0,
-+ .test_ctl_hi_val = 0x4000,
- };
-
- static const struct regmap_config ipq_pll_regmap_config = {
+++ /dev/null
-From e0a711bd88ba98f6ab5118d248ec84fcf495d313 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Fri, 19 Aug 2022 00:06:26 +0200
-Subject: [PATCH] clk: qcom: apss-ipq-pll: add support for IPQ8074
-
-Add support for IPQ8074 since it uses the same PLL setup, however it uses
-slightly different Alpha PLL config.
-
-Alpha PLL config was obtained by dumping PLL registers from a running
-device.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20220818220628.339366-7-robimarko@gmail.com
----
- drivers/clk/qcom/apss-ipq-pll.c | 13 +++++++++++++
- 1 file changed, 13 insertions(+)
-
---- a/drivers/clk/qcom/apss-ipq-pll.c
-+++ b/drivers/clk/qcom/apss-ipq-pll.c
-@@ -49,6 +49,18 @@ static const struct alpha_pll_config ipq
- .test_ctl_hi_val = 0x4000,
- };
-
-+static const struct alpha_pll_config ipq8074_pll_config = {
-+ .l = 0x48,
-+ .config_ctl_val = 0x200d4828,
-+ .config_ctl_hi_val = 0x6,
-+ .early_output_mask = BIT(3),
-+ .aux2_output_mask = BIT(2),
-+ .aux_output_mask = BIT(1),
-+ .main_output_mask = BIT(0),
-+ .test_ctl_val = 0x1c000000,
-+ .test_ctl_hi_val = 0x4000,
-+};
-+
- static const struct regmap_config ipq_pll_regmap_config = {
- .reg_bits = 32,
- .reg_stride = 4,
-@@ -89,6 +101,7 @@ static int apss_ipq_pll_probe(struct pla
-
- static const struct of_device_id apss_ipq_pll_match_table[] = {
- { .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_config },
-+ { .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_config },
- { }
- };
- MODULE_DEVICE_TABLE(of, apss_ipq_pll_match_table);
+++ /dev/null
-From f7fb35d540240889a8f45f3fd42363cbc1a448e2 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Fri, 19 Aug 2022 00:06:20 +0200
-Subject: [PATCH] clk: qcom: clk-rcg2: add rcg2 mux ops
-
-An RCG may act as a mux that switch between 2 parents.
-This is the case on IPQ6018 and IPQ8074 where the APCS core clk that feeds
-the CPU cluster clock just switches between XO and the PLL that feeds it.
-
-Add the required ops to add support for this special configuration and use
-the generic mux function to determine the rate.
-
-This way we dont have to keep a essentially dummy frequency table to use
-RCG2 as a mux.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20220818220628.339366-1-robimarko@gmail.com
----
- drivers/clk/qcom/clk-rcg.h | 1 +
- drivers/clk/qcom/clk-rcg2.c | 7 +++++++
- 2 files changed, 8 insertions(+)
-
---- a/drivers/clk/qcom/clk-rcg.h
-+++ b/drivers/clk/qcom/clk-rcg.h
-@@ -164,6 +164,7 @@ struct clk_rcg2_gfx3d {
-
- extern const struct clk_ops clk_rcg2_ops;
- extern const struct clk_ops clk_rcg2_floor_ops;
-+extern const struct clk_ops clk_rcg2_mux_closest_ops;
- extern const struct clk_ops clk_edp_pixel_ops;
- extern const struct clk_ops clk_byte_ops;
- extern const struct clk_ops clk_byte2_ops;
---- a/drivers/clk/qcom/clk-rcg2.c
-+++ b/drivers/clk/qcom/clk-rcg2.c
-@@ -477,6 +477,13 @@ const struct clk_ops clk_rcg2_floor_ops
- };
- EXPORT_SYMBOL_GPL(clk_rcg2_floor_ops);
-
-+const struct clk_ops clk_rcg2_mux_closest_ops = {
-+ .determine_rate = __clk_mux_determine_rate_closest,
-+ .get_parent = clk_rcg2_get_parent,
-+ .set_parent = clk_rcg2_set_parent,
-+};
-+EXPORT_SYMBOL_GPL(clk_rcg2_mux_closest_ops);
-+
- struct frac_entry {
- int num;
- int den;
+++ /dev/null
-From 6b9d5ecd2913758780a0529f9b95392f330b721b Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Fri, 19 Aug 2022 00:06:21 +0200
-Subject: [PATCH] clk: qcom: apss-ipq6018: fix apcs_alias0_clk_src
-
-While working on IPQ8074 APSS driver it was discovered that IPQ6018 and
-IPQ8074 use almost the same PLL and APSS clocks, however APSS driver is
-currently broken.
-
-More precisely apcs_alias0_clk_src is broken, it was added as regmap_mux
-clock.
-However after debugging why it was always stuck at 800Mhz, it was figured
-out that its not regmap_mux compatible at all.
-It is a simple mux but it uses RCG2 register layout and control bits, so
-utilize the new clk_rcg2_mux_closest_ops to correctly drive it while not
-having to provide a dummy frequency table.
-
-While we are here, use ARRAY_SIZE for number of parents.
-
-Tested on IPQ6018-CP01-C1 reference board and multiple IPQ8074 boards.
-
-Fixes: 5e77b4ef1b19 ("clk: qcom: Add ipq6018 apss clock controller")
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20220818220628.339366-2-robimarko@gmail.com
----
- drivers/clk/qcom/apss-ipq6018.c | 13 ++++++-------
- 1 file changed, 6 insertions(+), 7 deletions(-)
-
---- a/drivers/clk/qcom/apss-ipq6018.c
-+++ b/drivers/clk/qcom/apss-ipq6018.c
-@@ -16,7 +16,7 @@
- #include "clk-regmap.h"
- #include "clk-branch.h"
- #include "clk-alpha-pll.h"
--#include "clk-regmap-mux.h"
-+#include "clk-rcg.h"
-
- enum {
- P_XO,
-@@ -33,16 +33,15 @@ static const struct parent_map parents_a
- { P_APSS_PLL_EARLY, 5 },
- };
-
--static struct clk_regmap_mux apcs_alias0_clk_src = {
-- .reg = 0x0050,
-- .width = 3,
-- .shift = 7,
-+static struct clk_rcg2 apcs_alias0_clk_src = {
-+ .cmd_rcgr = 0x0050,
-+ .hid_width = 5,
- .parent_map = parents_apcs_alias0_clk_src_map,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "apcs_alias0_clk_src",
- .parent_data = parents_apcs_alias0_clk_src,
-- .num_parents = 2,
-- .ops = &clk_regmap_mux_closest_ops,
-+ .num_parents = ARRAY_SIZE(parents_apcs_alias0_clk_src),
-+ .ops = &clk_rcg2_mux_closest_ops,
- .flags = CLK_SET_RATE_PARENT,
- },
- };
+++ /dev/null
-From 23c5ff3143ce43a76eebdf60a93436de9db39a7a Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Fri, 19 Aug 2022 00:06:27 +0200
-Subject: [PATCH] arm64: dts: qcom: ipq8074: correct APCS register space size
-
-APCS DTS addition that was merged, was not supposed to get merged as it
-was part of patch series that was superseded by 2 more patch series
-that resolved issues with this one and greatly simplified things.
-
-Since it already got merged, start by correcting the register space
-size as APCS will not be providing regmap for PLL and it will conflict
-with the standalone A53 PLL node.
-
-Fixes: 50ed9fffec3a ("arm64: dts: qcom: ipq8074: add APCS node")
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20220818220628.339366-8-robimarko@gmail.com
----
- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
-@@ -669,7 +669,7 @@
-
- apcs_glb: mailbox@b111000 {
- compatible = "qcom,ipq8074-apcs-apps-global";
-- reg = <0x0b111000 0x6000>;
-+ reg = <0x0b111000 0x1000>;
-
- #clock-cells = <1>;
- #mbox-cells = <1>;
+++ /dev/null
-From 72bc31aa621e21a7c36a7da8aa6f6a77bb234e0b Mon Sep 17 00:00:00 2001
-From: Stephan Gerhold <stephan.gerhold@kernkonzept.com>
-Date: Wed, 6 Jul 2022 15:41:29 +0200
-Subject: [PATCH] clk: qcom: reset: Allow specifying custom reset delay
-
-The amount of time required between asserting and deasserting the reset
-signal can vary depending on the involved hardware component. Sometimes
-1 us might not be enough and a larger delay is necessary to conform to
-the specifications.
-
-Usually this is worked around in the consuming drivers, by replacing
-reset_control_reset() with a sequence of reset_control_assert(), waiting
-for a custom delay, followed by reset_control_deassert().
-
-However, in some cases the driver making use of the reset is generic and
-can be used with different reset controllers. In this case the reset
-time requirement is better handled directly by the reset controller
-driver.
-
-Make this possible by adding an "udelay" field to the qcom_reset_map
-that allows setting a different reset delay (in microseconds).
-
-Signed-off-by: Stephan Gerhold <stephan.gerhold@kernkonzept.com>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20220706134132.3623415-4-stephan.gerhold@kernkonzept.com
----
- drivers/clk/qcom/reset.c | 4 +++-
- drivers/clk/qcom/reset.h | 1 +
- 2 files changed, 4 insertions(+), 1 deletion(-)
-
---- a/drivers/clk/qcom/reset.c
-+++ b/drivers/clk/qcom/reset.c
-@@ -13,8 +13,10 @@
-
- static int qcom_reset(struct reset_controller_dev *rcdev, unsigned long id)
- {
-+ struct qcom_reset_controller *rst = to_qcom_reset_controller(rcdev);
-+
- rcdev->ops->assert(rcdev, id);
-- udelay(1);
-+ udelay(rst->reset_map[id].udelay ?: 1); /* use 1 us as default */
- rcdev->ops->deassert(rcdev, id);
- return 0;
- }
---- a/drivers/clk/qcom/reset.h
-+++ b/drivers/clk/qcom/reset.h
-@@ -11,6 +11,7 @@
- struct qcom_reset_map {
- unsigned int reg;
- u8 bit;
-+ u8 udelay;
- };
-
- struct regmap;
+++ /dev/null
-From 0afa47c1b57ba645225b38654869a6e5d2939da5 Mon Sep 17 00:00:00 2001
-From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Date: Fri, 6 May 2022 18:21:07 +0300
-Subject: [PATCH] arm64: dts: qcom: replace deprecated perst-gpio with
- perst-gpios
-
-Replace deprecated perst-gpio and wake-gpio properties with up-to-date
-perst-gpios and wake-gpios in the Qualcomm device trees.
-
-Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-Link: https://lore.kernel.org/r/20220506152107.1527552-9-dmitry.baryshkov@linaro.org
----
- arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 4 ++--
- arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi | 4 ++--
- 2 files changed, 4 insertions(+), 4 deletions(-)
-
---- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
-+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
-@@ -49,12 +49,12 @@
-
- &pcie0 {
- status = "okay";
-- perst-gpio = <&tlmm 61 0x1>;
-+ perst-gpios = <&tlmm 61 0x1>;
- };
-
- &pcie1 {
- status = "okay";
-- perst-gpio = <&tlmm 58 0x1>;
-+ perst-gpios = <&tlmm 58 0x1>;
- };
-
- &pcie_qmp0 {
---- a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
-+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
-@@ -39,12 +39,12 @@
-
- &pcie0 {
- status = "ok";
-- perst-gpio = <&tlmm 58 0x1>;
-+ perst-gpios = <&tlmm 58 0x1>;
- };
-
- &pcie1 {
- status = "ok";
-- perst-gpio = <&tlmm 61 0x1>;
-+ perst-gpios = <&tlmm 61 0x1>;
- };
-
- &pcie_phy0 {
+++ /dev/null
-From 0eda4c5c7704363f665f4ccf0327349faad245a4 Mon Sep 17 00:00:00 2001
-From: Caleb Connolly <caleb.connolly@linaro.org>
-Date: Fri, 29 Apr 2022 23:08:56 +0100
-Subject: [PATCH] spmi: add a helper to look up an SPMI device from a device
- node
-
-The helper function spmi_device_from_of() takes a device node and
-returns the SPMI device associated with it.
-This is like of_find_device_by_node but for SPMI devices.
-
-Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
-Acked-by: Stephen Boyd <sboyd@kernel.org>
-Link: https://lore.kernel.org/r/20220429220904.137297-2-caleb.connolly@linaro.org
-Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
----
- drivers/spmi/spmi.c | 17 +++++++++++++++++
- include/linux/spmi.h | 3 +++
- 2 files changed, 20 insertions(+)
-
---- a/drivers/spmi/spmi.c
-+++ b/drivers/spmi/spmi.c
-@@ -388,6 +388,23 @@ static struct bus_type spmi_bus_type = {
- };
-
- /**
-+ * spmi_device_from_of() - get the associated SPMI device from a device node
-+ *
-+ * @np: device node
-+ *
-+ * Returns the struct spmi_device associated with a device node or NULL.
-+ */
-+struct spmi_device *spmi_device_from_of(struct device_node *np)
-+{
-+ struct device *dev = bus_find_device_by_of_node(&spmi_bus_type, np);
-+
-+ if (dev)
-+ return to_spmi_device(dev);
-+ return NULL;
-+}
-+EXPORT_SYMBOL_GPL(spmi_device_from_of);
-+
-+/**
- * spmi_controller_alloc() - Allocate a new SPMI device
- * @ctrl: associated controller
- *
---- a/include/linux/spmi.h
-+++ b/include/linux/spmi.h
-@@ -164,6 +164,9 @@ static inline void spmi_driver_unregiste
- module_driver(__spmi_driver, spmi_driver_register, \
- spmi_driver_unregister)
-
-+struct device_node;
-+
-+struct spmi_device *spmi_device_from_of(struct device_node *np);
- int spmi_register_read(struct spmi_device *sdev, u8 addr, u8 *buf);
- int spmi_ext_register_read(struct spmi_device *sdev, u8 addr, u8 *buf,
- size_t len);
+++ /dev/null
-From 60df90d6829d16338e2971420220395cfc289247 Mon Sep 17 00:00:00 2001
-From: Bjorn Andersson <bjorn.andersson@linaro.org>
-Date: Sun, 17 Oct 2021 09:12:16 -0700
-Subject: [PATCH] mfd: qcom-spmi-pmic: Sort compatibles in the driver
-
-Sort the compatibles in the driver, to make it easier to validate that
-the DT binding and driver are in sync.
-
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Signed-off-by: Lee Jones <lee.jones@linaro.org>
-Link: https://lore.kernel.org/r/20211017161218.2378176-2-bjorn.andersson@linaro.org
----
- drivers/mfd/qcom-spmi-pmic.c | 30 +++++++++++++++---------------
- 1 file changed, 15 insertions(+), 15 deletions(-)
-
---- a/drivers/mfd/qcom-spmi-pmic.c
-+++ b/drivers/mfd/qcom-spmi-pmic.c
-@@ -40,27 +40,27 @@
- #define PM660_SUBTYPE 0x1B
-
- static const struct of_device_id pmic_spmi_id_table[] = {
-- { .compatible = "qcom,spmi-pmic", .data = (void *)COMMON_SUBTYPE },
-- { .compatible = "qcom,pm8941", .data = (void *)PM8941_SUBTYPE },
-- { .compatible = "qcom,pm8841", .data = (void *)PM8841_SUBTYPE },
-+ { .compatible = "qcom,pm660", .data = (void *)PM660_SUBTYPE },
-+ { .compatible = "qcom,pm660l", .data = (void *)PM660L_SUBTYPE },
-+ { .compatible = "qcom,pm8004", .data = (void *)PM8004_SUBTYPE },
-+ { .compatible = "qcom,pm8005", .data = (void *)PM8005_SUBTYPE },
- { .compatible = "qcom,pm8019", .data = (void *)PM8019_SUBTYPE },
-- { .compatible = "qcom,pm8226", .data = (void *)PM8226_SUBTYPE },
- { .compatible = "qcom,pm8110", .data = (void *)PM8110_SUBTYPE },
-- { .compatible = "qcom,pma8084", .data = (void *)PMA8084_SUBTYPE },
-- { .compatible = "qcom,pmi8962", .data = (void *)PMI8962_SUBTYPE },
-- { .compatible = "qcom,pmd9635", .data = (void *)PMD9635_SUBTYPE },
-- { .compatible = "qcom,pm8994", .data = (void *)PM8994_SUBTYPE },
-- { .compatible = "qcom,pmi8994", .data = (void *)PMI8994_SUBTYPE },
-- { .compatible = "qcom,pm8916", .data = (void *)PM8916_SUBTYPE },
-- { .compatible = "qcom,pm8004", .data = (void *)PM8004_SUBTYPE },
-+ { .compatible = "qcom,pm8226", .data = (void *)PM8226_SUBTYPE },
-+ { .compatible = "qcom,pm8841", .data = (void *)PM8841_SUBTYPE },
- { .compatible = "qcom,pm8909", .data = (void *)PM8909_SUBTYPE },
-+ { .compatible = "qcom,pm8916", .data = (void *)PM8916_SUBTYPE },
-+ { .compatible = "qcom,pm8941", .data = (void *)PM8941_SUBTYPE },
- { .compatible = "qcom,pm8950", .data = (void *)PM8950_SUBTYPE },
-- { .compatible = "qcom,pmi8950", .data = (void *)PMI8950_SUBTYPE },
-+ { .compatible = "qcom,pm8994", .data = (void *)PM8994_SUBTYPE },
- { .compatible = "qcom,pm8998", .data = (void *)PM8998_SUBTYPE },
-+ { .compatible = "qcom,pma8084", .data = (void *)PMA8084_SUBTYPE },
-+ { .compatible = "qcom,pmd9635", .data = (void *)PMD9635_SUBTYPE },
-+ { .compatible = "qcom,pmi8950", .data = (void *)PMI8950_SUBTYPE },
-+ { .compatible = "qcom,pmi8962", .data = (void *)PMI8962_SUBTYPE },
-+ { .compatible = "qcom,pmi8994", .data = (void *)PMI8994_SUBTYPE },
- { .compatible = "qcom,pmi8998", .data = (void *)PMI8998_SUBTYPE },
-- { .compatible = "qcom,pm8005", .data = (void *)PM8005_SUBTYPE },
-- { .compatible = "qcom,pm660l", .data = (void *)PM660L_SUBTYPE },
-- { .compatible = "qcom,pm660", .data = (void *)PM660_SUBTYPE },
-+ { .compatible = "qcom,spmi-pmic", .data = (void *)COMMON_SUBTYPE },
- { }
- };
-
+++ /dev/null
-From 18921bfd81c88fb85a19683467f680897672f062 Mon Sep 17 00:00:00 2001
-From: Bjorn Andersson <bjorn.andersson@linaro.org>
-Date: Sun, 17 Oct 2021 09:12:18 -0700
-Subject: [PATCH] mfd: qcom-spmi-pmic: Add missing PMICs supported by socinfo
-
-The Qualcomm socinfo driver has eight more PMICs described, add these to
-the SPMI PMIC driver as well.
-
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Signed-off-by: Lee Jones <lee.jones@linaro.org>
-Link: https://lore.kernel.org/r/20211017161218.2378176-4-bjorn.andersson@linaro.org
----
- drivers/mfd/qcom-spmi-pmic.c | 17 +++++++++++++++++
- 1 file changed, 17 insertions(+)
-
---- a/drivers/mfd/qcom-spmi-pmic.c
-+++ b/drivers/mfd/qcom-spmi-pmic.c
-@@ -31,6 +31,8 @@
- #define PM8916_SUBTYPE 0x0b
- #define PM8004_SUBTYPE 0x0c
- #define PM8909_SUBTYPE 0x0d
-+#define PM8028_SUBTYPE 0x0e
-+#define PM8901_SUBTYPE 0x0f
- #define PM8950_SUBTYPE 0x10
- #define PMI8950_SUBTYPE 0x11
- #define PM8998_SUBTYPE 0x14
-@@ -38,6 +40,13 @@
- #define PM8005_SUBTYPE 0x18
- #define PM660L_SUBTYPE 0x1A
- #define PM660_SUBTYPE 0x1B
-+#define PM8150_SUBTYPE 0x1E
-+#define PM8150L_SUBTYPE 0x1f
-+#define PM8150B_SUBTYPE 0x20
-+#define PMK8002_SUBTYPE 0x21
-+#define PM8009_SUBTYPE 0x24
-+#define PM8150C_SUBTYPE 0x26
-+#define SMB2351_SUBTYPE 0x29
-
- static const struct of_device_id pmic_spmi_id_table[] = {
- { .compatible = "qcom,pm660", .data = (void *)PM660_SUBTYPE },
-@@ -45,9 +54,15 @@ static const struct of_device_id pmic_sp
- { .compatible = "qcom,pm8004", .data = (void *)PM8004_SUBTYPE },
- { .compatible = "qcom,pm8005", .data = (void *)PM8005_SUBTYPE },
- { .compatible = "qcom,pm8019", .data = (void *)PM8019_SUBTYPE },
-+ { .compatible = "qcom,pm8028", .data = (void *)PM8028_SUBTYPE },
- { .compatible = "qcom,pm8110", .data = (void *)PM8110_SUBTYPE },
-+ { .compatible = "qcom,pm8150", .data = (void *)PM8150_SUBTYPE },
-+ { .compatible = "qcom,pm8150b", .data = (void *)PM8150B_SUBTYPE },
-+ { .compatible = "qcom,pm8150c", .data = (void *)PM8150C_SUBTYPE },
-+ { .compatible = "qcom,pm8150l", .data = (void *)PM8150L_SUBTYPE },
- { .compatible = "qcom,pm8226", .data = (void *)PM8226_SUBTYPE },
- { .compatible = "qcom,pm8841", .data = (void *)PM8841_SUBTYPE },
-+ { .compatible = "qcom,pm8901", .data = (void *)PM8901_SUBTYPE },
- { .compatible = "qcom,pm8909", .data = (void *)PM8909_SUBTYPE },
- { .compatible = "qcom,pm8916", .data = (void *)PM8916_SUBTYPE },
- { .compatible = "qcom,pm8941", .data = (void *)PM8941_SUBTYPE },
-@@ -60,6 +75,8 @@ static const struct of_device_id pmic_sp
- { .compatible = "qcom,pmi8962", .data = (void *)PMI8962_SUBTYPE },
- { .compatible = "qcom,pmi8994", .data = (void *)PMI8994_SUBTYPE },
- { .compatible = "qcom,pmi8998", .data = (void *)PMI8998_SUBTYPE },
-+ { .compatible = "qcom,pmk8002", .data = (void *)PMK8002_SUBTYPE },
-+ { .compatible = "qcom,smb2351", .data = (void *)SMB2351_SUBTYPE },
- { .compatible = "qcom,spmi-pmic", .data = (void *)COMMON_SUBTYPE },
- { }
- };
+++ /dev/null
-From 231f6a9f24a5e9b6e7af801ca2377970474cdf59 Mon Sep 17 00:00:00 2001
-From: Caleb Connolly <caleb.connolly@linaro.org>
-Date: Fri, 29 Apr 2022 23:08:57 +0100
-Subject: [PATCH] mfd: qcom-spmi-pmic: expose the PMIC revid information to
- clients
-
-Some PMIC functions such as the RRADC need to be aware of the PMIC
-chip revision information to implement errata or otherwise adjust
-behaviour, export the PMIC information to enable this.
-
-This is specifically required to enable the RRADC to adjust
-coefficients based on which chip fab the PMIC was produced in,
-this can vary per unique device and therefore has to be read at
-runtime.
-
-Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
-Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Acked-by: Lee Jones <lee.jones@linaro.org>
-Link: https://lore.kernel.org/r/20220429220904.137297-3-caleb.connolly@linaro.org
-Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
----
- drivers/mfd/qcom-spmi-pmic.c | 265 ++++++++++++++++++++----------
- include/soc/qcom/qcom-spmi-pmic.h | 60 +++++++
- 2 files changed, 235 insertions(+), 90 deletions(-)
- create mode 100644 include/soc/qcom/qcom-spmi-pmic.h
-
---- a/drivers/mfd/qcom-spmi-pmic.c
-+++ b/drivers/mfd/qcom-spmi-pmic.c
-@@ -3,11 +3,16 @@
- * Copyright (c) 2014, The Linux Foundation. All rights reserved.
- */
-
-+#include <linux/device.h>
-+#include <linux/errno.h>
-+#include <linux/gfp.h>
- #include <linux/kernel.h>
- #include <linux/module.h>
- #include <linux/spmi.h>
-+#include <linux/types.h>
- #include <linux/regmap.h>
- #include <linux/of_platform.h>
-+#include <soc/qcom/qcom-spmi-pmic.h>
-
- #define PMIC_REV2 0x101
- #define PMIC_REV3 0x102
-@@ -17,106 +22,140 @@
-
- #define PMIC_TYPE_VALUE 0x51
-
--#define COMMON_SUBTYPE 0x00
--#define PM8941_SUBTYPE 0x01
--#define PM8841_SUBTYPE 0x02
--#define PM8019_SUBTYPE 0x03
--#define PM8226_SUBTYPE 0x04
--#define PM8110_SUBTYPE 0x05
--#define PMA8084_SUBTYPE 0x06
--#define PMI8962_SUBTYPE 0x07
--#define PMD9635_SUBTYPE 0x08
--#define PM8994_SUBTYPE 0x09
--#define PMI8994_SUBTYPE 0x0a
--#define PM8916_SUBTYPE 0x0b
--#define PM8004_SUBTYPE 0x0c
--#define PM8909_SUBTYPE 0x0d
--#define PM8028_SUBTYPE 0x0e
--#define PM8901_SUBTYPE 0x0f
--#define PM8950_SUBTYPE 0x10
--#define PMI8950_SUBTYPE 0x11
--#define PM8998_SUBTYPE 0x14
--#define PMI8998_SUBTYPE 0x15
--#define PM8005_SUBTYPE 0x18
--#define PM660L_SUBTYPE 0x1A
--#define PM660_SUBTYPE 0x1B
--#define PM8150_SUBTYPE 0x1E
--#define PM8150L_SUBTYPE 0x1f
--#define PM8150B_SUBTYPE 0x20
--#define PMK8002_SUBTYPE 0x21
--#define PM8009_SUBTYPE 0x24
--#define PM8150C_SUBTYPE 0x26
--#define SMB2351_SUBTYPE 0x29
-+#define PMIC_REV4_V2 0x02
-+
-+struct qcom_spmi_dev {
-+ int num_usids;
-+ struct qcom_spmi_pmic pmic;
-+};
-+
-+#define N_USIDS(n) ((void *)n)
-
- static const struct of_device_id pmic_spmi_id_table[] = {
-- { .compatible = "qcom,pm660", .data = (void *)PM660_SUBTYPE },
-- { .compatible = "qcom,pm660l", .data = (void *)PM660L_SUBTYPE },
-- { .compatible = "qcom,pm8004", .data = (void *)PM8004_SUBTYPE },
-- { .compatible = "qcom,pm8005", .data = (void *)PM8005_SUBTYPE },
-- { .compatible = "qcom,pm8019", .data = (void *)PM8019_SUBTYPE },
-- { .compatible = "qcom,pm8028", .data = (void *)PM8028_SUBTYPE },
-- { .compatible = "qcom,pm8110", .data = (void *)PM8110_SUBTYPE },
-- { .compatible = "qcom,pm8150", .data = (void *)PM8150_SUBTYPE },
-- { .compatible = "qcom,pm8150b", .data = (void *)PM8150B_SUBTYPE },
-- { .compatible = "qcom,pm8150c", .data = (void *)PM8150C_SUBTYPE },
-- { .compatible = "qcom,pm8150l", .data = (void *)PM8150L_SUBTYPE },
-- { .compatible = "qcom,pm8226", .data = (void *)PM8226_SUBTYPE },
-- { .compatible = "qcom,pm8841", .data = (void *)PM8841_SUBTYPE },
-- { .compatible = "qcom,pm8901", .data = (void *)PM8901_SUBTYPE },
-- { .compatible = "qcom,pm8909", .data = (void *)PM8909_SUBTYPE },
-- { .compatible = "qcom,pm8916", .data = (void *)PM8916_SUBTYPE },
-- { .compatible = "qcom,pm8941", .data = (void *)PM8941_SUBTYPE },
-- { .compatible = "qcom,pm8950", .data = (void *)PM8950_SUBTYPE },
-- { .compatible = "qcom,pm8994", .data = (void *)PM8994_SUBTYPE },
-- { .compatible = "qcom,pm8998", .data = (void *)PM8998_SUBTYPE },
-- { .compatible = "qcom,pma8084", .data = (void *)PMA8084_SUBTYPE },
-- { .compatible = "qcom,pmd9635", .data = (void *)PMD9635_SUBTYPE },
-- { .compatible = "qcom,pmi8950", .data = (void *)PMI8950_SUBTYPE },
-- { .compatible = "qcom,pmi8962", .data = (void *)PMI8962_SUBTYPE },
-- { .compatible = "qcom,pmi8994", .data = (void *)PMI8994_SUBTYPE },
-- { .compatible = "qcom,pmi8998", .data = (void *)PMI8998_SUBTYPE },
-- { .compatible = "qcom,pmk8002", .data = (void *)PMK8002_SUBTYPE },
-- { .compatible = "qcom,smb2351", .data = (void *)SMB2351_SUBTYPE },
-- { .compatible = "qcom,spmi-pmic", .data = (void *)COMMON_SUBTYPE },
-+ { .compatible = "qcom,pm660", .data = N_USIDS(2) },
-+ { .compatible = "qcom,pm660l", .data = N_USIDS(2) },
-+ { .compatible = "qcom,pm8004", .data = N_USIDS(2) },
-+ { .compatible = "qcom,pm8005", .data = N_USIDS(2) },
-+ { .compatible = "qcom,pm8019", .data = N_USIDS(2) },
-+ { .compatible = "qcom,pm8028", .data = N_USIDS(2) },
-+ { .compatible = "qcom,pm8110", .data = N_USIDS(2) },
-+ { .compatible = "qcom,pm8150", .data = N_USIDS(2) },
-+ { .compatible = "qcom,pm8150b", .data = N_USIDS(2) },
-+ { .compatible = "qcom,pm8150c", .data = N_USIDS(2) },
-+ { .compatible = "qcom,pm8150l", .data = N_USIDS(2) },
-+ { .compatible = "qcom,pm8226", .data = N_USIDS(2) },
-+ { .compatible = "qcom,pm8841", .data = N_USIDS(2) },
-+ { .compatible = "qcom,pm8901", .data = N_USIDS(2) },
-+ { .compatible = "qcom,pm8909", .data = N_USIDS(2) },
-+ { .compatible = "qcom,pm8916", .data = N_USIDS(2) },
-+ { .compatible = "qcom,pm8941", .data = N_USIDS(2) },
-+ { .compatible = "qcom,pm8950", .data = N_USIDS(2) },
-+ { .compatible = "qcom,pm8994", .data = N_USIDS(2) },
-+ { .compatible = "qcom,pm8998", .data = N_USIDS(2) },
-+ { .compatible = "qcom,pma8084", .data = N_USIDS(2) },
-+ { .compatible = "qcom,pmd9635", .data = N_USIDS(2) },
-+ { .compatible = "qcom,pmi8950", .data = N_USIDS(2) },
-+ { .compatible = "qcom,pmi8962", .data = N_USIDS(2) },
-+ { .compatible = "qcom,pmi8994", .data = N_USIDS(2) },
-+ { .compatible = "qcom,pmi8998", .data = N_USIDS(2) },
-+ { .compatible = "qcom,pmk8002", .data = N_USIDS(2) },
-+ { .compatible = "qcom,smb2351", .data = N_USIDS(2) },
-+ { .compatible = "qcom,spmi-pmic", .data = N_USIDS(1) },
- { }
- };
-
--static void pmic_spmi_show_revid(struct regmap *map, struct device *dev)
-+/*
-+ * A PMIC can be represented by multiple SPMI devices, but
-+ * only the base PMIC device will contain a reference to
-+ * the revision information.
-+ *
-+ * This function takes a pointer to a pmic device and
-+ * returns a pointer to the base PMIC device.
-+ *
-+ * This only supports PMICs with 1 or 2 USIDs.
-+ */
-+static struct spmi_device *qcom_pmic_get_base_usid(struct device *dev)
- {
-- unsigned int rev2, minor, major, type, subtype;
-- const char *name = "unknown";
-- int ret, i;
-+ struct spmi_device *sdev;
-+ struct qcom_spmi_dev *ctx;
-+ struct device_node *spmi_bus;
-+ struct device_node *other_usid = NULL;
-+ int function_parent_usid, ret;
-+ u32 pmic_addr;
-
-- ret = regmap_read(map, PMIC_TYPE, &type);
-- if (ret < 0)
-- return;
-+ sdev = to_spmi_device(dev);
-+ ctx = dev_get_drvdata(&sdev->dev);
-
-- if (type != PMIC_TYPE_VALUE)
-- return;
-+ /*
-+ * Quick return if the function device is already in the base
-+ * USID. This will always be hit for PMICs with only 1 USID.
-+ */
-+ if (sdev->usid % ctx->num_usids == 0)
-+ return sdev;
-
-- ret = regmap_read(map, PMIC_SUBTYPE, &subtype);
-+ function_parent_usid = sdev->usid;
-+
-+ /*
-+ * Walk through the list of PMICs until we find the sibling USID.
-+ * The goal is to find the first USID which is less than the
-+ * number of USIDs in the PMIC array, e.g. for a PMIC with 2 USIDs
-+ * where the function device is under USID 3, we want to find the
-+ * device for USID 2.
-+ */
-+ spmi_bus = of_get_parent(sdev->dev.of_node);
-+ do {
-+ other_usid = of_get_next_child(spmi_bus, other_usid);
-+
-+ ret = of_property_read_u32_index(other_usid, "reg", 0, &pmic_addr);
-+ if (ret)
-+ return ERR_PTR(ret);
-+
-+ sdev = spmi_device_from_of(other_usid);
-+ if (pmic_addr == function_parent_usid - (ctx->num_usids - 1)) {
-+ if (!sdev)
-+ /*
-+ * If the base USID for this PMIC hasn't probed yet
-+ * but the secondary USID has, then we need to defer
-+ * the function driver so that it will attempt to
-+ * probe again when the base USID is ready.
-+ */
-+ return ERR_PTR(-EPROBE_DEFER);
-+ return sdev;
-+ }
-+ } while (other_usid->sibling);
-+
-+ return ERR_PTR(-ENODATA);
-+}
-+
-+static int pmic_spmi_load_revid(struct regmap *map, struct device *dev,
-+ struct qcom_spmi_pmic *pmic)
-+{
-+ int ret;
-+
-+ ret = regmap_read(map, PMIC_TYPE, &pmic->type);
- if (ret < 0)
-- return;
-+ return ret;
-
-- for (i = 0; i < ARRAY_SIZE(pmic_spmi_id_table); i++) {
-- if (subtype == (unsigned long)pmic_spmi_id_table[i].data)
-- break;
-- }
-+ if (pmic->type != PMIC_TYPE_VALUE)
-+ return ret;
-
-- if (i != ARRAY_SIZE(pmic_spmi_id_table))
-- name = pmic_spmi_id_table[i].compatible;
-+ ret = regmap_read(map, PMIC_SUBTYPE, &pmic->subtype);
-+ if (ret < 0)
-+ return ret;
-
-- ret = regmap_read(map, PMIC_REV2, &rev2);
-+ pmic->name = of_match_device(pmic_spmi_id_table, dev)->compatible;
-+
-+ ret = regmap_read(map, PMIC_REV2, &pmic->rev2);
- if (ret < 0)
-- return;
-+ return ret;
-
-- ret = regmap_read(map, PMIC_REV3, &minor);
-+ ret = regmap_read(map, PMIC_REV3, &pmic->minor);
- if (ret < 0)
-- return;
-+ return ret;
-
-- ret = regmap_read(map, PMIC_REV4, &major);
-+ ret = regmap_read(map, PMIC_REV4, &pmic->major);
- if (ret < 0)
-- return;
-+ return ret;
-
- /*
- * In early versions of PM8941 and PM8226, the major revision number
-@@ -124,15 +163,49 @@ static void pmic_spmi_show_revid(struct
- * Increment the major revision number here if the chip is an early
- * version of PM8941 or PM8226.
- */
-- if ((subtype == PM8941_SUBTYPE || subtype == PM8226_SUBTYPE) &&
-- major < 0x02)
-- major++;
-+ if ((pmic->subtype == PM8941_SUBTYPE || pmic->subtype == PM8226_SUBTYPE) &&
-+ pmic->major < PMIC_REV4_V2)
-+ pmic->major++;
-+
-+ if (pmic->subtype == PM8110_SUBTYPE)
-+ pmic->minor = pmic->rev2;
-+
-+ dev_dbg(dev, "%x: %s v%d.%d\n",
-+ pmic->subtype, pmic->name, pmic->major, pmic->minor);
-+
-+ return 0;
-+}
-+
-+/**
-+ * qcom_pmic_get() - Get a pointer to the base PMIC device
-+ *
-+ * This function takes a struct device for a driver which is a child of a PMIC.
-+ * And locates the PMIC revision information for it.
-+ *
-+ * @dev: the pmic function device
-+ * @return: the struct qcom_spmi_pmic* pointer associated with the function device
-+ */
-+const struct qcom_spmi_pmic *qcom_pmic_get(struct device *dev)
-+{
-+ struct spmi_device *sdev;
-+ struct qcom_spmi_dev *spmi;
-+
-+ /*
-+ * Make sure the device is actually a child of a PMIC
-+ */
-+ if (!of_match_device(pmic_spmi_id_table, dev->parent))
-+ return ERR_PTR(-EINVAL);
-+
-+ sdev = qcom_pmic_get_base_usid(dev->parent);
-
-- if (subtype == PM8110_SUBTYPE)
-- minor = rev2;
-+ if (IS_ERR(sdev))
-+ return ERR_CAST(sdev);
-
-- dev_dbg(dev, "%x: %s v%d.%d\n", subtype, name, major, minor);
-+ spmi = dev_get_drvdata(&sdev->dev);
-+
-+ return &spmi->pmic;
- }
-+EXPORT_SYMBOL(qcom_pmic_get);
-
- static const struct regmap_config spmi_regmap_config = {
- .reg_bits = 16,
-@@ -144,14 +217,26 @@ static const struct regmap_config spmi_r
- static int pmic_spmi_probe(struct spmi_device *sdev)
- {
- struct regmap *regmap;
-+ struct qcom_spmi_dev *ctx;
-+ int ret;
-
- regmap = devm_regmap_init_spmi_ext(sdev, &spmi_regmap_config);
- if (IS_ERR(regmap))
- return PTR_ERR(regmap);
-
-+ ctx = devm_kzalloc(&sdev->dev, sizeof(*ctx), GFP_KERNEL);
-+ if (!ctx)
-+ return -ENOMEM;
-+
-+ ctx->num_usids = (uintptr_t)of_device_get_match_data(&sdev->dev);
-+
- /* Only the first slave id for a PMIC contains this information */
-- if (sdev->usid % 2 == 0)
-- pmic_spmi_show_revid(regmap, &sdev->dev);
-+ if (sdev->usid % ctx->num_usids == 0) {
-+ ret = pmic_spmi_load_revid(regmap, &sdev->dev, &ctx->pmic);
-+ if (ret < 0)
-+ return ret;
-+ }
-+ spmi_device_set_drvdata(sdev, ctx);
-
- return devm_of_platform_populate(&sdev->dev);
- }
---- /dev/null
-+++ b/include/soc/qcom/qcom-spmi-pmic.h
-@@ -0,0 +1,60 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+/* Copyright (c) 2022 Linaro. All rights reserved.
-+ * Author: Caleb Connolly <caleb.connolly@linaro.org>
-+ */
-+
-+#ifndef __QCOM_SPMI_PMIC_H__
-+#define __QCOM_SPMI_PMIC_H__
-+
-+#include <linux/device.h>
-+
-+#define COMMON_SUBTYPE 0x00
-+#define PM8941_SUBTYPE 0x01
-+#define PM8841_SUBTYPE 0x02
-+#define PM8019_SUBTYPE 0x03
-+#define PM8226_SUBTYPE 0x04
-+#define PM8110_SUBTYPE 0x05
-+#define PMA8084_SUBTYPE 0x06
-+#define PMI8962_SUBTYPE 0x07
-+#define PMD9635_SUBTYPE 0x08
-+#define PM8994_SUBTYPE 0x09
-+#define PMI8994_SUBTYPE 0x0a
-+#define PM8916_SUBTYPE 0x0b
-+#define PM8004_SUBTYPE 0x0c
-+#define PM8909_SUBTYPE 0x0d
-+#define PM8028_SUBTYPE 0x0e
-+#define PM8901_SUBTYPE 0x0f
-+#define PM8950_SUBTYPE 0x10
-+#define PMI8950_SUBTYPE 0x11
-+#define PM8998_SUBTYPE 0x14
-+#define PMI8998_SUBTYPE 0x15
-+#define PM8005_SUBTYPE 0x18
-+#define PM660L_SUBTYPE 0x1A
-+#define PM660_SUBTYPE 0x1B
-+#define PM8150_SUBTYPE 0x1E
-+#define PM8150L_SUBTYPE 0x1f
-+#define PM8150B_SUBTYPE 0x20
-+#define PMK8002_SUBTYPE 0x21
-+#define PM8009_SUBTYPE 0x24
-+#define PM8150C_SUBTYPE 0x26
-+#define SMB2351_SUBTYPE 0x29
-+
-+#define PMI8998_FAB_ID_SMIC 0x11
-+#define PMI8998_FAB_ID_GF 0x30
-+
-+#define PM660_FAB_ID_GF 0x0
-+#define PM660_FAB_ID_TSMC 0x2
-+#define PM660_FAB_ID_MX 0x3
-+
-+struct qcom_spmi_pmic {
-+ unsigned int type;
-+ unsigned int subtype;
-+ unsigned int major;
-+ unsigned int minor;
-+ unsigned int rev2;
-+ const char *name;
-+};
-+
-+const struct qcom_spmi_pmic *qcom_pmic_get(struct device *dev);
-+
-+#endif /* __QCOM_SPMI_PMIC_H__ */
+++ /dev/null
-From 0c309f4e86c827cd5fd2eb0e36d5d1f19927380d Mon Sep 17 00:00:00 2001
-From: Caleb Connolly <caleb.connolly@linaro.org>
-Date: Fri, 29 Apr 2022 23:08:58 +0100
-Subject: [PATCH] mfd: qcom-spmi-pmic: read fab id on supported PMICs
-
-The PMI8998 and PM660 expose the fab_id, this is needed by drivers like
-the RRADC to calibrate ADC values.
-
-Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
-Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Acked-by: Lee Jones <lee.jones@linaro.org>
-Link: https://lore.kernel.org/r/20220429220904.137297-4-caleb.connolly@linaro.org
-Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
----
- drivers/mfd/qcom-spmi-pmic.c | 7 +++++++
- include/soc/qcom/qcom-spmi-pmic.h | 1 +
- 2 files changed, 8 insertions(+)
-
---- a/drivers/mfd/qcom-spmi-pmic.c
-+++ b/drivers/mfd/qcom-spmi-pmic.c
-@@ -19,6 +19,7 @@
- #define PMIC_REV4 0x103
- #define PMIC_TYPE 0x104
- #define PMIC_SUBTYPE 0x105
-+#define PMIC_FAB_ID 0x1f2
-
- #define PMIC_TYPE_VALUE 0x51
-
-@@ -157,6 +158,12 @@ static int pmic_spmi_load_revid(struct r
- if (ret < 0)
- return ret;
-
-+ if (pmic->subtype == PMI8998_SUBTYPE || pmic->subtype == PM660_SUBTYPE) {
-+ ret = regmap_read(map, PMIC_FAB_ID, &pmic->fab_id);
-+ if (ret < 0)
-+ return ret;
-+ }
-+
- /*
- * In early versions of PM8941 and PM8226, the major revision number
- * started incrementing from 0 (eg 0 = v1.0, 1 = v2.0).
---- a/include/soc/qcom/qcom-spmi-pmic.h
-+++ b/include/soc/qcom/qcom-spmi-pmic.h
-@@ -52,6 +52,7 @@ struct qcom_spmi_pmic {
- unsigned int major;
- unsigned int minor;
- unsigned int rev2;
-+ unsigned int fab_id;
- const char *name;
- };
-
+++ /dev/null
-From 46878413ba10170aaa9b7c797816e928a11923e3 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Fri, 19 Aug 2022 00:18:12 +0200
-Subject: [PATCH] mfd: qcom-spmi-pmic: Add support for PMP8074
-
-Add support for PMP8074 PMIC which is a companion PMIC for the Qualcomm
-IPQ8074 SoC-s.
-
-It shares the same subtype identifier as PM8901.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Signed-off-by: Lee Jones <lee@kernel.org>
-Link: https://lore.kernel.org/r/20220818221815.346233-2-robimarko@gmail.com
----
- drivers/mfd/qcom-spmi-pmic.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/mfd/qcom-spmi-pmic.c
-+++ b/drivers/mfd/qcom-spmi-pmic.c
-@@ -60,6 +60,7 @@ static const struct of_device_id pmic_sp
- { .compatible = "qcom,pmi8994", .data = N_USIDS(2) },
- { .compatible = "qcom,pmi8998", .data = N_USIDS(2) },
- { .compatible = "qcom,pmk8002", .data = N_USIDS(2) },
-+ { .compatible = "qcom,pmp8074", .data = N_USIDS(2) },
- { .compatible = "qcom,smb2351", .data = N_USIDS(2) },
- { .compatible = "qcom,spmi-pmic", .data = N_USIDS(1) },
- { }
+++ /dev/null
-From dedc087d43013ab6043dd1da4cd585dd4242a6bb Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Mon, 4 Jul 2022 23:23:54 +0200
-Subject: [PATCH] regulator: qcom_spmi: add support for HT_P150
-
-HT_P150 is a LDO PMOS regulator based on LV P150 using HFS430 layout
-found in PMP8074 and PMS405 PMIC-s.
-
-Both PMP8074 and PMS405 define the programmable range as 1.616V to 3.304V
-but the actual MAX output voltage depends on the exact LDO in each of
-the PMIC-s.
-
-It has a max current of 150mA, voltage step of 8mV.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Link: https://lore.kernel.org/r/20220704212402.1715182-4-robimarko@gmail.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- drivers/regulator/qcom_spmi-regulator.c | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/drivers/regulator/qcom_spmi-regulator.c
-+++ b/drivers/regulator/qcom_spmi-regulator.c
-@@ -164,6 +164,7 @@ enum spmi_regulator_subtype {
- SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL3 = 0x0f,
- SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL4 = 0x10,
- SPMI_REGULATOR_SUBTYPE_HFS430 = 0x0a,
-+ SPMI_REGULATOR_SUBTYPE_HT_P150 = 0x35,
- };
-
- enum spmi_common_regulator_registers {
-@@ -544,6 +545,10 @@ static struct spmi_voltage_range hfs430_
- SPMI_VOLTAGE_RANGE(0, 320000, 320000, 2040000, 2040000, 8000),
- };
-
-+static struct spmi_voltage_range ht_p150_ranges[] = {
-+ SPMI_VOLTAGE_RANGE(0, 1616000, 1616000, 3304000, 3304000, 8000),
-+};
-+
- static DEFINE_SPMI_SET_POINTS(pldo);
- static DEFINE_SPMI_SET_POINTS(nldo1);
- static DEFINE_SPMI_SET_POINTS(nldo2);
-@@ -564,6 +569,7 @@ static DEFINE_SPMI_SET_POINTS(nldo660);
- static DEFINE_SPMI_SET_POINTS(ht_lvpldo);
- static DEFINE_SPMI_SET_POINTS(ht_nldo);
- static DEFINE_SPMI_SET_POINTS(hfs430);
-+static DEFINE_SPMI_SET_POINTS(ht_p150);
-
- static inline int spmi_vreg_read(struct spmi_regulator *vreg, u16 addr, u8 *buf,
- int len)
-@@ -1458,6 +1464,7 @@ static const struct regulator_ops spmi_h
-
- static const struct spmi_regulator_mapping supported_regulators[] = {
- /* type subtype dig_min dig_max ltype ops setpoints hpm_min */
-+ SPMI_VREG(LDO, HT_P150, 0, INF, HFS430, hfs430, ht_p150, 10000),
- SPMI_VREG(BUCK, GP_CTL, 0, INF, SMPS, smps, smps, 100000),
- SPMI_VREG(BUCK, HFS430, 0, INF, HFS430, hfs430, hfs430, 10000),
- SPMI_VREG(LDO, N300, 0, INF, LDO, ldo, nldo1, 10000),
+++ /dev/null
-From 14789f38e03c42857613b69ff0f032e03653b246 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Mon, 4 Jul 2022 23:23:55 +0200
-Subject: [PATCH] regulator: qcom_spmi: add support for HT_P600
-
-HT_P600 is a LDO PMOS regulator based on LV P600 using HFS430 layout
-found in PMP8074 and PMS405 PMIC-s.
-
-Both PMP8074 and PMS405 define the programmable range as 1.704 to 1.896V
-but the actual MAX output voltage depends on the exact LDO in each of
-the PMIC-s.
-Their usual voltage that they are used is 1.8V.
-
-It has a max current of 600mA, voltage step of 8mV.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Link: https://lore.kernel.org/r/20220704212402.1715182-5-robimarko@gmail.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- drivers/regulator/qcom_spmi-regulator.c | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/drivers/regulator/qcom_spmi-regulator.c
-+++ b/drivers/regulator/qcom_spmi-regulator.c
-@@ -165,6 +165,7 @@ enum spmi_regulator_subtype {
- SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL4 = 0x10,
- SPMI_REGULATOR_SUBTYPE_HFS430 = 0x0a,
- SPMI_REGULATOR_SUBTYPE_HT_P150 = 0x35,
-+ SPMI_REGULATOR_SUBTYPE_HT_P600 = 0x3d,
- };
-
- enum spmi_common_regulator_registers {
-@@ -549,6 +550,10 @@ static struct spmi_voltage_range ht_p150
- SPMI_VOLTAGE_RANGE(0, 1616000, 1616000, 3304000, 3304000, 8000),
- };
-
-+static struct spmi_voltage_range ht_p600_ranges[] = {
-+ SPMI_VOLTAGE_RANGE(0, 1704000, 1704000, 1896000, 1896000, 8000),
-+};
-+
- static DEFINE_SPMI_SET_POINTS(pldo);
- static DEFINE_SPMI_SET_POINTS(nldo1);
- static DEFINE_SPMI_SET_POINTS(nldo2);
-@@ -570,6 +575,7 @@ static DEFINE_SPMI_SET_POINTS(ht_lvpldo)
- static DEFINE_SPMI_SET_POINTS(ht_nldo);
- static DEFINE_SPMI_SET_POINTS(hfs430);
- static DEFINE_SPMI_SET_POINTS(ht_p150);
-+static DEFINE_SPMI_SET_POINTS(ht_p600);
-
- static inline int spmi_vreg_read(struct spmi_regulator *vreg, u16 addr, u8 *buf,
- int len)
-@@ -1464,6 +1470,7 @@ static const struct regulator_ops spmi_h
-
- static const struct spmi_regulator_mapping supported_regulators[] = {
- /* type subtype dig_min dig_max ltype ops setpoints hpm_min */
-+ SPMI_VREG(LDO, HT_P600, 0, INF, HFS430, hfs430, ht_p600, 10000),
- SPMI_VREG(LDO, HT_P150, 0, INF, HFS430, hfs430, ht_p150, 10000),
- SPMI_VREG(BUCK, GP_CTL, 0, INF, SMPS, smps, smps, 100000),
- SPMI_VREG(BUCK, HFS430, 0, INF, HFS430, hfs430, hfs430, 10000),
+++ /dev/null
-From 3e3da8da25f81fa3f0f3a37f60d10b17d1166864 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Mon, 4 Jul 2022 23:23:57 +0200
-Subject: [PATCH] regulator: qcom_spmi: add support for PMP8074 regulators
-
-PMP8074 is a companion PMIC for the Qualcomm IPQ8074 WiSoC-s.
-
-It features 5 HF-SMPS and 13 LDO regulators.
-
-HF-SMPS regulators are Buck HFS430 regulators.
-L1, L2 and L3 are HT_N1200_ST subtype LDO regulators.
-L4 is HT_N300_ST subtype LDO regulator.
-L5 and L6 are HT_P600 subtype LDO regulators.
-L7, L11, L12 and L13 are HT_P150 subtype LDO regulators.
-L10 is HT_P50 subtype LDO regulator.
-
-This commit adds support for all of the buck regulators and LDO-s except
-for L10 as I dont have documentation on its output voltage range.
-
-S3 is the CPU cluster voltage supply, S4 supplies the UBI32 NPU cores
-and L11 is the SDIO/eMMC I/O voltage regulator required for high speeds.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Link: https://lore.kernel.org/r/20220704212402.1715182-7-robimarko@gmail.com
-Signed-off-by: Mark Brown <broonie@kernel.org>
----
- drivers/regulator/qcom_spmi-regulator.c | 23 +++++++++++++++++++++++
- 1 file changed, 23 insertions(+)
-
---- a/drivers/regulator/qcom_spmi-regulator.c
-+++ b/drivers/regulator/qcom_spmi-regulator.c
-@@ -2101,6 +2101,28 @@ static const struct spmi_regulator_data
- { }
- };
-
-+static const struct spmi_regulator_data pmp8074_regulators[] = {
-+ { "s1", 0x1400, "vdd_s1"},
-+ { "s2", 0x1700, "vdd_s2"},
-+ { "s3", 0x1a00, "vdd_s3"},
-+ { "s4", 0x1d00, "vdd_s4"},
-+ { "s5", 0x2000, "vdd_s5"},
-+ { "l1", 0x4000, "vdd_l1_l2"},
-+ { "l2", 0x4100, "vdd_l1_l2"},
-+ { "l3", 0x4200, "vdd_l3_l8"},
-+ { "l4", 0x4300, "vdd_l4"},
-+ { "l5", 0x4400, "vdd_l5_l6_l15"},
-+ { "l6", 0x4500, "vdd_l5_l6_l15"},
-+ { "l7", 0x4600, "vdd_l7"},
-+ { "l8", 0x4700, "vdd_l3_l8"},
-+ { "l9", 0x4800, "vdd_l9"},
-+ /* l10 is currently unsupported HT_P50 */
-+ { "l11", 0x4a00, "vdd_l10_l11_l12_l13"},
-+ { "l12", 0x4b00, "vdd_l10_l11_l12_l13"},
-+ { "l13", 0x4c00, "vdd_l10_l11_l12_l13"},
-+ { }
-+};
-+
- static const struct spmi_regulator_data pms405_regulators[] = {
- { "s3", 0x1a00, "vdd_s3"},
- { }
-@@ -2117,6 +2139,7 @@ static const struct of_device_id qcom_sp
- { .compatible = "qcom,pmi8994-regulators", .data = &pmi8994_regulators },
- { .compatible = "qcom,pm660-regulators", .data = &pm660_regulators },
- { .compatible = "qcom,pm660l-regulators", .data = &pm660l_regulators },
-+ { .compatible = "qcom,pmp8074-regulators", .data = &pmp8074_regulators },
- { .compatible = "qcom,pms405-regulators", .data = &pms405_regulators },
- { }
- };
+++ /dev/null
-From 204cd3516f59eb7040b814429187e674f49ba065 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Mon, 11 Jul 2022 22:34:05 +0200
-Subject: [PATCH] pinctrl: qcom-pmic-gpio: add support for PMP8074
-
-PMP8074 has 12 GPIO-s with holes on GPIO1 and GPIO12.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Link: https://lore.kernel.org/r/20220711203408.2949888-4-robimarko@gmail.com
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
-+++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
-@@ -1167,6 +1167,8 @@ static const struct of_device_id pmic_gp
- { .compatible = "qcom,pmi8998-gpio", .data = (void *) 14 },
- { .compatible = "qcom,pmk8350-gpio", .data = (void *) 4 },
- { .compatible = "qcom,pmm8155au-gpio", .data = (void *) 10 },
-+ /* pmp8074 has 12 GPIOs with holes on 1 and 12 */
-+ { .compatible = "qcom,pmp8074-gpio", .data = (void *) 12 },
- { .compatible = "qcom,pmr735a-gpio", .data = (void *) 4 },
- { .compatible = "qcom,pmr735b-gpio", .data = (void *) 4 },
- /* pms405 has 12 GPIOs with holes on 1, 9, and 10 */
+++ /dev/null
-From 41a02abb863edca0de0373bc3deaf0639b18c589 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Fri, 19 Aug 2022 00:18:13 +0200
-Subject: [PATCH] iio: adc: qcom-spmi-adc5: add ADC5_VREF_VADC to rev2 ADC5
-
-Add support for ADC5_VREF_VADC channel to rev2 ADC5 channel list.
-This channel measures the VADC reference LDO output.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Link: https://lore.kernel.org/r/20220818221815.346233-3-robimarko@gmail.com
-Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
----
- drivers/iio/adc/qcom-spmi-adc5.c | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/drivers/iio/adc/qcom-spmi-adc5.c
-+++ b/drivers/iio/adc/qcom-spmi-adc5.c
-@@ -589,6 +589,8 @@ static const struct adc5_channels adc5_c
- SCALE_HW_CALIB_DEFAULT)
- [ADC5_1P25VREF] = ADC5_CHAN_VOLT("vref_1p25", 0,
- SCALE_HW_CALIB_DEFAULT)
-+ [ADC5_VREF_VADC] = ADC5_CHAN_VOLT("vref_vadc", 0,
-+ SCALE_HW_CALIB_DEFAULT)
- [ADC5_VPH_PWR] = ADC5_CHAN_VOLT("vph_pwr", 1,
- SCALE_HW_CALIB_DEFAULT)
- [ADC5_VBAT_SNS] = ADC5_CHAN_VOLT("vbat_sns", 1,
+++ /dev/null
-From a212eb94fc9f72a126df651c5d7898feaea29526 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Sun, 5 Sep 2021 19:11:31 +0200
-Subject: [PATCH] soc: qcom: socinfo: Add IPQ8074 family ID-s
-
-IPQ8074 family SoC ID-s are missing, so lets add them based on
-the downstream driver.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Reviewed-by: Kathiravan T <kathirav@codeaurora.org>
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Link: https://lore.kernel.org/r/20210905171131.660885-1-robimarko@gmail.com
----
- drivers/soc/qcom/socinfo.c | 12 ++++++++++++
- 1 file changed, 12 insertions(+)
-
---- a/drivers/soc/qcom/socinfo.c
-+++ b/drivers/soc/qcom/socinfo.c
-@@ -281,19 +281,31 @@ static const struct soc_id soc_id[] = {
- { 319, "APQ8098" },
- { 321, "SDM845" },
- { 322, "MDM9206" },
-+ { 323, "IPQ8074" },
- { 324, "SDA660" },
- { 325, "SDM658" },
- { 326, "SDA658" },
- { 327, "SDA630" },
- { 338, "SDM450" },
- { 341, "SDA845" },
-+ { 342, "IPQ8072" },
-+ { 343, "IPQ8076" },
-+ { 344, "IPQ8078" },
- { 345, "SDM636" },
- { 346, "SDA636" },
- { 349, "SDM632" },
- { 350, "SDA632" },
- { 351, "SDA450" },
- { 356, "SM8250" },
-+ { 375, "IPQ8070" },
-+ { 376, "IPQ8071" },
-+ { 389, "IPQ8072A" },
-+ { 390, "IPQ8074A" },
-+ { 391, "IPQ8076A" },
-+ { 392, "IPQ8078A" },
- { 394, "SM6125" },
-+ { 395, "IPQ8070A" },
-+ { 396, "IPQ8071A" },
- { 402, "IPQ6018" },
- { 403, "IPQ6028" },
- { 421, "IPQ6000" },
+++ /dev/null
-From 2b0fe9137aa32d7fc367bf3a1cef4fa97ece6d58 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Tue, 23 Aug 2022 22:43:51 +0200
-Subject: [PATCH] phy: qcom-qmp-pcie: make pipe clock rate configurable
-
-IPQ8074 Gen3 PCIe PHY uses 250MHz as the pipe clock rate instead of 125MHz
-like every other PCIe QMP PHY does, so make it configurable as part of the
-qmp_phy_cfg.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Link: https://lore.kernel.org/r/20220621195512.1760362-1-robimarko@gmail.com
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
----
- drivers/phy/qualcomm/phy-qcom-qmp.c | 14 ++++++++++++--
- 1 file changed, 12 insertions(+), 2 deletions(-)
-
---- a/drivers/phy/qualcomm/phy-qcom-qmp.c
-+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
-@@ -2842,6 +2842,9 @@ struct qmp_phy_cfg {
- /* true, if PHY has secondary tx/rx lanes to be configured */
- bool is_dual_lane_phy;
-
-+ /* QMP PHY pipe clock interface rate */
-+ unsigned long pipe_clock_rate;
-+
- /* true, if PCS block has no separate SW_RESET register */
- bool no_pcs_sw_reset;
- };
-@@ -5139,8 +5142,15 @@ static int phy_pipe_clk_register(struct
-
- init.ops = &clk_fixed_rate_ops;
-
-- /* controllers using QMP phys use 125MHz pipe clock interface */
-- fixed->fixed_rate = 125000000;
-+ /*
-+ * Controllers using QMP PHY-s use 125MHz pipe clock interface
-+ * unless other frequency is specified in the PHY config.
-+ */
-+ if (qmp->phys[0]->cfg->pipe_clock_rate)
-+ fixed->fixed_rate = qmp->phys[0]->cfg->pipe_clock_rate;
-+ else
-+ fixed->fixed_rate = 125000000;
-+
- fixed->hw.init = &init;
-
- ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
+++ /dev/null
-From 23bd21d8c05109b57aa9508e88fbdbc2b6d33de7 Mon Sep 17 00:00:00 2001
-From: Robert Marko <robimarko@gmail.com>
-Date: Tue, 23 Aug 2022 22:47:40 +0200
-Subject: [PATCH] phy: qcom-qmp-pcie: add IPQ8074 PCIe Gen3 QMP PHY support
-
-IPQ8074 has 2 different single lane PCIe PHY-s, one Gen2 and one Gen3.
-Gen2 one is already supported, so add the support for the Gen3 one.
-It uses the same register layout as IPQ6018.
-
-Signed-off-by: Robert Marko <robimarko@gmail.com>
-Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
-Link: https://lore.kernel.org/r/20220621195512.1760362-3-robimarko@gmail.com
-Signed-off-by: Vinod Koul <vkoul@kernel.org>
----
- drivers/phy/qualcomm/phy-qcom-qmp.c | 160 ++++++++++++++++++++++++++++
- 1 file changed, 160 insertions(+)
-
---- a/drivers/phy/qualcomm/phy-qcom-qmp.c
-+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
-@@ -812,6 +812,133 @@ static const struct qmp_phy_init_tbl ipq
- QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
- };
-
-+static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_serdes_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x82),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0x355),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0x35555),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x1a),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0x1a0a),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0xb),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0xa),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0xa),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x1),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x68),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x2),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x2aa),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x2aaab),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x34),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0x3414),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x0b),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x0),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28),
-+ QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_tx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
-+ QMP_PHY_INIT_CFG(QSERDES_TX0_HIGHZ_DRVR_EN, 0x10),
-+ QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_rx_tbl[] = {
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0xe),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x4),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x2),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
-+ QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
-+};
-+
-+static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_tbl[] = {
-+ QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL2, 0x83),
-+ QMP_PHY_INIT_CFG(PCS_COM_FLL_CNT_VAL_L, 0x9),
-+ QMP_PHY_INIT_CFG(PCS_COM_FLL_CNT_VAL_H_TOL, 0x42),
-+ QMP_PHY_INIT_CFG(PCS_COM_FLL_MAN_CODE, 0x40),
-+ QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x0),
-+ QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x1),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x0),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG2, 0xb),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_CONFIG2, 0x52),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x6),
-+ QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
-+ QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
-+ QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
-+ QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
-+ QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
-+};
-+
- static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
- QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
- QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
-@@ -3168,6 +3295,36 @@ static const struct qmp_phy_cfg ipq8074_
- .pwrdn_delay_max = 1005, /* us */
- };
-
-+static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = {
-+ .type = PHY_TYPE_PCIE,
-+ .nlanes = 1,
-+
-+ .serdes_tbl = ipq8074_pcie_gen3_serdes_tbl,
-+ .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl),
-+ .tx_tbl = ipq8074_pcie_gen3_tx_tbl,
-+ .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl),
-+ .rx_tbl = ipq8074_pcie_gen3_rx_tbl,
-+ .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_rx_tbl),
-+ .pcs_tbl = ipq8074_pcie_gen3_pcs_tbl,
-+ .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_tbl),
-+ .clk_list = ipq8074_pciephy_clk_l,
-+ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
-+ .reset_list = ipq8074_pciephy_reset_l,
-+ .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
-+ .vreg_list = NULL,
-+ .num_vregs = 0,
-+ .regs = ipq_pciephy_gen3_regs_layout,
-+
-+ .start_ctrl = SERDES_START | PCS_START,
-+ .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
-+
-+ .has_pwrdn_delay = true,
-+ .pwrdn_delay_min = 995, /* us */
-+ .pwrdn_delay_max = 1005, /* us */
-+
-+ .pipe_clock_rate = 250000000,
-+};
-+
- static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
- .type = PHY_TYPE_PCIE,
- .nlanes = 1,
-@@ -5571,6 +5728,9 @@ static const struct of_device_id qcom_qm
- .compatible = "qcom,ipq8074-qmp-pcie-phy",
- .data = &ipq8074_pciephy_cfg,
- }, {
-+ .compatible = "qcom,ipq8074-qmp-gen3-pcie-phy",
-+ .data = &ipq8074_pciephy_gen3_cfg,
-+ }, {
- .compatible = "qcom,ipq6018-qmp-pcie-phy",
- .data = &ipq6018_pciephy_cfg,
- }, {
+++ /dev/null
-From 8df9fefd1d04f6f97f6015d7347104f69e6ea580 Mon Sep 17 00:00:00 2001
-From: Baruch Siach <baruch.siach@siklu.com>
-Date: Tue, 21 Jun 2022 11:54:52 +0300
-Subject: [PATCH] PCI: dwc: Move GEN3_RELATED DBI definitions to common header
-
-These are common dwc macros that will be used for other platforms.
-
-Link: https://lore.kernel.org/r/1c2d5a7a139be81fa15f356b2380163dbdebdc09.1655799816.git.baruch@tkos.co.il
-Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
-Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-Reviewed-by: Rob Herring <robh@kernel.org>
----
- drivers/pci/controller/dwc/pcie-designware.h | 6 ++++++
- drivers/pci/controller/dwc/pcie-tegra194.c | 6 ------
- 2 files changed, 6 insertions(+), 6 deletions(-)
-
---- a/drivers/pci/controller/dwc/pcie-designware.h
-+++ b/drivers/pci/controller/dwc/pcie-designware.h
-@@ -74,6 +74,12 @@
- #define PCIE_MSI_INTR0_MASK 0x82C
- #define PCIE_MSI_INTR0_STATUS 0x830
-
-+#define GEN3_RELATED_OFF 0x890
-+#define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0)
-+#define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16)
-+#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24
-+#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24)
-+
- #define PCIE_PORT_MULTI_LANE_CTRL 0x8C0
- #define PORT_MLTI_UPCFG_SUPPORT BIT(7)
-
---- a/drivers/pci/controller/dwc/pcie-tegra194.c
-+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
-@@ -193,12 +193,6 @@
- #define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK GENMASK(23, 8)
- #define GEN3_EQ_CONTROL_OFF_FB_MODE_MASK GENMASK(3, 0)
-
--#define GEN3_RELATED_OFF 0x890
--#define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0)
--#define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16)
--#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24
--#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24)
--
- #define PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT 0x8D0
- #define AMBA_ERROR_RESPONSE_CRS_SHIFT 3
- #define AMBA_ERROR_RESPONSE_CRS_MASK GENMASK(1, 0)
+++ /dev/null
-From d568739f1c21e1768a887ff85611769f782eb64f Mon Sep 17 00:00:00 2001
-From: Baruch Siach <baruch.siach@siklu.com>
-Date: Tue, 21 Jun 2022 11:54:53 +0300
-Subject: [PATCH] PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_*
-
-The PCIE_CAP_LINK1_VAL macro actually defines slot capabilities. Use
-PCI_EXP_SLTCAP_* macros to spell its value, and rename it to better
-describe its meaning.
-
-Link: https://lore.kernel.org/r/3025d5e1d8da64798db6958f9780c4763fbcac47.1655799816.git.baruch@tkos.co.il
-Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
-Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-Reviewed-by: Rob Herring <robh@kernel.org>
-Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
----
- drivers/pci/controller/dwc/pcie-qcom.c | 17 +++++++++++++++--
- 1 file changed, 15 insertions(+), 2 deletions(-)
-
---- a/drivers/pci/controller/dwc/pcie-qcom.c
-+++ b/drivers/pci/controller/dwc/pcie-qcom.c
-@@ -69,7 +69,20 @@
- #define PCIE20_AXI_MSTR_RESP_COMP_CTRL1 0x81c
- #define CFG_BRIDGE_SB_INIT BIT(0)
-
--#define PCIE_CAP_LINK1_VAL 0x2FD7F
-+#define PCIE_CAP_SLOT_POWER_LIMIT_VAL FIELD_PREP(PCI_EXP_SLTCAP_SPLV, \
-+ 250)
-+#define PCIE_CAP_SLOT_POWER_LIMIT_SCALE FIELD_PREP(PCI_EXP_SLTCAP_SPLS, \
-+ 1)
-+#define PCIE_CAP_SLOT_VAL (PCI_EXP_SLTCAP_ABP | \
-+ PCI_EXP_SLTCAP_PCP | \
-+ PCI_EXP_SLTCAP_MRLSP | \
-+ PCI_EXP_SLTCAP_AIP | \
-+ PCI_EXP_SLTCAP_PIP | \
-+ PCI_EXP_SLTCAP_HPS | \
-+ PCI_EXP_SLTCAP_HPC | \
-+ PCI_EXP_SLTCAP_EIP | \
-+ PCIE_CAP_SLOT_POWER_LIMIT_VAL | \
-+ PCIE_CAP_SLOT_POWER_LIMIT_SCALE)
-
- #define PCIE20_PARF_Q2A_FLUSH 0x1AC
-
-@@ -1125,7 +1138,7 @@ static int qcom_pcie_post_init_2_3_3(str
-
- writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND);
- writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG);
-- writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
-+ writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
-
- val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
- val &= ~PCI_EXP_LNKCAP_ASPMS;
+++ /dev/null
-From 180ce25d5c3ccff206f084b7ab350778641d1b1c Mon Sep 17 00:00:00 2001
-From: Prasad Malisetty <pmaliset@codeaurora.org>
-Date: Thu, 7 Oct 2021 23:18:42 +0530
-Subject: [PATCH] PCI: qcom: Replace ops with struct pcie_cfg in pcie match
- data
-
-Add struct qcom_pcie_cfg as match data for all platforms. Assign
-appropriate platform ops into struct qcom_pcie_cfg and read using
-of_device_get_match_data() in qcom_pcie_probe().
-
-Link: https://lore.kernel.org/r/1633628923-25047-5-git-send-email-pmaliset@codeaurora.org
-Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org>
-Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
-Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-Reviewed-by: Stephen Boyd <swboyd@chromium.org>
----
- drivers/pci/controller/dwc/pcie-qcom.c | 66 +++++++++++++++++++++-----
- 1 file changed, 55 insertions(+), 11 deletions(-)
-
---- a/drivers/pci/controller/dwc/pcie-qcom.c
-+++ b/drivers/pci/controller/dwc/pcie-qcom.c
-@@ -202,6 +202,10 @@ struct qcom_pcie_ops {
- int (*config_sid)(struct qcom_pcie *pcie);
- };
-
-+struct qcom_pcie_cfg {
-+ const struct qcom_pcie_ops *ops;
-+};
-+
- struct qcom_pcie {
- struct dw_pcie *pci;
- void __iomem *parf; /* DT parf */
-@@ -1467,6 +1471,38 @@ static const struct qcom_pcie_ops ops_1_
- .config_sid = qcom_pcie_config_sid_sm8250,
- };
-
-+static const struct qcom_pcie_cfg apq8084_cfg = {
-+ .ops = &ops_1_0_0,
-+};
-+
-+static const struct qcom_pcie_cfg ipq8064_cfg = {
-+ .ops = &ops_2_1_0,
-+};
-+
-+static const struct qcom_pcie_cfg msm8996_cfg = {
-+ .ops = &ops_2_3_2,
-+};
-+
-+static const struct qcom_pcie_cfg ipq8074_cfg = {
-+ .ops = &ops_2_3_3,
-+};
-+
-+static const struct qcom_pcie_cfg ipq4019_cfg = {
-+ .ops = &ops_2_4_0,
-+};
-+
-+static const struct qcom_pcie_cfg sdm845_cfg = {
-+ .ops = &ops_2_7_0,
-+};
-+
-+static const struct qcom_pcie_cfg sm8250_cfg = {
-+ .ops = &ops_1_9_0,
-+};
-+
-+static const struct qcom_pcie_cfg sc7280_cfg = {
-+ .ops = &ops_1_9_0,
-+};
-+
- static const struct dw_pcie_ops dw_pcie_ops = {
- .link_up = qcom_pcie_link_up,
- .start_link = qcom_pcie_start_link,
-@@ -1478,6 +1514,7 @@ static int qcom_pcie_probe(struct platfo
- struct pcie_port *pp;
- struct dw_pcie *pci;
- struct qcom_pcie *pcie;
-+ const struct qcom_pcie_cfg *pcie_cfg;
- int ret;
-
- pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
-@@ -1499,7 +1536,13 @@ static int qcom_pcie_probe(struct platfo
-
- pcie->pci = pci;
-
-- pcie->ops = of_device_get_match_data(dev);
-+ pcie_cfg = of_device_get_match_data(dev);
-+ if (!pcie_cfg || !pcie_cfg->ops) {
-+ dev_err(dev, "Invalid platform data\n");
-+ return -EINVAL;
-+ }
-+
-+ pcie->ops = pcie_cfg->ops;
-
- pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH);
- if (IS_ERR(pcie->reset)) {
-@@ -1555,16 +1598,17 @@ err_pm_runtime_put:
- }
-
- static const struct of_device_id qcom_pcie_match[] = {
-- { .compatible = "qcom,pcie-apq8084", .data = &ops_1_0_0 },
-- { .compatible = "qcom,pcie-ipq8064", .data = &ops_2_1_0 },
-- { .compatible = "qcom,pcie-ipq8064-v2", .data = &ops_2_1_0 },
-- { .compatible = "qcom,pcie-apq8064", .data = &ops_2_1_0 },
-- { .compatible = "qcom,pcie-msm8996", .data = &ops_2_3_2 },
-- { .compatible = "qcom,pcie-ipq8074", .data = &ops_2_3_3 },
-- { .compatible = "qcom,pcie-ipq4019", .data = &ops_2_4_0 },
-- { .compatible = "qcom,pcie-qcs404", .data = &ops_2_4_0 },
-- { .compatible = "qcom,pcie-sdm845", .data = &ops_2_7_0 },
-- { .compatible = "qcom,pcie-sm8250", .data = &ops_1_9_0 },
-+ { .compatible = "qcom,pcie-apq8084", .data = &apq8084_cfg },
-+ { .compatible = "qcom,pcie-ipq8064", .data = &ipq8064_cfg },
-+ { .compatible = "qcom,pcie-ipq8064-v2", .data = &ipq8064_cfg },
-+ { .compatible = "qcom,pcie-apq8064", .data = &ipq8064_cfg },
-+ { .compatible = "qcom,pcie-msm8996", .data = &msm8996_cfg },
-+ { .compatible = "qcom,pcie-ipq8074", .data = &ipq8074_cfg },
-+ { .compatible = "qcom,pcie-ipq4019", .data = &ipq4019_cfg },
-+ { .compatible = "qcom,pcie-qcs404", .data = &ipq4019_cfg },
-+ { .compatible = "qcom,pcie-sdm845", .data = &sdm845_cfg },
-+ { .compatible = "qcom,pcie-sm8250", .data = &sm8250_cfg },
-+ { .compatible = "qcom,pcie-sc7280", .data = &sc7280_cfg },
- { }
- };
-
+++ /dev/null
-From a7d96ca20847ade9f29cff4521f43b8ae968b3df Mon Sep 17 00:00:00 2001
-From: Selvam Sathappan Periakaruppan <quic_speriaka@quicinc.com>
-Date: Tue, 21 Jun 2022 11:54:54 +0300
-Subject: [PATCH] PCI: qcom: Add IPQ60xx support
-
-IPQ60xx series of SoCs have one port of PCIe gen 3. Add support for that
-platform.
-
-The code is based on downstream[1] Codeaurora kernel v5.4 (branch
-win.linuxopenwrt.2.0).
-
-Split out the DBI registers access part from .init into .post_init. DBI
-registers are only accessible after phy_power_on().
-
-[1] https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-ipq-5.4/
-
-Link: https://lore.kernel.org/r/f7f848653c99abbf9a0f877949a44e52329543ae.1655799816.git.baruch@tkos.co.il
-Tested-by: Robert Marko <robert.marko@sartura.hr>
-Signed-off-by: Selvam Sathappan Periakaruppan <quic_speriaka@quicinc.com>
-Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
-Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-Reviewed-by: Rob Herring <robh@kernel.org>
-Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
-Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
----
- drivers/pci/controller/dwc/pcie-designware.h | 1 +
- drivers/pci/controller/dwc/pcie-qcom.c | 130 +++++++++++++++++++
- 2 files changed, 131 insertions(+)
-
---- a/drivers/pci/controller/dwc/pcie-designware.h
-+++ b/drivers/pci/controller/dwc/pcie-designware.h
-@@ -76,6 +76,7 @@
-
- #define GEN3_RELATED_OFF 0x890
- #define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0)
-+#define GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS BIT(13)
- #define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16)
- #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24
- #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24)
---- a/drivers/pci/controller/dwc/pcie-qcom.c
-+++ b/drivers/pci/controller/dwc/pcie-qcom.c
-@@ -52,6 +52,10 @@
- #define PCIE20_PARF_DBI_BASE_ADDR 0x168
- #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C
- #define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174
-+#define AHB_CLK_EN BIT(0)
-+#define MSTR_AXI_CLK_EN BIT(1)
-+#define BYPASS BIT(4)
-+
- #define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x178
- #define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1A8
- #define PCIE20_PARF_LTSSM 0x1B0
-@@ -181,6 +185,11 @@ struct qcom_pcie_resources_2_7_0 {
- struct clk *pipe_clk;
- };
-
-+struct qcom_pcie_resources_2_9_0 {
-+ struct clk_bulk_data clks[5];
-+ struct reset_control *rst;
-+};
-+
- union qcom_pcie_resources {
- struct qcom_pcie_resources_1_0_0 v1_0_0;
- struct qcom_pcie_resources_2_1_0 v2_1_0;
-@@ -188,6 +197,7 @@ union qcom_pcie_resources {
- struct qcom_pcie_resources_2_3_3 v2_3_3;
- struct qcom_pcie_resources_2_4_0 v2_4_0;
- struct qcom_pcie_resources_2_7_0 v2_7_0;
-+ struct qcom_pcie_resources_2_9_0 v2_9_0;
- };
-
- struct qcom_pcie;
-@@ -1280,6 +1290,112 @@ static void qcom_pcie_post_deinit_2_7_0(
- clk_disable_unprepare(res->pipe_clk);
- }
-
-+static int qcom_pcie_get_resources_2_9_0(struct qcom_pcie *pcie)
-+{
-+ struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
-+ struct dw_pcie *pci = pcie->pci;
-+ struct device *dev = pci->dev;
-+ int ret;
-+
-+ res->clks[0].id = "iface";
-+ res->clks[1].id = "axi_m";
-+ res->clks[2].id = "axi_s";
-+ res->clks[3].id = "axi_bridge";
-+ res->clks[4].id = "rchng";
-+
-+ ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks);
-+ if (ret < 0)
-+ return ret;
-+
-+ res->rst = devm_reset_control_array_get_exclusive(dev);
-+ if (IS_ERR(res->rst))
-+ return PTR_ERR(res->rst);
-+
-+ return 0;
-+}
-+
-+static void qcom_pcie_deinit_2_9_0(struct qcom_pcie *pcie)
-+{
-+ struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
-+
-+ clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
-+}
-+
-+static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie)
-+{
-+ struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
-+ struct device *dev = pcie->pci->dev;
-+ int ret;
-+
-+ ret = reset_control_assert(res->rst);
-+ if (ret) {
-+ dev_err(dev, "reset assert failed (%d)\n", ret);
-+ return ret;
-+ }
-+
-+ /*
-+ * Delay periods before and after reset deassert are working values
-+ * from downstream Codeaurora kernel
-+ */
-+ usleep_range(2000, 2500);
-+
-+ ret = reset_control_deassert(res->rst);
-+ if (ret) {
-+ dev_err(dev, "reset deassert failed (%d)\n", ret);
-+ return ret;
-+ }
-+
-+ usleep_range(2000, 2500);
-+
-+ return clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
-+}
-+
-+static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie)
-+{
-+ struct dw_pcie *pci = pcie->pci;
-+ u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
-+ u32 val;
-+ int i;
-+
-+ writel(SLV_ADDR_SPACE_SZ,
-+ pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE);
-+
-+ val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
-+ val &= ~BIT(0);
-+ writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
-+
-+ writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
-+
-+ writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE);
-+ writel(BYPASS | MSTR_AXI_CLK_EN | AHB_CLK_EN,
-+ pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
-+ writel(GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS |
-+ GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL,
-+ pci->dbi_base + GEN3_RELATED_OFF);
-+
-+ writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS |
-+ SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS |
-+ AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS,
-+ pcie->parf + PCIE20_PARF_SYS_CTRL);
-+
-+ writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH);
-+
-+ dw_pcie_dbi_ro_wr_en(pci);
-+ writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
-+
-+ val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
-+ val &= ~PCI_EXP_LNKCAP_ASPMS;
-+ writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP);
-+
-+ writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset +
-+ PCI_EXP_DEVCTL2);
-+
-+ for (i = 0; i < 256; i++)
-+ writel(0, pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N + (4 * i));
-+
-+ return 0;
-+}
-+
- static int qcom_pcie_link_up(struct dw_pcie *pci)
- {
- u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
-@@ -1471,6 +1587,15 @@ static const struct qcom_pcie_ops ops_1_
- .config_sid = qcom_pcie_config_sid_sm8250,
- };
-
-+/* Qcom IP rev.: 2.9.0 Synopsys IP rev.: 5.00a */
-+static const struct qcom_pcie_ops ops_2_9_0 = {
-+ .get_resources = qcom_pcie_get_resources_2_9_0,
-+ .init = qcom_pcie_init_2_9_0,
-+ .post_init = qcom_pcie_post_init_2_9_0,
-+ .deinit = qcom_pcie_deinit_2_9_0,
-+ .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
-+};
-+
- static const struct qcom_pcie_cfg apq8084_cfg = {
- .ops = &ops_1_0_0,
- };
-@@ -1503,6 +1628,10 @@ static const struct qcom_pcie_cfg sc7280
- .ops = &ops_1_9_0,
- };
-
-+static const struct qcom_pcie_cfg ipq6018_cfg = {
-+ .ops = &ops_2_9_0,
-+};
-+
- static const struct dw_pcie_ops dw_pcie_ops = {
- .link_up = qcom_pcie_link_up,
- .start_link = qcom_pcie_start_link,
-@@ -1609,6 +1738,7 @@ static const struct of_device_id qcom_pc
- { .compatible = "qcom,pcie-sdm845", .data = &sdm845_cfg },
- { .compatible = "qcom,pcie-sm8250", .data = &sm8250_cfg },
- { .compatible = "qcom,pcie-sc7280", .data = &sc7280_cfg },
-+ { .compatible = "qcom,pcie-ipq6018", .data = &ipq6018_cfg },
- { }
- };
-
+++ /dev/null
-From e8e7ce92a49dc87f0d006cfbfe419b8e0b25476d Mon Sep 17 00:00:00 2001
-From: Bjorn Andersson <bjorn.andersson@linaro.org>
-Date: Tue, 26 Apr 2022 14:21:36 -0700
-Subject: [PATCH] clk: qcom: rcg2: Cache CFG register updates for parked RCGs
-
-As GDSCs are turned on and off some associated clocks are momentarily
-enabled for house keeping purposes. For this, and similar, purposes the
-"shared RCGs" will park the RCG on a source clock which is known to be
-available.
-When the RCG is parked, a safe clock source will be selected and
-committed, then the original source would be written back and upon enable
-the change back to the unparked source would be committed.
-
-But starting with SM8350 this fails, as the value in CFG is committed by
-the GDSC handshake and without a ticking parent the GDSC enablement will
-time out.
-
-This becomes a concrete problem if the runtime supended state of a
-device includes disabling such rcg's parent clock. As the device
-attempts to power up the domain again the rcg will fail to enable and
-hence the GDSC enablement will fail, preventing the device from
-returning from the suspended state.
-
-This can be seen in e.g. the display stack during probe on SM8350.
-
-To avoid this problem, the software needs to ensure that the RCG is
-configured to a active parent clock while it is disabled. This is done
-by caching the CFG register content while the shared RCG is parked on
-this safe source.
-
-Writes to M, N and D registers are committed as they are requested. New
-helpers for get_parent() and recalc_rate() are extracted from their
-previous implementations and __clk_rcg2_configure() is modified to allow
-it to operate on the cached value.
-
-Fixes: 7ef6f11887bd ("clk: qcom: Configure the RCGs to a safe source as needed")
-Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
-Reviewed-by: Stephen Boyd <sboyd@kernel.org>
-Link: https://lore.kernel.org/r/20220426212136.1543984-1-bjorn.andersson@linaro.org
----
- drivers/clk/qcom/clk-rcg.h | 2 +
- drivers/clk/qcom/clk-rcg2.c | 126 ++++++++++++++++++++++++++++--------
- 2 files changed, 101 insertions(+), 27 deletions(-)
-
---- a/drivers/clk/qcom/clk-rcg.h
-+++ b/drivers/clk/qcom/clk-rcg.h
-@@ -139,6 +139,7 @@ extern const struct clk_ops clk_dyn_rcg_
- * @freq_tbl: frequency table
- * @clkr: regmap clock handle
- * @cfg_off: defines the cfg register offset from the CMD_RCGR + CFG_REG
-+ * @parked_cfg: cached value of the CFG register for parked RCGs
- */
- struct clk_rcg2 {
- u32 cmd_rcgr;
-@@ -149,6 +150,7 @@ struct clk_rcg2 {
- const struct freq_tbl *freq_tbl;
- struct clk_regmap clkr;
- u8 cfg_off;
-+ u32 parked_cfg;
- };
-
- #define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr)
---- a/drivers/clk/qcom/clk-rcg2.c
-+++ b/drivers/clk/qcom/clk-rcg2.c
-@@ -74,16 +74,11 @@ static int clk_rcg2_is_enabled(struct cl
- return (cmd & CMD_ROOT_OFF) == 0;
- }
-
--static u8 clk_rcg2_get_parent(struct clk_hw *hw)
-+static u8 __clk_rcg2_get_parent(struct clk_hw *hw, u32 cfg)
- {
- struct clk_rcg2 *rcg = to_clk_rcg2(hw);
- int num_parents = clk_hw_get_num_parents(hw);
-- u32 cfg;
-- int i, ret;
--
-- ret = regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg);
-- if (ret)
-- goto err;
-+ int i;
-
- cfg &= CFG_SRC_SEL_MASK;
- cfg >>= CFG_SRC_SEL_SHIFT;
-@@ -92,12 +87,27 @@ static u8 clk_rcg2_get_parent(struct clk
- if (cfg == rcg->parent_map[i].cfg)
- return i;
-
--err:
- pr_debug("%s: Clock %s has invalid parent, using default.\n",
- __func__, clk_hw_get_name(hw));
- return 0;
- }
-
-+static u8 clk_rcg2_get_parent(struct clk_hw *hw)
-+{
-+ struct clk_rcg2 *rcg = to_clk_rcg2(hw);
-+ u32 cfg;
-+ int ret;
-+
-+ ret = regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg);
-+ if (ret) {
-+ pr_debug("%s: Unable to read CFG register for %s\n",
-+ __func__, clk_hw_get_name(hw));
-+ return 0;
-+ }
-+
-+ return __clk_rcg2_get_parent(hw, cfg);
-+}
-+
- static int update_config(struct clk_rcg2 *rcg)
- {
- int count, ret;
-@@ -164,12 +174,10 @@ calc_rate(unsigned long rate, u32 m, u32
- }
-
- static unsigned long
--clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
-+__clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate, u32 cfg)
- {
- struct clk_rcg2 *rcg = to_clk_rcg2(hw);
-- u32 cfg, hid_div, m = 0, n = 0, mode = 0, mask;
--
-- regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg);
-+ u32 hid_div, m = 0, n = 0, mode = 0, mask;
-
- if (rcg->mnd_width) {
- mask = BIT(rcg->mnd_width) - 1;
-@@ -190,6 +198,17 @@ clk_rcg2_recalc_rate(struct clk_hw *hw,
- return calc_rate(parent_rate, m, n, mode, hid_div);
- }
-
-+static unsigned long
-+clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
-+{
-+ struct clk_rcg2 *rcg = to_clk_rcg2(hw);
-+ u32 cfg;
-+
-+ regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg);
-+
-+ return __clk_rcg2_recalc_rate(hw, parent_rate, cfg);
-+}
-+
- static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f,
- struct clk_rate_request *req,
- enum freq_policy policy)
-@@ -263,7 +282,8 @@ static int clk_rcg2_determine_floor_rate
- return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, FLOOR);
- }
-
--static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
-+static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f,
-+ u32 *_cfg)
- {
- u32 cfg, mask, d_val, not2d_val, n_minus_m;
- struct clk_hw *hw = &rcg->clkr.hw;
-@@ -305,15 +325,27 @@ static int __clk_rcg2_configure(struct c
- cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
- if (rcg->mnd_width && f->n && (f->m != f->n))
- cfg |= CFG_MODE_DUAL_EDGE;
-- return regmap_update_bits(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg),
-- mask, cfg);
-+
-+ *_cfg &= ~mask;
-+ *_cfg |= cfg;
-+
-+ return 0;
- }
-
- static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
- {
-+ u32 cfg;
- int ret;
-
-- ret = __clk_rcg2_configure(rcg, f);
-+ ret = regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg);
-+ if (ret)
-+ return ret;
-+
-+ ret = __clk_rcg2_configure(rcg, f, &cfg);
-+ if (ret)
-+ return ret;
-+
-+ ret = regmap_write(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), cfg);
- if (ret)
- return ret;
-
-@@ -994,11 +1026,12 @@ static int clk_rcg2_shared_set_rate(stru
- return -EINVAL;
-
- /*
-- * In case clock is disabled, update the CFG, M, N and D registers
-- * and don't hit the update bit of CMD register.
-+ * In case clock is disabled, update the M, N and D registers, cache
-+ * the CFG value in parked_cfg and don't hit the update bit of CMD
-+ * register.
- */
-- if (!__clk_is_enabled(hw->clk))
-- return __clk_rcg2_configure(rcg, f);
-+ if (!clk_hw_is_enabled(hw))
-+ return __clk_rcg2_configure(rcg, f, &rcg->parked_cfg);
-
- return clk_rcg2_shared_force_enable_clear(hw, f);
- }
-@@ -1022,6 +1055,11 @@ static int clk_rcg2_shared_enable(struct
- if (ret)
- return ret;
-
-+ /* Write back the stored configuration corresponding to current rate */
-+ ret = regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, rcg->parked_cfg);
-+ if (ret)
-+ return ret;
-+
- ret = update_config(rcg);
- if (ret)
- return ret;
-@@ -1032,13 +1070,12 @@ static int clk_rcg2_shared_enable(struct
- static void clk_rcg2_shared_disable(struct clk_hw *hw)
- {
- struct clk_rcg2 *rcg = to_clk_rcg2(hw);
-- u32 cfg;
-
- /*
- * Store current configuration as switching to safe source would clear
- * the SRC and DIV of CFG register
- */
-- regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
-+ regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &rcg->parked_cfg);
-
- /*
- * Park the RCG at a safe configuration - sourced off of safe source.
-@@ -1056,17 +1093,52 @@ static void clk_rcg2_shared_disable(stru
- update_config(rcg);
-
- clk_rcg2_clear_force_enable(hw);
-+}
-
-- /* Write back the stored configuration corresponding to current rate */
-- regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, cfg);
-+static u8 clk_rcg2_shared_get_parent(struct clk_hw *hw)
-+{
-+ struct clk_rcg2 *rcg = to_clk_rcg2(hw);
-+
-+ /* If the shared rcg is parked use the cached cfg instead */
-+ if (!clk_hw_is_enabled(hw))
-+ return __clk_rcg2_get_parent(hw, rcg->parked_cfg);
-+
-+ return clk_rcg2_get_parent(hw);
-+}
-+
-+static int clk_rcg2_shared_set_parent(struct clk_hw *hw, u8 index)
-+{
-+ struct clk_rcg2 *rcg = to_clk_rcg2(hw);
-+
-+ /* If the shared rcg is parked only update the cached cfg */
-+ if (!clk_hw_is_enabled(hw)) {
-+ rcg->parked_cfg &= ~CFG_SRC_SEL_MASK;
-+ rcg->parked_cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
-+
-+ return 0;
-+ }
-+
-+ return clk_rcg2_set_parent(hw, index);
-+}
-+
-+static unsigned long
-+clk_rcg2_shared_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
-+{
-+ struct clk_rcg2 *rcg = to_clk_rcg2(hw);
-+
-+ /* If the shared rcg is parked use the cached cfg instead */
-+ if (!clk_hw_is_enabled(hw))
-+ return __clk_rcg2_recalc_rate(hw, parent_rate, rcg->parked_cfg);
-+
-+ return clk_rcg2_recalc_rate(hw, parent_rate);
- }
-
- const struct clk_ops clk_rcg2_shared_ops = {
- .enable = clk_rcg2_shared_enable,
- .disable = clk_rcg2_shared_disable,
-- .get_parent = clk_rcg2_get_parent,
-- .set_parent = clk_rcg2_set_parent,
-- .recalc_rate = clk_rcg2_recalc_rate,
-+ .get_parent = clk_rcg2_shared_get_parent,
-+ .set_parent = clk_rcg2_shared_set_parent,
-+ .recalc_rate = clk_rcg2_shared_recalc_rate,
- .determine_rate = clk_rcg2_determine_rate,
- .set_rate = clk_rcg2_shared_set_rate,
- .set_rate_and_parent = clk_rcg2_shared_set_rate_and_parent,
projects / openwrt / staging / hauke.git / commitdiff