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[openwrt/staging/hauke.git] / target / linux / ipq807x / patches-6.1 / 0073-v6.0-phy-qcom-qmp-pcie-add-IPQ8074-PCIe-Gen3-QMP-PHY-supp.patch
1 From 23bd21d8c05109b57aa9508e88fbdbc2b6d33de7 Mon Sep 17 00:00:00 2001
2 From: Robert Marko <robimarko@gmail.com>
3 Date: Tue, 23 Aug 2022 22:47:40 +0200
4 Subject: [PATCH] phy: qcom-qmp-pcie: add IPQ8074 PCIe Gen3 QMP PHY support
5
6 IPQ8074 has 2 different single lane PCIe PHY-s, one Gen2 and one Gen3.
7 Gen2 one is already supported, so add the support for the Gen3 one.
8 It uses the same register layout as IPQ6018.
9
10 Signed-off-by: Robert Marko <robimarko@gmail.com>
11 Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
12 Link: https://lore.kernel.org/r/20220621195512.1760362-3-robimarko@gmail.com
13 Signed-off-by: Vinod Koul <vkoul@kernel.org>
14 ---
15 drivers/phy/qualcomm/phy-qcom-qmp.c | 160 ++++++++++++++++++++++++++++
16 1 file changed, 160 insertions(+)
17
18 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c
19 +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
20 @@ -812,6 +812,133 @@ static const struct qmp_phy_init_tbl ipq
21 QMP_PHY_INIT_CFG_L(QPHY_START_CTRL, 0x3),
22 };
23
24 +static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_serdes_tbl[] = {
25 + QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
26 + QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
27 + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31),
28 + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
29 + QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
30 + QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
31 + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
32 + QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
33 + QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01),
34 + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04),
35 + QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
36 + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff),
37 + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f),
38 + QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30),
39 + QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21),
40 + QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x82),
41 + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x03),
42 + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0x355),
43 + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0x35555),
44 + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x1a),
45 + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0x1a0a),
46 + QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0xb),
47 + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
48 + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
49 + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x0),
50 + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0x40),
51 + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
52 + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
53 + QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
54 + QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20),
55 + QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0xa),
56 + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
57 + QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
58 + QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
59 + QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
60 + QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0xa),
61 + QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x1),
62 + QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x68),
63 + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x2),
64 + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x2aa),
65 + QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x2aaab),
66 + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
67 + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x34),
68 + QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0x3414),
69 + QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x0b),
70 + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
71 + QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
72 + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x0),
73 + QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0x40),
74 + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
75 + QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
76 + QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
77 + QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x0),
78 + QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
79 + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19),
80 + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28),
81 + QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
82 +};
83 +
84 +static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_tx_tbl[] = {
85 + QMP_PHY_INIT_CFG(QSERDES_TX0_RES_CODE_LANE_OFFSET_TX, 0x02),
86 + QMP_PHY_INIT_CFG(QSERDES_TX0_RCV_DETECT_LVL_2, 0x12),
87 + QMP_PHY_INIT_CFG(QSERDES_TX0_HIGHZ_DRVR_EN, 0x10),
88 + QMP_PHY_INIT_CFG(QSERDES_TX0_LANE_MODE_1, 0x06),
89 +};
90 +
91 +static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_rx_tbl[] = {
92 + QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_CNTRL, 0x03),
93 + QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_ENABLES, 0x1c),
94 + QMP_PHY_INIT_CFG(QSERDES_RX0_SIGDET_DEGLITCH_CNTRL, 0x14),
95 + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2, 0xe),
96 + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3, 0x4),
97 + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
98 + QMP_PHY_INIT_CFG(QSERDES_RX0_DFE_EN_TIMER, 0x04),
99 + QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
100 + QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_PI_CONTROLS, 0x70),
101 + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
102 + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
103 + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_LOW, 0x00),
104 + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH, 0x02),
105 + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH2, 0xc8),
106 + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH3, 0x09),
107 + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_10_HIGH4, 0xb1),
108 + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_LOW, 0x01),
109 + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH, 0x02),
110 + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH2, 0xc8),
111 + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH3, 0x09),
112 + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_01_HIGH4, 0xb1),
113 + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_LOW, 0xf0),
114 + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH, 0x2),
115 + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH2, 0x2f),
116 + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH3, 0xd3),
117 + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_MODE_00_HIGH4, 0x40),
118 + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_HIGH, 0x00),
119 + QMP_PHY_INIT_CFG(QSERDES_RX0_RX_IDAC_TSETTLE_LOW, 0xc0),
120 + QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_FO_GAIN, 0x0c),
121 + QMP_PHY_INIT_CFG(QSERDES_RX0_UCDR_SO_GAIN, 0x02),
122 +};
123 +
124 +static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_tbl[] = {
125 + QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL2, 0x83),
126 + QMP_PHY_INIT_CFG(PCS_COM_FLL_CNT_VAL_L, 0x9),
127 + QMP_PHY_INIT_CFG(PCS_COM_FLL_CNT_VAL_H_TOL, 0x42),
128 + QMP_PHY_INIT_CFG(PCS_COM_FLL_MAN_CODE, 0x40),
129 + QMP_PHY_INIT_CFG(PCS_COM_FLL_CNTRL1, 0x01),
130 + QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x0),
131 + QMP_PHY_INIT_CFG(PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x1),
132 + QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_ACTIONS, 0x0),
133 + QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
134 + QMP_PHY_INIT_CFG(PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
135 + QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
136 + QMP_PHY_INIT_CFG(PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
137 + QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG1, 0x11),
138 + QMP_PHY_INIT_CFG(PCS_PCIE_EQ_CONFIG2, 0xb),
139 + QMP_PHY_INIT_CFG(PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
140 + QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_CONFIG2, 0x52),
141 + QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50),
142 + QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a),
143 + QMP_PHY_INIT_CFG(PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x6),
144 + QMP_PHY_INIT_CFG(PCS_COM_G12S1_TXDEEMPH_M3P5DB, 0x10),
145 + QMP_PHY_INIT_CFG(PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
146 + QMP_PHY_INIT_CFG(PCS_COM_RX_DCC_CAL_CONFIG, 0x01),
147 + QMP_PHY_INIT_CFG(PCS_COM_RX_SIGDET_LVL, 0xaa),
148 + QMP_PHY_INIT_CFG(PCS_COM_REFGEN_REQ_CONFIG1, 0x0d),
149 +};
150 +
151 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
152 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
153 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
154 @@ -3168,6 +3295,36 @@ static const struct qmp_phy_cfg ipq8074_
155 .pwrdn_delay_max = 1005, /* us */
156 };
157
158 +static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = {
159 + .type = PHY_TYPE_PCIE,
160 + .nlanes = 1,
161 +
162 + .serdes_tbl = ipq8074_pcie_gen3_serdes_tbl,
163 + .serdes_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl),
164 + .tx_tbl = ipq8074_pcie_gen3_tx_tbl,
165 + .tx_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl),
166 + .rx_tbl = ipq8074_pcie_gen3_rx_tbl,
167 + .rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_rx_tbl),
168 + .pcs_tbl = ipq8074_pcie_gen3_pcs_tbl,
169 + .pcs_tbl_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_tbl),
170 + .clk_list = ipq8074_pciephy_clk_l,
171 + .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
172 + .reset_list = ipq8074_pciephy_reset_l,
173 + .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
174 + .vreg_list = NULL,
175 + .num_vregs = 0,
176 + .regs = ipq_pciephy_gen3_regs_layout,
177 +
178 + .start_ctrl = SERDES_START | PCS_START,
179 + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
180 +
181 + .has_pwrdn_delay = true,
182 + .pwrdn_delay_min = 995, /* us */
183 + .pwrdn_delay_max = 1005, /* us */
184 +
185 + .pipe_clock_rate = 250000000,
186 +};
187 +
188 static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
189 .type = PHY_TYPE_PCIE,
190 .nlanes = 1,
191 @@ -5571,6 +5728,9 @@ static const struct of_device_id qcom_qm
192 .compatible = "qcom,ipq8074-qmp-pcie-phy",
193 .data = &ipq8074_pciephy_cfg,
194 }, {
195 + .compatible = "qcom,ipq8074-qmp-gen3-pcie-phy",
196 + .data = &ipq8074_pciephy_gen3_cfg,
197 + }, {
198 .compatible = "qcom,ipq6018-qmp-pcie-phy",
199 .data = &ipq6018_pciephy_cfg,
200 }, {
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