target/linux/ipq806x/patches-6.6/107-10-ARM-dts-qcom-add-saw-for-l2-cache-and-kraitcc-for.patch

   1 From bef5018abb7cf94efafdc05087b4c998891ae4ec Mon Sep 17 00:00:00 2001
   2 From: Ansuel Smith <ansuelsmth@gmail.com>
   3 Date: Mon, 17 Jan 2022 23:39:34 +0100
   4 Subject: [PATCH v3 10/18] ARM: dts: qcom: add saw for l2 cache and kraitcc for
   5  ipq8064
   6
   7 Add saw compatible for l2 cache and kraitcc node for ipq8064 dtsi.
   8 Also declare clock-output-names for acc0 and acc1 and qsb fixed clock
   9 for the secondary mux.
  10
  11 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
  12 Tested-by: Jonathan McDowell <noodles@earth.li>
  13 ---
  14  arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 34 +++++++++++++++++++++++++++--
  15  1 file changed, 32 insertions(+), 2 deletions(-)
  16
  17 --- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
  18 +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
  19 @@ -302,6 +302,12 @@
  20         };
  21
  22         clocks {
  23 +               qsb: qsb {
  24 +                       compatible = "fixed-clock";
  25 +                       clock-frequency = <225000000>;
  26 +                       #clock-cells = <0>;
  27 +               };
  28 +
  29                 cxo_board: cxo_board {
  30                         compatible = "fixed-clock";
  31                         #clock-cells = <0>;
  32 @@ -587,7 +593,7 @@
  33                 };
  34
  35                 saw0: regulator@2089000 {
  36 -                       compatible = "qcom,saw2";
  37 +                       compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
  38                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
  39                         regulator;
  40                 };
  41 @@ -602,11 +608,27 @@
  42                 };
  43
  44                 saw1: regulator@2099000 {
  45 -                       compatible = "qcom,saw2";
  46 +                       compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
  47                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
  48                         regulator;
  49                 };
  50
  51 +               saw_l2: regulator@02012000 {
  52 +                       compatible = "qcom,saw2", "syscon";
  53 +                       reg = <0x02012000 0x1000>;
  54 +                       regulator;
  55 +               };
  56 +
  57 +               kraitcc: clock-controller {
  58 +                       compatible = "qcom,krait-cc-v1";
  59 +                       clocks = <&gcc PLL9>, <&gcc PLL10>, <&gcc PLL12>,
  60 +                                <&acc0>, <&acc1>, <&l2cc>, <&qsb>, <&pxo_board>;
  61 +                       clock-names = "hfpll0", "hfpll1", "hfpll_l2",
  62 +                                     "acpu0_aux", "acpu1_aux", "acpu_l2_aux",
  63 +                                     "qsb", "pxo";
  64 +                       #clock-cells = <1>;
  65 +               };
  66 +
  67                 nss_common: syscon@3000000 {
  68                         compatible = "syscon";
  69                         reg = <0x03000000 0x0000FFFF>;