mediatek: add basic mt7988 device tree support
authorSam Shih <sam.shih@mediatek.com>
Sun, 19 Feb 2023 02:18:36 +0000 (10:18 +0800)
committerDaniel Golle <daniel@makrotopia.org>
Wed, 24 May 2023 18:26:52 +0000 (19:26 +0100)
This add basic device tree support for mediatek MT7988 SoC

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
(cherry picked from commit e3a681bab4b2c193704e76b8a6091e57f0fab14e)

target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts [new file with mode: 0644]
target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtsi [new file with mode: 0644]
target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dtsi [new file with mode: 0644]
target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi [new file with mode: 0644]
target/linux/mediatek/filogic/base-files/etc/board.d/02_network
target/linux/mediatek/filogic/config-5.15
target/linux/mediatek/image/filogic.mk

diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-dsa-10g-spim-nand.dts
new file mode 100644 (file)
index 0000000..98dbf8d
--- /dev/null
@@ -0,0 +1,200 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Sam.Shih <sam.shih@mediatek.com>
+ */
+
+/dts-v1/;
+#include "mt7988a-rfb-spim-nand.dtsi"
+#include <dt-bindings/pinctrl/mt65xx.h>
+
+/ {
+       model = "MediaTek MT7988A DSA 10G SPIM-NAND RFB";
+       compatible = "mediatek,mt7988a-dsa-10g-spim-snand",
+                    "mediatek,mt7988a-rfb-snand",
+                    "mediatek,mt7988";
+
+       chosen {
+               bootargs = "console=ttyS0,115200n1 loglevel=8  \
+                           earlycon=uart8250,mmio32,0x11000000 \
+                           pci=pcie_bus_perf";
+       };
+
+       memory {
+               reg = <0 0x40000000 0 0x40000000>;
+       };
+};
+
+&eth {
+       pinctrl-0 = <&mdio0_pins>;
+       pinctrl-names = "default";
+       status = "okay";
+
+       gmac0: mac@0 {
+               compatible = "mediatek,eth-mac";
+               reg = <0>;
+               phy-mode = "internal";
+
+               fixed-link {
+                       speed = <10000>;
+                       full-duplex;
+                       pause;
+               };
+       };
+
+       gmac1: mac@1 {
+               compatible = "mediatek,eth-mac";
+               reg = <1>;
+               phy-mode = "internal";
+               phy-connection-type = "internal";
+               phy = <&phy15>;
+       };
+
+       gmac2: mac@2 {
+               compatible = "mediatek,eth-mac";
+               reg = <2>;
+               phy-mode = "10gbase-kr";
+               phy-connection-type = "10gbase-kr";
+               phy = <&phy8>;
+       };
+
+       mdio0: mdio-bus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               /* external Aquantia AQR113C */
+               phy0: ethernet-phy@0 {
+                       reg = <0>;
+                       compatible = "ethernet-phy-ieee802.3-c45";
+                       reset-gpios = <&pio 72 1>;
+                       reset-assert-us = <100000>;
+                       reset-deassert-us = <221000>;
+               };
+
+               /* external Aquantia AQR113C */
+               phy8: ethernet-phy@8 {
+                       reg = <8>;
+                       compatible = "ethernet-phy-ieee802.3-c45";
+                       reset-gpios = <&pio 71 1>;
+                       reset-assert-us = <100000>;
+                       reset-deassert-us = <221000>;
+               };
+
+               /* external Maxlinear GPY211C */
+               phy5: ethernet-phy@5 {
+                       reg = <5>;
+                       compatible = "ethernet-phy-ieee802.3-c45";
+                       phy-mode = "2500base-x";
+               };
+
+               /* external Maxlinear GPY211C */
+               phy13: ethernet-phy@13 {
+                       reg = <13>;
+                       compatible = "ethernet-phy-ieee802.3-c45";
+                       phy-mode = "2500base-x";
+               };
+
+               /* internal 2.5G PHY */
+               phy15: ethernet-phy@15 {
+                       reg = <15>;
+                       pinctrl-names = "i2p5gbe-led";
+                       pinctrl-0 = <&i2p5gbe_led0_pins>;
+                       compatible = "ethernet-phy-ieee802.3-c45";
+                       phy-mode = "internal";
+               };
+       };
+};
+
+&switch {
+       status = "okay";
+
+       ports {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               port@0 {
+                       reg = <0>;
+                       label = "lan0";
+                       phy-mode = "internal";
+                       phy-handle = <&gsw_phy0>;
+               };
+
+               port@1 {
+                       reg = <1>;
+                       label = "lan1";
+                       phy-mode = "internal";
+                       phy-handle = <&gsw_phy1>;
+               };
+
+               port@2 {
+                       reg = <2>;
+                       label = "lan2";
+                       phy-mode = "internal";
+                       phy-handle = <&gsw_phy2>;
+               };
+
+               port@3 {
+                       reg = <3>;
+                       label = "lan3";
+                       phy-mode = "internal";
+                       phy-handle = <&gsw_phy3>;
+               };
+
+               port@6 {
+                       reg = <6>;
+                       ethernet = <&gmac0>;
+                       phy-mode = "internal";
+
+                       fixed-link {
+                               speed = <10000>;
+                               full-duplex;
+                               pause;
+                       };
+               };
+       };
+
+       mdio {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               gsw_phy0: ethernet-phy@0 {
+                       compatible = "ethernet-phy-id03a2.9481";
+                       reg = <0>;
+                       phy-mode = "internal";
+                       pinctrl-names = "gbe-led";
+                       pinctrl-0 = <&gbe0_led0_pins>;
+                       nvmem-cells = <&phy_calibration_p0>;
+                       nvmem-cell-names = "phy-cal-data";
+               };
+
+               gsw_phy1: ethernet-phy@1 {
+                       compatible = "ethernet-phy-id03a2.9481";
+                       reg = <1>;
+                       phy-mode = "internal";
+                       pinctrl-names = "gbe-led";
+                       pinctrl-0 = <&gbe1_led0_pins>;
+                       nvmem-cells = <&phy_calibration_p1>;
+                       nvmem-cell-names = "phy-cal-data";
+               };
+
+               gsw_phy2: ethernet-phy@2 {
+                       compatible = "ethernet-phy-id03a2.9481";
+                       reg = <2>;
+                       phy-mode = "internal";
+                       pinctrl-names = "gbe-led";
+                       pinctrl-0 = <&gbe2_led0_pins>;
+                       nvmem-cells = <&phy_calibration_p2>;
+                       nvmem-cell-names = "phy-cal-data";
+               };
+
+               gsw_phy3: ethernet-phy@3 {
+                       compatible = "ethernet-phy-id03a2.9481";
+                       reg = <3>;
+                       phy-mode = "internal";
+                       pinctrl-names = "gbe-led";
+                       pinctrl-0 = <&gbe3_led0_pins>;
+                       nvmem-cells = <&phy_calibration_p3>;
+                       nvmem-cell-names = "phy-cal-data";
+               };
+       };
+};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtsi b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb-spim-nand.dtsi
new file mode 100644 (file)
index 0000000..e4c0571
--- /dev/null
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Sam.Shih <sam.shih@mediatek.com>
+ */
+
+/dts-v1/;
+#include "mt7988a-rfb.dtsi"
+
+&pio {
+       spi0_flash_pins: spi0-pins {
+               mux {
+                       function = "spi";
+                       groups = "spi0", "spi0_wp_hold";
+               };
+       };
+};
+
+&spi0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&spi0_flash_pins>;
+       status = "okay";
+
+       spi_nand: spi_nand@0 {
+               compatible = "spi-nand";
+               reg = <0>;
+               spi-max-frequency = <52000000>;
+               spi-tx-buswidth = <4>;
+               spi-rx-buswidth = <4>;
+       };
+
+};
+
+&spi_nand {
+       mediatek,nmbm;
+       mediatek,bmt-max-ratio = <1>;
+       mediatek,bmt-max-reserved-blocks = <64>;
+
+       partitions {
+               compatible = "fixed-partitions";
+               #address-cells = <1>;
+               #size-cells = <1>;
+
+               partition@0 {
+                       label = "BL2";
+                       reg = <0x00000 0x0100000>;
+                       read-only;
+               };
+
+               partition@100000 {
+                       label = "u-boot-env";
+                       reg = <0x0100000 0x0080000>;
+               };
+
+               factory: partition@180000 {
+                       label = "Factory";
+                       reg = <0x180000 0x0400000>;
+               };
+
+               partition@580000 {
+                       label = "FIP";
+                       reg = <0x580000 0x0200000>;
+               };
+
+               partition@780000 {
+                       label = "ubi";
+                       reg = <0x780000 0x7080000>;
+               };
+       };
+};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dtsi b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a-rfb.dtsi
new file mode 100644 (file)
index 0000000..423b386
--- /dev/null
@@ -0,0 +1,175 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Author: Sam.Shih <sam.shih@mediatek.com>
+ */
+
+/dts-v1/;
+#include "mt7988a.dtsi"
+#include <dt-bindings/regulator/richtek,rt5190a-regulator.h>
+
+&cpu0 {
+       proc-supply = <&rt5190_buck3>;
+};
+
+&cpu1 {
+       proc-supply = <&rt5190_buck3>;
+};
+
+&cpu2 {
+       proc-supply = <&rt5190_buck3>;
+};
+
+&cpu3 {
+       proc-supply = <&rt5190_buck3>;
+};
+
+&cci {
+       proc-supply = <&rt5190_buck3>;
+};
+
+&eth {
+       status = "okay";
+};
+
+&i2c0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&i2c0_pins>;
+       status = "okay";
+
+       rt5190a_64: rt5190a@64 {
+               compatible = "richtek,rt5190a";
+               reg = <0x64>;
+               /*interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;*/
+               vin2-supply = <&rt5190_buck1>;
+               vin3-supply = <&rt5190_buck1>;
+               vin4-supply = <&rt5190_buck1>;
+
+               regulators {
+                       rt5190_buck1: buck1 {
+                               regulator-name = "rt5190a-buck1";
+                               regulator-min-microvolt = <5090000>;
+                               regulator-max-microvolt = <5090000>;
+                               regulator-allowed-modes =
+                               <RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+                       buck2 {
+                               regulator-name = "vcore";
+                               regulator-min-microvolt = <600000>;
+                               regulator-max-microvolt = <1400000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+                       rt5190_buck3: buck3 {
+                               regulator-name = "vproc";
+                               regulator-min-microvolt = <600000>;
+                               regulator-max-microvolt = <1400000>;
+                               regulator-boot-on;
+                       };
+                       buck4 {
+                               regulator-name = "rt5190a-buck4";
+                               regulator-min-microvolt = <850000>;
+                               regulator-max-microvolt = <850000>;
+                               regulator-allowed-modes =
+                               <RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+                       ldo {
+                               regulator-name = "rt5190a-ldo";
+                               regulator-min-microvolt = <1200000>;
+                               regulator-max-microvolt = <1200000>;
+                               regulator-boot-on;
+                               regulator-always-on;
+                       };
+               };
+       };
+};
+
+&pcie0 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pcie0_pins>;
+       status = "okay";
+};
+
+&pcie1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pcie1_pins>;
+       status = "okay";
+};
+
+&pcie2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pcie2_pins>;
+       status = "disabled";
+};
+
+&pcie3 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pcie3_pins>;
+       status = "okay";
+};
+
+&ssusb0 {
+       status = "okay";
+};
+
+&ssusb1 {
+       status = "okay";
+};
+
+&tphy {
+       status = "okay";
+};
+
+&pio {
+       pcie0_pins: pcie0-pins {
+               mux {
+                       function = "pcie";
+                       groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0",
+                                "pcie_wake_n0_0";
+               };
+       };
+
+       pcie1_pins: pcie1-pins {
+               mux {
+                       function = "pcie";
+                       groups = "pcie_2l_1_pereset", "pcie_clk_req_n1",
+                                "pcie_wake_n1_0";
+               };
+       };
+
+       pcie2_pins: pcie2-pins {
+               mux {
+                       function = "pcie";
+                       groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0",
+                                "pcie_wake_n2_0";
+               };
+       };
+
+       pcie3_pins: pcie3-pins {
+               mux {
+                       function = "pcie";
+                       groups = "pcie_1l_1_pereset", "pcie_clk_req_n3",
+                                "pcie_wake_n3_0";
+               };
+       };
+};
+
+&spi0 {
+       status = "disabled";
+};
+
+&uart0 {
+       status = "okay";
+};
+
+&watchdog {
+       status = "okay";
+};
+
+&xphy {
+       status = "okay";
+};
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
new file mode 100644 (file)
index 0000000..13ad395
--- /dev/null
@@ -0,0 +1,853 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 MediaTek Inc.
+ * Author: Sam.Shih <sam.shih@mediatek.com>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/reset/ti-syscon.h>
+#include <dt-bindings/clock/mediatek,mt7988-clk.h>
+#include <dt-bindings/pinctrl/mt65xx.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+       compatible = "mediatek,mt7988";
+       interrupt-parent = <&gic>;
+       #address-cells = <2>;
+       #size-cells = <2>;
+
+       clk40m: oscillator@0 {
+               compatible = "fixed-clock";
+               clock-frequency = <40000000>;
+               #clock-cells = <0>;
+               clock-output-names = "clkxtal";
+       };
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               cpu0: cpu@0 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a73";
+                       enable-method = "psci";
+                       reg = <0x0>;
+                       clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
+                                <&topckgen CLK_TOP_XTAL>;
+                       clock-names = "cpu", "intermediate";
+                       operating-points-v2 = <&cluster0_opp>;
+                       mediatek,cci = <&cci>;
+               };
+
+               cpu1: cpu@1 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a73";
+                       enable-method = "psci";
+                       reg = <0x1>;
+                       clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
+                                <&topckgen CLK_TOP_XTAL>;
+                       clock-names = "cpu", "intermediate";
+                       operating-points-v2 = <&cluster0_opp>;
+                       mediatek,cci = <&cci>;
+               };
+
+               cpu2: cpu@2 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a73";
+                       enable-method = "psci";
+                       reg = <0x2>;
+                       clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
+                                <&topckgen CLK_TOP_XTAL>;
+                       clock-names = "cpu", "intermediate";
+                       operating-points-v2 = <&cluster0_opp>;
+                       mediatek,cci = <&cci>;
+               };
+
+               cpu3: cpu@3 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a73";
+                       enable-method = "psci";
+                       reg = <0x3>;
+                       clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
+                                <&topckgen CLK_TOP_XTAL>;
+                       clock-names = "cpu", "intermediate";
+                       operating-points-v2 = <&cluster0_opp>;
+                       mediatek,cci = <&cci>;
+               };
+
+               cluster0_opp: opp_table0 {
+                       compatible = "operating-points-v2";
+                       opp-shared;
+                       opp00 {
+                               opp-hz = /bits/ 64 <800000000>;
+                               opp-microvolt = <850000>;
+                       };
+                       opp01 {
+                               opp-hz = /bits/ 64 <1100000000>;
+                               opp-microvolt = <850000>;
+                       };
+                       opp02 {
+                               opp-hz = /bits/ 64 <1500000000>;
+                               opp-microvolt = <850000>;
+                       };
+                       opp03 {
+                               opp-hz = /bits/ 64 <1800000000>;
+                               opp-microvolt = <900000>;
+                       };
+               };
+       };
+
+       cci: cci {
+               compatible = "mediatek,mt7988-cci",
+                            "mediatek,mt8183-cci";
+               clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
+                        <&topckgen CLK_TOP_XTAL>;
+               clock-names = "cci", "intermediate";
+               operating-points-v2 = <&cci_opp>;
+       };
+
+       cci_opp: opp_table_cci {
+               compatible = "operating-points-v2";
+               opp-shared;
+               opp00 {
+                       opp-hz = /bits/ 64 <480000000>;
+                       opp-microvolt = <850000>;
+               };
+               opp01 {
+                       opp-hz = /bits/ 64 <660000000>;
+                       opp-microvolt = <850000>;
+               };
+               opp02 {
+                       opp-hz = /bits/ 64 <900000000>;
+                       opp-microvolt = <850000>;
+               };
+               opp03 {
+                       opp-hz = /bits/ 64 <1080000000>;
+                       opp-microvolt = <900000>;
+               };
+       };
+
+       pmu {
+               compatible = "arm,cortex-a73-pmu";
+               interrupt-parent = <&gic>;
+               interrupt = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+       };
+
+       psci {
+               compatible  = "arm,psci-0.2";
+               method      = "smc";
+       };
+
+       reserved-memory {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
+               secmon_reserved: secmon@43000000 {
+                       reg = <0 0x43000000 0 0x30000>;
+                       no-map;
+               };
+       };
+
+       timer {
+               compatible = "arm,armv8-timer";
+               interrupt-parent = <&gic>;
+               interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+                            <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+                            <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+                            <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+       };
+
+       soc {
+               #address-cells = <2>;
+               #size-cells = <2>;
+               compatible = "simple-bus";
+               ranges;
+
+               gic: interrupt-controller@c000000 {
+                       compatible = "arm,gic-v3";
+                       #interrupt-cells = <3>;
+                       interrupt-parent = <&gic>;
+                       interrupt-controller;
+                       reg = <0 0x0c000000 0 0x40000>,  /* GICD */
+                             <0 0x0c080000 0 0x200000>, /* GICR */
+                             <0 0x0c400000 0 0x2000>,   /* GICC */
+                             <0 0x0c410000 0 0x1000>,   /* GICH */
+                             <0 0x0c420000 0 0x2000>;   /* GICV */
+
+                       interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+               };
+
+               phyfw: phy-firmware@f000000 {
+                       compatible = "mediatek,2p5gphy-fw";
+                       reg = <0 0x0f000000 0 0x8000>,
+                             <0 0x0f100000 0 0x20000>,
+                             <0 0x0f0f0000 0 0x200>;
+               };
+
+               infracfg: infracfg@10001000 {
+                       compatible = "mediatek,mt7988-infracfg", "syscon";
+                       reg = <0 0x10001000 0 0x1000>;
+                       #clock-cells = <1>;
+               };
+
+               topckgen: topckgen@1001b000 {
+                       compatible = "mediatek,mt7988-topckgen", "syscon";
+                       reg = <0 0x1001b000 0 0x1000>;
+                       #clock-cells = <1>;
+               };
+
+               watchdog: watchdog@1001c000 {
+                       compatible = "mediatek,mt7988-wdt",
+                                    "mediatek,mt6589-wdt",
+                                    "syscon";
+                       reg = <0 0x1001c000 0 0x1000>;
+                       interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+                       #reset-cells = <1>;
+               };
+
+               apmixedsys: apmixedsys@1001e000 {
+                       compatible = "mediatek,mt7988-apmixedsys";
+                       reg = <0 0x1001e000 0 0x1000>;
+                       #clock-cells = <1>;
+               };
+
+               pio: pinctrl@1001f000 {
+                       compatible = "mediatek,mt7988-pinctrl";
+                       reg = <0 0x1001f000 0 0x1000>,
+                       <0 0x11c10000 0 0x1000>,
+                       <0 0x11d00000 0 0x1000>,
+                       <0 0x11d20000 0 0x1000>,
+                       <0 0x11e00000 0 0x1000>,
+                       <0 0x11f00000 0 0x1000>,
+                       <0 0x1000b000 0 0x1000>;
+                       reg-names = "gpio_base", "iocfg_tr_base",
+                                   "iocfg_br_base", "iocfg_rb_base",
+                                   "iocfg_lb_base", "iocfg_tl_base", "eint";
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       gpio-ranges = <&pio 0 0 83>;
+                       interrupt-controller;
+                       interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-parent = <&gic>;
+                       #interrupt-cells = <2>;
+
+                       mdio0_pins: mdio0-pins {
+                               mux {
+                                       function = "eth";
+                                       groups = "mdc_mdio0";
+                               };
+
+                               conf {
+                                       groups = "mdc_mdio0";
+                                       drive-strength = <MTK_DRIVE_8mA>;
+                               };
+                       };
+
+                       i2c0_pins: i2c0-pins-g0 {
+                               mux {
+                                       function = "i2c";
+                                       groups = "i2c0_1";
+                               };
+                       };
+
+                       i2c1_pins: i2c1-pins-g0 {
+                               mux {
+                                       function = "i2c";
+                                       groups = "i2c1_0";
+                               };
+                       };
+
+                       i2c2_pins: i2c2-pins-g0 {
+                               mux {
+                                       function = "i2c";
+                                       groups = "i2c2_1";
+                               };
+                       };
+
+                       gbe0_led0_pins: gbe0-pins {
+                               mux {
+                                       function = "led";
+                                       groups = "gbe0_led0";
+                               };
+                       };
+
+                       gbe1_led0_pins: gbe1-pins {
+                               mux {
+                                       function = "led";
+                                       groups = "gbe1_led0";
+                               };
+                       };
+
+                       gbe2_led0_pins: gbe2-pins {
+                               mux {
+                                       function = "led";
+                                       groups = "gbe2_led0";
+                               };
+                       };
+
+                       gbe3_led0_pins: gbe3-pins {
+                               mux {
+                                       function = "led";
+                                       groups = "gbe3_led0";
+                               };
+                       };
+
+                       i2p5gbe_led0_pins: 2p5gbe-pins {
+                               mux {
+                                       function = "led";
+                                       groups = "2p5gbe_led0";
+                               };
+                       };
+               };
+
+               boottrap: boottrap@1001f6f0 {
+                       compatible = "mediatek,boottrap";
+                       reg = <0 0x1001f6f0 0 0x4>;
+               };
+
+               sgmiisys0: syscon@10060000 {
+                       compatible = "mediatek,mt7988-sgmiisys",
+                                    "mediatek,mt7988-sgmiisys_0",
+                                    "syscon";
+                       reg = <0 0x10060000 0 0x1000>;
+                       #clock-cells = <1>;
+               };
+
+               sgmiisys1: syscon@10070000 {
+                       compatible = "mediatek,mt7988-sgmiisys",
+                                    "mediatek,mt7988-sgmiisys_1",
+                                    "syscon";
+                       reg = <0 0x10070000 0 0x1000>;
+                       #clock-cells = <1>;
+               };
+
+               usxgmiisys0: usxgmiisys@10080000 {
+                       compatible = "mediatek,mt7988-usxgmiisys",
+                                    "mediatek,mt7988-usxgmiisys_0",
+                                    "syscon";
+                       reg = <0 0x10080000 0 0x1000>;
+                       #clock-cells = <1>;
+               };
+
+               usxgmiisys1: usxgmiisys@10081000 {
+                       compatible = "mediatek,mt7988-usxgmiisys",
+                                    "mediatek,mt7988-usxgmiisys_1",
+                                    "syscon";
+                       reg = <0 0x10081000 0 0x1000>;
+                       #clock-cells = <1>;
+               };
+
+               xfi_pextp0: xfi_pextp@11f20000 {
+                       compatible = "mediatek,mt7988-xfi_pextp",
+                                    "mediatek,mt7988-xfi_pextp_0",
+                                    "syscon";
+                       reg = <0 0x11f20000 0 0x10000>;
+                       #clock-cells = <1>;
+               };
+
+               xfi_pextp1: xfi_pextp@11f30000 {
+                       compatible = "mediatek,mt7988-xfi_pextp",
+                                    "mediatek,mt7988-xfi_pextp_1",
+                                    "syscon";
+                       reg = <0 0x11f30000 0 0x10000>;
+                       #clock-cells = <1>;
+               };
+
+               xfi_pll: xfi_pll@11f40000 {
+                       compatible = "mediatek,mt7988-xfi_pll", "syscon";
+                       reg = <0 0x11f40000 0 0x1000>;
+                       #clock-cells = <1>;
+               };
+
+               mcusys: mcusys@100e0000 {
+                       compatible = "mediatek,mt7988-mcusys", "syscon";
+                       reg = <0 0x100e0000 0 0x1000>;
+                       #clock-cells = <1>;
+               };
+
+               uart0: serial@11000000 {
+                       compatible = "mediatek,mt7986-uart",
+                                    "mediatek,mt6577-uart";
+                       reg = <0 0x11000000 0 0x100>;
+                       interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+                       /*
+                        * 8250-mtk driver don't control "baud" clock since commit
+                        * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
+                        * still need to be passed to the driver to prevent probe fail
+                        */
+                       clocks = <&topckgen CLK_TOP_UART_SEL>,
+                                <&infracfg CLK_INFRA_52M_UART0_CK>;
+                       clock-names = "baud", "bus";
+                       assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
+                                         <&infracfg CLK_INFRA_MUX_UART0_SEL>;
+                       assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
+                                                <&topckgen CLK_TOP_UART_SEL>;
+                       status = "disabled";
+               };
+
+               i2c0: i2c@11003000 {
+                       compatible = "mediatek,mt7988-i2c",
+                                    "mediatek,mt7981-i2c";
+                       reg = <0 0x11003000 0 0x1000>,
+                             <0 0x10217080 0 0x80>;
+                       interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+                       clock-div = <1>;
+                       clocks = <&infracfg CLK_INFRA_I2C_BCK>,
+                                <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
+                       clock-names = "main", "dma";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i2c1: i2c@11004000 {
+                       compatible = "mediatek,mt7988-i2c",
+                                    "mediatek,mt7981-i2c";
+                       reg = <0 0x11004000 0 0x1000>,
+                             <0 0x10217100 0 0x80>;
+                       interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+                       clock-div = <1>;
+                       clocks = <&infracfg CLK_INFRA_I2C_BCK>,
+                                <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
+                       clock-names = "main", "dma";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               i2c2: i2c@11005000 {
+                       compatible = "mediatek,mt7988-i2c",
+                               "mediatek,mt7981-i2c";
+                       reg = <0 0x11005000 0 0x1000>,
+                             <0 0x10217180 0 0x80>;
+                       interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+                       clock-div = <1>;
+                       clocks = <&infracfg CLK_INFRA_I2C_BCK>,
+                                <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
+                       clock-names = "main", "dma";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               spi0: spi@11007000 {
+                       compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm";
+                       reg = <0 0x11007000 0 0x100>;
+                       interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&topckgen CLK_TOP_MPLL_D2>,
+                                <&topckgen CLK_TOP_SPI_SEL>,
+                                <&infracfg CLK_INFRA_104M_SPI0>,
+                                <&infracfg CLK_INFRA_66M_SPI0_HCK>;
+                       clock-names = "parent-clk", "sel-clk", "spi-clk",
+                                     "spi-hclk";
+
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       status = "disabled";
+               };
+
+               pcie2: pcie@11280000 {
+                       compatible = "mediatek,mt7988-pcie",
+                                    "mediatek,mt7986-pcie",
+                                    "mediatek,mt8192-pcie";
+                       device_type = "pci";
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       reg = <0 0x11280000 0 0x2000>;
+                       reg-names = "pcie-mac";
+                       linux,pci-domain = <3>;
+                       interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+                       bus-range = <0x00 0xff>;
+                       ranges = <0x81000000 0x00 0x20000000 0x00
+                                 0x20000000 0x00 0x00200000>,
+                                <0x82000000 0x00 0x20200000 0x00
+                                 0x20200000 0x00 0x07e00000>;
+                       clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>,
+                                <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>,
+                                <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>,
+                                <&infracfg CLK_INFRA_133M_PCIE_CK_P2>;
+                       clock-names = "pl_250m", "tl_26m", "peri_26m",
+                                     "top_133m";
+                       status = "disabled";
+
+                       phys = <&xphyu3port0 PHY_TYPE_PCIE>;
+                       phy-names = "pcie-phy";
+
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 0x7>;
+                       interrupt-map = <0 0 0 1 &pcie_intc2 0>,
+                                       <0 0 0 2 &pcie_intc2 1>,
+                                       <0 0 0 3 &pcie_intc2 2>,
+                                       <0 0 0 4 &pcie_intc2 3>;
+                       pcie_intc2: interrupt-controller {
+                               #address-cells = <0>;
+                               #interrupt-cells = <1>;
+                               interrupt-controller;
+                       };
+               };
+
+               pcie3: pcie@11290000 {
+                       compatible = "mediatek,mt7988-pcie",
+                                    "mediatek,mt7986-pcie",
+                                    "mediatek,mt8192-pcie";
+                       device_type = "pci";
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       reg = <0 0x11290000 0 0x2000>;
+                       reg-names = "pcie-mac";
+                       linux,pci-domain = <2>;
+                       interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+                       bus-range = <0x00 0xff>;
+                       ranges = <0x81000000 0x00 0x28000000 0x00
+                                 0x28000000 0x00 0x00200000>,
+                                <0x82000000 0x00 0x28200000 0x00
+                                 0x28200000 0x00 0x07e00000>;
+                       clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>,
+                                <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>,
+                                <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>,
+                                <&infracfg CLK_INFRA_133M_PCIE_CK_P3>;
+                       clock-names = "pl_250m", "tl_26m", "peri_26m",
+                                     "top_133m";
+                       status = "disabled";
+
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 0x7>;
+                       interrupt-map = <0 0 0 1 &pcie_intc3 0>,
+                                       <0 0 0 2 &pcie_intc3 1>,
+                                       <0 0 0 3 &pcie_intc3 2>,
+                                       <0 0 0 4 &pcie_intc3 3>;
+                       pcie_intc3: interrupt-controller {
+                               #address-cells = <0>;
+                               #interrupt-cells = <1>;
+                               interrupt-controller;
+                       };
+               };
+
+               pcie0: pcie@11300000 {
+                       compatible = "mediatek,mt7988-pcie",
+                                    "mediatek,mt7986-pcie",
+                                    "mediatek,mt8192-pcie";
+                       device_type = "pci";
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       reg = <0 0x11300000 0 0x2000>;
+                       reg-names = "pcie-mac";
+                       linux,pci-domain = <0>;
+                       interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+                       bus-range = <0x00 0xff>;
+                       ranges = <0x81000000 0x00 0x30000000 0x00
+                                 0x30000000 0x00 0x00200000>,
+                                <0x82000000 0x00 0x30200000 0x00
+                                 0x30200000 0x00 0x07e00000>;
+                       clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>,
+                                <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>,
+                                <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>,
+                                <&infracfg CLK_INFRA_133M_PCIE_CK_P0>;
+                       clock-names = "pl_250m", "tl_26m", "peri_26m",
+                                     "top_133m";
+                       status = "disabled";
+
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 0x7>;
+                       interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+                                       <0 0 0 2 &pcie_intc0 1>,
+                                       <0 0 0 3 &pcie_intc0 2>,
+                                       <0 0 0 4 &pcie_intc0 3>;
+                       pcie_intc0: interrupt-controller {
+                               #address-cells = <0>;
+                               #interrupt-cells = <1>;
+                               interrupt-controller;
+                       };
+               };
+
+               pcie1: pcie@11310000 {
+                       compatible = "mediatek,mt7988-pcie",
+                                    "mediatek,mt7986-pcie",
+                                    "mediatek,mt8192-pcie";
+                       device_type = "pci";
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       reg = <0 0x11310000 0 0x2000>;
+                       reg-names = "pcie-mac";
+                       linux,pci-domain = <1>;
+                       interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+                       bus-range = <0x00 0xff>;
+                       ranges = <0x81000000 0x00 0x38000000 0x00
+                                 0x38000000 0x00 0x00200000>,
+                                <0x82000000 0x00 0x38200000 0x00
+                                 0x38200000 0x00 0x07e00000>;
+                       clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>,
+                                <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>,
+                                <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>,
+                                <&infracfg CLK_INFRA_133M_PCIE_CK_P1>;
+                       clock-names = "pl_250m", "tl_26m", "peri_26m",
+                                     "top_133m";
+                       status = "disabled";
+
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 0x7>;
+                       interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+                                       <0 0 0 2 &pcie_intc1 1>,
+                                       <0 0 0 3 &pcie_intc1 2>,
+                                       <0 0 0 4 &pcie_intc1 3>;
+                       pcie_intc1: interrupt-controller {
+                               #address-cells = <0>;
+                               #interrupt-cells = <1>;
+                               interrupt-controller;
+                       };
+               };
+
+               ssusb0: usb@11190000 {
+                       compatible = "mediatek,mt7988-xhci",
+                                    "mediatek,mtk-xhci";
+                       reg = <0 0x11190000 0 0x2e00>,
+                             <0 0x11193e00 0 0x0100>;
+                       reg-names = "mac", "ippc";
+                       interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+                       phys = <&xphyu2port0 PHY_TYPE_USB2>,
+                              <&xphyu3port0 PHY_TYPE_USB3>;
+                       clocks = <&infracfg CLK_INFRA_USB_SYS>,
+                                <&infracfg CLK_INFRA_USB_XHCI>,
+                                <&infracfg CLK_INFRA_USB_REF>,
+                                <&infracfg CLK_INFRA_66M_USB_HCK>,
+                                <&infracfg CLK_INFRA_133M_USB_HCK>;
+                       clock-names = "sys_ck",
+                                     "xhci_ck",
+                                     "ref_ck",
+                                     "mcu_ck",
+                                     "dma_ck";
+                       #address-cells = <2>;
+                       #size-cells = <2>;
+                       mediatek,p0_speed_fixup;
+                       status = "disabled";
+               };
+
+               ssusb1: usb@11200000 {
+                       compatible = "mediatek,mt7988-xhci",
+                                    "mediatek,mtk-xhci";
+                       reg = <0 0x11200000 0 0x2e00>,
+                             <0 0x11203e00 0 0x0100>;
+                       reg-names = "mac", "ippc";
+                       interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+                       phys = <&tphyu2port0 PHY_TYPE_USB2>,
+                              <&tphyu3port0 PHY_TYPE_USB3>;
+                       clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>,
+                                <&infracfg CLK_INFRA_USB_XHCI_CK_P1>,
+                                <&infracfg CLK_INFRA_USB_CK_P1>,
+                                <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>,
+                                <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>;
+                       clock-names = "sys_ck",
+                                     "xhci_ck",
+                                     "ref_ck",
+                                     "mcu_ck",
+                                     "dma_ck";
+                       #address-cells = <2>;
+                       #size-cells = <2>;
+                       status = "disabled";
+               };
+
+               tphy: tphy@11c50000 {
+                       compatible = "mediatek,mt7988",
+                                    "mediatek,generic-tphy-v2";
+                       #address-cells = <2>;
+                       #size-cells = <2>;
+                       ranges;
+                       status = "disabled";
+                       tphyu2port0: usb-phy@11c50000 {
+                               reg = <0 0x11c50000 0 0x700>;
+                               clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>;
+                               clock-names = "ref";
+                               #phy-cells = <1>;
+                       };
+                       tphyu3port0: usb-phy@11c50700 {
+                               reg = <0 0x11c50700 0 0x900>;
+                               clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>;
+                               clock-names = "ref";
+                               #phy-cells = <1>;
+                               mediatek,usb3-pll-ssc-delta;
+                               mediatek,usb3-pll-ssc-delta1;
+                       };
+               };
+
+               topmisc: topmisc@11d10000 {
+                       compatible = "mediatek,mt7988-topmisc", "syscon",
+                                    "mediatek,mt7988-power-controller";
+                       reg = <0 0x11d10000 0 0x10000>;
+                       #clock-cells = <1>;
+                       #power-domain-cells = <1>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
+               xphy: xphy@11e10000 {
+                       compatible = "mediatek,mt7988",
+                                    "mediatek,xsphy";
+                       #address-cells = <2>;
+                       #size-cells = <2>;
+                       ranges;
+                       status = "disabled";
+
+                       xphyu2port0: usb-phy@11e10000 {
+                               reg = <0 0x11e10000 0 0x400>;
+                               clocks = <&infracfg CLK_INFRA_USB_UTMI>;
+                               clock-names = "ref";
+                               #phy-cells = <1>;
+                       };
+
+                       xphyu3port0: usb-phy@11e13000 {
+                               reg = <0 0x11e13400 0 0x500>;
+                               clocks = <&infracfg CLK_INFRA_USB_PIPE>;
+                               clock-names = "ref";
+                               #phy-cells = <1>;
+                               mediatek,syscon-type = <&topmisc 0x218 0>;
+                       };
+               };
+
+               efuse: efuse@11f50000 {
+                       compatible = "mediatek,efuse";
+                       reg = <0 0x11f50000 0 0x1000>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       lvts_calibration: calib@918 {
+                               reg = <0x918 0x28>;
+                       };
+                       phy_calibration_p0: calib@940 {
+                               reg = <0x940 0x10>;
+                       };
+                       phy_calibration_p1: calib@954 {
+                               reg = <0x954 0x10>;
+                       };
+                       phy_calibration_p2: calib@968 {
+                               reg = <0x968 0x10>;
+                       };
+                       phy_calibration_p3: calib@97c {
+                               reg = <0x97c 0x10>;
+                       };
+                       cpufreq_calibration: calib@278 {
+                               reg = <0x278 0x1>;
+                       };
+               };
+
+               ethsys: syscon@15000000 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       compatible = "mediatek,mt7988-ethsys", "syscon";
+                       reg = <0 0x15000000 0 0x1000>;
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+               };
+
+               switch: switch@15020000 {
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       compatible = "mediatek,mt7988-switch";
+                       reg = <0 0x15020000 0 0x8000>;
+                       interrupt-controller;
+                       #interrupt-cells = <1>;
+                       interrupt-parent = <&gic>;
+                       interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
+                       resets = <&ethrst 0>;
+               };
+
+               ethwarp: syscon@15031000 {
+                       compatible = "mediatek,mt7988-ethwarp", "syscon", "simple-mfd";
+                       reg = <0 0x15031000 0 0x1000>;
+                       #clock-cells = <1>;
+
+                       ethrst: reset-controller {
+                               compatible = "ti,syscon-reset";
+                               #reset-cells = <1>;
+                               ti,reset-bits = <
+                                       0x8 9 0x8 9 0 0 (ASSERT_SET | DEASSERT_CLEAR | STATUS_NONE)
+                               >;
+                       };
+               };
+
+               eth: ethernet@15100000 {
+                       compatible = "mediatek,mt7988-eth";
+                       reg = <0 0x15100000 0 0x80000>,
+                             <0 0x15400000 0 0x380000>;
+                       interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&ethsys CLK_ETHDMA_XGP1_EN>,
+                                <&ethsys CLK_ETHDMA_XGP2_EN>,
+                                <&ethsys CLK_ETHDMA_XGP3_EN>,
+                                <&ethsys CLK_ETHDMA_FE_EN>,
+                                <&ethsys CLK_ETHDMA_GP2_EN>,
+                                <&ethsys CLK_ETHDMA_GP1_EN>,
+                                <&ethsys CLK_ETHDMA_GP3_EN>,
+                                <&ethsys CLK_ETHDMA_ESW_EN>,
+                                <&ethsys CLK_ETHDMA_CRYPT0_EN>,
+                                <&sgmiisys0 CLK_SGM0_TX_EN>,
+                                <&sgmiisys0 CLK_SGM0_RX_EN>,
+                                <&sgmiisys1 CLK_SGM1_TX_EN>,
+                                <&sgmiisys1 CLK_SGM1_RX_EN>,
+                                <&ethwarp CLK_ETHWARP_WOCPU2_EN>,
+                                <&ethwarp CLK_ETHWARP_WOCPU1_EN>,
+                                <&ethwarp CLK_ETHWARP_WOCPU0_EN>,
+                                <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
+                                <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
+                                <&topckgen CLK_TOP_SGM_0_SEL>,
+                                <&topckgen CLK_TOP_SGM_1_SEL>,
+                                <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>,
+                                <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>,
+                                <&topckgen CLK_TOP_ETH_GMII_SEL>,
+                                <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>,
+                                <&topckgen CLK_TOP_ETH_SYS_200M_SEL>,
+                                <&topckgen CLK_TOP_ETH_SYS_SEL>,
+                                <&topckgen CLK_TOP_ETH_XGMII_SEL>,
+                                <&topckgen CLK_TOP_ETH_MII_SEL>,
+                                <&topckgen CLK_TOP_NETSYS_SEL>,
+                                <&topckgen CLK_TOP_NETSYS_500M_SEL>,
+                                <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>,
+                                <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>,
+                                <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>,
+                                <&topckgen CLK_TOP_NETSYS_WARP_SEL>;
+                       clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1",
+                                     "gp3", "esw", "crypto", "sgmii_tx250m",
+                                     "sgmii_rx250m", "sgmii2_tx250m", "sgmii2_rx250m",
+                                     "ethwarp_wocpu2", "ethwarp_wocpu1",
+                                     "ethwarp_wocpu0", "top_usxgmii0_sel",
+                                     "top_usxgmii1_sel", "top_sgm0_sel",
+                                     "top_sgm1_sel", "top_xfi_phy0_xtal_sel",
+                                     "top_xfi_phy1_xtal_sel", "top_eth_gmii_sel",
+                                     "top_eth_refck_50m_sel", "top_eth_sys_200m_sel",
+                                     "top_eth_sys_sel", "top_eth_xgmii_sel",
+                                     "top_eth_mii_sel", "top_netsys_sel",
+                                     "top_netsys_500m_sel", "top_netsys_pao_2x_sel",
+                                     "top_netsys_sync_250m_sel",
+                                     "top_netsys_ppefb_250m_sel",
+                                     "top_netsys_warp_sel";
+                       assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
+                                         <&topckgen CLK_TOP_NETSYS_GSW_SEL>,
+                                         <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
+                                         <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
+                                         <&topckgen CLK_TOP_SGM_0_SEL>,
+                                         <&topckgen CLK_TOP_SGM_1_SEL>;
+                       assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
+                                                <&topckgen CLK_TOP_NET1PLL_D4>,
+                                                <&topckgen CLK_TOP_NET1PLL_D8_D4>,
+                                                <&topckgen CLK_TOP_NET1PLL_D8_D4>,
+                                                <&apmixedsys CLK_APMIXED_SGMPLL>,
+                                                <&apmixedsys CLK_APMIXED_SGMPLL>;
+                       mediatek,ethsys = <&ethsys>;
+                       mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
+                       mediatek,usxgmiisys = <&usxgmiisys0>, <&usxgmiisys1>;
+                       mediatek,xfi_pextp = <&xfi_pextp0>, <&xfi_pextp1>;
+                       mediatek,xfi_pll = <&xfi_pll>;
+                       mediatek,infracfg = <&topmisc>;
+                       mediatek,toprgu = <&watchdog>;
+                       #reset-cells = <1>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+       };
+};
index 63f898a9cd25114f47bd4e8abaa542d799175ee9..2fca00921b8caf1a09758c065de69886a7461f52 100644 (file)
@@ -26,6 +26,9 @@ mediatek_setup_interfaces()
        mediatek,mt7986b-rfb)
                ucidef_set_interfaces_lan_wan "lan0 lan1 lan2 lan3" eth1
                ;;
+       mediatek,mt7988a-dsa-10g-spim-snand)
+               ucidef_set_interfaces_lan_wan "lan0 lan1 lan2 lan3" "eth1 eth2"
+               ;;
        tplink,tl-xdr4288|\
        tplink,tl-xdr6088)
                ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 lan5" eth1
index 3e6a1654f20b8cef8b9164f29058ebd003ecc061..4cae8c50ac7427b7f4c060f99ed0dbb029051e9b 100644 (file)
@@ -360,6 +360,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_REGULATOR_MT6380=y
 CONFIG_REGULATOR_RT5190A=y
 CONFIG_RESET_CONTROLLER=y
+CONFIG_RESET_TI_SYSCON=y
 CONFIG_RFS_ACCEL=y
 CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
 CONFIG_RPS=y
index 92d1dcfad24991dbab9545a7e2a1bb6427836784..72adb490666414e490235c410fd7fed5a5dc0d07 100644 (file)
@@ -206,6 +206,24 @@ define Device/mediatek_mt7986b-rfb
 endef
 TARGET_DEVICES += mediatek_mt7986b-rfb
 
+define Device/mediatek_mt7988a-rfb-nand
+  DEVICE_VENDOR := MediaTek
+  DEVICE_MODEL := MT7988a nand rfb
+  DEVICE_DTS := mt7988a-dsa-10g-spim-nand
+  DEVICE_DTS_DIR := $(DTS_DIR)/
+  KERNEL_LOADADDR := 0x48000000
+  SUPPORTED_DEVICES := mediatek,mt7988a-rfb
+  UBINIZE_OPTS := -E 5
+  BLOCKSIZE := 128k
+  PAGESIZE := 2048
+  IMAGE_SIZE := 65536k
+  KERNEL_IN_UBI := 1
+  IMAGES += factory.bin
+  IMAGE/factory.bin := append-ubi | check-size $$$$(IMAGE_SIZE)
+  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
+endef
+TARGET_DEVICES += mediatek_mt7988a-rfb-nand
+
 define Device/tplink_tl-xdr-common
   DEVICE_VENDOR := TP-Link
   DEVICE_DTS_DIR := ../dts