target/linux/ramips/patches-5.10/322-mt7621-fix-cpu-clk-add-clkdev.patch

   1 --- a/arch/mips/include/asm/mach-ralink/mt7621.h
   2 +++ b/arch/mips/include/asm/mach-ralink/mt7621.h
   3 @@ -17,6 +17,10 @@
   4  #define SYSC_REG_CHIP_REV              0x0c
   5  #define SYSC_REG_SYSTEM_CONFIG0                0x10
   6  #define SYSC_REG_SYSTEM_CONFIG1                0x14
   7 +#define SYSC_REG_CLKCFG0               0x2c
   8 +#define SYSC_REG_CUR_CLK_STS           0x44
   9 +
  10 +#define MEMC_REG_CPU_PLL               0x648
  11
  12  #define CHIP_REV_PKG_MASK              0x1
  13  #define CHIP_REV_PKG_SHIFT             16
  14 @@ -24,6 +28,22 @@
  15  #define CHIP_REV_VER_SHIFT             8
  16  #define CHIP_REV_ECO_MASK              0xf
  17
  18 +#define XTAL_MODE_SEL_MASK             0x7
  19 +#define XTAL_MODE_SEL_SHIFT            6
  20 +
  21 +#define CPU_CLK_SEL_MASK               0x3
  22 +#define CPU_CLK_SEL_SHIFT              30
  23 +
  24 +#define CUR_CPU_FDIV_MASK              0x1f
  25 +#define CUR_CPU_FDIV_SHIFT             8
  26 +#define CUR_CPU_FFRAC_MASK             0x1f
  27 +#define CUR_CPU_FFRAC_SHIFT            0
  28 +
  29 +#define CPU_PLL_PREDIV_MASK            0x3
  30 +#define CPU_PLL_PREDIV_SHIFT           12
  31 +#define CPU_PLL_FBDIV_MASK             0x7f
  32 +#define CPU_PLL_FBDIV_SHIFT            4
  33 +
  34  #define MT7621_DRAM_BASE                0x0
  35  #define MT7621_DDR2_SIZE_MIN           32
  36  #define MT7621_DDR2_SIZE_MAX           256
  37 --- a/arch/mips/ralink/mt7621.c
  38 +++ b/arch/mips/ralink/mt7621.c
  39 @@ -10,6 +10,10 @@
  40  #include <linux/slab.h>
  41  #include <linux/sys_soc.h>
  42  #include <linux/jiffies.h>
  43 +#include <linux/clk.h>
  44 +#include <linux/clkdev.h>
  45 +#include <linux/clk-provider.h>
  46 +#include <dt-bindings/clock/mt7621-clk.h>
  47
  48  #include <asm/mipsregs.h>
  49  #include <asm/smp-ops.h>
  50 @@ -18,6 +22,7 @@
  51  #include <asm/mach-ralink/mt7621.h>
  52  #include <asm/mips-boards/launch.h>
  53  #include <asm/delay.h>
  54 +#include <asm/time.h>
  55
  56  #include <pinmux.h>
  57
  58 @@ -108,11 +113,89 @@ static struct rt2880_pmx_group mt7621_pi
  59         { 0 }
  60  };
  61
  62 +static struct clk *clks[MT7621_CLK_MAX];
  63 +static struct clk_onecell_data clk_data = {
  64 +       .clks = clks,
  65 +       .clk_num = ARRAY_SIZE(clks),
  66 +};
  67 +
  68  phys_addr_t mips_cpc_default_phys_base(void)
  69  {
  70         panic("Cannot detect cpc address");
  71  }
  72
  73 +static struct clk *__init mt7621_add_sys_clkdev(
  74 +       const char *id, unsigned long rate)
  75 +{
  76 +       struct clk *clk;
  77 +       int err;
  78 +
  79 +       clk = clk_register_fixed_rate(NULL, id, NULL, 0, rate);
  80 +       if (IS_ERR(clk))
  81 +               panic("failed to allocate %s clock structure", id);
  82 +
  83 +       err = clk_register_clkdev(clk, id, NULL);
  84 +       if (err)
  85 +               panic("unable to register %s clock device", id);
  86 +
  87 +       return clk;
  88 +}
  89 +
  90 +void __init ralink_clk_init(void)
  91 +{
  92 +       u32 syscfg, xtal_sel, clkcfg, clk_sel, curclk, ffiv, ffrac;
  93 +       u32 pll, prediv, fbdiv;
  94 +       u32 xtal_clk, cpu_clk, bus_clk;
  95 +       const static u32 prediv_tbl[] = {0, 1, 2, 2};
  96 +
  97 +       syscfg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
  98 +       xtal_sel = (syscfg >> XTAL_MODE_SEL_SHIFT) & XTAL_MODE_SEL_MASK;
  99 +
 100 +       clkcfg = rt_sysc_r32(SYSC_REG_CLKCFG0);
 101 +       clk_sel = (clkcfg >> CPU_CLK_SEL_SHIFT) & CPU_CLK_SEL_MASK;
 102 +
 103 +       curclk = rt_sysc_r32(SYSC_REG_CUR_CLK_STS);
 104 +       ffiv = (curclk >> CUR_CPU_FDIV_SHIFT) & CUR_CPU_FDIV_MASK;
 105 +       ffrac = (curclk >> CUR_CPU_FFRAC_SHIFT) & CUR_CPU_FFRAC_MASK;
 106 +
 107 +       if (xtal_sel <= 2)
 108 +               xtal_clk = 20 * 1000 * 1000;
 109 +       else if (xtal_sel <= 5)
 110 +               xtal_clk = 40 * 1000 * 1000;
 111 +       else
 112 +               xtal_clk = 25 * 1000 * 1000;
 113 +
 114 +       switch (clk_sel) {
 115 +       case 0:
 116 +               cpu_clk = 500 * 1000 * 1000;
 117 +               break;
 118 +       case 1:
 119 +               pll = rt_memc_r32(MEMC_REG_CPU_PLL);
 120 +               fbdiv = (pll >> CPU_PLL_FBDIV_SHIFT) & CPU_PLL_FBDIV_MASK;
 121 +               prediv = (pll >> CPU_PLL_PREDIV_SHIFT) & CPU_PLL_PREDIV_MASK;
 122 +               cpu_clk = ((fbdiv + 1) * xtal_clk) >> prediv_tbl[prediv];
 123 +               break;
 124 +       default:
 125 +               cpu_clk = xtal_clk;
 126 +       }
 127 +
 128 +       cpu_clk = cpu_clk / ffiv * ffrac;
 129 +       bus_clk = cpu_clk / 4;
 130 +
 131 +       clks[MT7621_CLK_CPU] = mt7621_add_sys_clkdev("cpu", cpu_clk);
 132 +       clks[MT7621_CLK_BUS] = mt7621_add_sys_clkdev("bus", bus_clk);
 133 +
 134 +       pr_info("CPU Clock: %dMHz\n", cpu_clk / 1000000);
 135 +       mips_hpt_frequency = cpu_clk / 2;
 136 +}
 137 +
 138 +static void __init mt7621_clocks_init_dt(struct device_node *np)
 139 +{
 140 +       of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 141 +}
 142 +
 143 +CLK_OF_DECLARE(mt7621, "mediatek,mt7621-pll", mt7621_clocks_init_dt);
 144 +
 145  void __init ralink_of_remap(void)
 146  {
 147         rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc");
 148 --- a/arch/mips/ralink/timer-gic.c
 149 +++ b/arch/mips/ralink/timer-gic.c
 150 @@ -9,14 +9,14 @@
 151
 152  #include <linux/of.h>
 153  #include <linux/of_clk.h>
 154 -#include <linux/clocksource.h>
 155 +#include <asm/time.h>
 156
 157  #include "common.h"
 158
 159  void __init plat_time_init(void)
 160  {
 161         ralink_of_remap();
 162 -
 163 +       ralink_clk_init();
 164         of_clk_init(NULL);
 165         timer_probe();
 166  }
 167 --- /dev/null
 168 +++ b/include/dt-bindings/clock/mt7621-clk.h
 169 @@ -0,0 +1,18 @@
 170 +/*
 171 + * Copyright (C) 2018 Weijie Gao <hackpascal@gmail.com>
 172 + *
 173 + * This program is free software; you can redistribute it and/or modify
 174 + * it under the terms of the GNU General Public License version 2 as
 175 + * published by the Free Software Foundation.
 176 + *
 177 + */
 178 +
 179 +#ifndef __DT_BINDINGS_MT7621_CLK_H
 180 +#define __DT_BINDINGS_MT7621_CLK_H
 181 +
 182 +#define MT7621_CLK_CPU         0
 183 +#define MT7621_CLK_BUS         1
 184 +
 185 +#define MT7621_CLK_MAX         2
 186 +
 187 +#endif /* __DT_BINDINGS_MT7621_CLK_H */