target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c

   1 /*   This program is free software; you can redistribute it and/or modify
   2  *   it under the terms of the GNU General Public License as published by
   3  *   the Free Software Foundation; version 2 of the License
   4  *
   5  *   This program is distributed in the hope that it will be useful,
   6  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
   7  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   8  *   GNU General Public License for more details.
   9  *
  10  *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
  11  *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
  12  *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/if_vlan.h>
  18 #include <linux/of_net.h>
  19
  20 #include <asm/mach-ralink/ralink_regs.h>
  21
  22 #include <mt7620.h>
  23 #include "mtk_eth_soc.h"
  24 #include "gsw_mt7620.h"
  25 #include "mt7530.h"
  26 #include "mdio.h"
  27
  28 #define MT7620A_CDMA_CSG_CFG    0x400
  29 #define MT7620_DMA_VID          (MT7620A_CDMA_CSG_CFG | 0x30)
  30 #define MT7620A_RESET_FE        BIT(21)
  31 #define MT7620A_RESET_ESW       BIT(23)
  32 #define MT7620_L4_VALID         BIT(23)
  33
  34 #define MT7620_TX_DMA_UDF       BIT(15)
  35 #define TX_DMA_FP_BMAP          ((0xff) << 19)
  36
  37 #define CDMA_ICS_EN             BIT(2)
  38 #define CDMA_UCS_EN             BIT(1)
  39 #define CDMA_TCS_EN             BIT(0)
  40
  41 #define GDMA_ICS_EN             BIT(22)
  42 #define GDMA_TCS_EN             BIT(21)
  43 #define GDMA_UCS_EN             BIT(20)
  44
  45 /* frame engine counters */
  46 #define MT7620_REG_MIB_OFFSET   0x1000
  47 #define MT7620_PPE_AC_BCNT0     (MT7620_REG_MIB_OFFSET + 0x00)
  48 #define MT7620_GDM1_TX_GBCNT    (MT7620_REG_MIB_OFFSET + 0x300)
  49 #define MT7620_GDM2_TX_GBCNT    (MT7620_GDM1_TX_GBCNT + 0x40)
  50
  51 #define GSW_REG_GDMA1_MAC_ADRL  0x508
  52 #define GSW_REG_GDMA1_MAC_ADRH  0x50C
  53
  54 #define MT7621_FE_RST_GL        (FE_FE_OFFSET + 0x04)
  55 #define MT7620_FE_INT_STATUS2   (FE_FE_OFFSET + 0x08)
  56
  57 /* FE_INT_STATUS reg on mt7620 define CNT_GDM1_AF at BIT(29)
  58  * but after test it should be BIT(13).
  59  */
  60 #define MT7620_FE_GDM1_AF       BIT(13)
  61
  62 static const u16 mt7620_reg_table[FE_REG_COUNT] = {
  63         [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
  64         [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
  65         [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
  66         [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
  67         [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
  68         [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
  69         [FE_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0,
  70         [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
  71         [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
  72         [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
  73         [FE_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0,
  74         [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
  75         [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
  76         [FE_REG_FE_DMA_VID_BASE] = MT7620_DMA_VID,
  77         [FE_REG_FE_COUNTER_BASE] = MT7620_GDM1_TX_GBCNT,
  78         [FE_REG_FE_RST_GL] = MT7621_FE_RST_GL,
  79         [FE_REG_FE_INT_STATUS2] = MT7620_FE_INT_STATUS2,
  80 };
  81
  82 static int mt7620_gsw_config(struct fe_priv *priv)
  83 {
  84         struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
  85
  86         /* is the mt7530 internal or external */
  87         if (priv->mii_bus && mdiobus_get_phy(priv->mii_bus, 0x1f)) {
  88                 mt7530_probe(priv->dev, gsw->base, NULL, 0);
  89                 mt7530_probe(priv->dev, NULL, priv->mii_bus, 1);
  90         } else {
  91                 mt7530_probe(priv->dev, gsw->base, NULL, 1);
  92         }
  93
  94         return 0;
  95 }
  96
  97 static void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac)
  98 {
  99         struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
 100         unsigned long flags;
 101
 102         spin_lock_irqsave(&priv->page_lock, flags);
 103         mtk_switch_w32(gsw, (mac[0] << 8) | mac[1], GSW_REG_SMACCR1);
 104         mtk_switch_w32(gsw, (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
 105                 GSW_REG_SMACCR0);
 106         spin_unlock_irqrestore(&priv->page_lock, flags);
 107 }
 108
 109 static void mt7620_auto_poll(struct mt7620_gsw *gsw, int port)
 110 {
 111         int phy;
 112         int lsb = -1, msb = 0;
 113
 114         for_each_set_bit(phy, &gsw->autopoll, 32) {
 115                 if (lsb < 0)
 116                         lsb = phy;
 117                 msb = phy;
 118         }
 119
 120         if (lsb == msb && port ==  4)
 121                 msb++;
 122         else if (lsb == msb && port ==  5)
 123                 lsb--;
 124
 125         mtk_switch_w32(gsw, PHY_AN_EN | PHY_PRE_EN | PMY_MDC_CONF(5) |
 126                 (msb << 8) | lsb, ESW_PHY_POLLING);
 127 }
 128
 129 static void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
 130 {
 131         struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
 132         const __be32 *_id = of_get_property(np, "reg", NULL);
 133         const __be32 *phy_addr;
 134         int phy_mode, size, id;
 135         int shift = 12;
 136         u32 val, mask = 0;
 137         u32 val_delay = 0;
 138         u32 mask_delay = GSW_REG_GPCx_TXDELAY | GSW_REG_GPCx_RXDELAY;
 139         int min = (gsw->port4 == PORT4_EPHY) ? (5) : (4);
 140
 141         if (!_id || (be32_to_cpu(*_id) < min) || (be32_to_cpu(*_id) > 5)) {
 142                 if (_id)
 143                         pr_err("%s: invalid port id %d\n", np->name,
 144                                be32_to_cpu(*_id));
 145                 else
 146                         pr_err("%s: invalid port id\n", np->name);
 147                 return;
 148         }
 149
 150         id = be32_to_cpu(*_id);
 151
 152         if (id == 4)
 153                 shift = 14;
 154
 155         priv->phy->phy_fixed[id] = of_get_property(np, "mediatek,fixed-link",
 156                                                    &size);
 157         if (priv->phy->phy_fixed[id] &&
 158             (size != (4 * sizeof(*priv->phy->phy_fixed[id])))) {
 159                 pr_err("%s: invalid fixed link property\n", np->name);
 160                 priv->phy->phy_fixed[id] = NULL;
 161                 return;
 162         }
 163
 164         phy_mode = of_get_phy_mode(np);
 165         switch (phy_mode) {
 166         case PHY_INTERFACE_MODE_RGMII:
 167                 mask = 0;
 168                 /* Do not touch rx/tx delay in this state to avoid problems with
 169                  * backward compability.
 170                  */
 171                 mask_delay = 0;
 172                 break;
 173         case PHY_INTERFACE_MODE_RGMII_ID:
 174                 mask = 0;
 175                 val_delay |= GSW_REG_GPCx_TXDELAY;
 176                 val_delay &= ~GSW_REG_GPCx_RXDELAY;
 177                 break;
 178         case PHY_INTERFACE_MODE_RGMII_RXID:
 179                 mask = 0;
 180                 val_delay &= ~GSW_REG_GPCx_TXDELAY;
 181                 val_delay &= ~GSW_REG_GPCx_RXDELAY;
 182                 break;
 183         case PHY_INTERFACE_MODE_RGMII_TXID:
 184                 mask = 0;
 185                 val_delay &= ~GSW_REG_GPCx_TXDELAY;
 186                 val_delay |= GSW_REG_GPCx_RXDELAY;
 187                 break;
 188         case PHY_INTERFACE_MODE_MII:
 189                 mask = 1;
 190                 break;
 191         case PHY_INTERFACE_MODE_RMII:
 192                 mask = 2;
 193                 break;
 194         default:
 195                 dev_err(priv->dev, "port %d - invalid phy mode\n", id);
 196                 return;
 197         }
 198
 199         priv->phy->phy_node[id] = of_parse_phandle(np, "phy-handle", 0);
 200         if (!priv->phy->phy_node[id] && !priv->phy->phy_fixed[id])
 201                 return;
 202
 203         val = rt_sysc_r32(SYSC_REG_CFG1);
 204         val &= ~(3 << shift);
 205         val |= mask << shift;
 206         rt_sysc_w32(val, SYSC_REG_CFG1);
 207
 208         if (id == 4) {
 209                 val = mtk_switch_r32(gsw, GSW_REG_GPC2);
 210                 val &= ~(mask_delay);
 211                 val |= val_delay & mask_delay;
 212                 mtk_switch_w32(gsw, val, GSW_REG_GPC2);
 213         }
 214         else if (id == 5) {
 215                 val = mtk_switch_r32(gsw, GSW_REG_GPC1);
 216                 val &= ~(mask_delay);
 217                 val |= val_delay & mask_delay;
 218                 mtk_switch_w32(gsw, val, GSW_REG_GPC1);
 219         }
 220
 221         if (priv->phy->phy_fixed[id]) {
 222                 const __be32 *link = priv->phy->phy_fixed[id];
 223                 int tx_fc, rx_fc;
 224                 u32 val = 0;
 225
 226                 priv->phy->speed[id] = be32_to_cpup(link++);
 227                 tx_fc = be32_to_cpup(link++);
 228                 rx_fc = be32_to_cpup(link++);
 229                 priv->phy->duplex[id] = be32_to_cpup(link++);
 230                 priv->link[id] = 1;
 231
 232                 switch (priv->phy->speed[id]) {
 233                 case SPEED_10:
 234                         val = 0;
 235                         break;
 236                 case SPEED_100:
 237                         val = 1;
 238                         break;
 239                 case SPEED_1000:
 240                         val = 2;
 241                         break;
 242                 default:
 243                         dev_err(priv->dev, "invalid link speed: %d\n",
 244                                 priv->phy->speed[id]);
 245                         priv->phy->phy_fixed[id] = 0;
 246                         return;
 247                 }
 248                 val = PMCR_SPEED(val);
 249                 val |= PMCR_LINK | PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
 250                         PMCR_TX_EN | PMCR_FORCE | PMCR_MAC_MODE | PMCR_IPG;
 251                 if (tx_fc)
 252                         val |= PMCR_TX_FC;
 253                 if (rx_fc)
 254                         val |= PMCR_RX_FC;
 255                 if (priv->phy->duplex[id])
 256                         val |= PMCR_DUPLEX;
 257                 mtk_switch_w32(gsw, val, GSW_REG_PORT_PMCR(id));
 258                 dev_info(priv->dev, "using fixed link parameters\n");
 259                 return;
 260         }
 261
 262         phy_addr = of_get_property(priv->phy->phy_node[id], "reg", NULL);
 263         if (phy_addr && mdiobus_get_phy(priv->mii_bus, be32_to_cpup(phy_addr))) {
 264                 u32 val = PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
 265                         PMCR_TX_EN |  PMCR_MAC_MODE | PMCR_IPG;
 266
 267                 mtk_switch_w32(gsw, val, GSW_REG_PORT_PMCR(id));
 268                 fe_connect_phy_node(priv, priv->phy->phy_node[id], id);
 269                 gsw->autopoll |= BIT(be32_to_cpup(phy_addr));
 270                 mt7620_auto_poll(gsw,id);
 271                 return;
 272         }
 273 }
 274
 275 static void mt7620_fe_reset(void)
 276 {
 277         fe_reset(MT7620A_RESET_FE | MT7620A_RESET_ESW);
 278 }
 279
 280 static void mt7620_rxcsum_config(bool enable)
 281 {
 282         if (enable)
 283                 fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) | (GDMA_ICS_EN |
 284                                         GDMA_TCS_EN | GDMA_UCS_EN),
 285                                 MT7620A_GDMA1_FWD_CFG);
 286         else
 287                 fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~(GDMA_ICS_EN |
 288                                         GDMA_TCS_EN | GDMA_UCS_EN),
 289                                 MT7620A_GDMA1_FWD_CFG);
 290 }
 291
 292 static void mt7620_txcsum_config(bool enable)
 293 {
 294         if (enable)
 295                 fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) | (CDMA_ICS_EN |
 296                                         CDMA_UCS_EN | CDMA_TCS_EN),
 297                                 MT7620A_CDMA_CSG_CFG);
 298         else
 299                 fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) & ~(CDMA_ICS_EN |
 300                                         CDMA_UCS_EN | CDMA_TCS_EN),
 301                                 MT7620A_CDMA_CSG_CFG);
 302 }
 303
 304 static int mt7620_fwd_config(struct fe_priv *priv)
 305 {
 306         struct net_device *dev = priv_netdev(priv);
 307
 308         fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~7, MT7620A_GDMA1_FWD_CFG);
 309
 310         mt7620_txcsum_config((dev->features & NETIF_F_IP_CSUM));
 311         mt7620_rxcsum_config((dev->features & NETIF_F_RXCSUM));
 312
 313         return 0;
 314 }
 315
 316 static void mt7620_tx_dma(struct fe_tx_dma *txd)
 317 {
 318 }
 319
 320 static void mt7620_init_data(struct fe_soc_data *data,
 321                              struct net_device *netdev)
 322 {
 323         struct fe_priv *priv = netdev_priv(netdev);
 324
 325         priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_RX_2B_OFFSET |
 326                 FE_FLAG_RX_SG_DMA | FE_FLAG_HAS_SWITCH;
 327
 328         netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
 329                 NETIF_F_HW_VLAN_CTAG_TX;
 330         if (mt7620_get_eco() >= 5)
 331                 netdev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
 332                         NETIF_F_IPV6_CSUM;
 333 }
 334
 335 static struct fe_soc_data mt7620_data = {
 336         .init_data = mt7620_init_data,
 337         .reset_fe = mt7620_fe_reset,
 338         .set_mac = mt7620_set_mac,
 339         .fwd_config = mt7620_fwd_config,
 340         .tx_dma = mt7620_tx_dma,
 341         .switch_init = mtk_gsw_init,
 342         .switch_config = mt7620_gsw_config,
 343         .port_init = mt7620_port_init,
 344         .reg_table = mt7620_reg_table,
 345         .pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS,
 346         .rx_int = RT5350_RX_DONE_INT,
 347         .tx_int = RT5350_TX_DONE_INT,
 348         .status_int = MT7620_FE_GDM1_AF,
 349         .checksum_bit = MT7620_L4_VALID,
 350         .has_carrier = mt7620_has_carrier,
 351         .mdio_read = mt7620_mdio_read,
 352         .mdio_write = mt7620_mdio_write,
 353         .mdio_adjust_link = mt7620_mdio_link_adjust,
 354 };
 355
 356 const struct of_device_id of_fe_match[] = {
 357         { .compatible = "mediatek,mt7620-eth", .data = &mt7620_data },
 358         {},
 359 };
 360
 361 MODULE_DEVICE_TABLE(of, of_fe_match);