--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/dts-v1/;
+
+#include "ipq8074.dtsi"
+#include "ipq8074-hk-cpu.dtsi"
+#include "ipq8074-ess.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "Linksys MX8500";
+ compatible = "linksys,mx8500", "qcom,ipq8074";
+
+ aliases {
+ serial0 = &blsp1_uart5;
+ serial1 = &blsp1_uart3;
+ led-boot = &led_system_blue;
+ led-running = &led_system_blue;
+ led-failsafe = &led_system_red;
+ led-upgrade = &led_system_green;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ bootargs-append = " root=/dev/ubiblock0_0 rootfstype=squashfs ro";
+ };
+
+ gpio_export {
+ compatible = "gpio-export";
+ #size-cells = <0>;
+
+ bt_pwr {
+ gpio-export,name = "bt_pwr";
+ gpio-export,output = <1>;
+ gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&button_pins>;
+ pinctrl-names = "default";
+
+ reset-button {
+ label = "reset";
+ gpios = <&tlmm 67 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+
+ wps-button {
+ label = "wps";
+ gpios = <&tlmm 64 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WPS_BUTTON>;
+ };
+ };
+};
+
+&tlmm {
+ button_pins: button-state {
+ pins = "gpio64", "gpio67";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ mdio_pins: mdio-state {
+ mdc-pins {
+ pins = "gpio68";
+ function = "mdc";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ mdio-pins {
+ pins = "gpio69";
+ function = "mdio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+};
+
+&blsp1_uart3 {
+ status = "okay";
+};
+
+&blsp1_uart5 {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&cryptobam {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
+&qpic_bam {
+ status = "okay";
+};
+
+&qpic_nand {
+ status = "okay";
+
+ /*
+ * Bootloader will find the NAND DT node by the compatible and
+ * then "fixup" it by adding the partitions from the SMEM table
+ * using the legacy bindings thus making it impossible for us
+ * to change the partition table or utilize NVMEM for calibration.
+ * So add a dummy partitions node that bootloader will populate
+ * and set it as disabled so the kernel ignores it instead of
+ * printing warnings due to the broken way bootloader adds the
+ * partitions.
+ */
+ partitions {
+ status = "disabled";
+ };
+
+ nand@0 {
+ reg = <0>;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-bus-width = <8>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "0:sbl1";
+ reg = <0x0 0x100000>;
+ read-only;
+ };
+
+ partition@100000 {
+ label = "0:mibib";
+ reg = <0x100000 0x100000>;
+ read-only;
+ };
+
+ partition@200000 {
+ label = "0:bootconfig";
+ reg = <0x200000 0x80000>;
+ read-only;
+ };
+
+ partition@280000 {
+ label = "0:bootconfig1";
+ reg = <0x280000 0x80000>;
+ read-only;
+ };
+
+ partition@300000 {
+ label = "0:qsee";
+ reg = <0x300000 0x300000>;
+ read-only;
+ };
+
+ partition@600000 {
+ label = "0:qsee_1";
+ reg = <0x600000 0x300000>;
+ read-only;
+ };
+
+ partition@900000 {
+ label = "0:devcfg";
+ reg = <0x900000 0x80000>;
+ read-only;
+ };
+
+ partition@980000 {
+ label = "0:devcfg_1";
+ reg = <0x980000 0x80000>;
+ read-only;
+ };
+
+ partition@a00000 {
+ label = "0:apdp";
+ reg = <0xa00000 0x80000>;
+ read-only;
+ };
+
+ partition@a80000 {
+ label = "0:apdp_1";
+ reg = <0xa80000 0x80000>;
+ read-only;
+ };
+
+ partition@b00000 {
+ label = "0:rpm";
+ reg = <0xb00000 0x80000>;
+ read-only;
+ };
+
+ partition@b80000 {
+ label = "0:rpm_1";
+ reg = <0xb80000 0x80000>;
+ read-only;
+ };
+
+ partition@c00000 {
+ label = "0:cdt";
+ reg = <0xc00000 0x80000>;
+ read-only;
+ };
+
+ partition@c80000 {
+ label = "0:cdt_1";
+ reg = <0xc80000 0x80000>;
+ read-only;
+ };
+
+ partition@d00000 {
+ label = "0:appsblenv";
+ reg = <0xd00000 0x80000>;
+ };
+
+ partition@d80000 {
+ label = "0:appsbl";
+ reg = <0xd80000 0x100000>;
+ read-only;
+ };
+
+ partition@e80000 {
+ label = "0:appsbl_1";
+ reg = <0xe80000 0x100000>;
+ read-only;
+ };
+
+ partition@f80000 {
+ label = "0:art";
+ reg = <0xf80000 0x80000>;
+ read-only;
+ };
+
+ partition@1000000 {
+ label = "u_env";
+ reg = <0x1000000 0x40000>;
+ };
+
+ partition@1040000 {
+ label = "s_env";
+ reg = <0x1040000 0x20000>;
+ };
+
+ partition@1060000 {
+ label = "devinfo";
+ reg = <0x1060000 0x20000>;
+ read-only;
+ };
+
+ partition@1080000 {
+ label = "kernel";
+ reg = <0x1080000 0x9600000>;
+ };
+
+ partition@1680000 {
+ label = "rootfs";
+ reg = <0x1680000 0x9000000>;
+ };
+
+ partition@a680000 {
+ label = "alt_kernel";
+ reg = <0xa680000 0x9600000>;
+ };
+
+ partition@ac80000 {
+ label = "alt_rootfs";
+ reg = <0xac80000 0x9000000>;
+ };
+
+ partition@13c80000 {
+ label = "sysdiag";
+ reg = <0x13c80000 0x200000>;
+ read-only;
+ };
+
+ partition@13e80000 {
+ label = "0:ethphyfw";
+ reg = <0x13e80000 0x100000>;
+ read-only;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aqr_fw: firmware@0 {
+ /* Skip the QCOM MBN Header of 40 bytes */
+ reg = <0x28 0x60002>;
+ };
+ };
+ };
+
+ partition@13f80000 {
+ label = "syscfg";
+ reg = <0x13f80000 0xb180000>;
+ read-only;
+ };
+
+ partition@1f100000 {
+ label = "app_data";
+ reg = <0x1f100000 0x500000>;
+ read-only;
+ };
+
+ partition@1f600000 {
+ label = "0:wififw";
+ reg = <0x1f600000 0xa00000>;
+ read-only;
+ };
+ };
+ };
+};
+
+&blsp1_i2c2 {
+ status = "okay";
+
+ led-controller@62 {
+ compatible = "nxp,pca9633";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x62>;
+ nxp,hw-blink;
+
+ led_system_red: led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_STATUS;
+ };
+
+ led_system_green: led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ };
+
+ led_system_blue: led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_STATUS;
+ };
+ };
+};
+
+&mdio {
+ status = "okay";
+
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
+
+ ethernet-phy-package@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "qcom,qca8075-package";
+ reg = <0>;
+
+ qcom,package-mode = "qsgmii";
+
+ qca8075_0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+
+ qca8075_1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+
+ qca8075_2: ethernet-phy@2 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <2>;
+ };
+
+ qca8075_3: ethernet-phy@3 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <3>;
+ };
+ };
+
+ aqr114c: ethernet-phy@8 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <8>;
+ reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
+ firmware-name = "marvell/AQR-G4_v5.6.5-AQR_WNC_SAQA-L2_GT_ID45287_VER24005.cld";
+ nvmem-cells = <&aqr_fw>;
+ nvmem-cell-names = "firmware";
+ };
+};
+
+&switch {
+ status = "okay";
+
+ switch_lan_bmp = <(ESS_PORT1 | ESS_PORT2 | ESS_PORT3 | ESS_PORT4)>; /* lan port bitmap */
+ switch_wan_bmp = <ESS_PORT6>; /* wan port bitmap */
+ switch_mac_mode = <MAC_MODE_QSGMII>; /* mac mode for uniphy instance0*/
+ switch_mac_mode2 = <MAC_MODE_USXGMII>; /* mac mode for uniphy instance2*/
+
+ qcom,port_phyinfo {
+ port@1 {
+ port_id = <1>;
+ phy_address = <0>;
+ };
+
+ port@2 {
+ port_id = <2>;
+ phy_address = <1>;
+ };
+
+ port@3 {
+ port_id = <3>;
+ phy_address = <2>;
+ };
+
+ port@4 {
+ port_id = <4>;
+ phy_address = <3>;
+ };
+
+ port@6 {
+ port_id = <6>;
+ phy_address = <8>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ ethernet-phy-ieee802.3-c45;
+ };
+ };
+};
+
+&edma {
+ status = "okay";
+};
+
+&dp1 {
+ status = "okay";
+ phy-mode = "qsgmii";
+ phy-handle = <&qca8075_0>;
+ label = "lan1";
+};
+
+&dp2 {
+ status = "okay";
+ phy-mode = "qsgmii";
+ phy-handle = <&qca8075_1>;
+ label = "lan2";
+};
+
+&dp3 {
+ status = "okay";
+ phy-mode = "qsgmii";
+ phy-handle = <&qca8075_2>;
+ label = "lan3";
+};
+
+&dp4 {
+ status = "okay";
+ phy-mode = "qsgmii";
+ phy-handle = <&qca8075_3>;
+ label = "lan4";
+};
+
+&dp6_syn {
+ status = "okay";
+ phy-mode = "usxgmii";
+ phy-handle = <&aqr114c>;
+ label = "wan";
+};
+
+&ssphy_0 {
+ status = "okay";
+};
+
+&qusb_phy_0 {
+ status = "okay";
+};
+
+&usb_0 {
+ status = "okay";
+};
+
+&pcie_qmp0 {
+ status = "okay";
+};
+
+&pcie0 {
+ status = "okay";
+
+ perst-gpio = <&tlmm 61 GPIO_ACTIVE_LOW>;
+
+ bridge@0,0 {
+ reg = <0x00000000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ wifi@1,0 {
+ status = "okay";
+
+ /* ath11k has no DT compatible for PCI cards */
+ compatible = "pci17cb,1104";
+ reg = <0x00010000 0 0 0 0>;
+
+ qcom,ath11k-calibration-variant = "Linksys-MX8500";
+ };
+ };
+};
+
+&wifi {
+ status = "okay";
+
+ qcom,ath11k-calibration-variant = "Linksys-MX8500";
+};
projects / openwrt / openwrt.git / commitdiff