plat/bcm/include/platform_def.h

   1 /*
   2  * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #ifndef __PLATFORM_DEF_H__
   8 #define __PLATFORM_DEF_H__
   9
  10 /* Following two defines needed to makes use of shared PMC driver code */
  11 #define _CFE_
  12 #define _ATF_
  13
  14 #include <arch.h>
  15 #include <common_def.h>
  16 #include <tbbr_img_def.h>
  17 #include <bcm_map_part.h>
  18 #include <bcm_mem_reserve.h>
  19
  20 #define PLAT_ARM_NS_IMAGE_BASE 0x0
  21
  22 #define PLATFORM_STACK_SIZE 0x1000
  23
  24 #define PLATFORM_MAX_CPUS_PER_CLUSTER   4
  25 #define PLATFORM_CLUSTER_COUNT          1
  26 #define PLATFORM_CLUSTER0_CORE_COUNT    PLATFORM_MAX_CPUS_PER_CLUSTER
  27 #define PLATFORM_CLUSTER1_CORE_COUNT    0
  28 #define PLATFORM_CORE_COUNT             (PLATFORM_CLUSTER0_CORE_COUNT + \
  29                                          PLATFORM_CLUSTER1_CORE_COUNT)
  30
  31 #define BRCM_PRIMARY_CPU                0
  32
  33 #define PLAT_NUM_PWR_DOMAINS            (PLATFORM_CLUSTER_COUNT + \
  34                                         PLATFORM_CORE_COUNT)
  35 #define PLAT_MAX_PWR_LVL                MPIDR_AFFLVL1
  36
  37 #define PLAT_MAX_RET_STATE              1
  38 #define PLAT_MAX_OFF_STATE              2
  39
  40 /* Local power state for power domains in Run state. */
  41 #define PLAT_LOCAL_STATE_RUN            0
  42 /* Local power state for retention. Valid only for CPU power domains */
  43 #define PLAT_LOCAL_STATE_RET            1
  44 /*
  45  * Local power state for OFF/power-down. Valid for CPU and cluster power
  46  * domains.
  47  */
  48 #define PLAT_LOCAL_STATE_OFF            2
  49
  50 /*
  51  * Macros used to parse state information from State-ID if it is using the
  52  * recommended encoding for State-ID.
  53  */
  54 #define PLAT_LOCAL_PSTATE_WIDTH         4
  55 #define PLAT_LOCAL_PSTATE_MASK          ((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1)
  56
  57 /*
  58  * Some data must be aligned on the biggest cache line size in the platform.
  59  * This is known only to the platform as it might have a combination of
  60  * integrated and external caches.
  61  */
  62 #define CACHE_WRITEBACK_SHIFT           6
  63 #define CACHE_WRITEBACK_GRANULE         (1 << CACHE_WRITEBACK_SHIFT)
  64
  65
  66 /*
  67  * BL3-1 specific defines.
  68  *
  69  * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the
  70  * current BL3-1 debug size plus a little space for growth.
  71  */
  72 #define BL31_BASE                       (CFG_ATF_AREA_ADDR)
  73 #define BL31_LIMIT                      (CFG_ATF_AREA_ADDR + CFG_ATF_AREA_SIZE)
  74
  75
  76 #define PLAT_ARM_NS_IMAGE_OFFSET        (0x0)
  77 #define PLAT_PHY_ADDR_SPACE_SIZE        (1ULL << 32)
  78 #define PLAT_VIRT_ADDR_SPACE_SIZE       (1ULL << 32)
  79
  80 /*
  81  * BL3-2 specific defines.
  82  *
  83  */
  84 #if defined(AARCH32)
  85 #define BL32_BASE                       BL31_BASE
  86 #define BL32_SIZE                       CFG_ATF_AREA_SIZE
  87 #define BL32_LIMIT                      BL31_LIMIT
  88 #define BL322_BASE                      (CFG_OPTEE_AREA_ADDR)
  89 #else
  90 #define BL32_BASE                       (CFG_OPTEE_AREA_ADDR)
  91 #define BL32_SIZE                       (CFG_OPTEE_AREA_SIZE)
  92 #define BL32_LIMIT                      (CFG_OPTEE_AREA_ADDR + CFG_OPTEE_AREA_SIZE)
  93 #endif
  94
  95 #define ADDR_SPACE_SIZE                 (1ull << 32)
  96 #define MAX_MMAP_REGIONS                10
  97 #define MAX_XLAT_TABLES                 16
  98 #define MAX_IO_DEVICES                  3
  99 #define MAX_IO_HANDLES                  4
 100
 101 #if defined BOOTLUT_PHYS_BASE
 102 #undef BOOTLUT_BASE
 103 #define BOOTLUT_BASE                    BOOTLUT_PHYS_BASE
 104 #else
 105 #define BOOTLUT_BASE                    0xffff0000
 106 #endif
 107
 108 #if !defined(BOOTLUT_SIZE)
 109 #define BOOTLUT_SIZE                    0x1000
 110 #endif
 111
 112 #if defined (BIUCFG_BASE)
 113 #undef  BIUCFG_BASE
 114 #define BIUCFG_BASE                     (BIUCFG_PHYS_BASE + BIUCFG_OFFSET)
 115 #elif defined (BIUCTRL_BASE)
 116 #undef  BIUCTRL_BASE
 117 #define BIUCTRL_BASE                    (URB_PHYS_BASE + URB_BIUCTRL_OFFSET)
 118 #define BIUCTRL_SIZE                    URB_SIZE
 119 #endif
 120
 121 #if defined (B15_CTRL_BASE)
 122 #undef B15_CTRL_BASE
 123 #define B15_CTRL_BASE B15_CTRL_PHYS_BASE
 124 #define B15_CTRL_SIZE 0x3000
 125 #endif
 126
 127 #undef TIMR_BASE
 128 #if defined (PLATFORM_FLAVOR_63158) || defined (PLATFORM_FLAVOR_63178) || defined (PLATFORM_FLAVOR_47622) || defined (PLATFORM_FLAVOR_6878) || defined (PLATFORM_FLAVOR_63146) || defined (PLATFORM_FLAVOR_4912) || defined (PLATFORM_FLAVOR_6756)
 129 #define UART0_BASE                      0xff812000
 130 #elif defined (PLATFORM_FLAVOR_6858) || defined (PLATFORM_FLAVOR_6856) || defined (PLATFORM_FLAVOR_4908) || defined (PLATFORM_FLAVOR_6846)
 131 #define UART0_BASE                      0xff800000
 132 #elif defined (PLATFORM_FLAVOR_63138) || defined (PLATFORM_FLAVOR_63148)
 133 #define TIMR_BASE       PERF_PHYS_BASE
 134 #define TIMR_SIZE       0x10000
 135 #define TIMR_OFFSET     0x80
 136
 137 #undef UART0_BASE
 138 /* 63138 and 63148 do not support PL011 UART.
 139    UART is needed only for debug print.
 140    For now, just use JTAG to debug these platforms.
 141 */
 142 #define UART0_BASE                      0x0
 143 #endif
 144 #define UART0_SIZE                      0x1000
 145 #define UART0_CLK_IN_HZ                 (50 * 1000 * 1000)
 146
 147
 148 #undef  PMC_BASE
 149 #if defined (PMC_OFFSET)
 150 #define PMC_BASE                        (PMC_PHYS_BASE + PMC_OFFSET)
 151 #else
 152 #define PMC_BASE                        (PMC_PHYS_BASE)
 153 #endif
 154
 155 #if defined(PROC_MON_BASE)
 156 #undef PROC_MON_BASE
 157 #if defined(PROC_MON_PHYS_BASE)
 158 #define PROC_MON_BASE           (PROC_MON_PHYS_BASE)
 159 #else
 160 #define PROC_MON_BASE           (PMC_PHYS_BASE + PROC_MON_OFFSET)
 161 #endif
 162 #endif
 163
 164 #undef PMC_SIZE
 165 #define PMC_SIZE                        0x00200000
 166
 167 #define PLAT_BCM_CRASH_UART_BASE        UART0_BASE
 168 #define PLAT_BCM_CRASH_UART_CLK_IN_HZ   UART0_CLK_IN_HZ
 169 #define PLAT_BCM_CONSOLE_BAUDRATE       115200
 170
 171 #define PLAT_ARM_CRASH_UART_BASE        PLAT_BCM_CRASH_UART_BASE
 172 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ   PLAT_BCM_CRASH_UART_CLK_IN_HZ
 173 #define ARM_CONSOLE_BAUDRATE    PLAT_BCM_CONSOLE_BAUDRATE
 174
 175 #define DEVICE0_BASE                    0x08000000
 176 #define DEVICE0_SIZE                    0x00021000
 177 #define DEVICE1_BASE                    0x09000000
 178 #define DEVICE1_SIZE                    0x00011000
 179
 180
 181 #if defined(WDTIMR0_BASE)
 182 #undef WDTIMR0_BASE
 183 #define WDTIMR0_BASE (PERF_PHYS_BASE+WDTIMR0_OFFSET)
 184 #define WDTIMR_BASE  (PERF_PHYS_BASE)
 185 #define WDTIMR_SIZE  0x4000
 186 #endif
 187
 188 /*
 189  * GIC related constants
 190  */
 191
 192 #undef GICD_BASE
 193 #undef GICC_BASE
 194 #undef SCU_BASE
 195 #if defined (PLATFORM_FLAVOR_63138) || defined (PLATFORM_FLAVOR_63148)
 196 #define GICD_BASE                       GICD_PHYS_BASE
 197 #define GICC_BASE                       GICC_PHYS_BASE
 198 #if defined (PLATFORM_FLAVOR_63138)
 199 #define SCU_BASE                        SCU_PHYS_BASE
 200 #endif
 201 #else
 202 #define GICD_BASE                       (GIC_PHYS_BASE + GICD_OFFSET)
 203 #define GICC_BASE                       (GIC_PHYS_BASE + GICC_OFFSET)
 204 #endif
 205
 206 #define GICR_BASE                       0
 207
 208
 209 #define BRCM_IRQ_SEC_SGI_0              8
 210 #define BRCM_IRQ_SEC_SGI_1              9
 211 #define BRCM_IRQ_SEC_SGI_2              10
 212 #define BRCM_IRQ_SEC_SGI_3              11
 213 #define BRCM_IRQ_SEC_SGI_4              12
 214 #define BRCM_IRQ_SEC_SGI_5              13
 215 #define BRCM_IRQ_SEC_SGI_6              14
 216 #define BRCM_IRQ_SEC_SGI_7              15
 217
 218 #if defined (PLATFORM_FLAVOR_63138)
 219 #define PL310_BASE              0x8001D000
 220 #define PL310_MAP_SIZE  0x00002000
 221
 222 #undef  SCU_BASE
 223 #define SCU_BASE                0x8001E000
 224 #define SCU_ERRATA744369        0x30
 225
 226 #define BIT32(nr)               (1 << (nr))
 227 /*
 228  * Outer cache iomem
 229  */
 230 #define PL310_LINE_SIZE         32
 231 #define PL310_8_WAYS            8
 232
 233 /* reg1 */
 234 #define PL310_CTRL              0x100
 235 #define PL310_AUX_CTRL          0x104
 236 #define PL310_TAG_RAM_CTRL      0x108
 237 #define PL310_DATA_RAM_CTRL     0x10C
 238 /* reg7 */
 239 #define PL310_SYNC              0x730
 240 #define PL310_INV_BY_WAY        0x77C
 241 #define PL310_CLEAN_BY_WAY      0x7BC
 242 #define PL310_FLUSH_BY_WAY      0x7FC
 243 #define PL310_INV_BY_PA         0x770
 244 #define PL310_CLEAN_BY_PA       0x7B0
 245 #define PL310_FLUSH_BY_PA       0x7F0
 246 #define PL310_FLUSH_BY_INDEXWAY 0x7F8
 247 /* reg9 */
 248 #define PL310_DCACHE_LOCKDOWN_BASE 0x900
 249 #define PL310_ICACHE_LOCKDOWN_BASE 0x904
 250 /* reg12 */
 251 #define PL310_ADDR_FILT_START   0xC00
 252 #define PL310_ADDR_FILT_END     0xC04
 253 /* reg15 */
 254 #define PL310_DEBUG_CTRL        0xF40
 255 #define PL310_PREFETCH_CTRL     0xF60
 256 #define PL310_POWER_CTRL        0xF80
 257
 258 #define PL310_CTRL_ENABLE_BIT   BIT32(0)
 259 #define PL310_AUX_16WAY_BIT     BIT32(16)
 260
 261 /*
 262  * PL310 TAG RAM Control Register
 263  *
 264  * bit[10:8]:1 - 2 cycle of write accesses latency
 265  * bit[6:4]:1 - 2 cycle of read accesses latency
 266  * bit[2:0]:1 - 2 cycle of setup latency
 267  */
 268 #ifndef PL310_TAG_RAM_CTRL_INIT
 269 #define PL310_TAG_RAM_CTRL_INIT         0x00000111
 270 #endif
 271
 272 /*
 273  * PL310 DATA RAM Control Register
 274  *
 275  * bit[10:8]:2 - 3 cycle of write accesses latency
 276  * bit[6:4]:2 - 3 cycle of read accesses latency
 277  * bit[2:0]:2 - 3 cycle of setup latency
 278  */
 279 #ifndef PL310_DATA_RAM_CTRL_INIT
 280 #define PL310_DATA_RAM_CTRL_INIT        0x00000111
 281 #endif
 282
 283 /*
 284  * PL310 Auxiliary Control Register
 285  *
 286  * I/Dcache prefetch enabled (bit29:28=2b11)
 287  * NS can access interrupts (bit27=1)
 288  * NS can lockown cache lines (bit26=1)
 289  * Pseudo-random replacement policy (bit25=0)
 290  * Force write allocated (default)
 291  * Shared attribute internally ignored (bit22=1, bit13=0)
 292  * Parity disabled (bit21=0)
 293  * Event monitor disabled (bit20=0)
 294  * Platform fmavor specific way config (dual / quad):
 295  * - 64kb way size (bit19:17=3b011)
 296  * - 16-way associciativity (bit16=1)
 297  * Platform fmavor specific way config (dual lite / solo):
 298  * - 32kb way size (bit19:17=3b010)
 299  * - no 16-way associciativity (bit16=0)
 300  * Store buffer device limitation enabled (bit11=1)
 301  * Cacheable accesses have high prio (bit10=0)
 302  * Full Line Zero (FLZ) disabled (bit0=0)
 303  */
 304
 305 #define PL310_AUX_CTRL_INIT             0x4e450001
 306
 307 /*
 308  * PL310 Prefetch Control Register
 309  *
 310  * Double linefill disabled (bit30=0)
 311  * I/D prefetch enabled (bit29:28=2b11)
 312  * Prefetch drop enabled (bit24=1)
 313  * Incr double linefill disable (bit23=0)
 314  * Prefetch offset = 7 (bit4:0)
 315  */
 316 #define PL310_PREFETCH_CTRL_INIT        0x31000007
 317
 318 /*
 319  * PL310 Power Register
 320  *
 321  * Dynamic clock gating enabled
 322  * Standby mode enabled
 323  */
 324 #define PL310_POWER_CTRL_INIT           0x00000003
 325
 326 #define GICC_CTLR_OFFSET                0x0
 327 #define GICC_PMR_OFFSET                 0x4
 328 #define GICD_CTLR_OFFSET                0x0
 329 #define GICD_TYPER_OFFSET               0x4
 330 #define GICD_IGROUPR0_OFFSET            0x80
 331
 332 #endif
 333
 334 /*
 335  * System counter
 336  */
 337 #define SYS_COUNTER_FREQ_IN_TICKS       (50 * 1000 * 1000)
 338
 339 #endif /* __PLATFORM_DEF_H__ */