realtek: add image and device tree for ZYXEL XS1930 family

dts from Sebastian Gottschall <s.gottschall@dd-wrt.com>'s pie-5.10 tree
with fixed MTD partitions.
Use default image generation code which works with stock loader for
initramfs image.
Add CONFIG_AQUANTIA_PHY=y to kernel config to enable driver for AQR813
8-port PHY found as well as the AQR113C PHYs single port ones found in
the -12 version of the device.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>

diff --git a/target/linux/realtek/dts-5.10/rtl9313_zyxel_xs1930.dts b/target/linux/realtek/dts-5.10/rtl9313_zyxel_xs1930.dts
new file mode 100644 (file)
index 0000000..8e47848
--- /dev/null
+++ b/target/linux/realtek/dts-5.10/rtl9313_zyxel_xs1930.dts
@@ -0,0 +1,341 @@
+/dts-v1/;
+
+#include "rtl931x.dtsi"
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+       compatible = "zyxel,xs1930", "realtek,rtl838x-soc";
+       model = "Zyxel XS1930-12";
+/*
+       aliases {
+               led-boot = &led_sys;
+               led-failsafe = &led_sys;
+               led-running = &led_sys;
+               led-upgrade = &led_sys;
+       };
+*/
+       chosen {
+               bootargs = "console=ttyS0,115200";
+       };
+/*
+       leds {
+               compatible = "gpio-leds";
+
+               led_sys: sys {
+                       label = "gs1900_46:green:sys";
+                       gpios = <&gpio0 46 GPIO_ACTIVE_HIGH>;
+               };
+       }; */
+
+       /* I2C busses and SFP cages: all pins unknown, needs probing
+       i2c0: i2c-rtl9310 {
+               compatible = "realtek,rtl9310-i2c";
+               reg = <0x1b00100c 0x3c>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               sda-pin = <10>;
+               scl-pin = <8>;
+               clock-frequency = <100000>;
+       };
+
+       i2c1: i2c-rtl9310 {
+               compatible = "realtek,rtl9310-i2c";
+               reg = <0x1b001024 0x3c>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               sda-pin = <10>;
+               scl-pin = <8>;
+               clock-frequency = <100000>;
+       };
+
+       sfp0: sfp-p11 {
+               compatible = "sff,sfp";
+               i2c-bus = <&i2c0>;
+               los-gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>;
+               tx-fault-gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>;
+               mod-def0-gpio = <&gpio0 16 GPIO_ACTIVE_LOW>;
+               tx-disable-gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>;
+       };
+
+       sfp1: sfp-p12 {
+               compatible = "sff,sfp";
+               i2c-bus = <&i2c1>;
+               los-gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>;
+               tx-fault-gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>;
+               mod-def0-gpio = <&gpio0 16 GPIO_ACTIVE_LOW>;
+               tx-disable-gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>;
+       }; */
+
+       led_set: led_set@0 {
+               compatible = "realtek,rtl9300-leds";
+               led_set0 = <0xffff 0xa0b 0x0aa8 0xa82>;
+       };
+};
+
+/*
+&gpio0 {
+       indirect-access-bus-id = <0>;
+};
+*/
+
+&spi0 {
+       status = "okay";
+       flash@0 {
+               compatible = "jedec,spi-nor";
+               reg = <0>;
+               spi-max-frequency = <10000000>;
+
+               partitions {
+                       compatible = "fixed-partitions";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       partition@0 {
+                               label = "boot";
+                               reg = <0x0 0xa0000>;
+                               read-only;
+                       };
+
+/*
+ * not possible due to 64k sector size, we'd need to use 4k sectors for those:
+ *                     partition@9e000 {
+ *                             label = "u-boot-env";
+ *                             reg = <0x9e000 0x1000>;
+ *                     };
+ *                     partition@9f000 {
+ *                             label = "devinfo";
+ *                             reg = <0x9f000 0x1000>;
+ *                             read-only;
+ *                     };
+ */
+
+                       partition@a0000 {
+                               label = "firmware";
+                               reg = <0xa0000 0xf60000>;
+                       };
+
+                       partition@1000000 {
+                               label = "boot2";
+                               reg = <0x1000000 0xa0000>;
+                               read-only;
+                       };
+
+                       partition@10a0000 {
+                               label = "runtime2";
+                               reg = <0x10a0000 0xf60000>;
+                       };
+
+               };
+       };
+};
+
+&ethernet0 {
+       mdio: mdio-bus {
+               compatible = "realtek,rtl838x-mdio";
+               regmap = <&ethernet0>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               /* External phy ARQ813 8-port package */
+               phy0: ethernet-phy@0 {
+                       reg = <0>;
+                       compatible = "ethernet-phy-ieee802.3-c45";
+                       rtl9300,smi-address = <0 8>;
+                       sds = <2>;
+               };
+               phy1: ethernet-phy@1 {
+                       reg = <8>;
+                       compatible = "ethernet-phy-ieee802.3-c45";
+                       rtl9300,smi-address = <0 9>;
+                       sds = <3>;
+               };
+               phy2: ethernet-phy@2 {
+                       reg = <16>;
+                       compatible = "ethernet-phy-ieee802.3-c45";
+                       rtl9300,smi-address = <0 10>;
+                       sds = <4>;
+               };
+               phy3: ethernet-phy@3 {
+                       reg = <24>;
+                       compatible = "ethernet-phy-ieee802.3-c45";
+                       rtl9300,smi-address = <0 11>;
+                       sds = <5>;
+               };
+               phy4: ethernet-phy@4 {
+                       reg = <32>;
+                       compatible = "ethernet-phy-ieee802.3-c45";
+                       rtl9300,smi-address = <0 12>;
+                       sds = <6>;
+               };
+               phy5: ethernet-phy@5 {
+                       reg = <40>;
+                       compatible = "ethernet-phy-ieee802.3-c45";
+                       rtl9300,smi-address = <0 13>;
+                       sds = <7>;
+               };
+               phy6: ethernet-phy@6 {
+                       reg = <48>;
+                       compatible = "ethernet-phy-ieee802.3-c45";
+                       rtl9300,smi-address = <0 14>;
+                       sds = <8>;
+               };
+               phy7: ethernet-phy@7 {
+                       reg = <50>;
+                       compatible = "ethernet-phy-ieee802.3-c45";
+                       rtl9300,smi-address = <0 15>;
+                       sds = <9>;
+               };
+
+               /* External phy ARQ113C */
+               phy8: ethernet-phy@8 {
+                       reg = <52>;
+                       compatible = "ethernet-phy-ieee802.3-c45";
+                       rtl9300,smi-address = <1 0>;
+                       sds = <10>;
+               };
+
+               /* External phy ARQ113C */
+               phy9: ethernet-phy@9 {
+                       reg = <53>;
+                       compatible = "ethernet-phy-ieee802.3-c45";
+                       rtl9300,smi-address = <2 8>;
+                       sds = <11>;
+               };
+
+               /* SFP+ cages
+               phy54: ethernet-phy@54 {
+                       reg = <54>;
+                       compatible = "ethernet-phy-ieee802.3-c22";
+                       phy-is-integrated;
+                       sds = <12>;
+                       sfp = <&sfp0>;
+               };
+
+               phy55: ethernet-phy@55 {
+                       reg = <55>;
+                       compatible = "ethernet-phy-ieee802.3-c22";
+                       phy-is-integrated;
+                       sds = <13>;
+                       sfp = <&sfp1>;
+               }; */
+       };
+};
+
+&switch0 {
+       ports {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               port@0 {
+                       reg = <0>;
+                       label = "lan1";
+                       phy-handle = <&phy0>;
+                       phy-mode = "usxgmii";
+                       led-set = <0>;
+               };
+               port@8 {
+                       reg = <8>;
+                       label = "lan2";
+                       phy-handle = <&phy1>;
+                       phy-mode = "usxgmii";
+                       led-set = <0>;
+               };
+               port@16 {
+                       reg = <16>;
+                       label = "lan3";
+                       phy-handle = <&phy2>;
+                       phy-mode = "usxgmii";
+                       led-set = <0>;
+               };
+               port@24 {
+                       reg = <24>;
+                       label = "lan4";
+                       phy-handle = <&phy3>;
+                       phy-mode = "usxgmii";
+                       led-set = <0>;
+               };
+               port@32 {
+                       reg = <32>;
+                       label = "lan5";
+                       phy-handle = <&phy4>;
+                       phy-mode = "usxgmii";
+                       rx-polarity-invers;
+                       tx-polarity-invers;
+                       led-set = <0>;
+               };
+               port@40 {
+                       reg = <40>;
+                       label = "lan6";
+                       phy-handle = <&phy5>;
+                       phy-mode = "usxgmii";
+                       rx-polarity-invers;
+                       tx-polarity-invers;
+                       led-set = <0>;
+               };
+               port@48 {
+                       reg = <48>;
+                       label = "lan7";
+                       phy-handle = <&phy6>;
+                       phy-mode = "usxgmii";
+                       rx-polarity-invers;
+                       tx-polarity-invers;
+                       led-set = <0>;
+               };
+               port@50 {
+                       reg = <50>;
+                       label = "lan8";
+                       phy-handle = <&phy7>;
+                       phy-mode = "usxgmii";
+                       rx-polarity-invers;
+                       tx-polarity-invers;
+                       led-set = <0>;
+               };
+               port@52 {
+                       reg = <52>;
+                       label = "lan9";
+                       phy-mode = "usxgmii";
+                       phy-handle = <&phy8>;
+                       tx-polarity-invers;
+                       led-set = <0>;
+               };
+               port@53 {
+                       reg = <53>;
+                       label = "lan10";
+                       phy-mode = "usxgmii";
+                       phy-handle = <&phy9>;
+                       tx-polarity-invers;
+                       led-set = <0>;
+               };
+
+               /* SFP cages
+               port@54 {
+                       reg = <54>;
+                       label = "lan11";
+                       phy-mode = "internal";
+                       phy-handle = <&phy54>;
+                       tx-polarity-invers;
+                       led-set = <0>;
+               };
+               port@55 {
+                       reg = <55>;
+                       label = "lan12";
+                       phy-mode = "internal";
+                       phy-handle = <&phy55>;
+                       tx-polarity-invers;
+                       led-set = <0>;
+               }; */
+
+               /* CPU-Port */
+               port@56 {
+                       ethernet = <&ethernet0>;
+                       reg = <56>;
+                       phy-mode = "qsgmii";
+                       fixed-link {
+                               speed = <1000>;
+                               full-duplex;
+                       };
+               };
+       };
+};

diff --git a/target/linux/realtek/image/rtl931x.mk b/target/linux/realtek/image/rtl931x.mk
index a4e40e534e6a84db241abfe5076962a90f8a71bd..70a5b1b0ea4230a2c740d2ad59f85586b85d506c 100644 (file)
--- a/target/linux/realtek/image/rtl931x.mk
+++ b/target/linux/realtek/image/rtl931x.mk
@@ -1 +1,15 @@
 # SPDX-License-Identifier: GPL-2.0-only
+
+define Device/zyxel_xs1930
+  KERNEL_LOADADDR = 0x80220000
+  KERNEL_ENTRY = 0x80220000
+  SOC := rtl9313
+  IMAGE_SIZE := 14336k
+  DEVICE_VENDOR := ZyXEL
+  DEVICE_MODEL := XS1930 series
+  ZYXEL_VERS := ABQF
+  DEVICE_PACKAGES := ip-bridge ethtool
+  KERNEL_INITRAMFS := kernel-bin | append-dtb | gzip | zyxel-vers $$$$(ZYXEL_VERS) | \
+       uImage gzip
+endef
+TARGET_DEVICES += zyxel_xs1930

diff --git a/target/linux/realtek/rtl931x/config-5.10 b/target/linux/realtek/rtl931x/config-5.10
index ac60938ddce343d7d761ab64390e07eaaa6e7c28..a4d7a41f93fb3eccddf72803cb80ee8763de62ca 100644 (file)
--- a/target/linux/realtek/rtl931x/config-5.10
+++ b/target/linux/realtek/rtl931x/config-5.10
@@ -1,3 +1,4 @@
+CONFIG_AQUANTIA_PHY=y
 CONFIG_ARCH_32BIT_OFF_T=y
 CONFIG_ARCH_HIBERNATION_POSSIBLE=y
 CONFIG_ARCH_MMAP_RND_BITS_MAX=15