target/linux/bcm63xx/patches-5.4/441-mtd-rawnand-brcmnand-support-v2.1-v2.2-controllers.patch

   1 --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
   2 +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
   3 @@ -196,6 +196,7 @@ struct brcmnand_controller {
   4         const unsigned int      *block_sizes;
   5         unsigned int            max_page_size;
   6         const unsigned int      *page_sizes;
   7 +       unsigned int            page_size_shift;
   8         unsigned int            max_oob;
   9         u32                     features;
  10
  11 @@ -269,6 +270,36 @@ enum brcmnand_reg {
  12         BRCMNAND_FC_BASE,
  13  };
  14
  15 +/* BRCMNAND v2.1-v2.2 */
  16 +static const u16 brcmnand_regs_v21[] = {
  17 +       [BRCMNAND_CMD_START]            =  0x04,
  18 +       [BRCMNAND_CMD_EXT_ADDRESS]      =  0x08,
  19 +       [BRCMNAND_CMD_ADDRESS]          =  0x0c,
  20 +       [BRCMNAND_INTFC_STATUS]         =  0x5c,
  21 +       [BRCMNAND_CS_SELECT]            =  0x14,
  22 +       [BRCMNAND_CS_XOR]               =  0x18,
  23 +       [BRCMNAND_LL_OP]                =     0,
  24 +       [BRCMNAND_CS0_BASE]             =  0x40,
  25 +       [BRCMNAND_CS1_BASE]             =     0,
  26 +       [BRCMNAND_CORR_THRESHOLD]       =     0,
  27 +       [BRCMNAND_CORR_THRESHOLD_EXT]   =     0,
  28 +       [BRCMNAND_UNCORR_COUNT]         =     0,
  29 +       [BRCMNAND_CORR_COUNT]           =     0,
  30 +       [BRCMNAND_CORR_EXT_ADDR]        =  0x60,
  31 +       [BRCMNAND_CORR_ADDR]            =  0x64,
  32 +       [BRCMNAND_UNCORR_EXT_ADDR]      =  0x68,
  33 +       [BRCMNAND_UNCORR_ADDR]          =  0x6c,
  34 +       [BRCMNAND_SEMAPHORE]            =  0x50,
  35 +       [BRCMNAND_ID]                   =  0x54,
  36 +       [BRCMNAND_ID_EXT]               =     0,
  37 +       [BRCMNAND_LL_RDATA]             =     0,
  38 +       [BRCMNAND_OOB_READ_BASE]        =  0x20,
  39 +       [BRCMNAND_OOB_READ_10_BASE]     =     0,
  40 +       [BRCMNAND_OOB_WRITE_BASE]       =  0x30,
  41 +       [BRCMNAND_OOB_WRITE_10_BASE]    =     0,
  42 +       [BRCMNAND_FC_BASE]              = 0x200,
  43 +};
  44 +
  45  /* BRCMNAND v3.3-v4.0 */
  46  static const u16 brcmnand_regs_v33[] = {
  47         [BRCMNAND_CMD_START]            =  0x04,
  48 @@ -467,6 +498,9 @@ enum {
  49         CFG_BUS_WIDTH                   = BIT(CFG_BUS_WIDTH_SHIFT),
  50         CFG_DEVICE_SIZE_SHIFT           = 24,
  51
  52 +       /* Only for v2.1 */
  53 +       CFG_PAGE_SIZE_SHIFT_v2_1        = 30,
  54 +
  55         /* Only for pre-v7.1 (with no CFG_EXT register) */
  56         CFG_PAGE_SIZE_SHIFT             = 20,
  57         CFG_BLK_SIZE_SHIFT              = 28,
  58 @@ -502,12 +536,16 @@ static int brcmnand_revision_init(struct
  59  {
  60         static const unsigned int block_sizes_v6[] = { 8, 16, 128, 256, 512, 1024, 2048, 0 };
  61         static const unsigned int block_sizes_v4[] = { 16, 128, 8, 512, 256, 1024, 2048, 0 };
  62 +       static const unsigned int block_sizes_v2_2[] = { 16, 128, 8, 512, 256, 0 };
  63 +       static const unsigned int block_sizes_v2_1[] = { 16, 128, 8, 512, 0 };
  64         static const unsigned int page_sizes_v3_4[] = { 512, 2048, 4096, 8192, 0 };
  65 +       static const unsigned int page_sizes_v2_2[] = { 512, 2048, 4096, 0 };
  66 +       static const unsigned int page_sizes_v2_1[] = { 512, 2048, 0 };
  67
  68         ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff;
  69
  70 -       /* Only support v4.0+? */
  71 -       if (ctrl->nand_version < 0x0400) {
  72 +       /* Only support v2.1+ */
  73 +       if (ctrl->nand_version < 0x0201) {
  74                 dev_err(ctrl->dev, "version %#x not supported\n",
  75                         ctrl->nand_version);
  76                 return -ENODEV;
  77 @@ -524,6 +562,8 @@ static int brcmnand_revision_init(struct
  78                 ctrl->reg_offsets = brcmnand_regs_v50;
  79         else if (ctrl->nand_version >= 0x0303)
  80                 ctrl->reg_offsets = brcmnand_regs_v33;
  81 +       else if (ctrl->nand_version >= 0x0201)
  82 +               ctrl->reg_offsets = brcmnand_regs_v21;
  83
  84         /* Chip-select stride */
  85         if (ctrl->nand_version >= 0x0701)
  86 @@ -549,14 +589,32 @@ static int brcmnand_revision_init(struct
  87                 ctrl->max_page_size = 16 * 1024;
  88                 ctrl->max_block_size = 2 * 1024 * 1024;
  89         } else {
  90 -               ctrl->page_sizes = page_sizes_v3_4;
  91 +               if (ctrl->nand_version >= 0x0304)
  92 +                       ctrl->page_sizes = page_sizes_v3_4;
  93 +               else if (ctrl->nand_version >= 0x0202)
  94 +                       ctrl->page_sizes = page_sizes_v2_2;
  95 +               else
  96 +                       ctrl->page_sizes = page_sizes_v2_1;
  97 +
  98 +               if (ctrl->nand_version >= 0x0202)
  99 +                       ctrl->page_size_shift = CFG_PAGE_SIZE_SHIFT;
 100 +               else
 101 +                       ctrl->page_size_shift = CFG_PAGE_SIZE_SHIFT_v2_1;
 102 +
 103                 if (ctrl->nand_version >= 0x0600)
 104                         ctrl->block_sizes = block_sizes_v6;
 105 -               else
 106 +               else if (ctrl->nand_version >= 0x0400)
 107                         ctrl->block_sizes = block_sizes_v4;
 108 +               else if (ctrl->nand_version >= 0x0202)
 109 +                       ctrl->block_sizes = block_sizes_v2_2;
 110 +               else
 111 +                       ctrl->block_sizes = block_sizes_v2_1;
 112
 113                 if (ctrl->nand_version < 0x0400) {
 114 -                       ctrl->max_page_size = 4096;
 115 +                       if (ctrl->nand_version < 0x0202)
 116 +                               ctrl->max_page_size = 2048;
 117 +                       else
 118 +                               ctrl->max_page_size = 4096;
 119                         ctrl->max_block_size = 512 * 1024;
 120                 }
 121         }
 122 @@ -724,6 +782,9 @@ static void brcmnand_wr_corr_thresh(stru
 123         enum brcmnand_reg reg = BRCMNAND_CORR_THRESHOLD;
 124         int cs = host->cs;
 125
 126 +       if (!ctrl->reg_offsets[reg])
 127 +               return;
 128 +
 129         if (ctrl->nand_version == 0x0702)
 130                 bits = 7;
 131         else if (ctrl->nand_version >= 0x0600)
 132 @@ -782,8 +843,10 @@ static inline u32 brcmnand_spare_area_ma
 133                 return GENMASK(7, 0);
 134         else if (ctrl->nand_version >= 0x0600)
 135                 return GENMASK(6, 0);
 136 -       else
 137 +       else if (ctrl->nand_version >= 0x0303)
 138                 return GENMASK(5, 0);
 139 +       else
 140 +               return GENMASK(4, 0);
 141  }
 142
 143  #define NAND_ACC_CONTROL_ECC_SHIFT     16
 144 @@ -2146,7 +2209,7 @@ static int brcmnand_set_cfg(struct brcmn
 145                 (!!(cfg->device_width == 16) << CFG_BUS_WIDTH_SHIFT) |
 146                 (device_size << CFG_DEVICE_SIZE_SHIFT);
 147         if (cfg_offs == cfg_ext_offs) {
 148 -               tmp |= (page_size << CFG_PAGE_SIZE_SHIFT) |
 149 +               tmp |= (page_size << ctrl->page_size_shift) |
 150                        (block_size << CFG_BLK_SIZE_SHIFT);
 151                 nand_writereg(ctrl, cfg_offs, tmp);
 152         } else {
 153 @@ -2158,9 +2221,11 @@ static int brcmnand_set_cfg(struct brcmn
 154
 155         tmp = nand_readreg(ctrl, acc_control_offs);
 156         tmp &= ~brcmnand_ecc_level_mask(ctrl);
 157 -       tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT;
 158         tmp &= ~brcmnand_spare_area_mask(ctrl);
 159 -       tmp |= cfg->spare_area_size;
 160 +       if (ctrl->nand_version >= 0x0302) {
 161 +               tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT;
 162 +               tmp |= cfg->spare_area_size;
 163 +       }
 164         nand_writereg(ctrl, acc_control_offs, tmp);
 165
 166         brcmnand_set_sector_size_1k(host, cfg->sector_size_1k);
 167 @@ -2524,6 +2589,8 @@ const struct dev_pm_ops brcmnand_pm_ops
 168  EXPORT_SYMBOL_GPL(brcmnand_pm_ops);
 169
 170  static const struct of_device_id brcmnand_of_match[] = {
 171 +       { .compatible = "brcm,brcmnand-v2.1" },
 172 +       { .compatible = "brcm,brcmnand-v2.2" },
 173         { .compatible = "brcm,brcmnand-v4.0" },
 174         { .compatible = "brcm,brcmnand-v5.0" },
 175         { .compatible = "brcm,brcmnand-v6.0" },