mediatek: mt7988a.dtsi: add interrupts to GE switch PHYs
authorDaniel Golle <daniel@makrotopia.org>
Wed, 8 May 2024 13:51:54 +0000 (14:51 +0100)
committerDaniel Golle <daniel@makrotopia.org>
Wed, 8 May 2024 21:19:26 +0000 (22:19 +0100)
The way to register the switch MDIO bus and PHYs on the bus in upstream
Linux is more strict and requires each PHY to explicitely state the
interrupt instead of assuming it in case the 'interrupts' property in DT
is missing.

Add missing interrupts for the PHYs of the build-in 4x1GE switch of the
MT7988 SoC.

Fixes: 4354b34f6f ("generic: 6.6: sync mt7530 DSA driver with upstream")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
target/linux/mediatek/files-6.6/arch/arm64/boot/dts/mediatek/mt7988a.dtsi

index db2b85c1818dff7f53b9b9f4d027799da7551f9a..af4dcb358135e01c8dfc8e4721ae12f720a7cba9 100644 (file)
                                gsw_phy0: ethernet-phy@0 {
                                        compatible = "ethernet-phy-ieee802.3-c22";
                                        reg = <0>;
+                                       interrupts = <0>;
                                        phy-mode = "internal";
                                        nvmem-cells = <&phy_calibration_p0>;
                                        nvmem-cell-names = "phy-cal-data";
                                gsw_phy1: ethernet-phy@1 {
                                        compatible = "ethernet-phy-ieee802.3-c22";
                                        reg = <1>;
+                                       interrupts = <1>;
                                        phy-mode = "internal";
                                        nvmem-cells = <&phy_calibration_p1>;
                                        nvmem-cell-names = "phy-cal-data";
                                gsw_phy2: ethernet-phy@2 {
                                        compatible = "ethernet-phy-ieee802.3-c22";
                                        reg = <2>;
+                                       interrupts = <2>;
                                        phy-mode = "internal";
                                        nvmem-cells = <&phy_calibration_p2>;
                                        nvmem-cell-names = "phy-cal-data";
                                gsw_phy3: ethernet-phy@3 {
                                        compatible = "ethernet-phy-ieee802.3-c22";
                                        reg = <3>;
+                                       interrupts = <3>;
                                        phy-mode = "internal";
                                        nvmem-cells = <&phy_calibration_p3>;
                                        nvmem-cell-names = "phy-cal-data";