1 From 21bdcd324f769545b1765fe391d939a1edd07cbb Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Wed, 20 Jan 2016 09:55:08 +0100
4 Subject: [PATCH 039/102] soc: mediatek: PMIC wrap: add a slave specific
7 This patch adds a new struct pwrap_slv_type that we use to store the slave
8 specific data. The patch adds 2 new helper functions to access the dew
9 registers. The slave type is looked up via the wrappers child node.
11 Signed-off-by: John Crispin <blogic@openwrt.org>
13 drivers/soc/mediatek/mtk-pmic-wrap.c | 159 ++++++++++++++++++++++++----------
14 1 file changed, 112 insertions(+), 47 deletions(-)
16 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
17 +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
19 PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE | \
20 PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE)
22 -/* macro for slave device wrapper registers */
23 -#define PWRAP_DEW_BASE 0xbc00
24 -#define PWRAP_DEW_EVENT_OUT_EN (PWRAP_DEW_BASE + 0x0)
25 -#define PWRAP_DEW_DIO_EN (PWRAP_DEW_BASE + 0x2)
26 -#define PWRAP_DEW_EVENT_SRC_EN (PWRAP_DEW_BASE + 0x4)
27 -#define PWRAP_DEW_EVENT_SRC (PWRAP_DEW_BASE + 0x6)
28 -#define PWRAP_DEW_EVENT_FLAG (PWRAP_DEW_BASE + 0x8)
29 -#define PWRAP_DEW_READ_TEST (PWRAP_DEW_BASE + 0xa)
30 -#define PWRAP_DEW_WRITE_TEST (PWRAP_DEW_BASE + 0xc)
31 -#define PWRAP_DEW_CRC_EN (PWRAP_DEW_BASE + 0xe)
32 -#define PWRAP_DEW_CRC_VAL (PWRAP_DEW_BASE + 0x10)
33 -#define PWRAP_DEW_MON_GRP_SEL (PWRAP_DEW_BASE + 0x12)
34 -#define PWRAP_DEW_MON_FLAG_SEL (PWRAP_DEW_BASE + 0x14)
35 -#define PWRAP_DEW_EVENT_TEST (PWRAP_DEW_BASE + 0x16)
36 -#define PWRAP_DEW_CIPHER_KEY_SEL (PWRAP_DEW_BASE + 0x18)
37 -#define PWRAP_DEW_CIPHER_IV_SEL (PWRAP_DEW_BASE + 0x1a)
38 -#define PWRAP_DEW_CIPHER_LOAD (PWRAP_DEW_BASE + 0x1c)
39 -#define PWRAP_DEW_CIPHER_START (PWRAP_DEW_BASE + 0x1e)
40 -#define PWRAP_DEW_CIPHER_RDY (PWRAP_DEW_BASE + 0x20)
41 -#define PWRAP_DEW_CIPHER_MODE (PWRAP_DEW_BASE + 0x22)
42 -#define PWRAP_DEW_CIPHER_SWRST (PWRAP_DEW_BASE + 0x24)
43 -#define PWRAP_MT8173_DEW_CIPHER_IV0 (PWRAP_DEW_BASE + 0x26)
44 -#define PWRAP_MT8173_DEW_CIPHER_IV1 (PWRAP_DEW_BASE + 0x28)
45 -#define PWRAP_MT8173_DEW_CIPHER_IV2 (PWRAP_DEW_BASE + 0x2a)
46 -#define PWRAP_MT8173_DEW_CIPHER_IV3 (PWRAP_DEW_BASE + 0x2c)
47 -#define PWRAP_MT8173_DEW_CIPHER_IV4 (PWRAP_DEW_BASE + 0x2e)
48 -#define PWRAP_MT8173_DEW_CIPHER_IV5 (PWRAP_DEW_BASE + 0x30)
49 +/* defines for slave device wrapper registers */
53 + PWRAP_DEW_READ_TEST,
54 + PWRAP_DEW_WRITE_TEST,
57 + PWRAP_DEW_MON_GRP_SEL,
58 + PWRAP_DEW_CIPHER_KEY_SEL,
59 + PWRAP_DEW_CIPHER_IV_SEL,
60 + PWRAP_DEW_CIPHER_RDY,
61 + PWRAP_DEW_CIPHER_MODE,
62 + PWRAP_DEW_CIPHER_SWRST,
64 + /* MT6397 only regs */
65 + PWRAP_DEW_EVENT_OUT_EN,
66 + PWRAP_DEW_EVENT_SRC_EN,
67 + PWRAP_DEW_EVENT_SRC,
68 + PWRAP_DEW_EVENT_FLAG,
69 + PWRAP_DEW_MON_FLAG_SEL,
70 + PWRAP_DEW_EVENT_TEST,
71 + PWRAP_DEW_CIPHER_LOAD,
72 + PWRAP_DEW_CIPHER_START,
75 +static const u32 mt6397_regs[] = {
76 + [PWRAP_DEW_BASE] = 0xbc00,
77 + [PWRAP_DEW_EVENT_OUT_EN] = 0xbc00,
78 + [PWRAP_DEW_DIO_EN] = 0xbc02,
79 + [PWRAP_DEW_EVENT_SRC_EN] = 0xbc04,
80 + [PWRAP_DEW_EVENT_SRC] = 0xbc06,
81 + [PWRAP_DEW_EVENT_FLAG] = 0xbc08,
82 + [PWRAP_DEW_READ_TEST] = 0xbc0a,
83 + [PWRAP_DEW_WRITE_TEST] = 0xbc0c,
84 + [PWRAP_DEW_CRC_EN] = 0xbc0e,
85 + [PWRAP_DEW_CRC_VAL] = 0xbc10,
86 + [PWRAP_DEW_MON_GRP_SEL] = 0xbc12,
87 + [PWRAP_DEW_MON_FLAG_SEL] = 0xbc14,
88 + [PWRAP_DEW_EVENT_TEST] = 0xbc16,
89 + [PWRAP_DEW_CIPHER_KEY_SEL] = 0xbc18,
90 + [PWRAP_DEW_CIPHER_IV_SEL] = 0xbc1a,
91 + [PWRAP_DEW_CIPHER_LOAD] = 0xbc1c,
92 + [PWRAP_DEW_CIPHER_START] = 0xbc1e,
93 + [PWRAP_DEW_CIPHER_RDY] = 0xbc20,
94 + [PWRAP_DEW_CIPHER_MODE] = 0xbc22,
95 + [PWRAP_DEW_CIPHER_SWRST] = 0xbc24,
100 @@ -349,16 +370,26 @@ static int mt8135_regs[] = {
101 [PWRAP_DCM_DBC_PRD] = 0x160,
113 +struct pwrap_slv_type {
114 + const u32 *dew_regs;
115 + enum pmic_type type;
118 struct pmic_wrapper {
121 struct regmap *regmap;
122 const struct pmic_wrapper_type *master;
123 + const struct pwrap_slv_type *slave;
125 struct clk *clk_wrap;
126 struct reset_control *rstc;
127 @@ -544,7 +575,8 @@ static int pwrap_init_sidly(struct pmic_
129 for (i = 0; i < 4; i++) {
130 pwrap_writel(wrp, i, PWRAP_SIDLY);
131 - pwrap_read(wrp, PWRAP_DEW_READ_TEST, &rdata);
132 + pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_READ_TEST],
134 if (rdata == PWRAP_DEW_READ_TEST_VAL) {
135 dev_dbg(wrp->dev, "[Read Test] pass, SIDLY=%x\n", i);
137 @@ -593,7 +625,8 @@ static bool pwrap_is_pmic_cipher_ready(s
141 - ret = pwrap_read(wrp, PWRAP_DEW_CIPHER_RDY, &rdata);
142 + ret = pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_RDY],
147 @@ -621,12 +654,12 @@ static int pwrap_init_cipher(struct pmic
150 /* Config cipher mode @PMIC */
151 - pwrap_write(wrp, PWRAP_DEW_CIPHER_SWRST, 0x1);
152 - pwrap_write(wrp, PWRAP_DEW_CIPHER_SWRST, 0x0);
153 - pwrap_write(wrp, PWRAP_DEW_CIPHER_KEY_SEL, 0x1);
154 - pwrap_write(wrp, PWRAP_DEW_CIPHER_IV_SEL, 0x2);
155 - pwrap_write(wrp, PWRAP_DEW_CIPHER_LOAD, 0x1);
156 - pwrap_write(wrp, PWRAP_DEW_CIPHER_START, 0x1);
157 + pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x1);
158 + pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x0);
159 + pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_KEY_SEL], 0x1);
160 + pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_IV_SEL], 0x2);
161 + pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_LOAD], 0x1);
162 + pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_START], 0x1);
164 /* wait for cipher data ready@AP */
165 ret = pwrap_wait_for_state(wrp, pwrap_is_cipher_ready);
166 @@ -643,7 +676,7 @@ static int pwrap_init_cipher(struct pmic
169 /* wait for cipher mode idle */
170 - pwrap_write(wrp, PWRAP_DEW_CIPHER_MODE, 0x1);
171 + pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_MODE], 0x1);
172 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
174 dev_err(wrp->dev, "cipher mode idle fail, ret=%d\n", ret);
175 @@ -653,9 +686,11 @@ static int pwrap_init_cipher(struct pmic
176 pwrap_writel(wrp, 1, PWRAP_CIPHER_MODE);
179 - if (pwrap_write(wrp, PWRAP_DEW_WRITE_TEST, PWRAP_DEW_WRITE_TEST_VAL) ||
180 - pwrap_read(wrp, PWRAP_DEW_WRITE_TEST, &rdata) ||
181 - (rdata != PWRAP_DEW_WRITE_TEST_VAL)) {
182 + if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
183 + PWRAP_DEW_WRITE_TEST_VAL) ||
184 + pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
186 + (rdata != PWRAP_DEW_WRITE_TEST_VAL)) {
187 dev_err(wrp->dev, "rdata=0x%04X\n", rdata);
190 @@ -677,8 +712,10 @@ static int pwrap_mt8135_init_soc_specifi
191 writel(0x7ff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INT_EN);
193 /* enable PMIC event out and sources */
194 - if (pwrap_write(wrp, PWRAP_DEW_EVENT_OUT_EN, 0x1) ||
195 - pwrap_write(wrp, PWRAP_DEW_EVENT_SRC_EN, 0xffff)) {
196 + if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN],
198 + pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN],
200 dev_err(wrp->dev, "enable dewrap fail\n");
203 @@ -689,8 +726,10 @@ static int pwrap_mt8135_init_soc_specifi
204 static int pwrap_mt8173_init_soc_specific(struct pmic_wrapper *wrp)
206 /* PMIC_DEWRAP enables */
207 - if (pwrap_write(wrp, PWRAP_DEW_EVENT_OUT_EN, 0x1) ||
208 - pwrap_write(wrp, PWRAP_DEW_EVENT_SRC_EN, 0xffff)) {
209 + if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN],
211 + pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN],
213 dev_err(wrp->dev, "enable dewrap fail\n");
216 @@ -734,7 +773,7 @@ static int pwrap_init(struct pmic_wrappe
219 /* Enable dual IO mode */
220 - pwrap_write(wrp, PWRAP_DEW_DIO_EN, 1);
221 + pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_DIO_EN], 1);
223 /* Check IDLE & INIT_DONE in advance */
224 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
225 @@ -746,7 +785,7 @@ static int pwrap_init(struct pmic_wrappe
226 pwrap_writel(wrp, 1, PWRAP_DIO_EN);
229 - pwrap_read(wrp, PWRAP_DEW_READ_TEST, &rdata);
230 + pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_READ_TEST], &rdata);
231 if (rdata != PWRAP_DEW_READ_TEST_VAL) {
232 dev_err(wrp->dev, "Read test failed after switch to DIO mode: 0x%04x != 0x%04x\n",
233 PWRAP_DEW_READ_TEST_VAL, rdata);
234 @@ -759,12 +798,13 @@ static int pwrap_init(struct pmic_wrappe
237 /* Signature checking - using CRC */
238 - if (pwrap_write(wrp, PWRAP_DEW_CRC_EN, 0x1))
239 + if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1))
242 pwrap_writel(wrp, 0x1, PWRAP_CRC_EN);
243 pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE);
244 - pwrap_writel(wrp, PWRAP_DEW_CRC_VAL, PWRAP_SIG_ADR);
245 + pwrap_writel(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_VAL],
247 pwrap_writel(wrp, wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
249 if (wrp->master->type == PWRAP_MT8135)
250 @@ -818,6 +858,21 @@ static const struct regmap_config pwrap_
251 .max_register = 0xffff,
254 +static const struct pwrap_slv_type pmic_mt6397 = {
255 + .dew_regs = mt6397_regs,
256 + .type = PMIC_MT6397,
259 +static const struct of_device_id of_slave_match_tbl[] = {
261 + .compatible = "mediatek,mt6397",
262 + .data = &pmic_mt6397,
267 +MODULE_DEVICE_TABLE(of, of_slave_match_tbl);
269 static struct pmic_wrapper_type pwrap_mt8135 = {
271 .type = PWRAP_MT8135,
272 @@ -862,8 +917,17 @@ static int pwrap_probe(struct platform_d
273 struct device_node *np = pdev->dev.of_node;
274 const struct of_device_id *of_id =
275 of_match_device(of_pwrap_match_tbl, &pdev->dev);
276 + const struct of_device_id *of_slave_id = NULL;
277 struct resource *res;
279 + if (pdev->dev.of_node->child)
280 + of_slave_id = of_match_node(of_slave_match_tbl,
281 + pdev->dev.of_node->child);
282 + if (!of_slave_id) {
283 + dev_dbg(&pdev->dev, "slave pmic should be defined in dts\n");
287 wrp = devm_kzalloc(&pdev->dev, sizeof(*wrp), GFP_KERNEL);
290 @@ -871,6 +935,7 @@ static int pwrap_probe(struct platform_d
291 platform_set_drvdata(pdev, wrp);
293 wrp->master = of_id->data;
294 + wrp->slave = of_slave_id->data;
295 wrp->dev = &pdev->dev;
297 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwrap");