target/linux/layerscape/patches-4.4/8241-irqchip-ls-scfg-msi-add-MSI-affinity-support.patch

   1 From a761ae710d6395af0d8d17a0b4b8f93a816ead46 Mon Sep 17 00:00:00 2001
   2 From: Minghuan Lian <Minghuan.Lian@nxp.com>
   3 Date: Tue, 17 Jan 2017 17:32:43 +0800
   4 Subject: [PATCH 12/13] irqchip/ls-scfg-msi: add MSI affinity support
   5
   6 Cherry-pick patchwork patch.
   7
   8 For LS1046a and LS1043a v1.1, the MSI controller has 4 MSIRs and 4 GIC
   9 SPI interrupts which can be associated with different Core.
  10 So we can support affinity to improve the performance.
  11 The MSI message data is a byte for Layerscape MSI.
  12   7    6   5  4  3  2   1   0
  13 | - |       IBS       |  SRS |
  14 SRS bit0-1 is to select a MSIR which is associated with a CPU.
  15 IBS bit2-6 of ls1046, bit2-4 of ls1043a v1.1 is to select bit of the
  16 MSIR. With affinity, only bits of MSIR0(srs=0 cpu0) are available.
  17 All other bits of the MSIR1-3(cpu1-3) are reserved. The MSI hwirq
  18 always equals bit index of the MSIR0. When changing affinity, MSI
  19 message data will be appended corresponding SRS then MSI will be
  20 moved to the corresponding core.
  21 But in affinity mode, there is only 8 MSI interrupts for a controller
  22 of LS1043a v1.1. It cannot meet the requirement of the some PCIe
  23 devices such as 4 ports Ethernet card. In contrast, without affinity,
  24 all MSIRs can be used for core 0, the MSI interrupts can up to 32.
  25 So the parameter is added to control affinity mode.
  26 "lsmsi=no-affinity" will disable affinity and increase MSI
  27 interrupt number.
  28
  29 Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
  30 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  31 ---
  32  drivers/irqchip/irq-ls-scfg-msi.c | 68 ++++++++++++++++++++++++++++++++++++---
  33  1 file changed, 63 insertions(+), 5 deletions(-)
  34
  35 --- a/drivers/irqchip/irq-ls-scfg-msi.c
  36 +++ b/drivers/irqchip/irq-ls-scfg-msi.c
  37 @@ -40,6 +40,7 @@ struct ls_scfg_msir {
  38         unsigned int gic_irq;
  39         unsigned int bit_start;
  40         unsigned int bit_end;
  41 +       unsigned int srs; /* Shared interrupt register select */
  42         void __iomem *reg;
  43  };
  44
  45 @@ -70,6 +71,19 @@ static struct msi_domain_info ls_scfg_ms
  46         .chip   = &ls_scfg_msi_irq_chip,
  47  };
  48
  49 +static int msi_affinity_flag = 1;
  50 +
  51 +static int __init early_parse_ls_scfg_msi(char *p)
  52 +{
  53 +       if (p && strncmp(p, "no-affinity", 11) == 0)
  54 +               msi_affinity_flag = 0;
  55 +       else
  56 +               msi_affinity_flag = 1;
  57 +
  58 +       return 0;
  59 +}
  60 +early_param("lsmsi", early_parse_ls_scfg_msi);
  61 +
  62  static void ls_scfg_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
  63  {
  64         struct ls_scfg_msi *msi_data = irq_data_get_irq_chip_data(data);
  65 @@ -77,12 +91,36 @@ static void ls_scfg_msi_compose_msg(stru
  66         msg->address_hi = upper_32_bits(msi_data->msiir_addr);
  67         msg->address_lo = lower_32_bits(msi_data->msiir_addr);
  68         msg->data = data->hwirq;
  69 +
  70 +       if (msi_affinity_flag)
  71 +               msg->data |= cpumask_first(data->common->affinity);
  72  }
  73
  74  static int ls_scfg_msi_set_affinity(struct irq_data *irq_data,
  75                                     const struct cpumask *mask, bool force)
  76  {
  77 -       return -EINVAL;
  78 +       struct ls_scfg_msi *msi_data = irq_data_get_irq_chip_data(irq_data);
  79 +       u32 cpu;
  80 +
  81 +       if (!msi_affinity_flag)
  82 +               return -EINVAL;
  83 +
  84 +       if (!force)
  85 +               cpu = cpumask_any_and(mask, cpu_online_mask);
  86 +       else
  87 +               cpu = cpumask_first(mask);
  88 +
  89 +       if (cpu >= msi_data->msir_num)
  90 +               return -EINVAL;
  91 +
  92 +       if (msi_data->msir[cpu].gic_irq <= 0) {
  93 +               pr_warn("cannot bind the irq to cpu%d\n", cpu);
  94 +               return -EINVAL;
  95 +       }
  96 +
  97 +       cpumask_copy(irq_data->common->affinity, mask);
  98 +
  99 +       return IRQ_SET_MASK_OK;
 100  }
 101
 102  static struct irq_chip ls_scfg_msi_parent_chip = {
 103 @@ -158,7 +196,7 @@ static void ls_scfg_msi_irq_handler(stru
 104
 105         for_each_set_bit_from(pos, &val, size) {
 106                 hwirq = ((msir->bit_end - pos) << msi_data->cfg->ibs_shift) |
 107 -                       msir->index;
 108 +                       msir->srs;
 109                 virq = irq_find_mapping(msi_data->parent, hwirq);
 110                 if (virq)
 111                         generic_handle_irq(virq);
 112 @@ -221,10 +259,19 @@ static int ls_scfg_msi_setup_hwirq(struc
 113                                          ls_scfg_msi_irq_handler,
 114                                          msir);
 115
 116 +       if (msi_affinity_flag) {
 117 +               /* Associate MSIR interrupt to the cpu */
 118 +               irq_set_affinity(msir->gic_irq, get_cpu_mask(index));
 119 +               msir->srs = 0; /* This value is determined by the CPU */
 120 +       } else
 121 +               msir->srs = index;
 122 +
 123         /* Release the hwirqs corresponding to this MSIR */
 124 -       for (i = 0; i < msi_data->cfg->msir_irqs; i++) {
 125 -               hwirq = i << msi_data->cfg->ibs_shift | msir->index;
 126 -               bitmap_clear(msi_data->used, hwirq, 1);
 127 +       if (!msi_affinity_flag || msir->index == 0) {
 128 +               for (i = 0; i < msi_data->cfg->msir_irqs; i++) {
 129 +                       hwirq = i << msi_data->cfg->ibs_shift | msir->index;
 130 +                       bitmap_clear(msi_data->used, hwirq, 1);
 131 +               }
 132         }
 133
 134         return 0;
 135 @@ -321,6 +368,17 @@ static int ls_scfg_msi_probe(struct plat
 136         bitmap_set(msi_data->used, 0, msi_data->irqs_num);
 137
 138         msi_data->msir_num = of_irq_count(pdev->dev.of_node);
 139 +
 140 +       if (msi_affinity_flag) {
 141 +               u32 cpu_num;
 142 +
 143 +               cpu_num = num_possible_cpus();
 144 +               if (msi_data->msir_num >= cpu_num)
 145 +                       msi_data->msir_num = cpu_num;
 146 +               else
 147 +                       msi_affinity_flag = 0;
 148 +       }
 149 +
 150         msi_data->msir = devm_kcalloc(&pdev->dev, msi_data->msir_num,
 151                                       sizeof(*msi_data->msir),
 152                                       GFP_KERNEL);