target/linux/layerscape/patches-4.4/8240-irqchip-ls-scfg-msi-add-LS1043a-v1.1-MSI-support.patch

   1 From ab9d5c5c767c17bf9526f84beb5667f2a50e1a4d Mon Sep 17 00:00:00 2001
   2 From: Minghuan Lian <Minghuan.Lian@nxp.com>
   3 Date: Tue, 17 Jan 2017 17:32:42 +0800
   4 Subject: [PATCH] irqchip/ls-scfg-msi: add LS1043a v1.1 MSI support
   5
   6 Cherry-pick patchwork patch with context adjustment.
   7
   8 A MSI controller of LS1043a v1.0 only includes one MSIR and
   9 is assigned one GIC interrupt. In order to support affinity,
  10 LS1043a v1.1 MSI is assigned 4 MSIRs and 4 GIC interrupts.
  11 But the MSIR has the different offset and only supports 8 MSIs.
  12 The bits between variable bit_start and bit_end in structure
  13 ls_scfg_msir are used to show 8 MSI interrupts. msir_irqs and
  14 msir_base are added to describe the difference of MSI between
  15 LS1043a v1.1 and other SoCs.
  16
  17 Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
  18 Acked-by: Rob Herring <robh@kernel.org>
  19 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  20 ---
  21  drivers/irqchip/irq-ls-scfg-msi.c | 45 +++++++++++++++++++++++++++++++++------
  22  1 file changed, 39 insertions(+), 6 deletions(-)
  23
  24 --- a/drivers/irqchip/irq-ls-scfg-msi.c
  25 +++ b/drivers/irqchip/irq-ls-scfg-msi.c
  26 @@ -25,14 +25,21 @@
  27  #define MSI_IRQS_PER_MSIR      32
  28  #define MSI_MSIR_OFFSET                4
  29
  30 +#define MSI_LS1043V1_1_IRQS_PER_MSIR   8
  31 +#define MSI_LS1043V1_1_MSIR_OFFSET     0x10
  32 +
  33  struct ls_scfg_msi_cfg {
  34         u32 ibs_shift; /* Shift of interrupt bit select */
  35 +       u32 msir_irqs; /* The irq number per MSIR */
  36 +       u32 msir_base; /* The base address of MSIR */
  37  };
  38
  39  struct ls_scfg_msir {
  40         struct ls_scfg_msi *msi_data;
  41         unsigned int index;
  42         unsigned int gic_irq;
  43 +       unsigned int bit_start;
  44 +       unsigned int bit_end;
  45         void __iomem *reg;
  46  };
  47
  48 @@ -140,13 +147,18 @@ static void ls_scfg_msi_irq_handler(stru
  49         struct ls_scfg_msir *msir = irq_desc_get_handler_data(desc);
  50         struct ls_scfg_msi *msi_data = msir->msi_data;
  51         unsigned long val;
  52 -       int pos, virq, hwirq;
  53 +       int pos, size, virq, hwirq;
  54
  55         chained_irq_enter(irq_desc_get_chip(desc), desc);
  56
  57         val = ioread32be(msir->reg);
  58 -       for_each_set_bit(pos, &val, MSI_IRQS_PER_MSIR) {
  59 -               hwirq = ((31 - pos) << msi_data->cfg->ibs_shift) | msir->index;
  60 +
  61 +       pos = msir->bit_start;
  62 +       size = msir->bit_end + 1;
  63 +
  64 +       for_each_set_bit_from(pos, &val, size) {
  65 +               hwirq = ((msir->bit_end - pos) << msi_data->cfg->ibs_shift) |
  66 +                       msir->index;
  67                 virq = irq_find_mapping(msi_data->parent, hwirq);
  68                 if (virq)
  69                         generic_handle_irq(virq);
  70 @@ -193,14 +205,24 @@ static int ls_scfg_msi_setup_hwirq(struc
  71         msir->index = index;
  72         msir->msi_data = msi_data;
  73         msir->gic_irq = virq;
  74 -       msir->reg = msi_data->regs + MSI_MSIR_OFFSET + 4 * index;
  75 +       msir->reg = msi_data->regs + msi_data->cfg->msir_base + 4 * index;
  76 +
  77 +       if (msi_data->cfg->msir_irqs == MSI_LS1043V1_1_IRQS_PER_MSIR) {
  78 +               msir->bit_start = 32 - ((msir->index + 1) *
  79 +                                 MSI_LS1043V1_1_IRQS_PER_MSIR);
  80 +               msir->bit_end = msir->bit_start +
  81 +                               MSI_LS1043V1_1_IRQS_PER_MSIR - 1;
  82 +       } else {
  83 +               msir->bit_start = 0;
  84 +               msir->bit_end = msi_data->cfg->msir_irqs - 1;
  85 +       }
  86
  87         irq_set_chained_handler_and_data(msir->gic_irq,
  88                                          ls_scfg_msi_irq_handler,
  89                                          msir);
  90
  91         /* Release the hwirqs corresponding to this MSIR */
  92 -       for (i = 0; i < MSI_IRQS_PER_MSIR; i++) {
  93 +       for (i = 0; i < msi_data->cfg->msir_irqs; i++) {
  94                 hwirq = i << msi_data->cfg->ibs_shift | msir->index;
  95                 bitmap_clear(msi_data->used, hwirq, 1);
  96         }
  97 @@ -216,7 +238,7 @@ static int ls_scfg_msi_teardown_hwirq(st
  98         if (msir->gic_irq > 0)
  99                 irq_set_chained_handler_and_data(msir->gic_irq, NULL, NULL);
 100
 101 -       for (i = 0; i < MSI_IRQS_PER_MSIR; i++) {
 102 +       for (i = 0; i < msi_data->cfg->msir_irqs; i++) {
 103                 hwirq = i << msi_data->cfg->ibs_shift | msir->index;
 104                 bitmap_set(msi_data->used, hwirq, 1);
 105         }
 106 @@ -226,10 +248,20 @@ static int ls_scfg_msi_teardown_hwirq(st
 107
 108  static struct ls_scfg_msi_cfg ls1021_msi_cfg = {
 109         .ibs_shift = 3,
 110 +       .msir_irqs = MSI_IRQS_PER_MSIR,
 111 +       .msir_base = MSI_MSIR_OFFSET,
 112  };
 113
 114  static struct ls_scfg_msi_cfg ls1046_msi_cfg = {
 115         .ibs_shift = 2,
 116 +       .msir_irqs = MSI_IRQS_PER_MSIR,
 117 +       .msir_base = MSI_MSIR_OFFSET,
 118 +};
 119 +
 120 +static struct ls_scfg_msi_cfg ls1043_v1_1_msi_cfg = {
 121 +       .ibs_shift = 2,
 122 +       .msir_irqs = MSI_LS1043V1_1_IRQS_PER_MSIR,
 123 +       .msir_base = MSI_LS1043V1_1_MSIR_OFFSET,
 124  };
 125
 126  static const struct of_device_id ls_scfg_msi_id[] = {
 127 @@ -240,6 +272,7 @@ static const struct of_device_id ls_scfg
 128         { .compatible = "fsl,ls1012a-msi", .data = &ls1021_msi_cfg },
 129         { .compatible = "fsl,ls1021a-msi", .data = &ls1021_msi_cfg },
 130         { .compatible = "fsl,ls1043a-msi", .data = &ls1021_msi_cfg },
 131 +       { .compatible = "fsl,ls1043a-v1.1-msi", .data = &ls1043_v1_1_msi_cfg },
 132         { .compatible = "fsl,ls1046a-msi", .data = &ls1046_msi_cfg },
 133         {},
 134  };