target/linux/layerscape/patches-4.4/0239-ARM-dts-ls1021a-add-PCIe-dts-node.patch

   1 From 1f58043afef0dca3d12dc23ac3a35d7074412939 Mon Sep 17 00:00:00 2001
   2 From: Minghuan Lian <Minghuan.Lian@nxp.com>
   3 Date: Tue, 2 Feb 2016 16:30:07 +0800
   4 Subject: [PATCH 01/13] ARM: dts: ls1021a: add PCIe dts node
   5
   6 Cherry-pick upstream patch.
   7
   8 LS1021a contains two PCIe controllers. The patch adds their node to
   9 dts file.
  10
  11 Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
  12 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  13 ---
  14  arch/arm/boot/dts/ls1021a.dtsi | 44 ++++++++++++++++++++++++++++++++++++++++++
  15  1 file changed, 44 insertions(+)
  16
  17 --- a/arch/arm/boot/dts/ls1021a.dtsi
  18 +++ b/arch/arm/boot/dts/ls1021a.dtsi
  19 @@ -539,5 +539,49 @@
  20                         dr_mode = "host";
  21                         snps,quirk-frame-length-adjustment = <0x20>;
  22                 };
  23 +
  24 +               pcie@3400000 {
  25 +                       compatible = "fsl,ls1021a-pcie", "snps,dw-pcie";
  26 +                       reg = <0x00 0x03400000 0x0 0x00010000   /* controller registers */
  27 +                              0x40 0x00000000 0x0 0x00002000>; /* configuration space */
  28 +                       reg-names = "regs", "config";
  29 +                       interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
  30 +                       fsl,pcie-scfg = <&scfg 0>;
  31 +                       #address-cells = <3>;
  32 +                       #size-cells = <2>;
  33 +                       device_type = "pci";
  34 +                       num-lanes = <4>;
  35 +                       bus-range = <0x0 0xff>;
  36 +                       ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
  37 +                                 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
  38 +                       #interrupt-cells = <1>;
  39 +                       interrupt-map-mask = <0 0 0 7>;
  40 +                       interrupt-map = <0000 0 0 1 &gic GIC_SPI 91  IRQ_TYPE_LEVEL_HIGH>,
  41 +                                       <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
  42 +                                       <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
  43 +                                       <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
  44 +               };
  45 +
  46 +               pcie@3500000 {
  47 +                       compatible = "fsl,ls1021a-pcie", "snps,dw-pcie";
  48 +                       reg = <0x00 0x03500000 0x0 0x00010000   /* controller registers */
  49 +                              0x48 0x00000000 0x0 0x00002000>; /* configuration space */
  50 +                       reg-names = "regs", "config";
  51 +                       interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
  52 +                       fsl,pcie-scfg = <&scfg 1>;
  53 +                       #address-cells = <3>;
  54 +                       #size-cells = <2>;
  55 +                       device_type = "pci";
  56 +                       num-lanes = <4>;
  57 +                       bus-range = <0x0 0xff>;
  58 +                       ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
  59 +                                 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
  60 +                       #interrupt-cells = <1>;
  61 +                       interrupt-map-mask = <0 0 0 7>;
  62 +                       interrupt-map = <0000 0 0 1 &gic GIC_SPI 92  IRQ_TYPE_LEVEL_HIGH>,
  63 +                                       <0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
  64 +                                       <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
  65 +                                       <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
  66 +               };
  67         };
  68  };