target/linux/generic/backport-5.10/797-v5.16-01-dsa-qca8k-add-mac-power-sel-support.patch

   1 From d8b6f5bae6d3b648a67b6958cb98e4e97256d652 Mon Sep 17 00:00:00 2001
   2 From: Ansuel Smith <ansuelsmth@gmail.com>
   3 Date: Thu, 14 Oct 2021 00:39:06 +0200
   4 Subject: dsa: qca8k: add mac_power_sel support
   5
   6 Add missing mac power sel support needed for ipq8064/5 SoC that require
   7 1.8v for the internal regulator port instead of the default 1.5v.
   8 If other device needs this, consider adding a dedicated binding to
   9 support this.
  10
  11 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
  12 Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
  13 Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
  14 Signed-off-by: David S. Miller <davem@davemloft.net>
  15 ---
  16  drivers/net/dsa/qca8k.c | 31 +++++++++++++++++++++++++++++++
  17  drivers/net/dsa/qca8k.h |  5 +++++
  18  2 files changed, 36 insertions(+)
  19
  20 --- a/drivers/net/dsa/qca8k.c
  21 +++ b/drivers/net/dsa/qca8k.c
  22 @@ -951,6 +951,33 @@ qca8k_setup_of_rgmii_delay(struct qca8k_
  23  }
  24
  25  static int
  26 +qca8k_setup_mac_pwr_sel(struct qca8k_priv *priv)
  27 +{
  28 +       u32 mask = 0;
  29 +       int ret = 0;
  30 +
  31 +       /* SoC specific settings for ipq8064.
  32 +        * If more device require this consider adding
  33 +        * a dedicated binding.
  34 +        */
  35 +       if (of_machine_is_compatible("qcom,ipq8064"))
  36 +               mask |= QCA8K_MAC_PWR_RGMII0_1_8V;
  37 +
  38 +       /* SoC specific settings for ipq8065 */
  39 +       if (of_machine_is_compatible("qcom,ipq8065"))
  40 +               mask |= QCA8K_MAC_PWR_RGMII1_1_8V;
  41 +
  42 +       if (mask) {
  43 +               ret = qca8k_rmw(priv, QCA8K_REG_MAC_PWR_SEL,
  44 +                               QCA8K_MAC_PWR_RGMII0_1_8V |
  45 +                               QCA8K_MAC_PWR_RGMII1_1_8V,
  46 +                               mask);
  47 +       }
  48 +
  49 +       return ret;
  50 +}
  51 +
  52 +static int
  53  qca8k_setup(struct dsa_switch *ds)
  54  {
  55         struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
  56 @@ -979,6 +1006,10 @@ qca8k_setup(struct dsa_switch *ds)
  57         if (ret)
  58                 return ret;
  59
  60 +       ret = qca8k_setup_mac_pwr_sel(priv);
  61 +       if (ret)
  62 +               return ret;
  63 +
  64         /* Enable CPU Port */
  65         ret = qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,
  66                             QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
  67 --- a/drivers/net/dsa/qca8k.h
  68 +++ b/drivers/net/dsa/qca8k.h
  69 @@ -100,6 +100,11 @@
  70  #define   QCA8K_SGMII_MODE_CTRL_PHY                    (1 << 22)
  71  #define   QCA8K_SGMII_MODE_CTRL_MAC                    (2 << 22)
  72
  73 +/* MAC_PWR_SEL registers */
  74 +#define QCA8K_REG_MAC_PWR_SEL                          0x0e4
  75 +#define   QCA8K_MAC_PWR_RGMII1_1_8V                    BIT(18)
  76 +#define   QCA8K_MAC_PWR_RGMII0_1_8V                    BIT(19)
  77 +
  78  /* EEE control registers */
  79  #define QCA8K_REG_EEE_CTRL                             0x100
  80  #define  QCA8K_REG_EEE_CTRL_LPI_EN(_i)                 ((_i + 1) * 2)