--- /dev/null
+From a38a6e5d2dc41feeaa839cd61196f86c0ee223b8 Mon Sep 17 00:00:00 2001
+From: Johan Hovold <johan+linaro@kernel.org>
+Date: Fri, 4 Nov 2022 10:39:13 +0100
+Subject: [PATCH 01/13] bus: mhi: host: pci_generic: add support for
+ sc8280xp-crd SDX55 variant
+
+The SC8280XP Compute Reference Design (CRD) has an on-PCB SDX55 modem
+which uses MBIM.
+
+The exact channel configuration is not known but the Foxconn SDX55
+configuration allows the modem to be used so reuse that one for now.
+
+Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
+Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
+Link: https://lore.kernel.org/r/20221104093913.23347-1-johan+linaro@kernel.org
+[mani: modified the subject to format "bus: mhi: host"]
+Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+---
+ drivers/bus/mhi/host/pci_generic.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/bus/mhi/host/pci_generic.c
++++ b/drivers/bus/mhi/host/pci_generic.c
+@@ -542,6 +542,8 @@ static const struct mhi_pci_dev_info mhi
+ static const struct pci_device_id mhi_pci_id_table[] = {
+ { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0304),
+ .driver_data = (kernel_ulong_t) &mhi_qcom_sdx24_info },
++ { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0306, PCI_VENDOR_ID_QCOM, 0x010c),
++ .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
+ /* EM919x (sdx55), use the same vid:pid as qcom-sdx55m */
+ { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0306, 0x18d7, 0x0200),
+ .driver_data = (kernel_ulong_t) &mhi_sierra_em919x_info },
--- /dev/null
+From 6a150325917a6df9467beeaa6518ab91ada81d97 Mon Sep 17 00:00:00 2001
+From: Song Fuchang <song.fc@gmail.com>
+Date: Mon, 7 Nov 2022 19:18:35 +0530
+Subject: [PATCH 02/13] bus: mhi: host: pci_generic: Add HP variant of T99W175
+
+The Foxconn T99W175 modem has an HP variant, which has
+the following output from lspci:
+
+01:00.0 Wireless controller [0d40]: Device 03f0:0a6c
+
+It also has some HP-specific serial numbers on the
+metal case. It works well with this driver, so add
+support for this to the pci_generic driver.
+
+Signed-off-by: Song Fuchang <song.fc@gmail.com>
+Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
+[mani: manually applied the patch]
+Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+---
+ drivers/bus/mhi/host/pci_generic.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/drivers/bus/mhi/host/pci_generic.c
++++ b/drivers/bus/mhi/host/pci_generic.c
+@@ -596,6 +596,9 @@ static const struct pci_device_id mhi_pc
+ /* MV32-WB (Cinterion) */
+ { PCI_DEVICE(0x1269, 0x00bb),
+ .driver_data = (kernel_ulong_t) &mhi_mv32_info },
++ /* T99W175 (sdx55), HP variant */
++ { PCI_DEVICE(0x03f0, 0x0a6c),
++ .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx55_info },
+ { }
+ };
+ MODULE_DEVICE_TABLE(pci, mhi_pci_id_table);
--- /dev/null
+From e8bc362f158f45185778e2bec081146aeeb283b5 Mon Sep 17 00:00:00 2001
+From: Slark Xiao <slark_xiao@163.com>
+Date: Mon, 7 Nov 2022 19:27:00 +0800
+Subject: [PATCH 03/13] bus: mhi: host: pci_generic: Add definition for some
+ VIDs
+
+To make code neat and for convenience purpose, add definition for some
+VIDs. Adding it locally until these VIDs are used in multiple places.
+
+Signed-off-by: Slark Xiao <slark_xiao@163.com>
+Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
+Link: https://lore.kernel.org/r/20221107112700.773-1-slark_xiao@163.com
+Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+---
+ drivers/bus/mhi/host/pci_generic.c | 18 +++++++++++-------
+ 1 file changed, 11 insertions(+), 7 deletions(-)
+
+--- a/drivers/bus/mhi/host/pci_generic.c
++++ b/drivers/bus/mhi/host/pci_generic.c
+@@ -24,6 +24,10 @@
+
+ #define HEALTH_CHECK_PERIOD (HZ * 2)
+
++/* PCI VID definitions */
++#define PCI_VENDOR_ID_THALES 0x1269
++#define PCI_VENDOR_ID_QUECTEL 0x1eac
++
+ /**
+ * struct mhi_pci_dev_info - MHI PCI device specific information
+ * @config: MHI controller configuration
+@@ -557,11 +561,11 @@ static const struct pci_device_id mhi_pc
+ .driver_data = (kernel_ulong_t) &mhi_telit_fn990_info },
+ { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0308),
+ .driver_data = (kernel_ulong_t) &mhi_qcom_sdx65_info },
+- { PCI_DEVICE(0x1eac, 0x1001), /* EM120R-GL (sdx24) */
++ { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1001), /* EM120R-GL (sdx24) */
+ .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
+- { PCI_DEVICE(0x1eac, 0x1002), /* EM160R-GL (sdx24) */
++ { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1002), /* EM160R-GL (sdx24) */
+ .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
+- { PCI_DEVICE(0x1eac, 0x2001), /* EM120R-GL for FCCL (sdx24) */
++ { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x2001), /* EM120R-GL for FCCL (sdx24) */
+ .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
+ /* T99W175 (sdx55), Both for eSIM and Non-eSIM */
+ { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0ab),
+@@ -585,16 +589,16 @@ static const struct pci_device_id mhi_pc
+ { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0d9),
+ .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx65_info },
+ /* MV31-W (Cinterion) */
+- { PCI_DEVICE(0x1269, 0x00b3),
++ { PCI_DEVICE(PCI_VENDOR_ID_THALES, 0x00b3),
+ .driver_data = (kernel_ulong_t) &mhi_mv31_info },
+ /* MV31-W (Cinterion), based on new baseline */
+- { PCI_DEVICE(0x1269, 0x00b4),
++ { PCI_DEVICE(PCI_VENDOR_ID_THALES, 0x00b4),
+ .driver_data = (kernel_ulong_t) &mhi_mv31_info },
+ /* MV32-WA (Cinterion) */
+- { PCI_DEVICE(0x1269, 0x00ba),
++ { PCI_DEVICE(PCI_VENDOR_ID_THALES, 0x00ba),
+ .driver_data = (kernel_ulong_t) &mhi_mv32_info },
+ /* MV32-WB (Cinterion) */
+- { PCI_DEVICE(0x1269, 0x00bb),
++ { PCI_DEVICE(PCI_VENDOR_ID_THALES, 0x00bb),
+ .driver_data = (kernel_ulong_t) &mhi_mv32_info },
+ /* T99W175 (sdx55), HP variant */
+ { PCI_DEVICE(0x03f0, 0x0a6c),
--- /dev/null
+From 6c00e1e4e9817e85b8ba83024cfa88382f898841 Mon Sep 17 00:00:00 2001
+From: Bjorn Helgaas <bhelgaas@google.com>
+Date: Tue, 7 Mar 2023 14:16:25 -0600
+Subject: [PATCH 04/13] bus: mhi: host: pci_generic: Drop redundant
+ pci_enable_pcie_error_reporting()
+
+pci_enable_pcie_error_reporting() enables the device to send ERR_*
+Messages. Since commit <f26e58bf6f54> ("PCI/AER: Enable error reporting
+when AER is native"), the PCI core does this for all devices during
+enumeration, so the driver doesn't need to do it itself.
+
+Remove the redundant pci_enable_pcie_error_reporting() call from the
+driver. Also remove the corresponding pci_disable_pcie_error_reporting()
+from the driver .remove() path.
+
+Note that this only controls ERR_* Messages from the device. An ERR_*
+Message may cause the Root Port to generate an interrupt, depending on the
+AER Root Error Command register managed by the AER service driver.
+
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
+Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
+Link: https://lore.kernel.org/r/20230307201625.879567-1-helgaas@kernel.org
+Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+---
+ drivers/bus/mhi/host/pci_generic.c | 8 +-------
+ 1 file changed, 1 insertion(+), 7 deletions(-)
+
+--- a/drivers/bus/mhi/host/pci_generic.c
++++ b/drivers/bus/mhi/host/pci_generic.c
+@@ -8,7 +8,6 @@
+ * Copyright (C) 2020 Linaro Ltd <loic.poulain@linaro.org>
+ */
+
+-#include <linux/aer.h>
+ #include <linux/delay.h>
+ #include <linux/device.h>
+ #include <linux/mhi.h>
+@@ -901,11 +900,9 @@ static int mhi_pci_probe(struct pci_dev
+ mhi_pdev->pci_state = pci_store_saved_state(pdev);
+ pci_load_saved_state(pdev, NULL);
+
+- pci_enable_pcie_error_reporting(pdev);
+-
+ err = mhi_register_controller(mhi_cntrl, mhi_cntrl_config);
+ if (err)
+- goto err_disable_reporting;
++ return err;
+
+ /* MHI bus does not power up the controller by default */
+ err = mhi_prepare_for_power_up(mhi_cntrl);
+@@ -939,8 +936,6 @@ err_unprepare:
+ mhi_unprepare_after_power_down(mhi_cntrl);
+ err_unregister:
+ mhi_unregister_controller(mhi_cntrl);
+-err_disable_reporting:
+- pci_disable_pcie_error_reporting(pdev);
+
+ return err;
+ }
+@@ -963,7 +958,6 @@ static void mhi_pci_remove(struct pci_de
+ pm_runtime_get_noresume(&pdev->dev);
+
+ mhi_unregister_controller(mhi_cntrl);
+- pci_disable_pcie_error_reporting(pdev);
+ }
+
+ static void mhi_pci_shutdown(struct pci_dev *pdev)
--- /dev/null
+From 537350abfcc6b639884d1ef7bff35d31a624549b Mon Sep 17 00:00:00 2001
+From: Slark Xiao <slark_xiao@163.com>
+Date: Wed, 29 Mar 2023 15:22:39 +0800
+Subject: [PATCH 05/13] bus: mhi: pci_generic: Add Foxconn T99W510
+
+The Foxconn T99W510 device is designed based on Qualcomm
+SDX24. Add 3 variants for different potential customer.
+
+Signed-off-by: Slark Xiao <slark_xiao@163.com>
+Link: https://lore.kernel.org/r/20230329072239.93632-1-slark_xiao@163.com
+Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+---
+ drivers/bus/mhi/host/pci_generic.c | 18 ++++++++++++++++++
+ 1 file changed, 18 insertions(+)
+
+--- a/drivers/bus/mhi/host/pci_generic.c
++++ b/drivers/bus/mhi/host/pci_generic.c
+@@ -363,6 +363,15 @@ static const struct mhi_controller_confi
+ .event_cfg = mhi_foxconn_sdx55_events,
+ };
+
++static const struct mhi_pci_dev_info mhi_foxconn_sdx24_info = {
++ .name = "foxconn-sdx24",
++ .config = &modem_foxconn_sdx55_config,
++ .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
++ .dma_data_width = 32,
++ .mru_default = 32768,
++ .sideband_wake = false,
++};
++
+ static const struct mhi_pci_dev_info mhi_foxconn_sdx55_info = {
+ .name = "foxconn-sdx55",
+ .fw = "qcom/sdx55m/sbl1.mbn",
+@@ -587,6 +596,15 @@ static const struct pci_device_id mhi_pc
+ /* T99W373 (sdx62) */
+ { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0d9),
+ .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx65_info },
++ /* T99W510 (sdx24), variant 1 */
++ { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f0),
++ .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx24_info },
++ /* T99W510 (sdx24), variant 2 */
++ { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f1),
++ .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx24_info },
++ /* T99W510 (sdx24), variant 3 */
++ { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f2),
++ .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx24_info },
+ /* MV31-W (Cinterion) */
+ { PCI_DEVICE(PCI_VENDOR_ID_THALES, 0x00b3),
+ .driver_data = (kernel_ulong_t) &mhi_mv31_info },
--- /dev/null
+From 440b01a2a9a62352cfa355354d3a4de6c5d96adf Mon Sep 17 00:00:00 2001
+From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+Date: Fri, 19 May 2023 19:28:03 +0530
+Subject: [PATCH 06/13] bus: mhi: host: pci_generic: Add support for IP_SW0
+ channels
+
+IP_SW0 channels are used to transfer data over the networking interface
+between MHI endpoint and the host. Define the channels in the MHI v1
+channel config along with dedicated event rings.
+
+Reviewed-by: Loic Poulain <loic.poulain@linaro.org>
+Link: https://lore.kernel.org/r/20230519135803.13850-1-manivannan.sadhasivam@linaro.org
+Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+---
+ drivers/bus/mhi/host/pci_generic.c | 26 ++++++++++++++++++++++----
+ 1 file changed, 22 insertions(+), 4 deletions(-)
+
+--- a/drivers/bus/mhi/host/pci_generic.c
++++ b/drivers/bus/mhi/host/pci_generic.c
+@@ -212,6 +212,19 @@ struct mhi_pci_dev_info {
+ .offload_channel = false, \
+ }
+
++#define MHI_EVENT_CONFIG_SW_DATA(ev_ring, el_count) \
++ { \
++ .num_elements = el_count, \
++ .irq_moderation_ms = 0, \
++ .irq = (ev_ring) + 1, \
++ .priority = 1, \
++ .mode = MHI_DB_BRST_DISABLE, \
++ .data_type = MHI_ER_DATA, \
++ .hardware_event = false, \
++ .client_managed = false, \
++ .offload_channel = false, \
++ }
++
+ #define MHI_EVENT_CONFIG_HW_DATA(ev_ring, el_count, ch_num) \
+ { \
+ .num_elements = el_count, \
+@@ -237,8 +250,10 @@ static const struct mhi_channel_config m
+ MHI_CHANNEL_CONFIG_DL_AUTOQUEUE(21, "IPCR", 8, 0),
+ MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0),
+ MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0),
+- MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 2),
+- MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 3),
++ MHI_CHANNEL_CONFIG_UL(46, "IP_SW0", 64, 2),
++ MHI_CHANNEL_CONFIG_DL(47, "IP_SW0", 64, 3),
++ MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 4),
++ MHI_CHANNEL_CONFIG_HW_DL(101, "IP_HW0", 128, 5),
+ };
+
+ static struct mhi_event_config modem_qcom_v1_mhi_events[] = {
+@@ -246,9 +261,12 @@ static struct mhi_event_config modem_qco
+ MHI_EVENT_CONFIG_CTRL(0, 64),
+ /* DIAG dedicated event ring */
+ MHI_EVENT_CONFIG_DATA(1, 128),
++ /* Software channels dedicated event ring */
++ MHI_EVENT_CONFIG_SW_DATA(2, 64),
++ MHI_EVENT_CONFIG_SW_DATA(3, 64),
+ /* Hardware channels request dedicated hardware event rings */
+- MHI_EVENT_CONFIG_HW_DATA(2, 1024, 100),
+- MHI_EVENT_CONFIG_HW_DATA(3, 2048, 101)
++ MHI_EVENT_CONFIG_HW_DATA(4, 1024, 100),
++ MHI_EVENT_CONFIG_HW_DATA(5, 2048, 101)
+ };
+
+ static const struct mhi_controller_config modem_qcom_v1_mhiv_config = {
--- /dev/null
+From 2dc36ddb6ca4eeda21204dc9e57750494c74c06d Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Duke=20Xin=20=28=E8=BE=9B=E5=AE=89=E6=96=87=29?=
+ <duke_xinanwen@163.com>
+Date: Thu, 8 Jun 2023 02:29:27 -0700
+Subject: [PATCH 07/13] bus: mhi: host: pci_generic: Add support for Quectel
+ EM160R-GL modem
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This modem is identical to the previous EM160R-GL modem with same product
+name. But this one is designed for a specific laptop usecase, hence Quectel
+got a new PID.
+
+Signed-off-by: Duke Xin(辛安文) <duke_xinanwen@163.com>
+Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
+Link: https://lore.kernel.org/r/20230608092927.2893-1-duke_xinanwen@163.com
+[mani: modified the commit message and subject]
+Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+---
+ drivers/bus/mhi/host/pci_generic.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/bus/mhi/host/pci_generic.c
++++ b/drivers/bus/mhi/host/pci_generic.c
+@@ -591,6 +591,8 @@ static const struct pci_device_id mhi_pc
+ .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
+ { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1002), /* EM160R-GL (sdx24) */
+ .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
++ { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x100d), /* EM160R-GL (sdx24) */
++ .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
+ { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x2001), /* EM120R-GL for FCCL (sdx24) */
+ .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
+ /* T99W175 (sdx55), Both for eSIM and Non-eSIM */
--- /dev/null
+From 7e2f6cb11c24799b6851142c4a5ce69bdc630364 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Duke=20Xin=20=28=E8=BE=9B=E5=AE=89=E6=96=87=29?=
+ <duke_xinanwen@163.com>
+Date: Thu, 29 Jun 2023 23:23:18 -0700
+Subject: [PATCH 08/13] bus: mhi: host: pci_generic: Add support for Quectel
+ RM520N-GL modem
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add MHI interface definition for RM520 product based on Qualcomm SDX6X chip
+
+Signed-off-by: Duke Xin(辛安文) <duke_xinanwen@163.com>
+Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
+Link: https://lore.kernel.org/r/20230630062318.12114-1-duke_xinanwen@163.com
+Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+---
+ drivers/bus/mhi/host/pci_generic.c | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+--- a/drivers/bus/mhi/host/pci_generic.c
++++ b/drivers/bus/mhi/host/pci_generic.c
+@@ -352,6 +352,16 @@ static const struct mhi_pci_dev_info mhi
+ .sideband_wake = true,
+ };
+
++static const struct mhi_pci_dev_info mhi_quectel_rm5xx_info = {
++ .name = "quectel-rm5xx",
++ .edl = "qcom/prog_firehose_sdx6x.elf",
++ .config = &modem_quectel_em1xx_config,
++ .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
++ .dma_data_width = 32,
++ .mru_default = 32768,
++ .sideband_wake = true,
++};
++
+ static const struct mhi_channel_config mhi_foxconn_sdx55_channels[] = {
+ MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 0),
+ MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 0),
+@@ -591,6 +601,9 @@ static const struct pci_device_id mhi_pc
+ .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
+ { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1002), /* EM160R-GL (sdx24) */
+ .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
++ /* RM520N-GL (sdx6x), eSIM */
++ { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1004),
++ .driver_data = (kernel_ulong_t) &mhi_quectel_rm5xx_info },
+ { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x100d), /* EM160R-GL (sdx24) */
+ .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
+ { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x2001), /* EM120R-GL for FCCL (sdx24) */
--- /dev/null
+From 5e20ac8e7d3221e079e87066c4e8f4b64bd58ccb Mon Sep 17 00:00:00 2001
+From: Slark Xiao <slark_xiao@163.com>
+Date: Wed, 12 Jul 2023 16:37:41 +0800
+Subject: [PATCH 09/13] bus: mhi: host: pci_generic: Add support for Dell
+ DW5932e
+
+The DW5932e has 2 variants: eSIM(DW5932e-eSIM) and non-eSIM(DW5932e).
+Both of them are designed based on Qualcomm SDX62 and it will
+align with the Foxconn sdx65 settings.
+
+Signed-off-by: Slark Xiao <slark_xiao@163.com>
+Reviewed-by: Loic Poulain <loic.poulain@linaro.org>
+Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
+Link: https://lore.kernel.org/r/20230712083741.7615-1-slark_xiao@163.com
+Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+---
+ drivers/bus/mhi/host/pci_generic.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/drivers/bus/mhi/host/pci_generic.c
++++ b/drivers/bus/mhi/host/pci_generic.c
+@@ -638,6 +638,12 @@ static const struct pci_device_id mhi_pc
+ /* T99W510 (sdx24), variant 3 */
+ { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f2),
+ .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx24_info },
++ /* DW5932e-eSIM (sdx62), With eSIM */
++ { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f5),
++ .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx65_info },
++ /* DW5932e (sdx62), Non-eSIM */
++ { PCI_DEVICE(PCI_VENDOR_ID_FOXCONN, 0xe0f9),
++ .driver_data = (kernel_ulong_t) &mhi_foxconn_sdx65_info },
+ /* MV31-W (Cinterion) */
+ { PCI_DEVICE(PCI_VENDOR_ID_THALES, 0x00b3),
+ .driver_data = (kernel_ulong_t) &mhi_mv31_info },
--- /dev/null
+From 8be9e92a2c8f26fd7482acc2323c6dc2a4ad43aa Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Duke=20Xin=20=28=E8=BE=9B=E5=AE=89=E6=96=87=29?=
+ <duke_xinanwen@163.com>
+Date: Sun, 6 Aug 2023 20:04:54 -0700
+Subject: [PATCH 10/13] bus: mhi: host: pci_generic: Add support for Quectel
+ RM520N-GL Lenovo variant
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Quectel's RM520N-GL Lenovo variant is same as that of the existing
+RM520N-GL modem and uses the same config. But this one is designed for
+Lenovo laptop usecase, hence Quectel got a new PID.
+
+Signed-off-by: Duke Xin(辛安文) <duke_xinanwen@163.com>
+Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
+Reviewed-by: Loic Poulain <loic.poulain@linaro.org>
+Link: https://lore.kernel.org/r/20230807030454.37255-1-duke_xinanwen@163.com
+[mani: tweaked subject and commit message a bit]
+Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+---
+ drivers/bus/mhi/host/pci_generic.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/drivers/bus/mhi/host/pci_generic.c
++++ b/drivers/bus/mhi/host/pci_generic.c
+@@ -604,6 +604,9 @@ static const struct pci_device_id mhi_pc
+ /* RM520N-GL (sdx6x), eSIM */
+ { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1004),
+ .driver_data = (kernel_ulong_t) &mhi_quectel_rm5xx_info },
++ /* RM520N-GL (sdx6x), Lenovo variant */
++ { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1007),
++ .driver_data = (kernel_ulong_t) &mhi_quectel_rm5xx_info },
+ { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x100d), /* EM160R-GL (sdx24) */
+ .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
+ { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x2001), /* EM120R-GL for FCCL (sdx24) */
--- /dev/null
+From 30001cf3a19a2f676a0e23c2c3a511c4a8903284 Mon Sep 17 00:00:00 2001
+From: Daniele Palmas <dnlplm@gmail.com>
+Date: Fri, 4 Aug 2023 11:40:39 +0200
+Subject: [PATCH 11/13] bus: mhi: host: pci_generic: add support for Telit
+ FE990 modem
+
+Add support for Telit FE990 that has the same configuration as FN990:
+
+$ lspci -vv
+04:00.0 Unassigned class [ff00]: Qualcomm Device 0308
+ Subsystem: Device 1c5d:2015
+
+Signed-off-by: Daniele Palmas <dnlplm@gmail.com>
+Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
+Link: https://lore.kernel.org/r/20230804094039.365102-1-dnlplm@gmail.com
+[mani: minor update to commit subject and adjusted comment]
+Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+---
+ drivers/bus/mhi/host/pci_generic.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/drivers/bus/mhi/host/pci_generic.c
++++ b/drivers/bus/mhi/host/pci_generic.c
+@@ -595,6 +595,9 @@ static const struct pci_device_id mhi_pc
+ /* Telit FN990 */
+ { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0308, 0x1c5d, 0x2010),
+ .driver_data = (kernel_ulong_t) &mhi_telit_fn990_info },
++ /* Telit FE990 */
++ { PCI_DEVICE_SUB(PCI_VENDOR_ID_QCOM, 0x0308, 0x1c5d, 0x2015),
++ .driver_data = (kernel_ulong_t) &mhi_telit_fn990_info },
+ { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0308),
+ .driver_data = (kernel_ulong_t) &mhi_qcom_sdx65_info },
+ { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1001), /* EM120R-GL (sdx24) */
--- /dev/null
+From 6ab3d50b106c9aea123a80551a6c9deace83b914 Mon Sep 17 00:00:00 2001
+From: Qiang Yu <quic_qianyu@quicinc.com>
+Date: Tue, 7 Nov 2023 16:14:49 +0800
+Subject: [PATCH] bus: mhi: host: Add a separate timeout parameter for waiting
+ ready
+
+Some devices(eg. SDX75) take longer than expected (default, 8 seconds) to
+set ready after reboot. Hence add optional ready timeout parameter and pass
+the appropriate timeout value to mhi_poll_reg_field() to wait enough for
+device ready as part of power up sequence.
+
+Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
+Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+Link: https://lore.kernel.org/r/1699344890-87076-2-git-send-email-quic_qianyu@quicinc.com
+Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+---
+ drivers/bus/mhi/host/init.c | 1 +
+ drivers/bus/mhi/host/internal.h | 2 +-
+ drivers/bus/mhi/host/main.c | 5 +++--
+ drivers/bus/mhi/host/pm.c | 24 +++++++++++++++++-------
+ include/linux/mhi.h | 4 ++++
+ 5 files changed, 26 insertions(+), 10 deletions(-)
+
+--- a/drivers/bus/mhi/host/init.c
++++ b/drivers/bus/mhi/host/init.c
+@@ -881,6 +881,7 @@ static int parse_config(struct mhi_contr
+ if (!mhi_cntrl->timeout_ms)
+ mhi_cntrl->timeout_ms = MHI_TIMEOUT_MS;
+
++ mhi_cntrl->ready_timeout_ms = config->ready_timeout_ms;
+ mhi_cntrl->bounce_buf = config->use_bounce_buf;
+ mhi_cntrl->buffer_len = config->buf_len;
+ if (!mhi_cntrl->buffer_len)
+--- a/drivers/bus/mhi/host/internal.h
++++ b/drivers/bus/mhi/host/internal.h
+@@ -321,7 +321,7 @@ int __must_check mhi_read_reg_field(stru
+ u32 *out);
+ int __must_check mhi_poll_reg_field(struct mhi_controller *mhi_cntrl,
+ void __iomem *base, u32 offset, u32 mask,
+- u32 val, u32 delayus);
++ u32 val, u32 delayus, u32 timeout_ms);
+ void mhi_write_reg(struct mhi_controller *mhi_cntrl, void __iomem *base,
+ u32 offset, u32 val);
+ int __must_check mhi_write_reg_field(struct mhi_controller *mhi_cntrl,
+--- a/drivers/bus/mhi/host/main.c
++++ b/drivers/bus/mhi/host/main.c
+@@ -40,10 +40,11 @@ int __must_check mhi_read_reg_field(stru
+
+ int __must_check mhi_poll_reg_field(struct mhi_controller *mhi_cntrl,
+ void __iomem *base, u32 offset,
+- u32 mask, u32 val, u32 delayus)
++ u32 mask, u32 val, u32 delayus,
++ u32 timeout_ms)
+ {
+ int ret;
+- u32 out, retry = (mhi_cntrl->timeout_ms * 1000) / delayus;
++ u32 out, retry = (timeout_ms * 1000) / delayus;
+
+ while (retry--) {
+ ret = mhi_read_reg_field(mhi_cntrl, base, offset, mask, &out);
+--- a/drivers/bus/mhi/host/pm.c
++++ b/drivers/bus/mhi/host/pm.c
+@@ -163,6 +163,7 @@ int mhi_ready_state_transition(struct mh
+ enum mhi_pm_state cur_state;
+ struct device *dev = &mhi_cntrl->mhi_dev->dev;
+ u32 interval_us = 25000; /* poll register field every 25 milliseconds */
++ u32 timeout_ms;
+ int ret, i;
+
+ /* Check if device entered error state */
+@@ -173,14 +174,18 @@ int mhi_ready_state_transition(struct mh
+
+ /* Wait for RESET to be cleared and READY bit to be set by the device */
+ ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL,
+- MHICTRL_RESET_MASK, 0, interval_us);
++ MHICTRL_RESET_MASK, 0, interval_us,
++ mhi_cntrl->timeout_ms);
+ if (ret) {
+ dev_err(dev, "Device failed to clear MHI Reset\n");
+ return ret;
+ }
+
++ timeout_ms = mhi_cntrl->ready_timeout_ms ?
++ mhi_cntrl->ready_timeout_ms : mhi_cntrl->timeout_ms;
+ ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs, MHISTATUS,
+- MHISTATUS_READY_MASK, 1, interval_us);
++ MHISTATUS_READY_MASK, 1, interval_us,
++ timeout_ms);
+ if (ret) {
+ dev_err(dev, "Device failed to enter MHI Ready\n");
+ return ret;
+@@ -479,7 +484,7 @@ static void mhi_pm_disable_transition(st
+
+ /* Wait for the reset bit to be cleared by the device */
+ ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL,
+- MHICTRL_RESET_MASK, 0, 25000);
++ MHICTRL_RESET_MASK, 0, 25000, mhi_cntrl->timeout_ms);
+ if (ret)
+ dev_err(dev, "Device failed to clear MHI Reset\n");
+
+@@ -492,8 +497,8 @@ static void mhi_pm_disable_transition(st
+ if (!MHI_IN_PBL(mhi_get_exec_env(mhi_cntrl))) {
+ /* wait for ready to be set */
+ ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs,
+- MHISTATUS,
+- MHISTATUS_READY_MASK, 1, 25000);
++ MHISTATUS, MHISTATUS_READY_MASK,
++ 1, 25000, mhi_cntrl->timeout_ms);
+ if (ret)
+ dev_err(dev, "Device failed to enter READY state\n");
+ }
+@@ -1111,7 +1116,8 @@ int mhi_async_power_up(struct mhi_contro
+ if (state == MHI_STATE_SYS_ERR) {
+ mhi_set_mhi_state(mhi_cntrl, MHI_STATE_RESET);
+ ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL,
+- MHICTRL_RESET_MASK, 0, interval_us);
++ MHICTRL_RESET_MASK, 0, interval_us,
++ mhi_cntrl->timeout_ms);
+ if (ret) {
+ dev_info(dev, "Failed to reset MHI due to syserr state\n");
+ goto error_exit;
+@@ -1202,14 +1208,18 @@ EXPORT_SYMBOL_GPL(mhi_power_down);
+ int mhi_sync_power_up(struct mhi_controller *mhi_cntrl)
+ {
+ int ret = mhi_async_power_up(mhi_cntrl);
++ u32 timeout_ms;
+
+ if (ret)
+ return ret;
+
++ /* Some devices need more time to set ready during power up */
++ timeout_ms = mhi_cntrl->ready_timeout_ms ?
++ mhi_cntrl->ready_timeout_ms : mhi_cntrl->timeout_ms;
+ wait_event_timeout(mhi_cntrl->state_event,
+ MHI_IN_MISSION_MODE(mhi_cntrl->ee) ||
+ MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
+- msecs_to_jiffies(mhi_cntrl->timeout_ms));
++ msecs_to_jiffies(timeout_ms));
+
+ ret = (MHI_IN_MISSION_MODE(mhi_cntrl->ee)) ? 0 : -ETIMEDOUT;
+ if (ret)
+--- a/include/linux/mhi.h
++++ b/include/linux/mhi.h
+@@ -266,6 +266,7 @@ struct mhi_event_config {
+ * struct mhi_controller_config - Root MHI controller configuration
+ * @max_channels: Maximum number of channels supported
+ * @timeout_ms: Timeout value for operations. 0 means use default
++ * @ready_timeout_ms: Timeout value for waiting device to be ready (optional)
+ * @buf_len: Size of automatically allocated buffers. 0 means use default
+ * @num_channels: Number of channels defined in @ch_cfg
+ * @ch_cfg: Array of defined channels
+@@ -277,6 +278,7 @@ struct mhi_event_config {
+ struct mhi_controller_config {
+ u32 max_channels;
+ u32 timeout_ms;
++ u32 ready_timeout_ms;
+ u32 buf_len;
+ u32 num_channels;
+ const struct mhi_channel_config *ch_cfg;
+@@ -326,6 +328,7 @@ struct mhi_controller_config {
+ * @pm_mutex: Mutex for suspend/resume operation
+ * @pm_lock: Lock for protecting MHI power management state
+ * @timeout_ms: Timeout in ms for state transitions
++ * @ready_timeout_ms: Timeout in ms for waiting device to be ready (optional)
+ * @pm_state: MHI power management state
+ * @db_access: DB access states
+ * @ee: MHI device execution environment
+@@ -413,6 +416,7 @@ struct mhi_controller {
+ struct mutex pm_mutex;
+ rwlock_t pm_lock;
+ u32 timeout_ms;
++ u32 ready_timeout_ms;
+ u32 pm_state;
+ u32 db_access;
+ enum mhi_ee_type ee;
--- /dev/null
+From b2f401efbff8878be31b2bce6e8d7bdad23e6f12 Mon Sep 17 00:00:00 2001
+From: Qiang Yu <quic_qianyu@quicinc.com>
+Date: Tue, 7 Nov 2023 16:14:50 +0800
+Subject: [PATCH 12/13] bus: mhi: host: pci_generic: Add SDX75 based modem
+ support
+
+Add generic info for SDX75 based modems. SDX75 takes longer to set ready
+during power up. Hence use separate configuration.
+
+Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
+Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+Link: https://lore.kernel.org/r/1699344890-87076-3-git-send-email-quic_qianyu@quicinc.com
+Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+---
+ drivers/bus/mhi/host/pci_generic.c | 22 ++++++++++++++++++++++
+ 1 file changed, 22 insertions(+)
+
+--- a/drivers/bus/mhi/host/pci_generic.c
++++ b/drivers/bus/mhi/host/pci_generic.c
+@@ -269,6 +269,16 @@ static struct mhi_event_config modem_qco
+ MHI_EVENT_CONFIG_HW_DATA(5, 2048, 101)
+ };
+
++static const struct mhi_controller_config modem_qcom_v2_mhiv_config = {
++ .max_channels = 128,
++ .timeout_ms = 8000,
++ .ready_timeout_ms = 50000,
++ .num_channels = ARRAY_SIZE(modem_qcom_v1_mhi_channels),
++ .ch_cfg = modem_qcom_v1_mhi_channels,
++ .num_events = ARRAY_SIZE(modem_qcom_v1_mhi_events),
++ .event_cfg = modem_qcom_v1_mhi_events,
++};
++
+ static const struct mhi_controller_config modem_qcom_v1_mhiv_config = {
+ .max_channels = 128,
+ .timeout_ms = 8000,
+@@ -278,6 +288,16 @@ static const struct mhi_controller_confi
+ .event_cfg = modem_qcom_v1_mhi_events,
+ };
+
++static const struct mhi_pci_dev_info mhi_qcom_sdx75_info = {
++ .name = "qcom-sdx75m",
++ .fw = "qcom/sdx75m/xbl.elf",
++ .edl = "qcom/sdx75m/edl.mbn",
++ .config = &modem_qcom_v2_mhiv_config,
++ .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
++ .dma_data_width = 32,
++ .sideband_wake = false,
++};
++
+ static const struct mhi_pci_dev_info mhi_qcom_sdx65_info = {
+ .name = "qcom-sdx65m",
+ .fw = "qcom/sdx65m/xbl.elf",
+@@ -600,6 +620,8 @@ static const struct pci_device_id mhi_pc
+ .driver_data = (kernel_ulong_t) &mhi_telit_fn990_info },
+ { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0308),
+ .driver_data = (kernel_ulong_t) &mhi_qcom_sdx65_info },
++ { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0309),
++ .driver_data = (kernel_ulong_t) &mhi_qcom_sdx75_info },
+ { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1001), /* EM120R-GL (sdx24) */
+ .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
+ { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1002), /* EM160R-GL (sdx24) */
--- /dev/null
+From 5f157aa89b876e82d6aafb2d009979118d0bdd2b Mon Sep 17 00:00:00 2001
+From: Jeff Johnson <quic_jjohnson@quicinc.com>
+Date: Thu, 22 Feb 2024 18:00:23 -0800
+Subject: [PATCH 13/13] bus: mhi: host: pci_generic: constify
+ modem_telit_fn980_hw_v1_config
+
+MHI expects the controller configs to be const, and all of the other ones
+in this file already are, so constify modem_telit_fn980_hw_v1_config.
+
+Signed-off-by: Jeff Johnson <quic_jjohnson@quicinc.com>
+Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+Link: https://lore.kernel.org/r/20240222-mhi-const-bus-mhi-host-pci_generic-v1-1-d4c9b0b0a7a5@quicinc.com
+Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+---
+ drivers/bus/mhi/host/pci_generic.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/bus/mhi/host/pci_generic.c
++++ b/drivers/bus/mhi/host/pci_generic.c
+@@ -538,7 +538,7 @@ static struct mhi_event_config mhi_telit
+ MHI_EVENT_CONFIG_HW_DATA(2, 2048, 101)
+ };
+
+-static struct mhi_controller_config modem_telit_fn980_hw_v1_config = {
++static const struct mhi_controller_config modem_telit_fn980_hw_v1_config = {
+ .max_channels = 128,
+ .timeout_ms = 20000,
+ .num_channels = ARRAY_SIZE(mhi_telit_fn980_hw_v1_channels),
--- a/drivers/bus/mhi/host/main.c
+++ b/drivers/bus/mhi/host/main.c
-@@ -905,6 +905,7 @@ int mhi_process_ctrl_ev_ring(struct mhi_
+@@ -906,6 +906,7 @@ int mhi_process_ctrl_ev_ring(struct mhi_
switch (event) {
case MHI_EE_SBL:
st = DEV_ST_TRANSITION_SBL;
projects / openwrt / staging / stintel.git / commitdiff