compatible = "ti,tmp421";
reg = <0x4c>;
};
- sfp0: eeprom@50 {
+ sfp0_eeprom: eeprom@50 {
compatible = "atmel,24c01";
reg = <0x50>;
};
*/
clock-frequency = <30000>;
- sfp1: eeprom@50 {
+ sfp1_eeprom: eeprom@50 {
compatible = "atmel,24c01";
reg = <0x50>;
};
};
+
+
smi0: mdio@1180000001800 {
compatible = "cavium,octeon-3860-mdio";
#address-cells = <1>;
* passive copper.
*/
vitesse,copper_agc_config4 = <0x0496>;
-
- /* The Vitesse 10G PHY does not
- * automatically read the SFP EEPROM
- * so the host needs to do it to put
- * the PHY in the proper mode for
- * copper or optical.
- */
- nvmem = <&sfp0>;
};
phy1: ethernet-phy@1 {
* passive copper.
*/
vitesse,copper_agc_config4 = <0x0496>;
-
- /* The Vitesse 10G PHY does not
- * automatically read the SFP EEPROM
- * so the host needs to do it to put
- * the PHY in the proper mode for
- * copper or optical.
- */
- nvmem = <&sfp0>;
- };
- };
- mphyB: ethernet-phy-nexus@B {
- reg = <0>;
- /* The TI TLK10232 is a dual-PHY where
- * some of the configuration is common across
- * both of the phy devices such as the reset
- * line and the base MDIO address.
- */
- compatible = "ti,tlk10232-nexus", "ethernet-phy-nexus";
- #address-cells = <1>;
- #size-cells = <0>;
- ranges;
-
- /* Hardware reset signal open-drain active low on GPIO 17, must not be driven high. */
- reset = <&gpio 17 GPIO_LINE_OPEN_DRAIN>;
-
- phy11: ethernet-phy@0 {
- /* Absolute address */
- reg = <0>;
- compatible = "ti,tlk10232", "ethernet-phy-ieee802.3-c45";
-
- /* The TI 10G PHY does not
- * automatically read the SFP EEPROM
- * so the host needs to do it to put
- * the PHY in the proper mode for
- * copper or optical.
- */
- sfp-eeprom = <&sfp0>;
-
- /* TX fault input signal for PHY from SFP+ */
- tx-fault = <&gpio1 4 GPIO_ACTIVE_HIGH>;
- /* TX disable for PHY to SFP+ */
- tx-disable = <&gpio1 5 GPIO_ACTIVE_HIGH>;
- /* MOD ABS signal for PHY from SFP+ */
- mod-abs = <&gpio1 6 GPIO_ACTIVE_HIGH>;
- /* RX los of singal for PHY from SFP+ */
- rx-los = <&gpio1 7 GPIO_ACTIVE_HIGH>;
- };
-
- phy10: ethernet-phy@1 {
- /* Absolute address */
- reg = <0x1>;
- compatible = "ti,tlk10232", "ethernet-phy-ieee802.3-c45";
-
- /* The TI 10G PHY does not
- * automatically read the SFP EEPROM
- * so the host needs to do it to put
- * the PHY in the proper mode for
- * copper or optical.
- */
- sfp-eeprom = <&sfp1>;
- /* TX fault input signal for PHY */
- tx-fault = <&gpio1 0 GPIO_ACTIVE_HIGH>;
- /* TX disable for PHY */
- tx-disable = <&gpio1 1 GPIO_ACTIVE_HIGH>;
- /* MOD ABS signal for PHY */
- mod-abs = <&gpio1 2 GPIO_ACTIVE_HIGH>;
- /* RX los of singal for PHY */
- rx-los = <&gpio1 3 GPIO_ACTIVE_HIGH>;
};
};
};
#size-cells = <0>;
reg = <0x11800 0xa0000000 0x0 0x2000>;
- interface@A {
+ interface@0 {
compatible = "cavium,octeon-3860-pip-interface";
#address-cells = <1>;
#size-cells = <0>;
ethernet@0 {
compatible = "cavium,octeon-3860-pip-port";
reg = <0x0>; /* Port */
- local-mac-address = [ 00 00 00 00 00 00 ];
nvmem-cells = <&macaddr_tlv>;
nvmem-cell-names = "mac-address";
phy-handle = <&phy0>;
};
};
- interface@B {
+ interface@1 {
compatible = "cavium,octeon-3860-pip-interface";
#address-cells = <1>;
#size-cells = <0>;
reg = <1>; /* interface */
- ethernet@0 {
+
+ //status = "disabled";
+
+ ethernet@1 {
compatible = "cavium,octeon-3860-pip-port";
reg = <0x0>; /* Port */
- local-mac-address = [ 00 00 00 00 00 00 ];
mac-address-increment = <(1)>;
nvmem-cells = <&macaddr_tlv>;
nvmem-cell-names = "mac-address";
phy-handle = <&phy1>;
};
};
- interface@C {
- compatible = "cavium,octeon-3860-pip-interface";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>; /* interface */
-
- ethernet@0 {
- compatible = "cavium,octeon-3860-pip-port";
- reg = <0x0>; /* Port */
- local-mac-address = [ 00 00 00 00 00 00 ];
- phy-handle = <&phy10>;
- };
- };
- interface@D {
- compatible = "cavium,octeon-3860-pip-interface";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>; /* interface */
-
- ethernet@0 {
- compatible = "cavium,octeon-3860-pip-port";
- reg = <0x0>; /* Port */
- local-mac-address = [ 00 00 00 00 00 00 ];
- phy-handle = <&phy11>;
- };
- };
};
uart0: serial@1180000000800 {
};
};
};
+
+ sfp0: sfp-slot@0 {
+ compatible = "sff,sfp";
+ i2c-bus = <&twsi0>;
+ //mod-def0-gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
+ //tx-disable-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;
+ //tx-fault-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ sfp1: sfp-slot@1 {
+ compatible = "sff,sfp";
+ i2c-bus = <&twsi1>;
+ //mod-def0-gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
+ //tx-disable-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
+ //tx-fault-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
+ };
+
gpio-leds {
compatible = "gpio-leds";
+++ /dev/null
---- a/drivers/staging/octeon/ethernet.c
-+++ b/drivers/staging/octeon/ethernet.c
-@@ -676,6 +676,7 @@ static int cvm_oct_probe(struct platform
- int interface;
- int fau = FAU_NUM_PACKET_BUFFERS_TO_FREE;
- int qos;
-+ int i;
- struct device_node *pip;
- int mtu_overhead = ETH_HLEN + ETH_FCS_LEN;
-
-@@ -797,13 +798,19 @@ static int cvm_oct_probe(struct platform
- }
-
- num_interfaces = cvmx_helper_get_number_of_interfaces();
-- for (interface = 0; interface < num_interfaces; interface++) {
-- cvmx_helper_interface_mode_t imode =
-- cvmx_helper_interface_get_mode(interface);
-- int num_ports = cvmx_helper_ports_on_interface(interface);
-+ for (i = 0; i < num_interfaces; i++) {
-+ cvmx_helper_interface_mode_t imode;
-+ int interface;
-+ int num_ports;
- int port;
- int port_index;
-
-+ interface = i;
-+ if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_UBNT_E200)
-+ interface = num_interfaces - (i + 1);
-+
-+ num_ports = cvmx_helper_ports_on_interface(interface);
-+ imode = cvmx_helper_interface_get_mode(interface);
- for (port_index = 0,
- port = cvmx_helper_get_ipd_port(interface, 0);
- port < cvmx_helper_get_ipd_port(interface, num_ports);
projects / openwrt / staging / stintel.git / commitdiff