Add support for the Xunlong Orange Pi R1 Plus.
Manually generated of-platdata files to avoid swig dependency.
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
friendlyarm_nanopi-r2s
endef
+define U-Boot/orangepi-r1-plus-rk3328
+ $(U-Boot/rk3328/Default)
+ NAME:=Orange Pi R1 Plus
+ BUILD_DEVICES:= \
+ xunlong_orangepi-r1-plus
+endef
+
define U-Boot/roc-cc-rk3328
$(U-Boot/rk3328/Default)
NAME:=ROC-RK3328-CC
rockpro64-rk3399 \
nanopi-r2c-rk3328 \
nanopi-r2s-rk3328 \
+ orangepi-r1-plus-rk3328 \
roc-cc-rk3328
UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes
--- /dev/null
+From ff312af37d5f263f181468639aab83f645d331f1 Mon Sep 17 00:00:00 2001
+From: Tianling Shen <cnsztl@gmail.com>
+Date: Sat, 20 May 2023 18:50:38 +0800
+Subject: [PATCH] rockchip: rk3328: Add support for Orange Pi R1 Plus
+
+Orange Pi R1 Plus is a Rockchip RK3328 based SBC by Xunlong.
+
+This device is similar to the NanoPi R2S, and has a 16MB
+SPI NOR (mx25l12805d). The reset button is changed to
+directly reset the power supply, another detail is that
+both network ports have independent MAC addresses.
+
+The device tree and description are taken from kernel v6.3-rc1.
+
+Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
+Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+---
+ arch/arm/dts/Makefile | 1 +
+ .../dts/rk3328-orangepi-r1-plus-u-boot.dtsi | 46 +++
+ arch/arm/dts/rk3328-orangepi-r1-plus.dts | 373 ++++++++++++++++++
+ board/rockchip/evb_rk3328/MAINTAINERS | 6 +
+ configs/orangepi-r1-plus-rk3328_defconfig | 114 ++++++
+ 5 files changed, 540 insertions(+)
+ create mode 100644 arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
+ create mode 100644 arch/arm/dts/rk3328-orangepi-r1-plus.dts
+ create mode 100644 configs/orangepi-r1-plus-rk3328_defconfig
+
+--- a/arch/arm/dts/Makefile
++++ b/arch/arm/dts/Makefile
+@@ -110,6 +110,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3328) += \
+ rk3328-evb.dtb \
+ rk3328-nanopi-r2c.dtb \
+ rk3328-nanopi-r2s.dtb \
++ rk3328-orangepi-r1-plus.dtb \
+ rk3328-roc-cc.dtb \
+ rk3328-rock64.dtb \
+ rk3328-rock-pi-e.dtb
+--- /dev/null
++++ b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
+@@ -0,0 +1,46 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++/*
++ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
++ * (C) Copyright 2020 David Bauer
++ */
++
++#include "rk3328-u-boot.dtsi"
++#include "rk3328-sdram-ddr4-666.dtsi"
++/ {
++ chosen {
++ u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
++ };
++};
++
++&gpio0 {
++ u-boot,dm-spl;
++};
++
++&pinctrl {
++ u-boot,dm-spl;
++};
++
++&sdmmc0m1_gpio {
++ u-boot,dm-spl;
++};
++
++&pcfg_pull_up_4ma {
++ u-boot,dm-spl;
++};
++
++/* Need this and all the pinctrl/gpio stuff above to set pinmux */
++&vcc_sd {
++ u-boot,dm-spl;
++};
++
++&gmac2io {
++ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
++ snps,reset-active-low;
++ snps,reset-delays-us = <0 10000 50000>;
++};
++
++&spi0 {
++ spi_flash: spiflash@0 {
++ u-boot,dm-pre-reloc;
++ };
++};
+--- /dev/null
++++ b/arch/arm/dts/rk3328-orangepi-r1-plus.dts
+@@ -0,0 +1,359 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Based on rk3328-nanopi-r2s.dts, which is:
++ * Copyright (c) 2020 David Bauer <mail@david-bauer.net>
++ */
++
++/dts-v1/;
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/leds/common.h>
++#include "rk3328.dtsi"
++
++/ {
++ model = "Xunlong Orange Pi R1 Plus";
++ compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328";
++
++ aliases {
++ mmc0 = &sdmmc;
++ };
++
++ chosen {
++ stdout-path = "serial2:1500000n8";
++ };
++
++ gmac_clk: gmac-clock {
++ compatible = "fixed-clock";
++ clock-frequency = <125000000>;
++ clock-output-names = "gmac_clkin";
++ #clock-cells = <0>;
++ };
++
++ leds {
++ compatible = "gpio-leds";
++ pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
++ pinctrl-names = "default";
++
++ led-0 {
++ function = LED_FUNCTION_LAN;
++ color = <LED_COLOR_ID_GREEN>;
++ gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
++ };
++
++ led-1 {
++ function = LED_FUNCTION_STATUS;
++ color = <LED_COLOR_ID_RED>;
++ gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
++ linux,default-trigger = "heartbeat";
++ };
++
++ led-2 {
++ function = LED_FUNCTION_WAN;
++ color = <LED_COLOR_ID_GREEN>;
++ gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
++ };
++ };
++
++ vcc_sd: sdmmc-regulator {
++ compatible = "regulator-fixed";
++ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
++ pinctrl-0 = <&sdmmc0m1_gpio>;
++ pinctrl-names = "default";
++ regulator-name = "vcc_sd";
++ regulator-boot-on;
++ vin-supply = <&vcc_io>;
++ };
++
++ vcc_sys: vcc-sys-regulator {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc_sys";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ };
++
++ vdd_5v_lan: vdd-5v-lan-regulator {
++ compatible = "regulator-fixed";
++ enable-active-high;
++ gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
++ pinctrl-0 = <&lan_vdd_pin>;
++ pinctrl-names = "default";
++ regulator-name = "vdd_5v_lan";
++ regulator-always-on;
++ regulator-boot-on;
++ vin-supply = <&vcc_sys>;
++ };
++};
++
++&cpu0 {
++ cpu-supply = <&vdd_arm>;
++};
++
++&cpu1 {
++ cpu-supply = <&vdd_arm>;
++};
++
++&cpu2 {
++ cpu-supply = <&vdd_arm>;
++};
++
++&cpu3 {
++ cpu-supply = <&vdd_arm>;
++};
++
++&display_subsystem {
++ status = "disabled";
++};
++
++&gmac2io {
++ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
++ assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
++ clock_in_out = "input";
++ phy-handle = <&rtl8211e>;
++ phy-mode = "rgmii";
++ phy-supply = <&vcc_io>;
++ pinctrl-0 = <&rgmiim1_pins>;
++ pinctrl-names = "default";
++ snps,aal;
++ rx_delay = <0x18>;
++ tx_delay = <0x24>;
++ status = "okay";
++
++ mdio {
++ compatible = "snps,dwmac-mdio";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ rtl8211e: ethernet-phy@1 {
++ reg = <1>;
++ pinctrl-0 = <ð_phy_reset_pin>;
++ pinctrl-names = "default";
++ reset-assert-us = <10000>;
++ reset-deassert-us = <50000>;
++ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
++ };
++ };
++};
++
++&i2c1 {
++ status = "okay";
++
++ rk805: pmic@18 {
++ compatible = "rockchip,rk805";
++ reg = <0x18>;
++ interrupt-parent = <&gpio1>;
++ interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
++ #clock-cells = <1>;
++ clock-output-names = "xin32k", "rk805-clkout2";
++ gpio-controller;
++ #gpio-cells = <2>;
++ pinctrl-0 = <&pmic_int_l>;
++ pinctrl-names = "default";
++ rockchip,system-power-controller;
++ wakeup-source;
++
++ vcc1-supply = <&vcc_sys>;
++ vcc2-supply = <&vcc_sys>;
++ vcc3-supply = <&vcc_sys>;
++ vcc4-supply = <&vcc_sys>;
++ vcc5-supply = <&vcc_io>;
++ vcc6-supply = <&vcc_sys>;
++
++ regulators {
++ vdd_log: DCDC_REG1 {
++ regulator-name = "vdd_log";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <712500>;
++ regulator-max-microvolt = <1450000>;
++ regulator-ramp-delay = <12500>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1000000>;
++ };
++ };
++
++ vdd_arm: DCDC_REG2 {
++ regulator-name = "vdd_arm";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <712500>;
++ regulator-max-microvolt = <1450000>;
++ regulator-ramp-delay = <12500>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <950000>;
++ };
++ };
++
++ vcc_ddr: DCDC_REG3 {
++ regulator-name = "vcc_ddr";
++ regulator-always-on;
++ regulator-boot-on;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ };
++ };
++
++ vcc_io: DCDC_REG4 {
++ regulator-name = "vcc_io";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <3300000>;
++ };
++ };
++
++ vcc_18: LDO_REG1 {
++ regulator-name = "vcc_18";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1800000>;
++ };
++ };
++
++ vcc18_emmc: LDO_REG2 {
++ regulator-name = "vcc18_emmc";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1800000>;
++ };
++ };
++
++ vdd_10: LDO_REG3 {
++ regulator-name = "vdd_10";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <1000000>;
++ regulator-max-microvolt = <1000000>;
++
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1000000>;
++ };
++ };
++ };
++ };
++};
++
++&io_domains {
++ pmuio-supply = <&vcc_io>;
++ vccio1-supply = <&vcc_io>;
++ vccio2-supply = <&vcc18_emmc>;
++ vccio3-supply = <&vcc_io>;
++ vccio4-supply = <&vcc_io>;
++ vccio5-supply = <&vcc_io>;
++ vccio6-supply = <&vcc_io>;
++ status = "okay";
++};
++
++&pinctrl {
++ gmac2io {
++ eth_phy_reset_pin: eth-phy-reset-pin {
++ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
++ };
++ };
++
++ leds {
++ lan_led_pin: lan-led-pin {
++ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
++ sys_led_pin: sys-led-pin {
++ rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++
++ wan_led_pin: wan-led-pin {
++ rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ lan {
++ lan_vdd_pin: lan-vdd-pin {
++ rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ pmic {
++ pmic_int_l: pmic-int-l {
++ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++ };
++};
++
++&pwm2 {
++ status = "okay";
++};
++
++&sdmmc {
++ bus-width = <4>;
++ cap-sd-highspeed;
++ disable-wp;
++ pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
++ pinctrl-names = "default";
++ vmmc-supply = <&vcc_sd>;
++ status = "okay";
++};
++
++&spi0 {
++ status = "okay";
++
++ flash@0 {
++ compatible = "jedec,spi-nor";
++ reg = <0>;
++ spi-max-frequency = <50000000>;
++ };
++};
++
++&tsadc {
++ rockchip,hw-tshut-mode = <0>;
++ rockchip,hw-tshut-polarity = <0>;
++ status = "okay";
++};
++
++&u2phy {
++ status = "okay";
++};
++
++&u2phy_host {
++ status = "okay";
++};
++
++&u2phy_otg {
++ status = "okay";
++};
++
++&uart2 {
++ status = "okay";
++};
++
++&usb20_otg {
++ dr_mode = "host";
++ status = "okay";
++};
++
++&usb_host0_ehci {
++ status = "okay";
++};
++
++&usb_host0_ohci {
++ status = "okay";
++};
+--- a/board/rockchip/evb_rk3328/MAINTAINERS
++++ b/board/rockchip/evb_rk3328/MAINTAINERS
+@@ -18,6 +18,12 @@ F: configs/nanopi-r2s-rk3328_defcon
+ F: arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
+ F: arch/arm/dts/rk3328-nanopi-r2s.dts
+
++ORANGEPI-R1-PLUS-RK3328
++M: Tianling Shen <cnsztl@gmail.com>
++S: Maintained
++F: configs/orangepi-r1-plus-rk3328_defconfig
++F: arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
++
+ ROC-RK3328-CC
+ M: Loic Devulder <ldevulder@suse.com>
+ M: Chen-Yu Tsai <wens@csie.org>
+--- /dev/null
++++ b/configs/orangepi-r1-plus-rk3328_defconfig
+@@ -0,0 +1,98 @@
++CONFIG_ARM=y
++CONFIG_ARCH_ROCKCHIP=y
++CONFIG_SYS_TEXT_BASE=0x00200000
++CONFIG_SPL_GPIO_SUPPORT=y
++CONFIG_ENV_OFFSET=0x3F8000
++CONFIG_ROCKCHIP_RK3328=y
++CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
++CONFIG_TPL_LIBCOMMON_SUPPORT=y
++CONFIG_TPL_LIBGENERIC_SUPPORT=y
++CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
++CONFIG_SPL_STACK_R_ADDR=0x600000
++CONFIG_NR_DRAM_BANKS=1
++CONFIG_DEBUG_UART_BASE=0xFF130000
++CONFIG_DEBUG_UART_CLOCK=24000000
++CONFIG_SYSINFO=y
++CONFIG_DEBUG_UART=y
++CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
++# CONFIG_ANDROID_BOOT_IMAGE is not set
++CONFIG_FIT=y
++CONFIG_FIT_VERBOSE=y
++CONFIG_SPL_LOAD_FIT=y
++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-orangepi-r1-plus.dtb"
++CONFIG_MISC_INIT_R=y
++# CONFIG_DISPLAY_CPUINFO is not set
++CONFIG_DISPLAY_BOARDINFO_LATE=y
++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
++CONFIG_TPL_SYS_MALLOC_SIMPLE=y
++CONFIG_SPL_STACK_R=y
++CONFIG_SPL_I2C_SUPPORT=y
++CONFIG_SPL_POWER_SUPPORT=y
++CONFIG_SPL_ATF=y
++CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
++CONFIG_CMD_BOOTZ=y
++CONFIG_CMD_GPT=y
++CONFIG_CMD_MMC=y
++CONFIG_CMD_USB=y
++# CONFIG_CMD_SETEXPR is not set
++CONFIG_CMD_TIME=y
++CONFIG_SPL_OF_CONTROL=y
++CONFIG_TPL_OF_CONTROL=y
++CONFIG_DEFAULT_DEVICE_TREE="rk3328-orangepi-r1-plus"
++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
++CONFIG_TPL_OF_PLATDATA=y
++CONFIG_ENV_IS_IN_MMC=y
++CONFIG_SYS_RELOC_GD_ENV_ADDR=y
++CONFIG_NET_RANDOM_ETHADDR=y
++CONFIG_TPL_DM=y
++CONFIG_REGMAP=y
++CONFIG_SPL_REGMAP=y
++CONFIG_TPL_REGMAP=y
++CONFIG_SYSCON=y
++CONFIG_SPL_SYSCON=y
++CONFIG_TPL_SYSCON=y
++CONFIG_CLK=y
++CONFIG_SPL_CLK=y
++CONFIG_FASTBOOT_BUF_ADDR=0x800800
++CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
++CONFIG_ROCKCHIP_GPIO=y
++CONFIG_SYS_I2C_ROCKCHIP=y
++CONFIG_MMC_DW=y
++CONFIG_MMC_DW_ROCKCHIP=y
++CONFIG_SF_DEFAULT_SPEED=20000000
++CONFIG_DM_ETH=y
++CONFIG_ETH_DESIGNWARE=y
++CONFIG_GMAC_ROCKCHIP=y
++CONFIG_PINCTRL=y
++CONFIG_SPL_PINCTRL=y
++CONFIG_DM_PMIC=y
++CONFIG_PMIC_RK8XX=y
++CONFIG_SPL_DM_REGULATOR=y
++CONFIG_REGULATOR_PWM=y
++CONFIG_DM_REGULATOR_FIXED=y
++CONFIG_SPL_DM_REGULATOR_FIXED=y
++CONFIG_REGULATOR_RK8XX=y
++CONFIG_PWM_ROCKCHIP=y
++CONFIG_RAM=y
++CONFIG_SPL_RAM=y
++CONFIG_TPL_RAM=y
++CONFIG_DM_RESET=y
++CONFIG_BAUDRATE=1500000
++CONFIG_DEBUG_UART_SHIFT=2
++CONFIG_SYSRESET=y
++# CONFIG_TPL_SYSRESET is not set
++CONFIG_USB=y
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_XHCI_DWC3=y
++CONFIG_USB_EHCI_HCD=y
++CONFIG_USB_EHCI_GENERIC=y
++CONFIG_USB_OHCI_HCD=y
++CONFIG_USB_OHCI_GENERIC=y
++CONFIG_USB_DWC2=y
++CONFIG_USB_DWC3=y
++# CONFIG_USB_DWC3_GADGET is not set
++CONFIG_USB_GADGET=y
++CONFIG_USB_GADGET_DWC2_OTG=y
++CONFIG_SPL_TINY_MEMSET=y
++CONFIG_TPL_TINY_MEMSET=y
++CONFIG_ERRNO_STR=y
--- /dev/null
+/*
+ * DO NOT MODIFY
+ *
+ * Declares externs for all device/uclass instances.
+ * This was generated by dtoc from a .dtb (device tree binary) file.
+ */
+
+#include <dm/device-internal.h>
+#include <dm/uclass-internal.h>
+
+/* driver declarations - these allow DM_DRIVER_GET() to be used */
+extern U_BOOT_DRIVER(rockchip_rk3328_cru);
+extern U_BOOT_DRIVER(rockchip_rk3328_dmc);
+extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc);
+extern U_BOOT_DRIVER(ns16550_serial);
+extern U_BOOT_DRIVER(rockchip_rk3328_spi);
+extern U_BOOT_DRIVER(rockchip_rk3328_grf);
+
+/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */
+extern UCLASS_DRIVER(clk);
+extern UCLASS_DRIVER(mmc);
+extern UCLASS_DRIVER(ram);
+extern UCLASS_DRIVER(serial);
+extern UCLASS_DRIVER(syscon);
--- /dev/null
+/*
+ * DO NOT MODIFY
+ *
+ * Declares the U_BOOT_DRIVER() records and platform data.
+ * This was generated by dtoc from a .dtb (device tree binary) file.
+ */
+
+/* Allow use of U_BOOT_DRVINFO() in this file */
+#define DT_PLAT_C
+
+#include <common.h>
+#include <dm.h>
+#include <dt-structs.h>
+
+/*
+ * driver_info declarations, ordered by 'struct driver_info' linker_list idx:
+ *
+ * idx driver_info driver
+ * --- -------------------- --------------------
+ * 0: clock_controller_at_ff440000 rockchip_rk3328_cru
+ * 1: dmc rockchip_rk3328_dmc
+ * 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc
+ * 3: serial_at_ff130000 ns16550_serial
+ * 4: spi_at_ff190000 rockchip_rk3328_spi
+ * 5: syscon_at_ff100000 rockchip_rk3328_grf
+ * --- -------------------- --------------------
+ */
+
+/*
+ * Node /clock-controller@ff440000 index 0
+ * driver rockchip_rk3328_cru parent None
+ */
+static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = {
+ .reg = {0xff440000, 0x1000},
+ .rockchip_grf = 0x38,
+};
+U_BOOT_DRVINFO(clock_controller_at_ff440000) = {
+ .name = "rockchip_rk3328_cru",
+ .plat = &dtv_clock_controller_at_ff440000,
+ .plat_size = sizeof(dtv_clock_controller_at_ff440000),
+ .parent_idx = -1,
+};
+
+/*
+ * Node /dmc index 1
+ * driver rockchip_rk3328_dmc parent None
+ */
+static struct dtd_rockchip_rk3328_dmc dtv_dmc = {
+ .reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000,
+ 0xff720000, 0x1000, 0xff798000, 0x1000},
+ .rockchip_sdram_params = {0x1, 0xa, 0x2, 0x1, 0x0, 0x0, 0x11, 0x0,
+ 0x11, 0x0, 0x0, 0x94291288, 0x0, 0x27, 0x462, 0x15,
+ 0x242, 0xff, 0x14d, 0x0, 0x1, 0x0, 0x0, 0x0,
+ 0x43049010, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x220000, 0xd8,
+ 0x100, 0xdc, 0x40000, 0xe0, 0x0, 0xe4, 0x110000, 0xe8,
+ 0x420, 0xec, 0x400, 0xf4, 0xf011f, 0x100, 0x9060b06, 0x104,
+ 0x20209, 0x108, 0x505040a, 0x10c, 0x40400c, 0x110, 0x5030206, 0x114,
+ 0x3030202, 0x120, 0x3030b03, 0x124, 0x20208, 0x180, 0x1000040, 0x184,
+ 0x0, 0x190, 0x7030003, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240,
+ 0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490, 0x1, 0xffffffff,
+ 0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xc, 0x28, 0xa, 0x2c,
+ 0x0, 0x30, 0x9, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79,
+ 0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87,
+ 0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78,
+ 0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77,
+ 0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77,
+ 0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
+ 0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77,
+ 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9,
+ 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
+ 0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77,
+ 0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78,
+ 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69,
+ 0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77,
+ 0x77, 0x77, 0x79, 0x9},
+};
+U_BOOT_DRVINFO(dmc) = {
+ .name = "rockchip_rk3328_dmc",
+ .plat = &dtv_dmc,
+ .plat_size = sizeof(dtv_dmc),
+ .parent_idx = -1,
+};
+
+/*
+ * Node /mmc@ff500000 index 2
+ * driver rockchip_rk3288_dw_mshc parent None
+ */
+static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = {
+ .bus_width = 0x4,
+ .cap_sd_highspeed = true,
+ .clocks = {
+ {0, {317}},
+ {0, {33}},
+ {0, {74}},
+ {0, {78}},},
+ .disable_wp = true,
+ .fifo_depth = 0x100,
+ .interrupts = {0x0, 0xc, 0x4},
+ .max_frequency = 0x8f0d180,
+ .pinctrl_0 = {0x45, 0x46, 0x47, 0x48},
+ .pinctrl_names = "default",
+ .reg = {0xff500000, 0x4000},
+ .u_boot_spl_fifo_mode = true,
+ .vmmc_supply = 0x49,
+};
+U_BOOT_DRVINFO(mmc_at_ff500000) = {
+ .name = "rockchip_rk3288_dw_mshc",
+ .plat = &dtv_mmc_at_ff500000,
+ .plat_size = sizeof(dtv_mmc_at_ff500000),
+ .parent_idx = -1,
+};
+
+/*
+ * Node /serial@ff130000 index 3
+ * driver ns16550_serial parent None
+ */
+static struct dtd_ns16550_serial dtv_serial_at_ff130000 = {
+ .clock_frequency = 0x16e3600,
+ .clocks = {
+ {0, {40}},
+ {0, {212}},},
+ .dma_names = {"tx", "rx"},
+ .dmas = {0x10, 0x6, 0x10, 0x7},
+ .interrupts = {0x0, 0x39, 0x4},
+ .pinctrl_0 = 0x24,
+ .pinctrl_names = "default",
+ .reg = {0xff130000, 0x100},
+ .reg_io_width = 0x4,
+ .reg_shift = 0x2,
+};
+U_BOOT_DRVINFO(serial_at_ff130000) = {
+ .name = "ns16550_serial",
+ .plat = &dtv_serial_at_ff130000,
+ .plat_size = sizeof(dtv_serial_at_ff130000),
+ .parent_idx = -1,
+};
+
+/* Node /spi@ff190000 index 4 */
+static struct dtd_rockchip_rk3328_spi dtv_spi_at_ff190000 = {
+ .clocks = {
+ {0, {32}},
+ {0, {209}},},
+ .dma_names = {"tx", "rx"},
+ .dmas = {0x10, 0x8, 0x10, 0x9},
+ .interrupts = {0x0, 0x31, 0x4},
+ .pinctrl_0 = {0x2c, 0x2d, 0x2e, 0x2f},
+ .pinctrl_names = "default",
+ .reg = {0xff190000, 0x1000},
+};
+U_BOOT_DRVINFO(spi_at_ff190000) = {
+ .name = "rockchip_rk3328_spi",
+ .plat = &dtv_spi_at_ff190000,
+ .plat_size = sizeof(dtv_spi_at_ff190000),
+ .parent_idx = -1,
+};
+
+/*
+ * Node /syscon@ff100000 index 5
+ * driver rockchip_rk3328_grf parent None
+ */
+static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = {
+ .reg = {0xff100000, 0x1000},
+};
+U_BOOT_DRVINFO(syscon_at_ff100000) = {
+ .name = "rockchip_rk3328_grf",
+ .plat = &dtv_syscon_at_ff100000,
+ .plat_size = sizeof(dtv_syscon_at_ff100000),
+ .parent_idx = -1,
+};
+
--- /dev/null
+/*
+ * DO NOT MODIFY
+ *
+ * Defines the structs used to hold devicetree data.
+ * This was generated by dtoc from a .dtb (device tree binary) file.
+ */
+
+#include <stdbool.h>
+#include <linux/libfdt.h>
+struct dtd_ns16550_serial {
+ fdt32_t clock_frequency;
+ struct phandle_1_arg clocks[2];
+ const char * dma_names[2];
+ fdt32_t dmas[4];
+ fdt32_t interrupts[3];
+ fdt32_t pinctrl_0;
+ const char * pinctrl_names;
+ fdt64_t reg[2];
+ fdt32_t reg_io_width;
+ fdt32_t reg_shift;
+};
+struct dtd_rockchip_rk3288_dw_mshc {
+ fdt32_t bus_width;
+ bool cap_sd_highspeed;
+ struct phandle_1_arg clocks[4];
+ bool disable_wp;
+ fdt32_t fifo_depth;
+ fdt32_t interrupts[3];
+ fdt32_t max_frequency;
+ fdt32_t pinctrl_0[4];
+ const char * pinctrl_names;
+ fdt64_t reg[2];
+ bool u_boot_spl_fifo_mode;
+ fdt32_t vmmc_supply;
+};
+struct dtd_rockchip_rk3328_cru {
+ fdt64_t reg[2];
+ fdt32_t rockchip_grf;
+};
+struct dtd_rockchip_rk3328_dmc {
+ fdt64_t reg[12];
+ fdt32_t rockchip_sdram_params[196];
+};
+struct dtd_rockchip_rk3328_grf {
+ fdt64_t reg[2];
+};
+struct dtd_rockchip_rk3328_spi {
+ struct phandle_1_arg clocks[2];
+ const char * dma_names[2];
+ fdt32_t dmas[4];
+ fdt32_t interrupts[3];
+ fdt32_t pinctrl_0[4];
+ const char * pinctrl_names;
+ fdt64_t reg[2];
+};
projects / openwrt / staging / stintel.git / commitdiff