--- /dev/null
+From b3f1a164c7f742503dc7159011f7ad6b092b660e Mon Sep 17 00:00:00 2001
+From: Greg Ungerer <gerg@kernel.org>
+Date: Fri, 24 Nov 2023 14:15:28 +1000
+Subject: [PATCH] net: dsa: mv88e6xxx: fix marvell 6350 switch probing
+
+As of commit de5c9bf40c45 ("net: phylink: require supported_interfaces to
+be filled") Marvell 88e6350 switches fail to be probed:
+
+ ...
+ mv88e6085 d0072004.mdio-mii:11: switch 0x3710 detected: Marvell 88E6350, revision 2
+ mv88e6085 d0072004.mdio-mii:11: phylink: error: empty supported_interfaces
+ error creating PHYLINK: -22
+ mv88e6085: probe of d0072004.mdio-mii:11 failed with error -22
+ ...
+
+The problem stems from the use of mv88e6185_phylink_get_caps() to get
+the device capabilities. Create a new dedicated phylink_get_caps for the
+6351 family (which the 6350 is one of) to properly support their set of
+capabilities.
+
+According to chip.h the 6351 switch family includes the 6171, 6175, 6350
+and 6351 switches, so update each of these to use the correct
+phylink_get_caps.
+
+Fixes: de5c9bf40c45 ("net: phylink: require supported_interfaces to be filled")
+Signed-off-by: Greg Ungerer <gerg@kernel.org>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/dsa/mv88e6xxx/chip.c | 20 ++++++++++++++++----
+ 1 file changed, 16 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/dsa/mv88e6xxx/chip.c
++++ b/drivers/net/dsa/mv88e6xxx/chip.c
+@@ -652,6 +652,18 @@ static void mv88e6250_phylink_get_caps(s
+ config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
+ }
+
++static void mv88e6351_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
++ struct phylink_config *config)
++{
++ unsigned long *supported = config->supported_interfaces;
++
++ /* Translate the default cmode */
++ mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
++
++ config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
++ MAC_1000FD;
++}
++
+ static int mv88e6352_get_port4_serdes_cmode(struct mv88e6xxx_chip *chip)
+ {
+ u16 reg, val;
+@@ -4489,7 +4501,7 @@ static const struct mv88e6xxx_ops mv88e6
+ .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
+ .stu_getnext = mv88e6352_g1_stu_getnext,
+ .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
+- .phylink_get_caps = mv88e6185_phylink_get_caps,
++ .phylink_get_caps = mv88e6351_phylink_get_caps,
+ };
+
+ static const struct mv88e6xxx_ops mv88e6172_ops = {
+@@ -4590,7 +4602,7 @@ static const struct mv88e6xxx_ops mv88e6
+ .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
+ .stu_getnext = mv88e6352_g1_stu_getnext,
+ .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
+- .phylink_get_caps = mv88e6185_phylink_get_caps,
++ .phylink_get_caps = mv88e6351_phylink_get_caps,
+ };
+
+ static const struct mv88e6xxx_ops mv88e6176_ops = {
+@@ -5247,7 +5259,7 @@ static const struct mv88e6xxx_ops mv88e6
+ .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
+ .stu_getnext = mv88e6352_g1_stu_getnext,
+ .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
+- .phylink_get_caps = mv88e6185_phylink_get_caps,
++ .phylink_get_caps = mv88e6351_phylink_get_caps,
+ };
+
+ static const struct mv88e6xxx_ops mv88e6351_ops = {
+@@ -5293,7 +5305,7 @@ static const struct mv88e6xxx_ops mv88e6
+ .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
+ .avb_ops = &mv88e6352_avb_ops,
+ .ptp_ops = &mv88e6352_ptp_ops,
+- .phylink_get_caps = mv88e6185_phylink_get_caps,
++ .phylink_get_caps = mv88e6351_phylink_get_caps,
+ };
+
+ static const struct mv88e6xxx_ops mv88e6352_ops = {
__set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
} else {
if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) &&
-@@ -839,7 +837,7 @@ static void mv88e6xxx_get_caps(struct ds
+@@ -851,7 +849,7 @@ static void mv88e6xxx_get_caps(struct ds
chip->info->ops->phylink_get_caps(chip, port, config);
mv88e6xxx_reg_unlock(chip);
__set_bit(PHY_INTERFACE_MODE_INTERNAL,
config->supported_interfaces);
/* Internal ports with no phy-mode need GMII for PHYLIB */
-@@ -860,7 +858,7 @@ static void mv88e6xxx_mac_config(struct
+@@ -872,7 +870,7 @@ static void mv88e6xxx_mac_config(struct
mv88e6xxx_reg_lock(chip);
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
-@@ -5944,7 +5944,8 @@ static const struct mv88e6xxx_info mv88e
+@@ -5956,7 +5956,8 @@ static const struct mv88e6xxx_info mv88e
.name = "Marvell 88E6191X",
.num_databases = 4096,
.num_ports = 11, /* 10 + Z80 */
.max_vid = 8191,
.max_sid = 63,
.port_base_addr = 0x0,
-@@ -5967,7 +5968,8 @@ static const struct mv88e6xxx_info mv88e
+@@ -5979,7 +5980,8 @@ static const struct mv88e6xxx_info mv88e
.name = "Marvell 88E6193X",
.num_databases = 4096,
.num_ports = 11, /* 10 + Z80 */
.max_vid = 8191,
.max_sid = 63,
.port_base_addr = 0x0,
-@@ -6286,7 +6288,8 @@ static const struct mv88e6xxx_info mv88e
+@@ -6298,7 +6300,8 @@ static const struct mv88e6xxx_info mv88e
.name = "Marvell 88E6393X",
.num_databases = 4096,
.num_ports = 11, /* 10 + Z80 */
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
-@@ -3328,7 +3328,7 @@ static int mv88e6xxx_setup_port(struct m
+@@ -3340,7 +3340,7 @@ static int mv88e6xxx_setup_port(struct m
caps = pl_config.mac_capabilities;
if (chip->info->ops->port_max_speed_mode)
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
-@@ -797,6 +797,8 @@ static void mv88e6393x_phylink_get_caps(
+@@ -809,6 +809,8 @@ static void mv88e6393x_phylink_get_caps(
unsigned long *supported = config->supported_interfaces;
bool is_6191x =
chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X;
mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
-@@ -811,13 +813,17 @@ static void mv88e6393x_phylink_get_caps(
+@@ -823,13 +825,17 @@ static void mv88e6393x_phylink_get_caps(
/* 6191X supports >1G modes only on port 10 */
if (!is_6191x || port == 10) {
__set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
}
}
-@@ -6231,6 +6237,32 @@ static const struct mv88e6xxx_info mv88e
+@@ -6243,6 +6249,32 @@ static const struct mv88e6xxx_info mv88e
.ptp_support = true,
.ops = &mv88e6352_ops,
},
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
-@@ -3488,6 +3488,9 @@ static int mv88e6xxx_setup_port(struct m
+@@ -3500,6 +3500,9 @@ static int mv88e6xxx_setup_port(struct m
else
reg = 1 << port;
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
-@@ -7025,6 +7025,7 @@ static int mv88e6xxx_register_switch(str
+@@ -7037,6 +7037,7 @@ static int mv88e6xxx_register_switch(str
ds->ops = &mv88e6xxx_switch_ops;
ds->ageing_time_min = chip->info->age_time_coeff;
ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
+++ /dev/null
-From b3f1a164c7f742503dc7159011f7ad6b092b660e Mon Sep 17 00:00:00 2001
-From: Greg Ungerer <gerg@kernel.org>
-Date: Fri, 24 Nov 2023 14:15:28 +1000
-Subject: [PATCH] net: dsa: mv88e6xxx: fix marvell 6350 switch probing
-
-As of commit de5c9bf40c45 ("net: phylink: require supported_interfaces to
-be filled") Marvell 88e6350 switches fail to be probed:
-
- ...
- mv88e6085 d0072004.mdio-mii:11: switch 0x3710 detected: Marvell 88E6350, revision 2
- mv88e6085 d0072004.mdio-mii:11: phylink: error: empty supported_interfaces
- error creating PHYLINK: -22
- mv88e6085: probe of d0072004.mdio-mii:11 failed with error -22
- ...
-
-The problem stems from the use of mv88e6185_phylink_get_caps() to get
-the device capabilities. Create a new dedicated phylink_get_caps for the
-6351 family (which the 6350 is one of) to properly support their set of
-capabilities.
-
-According to chip.h the 6351 switch family includes the 6171, 6175, 6350
-and 6351 switches, so update each of these to use the correct
-phylink_get_caps.
-
-Fixes: de5c9bf40c45 ("net: phylink: require supported_interfaces to be filled")
-Signed-off-by: Greg Ungerer <gerg@kernel.org>
-Reviewed-by: Andrew Lunn <andrew@lunn.ch>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/dsa/mv88e6xxx/chip.c | 20 ++++++++++++++++----
- 1 file changed, 16 insertions(+), 4 deletions(-)
-
---- a/drivers/net/dsa/mv88e6xxx/chip.c
-+++ b/drivers/net/dsa/mv88e6xxx/chip.c
-@@ -652,6 +652,18 @@ static void mv88e6250_phylink_get_caps(s
- config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
- }
-
-+static void mv88e6351_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
-+ struct phylink_config *config)
-+{
-+ unsigned long *supported = config->supported_interfaces;
-+
-+ /* Translate the default cmode */
-+ mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
-+
-+ config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
-+ MAC_1000FD;
-+}
-+
- static int mv88e6352_get_port4_serdes_cmode(struct mv88e6xxx_chip *chip)
- {
- u16 reg, val;
-@@ -4498,7 +4510,7 @@ static const struct mv88e6xxx_ops mv88e6
- .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
- .stu_getnext = mv88e6352_g1_stu_getnext,
- .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
-- .phylink_get_caps = mv88e6185_phylink_get_caps,
-+ .phylink_get_caps = mv88e6351_phylink_get_caps,
- };
-
- static const struct mv88e6xxx_ops mv88e6172_ops = {
-@@ -4599,7 +4611,7 @@ static const struct mv88e6xxx_ops mv88e6
- .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
- .stu_getnext = mv88e6352_g1_stu_getnext,
- .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
-- .phylink_get_caps = mv88e6185_phylink_get_caps,
-+ .phylink_get_caps = mv88e6351_phylink_get_caps,
- };
-
- static const struct mv88e6xxx_ops mv88e6176_ops = {
-@@ -5256,7 +5268,7 @@ static const struct mv88e6xxx_ops mv88e6
- .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
- .stu_getnext = mv88e6352_g1_stu_getnext,
- .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
-- .phylink_get_caps = mv88e6185_phylink_get_caps,
-+ .phylink_get_caps = mv88e6351_phylink_get_caps,
- };
-
- static const struct mv88e6xxx_ops mv88e6351_ops = {
-@@ -5302,7 +5314,7 @@ static const struct mv88e6xxx_ops mv88e6
- .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
- .avb_ops = &mv88e6352_avb_ops,
- .ptp_ops = &mv88e6352_ptp_ops,
-- .phylink_get_caps = mv88e6185_phylink_get_caps,
-+ .phylink_get_caps = mv88e6351_phylink_get_caps,
- };
-
- static const struct mv88e6xxx_ops mv88e6352_ops = {
projects / openwrt / staging / stintel.git / commitdiff