target/linux/starfive/patches-6.1/0102-hwrng-starfive-Add-TRNG-driver-for-StarFive-SoC.patch

   1 From 99a7ca1d1320288efc5b4532ce4ea637d622aa00 Mon Sep 17 00:00:00 2001
   2 From: Jia Jie Ho <jiajie.ho@starfivetech.com>
   3 Date: Tue, 17 Jan 2023 09:54:44 +0800
   4 Subject: [PATCH 102/122] hwrng: starfive - Add TRNG driver for StarFive SoC
   5
   6 This adds driver support for the hardware random number generator in
   7 Starfive SoCs and adds StarFive TRNG entry to MAINTAINERS.
   8
   9 Co-developed-by: Jenny Zhang <jenny.zhang@starfivetech.com>
  10 Signed-off-by: Jenny Zhang <jenny.zhang@starfivetech.com>
  11 Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com>
  12 ---
  13  MAINTAINERS                          |   6 +
  14  drivers/char/hw_random/Kconfig       |  11 +
  15  drivers/char/hw_random/Makefile      |   1 +
  16  drivers/char/hw_random/jh7110-trng.c | 393 +++++++++++++++++++++++++++
  17  4 files changed, 411 insertions(+)
  18  create mode 100644 drivers/char/hw_random/jh7110-trng.c
  19
  20 --- a/MAINTAINERS
  21 +++ b/MAINTAINERS
  22 @@ -19716,6 +19716,12 @@ F:     Documentation/devicetree/bindings/pow
  23  F:     drivers/soc/starfive/jh71xx_pmu.c
  24  F:     include/dt-bindings/power/starfive,jh7110-pmu.h
  25
  26 +STARFIVE TRNG DRIVER
  27 +M:     Jia Jie Ho <jiajie.ho@starfivetech.com>
  28 +S:     Supported
  29 +F:     Documentation/devicetree/bindings/rng/starfive*
  30 +F:     drivers/char/hw_random/starfive-trng.c
  31 +
  32  STATIC BRANCH/CALL
  33  M:     Peter Zijlstra <peterz@infradead.org>
  34  M:     Josh Poimboeuf <jpoimboe@kernel.org>
  35 --- a/drivers/char/hw_random/Kconfig
  36 +++ b/drivers/char/hw_random/Kconfig
  37 @@ -549,6 +549,17 @@ config HW_RANDOM_CN10K
  38          To compile this driver as a module, choose M here.
  39          The module will be called cn10k_rng. If unsure, say Y.
  40
  41 +config HW_RANDOM_JH7110
  42 +       tristate "StarFive JH7110 Random Number Generator support"
  43 +       depends on SOC_STARFIVE
  44 +       depends on HW_RANDOM
  45 +       help
  46 +         This driver provides support for the True Random Number
  47 +         Generator in StarFive JH7110 SoCs.
  48 +
  49 +         To compile this driver as a module, choose M here.
  50 +         The module will be called jh7110-trng.
  51 +
  52  endif # HW_RANDOM
  53
  54  config UML_RANDOM
  55 --- a/drivers/char/hw_random/Makefile
  56 +++ b/drivers/char/hw_random/Makefile
  57 @@ -47,3 +47,4 @@ obj-$(CONFIG_HW_RANDOM_XIPHERA) += xiphe
  58  obj-$(CONFIG_HW_RANDOM_ARM_SMCCC_TRNG) += arm_smccc_trng.o
  59  obj-$(CONFIG_HW_RANDOM_CN10K) += cn10k-rng.o
  60  obj-$(CONFIG_HW_RANDOM_POLARFIRE_SOC) += mpfs-rng.o
  61 +obj-$(CONFIG_HW_RANDOM_JH7110) += jh7110-trng.o
  62 --- /dev/null
  63 +++ b/drivers/char/hw_random/jh7110-trng.c
  64 @@ -0,0 +1,393 @@
  65 +// SPDX-License-Identifier: GPL-2.0
  66 +/*
  67 + * TRNG driver for the StarFive JH7110 SoC
  68 + *
  69 + * Copyright (C) 2022 StarFive Technology Co.
  70 + */
  71 +
  72 +#include <linux/clk.h>
  73 +#include <linux/completion.h>
  74 +#include <linux/delay.h>
  75 +#include <linux/err.h>
  76 +#include <linux/hw_random.h>
  77 +#include <linux/interrupt.h>
  78 +#include <linux/io.h>
  79 +#include <linux/iopoll.h>
  80 +#include <linux/kernel.h>
  81 +#include <linux/module.h>
  82 +#include <linux/of.h>
  83 +#include <linux/platform_device.h>
  84 +#include <linux/pm_runtime.h>
  85 +#include <linux/random.h>
  86 +#include <linux/reset.h>
  87 +
  88 +/* trng register offset */
  89 +#define STARFIVE_CTRL                  0x00
  90 +#define STARFIVE_STAT                  0x04
  91 +#define STARFIVE_MODE                  0x08
  92 +#define STARFIVE_SMODE                 0x0C
  93 +#define STARFIVE_IE                    0x10
  94 +#define STARFIVE_ISTAT                 0x14
  95 +#define STARFIVE_RAND0                 0x20
  96 +#define STARFIVE_RAND1                 0x24
  97 +#define STARFIVE_RAND2                 0x28
  98 +#define STARFIVE_RAND3                 0x2C
  99 +#define STARFIVE_RAND4                 0x30
 100 +#define STARFIVE_RAND5                 0x34
 101 +#define STARFIVE_RAND6                 0x38
 102 +#define STARFIVE_RAND7                 0x3C
 103 +#define STARFIVE_AUTO_RQSTS            0x60
 104 +#define STARFIVE_AUTO_AGE              0x64
 105 +
 106 +/* CTRL CMD */
 107 +#define STARFIVE_CTRL_EXEC_NOP         0x0
 108 +#define STARFIVE_CTRL_GENE_RANDNUM     0x1
 109 +#define STARFIVE_CTRL_EXEC_RANDRESEED  0x2
 110 +
 111 +/* STAT */
 112 +#define STARFIVE_STAT_NONCE_MODE       BIT(2)
 113 +#define STARFIVE_STAT_R256             BIT(3)
 114 +#define STARFIVE_STAT_MISSION_MODE     BIT(8)
 115 +#define STARFIVE_STAT_SEEDED           BIT(9)
 116 +#define STARFIVE_STAT_LAST_RESEED(x)   ((x) << 16)
 117 +#define STARFIVE_STAT_SRVC_RQST                BIT(27)
 118 +#define STARFIVE_STAT_RAND_GENERATING  BIT(30)
 119 +#define STARFIVE_STAT_RAND_SEEDING     BIT(31)
 120 +
 121 +/* MODE */
 122 +#define STARFIVE_MODE_R256             BIT(3)
 123 +
 124 +/* SMODE */
 125 +#define STARFIVE_SMODE_NONCE_MODE      BIT(2)
 126 +#define STARFIVE_SMODE_MISSION_MODE    BIT(8)
 127 +#define STARFIVE_SMODE_MAX_REJECTS(x)  ((x) << 16)
 128 +
 129 +/* IE */
 130 +#define STARFIVE_IE_RAND_RDY_EN                BIT(0)
 131 +#define STARFIVE_IE_SEED_DONE_EN       BIT(1)
 132 +#define STARFIVE_IE_LFSR_LOCKUP_EN     BIT(4)
 133 +#define STARFIVE_IE_GLBL_EN            BIT(31)
 134 +
 135 +#define STARFIVE_IE_ALL                        (STARFIVE_IE_GLBL_EN | \
 136 +                                        STARFIVE_IE_RAND_RDY_EN | \
 137 +                                        STARFIVE_IE_SEED_DONE_EN | \
 138 +                                        STARFIVE_IE_LFSR_LOCKUP_EN)
 139 +
 140 +/* ISTAT */
 141 +#define STARFIVE_ISTAT_RAND_RDY                BIT(0)
 142 +#define STARFIVE_ISTAT_SEED_DONE       BIT(1)
 143 +#define STARFIVE_ISTAT_LFSR_LOCKUP     BIT(4)
 144 +
 145 +#define STARFIVE_RAND_LEN              sizeof(u32)
 146 +
 147 +#define to_trng(p)                     container_of(p, struct starfive_trng, rng)
 148 +
 149 +enum reseed {
 150 +       RANDOM_RESEED,
 151 +       NONCE_RESEED,
 152 +};
 153 +
 154 +enum mode {
 155 +       PRNG_128BIT,
 156 +       PRNG_256BIT,
 157 +};
 158 +
 159 +struct starfive_trng {
 160 +       struct device           *dev;
 161 +       void __iomem            *base;
 162 +       struct clk              *hclk;
 163 +       struct clk              *ahb;
 164 +       struct reset_control    *rst;
 165 +       struct hwrng            rng;
 166 +       struct completion       random_done;
 167 +       struct completion       reseed_done;
 168 +       u32                     mode;
 169 +       u32                     mission;
 170 +       u32                     reseed;
 171 +       /* protects against concurrent write to ctrl register */
 172 +       spinlock_t              write_lock;
 173 +};
 174 +
 175 +static u16 autoreq;
 176 +module_param(autoreq, ushort, 0);
 177 +MODULE_PARM_DESC(autoreq, "Auto-reseeding after random number requests by host reaches specified counter:\n"
 178 +                               " 0 - disable counter\n"
 179 +                               " other - reload value for internal counter");
 180 +
 181 +static u16 autoage;
 182 +module_param(autoage, ushort, 0);
 183 +MODULE_PARM_DESC(autoage, "Auto-reseeding after specified timer countdowns to 0:\n"
 184 +                               " 0 - disable timer\n"
 185 +                               " other - reload value for internal timer");
 186 +
 187 +static inline int starfive_trng_wait_idle(struct starfive_trng *trng)
 188 +{
 189 +       u32 stat;
 190 +
 191 +       return readl_relaxed_poll_timeout(trng->base + STARFIVE_STAT, stat,
 192 +                                         !(stat & (STARFIVE_STAT_RAND_GENERATING |
 193 +                                                   STARFIVE_STAT_RAND_SEEDING)),
 194 +                                         10, 100000);
 195 +}
 196 +
 197 +static inline void starfive_trng_irq_mask_clear(struct starfive_trng *trng)
 198 +{
 199 +       /* clear register: ISTAT */
 200 +       u32 data = readl(trng->base + STARFIVE_ISTAT);
 201 +
 202 +       writel(data, trng->base + STARFIVE_ISTAT);
 203 +}
 204 +
 205 +static int starfive_trng_cmd(struct starfive_trng *trng, u32 cmd, bool wait)
 206 +{
 207 +       int wait_time = 1000;
 208 +
 209 +       /* allow up to 40 us for wait == 0 */
 210 +       if (!wait)
 211 +               wait_time = 40;
 212 +
 213 +       switch (cmd) {
 214 +       case STARFIVE_CTRL_GENE_RANDNUM:
 215 +               reinit_completion(&trng->random_done);
 216 +               spin_lock_irq(&trng->write_lock);
 217 +               writel(cmd, trng->base + STARFIVE_CTRL);
 218 +               spin_unlock_irq(&trng->write_lock);
 219 +               if (!wait_for_completion_timeout(&trng->random_done, usecs_to_jiffies(wait_time)))
 220 +                       return -ETIMEDOUT;
 221 +               break;
 222 +       case STARFIVE_CTRL_EXEC_RANDRESEED:
 223 +               reinit_completion(&trng->reseed_done);
 224 +               spin_lock_irq(&trng->write_lock);
 225 +               writel(cmd, trng->base + STARFIVE_CTRL);
 226 +               spin_unlock_irq(&trng->write_lock);
 227 +               if (!wait_for_completion_timeout(&trng->reseed_done, usecs_to_jiffies(wait_time)))
 228 +                       return -ETIMEDOUT;
 229 +               break;
 230 +       default:
 231 +               return -EINVAL;
 232 +       }
 233 +
 234 +       return 0;
 235 +}
 236 +
 237 +static int starfive_trng_init(struct hwrng *rng)
 238 +{
 239 +       struct starfive_trng *trng = to_trng(rng);
 240 +       u32 mode, intr = 0;
 241 +
 242 +       /* setup Auto Request/Age register */
 243 +       writel(autoage, trng->base + STARFIVE_AUTO_AGE);
 244 +       writel(autoreq, trng->base + STARFIVE_AUTO_RQSTS);
 245 +
 246 +       /* clear register: ISTAT */
 247 +       starfive_trng_irq_mask_clear(trng);
 248 +
 249 +       intr |= STARFIVE_IE_ALL;
 250 +       writel(intr, trng->base + STARFIVE_IE);
 251 +
 252 +       mode  = readl(trng->base + STARFIVE_MODE);
 253 +
 254 +       switch (trng->mode) {
 255 +       case PRNG_128BIT:
 256 +               mode &= ~STARFIVE_MODE_R256;
 257 +               break;
 258 +       case PRNG_256BIT:
 259 +               mode |= STARFIVE_MODE_R256;
 260 +               break;
 261 +       default:
 262 +               mode |= STARFIVE_MODE_R256;
 263 +               break;
 264 +       }
 265 +
 266 +       writel(mode, trng->base + STARFIVE_MODE);
 267 +
 268 +       return starfive_trng_cmd(trng, STARFIVE_CTRL_EXEC_RANDRESEED, 1);
 269 +}
 270 +
 271 +static irqreturn_t starfive_trng_irq(int irq, void *priv)
 272 +{
 273 +       u32 status;
 274 +       struct starfive_trng *trng = (struct starfive_trng *)priv;
 275 +
 276 +       status = readl(trng->base + STARFIVE_ISTAT);
 277 +       if (status & STARFIVE_ISTAT_RAND_RDY) {
 278 +               writel(STARFIVE_ISTAT_RAND_RDY, trng->base + STARFIVE_ISTAT);
 279 +               complete(&trng->random_done);
 280 +       }
 281 +
 282 +       if (status & STARFIVE_ISTAT_SEED_DONE) {
 283 +               writel(STARFIVE_ISTAT_SEED_DONE, trng->base + STARFIVE_ISTAT);
 284 +               complete(&trng->reseed_done);
 285 +       }
 286 +
 287 +       if (status & STARFIVE_ISTAT_LFSR_LOCKUP) {
 288 +               writel(STARFIVE_ISTAT_LFSR_LOCKUP, trng->base + STARFIVE_ISTAT);
 289 +               /* SEU occurred, reseeding required*/
 290 +               spin_lock(&trng->write_lock);
 291 +               writel(STARFIVE_CTRL_EXEC_RANDRESEED, trng->base + STARFIVE_CTRL);
 292 +               spin_unlock(&trng->write_lock);
 293 +       }
 294 +
 295 +       return IRQ_HANDLED;
 296 +}
 297 +
 298 +static void starfive_trng_cleanup(struct hwrng *rng)
 299 +{
 300 +       struct starfive_trng *trng = to_trng(rng);
 301 +
 302 +       writel(0, trng->base + STARFIVE_CTRL);
 303 +
 304 +       reset_control_assert(trng->rst);
 305 +       clk_disable_unprepare(trng->hclk);
 306 +       clk_disable_unprepare(trng->ahb);
 307 +}
 308 +
 309 +static int starfive_trng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
 310 +{
 311 +       struct starfive_trng *trng = to_trng(rng);
 312 +       int ret;
 313 +
 314 +       pm_runtime_get_sync(trng->dev);
 315 +
 316 +       if (trng->mode == PRNG_256BIT)
 317 +               max = min_t(size_t, max, (STARFIVE_RAND_LEN * 8));
 318 +       else
 319 +               max = min_t(size_t, max, (STARFIVE_RAND_LEN * 4));
 320 +
 321 +       if (wait) {
 322 +               ret = starfive_trng_wait_idle(trng);
 323 +               if (ret)
 324 +                       return -ETIMEDOUT;
 325 +       }
 326 +
 327 +       ret = starfive_trng_cmd(trng, STARFIVE_CTRL_GENE_RANDNUM, wait);
 328 +       if (ret)
 329 +               return ret;
 330 +
 331 +       memcpy_fromio(buf, trng->base + STARFIVE_RAND0, max);
 332 +
 333 +       pm_runtime_put_sync_autosuspend(trng->dev);
 334 +
 335 +       return max;
 336 +}
 337 +
 338 +static int starfive_trng_probe(struct platform_device *pdev)
 339 +{
 340 +       int ret;
 341 +       int irq;
 342 +       struct starfive_trng *trng;
 343 +
 344 +       trng = devm_kzalloc(&pdev->dev, sizeof(*trng), GFP_KERNEL);
 345 +       if (!trng)
 346 +               return -ENOMEM;
 347 +
 348 +       platform_set_drvdata(pdev, trng);
 349 +       trng->dev = &pdev->dev;
 350 +
 351 +       trng->base = devm_platform_ioremap_resource(pdev, 0);
 352 +       if (IS_ERR(trng->base))
 353 +               return dev_err_probe(&pdev->dev, PTR_ERR(trng->base),
 354 +                                    "Error remapping memory for platform device.\n");
 355 +
 356 +       irq = platform_get_irq(pdev, 0);
 357 +       if (irq < 0)
 358 +               return irq;
 359 +
 360 +       init_completion(&trng->random_done);
 361 +       init_completion(&trng->reseed_done);
 362 +       spin_lock_init(&trng->write_lock);
 363 +
 364 +       ret = devm_request_irq(&pdev->dev, irq, starfive_trng_irq, 0, pdev->name,
 365 +                              (void *)trng);
 366 +       if (ret)
 367 +               return dev_err_probe(&pdev->dev, irq,
 368 +                                    "Failed to register interrupt handler\n");
 369 +
 370 +       trng->hclk = devm_clk_get(&pdev->dev, "hclk");
 371 +       if (IS_ERR(trng->hclk))
 372 +               return dev_err_probe(&pdev->dev, PTR_ERR(trng->hclk),
 373 +                                    "Error getting hardware reference clock\n");
 374 +
 375 +       trng->ahb = devm_clk_get(&pdev->dev, "ahb");
 376 +       if (IS_ERR(trng->ahb))
 377 +               return dev_err_probe(&pdev->dev, PTR_ERR(trng->ahb),
 378 +                                    "Error getting ahb reference clock\n");
 379 +
 380 +       trng->rst = devm_reset_control_get_shared(&pdev->dev, NULL);
 381 +       if (IS_ERR(trng->rst))
 382 +               return dev_err_probe(&pdev->dev, PTR_ERR(trng->rst),
 383 +                                    "Error getting hardware reset line\n");
 384 +
 385 +       clk_prepare_enable(trng->hclk);
 386 +       clk_prepare_enable(trng->ahb);
 387 +       reset_control_deassert(trng->rst);
 388 +
 389 +       trng->rng.name = dev_driver_string(&pdev->dev);
 390 +       trng->rng.init = starfive_trng_init;
 391 +       trng->rng.cleanup = starfive_trng_cleanup;
 392 +       trng->rng.read = starfive_trng_read;
 393 +
 394 +       trng->mode = PRNG_256BIT;
 395 +       trng->mission = 1;
 396 +       trng->reseed = RANDOM_RESEED;
 397 +
 398 +       pm_runtime_use_autosuspend(&pdev->dev);
 399 +       pm_runtime_set_autosuspend_delay(&pdev->dev, 100);
 400 +       pm_runtime_enable(&pdev->dev);
 401 +
 402 +       ret = devm_hwrng_register(&pdev->dev, &trng->rng);
 403 +       if (ret) {
 404 +               pm_runtime_disable(&pdev->dev);
 405 +
 406 +               reset_control_assert(trng->rst);
 407 +               clk_disable_unprepare(trng->ahb);
 408 +               clk_disable_unprepare(trng->hclk);
 409 +
 410 +               return dev_err_probe(&pdev->dev, ret, "Failed to register hwrng\n");
 411 +       }
 412 +
 413 +       return 0;
 414 +}
 415 +
 416 +static int __maybe_unused starfive_trng_suspend(struct device *dev)
 417 +{
 418 +       struct starfive_trng *trng = dev_get_drvdata(dev);
 419 +
 420 +       clk_disable_unprepare(trng->hclk);
 421 +       clk_disable_unprepare(trng->ahb);
 422 +
 423 +       return 0;
 424 +}
 425 +
 426 +static int __maybe_unused starfive_trng_resume(struct device *dev)
 427 +{
 428 +       struct starfive_trng *trng = dev_get_drvdata(dev);
 429 +
 430 +       clk_prepare_enable(trng->hclk);
 431 +       clk_prepare_enable(trng->ahb);
 432 +
 433 +       return 0;
 434 +}
 435 +
 436 +static DEFINE_SIMPLE_DEV_PM_OPS(starfive_trng_pm_ops, starfive_trng_suspend,
 437 +                               starfive_trng_resume);
 438 +
 439 +static const struct of_device_id trng_dt_ids[] __maybe_unused = {
 440 +       { .compatible = "starfive,jh7110-trng" },
 441 +       { }
 442 +};
 443 +MODULE_DEVICE_TABLE(of, trng_dt_ids);
 444 +
 445 +static struct platform_driver starfive_trng_driver = {
 446 +       .probe  = starfive_trng_probe,
 447 +       .driver = {
 448 +               .name           = "jh7110-trng",
 449 +               .pm             = &starfive_trng_pm_ops,
 450 +               .of_match_table = of_match_ptr(trng_dt_ids),
 451 +       },
 452 +};
 453 +
 454 +module_platform_driver(starfive_trng_driver);
 455 +
 456 +MODULE_LICENSE("GPL");
 457 +MODULE_DESCRIPTION("StarFive True Random Number Generator");