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realtek: rtl83xx-phy: fix RTL8214FC media change
[openwrt/staging/stintel.git] / target / linux / realtek / files-5.10 / drivers / net / phy / rtl83xx-phy.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Realtek RTL838X Ethernet MDIO interface driver
3 *
4 * Copyright (C) 2020 B. Koblitz
5 */
6
7 #include <linux/module.h>
8 #include <linux/delay.h>
9 #include <linux/phy.h>
10 #include <linux/netdevice.h>
11 #include <linux/firmware.h>
12 #include <linux/crc32.h>
13
14 #include <asm/mach-rtl838x/mach-rtl83xx.h>
15 #include "rtl83xx-phy.h"
16
17 extern struct rtl83xx_soc_info soc_info;
18 extern struct mutex smi_lock;
19
20 #define PHY_CTRL_REG 0
21 #define PHY_POWER_BIT 11
22
23 #define PHY_PAGE_2 2
24 #define PHY_PAGE_4 4
25
26 /* all Clause-22 RealTek MDIO PHYs use register 0x1f for page select */
27 #define RTL8XXX_PAGE_SELECT 0x1f
28
29 #define RTL8XXX_PAGE_MAIN 0x0000
30 #define RTL821X_PAGE_PORT 0x0266
31 #define RTL821X_PAGE_POWER 0x0a40
32 #define RTL821X_PAGE_GPHY 0x0a42
33 #define RTL821X_PAGE_MAC 0x0a43
34 #define RTL821X_PAGE_STATE 0x0b80
35 #define RTL821X_PAGE_PATCH 0x0b82
36
37 /*
38 * Using the special page 0xfff with the MDIO controller found in
39 * RealTek SoCs allows to access the PHY in RAW mode, ie. bypassing
40 * the cache and paging engine of the MDIO controller.
41 */
42 #define RTL83XX_PAGE_RAW 0x0fff
43
44 /* internal RTL821X PHY uses register 0x1d to select media page */
45 #define RTL821XINT_MEDIA_PAGE_SELECT 0x1d
46 /* external RTL821X PHY uses register 0x1e to select media page */
47 #define RTL821XEXT_MEDIA_PAGE_SELECT 0x1e
48
49 #define RTL821X_MEDIA_PAGE_AUTO 0
50 #define RTL821X_MEDIA_PAGE_COPPER 1
51 #define RTL821X_MEDIA_PAGE_FIBRE 3
52 #define RTL821X_MEDIA_PAGE_INTERNAL 8
53
54 #define RTL9300_PHY_ID_MASK 0xf0ffffff
55
56 /*
57 * This lock protects the state of the SoC automatically polling the PHYs over the SMI
58 * bus to detect e.g. link and media changes. For operations on the PHYs such as
59 * patching or other configuration changes such as EEE, polling needs to be disabled
60 * since otherwise these operations may fails or lead to unpredictable results.
61 */
62 DEFINE_MUTEX(poll_lock);
63
64 static const struct firmware rtl838x_8380_fw;
65 static const struct firmware rtl838x_8214fc_fw;
66 static const struct firmware rtl838x_8218b_fw;
67
68 static u64 disable_polling(int port)
69 {
70 u64 saved_state;
71
72 mutex_lock(&poll_lock);
73
74 switch (soc_info.family) {
75 case RTL8380_FAMILY_ID:
76 saved_state = sw_r32(RTL838X_SMI_POLL_CTRL);
77 sw_w32_mask(BIT(port), 0, RTL838X_SMI_POLL_CTRL);
78 break;
79 case RTL8390_FAMILY_ID:
80 saved_state = sw_r32(RTL839X_SMI_PORT_POLLING_CTRL + 4);
81 saved_state <<= 32;
82 saved_state |= sw_r32(RTL839X_SMI_PORT_POLLING_CTRL);
83 sw_w32_mask(BIT(port % 32), 0,
84 RTL839X_SMI_PORT_POLLING_CTRL + ((port >> 5) << 2));
85 break;
86 case RTL9300_FAMILY_ID:
87 saved_state = sw_r32(RTL930X_SMI_POLL_CTRL);
88 sw_w32_mask(BIT(port), 0, RTL930X_SMI_POLL_CTRL);
89 break;
90 case RTL9310_FAMILY_ID:
91 pr_warn("%s not implemented for RTL931X\n", __func__);
92 break;
93 }
94
95 mutex_unlock(&poll_lock);
96
97 return saved_state;
98 }
99
100 static int resume_polling(u64 saved_state)
101 {
102 mutex_lock(&poll_lock);
103
104 switch (soc_info.family) {
105 case RTL8380_FAMILY_ID:
106 sw_w32(saved_state, RTL838X_SMI_POLL_CTRL);
107 break;
108 case RTL8390_FAMILY_ID:
109 sw_w32(saved_state >> 32, RTL839X_SMI_PORT_POLLING_CTRL + 4);
110 sw_w32(saved_state, RTL839X_SMI_PORT_POLLING_CTRL);
111 break;
112 case RTL9300_FAMILY_ID:
113 sw_w32(saved_state, RTL930X_SMI_POLL_CTRL);
114 break;
115 case RTL9310_FAMILY_ID:
116 pr_warn("%s not implemented for RTL931X\n", __func__);
117 break;
118 }
119
120 mutex_unlock(&poll_lock);
121
122 return 0;
123 }
124
125 static void rtl8380_int_phy_on_off(struct phy_device *phydev, bool on)
126 {
127 phy_modify(phydev, 0, BIT(11), on?0:BIT(11));
128 }
129
130 static void rtl8380_rtl8214fc_on_off(struct phy_device *phydev, bool on)
131 {
132 /* fiber ports */
133 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_FIBRE);
134 phy_modify(phydev, 0x10, BIT(11), on?0:BIT(11));
135
136 /* copper ports */
137 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
138 phy_modify_paged(phydev, RTL821X_PAGE_POWER, 0x10, BIT(11), on?0:BIT(11));
139 }
140
141 static void rtl8380_phy_reset(struct phy_device *phydev)
142 {
143 phy_modify(phydev, 0, BIT(15), BIT(15));
144 }
145
146 // The access registers for SDS_MODE_SEL and the LSB for each SDS within
147 u16 rtl9300_sds_regs[] = { 0x0194, 0x0194, 0x0194, 0x0194, 0x02a0, 0x02a0, 0x02a0, 0x02a0,
148 0x02A4, 0x02A4, 0x0198, 0x0198 };
149 u8 rtl9300_sds_lsb[] = { 0, 6, 12, 18, 0, 6, 12, 18, 0, 6, 0, 6};
150
151 /*
152 * Reset the SerDes by powering it off and set a new operations mode
153 * of the SerDes. 0x1f is off. Other modes are
154 * 0x02: SGMII 0x04: 1000BX_FIBER 0x05: FIBER100
155 * 0x06: QSGMII 0x09: RSGMII 0x0d: USXGMII
156 * 0x10: XSGMII 0x12: HISGMII 0x16: 2500Base_X
157 * 0x17: RXAUI_LITE 0x19: RXAUI_PLUS 0x1a: 10G Base-R
158 * 0x1b: 10GR1000BX_AUTO 0x1f: OFF
159 */
160 void rtl9300_sds_rst(int sds_num, u32 mode)
161 {
162 pr_info("%s %d\n", __func__, mode);
163 if (sds_num < 0 || sds_num > 11) {
164 pr_err("Wrong SerDes number: %d\n", sds_num);
165 return;
166 }
167
168 sw_w32_mask(0x1f << rtl9300_sds_lsb[sds_num], 0x1f << rtl9300_sds_lsb[sds_num],
169 rtl9300_sds_regs[sds_num]);
170 mdelay(10);
171
172 sw_w32_mask(0x1f << rtl9300_sds_lsb[sds_num], mode << rtl9300_sds_lsb[sds_num],
173 rtl9300_sds_regs[sds_num]);
174 mdelay(10);
175
176 pr_debug("%s: 194:%08x 198:%08x 2a0:%08x 2a4:%08x\n", __func__,
177 sw_r32(0x194), sw_r32(0x198), sw_r32(0x2a0), sw_r32(0x2a4));
178 }
179
180 void rtl9300_sds_set(int sds_num, u32 mode)
181 {
182 pr_info("%s %d\n", __func__, mode);
183 if (sds_num < 0 || sds_num > 11) {
184 pr_err("Wrong SerDes number: %d\n", sds_num);
185 return;
186 }
187
188 sw_w32_mask(0x1f << rtl9300_sds_lsb[sds_num], mode << rtl9300_sds_lsb[sds_num],
189 rtl9300_sds_regs[sds_num]);
190 mdelay(10);
191
192 pr_debug("%s: 194:%08x 198:%08x 2a0:%08x 2a4:%08x\n", __func__,
193 sw_r32(0x194), sw_r32(0x198), sw_r32(0x2a0), sw_r32(0x2a4));
194 }
195
196 u32 rtl9300_sds_mode_get(int sds_num)
197 {
198 u32 v;
199
200 if (sds_num < 0 || sds_num > 11) {
201 pr_err("Wrong SerDes number: %d\n", sds_num);
202 return 0;
203 }
204
205 v = sw_r32(rtl9300_sds_regs[sds_num]);
206 v >>= rtl9300_sds_lsb[sds_num];
207
208 return v & 0x1f;
209 }
210
211 /*
212 * On the RTL839x family of SoCs with inbuilt SerDes, these SerDes are accessed through
213 * a 2048 bit register that holds the contents of the PHY being simulated by the SoC.
214 */
215 int rtl839x_read_sds_phy(int phy_addr, int phy_reg)
216 {
217 int offset = 0;
218 int reg;
219 u32 val;
220
221 if (phy_addr == 49)
222 offset = 0x100;
223
224 /*
225 * For the RTL8393 internal SerDes, we simulate a PHY ID in registers 2/3
226 * which would otherwise read as 0.
227 */
228 if (soc_info.id == 0x8393) {
229 if (phy_reg == 2)
230 return 0x1c;
231 if (phy_reg == 3)
232 return 0x8393;
233 }
234
235 /*
236 * Register RTL839X_SDS12_13_XSG0 is 2048 bit broad, the MSB (bit 15) of the
237 * 0th PHY register is bit 1023 (in byte 0x80). Because PHY-registers are 16
238 * bit broad, we offset by reg << 1. In the SoC 2 registers are stored in
239 * one 32 bit register.
240 */
241 reg = (phy_reg << 1) & 0xfc;
242 val = sw_r32(RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
243
244 if (phy_reg & 1)
245 val = (val >> 16) & 0xffff;
246 else
247 val &= 0xffff;
248 return val;
249 }
250
251 /*
252 * On the RTL930x family of SoCs, the internal SerDes are accessed through an IO
253 * register which simulates commands to an internal MDIO bus.
254 */
255 int rtl930x_read_sds_phy(int phy_addr, int page, int phy_reg)
256 {
257 int i;
258 u32 cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 1;
259
260 sw_w32(cmd, RTL930X_SDS_INDACS_CMD);
261
262 for (i = 0; i < 100; i++) {
263 if (!(sw_r32(RTL930X_SDS_INDACS_CMD) & 0x1))
264 break;
265 mdelay(1);
266 }
267
268 if (i >= 100)
269 return -EIO;
270
271 return sw_r32(RTL930X_SDS_INDACS_DATA) & 0xffff;
272 }
273
274 int rtl930x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v)
275 {
276 int i;
277 u32 cmd;
278
279 sw_w32(v, RTL930X_SDS_INDACS_DATA);
280 cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 0x3;
281
282 for (i = 0; i < 100; i++) {
283 if (!(sw_r32(RTL930X_SDS_INDACS_CMD) & 0x1))
284 break;
285 mdelay(1);
286 }
287
288
289 if (i >= 100) {
290 pr_info("%s ERROR !!!!!!!!!!!!!!!!!!!!\n", __func__);
291 return -EIO;
292 }
293
294 return 0;
295 }
296
297 int rtl931x_read_sds_phy(int phy_addr, int page, int phy_reg)
298 {
299 int i;
300 u32 cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 1;
301
302 pr_debug("%s: phy_addr(SDS-ID) %d, phy_reg: %d\n", __func__, phy_addr, phy_reg);
303 sw_w32(cmd, RTL931X_SERDES_INDRT_ACCESS_CTRL);
304
305 for (i = 0; i < 100; i++) {
306 if (!(sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL) & 0x1))
307 break;
308 mdelay(1);
309 }
310
311 if (i >= 100)
312 return -EIO;
313
314 pr_debug("%s: returning %04x\n", __func__, sw_r32(RTL931X_SERDES_INDRT_DATA_CTRL) & 0xffff);
315 return sw_r32(RTL931X_SERDES_INDRT_DATA_CTRL) & 0xffff;
316 }
317
318 int rtl931x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v)
319 {
320 int i;
321 u32 cmd;
322
323 cmd = phy_addr << 2 | page << 7 | phy_reg << 13;
324 sw_w32(cmd, RTL931X_SERDES_INDRT_ACCESS_CTRL);
325
326 sw_w32(v, RTL931X_SERDES_INDRT_DATA_CTRL);
327
328 cmd = sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL) | 0x3;
329 sw_w32(cmd, RTL931X_SERDES_INDRT_ACCESS_CTRL);
330
331 for (i = 0; i < 100; i++) {
332 if (!(sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL) & 0x1))
333 break;
334 mdelay(1);
335 }
336
337 if (i >= 100)
338 return -EIO;
339
340 return 0;
341 }
342
343 /*
344 * On the RTL838x SoCs, the internal SerDes is accessed through direct access to
345 * standard PHY registers, where a 32 bit register holds a 16 bit word as found
346 * in a standard page 0 of a PHY
347 */
348 int rtl838x_read_sds_phy(int phy_addr, int phy_reg)
349 {
350 int offset = 0;
351 u32 val;
352
353 if (phy_addr == 26)
354 offset = 0x100;
355 val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;
356
357 return val;
358 }
359
360 int rtl839x_write_sds_phy(int phy_addr, int phy_reg, u16 v)
361 {
362 int offset = 0;
363 int reg;
364 u32 val;
365
366 if (phy_addr == 49)
367 offset = 0x100;
368
369 reg = (phy_reg << 1) & 0xfc;
370 val = v;
371 if (phy_reg & 1) {
372 val = val << 16;
373 sw_w32_mask(0xffff0000, val,
374 RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
375 } else {
376 sw_w32_mask(0xffff, val,
377 RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
378 }
379
380 return 0;
381 }
382
383 /* Read the link and speed status of the 2 internal SGMII/1000Base-X
384 * ports of the RTL838x SoCs
385 */
386 static int rtl8380_read_status(struct phy_device *phydev)
387 {
388 int err;
389
390 err = genphy_read_status(phydev);
391
392 if (phydev->link) {
393 phydev->speed = SPEED_1000;
394 phydev->duplex = DUPLEX_FULL;
395 }
396
397 return err;
398 }
399
400 /* Read the link and speed status of the 2 internal SGMII/1000Base-X
401 * ports of the RTL8393 SoC
402 */
403 static int rtl8393_read_status(struct phy_device *phydev)
404 {
405 int offset = 0;
406 int err;
407 int phy_addr = phydev->mdio.addr;
408 u32 v;
409
410 err = genphy_read_status(phydev);
411 if (phy_addr == 49)
412 offset = 0x100;
413
414 if (phydev->link) {
415 phydev->speed = SPEED_100;
416 /* Read SPD_RD_00 (bit 13) and SPD_RD_01 (bit 6) out of the internal
417 * PHY registers
418 */
419 v = sw_r32(RTL839X_SDS12_13_XSG0 + offset + 0x80);
420 if (!(v & (1 << 13)) && (v & (1 << 6)))
421 phydev->speed = SPEED_1000;
422 phydev->duplex = DUPLEX_FULL;
423 }
424
425 return err;
426 }
427
428 static int rtl8226_read_page(struct phy_device *phydev)
429 {
430 return __phy_read(phydev, RTL8XXX_PAGE_SELECT);
431 }
432
433 static int rtl8226_write_page(struct phy_device *phydev, int page)
434 {
435 return __phy_write(phydev, RTL8XXX_PAGE_SELECT, page);
436 }
437
438 static int rtl8226_read_status(struct phy_device *phydev)
439 {
440 int ret = 0, i;
441 u32 val;
442
443 // TODO: ret = genphy_read_status(phydev);
444 // if (ret < 0) {
445 // pr_info("%s: genphy_read_status failed\n", __func__);
446 // return ret;
447 // }
448
449 // Link status must be read twice
450 for (i = 0; i < 2; i++) {
451 val = phy_read_mmd(phydev, MMD_VEND2, 0xA402);
452 }
453 phydev->link = val & BIT(2) ? 1 : 0;
454 if (!phydev->link)
455 goto out;
456
457 // Read duplex status
458 val = phy_read_mmd(phydev, MMD_VEND2, 0xA434);
459 if (val < 0)
460 goto out;
461 phydev->duplex = !!(val & BIT(3));
462
463 // Read speed
464 val = phy_read_mmd(phydev, MMD_VEND2, 0xA434);
465 switch (val & 0x0630) {
466 case 0x0000:
467 phydev->speed = SPEED_10;
468 break;
469 case 0x0010:
470 phydev->speed = SPEED_100;
471 break;
472 case 0x0020:
473 phydev->speed = SPEED_1000;
474 break;
475 case 0x0200:
476 phydev->speed = SPEED_10000;
477 break;
478 case 0x0210:
479 phydev->speed = SPEED_2500;
480 break;
481 case 0x0220:
482 phydev->speed = SPEED_5000;
483 break;
484 default:
485 break;
486 }
487 out:
488 return ret;
489 }
490
491 static int rtl8226_advertise_aneg(struct phy_device *phydev)
492 {
493 int ret = 0;
494 u32 v;
495
496 pr_info("In %s\n", __func__);
497
498 v = phy_read_mmd(phydev, MMD_AN, 16);
499 if (v < 0)
500 goto out;
501
502 v |= BIT(5); // HD 10M
503 v |= BIT(6); // FD 10M
504 v |= BIT(7); // HD 100M
505 v |= BIT(8); // FD 100M
506
507 ret = phy_write_mmd(phydev, MMD_AN, 16, v);
508
509 // Allow 1GBit
510 v = phy_read_mmd(phydev, MMD_VEND2, 0xA412);
511 if (v < 0)
512 goto out;
513 v |= BIT(9); // FD 1000M
514
515 ret = phy_write_mmd(phydev, MMD_VEND2, 0xA412, v);
516 if (ret < 0)
517 goto out;
518
519 // Allow 2.5G
520 v = phy_read_mmd(phydev, MMD_AN, 32);
521 if (v < 0)
522 goto out;
523
524 v |= BIT(7);
525 ret = phy_write_mmd(phydev, MMD_AN, 32, v);
526
527 out:
528 return ret;
529 }
530
531 static int rtl8226_config_aneg(struct phy_device *phydev)
532 {
533 int ret = 0;
534 u32 v;
535
536 pr_debug("In %s\n", __func__);
537 if (phydev->autoneg == AUTONEG_ENABLE) {
538 ret = rtl8226_advertise_aneg(phydev);
539 if (ret)
540 goto out;
541 // AutoNegotiationEnable
542 v = phy_read_mmd(phydev, MMD_AN, 0);
543 if (v < 0)
544 goto out;
545
546 v |= BIT(12); // Enable AN
547 ret = phy_write_mmd(phydev, MMD_AN, 0, v);
548 if (ret < 0)
549 goto out;
550
551 // RestartAutoNegotiation
552 v = phy_read_mmd(phydev, MMD_VEND2, 0xA400);
553 if (v < 0)
554 goto out;
555 v |= BIT(9);
556
557 ret = phy_write_mmd(phydev, MMD_VEND2, 0xA400, v);
558 }
559
560 // TODO: ret = __genphy_config_aneg(phydev, ret);
561
562 out:
563 return ret;
564 }
565
566 static int rtl8226_get_eee(struct phy_device *phydev,
567 struct ethtool_eee *e)
568 {
569 u32 val;
570 int addr = phydev->mdio.addr;
571
572 pr_debug("In %s, port %d, was enabled: %d\n", __func__, addr, e->eee_enabled);
573
574 val = phy_read_mmd(phydev, MMD_AN, 60);
575 if (e->eee_enabled) {
576 e->eee_enabled = !!(val & BIT(1));
577 if (!e->eee_enabled) {
578 val = phy_read_mmd(phydev, MMD_AN, 62);
579 e->eee_enabled = !!(val & BIT(0));
580 }
581 }
582 pr_debug("%s: enabled: %d\n", __func__, e->eee_enabled);
583
584 return 0;
585 }
586
587 static int rtl8226_set_eee(struct phy_device *phydev, struct ethtool_eee *e)
588 {
589 int port = phydev->mdio.addr;
590 u64 poll_state;
591 bool an_enabled;
592 u32 val;
593
594 pr_info("In %s, port %d, enabled %d\n", __func__, port, e->eee_enabled);
595
596 poll_state = disable_polling(port);
597
598 // Remember aneg state
599 val = phy_read_mmd(phydev, MMD_AN, 0);
600 an_enabled = !!(val & BIT(12));
601
602 // Setup 100/1000MBit
603 val = phy_read_mmd(phydev, MMD_AN, 60);
604 if (e->eee_enabled)
605 val |= 0x6;
606 else
607 val &= 0x6;
608 phy_write_mmd(phydev, MMD_AN, 60, val);
609
610 // Setup 2.5GBit
611 val = phy_read_mmd(phydev, MMD_AN, 62);
612 if (e->eee_enabled)
613 val |= 0x1;
614 else
615 val &= 0x1;
616 phy_write_mmd(phydev, MMD_AN, 62, val);
617
618 // RestartAutoNegotiation
619 val = phy_read_mmd(phydev, MMD_VEND2, 0xA400);
620 val |= BIT(9);
621 phy_write_mmd(phydev, MMD_VEND2, 0xA400, val);
622
623 resume_polling(poll_state);
624
625 return 0;
626 }
627
628 static struct fw_header *rtl838x_request_fw(struct phy_device *phydev,
629 const struct firmware *fw,
630 const char *name)
631 {
632 struct device *dev = &phydev->mdio.dev;
633 int err;
634 struct fw_header *h;
635 uint32_t checksum, my_checksum;
636
637 err = request_firmware(&fw, name, dev);
638 if (err < 0)
639 goto out;
640
641 if (fw->size < sizeof(struct fw_header)) {
642 pr_err("Firmware size too small.\n");
643 err = -EINVAL;
644 goto out;
645 }
646
647 h = (struct fw_header *) fw->data;
648 pr_info("Firmware loaded. Size %d, magic: %08x\n", fw->size, h->magic);
649
650 if (h->magic != 0x83808380) {
651 pr_err("Wrong firmware file: MAGIC mismatch.\n");
652 goto out;
653 }
654
655 checksum = h->checksum;
656 h->checksum = 0;
657 my_checksum = ~crc32(0xFFFFFFFFU, fw->data, fw->size);
658 if (checksum != my_checksum) {
659 pr_err("Firmware checksum mismatch.\n");
660 err = -EINVAL;
661 goto out;
662 }
663 h->checksum = checksum;
664
665 return h;
666 out:
667 dev_err(dev, "Unable to load firmware %s (%d)\n", name, err);
668 return NULL;
669 }
670
671 static void rtl821x_phy_setup_package_broadcast(struct phy_device *phydev, bool enable)
672 {
673 int mac = phydev->mdio.addr;
674
675 /* select main page 0 */
676 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
677 /* write to 0x8 to register 0x1d on main page 0 */
678 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
679 /* select page 0x266 */
680 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PORT);
681 /* set phy id and target broadcast bitmap in register 0x16 on page 0x266 */
682 phy_write_paged(phydev, RTL83XX_PAGE_RAW, 0x16, (enable?0xff00:0x00) | mac);
683 /* return to main page 0 */
684 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
685 /* write to 0x0 to register 0x1d on main page 0 */
686 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
687 mdelay(1);
688 }
689
690 static int rtl8390_configure_generic(struct phy_device *phydev)
691 {
692 int mac = phydev->mdio.addr;
693 u32 val, phy_id;
694
695 val = phy_read(phydev, 2);
696 phy_id = val << 16;
697 val = phy_read(phydev, 3);
698 phy_id |= val;
699 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
700
701 /* Read internal PHY ID */
702 phy_write_paged(phydev, 31, 27, 0x0002);
703 val = phy_read_paged(phydev, 31, 28);
704
705 /* Internal RTL8218B, version 2 */
706 phydev_info(phydev, "Detected unknown %x\n", val);
707 return 0;
708 }
709
710 static int rtl8380_configure_int_rtl8218b(struct phy_device *phydev)
711 {
712 u32 val, phy_id;
713 int i, p, ipd_flag;
714 int mac = phydev->mdio.addr;
715 struct fw_header *h;
716 u32 *rtl838x_6275B_intPhy_perport;
717 u32 *rtl8218b_6276B_hwEsd_perport;
718
719 val = phy_read(phydev, 2);
720 phy_id = val << 16;
721 val = phy_read(phydev, 3);
722 phy_id |= val;
723 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
724
725 /* Read internal PHY ID */
726 phy_write_paged(phydev, 31, 27, 0x0002);
727 val = phy_read_paged(phydev, 31, 28);
728 if (val != 0x6275) {
729 phydev_err(phydev, "Expected internal RTL8218B, found PHY-ID %x\n", val);
730 return -1;
731 }
732
733 /* Internal RTL8218B, version 2 */
734 phydev_info(phydev, "Detected internal RTL8218B\n");
735
736 h = rtl838x_request_fw(phydev, &rtl838x_8380_fw, FIRMWARE_838X_8380_1);
737 if (!h)
738 return -1;
739
740 if (h->phy != 0x83800000) {
741 phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n");
742 return -1;
743 }
744
745 rtl838x_6275B_intPhy_perport = (void *)h + sizeof(struct fw_header)
746 + h->parts[8].start;
747
748 rtl8218b_6276B_hwEsd_perport = (void *)h + sizeof(struct fw_header)
749 + h->parts[9].start;
750
751 if (sw_r32(RTL838X_DMY_REG31) == 0x1)
752 ipd_flag = 1;
753
754 val = phy_read(phydev, 0);
755 if (val & BIT(11))
756 rtl8380_int_phy_on_off(phydev, true);
757 else
758 rtl8380_phy_reset(phydev);
759 msleep(100);
760
761 /* Ready PHY for patch */
762 for (p = 0; p < 8; p++) {
763 phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PATCH);
764 phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW, 0x10, 0x0010);
765 }
766 msleep(500);
767 for (p = 0; p < 8; p++) {
768 for (i = 0; i < 100 ; i++) {
769 val = phy_package_port_read_paged(phydev, p, RTL821X_PAGE_STATE, 0x10);
770 if (val & 0x40)
771 break;
772 }
773 if (i >= 100) {
774 phydev_err(phydev,
775 "ERROR: Port %d not ready for patch.\n",
776 mac + p);
777 return -1;
778 }
779 }
780 for (p = 0; p < 8; p++) {
781 i = 0;
782 while (rtl838x_6275B_intPhy_perport[i * 2]) {
783 phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW,
784 rtl838x_6275B_intPhy_perport[i * 2],
785 rtl838x_6275B_intPhy_perport[i * 2 + 1]);
786 i++;
787 }
788 i = 0;
789 while (rtl8218b_6276B_hwEsd_perport[i * 2]) {
790 phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW,
791 rtl8218b_6276B_hwEsd_perport[i * 2],
792 rtl8218b_6276B_hwEsd_perport[i * 2 + 1]);
793 i++;
794 }
795 }
796 return 0;
797 }
798
799 static int rtl8380_configure_ext_rtl8218b(struct phy_device *phydev)
800 {
801 u32 val, ipd, phy_id;
802 int i, l;
803 int mac = phydev->mdio.addr;
804 struct fw_header *h;
805 u32 *rtl8380_rtl8218b_perchip;
806 u32 *rtl8218B_6276B_rtl8380_perport;
807 u32 *rtl8380_rtl8218b_perport;
808
809 if (soc_info.family == RTL8380_FAMILY_ID && mac != 0 && mac != 16) {
810 phydev_err(phydev, "External RTL8218B must have PHY-IDs 0 or 16!\n");
811 return -1;
812 }
813 val = phy_read(phydev, 2);
814 phy_id = val << 16;
815 val = phy_read(phydev, 3);
816 phy_id |= val;
817 pr_info("Phy on MAC %d: %x\n", mac, phy_id);
818
819 /* Read internal PHY ID */
820 phy_write_paged(phydev, 31, 27, 0x0002);
821 val = phy_read_paged(phydev, 31, 28);
822 if (val != 0x6276) {
823 phydev_err(phydev, "Expected external RTL8218B, found PHY-ID %x\n", val);
824 return -1;
825 }
826 phydev_info(phydev, "Detected external RTL8218B\n");
827
828 h = rtl838x_request_fw(phydev, &rtl838x_8218b_fw, FIRMWARE_838X_8218b_1);
829 if (!h)
830 return -1;
831
832 if (h->phy != 0x8218b000) {
833 phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n");
834 return -1;
835 }
836
837 rtl8380_rtl8218b_perchip = (void *)h + sizeof(struct fw_header)
838 + h->parts[0].start;
839
840 rtl8218B_6276B_rtl8380_perport = (void *)h + sizeof(struct fw_header)
841 + h->parts[1].start;
842
843 rtl8380_rtl8218b_perport = (void *)h + sizeof(struct fw_header)
844 + h->parts[2].start;
845
846 val = phy_read(phydev, 0);
847 if (val & (1 << 11))
848 rtl8380_int_phy_on_off(phydev, true);
849 else
850 rtl8380_phy_reset(phydev);
851
852 msleep(100);
853
854 /* Get Chip revision */
855 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
856 phy_write_paged(phydev, RTL83XX_PAGE_RAW, 0x1b, 0x4);
857 val = phy_read_paged(phydev, RTL83XX_PAGE_RAW, 0x1c);
858
859 phydev_info(phydev, "Detected chip revision %04x\n", val);
860
861 i = 0;
862 while (rtl8380_rtl8218b_perchip[i * 3]
863 && rtl8380_rtl8218b_perchip[i * 3 + 1]) {
864 phy_package_port_write_paged(phydev, rtl8380_rtl8218b_perchip[i * 3],
865 RTL83XX_PAGE_RAW, rtl8380_rtl8218b_perchip[i * 3 + 1],
866 rtl8380_rtl8218b_perchip[i * 3 + 2]);
867 i++;
868 }
869
870 /* Enable PHY */
871 for (i = 0; i < 8; i++) {
872 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
873 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x00, 0x1140);
874 }
875 mdelay(100);
876
877 /* Request patch */
878 for (i = 0; i < 8; i++) {
879 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PATCH);
880 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x10, 0x0010);
881 }
882
883 mdelay(300);
884
885 /* Verify patch readiness */
886 for (i = 0; i < 8; i++) {
887 for (l = 0; l < 100; l++) {
888 val = phy_package_port_read_paged(phydev, i, RTL821X_PAGE_STATE, 0x10);
889 if (val & 0x40)
890 break;
891 }
892 if (l >= 100) {
893 phydev_err(phydev, "Could not patch PHY\n");
894 return -1;
895 }
896 }
897
898 /* Use Broadcast ID method for patching */
899 rtl821x_phy_setup_package_broadcast(phydev, true);
900
901 phy_write_paged(phydev, RTL83XX_PAGE_RAW, 30, 8);
902 phy_write_paged(phydev, 0x26e, 17, 0xb);
903 phy_write_paged(phydev, 0x26e, 16, 0x2);
904 mdelay(1);
905 ipd = phy_read_paged(phydev, 0x26e, 19);
906 phy_write_paged(phydev, 0, 30, 0);
907 ipd = (ipd >> 4) & 0xf; /* unused ? */
908
909 i = 0;
910 while (rtl8218B_6276B_rtl8380_perport[i * 2]) {
911 phy_write_paged(phydev, RTL83XX_PAGE_RAW, rtl8218B_6276B_rtl8380_perport[i * 2],
912 rtl8218B_6276B_rtl8380_perport[i * 2 + 1]);
913 i++;
914 }
915
916 /*Disable broadcast ID*/
917 rtl821x_phy_setup_package_broadcast(phydev, false);
918
919 return 0;
920 }
921
922 static int rtl8218b_ext_match_phy_device(struct phy_device *phydev)
923 {
924 int addr = phydev->mdio.addr;
925
926 /* Both the RTL8214FC and the external RTL8218B have the same
927 * PHY ID. On the RTL838x, the RTL8218B can only be attached_dev
928 * at PHY IDs 0-7, while the RTL8214FC must be attached via
929 * the pair of SGMII/1000Base-X with higher PHY-IDs
930 */
931 if (soc_info.family == RTL8380_FAMILY_ID)
932 return phydev->phy_id == PHY_ID_RTL8218B_E && addr < 8;
933 else
934 return phydev->phy_id == PHY_ID_RTL8218B_E;
935 }
936
937 static void rtl8380_rtl8214fc_media_set(struct phy_device *phydev, bool set_fibre)
938 {
939 int mac = phydev->mdio.addr;
940
941 static int reg[] = {16, 19, 20, 21};
942 int val, media, power;
943
944 pr_info("%s: port %d, set_fibre: %d\n", __func__, mac, set_fibre);
945 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
946 val = phy_package_read_paged(phydev, RTL821X_PAGE_PORT, reg[mac % 4]);
947
948 media = (val >> 10) & 0x3;
949 pr_info("Current media %x\n", media);
950 if (media & 0x2) {
951 pr_info("Powering off COPPER\n");
952 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
953 /* Ensure power is off */
954 power = phy_read_paged(phydev, RTL821X_PAGE_POWER, 0x10);
955 if (!(power & (1 << 11)))
956 phy_write_paged(phydev, RTL821X_PAGE_POWER, 0x10, power | (1 << 11));
957 } else {
958 pr_info("Powering off FIBRE\n");
959 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_FIBRE);
960 /* Ensure power is off */
961 power = phy_read_paged(phydev, RTL821X_PAGE_POWER, 0x10);
962 if (!(power & (1 << 11)))
963 phy_write_paged(phydev, RTL821X_PAGE_POWER, 0x10, power | (1 << 11));
964 }
965 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
966
967 if (set_fibre) {
968 val |= 1 << 10;
969 val &= ~(1 << 11);
970 } else {
971 val |= 1 << 10;
972 val |= 1 << 11;
973 }
974 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
975 phy_package_write_paged(phydev, RTL821X_PAGE_PORT, reg[mac % 4], val);
976 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
977
978 if (set_fibre) {
979 pr_info("Powering on FIBRE\n");
980 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_FIBRE);
981 /* Ensure power is off */
982 power = phy_read_paged(phydev, RTL821X_PAGE_POWER, 0x10);
983 if (power & (1 << 11))
984 phy_write_paged(phydev, RTL821X_PAGE_POWER, 0x10, power & ~(1 << 11));
985 } else {
986 pr_info("Powering on COPPER\n");
987 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
988 /* Ensure power is off */
989 power = phy_read_paged(phydev, RTL821X_PAGE_POWER, 0x10);
990 if (power & (1 << 11))
991 phy_write_paged(phydev, RTL821X_PAGE_POWER, 0x10, power & ~(1 << 11));
992 }
993 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
994 }
995
996 static bool rtl8380_rtl8214fc_media_is_fibre(struct phy_device *phydev)
997 {
998 int mac = phydev->mdio.addr;
999
1000 static int reg[] = {16, 19, 20, 21};
1001 u32 val;
1002
1003 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
1004 val = phy_package_read_paged(phydev, RTL821X_PAGE_PORT, reg[mac % 4]);
1005 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1006 if (val & (1 << 11))
1007 return false;
1008 return true;
1009 }
1010
1011 static int rtl8214fc_set_port(struct phy_device *phydev, int port)
1012 {
1013 bool is_fibre = (port == PORT_FIBRE ? true : false);
1014 int addr = phydev->mdio.addr;
1015
1016 pr_debug("%s port %d to %d\n", __func__, addr, port);
1017
1018 rtl8380_rtl8214fc_media_set(phydev, is_fibre);
1019 return 0;
1020 }
1021
1022 static int rtl8214fc_get_port(struct phy_device *phydev)
1023 {
1024 int addr = phydev->mdio.addr;
1025
1026 pr_debug("%s: port %d\n", __func__, addr);
1027 if (rtl8380_rtl8214fc_media_is_fibre(phydev))
1028 return PORT_FIBRE;
1029 return PORT_MII;
1030 }
1031
1032 /*
1033 * Enable EEE on the RTL8218B PHYs
1034 * The method used is not the preferred way (which would be based on the MAC-EEE state,
1035 * but the only way that works since the kernel first enables EEE in the MAC
1036 * and then sets up the PHY. The MAC-based approach would require the oppsite.
1037 */
1038 void rtl8218d_eee_set(struct phy_device *phydev, bool enable)
1039 {
1040 u32 val;
1041 bool an_enabled;
1042
1043 pr_debug("In %s %d, enable %d\n", __func__, phydev->mdio.addr, enable);
1044 /* Set GPHY page to copper */
1045 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1046
1047 val = phy_read(phydev, 0);
1048 an_enabled = val & BIT(12);
1049
1050 /* Enable 100M (bit 1) / 1000M (bit 2) EEE */
1051 val = phy_read_mmd(phydev, 7, 60);
1052 val |= BIT(2) | BIT(1);
1053 phy_write_mmd(phydev, 7, 60, enable ? 0x6 : 0);
1054
1055 /* 500M EEE ability */
1056 val = phy_read_paged(phydev, RTL821X_PAGE_GPHY, 20);
1057 if (enable)
1058 val |= BIT(7);
1059 else
1060 val &= ~BIT(7);
1061 phy_write_paged(phydev, RTL821X_PAGE_GPHY, 20, val);
1062
1063 /* Restart AN if enabled */
1064 if (an_enabled) {
1065 val = phy_read(phydev, 0);
1066 val |= BIT(9);
1067 phy_write(phydev, 0, val);
1068 }
1069
1070 /* GPHY page back to auto*/
1071 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1072 }
1073
1074 static int rtl8218b_get_eee(struct phy_device *phydev,
1075 struct ethtool_eee *e)
1076 {
1077 u32 val;
1078 int addr = phydev->mdio.addr;
1079
1080 pr_debug("In %s, port %d, was enabled: %d\n", __func__, addr, e->eee_enabled);
1081
1082 /* Set GPHY page to copper */
1083 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1084
1085 val = phy_read_paged(phydev, 7, 60);
1086 if (e->eee_enabled) {
1087 // Verify vs MAC-based EEE
1088 e->eee_enabled = !!(val & BIT(7));
1089 if (!e->eee_enabled) {
1090 val = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25);
1091 e->eee_enabled = !!(val & BIT(4));
1092 }
1093 }
1094 pr_debug("%s: enabled: %d\n", __func__, e->eee_enabled);
1095
1096 /* GPHY page to auto */
1097 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1098
1099 return 0;
1100 }
1101
1102 static int rtl8218d_get_eee(struct phy_device *phydev,
1103 struct ethtool_eee *e)
1104 {
1105 u32 val;
1106 int addr = phydev->mdio.addr;
1107
1108 pr_debug("In %s, port %d, was enabled: %d\n", __func__, addr, e->eee_enabled);
1109
1110 /* Set GPHY page to copper */
1111 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1112
1113 val = phy_read_paged(phydev, 7, 60);
1114 if (e->eee_enabled)
1115 e->eee_enabled = !!(val & BIT(7));
1116 pr_debug("%s: enabled: %d\n", __func__, e->eee_enabled);
1117
1118 /* GPHY page to auto */
1119 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1120
1121 return 0;
1122 }
1123
1124 static int rtl8214fc_set_eee(struct phy_device *phydev,
1125 struct ethtool_eee *e)
1126 {
1127 u32 poll_state;
1128 int port = phydev->mdio.addr;
1129 bool an_enabled;
1130 u32 val;
1131
1132 pr_debug("In %s port %d, enabled %d\n", __func__, port, e->eee_enabled);
1133
1134 if (rtl8380_rtl8214fc_media_is_fibre(phydev)) {
1135 netdev_err(phydev->attached_dev, "Port %d configured for FIBRE", port);
1136 return -ENOTSUPP;
1137 }
1138
1139 poll_state = disable_polling(port);
1140
1141 /* Set GPHY page to copper */
1142 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1143
1144 // Get auto-negotiation status
1145 val = phy_read(phydev, 0);
1146 an_enabled = val & BIT(12);
1147
1148 pr_info("%s: aneg: %d\n", __func__, an_enabled);
1149 val = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25);
1150 val &= ~BIT(5); // Use MAC-based EEE
1151 phy_write_paged(phydev, RTL821X_PAGE_MAC, 25, val);
1152
1153 /* Enable 100M (bit 1) / 1000M (bit 2) EEE */
1154 phy_write_paged(phydev, 7, 60, e->eee_enabled ? 0x6 : 0);
1155
1156 /* 500M EEE ability */
1157 val = phy_read_paged(phydev, RTL821X_PAGE_GPHY, 20);
1158 if (e->eee_enabled)
1159 val |= BIT(7);
1160 else
1161 val &= ~BIT(7);
1162
1163 phy_write_paged(phydev, RTL821X_PAGE_GPHY, 20, val);
1164
1165 /* Restart AN if enabled */
1166 if (an_enabled) {
1167 pr_info("%s: doing aneg\n", __func__);
1168 val = phy_read(phydev, 0);
1169 val |= BIT(9);
1170 phy_write(phydev, 0, val);
1171 }
1172
1173 /* GPHY page back to auto*/
1174 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1175
1176 resume_polling(poll_state);
1177
1178 return 0;
1179 }
1180
1181 static int rtl8214fc_get_eee(struct phy_device *phydev,
1182 struct ethtool_eee *e)
1183 {
1184 int addr = phydev->mdio.addr;
1185
1186 pr_debug("In %s port %d, enabled %d\n", __func__, addr, e->eee_enabled);
1187 if (rtl8380_rtl8214fc_media_is_fibre(phydev)) {
1188 netdev_err(phydev->attached_dev, "Port %d configured for FIBRE", addr);
1189 return -ENOTSUPP;
1190 }
1191
1192 return rtl8218b_get_eee(phydev, e);
1193 }
1194
1195 static int rtl8218b_set_eee(struct phy_device *phydev, struct ethtool_eee *e)
1196 {
1197 int port = phydev->mdio.addr;
1198 u64 poll_state;
1199 u32 val;
1200 bool an_enabled;
1201
1202 pr_info("In %s, port %d, enabled %d\n", __func__, port, e->eee_enabled);
1203
1204 poll_state = disable_polling(port);
1205
1206 /* Set GPHY page to copper */
1207 phy_write(phydev, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1208 val = phy_read(phydev, 0);
1209 an_enabled = val & BIT(12);
1210
1211 if (e->eee_enabled) {
1212 /* 100/1000M EEE Capability */
1213 phy_write(phydev, 13, 0x0007);
1214 phy_write(phydev, 14, 0x003C);
1215 phy_write(phydev, 13, 0x4007);
1216 phy_write(phydev, 14, 0x0006);
1217
1218 val = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25);
1219 val |= BIT(4);
1220 phy_write_paged(phydev, RTL821X_PAGE_MAC, 25, val);
1221 } else {
1222 /* 100/1000M EEE Capability */
1223 phy_write(phydev, 13, 0x0007);
1224 phy_write(phydev, 14, 0x003C);
1225 phy_write(phydev, 13, 0x0007);
1226 phy_write(phydev, 14, 0x0000);
1227
1228 val = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25);
1229 val &= ~BIT(4);
1230 phy_write_paged(phydev, RTL821X_PAGE_MAC, 25, val);
1231 }
1232
1233 /* Restart AN if enabled */
1234 if (an_enabled) {
1235 val = phy_read(phydev, 0);
1236 val |= BIT(9);
1237 phy_write(phydev, 0, val);
1238 }
1239
1240 /* GPHY page back to auto*/
1241 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1242
1243 pr_info("%s done\n", __func__);
1244 resume_polling(poll_state);
1245
1246 return 0;
1247 }
1248
1249 static int rtl8218d_set_eee(struct phy_device *phydev, struct ethtool_eee *e)
1250 {
1251 int addr = phydev->mdio.addr;
1252 u64 poll_state;
1253
1254 pr_info("In %s, port %d, enabled %d\n", __func__, addr, e->eee_enabled);
1255
1256 poll_state = disable_polling(addr);
1257
1258 rtl8218d_eee_set(phydev, (bool) e->eee_enabled);
1259
1260 resume_polling(poll_state);
1261
1262 return 0;
1263 }
1264
1265 static int rtl8214c_match_phy_device(struct phy_device *phydev)
1266 {
1267 return phydev->phy_id == PHY_ID_RTL8214C;
1268 }
1269
1270 static int rtl8380_configure_rtl8214c(struct phy_device *phydev)
1271 {
1272 u32 phy_id, val;
1273 int mac = phydev->mdio.addr;
1274
1275 val = phy_read(phydev, 2);
1276 phy_id = val << 16;
1277 val = phy_read(phydev, 3);
1278 phy_id |= val;
1279 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
1280
1281 phydev_info(phydev, "Detected external RTL8214C\n");
1282
1283 /* GPHY auto conf */
1284 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1285 return 0;
1286 }
1287
1288 static int rtl8380_configure_rtl8214fc(struct phy_device *phydev)
1289 {
1290 u32 phy_id, val, page = 0;
1291 int i, l;
1292 int mac = phydev->mdio.addr;
1293 struct fw_header *h;
1294 u32 *rtl8380_rtl8214fc_perchip;
1295 u32 *rtl8380_rtl8214fc_perport;
1296
1297 val = phy_read(phydev, 2);
1298 phy_id = val << 16;
1299 val = phy_read(phydev, 3);
1300 phy_id |= val;
1301 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
1302
1303 /* Read internal PHY id */
1304 phy_write_paged(phydev, 0, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1305 phy_write_paged(phydev, 0x1f, 0x1b, 0x0002);
1306 val = phy_read_paged(phydev, 0x1f, 0x1c);
1307 if (val != 0x6276) {
1308 phydev_err(phydev, "Expected external RTL8214FC, found PHY-ID %x\n", val);
1309 return -1;
1310 }
1311 phydev_info(phydev, "Detected external RTL8214FC\n");
1312
1313 h = rtl838x_request_fw(phydev, &rtl838x_8214fc_fw, FIRMWARE_838X_8214FC_1);
1314 if (!h)
1315 return -1;
1316
1317 if (h->phy != 0x8214fc00) {
1318 phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n");
1319 return -1;
1320 }
1321
1322 rtl8380_rtl8214fc_perchip = (void *)h + sizeof(struct fw_header)
1323 + h->parts[0].start;
1324
1325 rtl8380_rtl8214fc_perport = (void *)h + sizeof(struct fw_header)
1326 + h->parts[1].start;
1327
1328 /* detect phy version */
1329 phy_write_paged(phydev, RTL83XX_PAGE_RAW, 27, 0x0004);
1330 val = phy_read_paged(phydev, RTL83XX_PAGE_RAW, 28);
1331
1332 val = phy_read(phydev, 16);
1333 if (val & (1 << 11))
1334 rtl8380_rtl8214fc_on_off(phydev, true);
1335 else
1336 rtl8380_phy_reset(phydev);
1337
1338 msleep(100);
1339 phy_write_paged(phydev, 0, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1340
1341 i = 0;
1342 while (rtl8380_rtl8214fc_perchip[i * 3]
1343 && rtl8380_rtl8214fc_perchip[i * 3 + 1]) {
1344 if (rtl8380_rtl8214fc_perchip[i * 3 + 1] == 0x1f)
1345 page = rtl8380_rtl8214fc_perchip[i * 3 + 2];
1346 if (rtl8380_rtl8214fc_perchip[i * 3 + 1] == 0x13 && page == 0x260) {
1347 val = phy_read_paged(phydev, 0x260, 13);
1348 val = (val & 0x1f00) | (rtl8380_rtl8214fc_perchip[i * 3 + 2]
1349 & 0xe0ff);
1350 phy_write_paged(phydev, RTL83XX_PAGE_RAW,
1351 rtl8380_rtl8214fc_perchip[i * 3 + 1], val);
1352 } else {
1353 phy_write_paged(phydev, RTL83XX_PAGE_RAW,
1354 rtl8380_rtl8214fc_perchip[i * 3 + 1],
1355 rtl8380_rtl8214fc_perchip[i * 3 + 2]);
1356 }
1357 i++;
1358 }
1359
1360 /* Force copper medium */
1361 for (i = 0; i < 4; i++) {
1362 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
1363 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1364 }
1365
1366 /* Enable PHY */
1367 for (i = 0; i < 4; i++) {
1368 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
1369 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x00, 0x1140);
1370 }
1371 mdelay(100);
1372
1373 /* Disable Autosensing */
1374 for (i = 0; i < 4; i++) {
1375 for (l = 0; l < 100; l++) {
1376 val = phy_package_port_read_paged(phydev, i, RTL821X_PAGE_GPHY, 0x10);
1377 if ((val & 0x7) >= 3)
1378 break;
1379 }
1380 if (l >= 100) {
1381 phydev_err(phydev, "Could not disable autosensing\n");
1382 return -1;
1383 }
1384 }
1385
1386 /* Request patch */
1387 for (i = 0; i < 4; i++) {
1388 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PATCH);
1389 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x10, 0x0010);
1390 }
1391 mdelay(300);
1392
1393 /* Verify patch readiness */
1394 for (i = 0; i < 4; i++) {
1395 for (l = 0; l < 100; l++) {
1396 val = phy_package_port_read_paged(phydev, i, RTL821X_PAGE_STATE, 0x10);
1397 if (val & 0x40)
1398 break;
1399 }
1400 if (l >= 100) {
1401 phydev_err(phydev, "Could not patch PHY\n");
1402 return -1;
1403 }
1404 }
1405 /* Use Broadcast ID method for patching */
1406 rtl821x_phy_setup_package_broadcast(phydev, true);
1407
1408 i = 0;
1409 while (rtl8380_rtl8214fc_perport[i * 2]) {
1410 phy_write_paged(phydev, RTL83XX_PAGE_RAW, rtl8380_rtl8214fc_perport[i * 2],
1411 rtl8380_rtl8214fc_perport[i * 2 + 1]);
1412 i++;
1413 }
1414
1415 /*Disable broadcast ID*/
1416 rtl821x_phy_setup_package_broadcast(phydev, false);
1417
1418 /* Auto medium selection */
1419 for (i = 0; i < 4; i++) {
1420 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
1421 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1422 }
1423
1424 return 0;
1425 }
1426
1427 static int rtl8214fc_match_phy_device(struct phy_device *phydev)
1428 {
1429 int addr = phydev->mdio.addr;
1430
1431 return phydev->phy_id == PHY_ID_RTL8214FC && addr >= 24;
1432 }
1433
1434 static int rtl8380_configure_serdes(struct phy_device *phydev)
1435 {
1436 u32 v;
1437 u32 sds_conf_value;
1438 int i;
1439 struct fw_header *h;
1440 u32 *rtl8380_sds_take_reset;
1441 u32 *rtl8380_sds_common;
1442 u32 *rtl8380_sds01_qsgmii_6275b;
1443 u32 *rtl8380_sds23_qsgmii_6275b;
1444 u32 *rtl8380_sds4_fiber_6275b;
1445 u32 *rtl8380_sds5_fiber_6275b;
1446 u32 *rtl8380_sds_reset;
1447 u32 *rtl8380_sds_release_reset;
1448
1449 phydev_info(phydev, "Detected internal RTL8380 SERDES\n");
1450
1451 h = rtl838x_request_fw(phydev, &rtl838x_8218b_fw, FIRMWARE_838X_8380_1);
1452 if (!h)
1453 return -1;
1454
1455 if (h->magic != 0x83808380) {
1456 phydev_err(phydev, "Wrong firmware file: magic number mismatch.\n");
1457 return -1;
1458 }
1459
1460 rtl8380_sds_take_reset = (void *)h + sizeof(struct fw_header)
1461 + h->parts[0].start;
1462
1463 rtl8380_sds_common = (void *)h + sizeof(struct fw_header)
1464 + h->parts[1].start;
1465
1466 rtl8380_sds01_qsgmii_6275b = (void *)h + sizeof(struct fw_header)
1467 + h->parts[2].start;
1468
1469 rtl8380_sds23_qsgmii_6275b = (void *)h + sizeof(struct fw_header)
1470 + h->parts[3].start;
1471
1472 rtl8380_sds4_fiber_6275b = (void *)h + sizeof(struct fw_header)
1473 + h->parts[4].start;
1474
1475 rtl8380_sds5_fiber_6275b = (void *)h + sizeof(struct fw_header)
1476 + h->parts[5].start;
1477
1478 rtl8380_sds_reset = (void *)h + sizeof(struct fw_header)
1479 + h->parts[6].start;
1480
1481 rtl8380_sds_release_reset = (void *)h + sizeof(struct fw_header)
1482 + h->parts[7].start;
1483
1484 /* Back up serdes power off value */
1485 sds_conf_value = sw_r32(RTL838X_SDS_CFG_REG);
1486 pr_info("SDS power down value: %x\n", sds_conf_value);
1487
1488 /* take serdes into reset */
1489 i = 0;
1490 while (rtl8380_sds_take_reset[2 * i]) {
1491 sw_w32(rtl8380_sds_take_reset[2 * i + 1], rtl8380_sds_take_reset[2 * i]);
1492 i++;
1493 udelay(1000);
1494 }
1495
1496 /* apply common serdes patch */
1497 i = 0;
1498 while (rtl8380_sds_common[2 * i]) {
1499 sw_w32(rtl8380_sds_common[2 * i + 1], rtl8380_sds_common[2 * i]);
1500 i++;
1501 udelay(1000);
1502 }
1503
1504 /* internal R/W enable */
1505 sw_w32(3, RTL838X_INT_RW_CTRL);
1506
1507 /* SerDes ports 4 and 5 are FIBRE ports */
1508 sw_w32_mask(0x7 | 0x38, 1 | (1 << 3), RTL838X_INT_MODE_CTRL);
1509
1510 /* SerDes module settings, SerDes 0-3 are QSGMII */
1511 v = 0x6 << 25 | 0x6 << 20 | 0x6 << 15 | 0x6 << 10;
1512 /* SerDes 4 and 5 are 1000BX FIBRE */
1513 v |= 0x4 << 5 | 0x4;
1514 sw_w32(v, RTL838X_SDS_MODE_SEL);
1515
1516 pr_info("PLL control register: %x\n", sw_r32(RTL838X_PLL_CML_CTRL));
1517 sw_w32_mask(0xfffffff0, 0xaaaaaaaf & 0xf, RTL838X_PLL_CML_CTRL);
1518 i = 0;
1519 while (rtl8380_sds01_qsgmii_6275b[2 * i]) {
1520 sw_w32(rtl8380_sds01_qsgmii_6275b[2 * i + 1],
1521 rtl8380_sds01_qsgmii_6275b[2 * i]);
1522 i++;
1523 }
1524
1525 i = 0;
1526 while (rtl8380_sds23_qsgmii_6275b[2 * i]) {
1527 sw_w32(rtl8380_sds23_qsgmii_6275b[2 * i + 1], rtl8380_sds23_qsgmii_6275b[2 * i]);
1528 i++;
1529 }
1530
1531 i = 0;
1532 while (rtl8380_sds4_fiber_6275b[2 * i]) {
1533 sw_w32(rtl8380_sds4_fiber_6275b[2 * i + 1], rtl8380_sds4_fiber_6275b[2 * i]);
1534 i++;
1535 }
1536
1537 i = 0;
1538 while (rtl8380_sds5_fiber_6275b[2 * i]) {
1539 sw_w32(rtl8380_sds5_fiber_6275b[2 * i + 1], rtl8380_sds5_fiber_6275b[2 * i]);
1540 i++;
1541 }
1542
1543 i = 0;
1544 while (rtl8380_sds_reset[2 * i]) {
1545 sw_w32(rtl8380_sds_reset[2 * i + 1], rtl8380_sds_reset[2 * i]);
1546 i++;
1547 }
1548
1549 i = 0;
1550 while (rtl8380_sds_release_reset[2 * i]) {
1551 sw_w32(rtl8380_sds_release_reset[2 * i + 1], rtl8380_sds_release_reset[2 * i]);
1552 i++;
1553 }
1554
1555 pr_info("SDS power down value now: %x\n", sw_r32(RTL838X_SDS_CFG_REG));
1556 sw_w32(sds_conf_value, RTL838X_SDS_CFG_REG);
1557
1558 pr_info("Configuration of SERDES done\n");
1559 return 0;
1560 }
1561
1562 static int rtl8390_configure_serdes(struct phy_device *phydev)
1563 {
1564 phydev_info(phydev, "Detected internal RTL8390 SERDES\n");
1565
1566 /* In autoneg state, force link, set SR4_CFG_EN_LINK_FIB1G */
1567 sw_w32_mask(0, 1 << 18, RTL839X_SDS12_13_XSG0 + 0x0a);
1568
1569 /* Disable EEE: Clear FRE16_EEE_RSG_FIB1G, FRE16_EEE_STD_FIB1G,
1570 * FRE16_C1_PWRSAV_EN_FIB1G, FRE16_C2_PWRSAV_EN_FIB1G
1571 * and FRE16_EEE_QUIET_FIB1G
1572 */
1573 sw_w32_mask(0x1f << 10, 0, RTL839X_SDS12_13_XSG0 + 0xe0);
1574
1575 return 0;
1576 }
1577
1578 void rtl9300_sds_field_w(int sds, u32 page, u32 reg, int end_bit, int start_bit, u32 v)
1579 {
1580 int l = end_bit - start_bit + 1;
1581 u32 data = v;
1582
1583 if (l < 32) {
1584 u32 mask = BIT(l) - 1;
1585
1586 data = rtl930x_read_sds_phy(sds, page, reg);
1587 data &= ~(mask << start_bit);
1588 data |= (v & mask) << start_bit;
1589 }
1590
1591 rtl930x_write_sds_phy(sds, page, reg, data);
1592 }
1593
1594 u32 rtl9300_sds_field_r(int sds, u32 page, u32 reg, int end_bit, int start_bit)
1595 {
1596 int l = end_bit - start_bit + 1;
1597 u32 v = rtl930x_read_sds_phy(sds, page, reg);
1598
1599 if (l >= 32)
1600 return v;
1601
1602 return (v >> start_bit) & (BIT(l) - 1);
1603 }
1604
1605 /* Read the link and speed status of the internal SerDes of the RTL9300
1606 */
1607 static int rtl9300_read_status(struct phy_device *phydev)
1608 {
1609 struct device *dev = &phydev->mdio.dev;
1610 int phy_addr = phydev->mdio.addr;
1611 struct device_node *dn;
1612 u32 sds_num = 0, status, latch_status, mode;
1613
1614 if (dev->of_node) {
1615 dn = dev->of_node;
1616
1617 if (of_property_read_u32(dn, "sds", &sds_num))
1618 sds_num = -1;
1619 pr_info("%s: Port %d, SerDes is %d\n", __func__, phy_addr, sds_num);
1620 } else {
1621 dev_err(dev, "No DT node.\n");
1622 return -EINVAL;
1623 }
1624
1625 if (sds_num < 0)
1626 return 0;
1627
1628 mode = rtl9300_sds_mode_get(sds_num);
1629 pr_info("%s got SDS mode %02x\n", __func__, mode);
1630 if (mode == 0x1a) { // 10GR mode
1631 status = rtl9300_sds_field_r(sds_num, 0x5, 0, 12, 12);
1632 latch_status = rtl9300_sds_field_r(sds_num, 0x4, 1, 2, 2);
1633 status |= rtl9300_sds_field_r(sds_num, 0x5, 0, 12, 12);
1634 latch_status |= rtl9300_sds_field_r(sds_num, 0x4, 1, 2, 2);
1635 } else {
1636 status = rtl9300_sds_field_r(sds_num, 0x1, 29, 8, 0);
1637 latch_status = rtl9300_sds_field_r(sds_num, 0x1, 30, 8, 0);
1638 status |= rtl9300_sds_field_r(sds_num, 0x1, 29, 8, 0);
1639 latch_status |= rtl9300_sds_field_r(sds_num, 0x1, 30, 8, 0);
1640 }
1641
1642 pr_info("%s link status: status: %d, latch %d\n", __func__, status, latch_status);
1643
1644 if (latch_status) {
1645 phydev->link = true;
1646 if (mode == 0x1a)
1647 phydev->speed = SPEED_10000;
1648 else
1649 phydev->speed = SPEED_1000;
1650
1651 phydev->duplex = DUPLEX_FULL;
1652 }
1653
1654 return 0;
1655 }
1656
1657 void rtl930x_sds_rx_rst(int sds_num, phy_interface_t phy_if)
1658 {
1659 int page = 0x2e; // 10GR and USXGMII
1660
1661 if (phy_if == PHY_INTERFACE_MODE_1000BASEX)
1662 page = 0x24;
1663
1664 rtl9300_sds_field_w(sds_num, page, 0x15, 4, 4, 0x1);
1665 mdelay(5);
1666 rtl9300_sds_field_w(sds_num, page, 0x15, 4, 4, 0x0);
1667 }
1668
1669 /*
1670 * Force PHY modes on 10GBit Serdes
1671 */
1672 void rtl9300_force_sds_mode(int sds, phy_interface_t phy_if)
1673 {
1674 int sds_mode;
1675 bool lc_on;
1676 int i, lc_value;
1677 int lane_0 = (sds % 2) ? sds - 1 : sds;
1678 u32 v, cr_0, cr_1, cr_2;
1679 u32 m_bit, l_bit;
1680
1681 pr_info("%s --------------------- serdes %d forcing to %x ...\n", __func__, sds, sds_mode);
1682 pr_info("%s: SDS: %d, mode %d\n", __func__, sds, phy_if);
1683 switch (phy_if) {
1684 case PHY_INTERFACE_MODE_SGMII:
1685 sds_mode = 0x2;
1686 lc_on = false;
1687 lc_value = 0x1;
1688 break;
1689
1690 case PHY_INTERFACE_MODE_HSGMII:
1691 sds_mode = 0x12;
1692 lc_value = 0x3;
1693 // Configure LC
1694 break;
1695
1696 case PHY_INTERFACE_MODE_1000BASEX:
1697 sds_mode = 0x04;
1698 lc_on = false;
1699 break;
1700
1701 case PHY_INTERFACE_MODE_2500BASEX:
1702 sds_mode = 0x16;
1703 lc_value = 0x3;
1704 // Configure LC
1705 break;
1706
1707 case PHY_INTERFACE_MODE_10GBASER:
1708 sds_mode = 0x1a;
1709 lc_on = true;
1710 lc_value = 0x5;
1711 break;
1712
1713 case PHY_INTERFACE_MODE_NA:
1714 // This will disable SerDes
1715 sds_mode = 0x1f;
1716 break;
1717
1718 default:
1719 pr_err("%s: unknown serdes mode: %s\n",
1720 __func__, phy_modes(phy_if));
1721 return;
1722 }
1723
1724 pr_info("%s: SDS mode %x\n", __func__, sds_mode);
1725 // Power down SerDes
1726 rtl9300_sds_field_w(sds, 0x20, 0, 7, 6, 0x3);
1727 if (sds == 5) pr_info("%s after %x\n", __func__, rtl930x_read_sds_phy(sds, 0x20, 0));
1728
1729 if (sds == 5) pr_info("%s a %x\n", __func__, rtl930x_read_sds_phy(sds, 0x1f, 9));
1730 // Force mode enable
1731 rtl9300_sds_field_w(sds, 0x1f, 9, 6, 6, 0x1);
1732 if (sds == 5) pr_info("%s b %x\n", __func__, rtl930x_read_sds_phy(sds, 0x1f, 9));
1733
1734 /* SerDes off */
1735 rtl9300_sds_field_w(sds, 0x1f, 9, 11, 7, 0x1f);
1736
1737 if (phy_if == PHY_INTERFACE_MODE_NA)
1738 return;
1739
1740 if (sds == 5) pr_info("%s c %x\n", __func__, rtl930x_read_sds_phy(sds, 0x20, 18));
1741 // Enable LC and ring
1742 rtl9300_sds_field_w(lane_0, 0x20, 18, 3, 0, 0xf);
1743
1744 if (sds == lane_0)
1745 rtl9300_sds_field_w(lane_0, 0x20, 18, 5, 4, 0x1);
1746 else
1747 rtl9300_sds_field_w(lane_0, 0x20, 18, 7, 6, 0x1);
1748
1749 rtl9300_sds_field_w(sds, 0x20, 0, 5, 4, 0x3);
1750
1751 if (lc_on)
1752 rtl9300_sds_field_w(lane_0, 0x20, 18, 11, 8, lc_value);
1753 else
1754 rtl9300_sds_field_w(lane_0, 0x20, 18, 15, 12, lc_value);
1755
1756 // Force analog LC & ring on
1757 rtl9300_sds_field_w(lane_0, 0x21, 11, 3, 0, 0xf);
1758
1759 v = lc_on ? 0x3 : 0x1;
1760
1761 if (sds == lane_0)
1762 rtl9300_sds_field_w(lane_0, 0x20, 18, 5, 4, v);
1763 else
1764 rtl9300_sds_field_w(lane_0, 0x20, 18, 7, 6, v);
1765
1766 // Force SerDes mode
1767 rtl9300_sds_field_w(sds, 0x1f, 9, 6, 6, 1);
1768 rtl9300_sds_field_w(sds, 0x1f, 9, 11, 7, sds_mode);
1769
1770 // Toggle LC or Ring
1771 for (i = 0; i < 20; i++) {
1772 mdelay(200);
1773
1774 rtl930x_write_sds_phy(lane_0, 0x1f, 2, 53);
1775
1776 m_bit = (lane_0 == sds) ? (4) : (5);
1777 l_bit = (lane_0 == sds) ? (4) : (5);
1778
1779 cr_0 = rtl9300_sds_field_r(lane_0, 0x1f, 20, m_bit, l_bit);
1780 mdelay(10);
1781 cr_1 = rtl9300_sds_field_r(lane_0, 0x1f, 20, m_bit, l_bit);
1782 mdelay(10);
1783 cr_2 = rtl9300_sds_field_r(lane_0, 0x1f, 20, m_bit, l_bit);
1784
1785 if (cr_0 && cr_1 && cr_2) {
1786 u32 t;
1787 if (phy_if != PHY_INTERFACE_MODE_10GBASER)
1788 break;
1789
1790 t = rtl9300_sds_field_r(sds, 0x6, 0x1, 2, 2);
1791 rtl9300_sds_field_w(sds, 0x6, 0x1, 2, 2, 0x1);
1792
1793 // Reset FSM
1794 rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x1);
1795 mdelay(10);
1796 rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x0);
1797 mdelay(10);
1798
1799 // Need to read this twice
1800 v = rtl9300_sds_field_r(sds, 0x5, 0, 12, 12);
1801 v = rtl9300_sds_field_r(sds, 0x5, 0, 12, 12);
1802
1803 rtl9300_sds_field_w(sds, 0x6, 0x1, 2, 2, t);
1804
1805 // Reset FSM again
1806 rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x1);
1807 mdelay(10);
1808 rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x0);
1809 mdelay(10);
1810
1811 if (v == 1)
1812 break;
1813 }
1814
1815 m_bit = (phy_if == PHY_INTERFACE_MODE_10GBASER) ? 3 : 1;
1816 l_bit = (phy_if == PHY_INTERFACE_MODE_10GBASER) ? 2 : 0;
1817
1818 rtl9300_sds_field_w(lane_0, 0x21, 11, m_bit, l_bit, 0x2);
1819 mdelay(10);
1820 rtl9300_sds_field_w(lane_0, 0x21, 11, m_bit, l_bit, 0x3);
1821 }
1822
1823 rtl930x_sds_rx_rst(sds, phy_if);
1824
1825 // Re-enable power
1826 rtl9300_sds_field_w(sds, 0x20, 0, 7, 6, 0);
1827
1828 pr_info("%s --------------------- serdes %d forced to %x DONE\n", __func__, sds, sds_mode);
1829 }
1830
1831 void rtl9300_sds_tx_config(int sds, phy_interface_t phy_if)
1832 {
1833 // parameters: rtl9303_80G_txParam_s2
1834 int impedance = 0x8;
1835 int pre_amp = 0x2;
1836 int main_amp = 0x9;
1837 int post_amp = 0x2;
1838 int pre_en = 0x1;
1839 int post_en = 0x1;
1840 int page;
1841
1842 switch(phy_if) {
1843 case PHY_INTERFACE_MODE_1000BASEX:
1844 page = 0x25;
1845 break;
1846 case PHY_INTERFACE_MODE_HSGMII:
1847 case PHY_INTERFACE_MODE_2500BASEX:
1848 page = 0x29;
1849 break;
1850 case PHY_INTERFACE_MODE_10GBASER:
1851 page = 0x2f;
1852 break;
1853 default:
1854 pr_err("%s: unsupported PHY mode\n", __func__);
1855 return;
1856 }
1857
1858 rtl9300_sds_field_w(sds, page, 0x1, 15, 11, pre_amp);
1859 rtl9300_sds_field_w(sds, page, 0x7, 0, 0, pre_en);
1860 rtl9300_sds_field_w(sds, page, 0x7, 8, 4, main_amp);
1861 rtl9300_sds_field_w(sds, page, 0x6, 4, 0, post_amp);
1862 rtl9300_sds_field_w(sds, page, 0x7, 3, 3, post_en);
1863 rtl9300_sds_field_w(sds, page, 0x18, 15, 12, impedance);
1864 }
1865
1866 /*
1867 * Wait for clock ready, this assumes the SerDes is in XGMII mode
1868 * timeout is in ms
1869 */
1870 int rtl9300_sds_clock_wait(int timeout)
1871 {
1872 u32 v;
1873 unsigned long start = jiffies;
1874
1875 do {
1876 rtl9300_sds_field_w(2, 0x1f, 0x2, 15, 0, 53);
1877 v = rtl9300_sds_field_r(2, 0x1f, 20, 5, 4);
1878 if (v == 3)
1879 return 0;
1880 } while (jiffies < start + (HZ / 1000) * timeout);
1881
1882 return 1;
1883 }
1884
1885 void rtl9300_serdes_mac_link_config(int sds, bool tx_normal, bool rx_normal)
1886 {
1887 u32 v10, v1;
1888
1889 v10 = rtl930x_read_sds_phy(sds, 6, 2); // 10GBit, page 6, reg 2
1890 v1 = rtl930x_read_sds_phy(sds, 0, 0); // 1GBit, page 0, reg 0
1891 pr_info("%s: registers before %08x %08x\n", __func__, v10, v1);
1892
1893 v10 &= ~(BIT(13) | BIT(14));
1894 v1 &= ~(BIT(8) | BIT(9));
1895
1896 v10 |= rx_normal ? 0 : BIT(13);
1897 v1 |= rx_normal ? 0 : BIT(9);
1898
1899 v10 |= tx_normal ? 0 : BIT(14);
1900 v1 |= tx_normal ? 0 : BIT(8);
1901
1902 rtl930x_write_sds_phy(sds, 6, 2, v10);
1903 rtl930x_write_sds_phy(sds, 0, 0, v1);
1904
1905 v10 = rtl930x_read_sds_phy(sds, 6, 2);
1906 v1 = rtl930x_read_sds_phy(sds, 0, 0);
1907 pr_info("%s: registers after %08x %08x\n", __func__, v10, v1);
1908 }
1909
1910 void rtl9300_sds_rxcal_dcvs_manual(u32 sds_num, u32 dcvs_id, bool manual, u32 dvcs_list[])
1911 {
1912 if (manual) {
1913 switch(dcvs_id) {
1914 case 0:
1915 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 14, 14, 0x1);
1916 rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 5, 5, dvcs_list[0]);
1917 rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 4, 0, dvcs_list[1]);
1918 break;
1919 case 1:
1920 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 13, 13, 0x1);
1921 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 15, 15, dvcs_list[0]);
1922 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 14, 11, dvcs_list[1]);
1923 break;
1924 case 2:
1925 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 12, 12, 0x1);
1926 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 10, 10, dvcs_list[0]);
1927 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 9, 6, dvcs_list[1]);
1928 break;
1929 case 3:
1930 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 11, 11, 0x1);
1931 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 5, 5, dvcs_list[0]);
1932 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 4, 1, dvcs_list[1]);
1933 break;
1934 case 4:
1935 rtl9300_sds_field_w(sds_num, 0x2e, 0x01, 15, 15, 0x1);
1936 rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 10, 10, dvcs_list[0]);
1937 rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 9, 6, dvcs_list[1]);
1938 break;
1939 case 5:
1940 rtl9300_sds_field_w(sds_num, 0x2e, 0x02, 11, 11, 0x1);
1941 rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 4, 4, dvcs_list[0]);
1942 rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 3, 0, dvcs_list[1]);
1943 break;
1944 default:
1945 break;
1946 }
1947 } else {
1948 switch(dcvs_id) {
1949 case 0:
1950 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 14, 14, 0x0);
1951 break;
1952 case 1:
1953 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 13, 13, 0x0);
1954 break;
1955 case 2:
1956 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 12, 12, 0x0);
1957 break;
1958 case 3:
1959 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 11, 11, 0x0);
1960 break;
1961 case 4:
1962 rtl9300_sds_field_w(sds_num, 0x2e, 0x01, 15, 15, 0x0);
1963 break;
1964 case 5:
1965 rtl9300_sds_field_w(sds_num, 0x2e, 0x02, 11, 11, 0x0);
1966 break;
1967 default:
1968 break;
1969 }
1970 mdelay(1);
1971 }
1972 }
1973
1974 void rtl9300_sds_rxcal_dcvs_get(u32 sds_num, u32 dcvs_id, u32 dcvs_list[])
1975 {
1976 u32 dcvs_sign_out = 0, dcvs_coef_bin = 0;
1977 bool dcvs_manual;
1978
1979 if (!(sds_num % 2))
1980 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
1981 else
1982 rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
1983
1984 // ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1]
1985 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
1986
1987 // ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x]
1988 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20);
1989
1990 switch(dcvs_id) {
1991 case 0:
1992 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x22);
1993 mdelay(1);
1994
1995 // ##DCVS0 Read Out
1996 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
1997 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
1998 dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 14, 14);
1999 break;
2000
2001 case 1:
2002 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x23);
2003 mdelay(1);
2004
2005 // ##DCVS0 Read Out
2006 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2007 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2008 dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 13, 13);
2009 break;
2010
2011 case 2:
2012 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x24);
2013 mdelay(1);
2014
2015 // ##DCVS0 Read Out
2016 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2017 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2018 dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 12, 12);
2019 break;
2020 case 3:
2021 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x25);
2022 mdelay(1);
2023
2024 // ##DCVS0 Read Out
2025 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2026 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2027 dcvs_manual = rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 11, 11);
2028 break;
2029
2030 case 4:
2031 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x2c);
2032 mdelay(1);
2033
2034 // ##DCVS0 Read Out
2035 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2036 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2037 dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x01, 15, 15);
2038 break;
2039
2040 case 5:
2041 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x2d);
2042 mdelay(1);
2043
2044 // ##DCVS0 Read Out
2045 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2046 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2047 dcvs_manual = rtl9300_sds_field_r(sds_num, 0x2e, 0x02, 11, 11);
2048 break;
2049
2050 default:
2051 break;
2052 }
2053
2054 if (dcvs_sign_out)
2055 pr_info("%s DCVS %u Sign: -", __func__, dcvs_id);
2056 else
2057 pr_info("%s DCVS %u Sign: +", __func__, dcvs_id);
2058
2059 pr_info("DCVS %u even coefficient = %u", dcvs_id, dcvs_coef_bin);
2060 pr_info("DCVS %u manual = %u", dcvs_id, dcvs_manual);
2061
2062 dcvs_list[0] = dcvs_sign_out;
2063 dcvs_list[1] = dcvs_coef_bin;
2064 }
2065
2066 void rtl9300_sds_rxcal_leq_manual(u32 sds_num, bool manual, u32 leq_gray)
2067 {
2068 if (manual) {
2069 rtl9300_sds_field_w(sds_num, 0x2e, 0x18, 15, 15, 0x1);
2070 rtl9300_sds_field_w(sds_num, 0x2e, 0x16, 14, 10, leq_gray);
2071 } else {
2072 rtl9300_sds_field_w(sds_num, 0x2e, 0x18, 15, 15, 0x0);
2073 mdelay(100);
2074 }
2075 }
2076
2077 void rtl9300_sds_rxcal_leq_offset_manual(u32 sds_num, bool manual, u32 offset)
2078 {
2079 if (manual) {
2080 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 6, 2, offset);
2081 } else {
2082 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 6, 2, offset);
2083 mdelay(1);
2084 }
2085 }
2086
2087 #define GRAY_BITS 5
2088 u32 rtl9300_sds_rxcal_gray_to_binary(u32 gray_code)
2089 {
2090 int i, j, m;
2091 u32 g[GRAY_BITS];
2092 u32 c[GRAY_BITS];
2093 u32 leq_binary = 0;
2094
2095 for(i = 0; i < GRAY_BITS; i++)
2096 g[i] = (gray_code & BIT(i)) >> i;
2097
2098 m = GRAY_BITS - 1;
2099
2100 c[m] = g[m];
2101
2102 for(i = 0; i < m; i++) {
2103 c[i] = g[i];
2104 for(j = i + 1; j < GRAY_BITS; j++)
2105 c[i] = c[i] ^ g[j];
2106 }
2107
2108 for(i = 0; i < GRAY_BITS; i++)
2109 leq_binary += c[i] << i;
2110
2111 return leq_binary;
2112 }
2113
2114 u32 rtl9300_sds_rxcal_leq_read(int sds_num)
2115 {
2116 u32 leq_gray, leq_bin;
2117 bool leq_manual;
2118
2119 if (!(sds_num % 2))
2120 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2121 else
2122 rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
2123
2124 // ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1]
2125 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2126
2127 // ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[0 1 x x x x]
2128 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x10);
2129 mdelay(1);
2130
2131 // ##LEQ Read Out
2132 leq_gray = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 7, 3);
2133 leq_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x18, 15, 15);
2134 leq_bin = rtl9300_sds_rxcal_gray_to_binary(leq_gray);
2135
2136 pr_info("LEQ_gray: %u, LEQ_bin: %u", leq_gray, leq_bin);
2137 pr_info("LEQ manual: %u", leq_manual);
2138
2139 return leq_bin;
2140 }
2141
2142 void rtl9300_sds_rxcal_vth_manual(u32 sds_num, bool manual, u32 vth_list[])
2143 {
2144 if (manual) {
2145 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, 13, 13, 0x1);
2146 rtl9300_sds_field_w(sds_num, 0x2e, 0x13, 5, 3, vth_list[0]);
2147 rtl9300_sds_field_w(sds_num, 0x2e, 0x13, 2, 0, vth_list[1]);
2148 } else {
2149 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, 13, 13, 0x0);
2150 mdelay(10);
2151 }
2152 }
2153
2154 void rtl9300_sds_rxcal_vth_get(u32 sds_num, u32 vth_list[])
2155 {
2156 u32 vth_manual;
2157
2158 //##Page0x1F, Reg0x02[15 0], REG_DBGO_SEL=[0x002F]; //Lane0
2159 //##Page0x1F, Reg0x02[15 0], REG_DBGO_SEL=[0x0031]; //Lane1
2160 if (!(sds_num % 2))
2161 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2162 else
2163 rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
2164
2165 //##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1]
2166 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2167 //##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x]
2168 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20);
2169 //##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 0 0]
2170 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0xc);
2171
2172 mdelay(1);
2173
2174 //##VthP & VthN Read Out
2175 vth_list[0] = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 2, 0); // v_thp set bin
2176 vth_list[1] = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 3); // v_thn set bin
2177
2178 pr_info("vth_set_bin = %d", vth_list[0]);
2179 pr_info("vth_set_bin = %d", vth_list[1]);
2180
2181 vth_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x0f, 13, 13);
2182 pr_info("Vth Maunal = %d", vth_manual);
2183 }
2184
2185 void rtl9300_sds_rxcal_tap_manual(u32 sds_num, int tap_id, bool manual, u32 tap_list[])
2186 {
2187 if (manual) {
2188 switch(tap_id) {
2189 case 0:
2190 //##REG0_LOAD_IN_INIT[0]=1; REG0_TAP0_INIT[5:0]=Tap0_Value
2191 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2192 rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 5, 5, tap_list[0]);
2193 rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 4, 0, tap_list[1]);
2194 break;
2195 case 1:
2196 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2197 rtl9300_sds_field_w(sds_num, 0x21, 0x07, 6, 6, tap_list[0]);
2198 rtl9300_sds_field_w(sds_num, 0x2e, 0x09, 11, 6, tap_list[1]);
2199 rtl9300_sds_field_w(sds_num, 0x21, 0x07, 5, 5, tap_list[2]);
2200 rtl9300_sds_field_w(sds_num, 0x2f, 0x12, 5, 0, tap_list[3]);
2201 break;
2202 case 2:
2203 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2204 rtl9300_sds_field_w(sds_num, 0x2e, 0x09, 5, 5, tap_list[0]);
2205 rtl9300_sds_field_w(sds_num, 0x2e, 0x09, 4, 0, tap_list[1]);
2206 rtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 11, 11, tap_list[2]);
2207 rtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 10, 6, tap_list[3]);
2208 break;
2209 case 3:
2210 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2211 rtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 5, 5, tap_list[0]);
2212 rtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 4, 0, tap_list[1]);
2213 rtl9300_sds_field_w(sds_num, 0x2e, 0x06, 5, 5, tap_list[2]);
2214 rtl9300_sds_field_w(sds_num, 0x2e, 0x06, 4, 0, tap_list[3]);
2215 break;
2216 case 4:
2217 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2218 rtl9300_sds_field_w(sds_num, 0x2f, 0x01, 5, 5, tap_list[0]);
2219 rtl9300_sds_field_w(sds_num, 0x2f, 0x01, 4, 0, tap_list[1]);
2220 rtl9300_sds_field_w(sds_num, 0x2e, 0x06, 11, 11, tap_list[2]);
2221 rtl9300_sds_field_w(sds_num, 0x2e, 0x06, 10, 6, tap_list[3]);
2222 break;
2223 default:
2224 break;
2225 }
2226 } else {
2227 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x0);
2228 mdelay(10);
2229 }
2230 }
2231
2232 void rtl9300_sds_rxcal_tap_get(u32 sds_num, u32 tap_id, u32 tap_list[])
2233 {
2234 u32 tap0_sign_out;
2235 u32 tap0_coef_bin;
2236 u32 tap_sign_out_even;
2237 u32 tap_coef_bin_even;
2238 u32 tap_sign_out_odd;
2239 u32 tap_coef_bin_odd;
2240 bool tap_manual;
2241
2242 if (!(sds_num % 2))
2243 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2244 else
2245 rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
2246
2247 //##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1]
2248 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2249 //##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x]
2250 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20);
2251
2252 if (!tap_id) {
2253 //##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 0 0 1]
2254 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0);
2255 //##Tap1 Even Read Out
2256 mdelay(1);
2257 tap0_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 5);
2258 tap0_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 0);
2259
2260 if (tap0_sign_out == 1)
2261 pr_info("Tap0 Sign : -");
2262 else
2263 pr_info("Tap0 Sign : +");
2264
2265 pr_info("tap0_coef_bin = %d", tap0_coef_bin);
2266
2267 tap_list[0] = tap0_sign_out;
2268 tap_list[1] = tap0_coef_bin;
2269
2270 tap_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x0f, 7, 7);
2271 pr_info("tap0 manual = %u",tap_manual);
2272 } else {
2273 //##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 0 0 1]
2274 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, tap_id);
2275 mdelay(1);
2276 //##Tap1 Even Read Out
2277 tap_sign_out_even = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 5);
2278 tap_coef_bin_even = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 0);
2279
2280 //##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 1 1 0]
2281 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, (tap_id + 5));
2282 //##Tap1 Odd Read Out
2283 tap_sign_out_odd = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 5);
2284 tap_coef_bin_odd = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 0);
2285
2286 if (tap_sign_out_even == 1)
2287 pr_info("Tap %u even sign: -", tap_id);
2288 else
2289 pr_info("Tap %u even sign: +", tap_id);
2290
2291 pr_info("Tap %u even coefficient = %u", tap_id, tap_coef_bin_even);
2292
2293 if (tap_sign_out_odd == 1)
2294 pr_info("Tap %u odd sign: -", tap_id);
2295 else
2296 pr_info("Tap %u odd sign: +", tap_id);
2297
2298 pr_info("Tap %u odd coefficient = %u", tap_id,tap_coef_bin_odd);
2299
2300 tap_list[0] = tap_sign_out_even;
2301 tap_list[1] = tap_coef_bin_even;
2302 tap_list[2] = tap_sign_out_odd;
2303 tap_list[3] = tap_coef_bin_odd;
2304
2305 tap_manual = rtl9300_sds_field_r(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7);
2306 pr_info("tap %u manual = %d",tap_id, tap_manual);
2307 }
2308 }
2309
2310 void rtl9300_do_rx_calibration_1(int sds, phy_interface_t phy_mode)
2311 {
2312 // From both rtl9300_rxCaliConf_serdes_myParam and rtl9300_rxCaliConf_phy_myParam
2313 int tap0_init_val = 0x1f; // Initial Decision Fed Equalizer 0 tap
2314 int vth_min = 0x0;
2315
2316 pr_info("start_1.1.1 initial value for sds %d\n", sds);
2317 rtl930x_write_sds_phy(sds, 6, 0, 0);
2318
2319 // FGCAL
2320 rtl9300_sds_field_w(sds, 0x2e, 0x01, 14, 14, 0x0);
2321 rtl9300_sds_field_w(sds, 0x2e, 0x1c, 10, 5, 0x20);
2322 rtl9300_sds_field_w(sds, 0x2f, 0x02, 0, 0, 0x1);
2323
2324 // DCVS
2325 rtl9300_sds_field_w(sds, 0x2e, 0x1e, 14, 11, 0x0);
2326 rtl9300_sds_field_w(sds, 0x2e, 0x01, 15, 15, 0x0);
2327 rtl9300_sds_field_w(sds, 0x2e, 0x02, 11, 11, 0x0);
2328 rtl9300_sds_field_w(sds, 0x2e, 0x1c, 4, 0, 0x0);
2329 rtl9300_sds_field_w(sds, 0x2e, 0x1d, 15, 11, 0x0);
2330 rtl9300_sds_field_w(sds, 0x2e, 0x1d, 10, 6, 0x0);
2331 rtl9300_sds_field_w(sds, 0x2e, 0x1d, 5, 1, 0x0);
2332 rtl9300_sds_field_w(sds, 0x2e, 0x02, 10, 6, 0x0);
2333 rtl9300_sds_field_w(sds, 0x2e, 0x11, 4, 0, 0x0);
2334 rtl9300_sds_field_w(sds, 0x2f, 0x00, 3, 0, 0xf);
2335 rtl9300_sds_field_w(sds, 0x2e, 0x04, 6, 6, 0x1);
2336 rtl9300_sds_field_w(sds, 0x2e, 0x04, 7, 7, 0x1);
2337
2338 // LEQ (Long Term Equivalent signal level)
2339 rtl9300_sds_field_w(sds, 0x2e, 0x16, 14, 8, 0x0);
2340
2341 // DFE (Decision Fed Equalizer)
2342 rtl9300_sds_field_w(sds, 0x2f, 0x03, 5, 0, tap0_init_val);
2343 rtl9300_sds_field_w(sds, 0x2e, 0x09, 11, 6, 0x0);
2344 rtl9300_sds_field_w(sds, 0x2e, 0x09, 5, 0, 0x0);
2345 rtl9300_sds_field_w(sds, 0x2e, 0x0a, 5, 0, 0x0);
2346 rtl9300_sds_field_w(sds, 0x2f, 0x01, 5, 0, 0x0);
2347 rtl9300_sds_field_w(sds, 0x2f, 0x12, 5, 0, 0x0);
2348 rtl9300_sds_field_w(sds, 0x2e, 0x0a, 11, 6, 0x0);
2349 rtl9300_sds_field_w(sds, 0x2e, 0x06, 5, 0, 0x0);
2350 rtl9300_sds_field_w(sds, 0x2f, 0x01, 5, 0, 0x0);
2351
2352 // Vth
2353 rtl9300_sds_field_w(sds, 0x2e, 0x13, 5, 3, 0x7);
2354 rtl9300_sds_field_w(sds, 0x2e, 0x13, 2, 0, 0x7);
2355 rtl9300_sds_field_w(sds, 0x2f, 0x0b, 5, 3, vth_min);
2356
2357 pr_info("end_1.1.1 --\n");
2358
2359 pr_info("start_1.1.2 Load DFE init. value\n");
2360
2361 rtl9300_sds_field_w(sds, 0x2e, 0x0f, 13, 7, 0x7f);
2362
2363 pr_info("end_1.1.2\n");
2364
2365 pr_info("start_1.1.3 disable LEQ training,enable DFE clock\n");
2366
2367 rtl9300_sds_field_w(sds, 0x2e, 0x17, 7, 7, 0x0);
2368 rtl9300_sds_field_w(sds, 0x2e, 0x17, 6, 2, 0x0);
2369 rtl9300_sds_field_w(sds, 0x2e, 0x0c, 8, 8, 0x0);
2370 rtl9300_sds_field_w(sds, 0x2e, 0x0b, 4, 4, 0x1);
2371 rtl9300_sds_field_w(sds, 0x2e, 0x12, 14, 14, 0x0);
2372 rtl9300_sds_field_w(sds, 0x2f, 0x02, 15, 15, 0x0);
2373
2374 pr_info("end_1.1.3 --\n");
2375
2376 pr_info("start_1.1.4 offset cali setting\n");
2377
2378 rtl9300_sds_field_w(sds, 0x2e, 0x0f, 15, 14, 0x3);
2379
2380 pr_info("end_1.1.4\n");
2381
2382 pr_info("start_1.1.5 LEQ and DFE setting\n");
2383
2384 // TODO: make this work for DAC cables of different lengths
2385 // For a 10GBit serdes wit Fibre, SDS 8 or 9
2386 if (phy_mode == PHY_INTERFACE_MODE_10GBASER || PHY_INTERFACE_MODE_1000BASEX)
2387 rtl9300_sds_field_w(sds, 0x2e, 0x16, 3, 2, 0x2);
2388 else
2389 pr_err("%s not PHY-based or SerDes, implement DAC!\n", __func__);
2390
2391 // No serdes, check for Aquantia PHYs
2392 rtl9300_sds_field_w(sds, 0x2e, 0x16, 3, 2, 0x2);
2393
2394 rtl9300_sds_field_w(sds, 0x2e, 0x0f, 6, 0, 0x5f);
2395 rtl9300_sds_field_w(sds, 0x2f, 0x05, 7, 2, 0x1f);
2396 rtl9300_sds_field_w(sds, 0x2e, 0x19, 9, 5, 0x1f);
2397 rtl9300_sds_field_w(sds, 0x2f, 0x0b, 15, 9, 0x3c);
2398 rtl9300_sds_field_w(sds, 0x2e, 0x0b, 1, 0, 0x3);
2399
2400 pr_info("end_1.1.5\n");
2401 }
2402
2403 void rtl9300_do_rx_calibration_2_1(u32 sds_num)
2404 {
2405 pr_info("start_1.2.1 ForegroundOffsetCal_Manual\n");
2406
2407 // Gray config endis to 1
2408 rtl9300_sds_field_w(sds_num, 0x2f, 0x02, 2, 2, 0x1);
2409
2410 // ForegroundOffsetCal_Manual(auto mode)
2411 rtl9300_sds_field_w(sds_num, 0x2e, 0x01, 14, 14, 0x0);
2412
2413 pr_info("end_1.2.1");
2414 }
2415
2416 void rtl9300_do_rx_calibration_2_2(int sds_num)
2417 {
2418 //Force Rx-Run = 0
2419 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 8, 8, 0x0);
2420
2421 rtl930x_sds_rx_rst(sds_num, PHY_INTERFACE_MODE_10GBASER);
2422 }
2423
2424 void rtl9300_do_rx_calibration_2_3(int sds_num)
2425 {
2426 u32 fgcal_binary, fgcal_gray;
2427 u32 offset_range;
2428
2429 pr_info("start_1.2.3 Foreground Calibration\n");
2430
2431 while(1) {
2432 if (!(sds_num % 2))
2433 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2434 else
2435 rtl930x_write_sds_phy(sds_num -1 , 0x1f, 0x2, 0x31);
2436
2437 // ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1]
2438 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2439 // ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x]
2440 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20);
2441 // ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 1 1]
2442 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0xf);
2443 // ##FGCAL read gray
2444 fgcal_gray = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 0);
2445 // ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 1 0]
2446 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0xe);
2447 // ##FGCAL read binary
2448 fgcal_binary = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 0);
2449
2450 pr_info("%s: fgcal_gray: %d, fgcal_binary %d\n",
2451 __func__, fgcal_gray, fgcal_binary);
2452
2453 offset_range = rtl9300_sds_field_r(sds_num, 0x2e, 0x15, 15, 14);
2454
2455 if (fgcal_binary > 60 || fgcal_binary < 3) {
2456 if (offset_range == 3) {
2457 pr_info("%s: Foreground Calibration result marginal!", __func__);
2458 break;
2459 } else {
2460 offset_range++;
2461 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 15, 14, offset_range);
2462 rtl9300_do_rx_calibration_2_2(sds_num);
2463 }
2464 } else {
2465 break;
2466 }
2467 }
2468 pr_info("%s: end_1.2.3\n", __func__);
2469 }
2470
2471 void rtl9300_do_rx_calibration_2(int sds)
2472 {
2473 rtl930x_sds_rx_rst(sds, PHY_INTERFACE_MODE_10GBASER);
2474 rtl9300_do_rx_calibration_2_1(sds);
2475 rtl9300_do_rx_calibration_2_2(sds);
2476 rtl9300_do_rx_calibration_2_3(sds);
2477 }
2478
2479 void rtl9300_sds_rxcal_3_1(int sds_num, phy_interface_t phy_mode)
2480 {
2481 pr_info("start_1.3.1");
2482
2483 // ##1.3.1
2484 if (phy_mode != PHY_INTERFACE_MODE_10GBASER && phy_mode != PHY_INTERFACE_MODE_1000BASEX)
2485 rtl9300_sds_field_w(sds_num, 0x2e, 0xc, 8, 8, 0);
2486
2487 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, 0x0);
2488 rtl9300_sds_rxcal_leq_manual(sds_num, false, 0);
2489
2490 pr_info("end_1.3.1");
2491 }
2492
2493 void rtl9300_sds_rxcal_3_2(int sds_num, phy_interface_t phy_mode)
2494 {
2495 u32 sum10 = 0, avg10, int10;
2496 int dac_long_cable_offset;
2497 bool eq_hold_enabled;
2498 int i;
2499
2500 if (phy_mode == PHY_INTERFACE_MODE_10GBASER || phy_mode == PHY_INTERFACE_MODE_1000BASEX) {
2501 // rtl9300_rxCaliConf_serdes_myParam
2502 dac_long_cable_offset = 3;
2503 eq_hold_enabled = true;
2504 } else {
2505 // rtl9300_rxCaliConf_phy_myParam
2506 dac_long_cable_offset = 0;
2507 eq_hold_enabled = false;
2508 }
2509
2510 if (phy_mode == PHY_INTERFACE_MODE_1000BASEX)
2511 pr_warn("%s: LEQ only valid for 10GR!\n", __func__);
2512
2513 pr_info("start_1.3.2");
2514
2515 for(i = 0; i < 10; i++) {
2516 sum10 += rtl9300_sds_rxcal_leq_read(sds_num);
2517 mdelay(10);
2518 }
2519
2520 avg10 = (sum10 / 10) + (((sum10 % 10) >= 5) ? 1 : 0);
2521 int10 = sum10 / 10;
2522
2523 pr_info("sum10:%u, avg10:%u, int10:%u", sum10, avg10, int10);
2524
2525 if (phy_mode == PHY_INTERFACE_MODE_10GBASER || phy_mode == PHY_INTERFACE_MODE_1000BASEX) {
2526 if (dac_long_cable_offset) {
2527 rtl9300_sds_rxcal_leq_offset_manual(sds_num, 1, dac_long_cable_offset);
2528 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, eq_hold_enabled);
2529 if (phy_mode == PHY_INTERFACE_MODE_10GBASER)
2530 rtl9300_sds_rxcal_leq_manual(sds_num, true, avg10);
2531 } else {
2532 if (sum10 >= 5) {
2533 rtl9300_sds_rxcal_leq_offset_manual(sds_num, 1, 3);
2534 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, 0x1);
2535 if (phy_mode == PHY_INTERFACE_MODE_10GBASER)
2536 rtl9300_sds_rxcal_leq_manual(sds_num, true, avg10);
2537 } else {
2538 rtl9300_sds_rxcal_leq_offset_manual(sds_num, 1, 0);
2539 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, 0x1);
2540 if (phy_mode == PHY_INTERFACE_MODE_10GBASER)
2541 rtl9300_sds_rxcal_leq_manual(sds_num, true, avg10);
2542 }
2543 }
2544 }
2545
2546 pr_info("Sds:%u LEQ = %u",sds_num, rtl9300_sds_rxcal_leq_read(sds_num));
2547
2548 pr_info("end_1.3.2");
2549 }
2550
2551 void rtl9300_do_rx_calibration_3(int sds_num, phy_interface_t phy_mode)
2552 {
2553 rtl9300_sds_rxcal_3_1(sds_num, phy_mode);
2554
2555 if (phy_mode == PHY_INTERFACE_MODE_10GBASER || phy_mode == PHY_INTERFACE_MODE_1000BASEX)
2556 rtl9300_sds_rxcal_3_2(sds_num, phy_mode);
2557 }
2558
2559 void rtl9300_do_rx_calibration_4_1(int sds_num)
2560 {
2561 u32 vth_list[2] = {0, 0};
2562 u32 tap0_list[4] = {0, 0, 0, 0};
2563
2564 pr_info("start_1.4.1");
2565
2566 // ##1.4.1
2567 rtl9300_sds_rxcal_vth_manual(sds_num, false, vth_list);
2568 rtl9300_sds_rxcal_tap_manual(sds_num, 0, false, tap0_list);
2569 mdelay(200);
2570
2571 pr_info("end_1.4.1");
2572 }
2573
2574 void rtl9300_do_rx_calibration_4_2(u32 sds_num)
2575 {
2576 u32 vth_list[2];
2577 u32 tap_list[4];
2578
2579 pr_info("start_1.4.2");
2580
2581 rtl9300_sds_rxcal_vth_get(sds_num, vth_list);
2582 rtl9300_sds_rxcal_vth_manual(sds_num, true, vth_list);
2583
2584 mdelay(100);
2585
2586 rtl9300_sds_rxcal_tap_get(sds_num, 0, tap_list);
2587 rtl9300_sds_rxcal_tap_manual(sds_num, 0, true, tap_list);
2588
2589 pr_info("end_1.4.2");
2590 }
2591
2592 void rtl9300_do_rx_calibration_4(u32 sds_num)
2593 {
2594 rtl9300_do_rx_calibration_4_1(sds_num);
2595 rtl9300_do_rx_calibration_4_2(sds_num);
2596 }
2597
2598 void rtl9300_do_rx_calibration_5_2(u32 sds_num)
2599 {
2600 u32 tap1_list[4] = {0};
2601 u32 tap2_list[4] = {0};
2602 u32 tap3_list[4] = {0};
2603 u32 tap4_list[4] = {0};
2604
2605 pr_info("start_1.5.2");
2606
2607 rtl9300_sds_rxcal_tap_manual(sds_num, 1, false, tap1_list);
2608 rtl9300_sds_rxcal_tap_manual(sds_num, 2, false, tap2_list);
2609 rtl9300_sds_rxcal_tap_manual(sds_num, 3, false, tap3_list);
2610 rtl9300_sds_rxcal_tap_manual(sds_num, 4, false, tap4_list);
2611
2612 mdelay(30);
2613
2614 pr_info("end_1.5.2");
2615 }
2616
2617 void rtl9300_do_rx_calibration_5(u32 sds_num, phy_interface_t phy_mode)
2618 {
2619 if (phy_mode == PHY_INTERFACE_MODE_10GBASER) // dfeTap1_4Enable true
2620 rtl9300_do_rx_calibration_5_2(sds_num);
2621 }
2622
2623
2624 void rtl9300_do_rx_calibration_dfe_disable(u32 sds_num)
2625 {
2626 u32 tap1_list[4] = {0};
2627 u32 tap2_list[4] = {0};
2628 u32 tap3_list[4] = {0};
2629 u32 tap4_list[4] = {0};
2630
2631 rtl9300_sds_rxcal_tap_manual(sds_num, 1, true, tap1_list);
2632 rtl9300_sds_rxcal_tap_manual(sds_num, 2, true, tap2_list);
2633 rtl9300_sds_rxcal_tap_manual(sds_num, 3, true, tap3_list);
2634 rtl9300_sds_rxcal_tap_manual(sds_num, 4, true, tap4_list);
2635
2636 mdelay(10);
2637 }
2638
2639 void rtl9300_do_rx_calibration(int sds, phy_interface_t phy_mode)
2640 {
2641 u32 latch_sts;
2642
2643 rtl9300_do_rx_calibration_1(sds, phy_mode);
2644 rtl9300_do_rx_calibration_2(sds);
2645 rtl9300_do_rx_calibration_4(sds);
2646 rtl9300_do_rx_calibration_5(sds, phy_mode);
2647 mdelay(20);
2648
2649 // Do this only for 10GR mode, SDS active in mode 0x1a
2650 if (rtl9300_sds_field_r(sds, 0x1f, 9, 11, 7) == 0x1a) {
2651 pr_info("%s: SDS enabled\n", __func__);
2652 latch_sts = rtl9300_sds_field_r(sds, 0x4, 1, 2, 2);
2653 mdelay(1);
2654 latch_sts = rtl9300_sds_field_r(sds, 0x4, 1, 2, 2);
2655 if (latch_sts) {
2656 rtl9300_do_rx_calibration_dfe_disable(sds);
2657 rtl9300_do_rx_calibration_4(sds);
2658 rtl9300_do_rx_calibration_5(sds, phy_mode);
2659 }
2660 }
2661 }
2662
2663 int rtl9300_sds_sym_err_reset(int sds_num, phy_interface_t phy_mode)
2664 {
2665 switch (phy_mode) {
2666 case PHY_INTERFACE_MODE_XGMII:
2667 break;
2668
2669 case PHY_INTERFACE_MODE_10GBASER:
2670 // Read twice to clear
2671 rtl930x_read_sds_phy(sds_num, 5, 1);
2672 rtl930x_read_sds_phy(sds_num, 5, 1);
2673 break;
2674
2675 case PHY_INTERFACE_MODE_1000BASEX:
2676 rtl9300_sds_field_w(sds_num, 0x1, 24, 2, 0, 0);
2677 rtl9300_sds_field_w(sds_num, 0x1, 3, 15, 8, 0);
2678 rtl9300_sds_field_w(sds_num, 0x1, 2, 15, 0, 0);
2679 break;
2680
2681 default:
2682 pr_info("%s unsupported phy mode\n", __func__);
2683 return -1;
2684 }
2685
2686 return 0;
2687 }
2688
2689 u32 rtl9300_sds_sym_err_get(int sds_num, phy_interface_t phy_mode)
2690 {
2691 u32 v = 0;
2692
2693 switch (phy_mode) {
2694 case PHY_INTERFACE_MODE_XGMII:
2695 break;
2696
2697 case PHY_INTERFACE_MODE_10GBASER:
2698 v = rtl930x_read_sds_phy(sds_num, 5, 1);
2699 return v & 0xff;
2700
2701 default:
2702 pr_info("%s unsupported PHY-mode\n", __func__);
2703 }
2704
2705 return v;
2706 }
2707
2708 int rtl9300_sds_check_calibration(int sds_num, phy_interface_t phy_mode)
2709 {
2710 u32 errors1, errors2;
2711
2712 rtl9300_sds_sym_err_reset(sds_num, phy_mode);
2713 rtl9300_sds_sym_err_reset(sds_num, phy_mode);
2714
2715 // Count errors during 1ms
2716 errors1 = rtl9300_sds_sym_err_get(sds_num, phy_mode);
2717 mdelay(1);
2718 errors2 = rtl9300_sds_sym_err_get(sds_num, phy_mode);
2719
2720 switch (phy_mode) {
2721 case PHY_INTERFACE_MODE_XGMII:
2722
2723 if ((errors2 - errors1 > 100)
2724 || (errors1 >= 0xffff00) || (errors2 >= 0xffff00)) {
2725 pr_info("%s XSGMII error rate too high\n", __func__);
2726 return 1;
2727 }
2728 break;
2729 case PHY_INTERFACE_MODE_10GBASER:
2730 if (errors2 > 0) {
2731 pr_info("%s 10GBASER error rate too high\n", __func__);
2732 return 1;
2733 }
2734 break;
2735 default:
2736 return 1;
2737 }
2738 return 0;
2739 }
2740
2741 void rtl9300_phy_enable_10g_1g(int sds_num)
2742 {
2743 u32 v;
2744
2745 // Enable 1GBit PHY
2746 v = rtl930x_read_sds_phy(sds_num, PHY_PAGE_2, PHY_CTRL_REG);
2747 pr_info("%s 1gbit phy: %08x\n", __func__, v);
2748 v &= ~BIT(PHY_POWER_BIT);
2749 rtl930x_write_sds_phy(sds_num, PHY_PAGE_2, PHY_CTRL_REG, v);
2750 pr_info("%s 1gbit phy enabled: %08x\n", __func__, v);
2751
2752 // Enable 10GBit PHY
2753 v = rtl930x_read_sds_phy(sds_num, PHY_PAGE_4, PHY_CTRL_REG);
2754 pr_info("%s 10gbit phy: %08x\n", __func__, v);
2755 v &= ~BIT(PHY_POWER_BIT);
2756 rtl930x_write_sds_phy(sds_num, PHY_PAGE_4, PHY_CTRL_REG, v);
2757 pr_info("%s 10gbit phy after: %08x\n", __func__, v);
2758
2759 // dal_longan_construct_mac_default_10gmedia_fiber
2760 v = rtl930x_read_sds_phy(sds_num, 0x1f, 11);
2761 pr_info("%s set medium: %08x\n", __func__, v);
2762 v |= BIT(1);
2763 rtl930x_write_sds_phy(sds_num, 0x1f, 11, v);
2764 pr_info("%s set medium after: %08x\n", __func__, v);
2765 }
2766
2767 #define RTL930X_MAC_FORCE_MODE_CTRL (0xCA1C)
2768 // phy_mode = PHY_INTERFACE_MODE_10GBASER, sds_mode = 0x1a
2769 int rtl9300_serdes_setup(int sds_num, phy_interface_t phy_mode)
2770 {
2771 int sds_mode;
2772 int calib_tries = 0;
2773
2774 switch (phy_mode) {
2775 case PHY_INTERFACE_MODE_HSGMII:
2776 sds_mode = 0x12;
2777 break;
2778 case PHY_INTERFACE_MODE_1000BASEX:
2779 sds_mode = 0x04;
2780 break;
2781 case PHY_INTERFACE_MODE_XGMII:
2782 sds_mode = 0x10;
2783 break;
2784 case PHY_INTERFACE_MODE_10GBASER:
2785 sds_mode = 0x1a;
2786 break;
2787 case PHY_INTERFACE_MODE_USXGMII:
2788 sds_mode = 0x0d;
2789 break;
2790 default:
2791 pr_err("%s: unknown serdes mode: %s\n", __func__, phy_modes(phy_mode));
2792 return -EINVAL;
2793 }
2794
2795 // Maybe use dal_longan_sds_init
2796
2797 // dal_longan_construct_serdesConfig_init // Serdes Construct
2798 rtl9300_phy_enable_10g_1g(sds_num);
2799
2800 // Set Serdes Mode
2801 rtl9300_sds_set(sds_num, 0x1a); // 0x1b: RTK_MII_10GR1000BX_AUTO
2802
2803 // Do RX calibration
2804 do {
2805 rtl9300_do_rx_calibration(sds_num, phy_mode);
2806 calib_tries++;
2807 mdelay(50);
2808 } while (rtl9300_sds_check_calibration(sds_num, phy_mode) && calib_tries < 3);
2809
2810
2811 return 0;
2812 }
2813
2814 typedef struct {
2815 u8 page;
2816 u8 reg;
2817 u16 data;
2818 } sds_config;
2819
2820 sds_config rtl9300_a_sds_10gr_lane0[] =
2821 {
2822 /*1G*/
2823 {0x00, 0x0E, 0x3053}, {0x01, 0x14, 0x0100}, {0x21, 0x03, 0x8206},
2824 {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010}, {0x21, 0x07, 0xF09F},
2825 {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009}, {0x21, 0x0E, 0x0000},
2826 {0x21, 0x0F, 0x0008}, {0x24, 0x00, 0x0668}, {0x24, 0x02, 0xD020},
2827 {0x24, 0x06, 0xC000}, {0x24, 0x0B, 0x1892}, {0x24, 0x0F, 0xFFDF},
2828 {0x24, 0x12, 0x03C4}, {0x24, 0x13, 0x027F}, {0x24, 0x14, 0x1311},
2829 {0x24, 0x16, 0x00C9}, {0x24, 0x17, 0xA100}, {0x24, 0x1A, 0x0001},
2830 {0x24, 0x1C, 0x0400}, {0x25, 0x01, 0x0300}, {0x25, 0x02, 0x1017},
2831 {0x25, 0x03, 0xFFDF}, {0x25, 0x05, 0x7F7C}, {0x25, 0x07, 0x8100},
2832 {0x25, 0x08, 0x0001}, {0x25, 0x09, 0xFFD4}, {0x25, 0x0A, 0x7C2F},
2833 {0x25, 0x0E, 0x003F}, {0x25, 0x0F, 0x0121}, {0x25, 0x10, 0x0020},
2834 {0x25, 0x11, 0x8840}, {0x2B, 0x13, 0x0050}, {0x2B, 0x18, 0x8E88},
2835 {0x2B, 0x19, 0x4902}, {0x2B, 0x1D, 0x2501}, {0x2D, 0x13, 0x0050},
2836 {0x2D, 0x18, 0x8E88}, {0x2D, 0x19, 0x4902}, {0x2D, 0x1D, 0x2641},
2837 {0x2F, 0x13, 0x0050}, {0x2F, 0x18, 0x8E88}, {0x2F, 0x19, 0x4902},
2838 {0x2F, 0x1D, 0x66E1},
2839 /*3.125G*/
2840 {0x28, 0x00, 0x0668}, {0x28, 0x02, 0xD020}, {0x28, 0x06, 0xC000},
2841 {0x28, 0x0B, 0x1892}, {0x28, 0x0F, 0xFFDF}, {0x28, 0x12, 0x01C4},
2842 {0x28, 0x13, 0x027F}, {0x28, 0x14, 0x1311}, {0x28, 0x16, 0x00C9},
2843 {0x28, 0x17, 0xA100}, {0x28, 0x1A, 0x0001}, {0x28, 0x1C, 0x0400},
2844 {0x29, 0x01, 0x0300}, {0x29, 0x02, 0x1017}, {0x29, 0x03, 0xFFDF},
2845 {0x29, 0x05, 0x7F7C}, {0x29, 0x07, 0x8100}, {0x29, 0x08, 0x0001},
2846 {0x29, 0x09, 0xFFD4}, {0x29, 0x0A, 0x7C2F}, {0x29, 0x0E, 0x003F},
2847 {0x29, 0x0F, 0x0121}, {0x29, 0x10, 0x0020}, {0x29, 0x11, 0x8840},
2848 /*10G*/
2849 {0x06, 0x0D, 0x0F00}, {0x06, 0x00, 0x0000}, {0x06, 0x01, 0xC800},
2850 {0x21, 0x03, 0x8206}, {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010},
2851 {0x21, 0x07, 0xF09F}, {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009},
2852 {0x21, 0x0E, 0x0000}, {0x21, 0x0F, 0x0008}, {0x2E, 0x00, 0xA668},
2853 {0x2E, 0x02, 0xD020}, {0x2E, 0x06, 0xC000}, {0x2E, 0x0B, 0x1892},
2854 {0x2E, 0x0F, 0xFFDF}, {0x2E, 0x11, 0x8280}, {0x2E, 0x12, 0x0044},
2855 {0x2E, 0x13, 0x027F}, {0x2E, 0x14, 0x1311}, {0x2E, 0x17, 0xA100},
2856 {0x2E, 0x1A, 0x0001}, {0x2E, 0x1C, 0x0400}, {0x2F, 0x01, 0x0300},
2857 {0x2F, 0x02, 0x1217}, {0x2F, 0x03, 0xFFDF}, {0x2F, 0x05, 0x7F7C},
2858 {0x2F, 0x07, 0x80C4}, {0x2F, 0x08, 0x0001}, {0x2F, 0x09, 0xFFD4},
2859 {0x2F, 0x0A, 0x7C2F}, {0x2F, 0x0E, 0x003F}, {0x2F, 0x0F, 0x0121},
2860 {0x2F, 0x10, 0x0020}, {0x2F, 0x11, 0x8840}, {0x2F, 0x14, 0xE008},
2861 {0x2B, 0x13, 0x0050}, {0x2B, 0x18, 0x8E88}, {0x2B, 0x19, 0x4902},
2862 {0x2B, 0x1D, 0x2501}, {0x2D, 0x13, 0x0050}, {0x2D, 0x17, 0x4109},
2863 {0x2D, 0x18, 0x8E88}, {0x2D, 0x19, 0x4902}, {0x2D, 0x1C, 0x1109},
2864 {0x2D, 0x1D, 0x2641}, {0x2F, 0x13, 0x0050}, {0x2F, 0x18, 0x8E88},
2865 {0x2F, 0x19, 0x4902}, {0x2F, 0x1D, 0x76E1},
2866 };
2867
2868 sds_config rtl9300_a_sds_10gr_lane1[] =
2869 {
2870 /*1G*/
2871 {0x00, 0x0E, 0x3053}, {0x01, 0x14, 0x0100}, {0x21, 0x03, 0x8206},
2872 {0x21, 0x06, 0x0010}, {0x21, 0x07, 0xF09F}, {0x21, 0x0A, 0x0003},
2873 {0x21, 0x0B, 0x0005}, {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009},
2874 {0x21, 0x0E, 0x0000}, {0x21, 0x0F, 0x0008}, {0x24, 0x00, 0x0668},
2875 {0x24, 0x02, 0xD020}, {0x24, 0x06, 0xC000}, {0x24, 0x0B, 0x1892},
2876 {0x24, 0x0F, 0xFFDF}, {0x24, 0x12, 0x03C4}, {0x24, 0x13, 0x027F},
2877 {0x24, 0x14, 0x1311}, {0x24, 0x16, 0x00C9}, {0x24, 0x17, 0xA100},
2878 {0x24, 0x1A, 0x0001}, {0x24, 0x1C, 0x0400}, {0x25, 0x00, 0x820F},
2879 {0x25, 0x01, 0x0300}, {0x25, 0x02, 0x1017}, {0x25, 0x03, 0xFFDF},
2880 {0x25, 0x05, 0x7F7C}, {0x25, 0x07, 0x8100}, {0x25, 0x08, 0x0001},
2881 {0x25, 0x09, 0xFFD4}, {0x25, 0x0A, 0x7C2F}, {0x25, 0x0E, 0x003F},
2882 {0x25, 0x0F, 0x0121}, {0x25, 0x10, 0x0020}, {0x25, 0x11, 0x8840},
2883 {0x2B, 0x13, 0x3D87}, {0x2B, 0x14, 0x3108}, {0x2D, 0x13, 0x3C87},
2884 {0x2D, 0x14, 0x1808},
2885 /*3.125G*/
2886 {0x28, 0x00, 0x0668}, {0x28, 0x02, 0xD020}, {0x28, 0x06, 0xC000},
2887 {0x28, 0x0B, 0x1892}, {0x28, 0x0F, 0xFFDF}, {0x28, 0x12, 0x01C4},
2888 {0x28, 0x13, 0x027F}, {0x28, 0x14, 0x1311}, {0x28, 0x16, 0x00C9},
2889 {0x28, 0x17, 0xA100}, {0x28, 0x1A, 0x0001}, {0x28, 0x1C, 0x0400},
2890 {0x29, 0x00, 0x820F}, {0x29, 0x01, 0x0300}, {0x29, 0x02, 0x1017},
2891 {0x29, 0x03, 0xFFDF}, {0x29, 0x05, 0x7F7C}, {0x29, 0x07, 0x8100},
2892 {0x29, 0x08, 0x0001}, {0x29, 0x0A, 0x7C2F}, {0x29, 0x0E, 0x003F},
2893 {0x29, 0x0F, 0x0121}, {0x29, 0x10, 0x0020}, {0x29, 0x11, 0x8840},
2894 /*10G*/
2895 {0x06, 0x0D, 0x0F00}, {0x06, 0x00, 0x0000}, {0x06, 0x01, 0xC800},
2896 {0x21, 0x03, 0x8206}, {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010},
2897 {0x21, 0x07, 0xF09F}, {0x21, 0x0A, 0x0003}, {0x21, 0x0B, 0x0005},
2898 {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009}, {0x21, 0x0E, 0x0000},
2899 {0x21, 0x0F, 0x0008}, {0x2E, 0x00, 0xA668}, {0x2E, 0x02, 0xD020},
2900 {0x2E, 0x06, 0xC000}, {0x2E, 0x0B, 0x1892}, {0x2E, 0x0F, 0xFFDF},
2901 {0x2E, 0x11, 0x8280}, {0x2E, 0x12, 0x0044}, {0x2E, 0x13, 0x027F},
2902 {0x2E, 0x14, 0x1311}, {0x2E, 0x17, 0xA100}, {0x2E, 0x1A, 0x0001},
2903 {0x2E, 0x1C, 0x0400}, {0x2F, 0x00, 0x820F}, {0x2F, 0x01, 0x0300},
2904 {0x2F, 0x02, 0x1217}, {0x2F, 0x03, 0xFFDF}, {0x2F, 0x05, 0x7F7C},
2905 {0x2F, 0x07, 0x80C4}, {0x2F, 0x08, 0x0001}, {0x2F, 0x09, 0xFFD4},
2906 {0x2F, 0x0A, 0x7C2F}, {0x2F, 0x0E, 0x003F}, {0x2F, 0x0F, 0x0121},
2907 {0x2F, 0x10, 0x0020}, {0x2F, 0x11, 0x8840}, {0x2B, 0x13, 0x3D87},
2908 {0x2B, 0x14, 0x3108}, {0x2D, 0x13, 0x3C87}, {0x2D, 0x14, 0x1808},
2909 };
2910
2911 int rtl9300_sds_cmu_band_get(int sds)
2912 {
2913 u32 page;
2914 u32 en;
2915 u32 cmu_band;
2916
2917 // page = rtl9300_sds_cmu_page_get(sds);
2918 page = 0x25; // 10GR and 1000BX
2919 sds = (sds % 2) ? (sds - 1) : (sds);
2920
2921 rtl9300_sds_field_w(sds, page, 0x1c, 15, 15, 1);
2922 rtl9300_sds_field_w(sds + 1, page, 0x1c, 15, 15, 1);
2923
2924 en = rtl9300_sds_field_r(sds, page, 27, 1, 1);
2925 if(!en) { // Auto mode
2926 rtl930x_write_sds_phy(sds, 0x1f, 0x02, 31);
2927
2928 cmu_band = rtl9300_sds_field_r(sds, 0x1f, 0x15, 5, 1);
2929 } else {
2930 cmu_band = rtl9300_sds_field_r(sds, page, 30, 4, 0);
2931 }
2932
2933 return cmu_band;
2934 }
2935
2936 int rtl9300_configure_serdes(struct phy_device *phydev)
2937 {
2938 struct device *dev = &phydev->mdio.dev;
2939 int phy_addr = phydev->mdio.addr;
2940 struct device_node *dn;
2941 u32 sds_num = 0;
2942 int sds_mode, calib_tries = 0, phy_mode = PHY_INTERFACE_MODE_10GBASER, i;
2943
2944 if (dev->of_node) {
2945 dn = dev->of_node;
2946
2947 if (of_property_read_u32(dn, "sds", &sds_num))
2948 sds_num = -1;
2949 pr_info("%s: Port %d, SerDes is %d\n", __func__, phy_addr, sds_num);
2950 } else {
2951 dev_err(dev, "No DT node.\n");
2952 return -EINVAL;
2953 }
2954
2955 if (sds_num < 0)
2956 return 0;
2957
2958 if (phy_mode != PHY_INTERFACE_MODE_10GBASER) // TODO: for now we only patch 10GR SerDes
2959 return 0;
2960
2961 switch (phy_mode) {
2962 case PHY_INTERFACE_MODE_HSGMII:
2963 sds_mode = 0x12;
2964 break;
2965 case PHY_INTERFACE_MODE_1000BASEX:
2966 sds_mode = 0x04;
2967 break;
2968 case PHY_INTERFACE_MODE_XGMII:
2969 sds_mode = 0x10;
2970 break;
2971 case PHY_INTERFACE_MODE_10GBASER:
2972 sds_mode = 0x1a;
2973 break;
2974 case PHY_INTERFACE_MODE_USXGMII:
2975 sds_mode = 0x0d;
2976 break;
2977 default:
2978 pr_err("%s: unknown serdes mode: %s\n", __func__, phy_modes(phy_mode));
2979 return -EINVAL;
2980 }
2981
2982 pr_info("%s CMU BAND is %d\n", __func__, rtl9300_sds_cmu_band_get(sds_num));
2983
2984 // Turn Off Serdes
2985 rtl9300_sds_rst(sds_num, 0x1f);
2986
2987 pr_info("%s PATCHING SerDes %d\n", __func__, sds_num);
2988 if (sds_num % 2) {
2989 for (i = 0; i < sizeof(rtl9300_a_sds_10gr_lane1) / sizeof(sds_config); ++i) {
2990 rtl930x_write_sds_phy(sds_num, rtl9300_a_sds_10gr_lane1[i].page,
2991 rtl9300_a_sds_10gr_lane1[i].reg,
2992 rtl9300_a_sds_10gr_lane1[i].data);
2993 }
2994 } else {
2995 for (i = 0; i < sizeof(rtl9300_a_sds_10gr_lane0) / sizeof(sds_config); ++i) {
2996 rtl930x_write_sds_phy(sds_num, rtl9300_a_sds_10gr_lane0[i].page,
2997 rtl9300_a_sds_10gr_lane0[i].reg,
2998 rtl9300_a_sds_10gr_lane0[i].data);
2999 }
3000 }
3001
3002 rtl9300_phy_enable_10g_1g(sds_num);
3003
3004 // Disable MAC
3005 sw_w32_mask(0, 1, RTL930X_MAC_FORCE_MODE_CTRL);
3006 mdelay(20);
3007
3008 // ----> dal_longan_sds_mode_set
3009 pr_info("%s: Configuring RTL9300 SERDES %d, mode %02x\n", __func__, sds_num, sds_mode);
3010
3011 // Configure link to MAC
3012 rtl9300_serdes_mac_link_config(sds_num, true, true); // MAC Construct
3013
3014 // Disable MAC
3015 sw_w32_mask(0, 1, RTL930X_MAC_FORCE_MODE_CTRL);
3016 mdelay(20);
3017
3018 rtl9300_force_sds_mode(sds_num, PHY_INTERFACE_MODE_NA);
3019
3020 // Re-Enable MAC
3021 sw_w32_mask(1, 0, RTL930X_MAC_FORCE_MODE_CTRL);
3022
3023 rtl9300_force_sds_mode(sds_num, phy_mode);
3024
3025 // Do RX calibration
3026 do {
3027 rtl9300_do_rx_calibration(sds_num, phy_mode);
3028 calib_tries++;
3029 mdelay(50);
3030 } while (rtl9300_sds_check_calibration(sds_num, phy_mode) && calib_tries < 3);
3031
3032 if (calib_tries >= 3)
3033 pr_err("%s CALIBTRATION FAILED\n", __func__);
3034
3035 rtl9300_sds_tx_config(sds_num, phy_mode);
3036
3037 // The clock needs only to be configured on the FPGA implementation
3038
3039 return 0;
3040 }
3041
3042 void rtl9310_sds_field_w(int sds, u32 page, u32 reg, int end_bit, int start_bit, u32 v)
3043 {
3044 int l = end_bit - start_bit + 1;
3045 u32 data = v;
3046
3047 if (l < 32) {
3048 u32 mask = BIT(l) - 1;
3049
3050 data = rtl930x_read_sds_phy(sds, page, reg);
3051 data &= ~(mask << start_bit);
3052 data |= (v & mask) << start_bit;
3053 }
3054
3055 rtl931x_write_sds_phy(sds, page, reg, data);
3056 }
3057
3058
3059 u32 rtl9310_sds_field_r(int sds, u32 page, u32 reg, int end_bit, int start_bit)
3060 {
3061 int l = end_bit - start_bit + 1;
3062 u32 v = rtl931x_read_sds_phy(sds, page, reg);
3063
3064 if (l >= 32)
3065 return v;
3066
3067 return (v >> start_bit) & (BIT(l) - 1);
3068 }
3069
3070 static void rtl931x_sds_rst(u32 sds)
3071 {
3072 u32 o, v, o_mode;
3073 int shift = ((sds & 0x3) << 3);
3074
3075 // TODO: We need to lock this!
3076
3077 o = sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3078 v = o | BIT(sds);
3079 sw_w32(v, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3080
3081 o_mode = sw_r32(RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3082 v = BIT(7) | 0x1F;
3083 sw_w32_mask(0xff << shift, v << shift, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3084 sw_w32(o_mode, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3085
3086 sw_w32(o, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3087 }
3088
3089 static void rtl931x_symerr_clear(u32 sds, phy_interface_t mode)
3090 {
3091 u32 i;
3092 u32 xsg_sdsid_0, xsg_sdsid_1;
3093
3094 switch (mode) {
3095 case PHY_INTERFACE_MODE_NA:
3096 break;
3097 case PHY_INTERFACE_MODE_XGMII:
3098 if (sds < 2)
3099 xsg_sdsid_0 = sds;
3100 else
3101 xsg_sdsid_0 = (sds - 1) * 2;
3102 xsg_sdsid_1 = xsg_sdsid_0 + 1;
3103
3104 for (i = 0; i < 4; ++i) {
3105 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 24, 2, 0, i);
3106 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 3, 15, 8, 0x0);
3107 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 2, 15, 0, 0x0);
3108 }
3109
3110 for (i = 0; i < 4; ++i) {
3111 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 24, 2, 0, i);
3112 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 3, 15, 8, 0x0);
3113 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 2, 15, 0, 0x0);
3114 }
3115
3116 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 0, 15, 0, 0x0);
3117 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 1, 15, 8, 0x0);
3118 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 0, 15, 0, 0x0);
3119 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 1, 15, 8, 0x0);
3120 break;
3121 default:
3122 break;
3123 }
3124
3125 return;
3126 }
3127
3128 static u32 rtl931x_get_analog_sds(u32 sds)
3129 {
3130 u32 sds_map[] = { 0, 1, 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23 };
3131
3132 if (sds < 14)
3133 return sds_map[sds];
3134 return sds;
3135 }
3136
3137 void rtl931x_sds_fiber_disable(u32 sds)
3138 {
3139 u32 v = 0x3F;
3140 u32 asds = rtl931x_get_analog_sds(sds);
3141
3142 rtl9310_sds_field_w(asds, 0x1F, 0x9, 11, 6, v);
3143 }
3144
3145 static void rtl931x_sds_fiber_mode_set(u32 sds, phy_interface_t mode)
3146 {
3147 u32 val, asds = rtl931x_get_analog_sds(sds);
3148
3149 /* clear symbol error count before changing mode */
3150 rtl931x_symerr_clear(sds, mode);
3151
3152 val = 0x9F;
3153 sw_w32(val, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3154
3155 switch (mode) {
3156 case PHY_INTERFACE_MODE_SGMII:
3157 val = 0x5;
3158 break;
3159
3160 case PHY_INTERFACE_MODE_1000BASEX:
3161 /* serdes mode FIBER1G */
3162 val = 0x9;
3163 break;
3164
3165 case PHY_INTERFACE_MODE_10GBASER:
3166 case PHY_INTERFACE_MODE_10GKR:
3167 val = 0x35;
3168 break;
3169 /* case MII_10GR1000BX_AUTO:
3170 val = 0x39;
3171 break; */
3172
3173
3174 case PHY_INTERFACE_MODE_USXGMII:
3175 val = 0x1B;
3176 break;
3177 default:
3178 val = 0x25;
3179 }
3180
3181 pr_info("%s writing analog SerDes Mode value %02x\n", __func__, val);
3182 rtl9310_sds_field_w(asds, 0x1F, 0x9, 11, 6, val);
3183
3184 return;
3185 }
3186
3187 static int rtl931x_sds_cmu_page_get(phy_interface_t mode)
3188 {
3189 switch (mode) {
3190 case PHY_INTERFACE_MODE_SGMII:
3191 case PHY_INTERFACE_MODE_1000BASEX: // MII_1000BX_FIBER / 100BX_FIBER / 1000BX100BX_AUTO
3192 return 0x24;
3193 case PHY_INTERFACE_MODE_HSGMII:
3194 case PHY_INTERFACE_MODE_2500BASEX: // MII_2500Base_X:
3195 return 0x28;
3196 // case MII_HISGMII_5G:
3197 // return 0x2a;
3198 case PHY_INTERFACE_MODE_QSGMII:
3199 return 0x2a; // Code also has 0x34
3200 case PHY_INTERFACE_MODE_XAUI: // MII_RXAUI_LITE:
3201 return 0x2c;
3202 case PHY_INTERFACE_MODE_XGMII: // MII_XSGMII
3203 case PHY_INTERFACE_MODE_10GKR:
3204 case PHY_INTERFACE_MODE_10GBASER: // MII_10GR
3205 return 0x2e;
3206 default:
3207 return -1;
3208 }
3209 return -1;
3210 }
3211
3212 static void rtl931x_cmu_type_set(u32 asds, phy_interface_t mode, int chiptype)
3213 {
3214 int cmu_type = 0; // Clock Management Unit
3215 u32 cmu_page = 0;
3216 u32 frc_cmu_spd;
3217 u32 evenSds;
3218 u32 lane, frc_lc_mode_bitnum, frc_lc_mode_val_bitnum;
3219
3220 switch (mode) {
3221 case PHY_INTERFACE_MODE_NA:
3222 case PHY_INTERFACE_MODE_10GKR:
3223 case PHY_INTERFACE_MODE_XGMII:
3224 case PHY_INTERFACE_MODE_10GBASER:
3225 case PHY_INTERFACE_MODE_USXGMII:
3226 return;
3227
3228 /* case MII_10GR1000BX_AUTO:
3229 if (chiptype)
3230 rtl9310_sds_field_w(asds, 0x24, 0xd, 14, 14, 0);
3231 return; */
3232
3233 case PHY_INTERFACE_MODE_QSGMII:
3234 cmu_type = 1;
3235 frc_cmu_spd = 0;
3236 break;
3237
3238 case PHY_INTERFACE_MODE_HSGMII:
3239 cmu_type = 1;
3240 frc_cmu_spd = 1;
3241 break;
3242
3243 case PHY_INTERFACE_MODE_1000BASEX:
3244 cmu_type = 1;
3245 frc_cmu_spd = 0;
3246 break;
3247
3248 /* case MII_1000BX100BX_AUTO:
3249 cmu_type = 1;
3250 frc_cmu_spd = 0;
3251 break; */
3252
3253 case PHY_INTERFACE_MODE_SGMII:
3254 cmu_type = 1;
3255 frc_cmu_spd = 0;
3256 break;
3257
3258 case PHY_INTERFACE_MODE_2500BASEX:
3259 cmu_type = 1;
3260 frc_cmu_spd = 1;
3261 break;
3262
3263 default:
3264 pr_info("SerDes %d mode is invalid\n", asds);
3265 return;
3266 }
3267
3268 if (cmu_type == 1)
3269 cmu_page = rtl931x_sds_cmu_page_get(mode);
3270
3271 lane = asds % 2;
3272
3273 if (!lane) {
3274 frc_lc_mode_bitnum = 4;
3275 frc_lc_mode_val_bitnum = 5;
3276 } else {
3277 frc_lc_mode_bitnum = 6;
3278 frc_lc_mode_val_bitnum = 7;
3279 }
3280
3281 evenSds = asds - lane;
3282
3283 pr_info("%s: cmu_type %0d cmu_page %x frc_cmu_spd %d lane %d asds %d\n",
3284 __func__, cmu_type, cmu_page, frc_cmu_spd, lane, asds);
3285
3286 if (cmu_type == 1) {
3287 pr_info("%s A CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7));
3288 rtl9310_sds_field_w(asds, cmu_page, 0x7, 15, 15, 0);
3289 pr_info("%s B CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7));
3290 if (chiptype) {
3291 rtl9310_sds_field_w(asds, cmu_page, 0xd, 14, 14, 0);
3292 }
3293
3294 rtl9310_sds_field_w(evenSds, 0x20, 0x12, 3, 2, 0x3);
3295 rtl9310_sds_field_w(evenSds, 0x20, 0x12, frc_lc_mode_bitnum, frc_lc_mode_bitnum, 1);
3296 rtl9310_sds_field_w(evenSds, 0x20, 0x12, frc_lc_mode_val_bitnum, frc_lc_mode_val_bitnum, 0);
3297 rtl9310_sds_field_w(evenSds, 0x20, 0x12, 12, 12, 1);
3298 rtl9310_sds_field_w(evenSds, 0x20, 0x12, 15, 13, frc_cmu_spd);
3299 }
3300
3301 pr_info("%s CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7));
3302 return;
3303 }
3304
3305 static void rtl931x_sds_rx_rst(u32 sds)
3306 {
3307 u32 asds = rtl931x_get_analog_sds(sds);
3308
3309 if (sds < 2)
3310 return;
3311
3312 rtl931x_write_sds_phy(asds, 0x2e, 0x12, 0x2740);
3313 rtl931x_write_sds_phy(asds, 0x2f, 0x0, 0x0);
3314 rtl931x_write_sds_phy(asds, 0x2f, 0x2, 0x2010);
3315 rtl931x_write_sds_phy(asds, 0x20, 0x0, 0xc10);
3316
3317 rtl931x_write_sds_phy(asds, 0x2e, 0x12, 0x27c0);
3318 rtl931x_write_sds_phy(asds, 0x2f, 0x0, 0xc000);
3319 rtl931x_write_sds_phy(asds, 0x2f, 0x2, 0x6010);
3320 rtl931x_write_sds_phy(asds, 0x20, 0x0, 0xc30);
3321
3322 mdelay(50);
3323 }
3324
3325 static void rtl931x_sds_disable(u32 sds)
3326 {
3327 u32 v = 0x1f;
3328
3329 v |= BIT(7);
3330 sw_w32(v, RTL931X_SERDES_MODE_CTRL + (sds >> 2) * 4);
3331 }
3332
3333 static void rtl931x_sds_mii_mode_set(u32 sds, phy_interface_t mode)
3334 {
3335 u32 val;
3336
3337 switch (mode) {
3338 case PHY_INTERFACE_MODE_QSGMII:
3339 val = 0x6;
3340 break;
3341 case PHY_INTERFACE_MODE_XGMII:
3342 val = 0x10; // serdes mode XSGMII
3343 break;
3344 case PHY_INTERFACE_MODE_USXGMII:
3345 case PHY_INTERFACE_MODE_2500BASEX:
3346 val = 0xD;
3347 break;
3348 case PHY_INTERFACE_MODE_HSGMII:
3349 val = 0x12;
3350 break;
3351 case PHY_INTERFACE_MODE_SGMII:
3352 val = 0x2;
3353 break;
3354 default:
3355 return;
3356 }
3357
3358 val |= (1 << 7);
3359
3360 sw_w32(val, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3361 }
3362
3363 static sds_config sds_config_10p3125g_type1[] = {
3364 { 0x2E, 0x00, 0x0107 }, { 0x2E, 0x01, 0x01A3 }, { 0x2E, 0x02, 0x6A24 },
3365 { 0x2E, 0x03, 0xD10D }, { 0x2E, 0x04, 0x8000 }, { 0x2E, 0x05, 0xA17E },
3366 { 0x2E, 0x06, 0xE31D }, { 0x2E, 0x07, 0x800E }, { 0x2E, 0x08, 0x0294 },
3367 { 0x2E, 0x09, 0x0CE4 }, { 0x2E, 0x0A, 0x7FC8 }, { 0x2E, 0x0B, 0xE0E7 },
3368 { 0x2E, 0x0C, 0x0200 }, { 0x2E, 0x0D, 0xDF80 }, { 0x2E, 0x0E, 0x0000 },
3369 { 0x2E, 0x0F, 0x1FC2 }, { 0x2E, 0x10, 0x0C3F }, { 0x2E, 0x11, 0x0000 },
3370 { 0x2E, 0x12, 0x27C0 }, { 0x2E, 0x13, 0x7E1D }, { 0x2E, 0x14, 0x1300 },
3371 { 0x2E, 0x15, 0x003F }, { 0x2E, 0x16, 0xBE7F }, { 0x2E, 0x17, 0x0090 },
3372 { 0x2E, 0x18, 0x0000 }, { 0x2E, 0x19, 0x4000 }, { 0x2E, 0x1A, 0x0000 },
3373 { 0x2E, 0x1B, 0x8000 }, { 0x2E, 0x1C, 0x011F }, { 0x2E, 0x1D, 0x0000 },
3374 { 0x2E, 0x1E, 0xC8FF }, { 0x2E, 0x1F, 0x0000 }, { 0x2F, 0x00, 0xC000 },
3375 { 0x2F, 0x01, 0xF000 }, { 0x2F, 0x02, 0x6010 }, { 0x2F, 0x12, 0x0EE7 },
3376 { 0x2F, 0x13, 0x0000 }
3377 };
3378
3379 static sds_config sds_config_10p3125g_cmu_type1[] = {
3380 { 0x2F, 0x03, 0x4210 }, { 0x2F, 0x04, 0x0000 }, { 0x2F, 0x05, 0x0019 },
3381 { 0x2F, 0x06, 0x18A6 }, { 0x2F, 0x07, 0x2990 }, { 0x2F, 0x08, 0xFFF4 },
3382 { 0x2F, 0x09, 0x1F08 }, { 0x2F, 0x0A, 0x0000 }, { 0x2F, 0x0B, 0x8000 },
3383 { 0x2F, 0x0C, 0x4224 }, { 0x2F, 0x0D, 0x0000 }, { 0x2F, 0x0E, 0x0000 },
3384 { 0x2F, 0x0F, 0xA470 }, { 0x2F, 0x10, 0x8000 }, { 0x2F, 0x11, 0x037B }
3385 };
3386
3387 void rtl931x_sds_init(u32 sds, phy_interface_t mode)
3388 {
3389
3390 u32 board_sds_tx_type1[] = { 0x1C3, 0x1C3, 0x1C3, 0x1A3, 0x1A3,
3391 0x1A3, 0x143, 0x143, 0x143, 0x143, 0x163, 0x163
3392 };
3393
3394 u32 board_sds_tx[] = { 0x1A00, 0x1A00, 0x200, 0x200, 0x200,
3395 0x200, 0x1A3, 0x1A3, 0x1A3, 0x1A3, 0x1E3, 0x1E3
3396 };
3397
3398 u32 board_sds_tx2[] = { 0xDC0, 0x1C0, 0x200, 0x180, 0x160,
3399 0x123, 0x123, 0x163, 0x1A3, 0x1A0, 0x1C3, 0x9C3
3400 };
3401
3402 u32 asds, dSds, ori, model_info, val;
3403 int chiptype = 0;
3404
3405 asds = rtl931x_get_analog_sds(sds);
3406
3407 if (sds > 13)
3408 return;
3409
3410 pr_info("%s: set sds %d to mode %d\n", __func__, sds, mode);
3411 val = rtl9310_sds_field_r(asds, 0x1F, 0x9, 11, 6);
3412
3413 pr_info("%s: fibermode %08X stored mode 0x%x analog SDS %d", __func__,
3414 rtl931x_read_sds_phy(asds, 0x1f, 0x9), val, asds);
3415 pr_info("%s: SGMII mode %08X in 0x24 0x9 analog SDS %d", __func__,
3416 rtl931x_read_sds_phy(asds, 0x24, 0x9), asds);
3417 pr_info("%s: CMU mode %08X stored even SDS %d", __func__,
3418 rtl931x_read_sds_phy(asds & ~1, 0x20, 0x12), asds & ~1);
3419 pr_info("%s: serdes_mode_ctrl %08X", __func__, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3420 pr_info("%s CMU page 0x24 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x24, 0x7));
3421 pr_info("%s CMU page 0x26 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x26, 0x7));
3422 pr_info("%s CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7));
3423 pr_info("%s XSG page 0x0 0xe %08x\n", __func__, rtl931x_read_sds_phy(dSds, 0x0, 0xe));
3424 pr_info("%s XSG2 page 0x0 0xe %08x\n", __func__, rtl931x_read_sds_phy(dSds + 1, 0x0, 0xe));
3425
3426 model_info = sw_r32(RTL93XX_MODEL_NAME_INFO);
3427 if ((model_info >> 4) & 0x1) {
3428 pr_info("detected chiptype 1\n");
3429 chiptype = 1;
3430 } else {
3431 pr_info("detected chiptype 0\n");
3432 }
3433
3434 if (sds < 2)
3435 dSds = sds;
3436 else
3437 dSds = (sds - 1) * 2;
3438
3439 pr_info("%s: 2.5gbit %08X dsds %d", __func__,
3440 rtl931x_read_sds_phy(dSds, 0x1, 0x14), dSds);
3441
3442 pr_info("%s: RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR 0x%08X\n", __func__, sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR));
3443 ori = sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3444 val = ori | (1 << sds);
3445 sw_w32(val, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3446
3447 switch (mode) {
3448 case PHY_INTERFACE_MODE_NA:
3449 break;
3450
3451 case PHY_INTERFACE_MODE_XGMII: // MII_XSGMII
3452
3453 if (chiptype) {
3454 u32 xsg_sdsid_1;
3455 xsg_sdsid_1 = dSds + 1;
3456 //fifo inv clk
3457 rtl9310_sds_field_w(dSds, 0x1, 0x1, 7, 4, 0xf);
3458 rtl9310_sds_field_w(dSds, 0x1, 0x1, 3, 0, 0xf);
3459
3460 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 0x1, 7, 4, 0xf);
3461 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 0x1, 3, 0, 0xf);
3462
3463 }
3464
3465 rtl9310_sds_field_w(dSds, 0x0, 0xE, 12, 12, 1);
3466 rtl9310_sds_field_w(dSds + 1, 0x0, 0xE, 12, 12, 1);
3467 break;
3468
3469 case PHY_INTERFACE_MODE_USXGMII: // MII_USXGMII_10GSXGMII/10GDXGMII/10GQXGMII:
3470 u32 i, evenSds;
3471 u32 op_code = 0x6003;
3472
3473 if (chiptype) {
3474 rtl9310_sds_field_w(asds, 0x6, 0x2, 12, 12, 1);
3475
3476 for (i = 0; i < sizeof(sds_config_10p3125g_type1) / sizeof(sds_config); ++i) {
3477 rtl931x_write_sds_phy(asds, sds_config_10p3125g_type1[i].page - 0x4, sds_config_10p3125g_type1[i].reg, sds_config_10p3125g_type1[i].data);
3478 }
3479
3480 evenSds = asds - (asds % 2);
3481
3482 for (i = 0; i < sizeof(sds_config_10p3125g_cmu_type1) / sizeof(sds_config); ++i) {
3483 rtl931x_write_sds_phy(evenSds,
3484 sds_config_10p3125g_cmu_type1[i].page - 0x4, sds_config_10p3125g_cmu_type1[i].reg, sds_config_10p3125g_cmu_type1[i].data);
3485 }
3486
3487 rtl9310_sds_field_w(asds, 0x6, 0x2, 12, 12, 0);
3488 } else {
3489
3490 rtl9310_sds_field_w(asds, 0x2e, 0xd, 6, 0, 0x0);
3491 rtl9310_sds_field_w(asds, 0x2e, 0xd, 7, 7, 0x1);
3492
3493 rtl9310_sds_field_w(asds, 0x2e, 0x1c, 5, 0, 0x1E);
3494 rtl9310_sds_field_w(asds, 0x2e, 0x1d, 11, 0, 0x00);
3495 rtl9310_sds_field_w(asds, 0x2e, 0x1f, 11, 0, 0x00);
3496 rtl9310_sds_field_w(asds, 0x2f, 0x0, 11, 0, 0x00);
3497 rtl9310_sds_field_w(asds, 0x2f, 0x1, 11, 0, 0x00);
3498
3499 rtl9310_sds_field_w(asds, 0x2e, 0xf, 12, 6, 0x7F);
3500 rtl931x_write_sds_phy(asds, 0x2f, 0x12, 0xaaa);
3501
3502 rtl931x_sds_rx_rst(sds);
3503
3504 rtl931x_write_sds_phy(asds, 0x7, 0x10, op_code);
3505 rtl931x_write_sds_phy(asds, 0x6, 0x1d, 0x0480);
3506 rtl931x_write_sds_phy(asds, 0x6, 0xe, 0x0400);
3507 }
3508 break;
3509
3510 case PHY_INTERFACE_MODE_10GBASER: // MII_10GR / MII_10GR1000BX_AUTO:
3511 // configure 10GR fiber mode=1
3512 rtl9310_sds_field_w(asds, 0x1f, 0xb, 1, 1, 1);
3513
3514 // init fiber_1g
3515 rtl9310_sds_field_w(dSds, 0x3, 0x13, 15, 14, 0);
3516
3517 rtl9310_sds_field_w(dSds, 0x2, 0x0, 12, 12, 1);
3518 rtl9310_sds_field_w(dSds, 0x2, 0x0, 6, 6, 1);
3519 rtl9310_sds_field_w(dSds, 0x2, 0x0, 13, 13, 0);
3520
3521 // init auto
3522 rtl9310_sds_field_w(asds, 0x1f, 13, 15, 0, 0x109e);
3523 rtl9310_sds_field_w(asds, 0x1f, 0x6, 14, 10, 0x8);
3524 rtl9310_sds_field_w(asds, 0x1f, 0x7, 10, 4, 0x7f);
3525 break;
3526
3527 case PHY_INTERFACE_MODE_HSGMII:
3528 rtl9310_sds_field_w(dSds, 0x1, 0x14, 8, 8, 1);
3529 break;
3530
3531 case PHY_INTERFACE_MODE_1000BASEX: // MII_1000BX_FIBER
3532 rtl9310_sds_field_w(dSds, 0x3, 0x13, 15, 14, 0);
3533
3534 rtl9310_sds_field_w(dSds, 0x2, 0x0, 12, 12, 1);
3535 rtl9310_sds_field_w(dSds, 0x2, 0x0, 6, 6, 1);
3536 rtl9310_sds_field_w(dSds, 0x2, 0x0, 13, 13, 0);
3537 break;
3538
3539 case PHY_INTERFACE_MODE_SGMII:
3540 rtl9310_sds_field_w(asds, 0x24, 0x9, 15, 15, 0);
3541 break;
3542
3543 case PHY_INTERFACE_MODE_2500BASEX:
3544 rtl9310_sds_field_w(dSds, 0x1, 0x14, 8, 8, 1);
3545 break;
3546
3547 case PHY_INTERFACE_MODE_QSGMII:
3548 default:
3549 pr_info("%s: PHY mode %s not supported by SerDes %d\n",
3550 __func__, phy_modes(mode), sds);
3551 return;
3552 }
3553
3554 rtl931x_cmu_type_set(asds, mode, chiptype);
3555
3556 if (sds >= 2 && sds <= 13) {
3557 if (chiptype)
3558 rtl931x_write_sds_phy(asds, 0x2E, 0x1, board_sds_tx_type1[sds - 2]);
3559 else {
3560 val = 0xa0000;
3561 sw_w32(val, RTL931X_CHIP_INFO_ADDR);
3562 val = sw_r32(RTL931X_CHIP_INFO_ADDR);
3563 if (val & BIT(28)) // consider 9311 etc. RTL9313_CHIP_ID == HWP_CHIP_ID(unit))
3564 {
3565 rtl931x_write_sds_phy(asds, 0x2E, 0x1, board_sds_tx2[sds - 2]);
3566 } else {
3567 rtl931x_write_sds_phy(asds, 0x2E, 0x1, board_sds_tx[sds - 2]);
3568 }
3569 val = 0;
3570 sw_w32(val, RTL931X_CHIP_INFO_ADDR);
3571 }
3572 }
3573
3574 val = ori & ~BIT(sds);
3575 sw_w32(val, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3576 pr_debug("%s: RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR 0x%08X\n", __func__, sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR));
3577
3578 if (mode == PHY_INTERFACE_MODE_XGMII || mode == PHY_INTERFACE_MODE_QSGMII
3579 || mode == PHY_INTERFACE_MODE_HSGMII || mode == PHY_INTERFACE_MODE_SGMII
3580 || mode == PHY_INTERFACE_MODE_USXGMII) {
3581 if (mode == PHY_INTERFACE_MODE_XGMII)
3582 rtl931x_sds_mii_mode_set(sds, mode);
3583 else
3584 rtl931x_sds_fiber_mode_set(sds, mode);
3585 }
3586 }
3587
3588 int rtl931x_sds_cmu_band_set(int sds, bool enable, u32 band, phy_interface_t mode)
3589 {
3590 u32 asds;
3591 int page = rtl931x_sds_cmu_page_get(mode);
3592
3593 sds -= (sds % 2);
3594 sds = sds & ~1;
3595 asds = rtl931x_get_analog_sds(sds);
3596 page += 1;
3597
3598 if (enable) {
3599 rtl9310_sds_field_w(asds, page, 0x7, 13, 13, 0);
3600 rtl9310_sds_field_w(asds, page, 0x7, 11, 11, 0);
3601 } else {
3602 rtl9310_sds_field_w(asds, page, 0x7, 13, 13, 0);
3603 rtl9310_sds_field_w(asds, page, 0x7, 11, 11, 0);
3604 }
3605
3606 rtl9310_sds_field_w(asds, page, 0x7, 4, 0, band);
3607
3608 rtl931x_sds_rst(sds);
3609
3610 return 0;
3611 }
3612
3613 int rtl931x_sds_cmu_band_get(int sds, phy_interface_t mode)
3614 {
3615 int page = rtl931x_sds_cmu_page_get(mode);
3616 u32 asds, band;
3617
3618 sds -= (sds % 2);
3619 asds = rtl931x_get_analog_sds(sds);
3620 page += 1;
3621 rtl931x_write_sds_phy(asds, 0x1f, 0x02, 73);
3622
3623 rtl9310_sds_field_w(asds, page, 0x5, 15, 15, 1);
3624 band = rtl9310_sds_field_r(asds, 0x1f, 0x15, 8, 3);
3625 pr_info("%s band is: %d\n", __func__, band);
3626
3627 return band;
3628 }
3629
3630
3631 int rtl931x_link_sts_get(u32 sds)
3632 {
3633 u32 sts, sts1, latch_sts, latch_sts1;
3634 if (0){
3635 u32 xsg_sdsid_0, xsg_sdsid_1;
3636
3637 xsg_sdsid_0 = sds < 2 ? sds : (sds - 1) * 2;
3638 xsg_sdsid_1 = xsg_sdsid_0 + 1;
3639
3640 sts = rtl9310_sds_field_r(xsg_sdsid_0, 0x1, 29, 8, 0);
3641 sts1 = rtl9310_sds_field_r(xsg_sdsid_1, 0x1, 29, 8, 0);
3642 latch_sts = rtl9310_sds_field_r(xsg_sdsid_0, 0x1, 30, 8, 0);
3643 latch_sts1 = rtl9310_sds_field_r(xsg_sdsid_1, 0x1, 30, 8, 0);
3644 } else {
3645 u32 asds, dsds;
3646
3647 asds = rtl931x_get_analog_sds(sds);
3648 sts = rtl9310_sds_field_r(asds, 0x5, 0, 12, 12);
3649 latch_sts = rtl9310_sds_field_r(asds, 0x4, 1, 2, 2);
3650
3651 dsds = sds < 2 ? sds : (sds - 1) * 2;
3652 latch_sts1 = rtl9310_sds_field_r(dsds, 0x2, 1, 2, 2);
3653 sts1 = rtl9310_sds_field_r(dsds, 0x2, 1, 2, 2);
3654 }
3655
3656 pr_info("%s: serdes %d sts %d, sts1 %d, latch_sts %d, latch_sts1 %d\n", __func__,
3657 sds, sts, sts1, latch_sts, latch_sts1);
3658 return sts1;
3659 }
3660
3661 static int rtl8214fc_phy_probe(struct phy_device *phydev)
3662 {
3663 struct device *dev = &phydev->mdio.dev;
3664 int addr = phydev->mdio.addr;
3665 int ret = 0;
3666
3667 /* 839x has internal SerDes */
3668 if (soc_info.id == 0x8393)
3669 return -ENODEV;
3670
3671 /* All base addresses of the PHYs start at multiples of 8 */
3672 devm_phy_package_join(dev, phydev, addr & (~7),
3673 sizeof(struct rtl83xx_shared_private));
3674
3675 if (!(addr % 8)) {
3676 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3677 shared->name = "RTL8214FC";
3678 /* Configuration must be done while patching still possible */
3679 ret = rtl8380_configure_rtl8214fc(phydev);
3680 if (ret)
3681 return ret;
3682 }
3683
3684 return 0;
3685 }
3686
3687 static int rtl8214c_phy_probe(struct phy_device *phydev)
3688 {
3689 struct device *dev = &phydev->mdio.dev;
3690 int addr = phydev->mdio.addr;
3691
3692 /* All base addresses of the PHYs start at multiples of 8 */
3693 devm_phy_package_join(dev, phydev, addr & (~7),
3694 sizeof(struct rtl83xx_shared_private));
3695
3696 if (!(addr % 8)) {
3697 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3698 shared->name = "RTL8214C";
3699 /* Configuration must be done whil patching still possible */
3700 return rtl8380_configure_rtl8214c(phydev);
3701 }
3702 return 0;
3703 }
3704
3705 static int rtl8218b_ext_phy_probe(struct phy_device *phydev)
3706 {
3707 struct device *dev = &phydev->mdio.dev;
3708 int addr = phydev->mdio.addr;
3709
3710 /* All base addresses of the PHYs start at multiples of 8 */
3711 devm_phy_package_join(dev, phydev, addr & (~7),
3712 sizeof(struct rtl83xx_shared_private));
3713
3714 if (!(addr % 8)) {
3715 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3716 shared->name = "RTL8218B (external)";
3717 if (soc_info.family == RTL8380_FAMILY_ID) {
3718 /* Configuration must be done while patching still possible */
3719 return rtl8380_configure_ext_rtl8218b(phydev);
3720 }
3721 }
3722
3723 return 0;
3724 }
3725
3726 static int rtl8218b_int_phy_probe(struct phy_device *phydev)
3727 {
3728 struct device *dev = &phydev->mdio.dev;
3729 int addr = phydev->mdio.addr;
3730
3731 if (soc_info.family != RTL8380_FAMILY_ID)
3732 return -ENODEV;
3733 if (addr >= 24)
3734 return -ENODEV;
3735
3736 pr_debug("%s: id: %d\n", __func__, addr);
3737 /* All base addresses of the PHYs start at multiples of 8 */
3738 devm_phy_package_join(dev, phydev, addr & (~7),
3739 sizeof(struct rtl83xx_shared_private));
3740
3741 if (!(addr % 8)) {
3742 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3743 shared->name = "RTL8218B (internal)";
3744 /* Configuration must be done while patching still possible */
3745 return rtl8380_configure_int_rtl8218b(phydev);
3746 }
3747
3748 return 0;
3749 }
3750
3751 static int rtl8218d_phy_probe(struct phy_device *phydev)
3752 {
3753 struct device *dev = &phydev->mdio.dev;
3754 int addr = phydev->mdio.addr;
3755
3756 pr_debug("%s: id: %d\n", __func__, addr);
3757 /* All base addresses of the PHYs start at multiples of 8 */
3758 devm_phy_package_join(dev, phydev, addr & (~7),
3759 sizeof(struct rtl83xx_shared_private));
3760
3761 /* All base addresses of the PHYs start at multiples of 8 */
3762 if (!(addr % 8)) {
3763 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3764 shared->name = "RTL8218D";
3765 /* Configuration must be done while patching still possible */
3766 // TODO: return configure_rtl8218d(phydev);
3767 }
3768 return 0;
3769 }
3770
3771 static int rtl838x_serdes_probe(struct phy_device *phydev)
3772 {
3773 int addr = phydev->mdio.addr;
3774
3775 if (soc_info.family != RTL8380_FAMILY_ID)
3776 return -ENODEV;
3777 if (addr < 24)
3778 return -ENODEV;
3779
3780 /* On the RTL8380M, PHYs 24-27 connect to the internal SerDes */
3781 if (soc_info.id == 0x8380) {
3782 if (addr == 24)
3783 return rtl8380_configure_serdes(phydev);
3784 return 0;
3785 }
3786 return -ENODEV;
3787 }
3788
3789 static int rtl8393_serdes_probe(struct phy_device *phydev)
3790 {
3791 int addr = phydev->mdio.addr;
3792
3793 pr_info("%s: id: %d\n", __func__, addr);
3794 if (soc_info.family != RTL8390_FAMILY_ID)
3795 return -ENODEV;
3796
3797 if (addr < 24)
3798 return -ENODEV;
3799
3800 return rtl8390_configure_serdes(phydev);
3801 }
3802
3803 static int rtl8390_serdes_probe(struct phy_device *phydev)
3804 {
3805 int addr = phydev->mdio.addr;
3806
3807 if (soc_info.family != RTL8390_FAMILY_ID)
3808 return -ENODEV;
3809
3810 if (addr < 24)
3811 return -ENODEV;
3812
3813 return rtl8390_configure_generic(phydev);
3814 }
3815
3816 static int rtl9300_serdes_probe(struct phy_device *phydev)
3817 {
3818 if (soc_info.family != RTL9300_FAMILY_ID)
3819 return -ENODEV;
3820
3821 phydev_info(phydev, "Detected internal RTL9300 Serdes\n");
3822
3823 return rtl9300_configure_serdes(phydev);
3824 }
3825
3826 static struct phy_driver rtl83xx_phy_driver[] = {
3827 {
3828 PHY_ID_MATCH_MODEL(PHY_ID_RTL8214C),
3829 .name = "Realtek RTL8214C",
3830 .features = PHY_GBIT_FEATURES,
3831 .flags = PHY_HAS_REALTEK_PAGES,
3832 .match_phy_device = rtl8214c_match_phy_device,
3833 .probe = rtl8214c_phy_probe,
3834 .suspend = genphy_suspend,
3835 .resume = genphy_resume,
3836 .set_loopback = genphy_loopback,
3837 },
3838 {
3839 PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC),
3840 .name = "Realtek RTL8214FC",
3841 .features = PHY_GBIT_FIBRE_FEATURES,
3842 .flags = PHY_HAS_REALTEK_PAGES,
3843 .match_phy_device = rtl8214fc_match_phy_device,
3844 .probe = rtl8214fc_phy_probe,
3845 .suspend = genphy_suspend,
3846 .resume = genphy_resume,
3847 .set_loopback = genphy_loopback,
3848 .set_port = rtl8214fc_set_port,
3849 .get_port = rtl8214fc_get_port,
3850 .set_eee = rtl8214fc_set_eee,
3851 .get_eee = rtl8214fc_get_eee,
3852 },
3853 {
3854 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_E),
3855 .name = "Realtek RTL8218B (external)",
3856 .features = PHY_GBIT_FEATURES,
3857 .flags = PHY_HAS_REALTEK_PAGES,
3858 .match_phy_device = rtl8218b_ext_match_phy_device,
3859 .probe = rtl8218b_ext_phy_probe,
3860 .suspend = genphy_suspend,
3861 .resume = genphy_resume,
3862 .set_loopback = genphy_loopback,
3863 .set_eee = rtl8218b_set_eee,
3864 .get_eee = rtl8218b_get_eee,
3865 },
3866 {
3867 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218D),
3868 .name = "REALTEK RTL8218D",
3869 .features = PHY_GBIT_FEATURES,
3870 .flags = PHY_HAS_REALTEK_PAGES,
3871 .probe = rtl8218d_phy_probe,
3872 .suspend = genphy_suspend,
3873 .resume = genphy_resume,
3874 .set_loopback = genphy_loopback,
3875 .set_eee = rtl8218d_set_eee,
3876 .get_eee = rtl8218d_get_eee,
3877 },
3878 {
3879 PHY_ID_MATCH_MODEL(PHY_ID_RTL8221B),
3880 .name = "REALTEK RTL8221B",
3881 .features = PHY_GBIT_FEATURES,
3882 .flags = PHY_HAS_REALTEK_PAGES,
3883 .suspend = genphy_suspend,
3884 .resume = genphy_resume,
3885 .set_loopback = genphy_loopback,
3886 .read_page = rtl8226_read_page,
3887 .write_page = rtl8226_write_page,
3888 .read_status = rtl8226_read_status,
3889 .config_aneg = rtl8226_config_aneg,
3890 .set_eee = rtl8226_set_eee,
3891 .get_eee = rtl8226_get_eee,
3892 },
3893 {
3894 PHY_ID_MATCH_MODEL(PHY_ID_RTL8226),
3895 .name = "REALTEK RTL8226",
3896 .features = PHY_GBIT_FEATURES,
3897 .flags = PHY_HAS_REALTEK_PAGES,
3898 .suspend = genphy_suspend,
3899 .resume = genphy_resume,
3900 .set_loopback = genphy_loopback,
3901 .read_page = rtl8226_read_page,
3902 .write_page = rtl8226_write_page,
3903 .read_status = rtl8226_read_status,
3904 .config_aneg = rtl8226_config_aneg,
3905 .set_eee = rtl8226_set_eee,
3906 .get_eee = rtl8226_get_eee,
3907 },
3908 {
3909 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I),
3910 .name = "Realtek RTL8218B (internal)",
3911 .features = PHY_GBIT_FEATURES,
3912 .flags = PHY_HAS_REALTEK_PAGES,
3913 .probe = rtl8218b_int_phy_probe,
3914 .suspend = genphy_suspend,
3915 .resume = genphy_resume,
3916 .set_loopback = genphy_loopback,
3917 .set_eee = rtl8218b_set_eee,
3918 .get_eee = rtl8218b_get_eee,
3919 },
3920 {
3921 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I),
3922 .name = "Realtek RTL8380 SERDES",
3923 .features = PHY_GBIT_FIBRE_FEATURES,
3924 .flags = PHY_HAS_REALTEK_PAGES,
3925 .probe = rtl838x_serdes_probe,
3926 .suspend = genphy_suspend,
3927 .resume = genphy_resume,
3928 .set_loopback = genphy_loopback,
3929 .read_status = rtl8380_read_status,
3930 },
3931 {
3932 PHY_ID_MATCH_MODEL(PHY_ID_RTL8393_I),
3933 .name = "Realtek RTL8393 SERDES",
3934 .features = PHY_GBIT_FIBRE_FEATURES,
3935 .flags = PHY_HAS_REALTEK_PAGES,
3936 .probe = rtl8393_serdes_probe,
3937 .suspend = genphy_suspend,
3938 .resume = genphy_resume,
3939 .set_loopback = genphy_loopback,
3940 .read_status = rtl8393_read_status,
3941 },
3942 {
3943 PHY_ID_MATCH_MODEL(PHY_ID_RTL8390_GENERIC),
3944 .name = "Realtek RTL8390 Generic",
3945 .features = PHY_GBIT_FIBRE_FEATURES,
3946 .flags = PHY_HAS_REALTEK_PAGES,
3947 .probe = rtl8390_serdes_probe,
3948 .suspend = genphy_suspend,
3949 .resume = genphy_resume,
3950 .set_loopback = genphy_loopback,
3951 },
3952 {
3953 PHY_ID_MATCH_MODEL(PHY_ID_RTL9300_I),
3954 .name = "REALTEK RTL9300 SERDES",
3955 .features = PHY_GBIT_FIBRE_FEATURES,
3956 .flags = PHY_HAS_REALTEK_PAGES,
3957 .probe = rtl9300_serdes_probe,
3958 .suspend = genphy_suspend,
3959 .resume = genphy_resume,
3960 .set_loopback = genphy_loopback,
3961 .read_status = rtl9300_read_status,
3962 },
3963 };
3964
3965 module_phy_driver(rtl83xx_phy_driver);
3966
3967 static struct mdio_device_id __maybe_unused rtl83xx_tbl[] = {
3968 { PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC) },
3969 { }
3970 };
3971
3972 MODULE_DEVICE_TABLE(mdio, rtl83xx_tbl);
3973
3974 MODULE_AUTHOR("B. Koblitz");
3975 MODULE_DESCRIPTION("RTL83xx PHY driver");
3976 MODULE_LICENSE("GPL");
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