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[openwrt/staging/stintel.git] / target / linux / ramips / patches-6.6 / 005-v6.5-06-mips-ralink-mt7620-remove-clock-related-code.patch
1 From 04b153abdfcbaba70ceef5a846067d4447fd0078 Mon Sep 17 00:00:00 2001
2 From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
3 Date: Mon, 19 Jun 2023 06:09:38 +0200
4 Subject: [PATCH 6/9] mips: ralink: mt7620: remove clock related code
5
6 A proper clock driver for ralink SoCs has been added. Hence there is no
7 need to have clock related code in 'arch/mips/ralink' folder anymore.
8 Since this is the last clock related code removal, remove also remaining
9 prototypes in 'common.h' header file.
10
11 Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
12 Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
13 ---
14 arch/mips/include/asm/mach-ralink/mt7620.h | 35 -----
15 arch/mips/ralink/common.h | 3 -
16 arch/mips/ralink/mt7620.c | 226 -----------------------------
17 3 files changed, 264 deletions(-)
18
19 --- a/arch/mips/include/asm/mach-ralink/mt7620.h
20 +++ b/arch/mips/include/asm/mach-ralink/mt7620.h
21 @@ -19,52 +19,17 @@
22 #define SYSC_REG_CHIP_REV 0x0c
23 #define SYSC_REG_SYSTEM_CONFIG0 0x10
24 #define SYSC_REG_SYSTEM_CONFIG1 0x14
25 -#define SYSC_REG_CLKCFG0 0x2c
26 -#define SYSC_REG_CPU_SYS_CLKCFG 0x3c
27 -#define SYSC_REG_CPLL_CONFIG0 0x54
28 -#define SYSC_REG_CPLL_CONFIG1 0x58
29
30 #define MT7620_CHIP_NAME0 0x3637544d
31 #define MT7620_CHIP_NAME1 0x20203032
32 #define MT7628_CHIP_NAME1 0x20203832
33
34 -#define SYSCFG0_XTAL_FREQ_SEL BIT(6)
35 -
36 #define CHIP_REV_PKG_MASK 0x1
37 #define CHIP_REV_PKG_SHIFT 16
38 #define CHIP_REV_VER_MASK 0xf
39 #define CHIP_REV_VER_SHIFT 8
40 #define CHIP_REV_ECO_MASK 0xf
41
42 -#define CLKCFG0_PERI_CLK_SEL BIT(4)
43 -
44 -#define CPU_SYS_CLKCFG_OCP_RATIO_SHIFT 16
45 -#define CPU_SYS_CLKCFG_OCP_RATIO_MASK 0xf
46 -#define CPU_SYS_CLKCFG_OCP_RATIO_1 0 /* 1:1 (Reserved) */
47 -#define CPU_SYS_CLKCFG_OCP_RATIO_1_5 1 /* 1:1.5 (Reserved) */
48 -#define CPU_SYS_CLKCFG_OCP_RATIO_2 2 /* 1:2 */
49 -#define CPU_SYS_CLKCFG_OCP_RATIO_2_5 3 /* 1:2.5 (Reserved) */
50 -#define CPU_SYS_CLKCFG_OCP_RATIO_3 4 /* 1:3 */
51 -#define CPU_SYS_CLKCFG_OCP_RATIO_3_5 5 /* 1:3.5 (Reserved) */
52 -#define CPU_SYS_CLKCFG_OCP_RATIO_4 6 /* 1:4 */
53 -#define CPU_SYS_CLKCFG_OCP_RATIO_5 7 /* 1:5 */
54 -#define CPU_SYS_CLKCFG_OCP_RATIO_10 8 /* 1:10 */
55 -#define CPU_SYS_CLKCFG_CPU_FDIV_SHIFT 8
56 -#define CPU_SYS_CLKCFG_CPU_FDIV_MASK 0x1f
57 -#define CPU_SYS_CLKCFG_CPU_FFRAC_SHIFT 0
58 -#define CPU_SYS_CLKCFG_CPU_FFRAC_MASK 0x1f
59 -
60 -#define CPLL_CFG0_SW_CFG BIT(31)
61 -#define CPLL_CFG0_PLL_MULT_RATIO_SHIFT 16
62 -#define CPLL_CFG0_PLL_MULT_RATIO_MASK 0x7
63 -#define CPLL_CFG0_LC_CURFCK BIT(15)
64 -#define CPLL_CFG0_BYPASS_REF_CLK BIT(14)
65 -#define CPLL_CFG0_PLL_DIV_RATIO_SHIFT 10
66 -#define CPLL_CFG0_PLL_DIV_RATIO_MASK 0x3
67 -
68 -#define CPLL_CFG1_CPU_AUX1 BIT(25)
69 -#define CPLL_CFG1_CPU_AUX0 BIT(24)
70 -
71 #define SYSCFG0_DRAM_TYPE_MASK 0x3
72 #define SYSCFG0_DRAM_TYPE_SHIFT 4
73 #define SYSCFG0_DRAM_TYPE_SDRAM 0
74 --- a/arch/mips/ralink/common.h
75 +++ b/arch/mips/ralink/common.h
76 @@ -23,9 +23,6 @@ extern struct ralink_soc_info soc_info;
77
78 extern void ralink_of_remap(void);
79
80 -extern void ralink_clk_init(void);
81 -extern void ralink_clk_add(const char *dev, unsigned long rate);
82 -
83 extern void ralink_rst_init(void);
84
85 extern void __init prom_soc_init(struct ralink_soc_info *soc_info);
86 --- a/arch/mips/ralink/mt7620.c
87 +++ b/arch/mips/ralink/mt7620.c
88 @@ -34,12 +34,6 @@
89 #define PMU1_CFG 0x8C
90 #define DIG_SW_SEL BIT(25)
91
92 -/* clock scaling */
93 -#define CLKCFG_FDIV_MASK 0x1f00
94 -#define CLKCFG_FDIV_USB_VAL 0x0300
95 -#define CLKCFG_FFRAC_MASK 0x001f
96 -#define CLKCFG_FFRAC_USB_VAL 0x0003
97 -
98 /* EFUSE bits */
99 #define EFUSE_MT7688 0x100000
100
101 @@ -49,226 +43,6 @@
102 /* does the board have sdram or ddram */
103 static int dram_type;
104
105 -static __init u32
106 -mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div)
107 -{
108 - u64 t;
109 -
110 - t = ref_rate;
111 - t *= mul;
112 - do_div(t, div);
113 -
114 - return t;
115 -}
116 -
117 -#define MHZ(x) ((x) * 1000 * 1000)
118 -
119 -static __init unsigned long
120 -mt7620_get_xtal_rate(void)
121 -{
122 - u32 reg;
123 -
124 - reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
125 - if (reg & SYSCFG0_XTAL_FREQ_SEL)
126 - return MHZ(40);
127 -
128 - return MHZ(20);
129 -}
130 -
131 -static __init unsigned long
132 -mt7620_get_periph_rate(unsigned long xtal_rate)
133 -{
134 - u32 reg;
135 -
136 - reg = rt_sysc_r32(SYSC_REG_CLKCFG0);
137 - if (reg & CLKCFG0_PERI_CLK_SEL)
138 - return xtal_rate;
139 -
140 - return MHZ(40);
141 -}
142 -
143 -static const u32 mt7620_clk_divider[] __initconst = { 2, 3, 4, 8 };
144 -
145 -static __init unsigned long
146 -mt7620_get_cpu_pll_rate(unsigned long xtal_rate)
147 -{
148 - u32 reg;
149 - u32 mul;
150 - u32 div;
151 -
152 - reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG0);
153 - if (reg & CPLL_CFG0_BYPASS_REF_CLK)
154 - return xtal_rate;
155 -
156 - if ((reg & CPLL_CFG0_SW_CFG) == 0)
157 - return MHZ(600);
158 -
159 - mul = (reg >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) &
160 - CPLL_CFG0_PLL_MULT_RATIO_MASK;
161 - mul += 24;
162 - if (reg & CPLL_CFG0_LC_CURFCK)
163 - mul *= 2;
164 -
165 - div = (reg >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) &
166 - CPLL_CFG0_PLL_DIV_RATIO_MASK;
167 -
168 - WARN_ON(div >= ARRAY_SIZE(mt7620_clk_divider));
169 -
170 - return mt7620_calc_rate(xtal_rate, mul, mt7620_clk_divider[div]);
171 -}
172 -
173 -static __init unsigned long
174 -mt7620_get_pll_rate(unsigned long xtal_rate, unsigned long cpu_pll_rate)
175 -{
176 - u32 reg;
177 -
178 - reg = rt_sysc_r32(SYSC_REG_CPLL_CONFIG1);
179 - if (reg & CPLL_CFG1_CPU_AUX1)
180 - return xtal_rate;
181 -
182 - if (reg & CPLL_CFG1_CPU_AUX0)
183 - return MHZ(480);
184 -
185 - return cpu_pll_rate;
186 -}
187 -
188 -static __init unsigned long
189 -mt7620_get_cpu_rate(unsigned long pll_rate)
190 -{
191 - u32 reg;
192 - u32 mul;
193 - u32 div;
194 -
195 - reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
196 -
197 - mul = reg & CPU_SYS_CLKCFG_CPU_FFRAC_MASK;
198 - div = (reg >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) &
199 - CPU_SYS_CLKCFG_CPU_FDIV_MASK;
200 -
201 - return mt7620_calc_rate(pll_rate, mul, div);
202 -}
203 -
204 -static const u32 mt7620_ocp_dividers[16] __initconst = {
205 - [CPU_SYS_CLKCFG_OCP_RATIO_2] = 2,
206 - [CPU_SYS_CLKCFG_OCP_RATIO_3] = 3,
207 - [CPU_SYS_CLKCFG_OCP_RATIO_4] = 4,
208 - [CPU_SYS_CLKCFG_OCP_RATIO_5] = 5,
209 - [CPU_SYS_CLKCFG_OCP_RATIO_10] = 10,
210 -};
211 -
212 -static __init unsigned long
213 -mt7620_get_dram_rate(unsigned long pll_rate)
214 -{
215 - if (dram_type == SYSCFG0_DRAM_TYPE_SDRAM)
216 - return pll_rate / 4;
217 -
218 - return pll_rate / 3;
219 -}
220 -
221 -static __init unsigned long
222 -mt7620_get_sys_rate(unsigned long cpu_rate)
223 -{
224 - u32 reg;
225 - u32 ocp_ratio;
226 - u32 div;
227 -
228 - reg = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
229 -
230 - ocp_ratio = (reg >> CPU_SYS_CLKCFG_OCP_RATIO_SHIFT) &
231 - CPU_SYS_CLKCFG_OCP_RATIO_MASK;
232 -
233 - if (WARN_ON(ocp_ratio >= ARRAY_SIZE(mt7620_ocp_dividers)))
234 - return cpu_rate;
235 -
236 - div = mt7620_ocp_dividers[ocp_ratio];
237 - if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio))
238 - return cpu_rate;
239 -
240 - return cpu_rate / div;
241 -}
242 -
243 -void __init ralink_clk_init(void)
244 -{
245 - unsigned long xtal_rate;
246 - unsigned long cpu_pll_rate;
247 - unsigned long pll_rate;
248 - unsigned long cpu_rate;
249 - unsigned long sys_rate;
250 - unsigned long dram_rate;
251 - unsigned long periph_rate;
252 - unsigned long pcmi2s_rate;
253 -
254 - xtal_rate = mt7620_get_xtal_rate();
255 -
256 -#define RFMT(label) label ":%lu.%03luMHz "
257 -#define RINT(x) ((x) / 1000000)
258 -#define RFRAC(x) (((x) / 1000) % 1000)
259 -
260 - if (is_mt76x8()) {
261 - if (xtal_rate == MHZ(40))
262 - cpu_rate = MHZ(580);
263 - else
264 - cpu_rate = MHZ(575);
265 - dram_rate = sys_rate = cpu_rate / 3;
266 - periph_rate = MHZ(40);
267 - pcmi2s_rate = MHZ(480);
268 -
269 - ralink_clk_add("10000d00.uartlite", periph_rate);
270 - ralink_clk_add("10000e00.uartlite", periph_rate);
271 - } else {
272 - cpu_pll_rate = mt7620_get_cpu_pll_rate(xtal_rate);
273 - pll_rate = mt7620_get_pll_rate(xtal_rate, cpu_pll_rate);
274 -
275 - cpu_rate = mt7620_get_cpu_rate(pll_rate);
276 - dram_rate = mt7620_get_dram_rate(pll_rate);
277 - sys_rate = mt7620_get_sys_rate(cpu_rate);
278 - periph_rate = mt7620_get_periph_rate(xtal_rate);
279 - pcmi2s_rate = periph_rate;
280 -
281 - pr_debug(RFMT("XTAL") RFMT("CPU_PLL") RFMT("PLL"),
282 - RINT(xtal_rate), RFRAC(xtal_rate),
283 - RINT(cpu_pll_rate), RFRAC(cpu_pll_rate),
284 - RINT(pll_rate), RFRAC(pll_rate));
285 -
286 - ralink_clk_add("10000500.uart", periph_rate);
287 - }
288 -
289 - pr_debug(RFMT("CPU") RFMT("DRAM") RFMT("SYS") RFMT("PERIPH"),
290 - RINT(cpu_rate), RFRAC(cpu_rate),
291 - RINT(dram_rate), RFRAC(dram_rate),
292 - RINT(sys_rate), RFRAC(sys_rate),
293 - RINT(periph_rate), RFRAC(periph_rate));
294 -#undef RFRAC
295 -#undef RINT
296 -#undef RFMT
297 -
298 - ralink_clk_add("cpu", cpu_rate);
299 - ralink_clk_add("10000100.timer", periph_rate);
300 - ralink_clk_add("10000120.watchdog", periph_rate);
301 - ralink_clk_add("10000900.i2c", periph_rate);
302 - ralink_clk_add("10000a00.i2s", pcmi2s_rate);
303 - ralink_clk_add("10000b00.spi", sys_rate);
304 - ralink_clk_add("10000b40.spi", sys_rate);
305 - ralink_clk_add("10000c00.uartlite", periph_rate);
306 - ralink_clk_add("10000d00.uart1", periph_rate);
307 - ralink_clk_add("10000e00.uart2", periph_rate);
308 - ralink_clk_add("10180000.wmac", xtal_rate);
309 -
310 - if (IS_ENABLED(CONFIG_USB) && !is_mt76x8()) {
311 - /*
312 - * When the CPU goes into sleep mode, the BUS clock will be
313 - * too low for USB to function properly. Adjust the busses
314 - * fractional divider to fix this
315 - */
316 - u32 val = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
317 -
318 - val &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK);
319 - val |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL;
320 -
321 - rt_sysc_w32(val, SYSC_REG_CPU_SYS_CLKCFG);
322 - }
323 -}
324 -
325 void __init ralink_of_remap(void)
326 {
327 rt_sysc_membase = plat_of_remap_node("ralink,mt7620a-sysc");
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