target/linux/ramips/patches-6.6/005-v6.5-04-mips-ralink-rt305x-remove-clock-related-code.patch

   1 From daf73c70f69386fb15960526772ef584a4efcaf2 Mon Sep 17 00:00:00 2001
   2 From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
   3 Date: Mon, 19 Jun 2023 06:09:36 +0200
   4 Subject: [PATCH 4/9] mips: ralink: rt305x: remove clock related code
   5
   6 A properly clock driver for ralink SoCs has been added. Hence there is no
   7 need to have clock related code in 'arch/mips/ralink' folder anymore.
   8
   9 Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
  10 Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
  11 ---
  12  arch/mips/include/asm/mach-ralink/rt305x.h | 21 --------
  13  arch/mips/ralink/rt305x.c                  | 78 ------------------------------
  14  2 files changed, 99 deletions(-)
  15
  16 --- a/arch/mips/include/asm/mach-ralink/rt305x.h
  17 +++ b/arch/mips/include/asm/mach-ralink/rt305x.h
  18 @@ -66,26 +66,9 @@ static inline int soc_is_rt5350(void)
  19  #define CHIP_ID_ID_SHIFT               8
  20  #define CHIP_ID_REV_MASK               0xff
  21
  22 -#define RT305X_SYSCFG_CPUCLK_SHIFT             18
  23 -#define RT305X_SYSCFG_CPUCLK_MASK              0x1
  24 -#define RT305X_SYSCFG_CPUCLK_LOW               0x0
  25 -#define RT305X_SYSCFG_CPUCLK_HIGH              0x1
  26 -
  27  #define RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT      2
  28 -#define RT305X_SYSCFG_CPUCLK_MASK              0x1
  29  #define RT305X_SYSCFG_SRAM_CS0_MODE_WDT                0x1
  30
  31 -#define RT3352_SYSCFG0_CPUCLK_SHIFT    8
  32 -#define RT3352_SYSCFG0_CPUCLK_MASK     0x1
  33 -#define RT3352_SYSCFG0_CPUCLK_LOW      0x0
  34 -#define RT3352_SYSCFG0_CPUCLK_HIGH     0x1
  35 -
  36 -#define RT5350_SYSCFG0_CPUCLK_SHIFT    8
  37 -#define RT5350_SYSCFG0_CPUCLK_MASK     0x3
  38 -#define RT5350_SYSCFG0_CPUCLK_360      0x0
  39 -#define RT5350_SYSCFG0_CPUCLK_320      0x2
  40 -#define RT5350_SYSCFG0_CPUCLK_300      0x3
  41 -
  42  #define RT5350_SYSCFG0_DRAM_SIZE_SHIFT  12
  43  #define RT5350_SYSCFG0_DRAM_SIZE_MASK   7
  44  #define RT5350_SYSCFG0_DRAM_SIZE_2M     0
  45 @@ -116,13 +99,9 @@ static inline int soc_is_rt5350(void)
  46
  47  #define RT3352_SYSC_REG_SYSCFG0                0x010
  48  #define RT3352_SYSC_REG_SYSCFG1         0x014
  49 -#define RT3352_SYSC_REG_CLKCFG1         0x030
  50  #define RT3352_SYSC_REG_RSTCTRL         0x034
  51  #define RT3352_SYSC_REG_USB_PS          0x05c
  52
  53 -#define RT3352_CLKCFG0_XTAL_SEL                BIT(20)
  54 -#define RT3352_CLKCFG1_UPHY0_CLK_EN    BIT(18)
  55 -#define RT3352_CLKCFG1_UPHY1_CLK_EN    BIT(20)
  56  #define RT3352_RSTCTRL_UHST            BIT(22)
  57  #define RT3352_RSTCTRL_UDEV            BIT(25)
  58  #define RT3352_SYSCFG1_USB0_HOST_MODE  BIT(10)
  59 --- a/arch/mips/ralink/rt305x.c
  60 +++ b/arch/mips/ralink/rt305x.c
  61 @@ -53,84 +53,6 @@ static unsigned long rt5350_get_mem_size
  62         return ret;
  63  }
  64
  65 -void __init ralink_clk_init(void)
  66 -{
  67 -       unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate;
  68 -       unsigned long wmac_rate = 40000000;
  69 -
  70 -       u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
  71 -
  72 -       if (soc_is_rt305x() || soc_is_rt3350()) {
  73 -               t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) &
  74 -                    RT305X_SYSCFG_CPUCLK_MASK;
  75 -               switch (t) {
  76 -               case RT305X_SYSCFG_CPUCLK_LOW:
  77 -                       cpu_rate = 320000000;
  78 -                       break;
  79 -               case RT305X_SYSCFG_CPUCLK_HIGH:
  80 -                       cpu_rate = 384000000;
  81 -                       break;
  82 -               }
  83 -               sys_rate = uart_rate = wdt_rate = cpu_rate / 3;
  84 -       } else if (soc_is_rt3352()) {
  85 -               t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) &
  86 -                    RT3352_SYSCFG0_CPUCLK_MASK;
  87 -               switch (t) {
  88 -               case RT3352_SYSCFG0_CPUCLK_LOW:
  89 -                       cpu_rate = 384000000;
  90 -                       break;
  91 -               case RT3352_SYSCFG0_CPUCLK_HIGH:
  92 -                       cpu_rate = 400000000;
  93 -                       break;
  94 -               }
  95 -               sys_rate = wdt_rate = cpu_rate / 3;
  96 -               uart_rate = 40000000;
  97 -       } else if (soc_is_rt5350()) {
  98 -               t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) &
  99 -                    RT5350_SYSCFG0_CPUCLK_MASK;
 100 -               switch (t) {
 101 -               case RT5350_SYSCFG0_CPUCLK_360:
 102 -                       cpu_rate = 360000000;
 103 -                       sys_rate = cpu_rate / 3;
 104 -                       break;
 105 -               case RT5350_SYSCFG0_CPUCLK_320:
 106 -                       cpu_rate = 320000000;
 107 -                       sys_rate = cpu_rate / 4;
 108 -                       break;
 109 -               case RT5350_SYSCFG0_CPUCLK_300:
 110 -                       cpu_rate = 300000000;
 111 -                       sys_rate = cpu_rate / 3;
 112 -                       break;
 113 -               default:
 114 -                       BUG();
 115 -               }
 116 -               uart_rate = 40000000;
 117 -               wdt_rate = sys_rate;
 118 -       } else {
 119 -               BUG();
 120 -       }
 121 -
 122 -       if (soc_is_rt3352() || soc_is_rt5350()) {
 123 -               u32 val = rt_sysc_r32(RT3352_SYSC_REG_SYSCFG0);
 124 -
 125 -               if (!(val & RT3352_CLKCFG0_XTAL_SEL))
 126 -                       wmac_rate = 20000000;
 127 -       }
 128 -
 129 -       ralink_clk_add("cpu", cpu_rate);
 130 -       ralink_clk_add("sys", sys_rate);
 131 -       ralink_clk_add("10000900.i2c", uart_rate);
 132 -       ralink_clk_add("10000a00.i2s", uart_rate);
 133 -       ralink_clk_add("10000b00.spi", sys_rate);
 134 -       ralink_clk_add("10000b40.spi", sys_rate);
 135 -       ralink_clk_add("10000100.timer", wdt_rate);
 136 -       ralink_clk_add("10000120.watchdog", wdt_rate);
 137 -       ralink_clk_add("10000500.uart", uart_rate);
 138 -       ralink_clk_add("10000c00.uartlite", uart_rate);
 139 -       ralink_clk_add("10100000.ethernet", sys_rate);
 140 -       ralink_clk_add("10180000.wmac", wmac_rate);
 141 -}
 142 -
 143  void __init ralink_of_remap(void)
 144  {
 145         rt_sysc_membase = plat_of_remap_node("ralink,rt3050-sysc");