target/linux/ramips/patches-6.6/003-v6.3-clk-ralink-fix-mt7621_gate_is_enabled-function.patch

   1 From 35dcae535afc153fa83f2fe51c0812536c192c58 Mon Sep 17 00:00:00 2001
   2 From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
   3 Date: Mon, 6 Feb 2023 09:33:05 +0100
   4 Subject: [PATCH] clk: ralink: fix 'mt7621_gate_is_enabled()' function
   5
   6 Compiling clock driver with CONFIG_UBSAN enabled shows the following trace:
   7
   8 UBSAN: shift-out-of-bounds in drivers/clk/ralink/clk-mt7621.c:121:15
   9 shift exponent 131072 is too large for 32-bit type 'long unsigned int'
  10 CPU: 1 PID: 1 Comm: swapper/0 Not tainted 5.15.86 #0
  11 Stack : ...
  12
  13 Call Trace:
  14 [<80009a58>] show_stack+0x38/0x118
  15 [<8045ce04>] dump_stack_lvl+0x60/0x80
  16 [<80458868>] ubsan_epilogue+0x10/0x54
  17 [<804590e0>] __ubsan_handle_shift_out_of_bounds+0x118/0x190
  18 [<804c9a10>] mt7621_gate_is_enabled+0x98/0xa0
  19 [<804bb774>] clk_core_is_enabled+0x34/0x90
  20 [<80aad73c>] clk_disable_unused_subtree+0x98/0x1e4
  21 [<80aad6d4>] clk_disable_unused_subtree+0x30/0x1e4
  22 [<80aad6d4>] clk_disable_unused_subtree+0x30/0x1e4
  23 [<80aad900>] clk_disable_unused+0x78/0x120
  24 [<80002030>] do_one_initcall+0x54/0x1f0
  25 [<80a922a4>] kernel_init_freeable+0x280/0x31c
  26 [<808047c4>] kernel_init+0x20/0x118
  27 [<80003e58>] ret_from_kernel_thread+0x14/0x1c
  28
  29 Shifting a value (131032) larger than the type (32 bit unsigned integer)
  30 is undefined behaviour in C.
  31
  32 The problem is in 'mt7621_gate_is_enabled()' function which is using the
  33 'BIT()' kernel macro with the bit index for the clock gate to check if the
  34 bit is set. When the clock gates structure is created driver is already
  35 setting 'bit_idx' using 'BIT()' macro, so we are wrongly applying an extra
  36 'BIT()' mask here. Removing it solve the problem and makes this function
  37 correct. However when clock gating is correctly working, the kernel starts
  38 disabling those clocks that are not requested. Some drivers for this SoC
  39 are older than this clock driver itself. So to avoid the kernel to disable
  40 clocks that have been enabled until now, we must apply 'CLK_IS_CRITICAL'
  41 flag on gates initialization code.
  42
  43 Fixes: 48df7a26f470 ("clk: ralink: add clock driver for mt7621 SoC")
  44 Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
  45 Link: https://lore.kernel.org/r/20230206083305.147582-1-sergio.paracuellos@gmail.com
  46 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
  47 ---
  48  drivers/clk/ralink/clk-mt7621.c | 10 ++++++++--
  49  1 file changed, 8 insertions(+), 2 deletions(-)
  50
  51 --- a/drivers/clk/ralink/clk-mt7621.c
  52 +++ b/drivers/clk/ralink/clk-mt7621.c
  53 @@ -121,7 +121,7 @@ static int mt7621_gate_is_enabled(struct
  54         if (regmap_read(sysc, SYSC_REG_CLKCFG1, &val))
  55                 return 0;
  56
  57 -       return val & BIT(clk_gate->bit_idx);
  58 +       return val & clk_gate->bit_idx;
  59  }
  60
  61  static const struct clk_ops mt7621_gate_ops = {
  62 @@ -133,8 +133,14 @@ static const struct clk_ops mt7621_gate_
  63  static int mt7621_gate_ops_init(struct device *dev,
  64                                 struct mt7621_gate *sclk)
  65  {
  66 +       /*
  67 +        * There are drivers for this SoC that are older
  68 +        * than clock driver and are not prepared for the clock.
  69 +        * We don't want the kernel to disable anything so we
  70 +        * add CLK_IS_CRITICAL flag here.
  71 +        */
  72         struct clk_init_data init = {
  73 -               .flags = CLK_SET_RATE_PARENT,
  74 +               .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
  75                 .num_parents = 1,
  76                 .parent_names = &sclk->parent_name,
  77                 .ops = &mt7621_gate_ops,