target/linux/ramips/patches-5.15/005-v6.5-03-mips-ralink-rt288x-remove-clock-related-code.patch

   1 From ffcdf47379eae86dc8f8f02c62994dacf2c9038e Mon Sep 17 00:00:00 2001
   2 From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
   3 Date: Mon, 19 Jun 2023 06:09:35 +0200
   4 Subject: [PATCH 3/9] mips: ralink: rt288x: remove clock related code
   5
   6 A properly clock driver for ralink SoCs has been added. Hence there is no
   7 need to have clock related code in 'arch/mips/ralink' folder anymore.
   8
   9 Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
  10 Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
  11 ---
  12  arch/mips/include/asm/mach-ralink/rt288x.h | 10 ----------
  13  arch/mips/ralink/rt288x.c                  | 31 ------------------------------
  14  2 files changed, 41 deletions(-)
  15
  16 --- a/arch/mips/include/asm/mach-ralink/rt288x.h
  17 +++ b/arch/mips/include/asm/mach-ralink/rt288x.h
  18 @@ -17,7 +17,6 @@
  19  #define SYSC_REG_CHIP_NAME1            0x04
  20  #define SYSC_REG_CHIP_ID               0x0c
  21  #define SYSC_REG_SYSTEM_CONFIG         0x10
  22 -#define SYSC_REG_CLKCFG                        0x30
  23
  24  #define RT2880_CHIP_NAME0              0x38325452
  25  #define RT2880_CHIP_NAME1              0x20203038
  26 @@ -26,15 +25,6 @@
  27  #define CHIP_ID_ID_SHIFT               8
  28  #define CHIP_ID_REV_MASK               0xff
  29
  30 -#define SYSTEM_CONFIG_CPUCLK_SHIFT     20
  31 -#define SYSTEM_CONFIG_CPUCLK_MASK      0x3
  32 -#define SYSTEM_CONFIG_CPUCLK_250       0x0
  33 -#define SYSTEM_CONFIG_CPUCLK_266       0x1
  34 -#define SYSTEM_CONFIG_CPUCLK_280       0x2
  35 -#define SYSTEM_CONFIG_CPUCLK_300       0x3
  36 -
  37 -#define CLKCFG_SRAM_CS_N_WDT           BIT(9)
  38 -
  39  #define RT2880_SDRAM_BASE              0x08000000
  40  #define RT2880_MEM_SIZE_MIN            2
  41  #define RT2880_MEM_SIZE_MAX            128
  42 --- a/arch/mips/ralink/rt288x.c
  43 +++ b/arch/mips/ralink/rt288x.c
  44 @@ -17,37 +17,6 @@
  45
  46  #include "common.h"
  47
  48 -void __init ralink_clk_init(void)
  49 -{
  50 -       unsigned long cpu_rate, wmac_rate = 40000000;
  51 -       u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
  52 -       t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK);
  53 -
  54 -       switch (t) {
  55 -       case SYSTEM_CONFIG_CPUCLK_250:
  56 -               cpu_rate = 250000000;
  57 -               break;
  58 -       case SYSTEM_CONFIG_CPUCLK_266:
  59 -               cpu_rate = 266666667;
  60 -               break;
  61 -       case SYSTEM_CONFIG_CPUCLK_280:
  62 -               cpu_rate = 280000000;
  63 -               break;
  64 -       case SYSTEM_CONFIG_CPUCLK_300:
  65 -               cpu_rate = 300000000;
  66 -               break;
  67 -       }
  68 -
  69 -       ralink_clk_add("cpu", cpu_rate);
  70 -       ralink_clk_add("300100.timer", cpu_rate / 2);
  71 -       ralink_clk_add("300120.watchdog", cpu_rate / 2);
  72 -       ralink_clk_add("300500.uart", cpu_rate / 2);
  73 -       ralink_clk_add("300900.i2c", cpu_rate / 2);
  74 -       ralink_clk_add("300c00.uartlite", cpu_rate / 2);
  75 -       ralink_clk_add("400000.ethernet", cpu_rate / 2);
  76 -       ralink_clk_add("480000.wmac", wmac_rate);
  77 -}
  78 -
  79  void __init ralink_of_remap(void)
  80  {
  81         rt_sysc_membase = plat_of_remap_node("ralink,rt2880-sysc");